From 2fca87e691d6f6c48db2f8d9f7f18c54d15fdf8a Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Tue, 19 Dec 2023 11:27:24 +0100
Subject: [PATCH 01/27] fixes on sw for interleaved memory

---
 Makefile                                        | 15 +++++++--------
 hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl |  7 ++++---
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/Makefile b/Makefile
index 1e060cc2..29cad677 100644
--- a/Makefile
+++ b/Makefile
@@ -13,22 +13,21 @@ PORT		?= /dev/ttyUSB2
 
 # 1 external domain for the CGRA
 EXTERNAL_DOMAINS = 1
-# Use more memory banks
-MEMORY_BANKS = 4
-
-# Project options are based on the app to be build (default - hello_world)
-PROJECT  ?= hello_world
+PROJECT ?= hello_world
 
+MEMORY_BANKS ?= 2 # Multiple of 2
+MEMORY_BANKS_IL ?= 4 # Power of 2
+  
 export HEEP_DIR = hw/vendor/esl_epfl_x_heep/
 include $(HEEP_DIR)Makefile.venv
 
-
 # Generates mcu files. First the mcu-gen from X-HEEP is called.
 # This is needed to be done after the X-HEEP mcu-gen because the test-bench to be used is the one from CGRA-X-HEEP, not the one from X-HEEP.
+
 mcu-gen:
-	$(MAKE) -f $(XHEEP_MAKE) EXTERNAL_DOMAINS=${EXTERNAL_DOMAINS} MEMORY_BANKS=${MEMORY_BANKS} $(MAKECMDGOALS)
+	$(MAKE) -f $(XHEEP_MAKE) EXTERNAL_DOMAINS=${EXTERNAL_DOMAINS} MEMORY_BANKS=$(MEMORY_BANKS) MEMORY_BANKS_IL=$(MEMORY_BANKS_IL) BUS=NtoM $(MAKECMDGOALS)
 	cd hw/vendor/esl_epfl_x_heep &&\
-	python util/mcu_gen.py --cfg mcu_cfg.hjson --pads_cfg pad_cfg.hjson  --outdir ../../../tb/ --memorybanks $(MEMORY_BANKS) --tpl-sv ../../../tb/tb_util.svh.tpl
+	python util/mcu_gen.py --cfg mcu_cfg.hjson --pads_cfg pad_cfg.hjson --outdir ../../../tb/ --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --bus NtoM --tpl-sv ../../../tb/tb_util.svh.tpl
 
 ## Builds (synthesis and implementation) the bitstream for the FPGA version using Vivado
 ## @param FPGA_BOARD=nexys-a7-100t,pynq-z2
diff --git a/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl b/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
index f05c107b..98f491ce 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
@@ -335,11 +335,12 @@ SECTIONS
    PROVIDE(__freertos_irq_stack_top = .);
   } >ram1
 
-% if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
-  .data_interleaved :
+.data_interleaved :
   {
+    . = ALIGN(4);
+    *(.xheep_data_interleaved)
+    . = ALIGN(4);
   } >ram_il
-% endif
 
   /* Stabs debugging sections.  */
   .stab          0 : { *(.stab) }

From 59cebb87a32b0166bb04dcd2f13998d2fc7fbd2c Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Fri, 15 Mar 2024 07:08:00 +0100
Subject: [PATCH 02/27] revendor x-heep

---
 hw/vendor/eslepfl_x_heep.vendor.hjson | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/vendor/eslepfl_x_heep.vendor.hjson b/hw/vendor/eslepfl_x_heep.vendor.hjson
index 1b336093..2571c6da 100644
--- a/hw/vendor/eslepfl_x_heep.vendor.hjson
+++ b/hw/vendor/eslepfl_x_heep.vendor.hjson
@@ -8,7 +8,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/x-heep.git",
-    rev: "df569a88fc7eaa447645262f0d3a76dd22c519f7",
+    rev: "76d58efe7b9dec0723c1cb9aaf8ad76ad6c85373",
   },
 
   patch_dir: "patches/esl_epfl_x_heep",

From cf060ebb31173fabfb65219621042733367be9fb Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Fri, 15 Mar 2024 07:08:39 +0100
Subject: [PATCH 03/27] Update esl_epfl_x_heep to esl-epfl/x-heep@76d58ef
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Update code from upstream repository https://github.com/esl-
epfl/x-heep.git to revision 76d58efe7b9dec0723c1cb9aaf8ad76ad6c85373

* Update ci (esl-epfl/x-heep#454) (Luigi Giuffrida)
* fix num of FPGAs in README (Davide Schiavone)
* Porting Ultrascale ZCU104 board (esl-epfl/x-heep#435) (jmiranda)
* Add absolute path to `CMakeLists.txt` match statements (esl-
  epfl/x-heep#469) (Michele Caon)
* add SystemC example (esl-epfl/x-heep#443) (Davide Schiavone)
* Structs multireg fix (esl-epfl/x-heep#466) (Stefano Albini)
* add Coremark and update cv32e40p (esl-epfl/x-heep#465) (Davide
  Schiavone)
* add tiled matmul (esl-epfl/x-heep#464) (Davide Schiavone)
* fix software errors/warnings (esl-epfl/x-heep#462) (Davide
  Schiavone)
* add xcelium support (esl-epfl/x-heep#452) (Davide Schiavone)
* Add matmul example (esl-epfl/x-heep#461) (Davide Schiavone)
* fix typo in debug_ss (esl-epfl/x-heep#460) (Luigi Giuffrida)
* update riscv_dbg (esl-epfl/x-heep#230) (Davide Schiavone)
* Fix esl-epfl/x-heep#430 (esl-epfl/x-heep#459) (David Mallasén
  Quintana)
* fix esl-epfl/x-heep#447 (esl-epfl/x-heep#453) (Davide Schiavone)
* fix typo (esl-epfl/x-heep#458) (Luigi Giuffrida)
* add OpenOCD BSCAN configuration file  (esl-epfl/x-heep#457) (Luis
  Waucquez)
* Removed repeated code in dma hal (esl-epfl/x-heep#456) (Juan-n-only)
* Fix linker script generation (esl-epfl/x-heep#451) (Luigi Giuffrida)
* Add a target to the Makefile to directly program the FPGA (esl-
  epfl/x-heep#450) (Luigi Giuffrida)
* [hw/sw] update flash load linker script, data_interleaved and
  data_flash_only sections (esl-epfl/x-heep#399) (Davide Schiavone)
* add simple accelerator example (esl-epfl/x-heep#446) (Davide
  Schiavone)
* change python format for Bootrom (esl-epfl/x-heep#442) (Davide
  Schiavone)
* fix memset bug (esl-epfl/x-heep#439) (Mattia Consani)
* update cv32e40px with dual-read support (esl-epfl/x-heep#441)
  (Davide Schiavone)
* Added X-HEEP Reference. (esl-epfl/x-heep#440) (Simone Machetti)
* add w25q128 flash BSP (esl-epfl/x-heep#433) (Mattia Consani)
* removed FEMU (esl-epfl/x-heep#437) (Simone Machetti)
* update cve2 (esl-epfl/x-heep#284) (Davide Schiavone)
* porting X-HEEP to the nexys FPGA (esl-epfl/x-heep#432) (Davide
  Schiavone)
* Add standard and quad write functionality to flash model (esl-
  epfl/x-heep#426) (Mattia Consani)
* revert :bug: introduced in last revendor of iceprog (davide
  schiavone)
* Add `example_spi_host_quadIO`  (esl-epfl/x-heep#401) (Mattia
  Consani)
* fix minimal cfg with stack and heap size (esl-epfl/x-heep#431)
  (Davide Schiavone)
* Update verible url (esl-epfl/x-heep#428) (David Mallasén Quintana)
* expose DMA slots externally + external FIFO example (esl-
  epfl/x-heep#417) (grinningmosfet)
* Updated the documentation on how to add external interrupts (esl-
  epfl/x-heep#427) (Juan-n-only)
* add citation in readme (Davide Schiavone)
* Fix run-blinky-freertos command (esl-epfl/x-heep#424) (jmiranda)
* Compilation fix (esl-epfl/x-heep#422) (jmiranda)
* add stack and heap size as parameters to mcu-gen (esl-
  epfl/x-heep#419) (Luigi Giuffrida)

Signed-off-by: mbelda <11842513+mbelda@users.noreply.github.com>
---
 hw/vendor/esl_epfl_x_heep/.gitignore          |    6 +-
 hw/vendor/esl_epfl_x_heep/Makefile            |   71 +-
 hw/vendor/esl_epfl_x_heep/README.md           |  167 +-
 .../esl_epfl_x_heep/core-v-mini-mcu.core      |  117 +-
 .../docs/source/How_to/CompileMakefile        |   34 +-
 .../docs/source/How_to/Debug.md               |   82 +-
 .../docs/source/How_to/ExternalDevices.md     |   52 +
 .../docs/source/How_to/ProgramFlash.md        |   18 +-
 .../docs/source/How_to/SystemC.md             |   16 +
 .../ao_peripheral_subsystem.sv                |    9 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv     |   21 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl |   21 +-
 .../hw/core-v-mini-mcu/cpu_subsystem.sv       |   82 +-
 .../hw/core-v-mini-mcu/debug_subsystem.sv     |    7 +-
 ..._epfl_nexys-a7-100t_board_files.lock.hjson |   14 +
 ...pfl_nexys-a7-100t_board_files.vendor.hjson |   17 +
 .../board.xml                                 | 1301 +++++++++++++++
 .../mig.prj                                   |  157 ++
 .../part0_pins.xml                            |  153 ++
 .../preset.xml                                |  398 +++++
 .../esl_epfl_zcu104_board_files.lock.hjson    |   14 +
 .../esl_epfl_zcu104_board_files.vendor.hjson  |   16 +
 .../esl_epfl_zcu104_board_files/board.xml     |  657 ++++++++
 .../part0_pins.xml                            |  228 +++
 .../esl_epfl_zcu104_board_files/preset.xml    |  446 +++++
 .../hw/fpga/constraints/nexys/constraints.xdc |    2 +-
 .../hw/fpga/constraints/nexys/pin_assign.xdc  |  258 +--
 .../fpga/constraints/pynq-z2/constraints.xdc  |    2 +-
 .../fpga/constraints/pynq-z2/pin_assign.xdc   |  135 +-
 .../hw/fpga/constraints/zcu104/pin_assign.xdc |   99 ++
 .../hw/fpga/prim_xilinx_clk.sv                |    9 +
 .../hw/fpga/scripts/nexys/set_board.tcl       |    3 +
 .../nexys/xilinx_generate_clk_wizard.tcl      |   43 +
 .../hw/fpga/scripts/pynq-z2/set_board.tcl     |    3 +
 .../xilinx_generate_clk_wizard.tcl            |    3 -
 .../hw/fpga/scripts/zcu104/set_board.tcl      |    3 +
 .../zcu104/xilinx_generate_clk_wizard.tcl     |   40 +
 .../hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv |   56 +-
 .../esl_epfl_x_heep/hw/ip/boot_rom/README.md  |   28 -
 .../esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.S |    2 +-
 .../hw/ip/boot_rom/boot_rom.dump              |   83 +-
 .../esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.h |   46 +-
 .../hw/ip/boot_rom/boot_rom.sv                |   46 +-
 .../hw/ip/boot_rom/environment.yml            |    6 -
 .../esl_epfl_x_heep/hw/ip/boot_rom/gen_rom.py |    5 +-
 .../esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_core.sv |    4 +-
 .../hw/ip/i2s/rtl/i2s_ws_gen.sv               |    2 +-
 .../hw/ip_examples/iffifo/data/iffifo.hjson   |   76 +
 .../hw/ip_examples/iffifo/iffifo.core         |   26 +
 .../hw/ip_examples/iffifo/iffifo.vlt          |   15 +
 .../hw/ip_examples/iffifo/iffifo_gen.sh       |    8 +
 .../hw/ip_examples/iffifo/rtl/iffifo.sv       |  115 ++
 .../ip_examples/iffifo/rtl/iffifo_reg_pkg.sv  |  106 ++
 .../ip_examples/iffifo/rtl/iffifo_reg_top.sv  |  451 +++++
 .../simple_accelerator.core                   |   22 +
 .../simple_accelerator/simple_accelerator.sv  |  421 +++++
 .../simple_accelerator/simple_accelerator.vlt |   10 +
 .../slow_memory/rtl/slow_memory.sv            |   35 +-
 .../hw/system/x_heep_system.sv.tpl            |    7 +-
 .../hw/vendor/esl_epfl_cv32e40px.core         |    1 +
 .../hw/vendor/esl_epfl_cv32e40px.lock.hjson   |    2 +-
 .../hw/vendor/esl_epfl_cv32e40px.vendor.hjson |    4 +-
 .../bhv/cv32e40px_instr_trace.svh             |   12 +-
 .../esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv  |  275 ++--
 .../bhv/cv32e40px_tb_wrapper.sv               |   30 +-
 .../bhv/include/cv32e40px_tracer_pkg.sv       |   12 +-
 .../esl_epfl_cv32e40px/bhv/insn_trace.sv      |  201 +--
 .../bhv/pipe_freeze_trace.sv                  |   47 +-
 .../rtl/cv32e40px_controller.sv               |   10 +-
 .../esl_epfl_cv32e40px/rtl/cv32e40px_core.sv  |   54 +-
 .../rtl/cv32e40px_cs_registers.sv             |    8 +-
 .../rtl/cv32e40px_ex_stage.sv                 |   76 +-
 .../rtl/cv32e40px_fp_wrapper.sv               |    2 +-
 .../rtl/cv32e40px_id_stage.sv                 |  179 +-
 .../rtl/cv32e40px_register_file_ff.sv         |   66 +-
 .../rtl/cv32e40px_register_file_latch.sv      |   53 +-
 .../rtl/cv32e40px_x_disp.sv                   |  115 +-
 .../rtl/include/cv32e40px_core_v_xif_pkg.sv   |    7 +-
 .../hw/dv/dpi/uartdpi/uartdpi.sv              |    2 +
 .../openhwgroup_cv32e20/.readthedocs.yaml     |   23 +
 .../bhv/cve2_sim_clock_gate.sv                |    2 +-
 .../cv32e20_manifest.flist                    |   63 +
 .../openhwgroup_cv32e20/cve2_configs.yaml     |   94 ++
 .../vendor/openhwgroup_cv32e20/cve2_core.core |  115 ++
 .../openhwgroup_cv32e20/cve2_icache.core      |   22 +
 .../openhwgroup_cv32e20/cve2_multdiv.core     |   28 +
 .../{ibex_pkg.core => cve2_pkg.core}          |    6 +-
 .../vendor/openhwgroup_cv32e20/cve2_top.core  |  115 ++
 .../{cve2.core => cve2_top_tracing.core}      |  111 +-
 .../openhwgroup_cv32e20/cve2_tracer.core      |   20 +
 .../lint/verilator_waiver.vlt                 |   30 +-
 .../rtl/{ibex_alu.sv => cve2_alu.sv}          |    8 +-
 ...anch_predict.sv => cve2_branch_predict.sv} |    4 +-
 ..._decoder.sv => cve2_compressed_decoder.sv} |    4 +-
 ...{ibex_controller.sv => cve2_controller.sv} |  182 +--
 .../openhwgroup_cv32e20/rtl/cve2_core.f       |   17 +
 .../rtl/{ibex_core.sv => cve2_core.sv}        |  475 +-----
 .../rtl/{ibex_counter.sv => cve2_counter.sv}  |    2 +-
 ...x_cs_registers.sv => cve2_cs_registers.sv} |  295 +---
 .../rtl/{ibex_csr.sv => cve2_csr.sv}          |    2 +-
 .../rtl/{ibex_decoder.sv => cve2_decoder.sv}  |   73 +-
 .../{ibex_ex_block.sv => cve2_ex_block.sv}    |   50 +-
 ...{ibex_fetch_fifo.sv => cve2_fetch_fifo.sv} |   32 +-
 .../{ibex_id_stage.sv => cve2_id_stage.sv}    |  475 +-----
 .../openhwgroup_cv32e20/rtl/cve2_if_stage.sv  |  278 ++++
 ..._store_unit.sv => cve2_load_store_unit.sv} |   14 +-
 ...x_multdiv_fast.sv => cve2_multdiv_fast.sv} |   27 +-
 ...x_multdiv_slow.sv => cve2_multdiv_slow.sv} |   15 +-
 .../rtl/{ibex_pkg.sv => cve2_pkg.sv}          |  126 +-
 .../rtl/{ibex_pmp.sv => cve2_pmp.sv}          |   14 +-
 ...default.svh => cve2_pmp_reset_default.svh} |    0
 ...etch_buffer.sv => cve2_prefetch_buffer.sv} |   68 +-
 ...er_file_ff.sv => cve2_register_file_ff.sv} |   34 +-
 .../rtl/cve2_sleep_unit.sv                    |  118 --
 .../openhwgroup_cv32e20/rtl/cve2_top.sv       |  272 ++++
 ...bex_top_tracing.sv => cve2_top_tracing.sv} |   75 +-
 .../rtl/{ibex_tracer.sv => cve2_tracer.sv}    |   14 +-
 ...{ibex_tracer_pkg.sv => cve2_tracer_pkg.sv} |    4 +-
 .../vendor/openhwgroup_cv32e20/rtl/cve2_wb.sv |   69 +
 .../openhwgroup_cv32e20/rtl/ibex_core.f       |   17 -
 .../rtl/ibex_dummy_instr.sv                   |  150 --
 .../openhwgroup_cv32e20/rtl/ibex_icache.sv    | 1165 -------------
 .../openhwgroup_cv32e20/rtl/ibex_if_stage.sv  |  750 ---------
 .../openhwgroup_cv32e20/rtl/ibex_lockstep.sv  |  491 ------
 .../rtl/ibex_register_file_fpga.sv            |   83 -
 .../rtl/ibex_register_file_latch.sv           |  164 --
 .../openhwgroup_cv32e20/rtl/ibex_top.sv       |  978 -----------
 .../openhwgroup_cv32e20/rtl/ibex_wb_stage.sv  |  214 ---
 .../lowrisc_ip/dv/sv/dv_utils/README.md       |    0
 .../dv/sv/dv_utils/dv_fcov_macros.core        |   17 +
 .../dv/sv/dv_utils/dv_fcov_macros.svh         |  112 ++
 .../lowrisc_ip/dv/sv/dv_utils/dv_macros.core  |   17 +
 .../lowrisc_ip/dv/sv/dv_utils/dv_macros.svh   |  536 ++++++
 .../dv/sv/dv_utils/dv_report_catcher.sv       |   46 +
 .../dv/sv/dv_utils/dv_report_server.sv        |   65 +
 .../dv/sv/dv_utils/dv_test_status.core        |   17 +
 .../dv/sv/dv_utils/dv_test_status_pkg.sv      |   31 +
 .../lowrisc_ip/dv/sv/dv_utils/dv_utils.core   |   28 +
 .../lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv |  223 +++
 .../lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv  |   96 ++
 .../hw/vendor/openhwgroup_cv32e40p.core       |    1 +
 .../hw/vendor/openhwgroup_cv32e40p.lock.hjson |    2 +-
 .../vendor/openhwgroup_cv32e40p.vendor.hjson  |    2 +-
 .../hw/vendor/openhwgroup_cv32e40p/.gitignore |    6 +
 .../bhv/cv32e40p_instr_trace.svh              |   12 +-
 .../openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv |  333 ++--
 .../bhv/cv32e40p_tb_wrapper.sv                |   16 +-
 .../bhv/include/cv32e40p_tracer_pkg.sv        |   12 +-
 .../openhwgroup_cv32e40p/bhv/insn_trace.sv    |  205 +--
 .../bhv/pipe_freeze_trace.sv                  |   47 +-
 .../rtl/cv32e40p_controller.sv                |   12 +-
 .../openhwgroup_cv32e40p/rtl/cv32e40p_core.sv |   54 +-
 .../rtl/cv32e40p_cs_registers.sv              |   10 +-
 .../rtl/cv32e40p_ex_stage.sv                  |   67 +-
 .../rtl/cv32e40p_fp_wrapper.sv                |    2 +-
 .../rtl/cv32e40p_id_stage.sv                  |   14 +-
 .../hw/vendor/openhwgroup_cv32e40x.core       |    1 +
 .../hw/vendor/openhwgroup_cve2.lock.hjson     |    4 +-
 .../hw/vendor/openhwgroup_cve2.vendor.hjson   |   29 +-
 .../0001-vendor-cv32e40px-Re-vendor.patch     |   44 -
 .../patches/lowrisc_opentitan/uartdpi.patch   |    8 +-
 .../openhwgroup_cv32e20/cv32e20_assert.patch  |   12 +
 .../openhwgroup_cv32e20/cv32e20_core.patch    |   12 +
 .../clk_mux_glitch_free.patch                 |   13 +
 .../0002-spiflash_valueargs.patch             |   20 -
 .../patches/yosyshq_picorv32/spiflash.patch   |  113 ++
 ....-lowactive-reset.patch => spimemio.patch} |    0
 .../src/clk_mux_glitch_free.sv                |    2 +-
 .../hw/vendor/pulp_platform_fpnew.lock.hjson  |    2 +-
 .../vendor/pulp_platform_fpnew.vendor.hjson   |    2 +-
 .../hw/vendor/pulp_platform_gpio.core         |    2 +
 .../vendor/pulp_platform_riscv_dbg.lock.hjson |    2 +-
 .../pulp_platform_riscv_dbg.vendor.hjson      |    2 +-
 .../pulp_platform_riscv_dbg/CHANGELOG.md      |   35 +-
 .../debug_rom/Makefile                        |    2 +-
 .../debug_rom/debug_rom.S                     |    9 +-
 .../debug_rom/debug_rom.h                     |   24 +-
 .../debug_rom/debug_rom.sv                    |   52 +-
 .../debug_rom/debug_rom_one_scratch.h         |   24 +-
 .../debug_rom/debug_rom_one_scratch.sv        |   44 +-
 .../debug_rom/gen_rom.py                      |   20 +-
 .../doc/debug-system.md                       |   10 +-
 .../pulp_platform_riscv_dbg/src/dm_csrs.sv    |  110 +-
 .../pulp_platform_riscv_dbg/src/dm_mem.sv     |   49 +-
 .../pulp_platform_riscv_dbg/src/dm_pkg.sv     |   12 +-
 .../pulp_platform_riscv_dbg/src/dm_top.sv     |    5 +-
 .../pulp_platform_riscv_dbg/src/dmi_jtag.sv   |   33 +-
 .../src/dmi_jtag_tap.sv                       |   13 +-
 .../pulp_platform_tech_cells_generic.core     |    1 +
 .../hw/vendor/waiver/lint/cv32e40p.vlt        |    1 +
 .../hw/vendor/waiver/lint/cve2.vlt            |    3 +
 .../hw/vendor/waiver/lint/riscv_dbg.vlt       |    1 +
 .../yosyshq_picorv32/picosoc/spiflash.v       |   53 +-
 .../esl_epfl_x_heep/linux_femu/README.md      |  171 --
 .../linux_femu/arm/openocd_cfg/README.md      |   80 -
 .../arm/openocd_cfg/gpio_bitbang.cfg          |   58 -
 .../linux_femu/arm/uart_enable/README.md      |   57 -
 .../arm/uart_enable/uart_enable.dtbo          |  Bin 344 -> 0 bytes
 .../arm/uart_enable/uart_enable.dtsi          |   18 -
 .../linux_femu/arm/uart_enable/uart_enable.sh |    5 -
 .../linux_femu/arm/virtual_flash/Makefile     |    7 -
 .../arm/virtual_flash/OverlayControl.c        |  103 --
 .../arm/virtual_flash/OverlayControl.h        |   27 -
 .../arm/virtual_flash/virtual_flash.cpp       |  100 --
 .../linux_femu/constraints/constraints.xdc    |    1 -
 .../linux_femu/constraints/pin_assign.xdc     |   73 -
 .../esl_epfl_x_heep/linux_femu/pad_cfg.hjson  |  208 ---
 .../linux_femu/rtl/axi_address_hijacker.v     |  331 ----
 .../linux_femu/rtl/linux_femu.sv.tpl          |  533 ------
 .../xilinx_generate_processing_system.tcl     |  118 --
 hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson       |    2 +
 .../esl_epfl_x_heep/mcu_cfg_minimal.hjson     |    2 +
 hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt   |   49 +-
 hw/vendor/esl_epfl_x_heep/sw/Makefile         |    9 +-
 .../sw/applications/coremark/core_list_join.c |  612 +++++++
 .../sw/applications/coremark/core_matrix.c    |  376 +++++
 .../sw/applications/coremark/core_portme.c    |  104 ++
 .../sw/applications/coremark/core_portme.h    |   93 ++
 .../sw/applications/coremark/core_state.c     |  347 ++++
 .../sw/applications/coremark/core_util.c      |  266 +++
 .../sw/applications/coremark/coremark.h       |  211 +++
 .../sw/applications/coremark/main.c           |  459 ++++++
 .../sw/applications/example_dma/main.c        |    4 +-
 .../sw/applications/example_ext_memory/main.c |  128 ++
 .../sw/applications/example_iffifo/main.c     |  206 +++
 .../example_matadd_interleaved/main.c         |   84 +
 .../example_matadd_interleaved/matrixAdd32.h  |   64 +
 .../example_matmul/gen_stimuly.py             |   52 +
 .../sw/applications/example_matmul/main.c     |  126 ++
 .../applications/example_matmul/matrixMul8.h  |   62 +
 .../example_simple_accelerator/main.c         |   85 +
 .../example_spi_flash_write/main.c            |  490 ------
 .../sw/applications/example_spi_host/main.c   |  265 ---
 .../applications/example_spi_host_dma/main.c  |  312 ----
 .../example_spi_host_dma_power_gate/main.c    |    9 +-
 .../sw/applications/example_spi_read/buffer.h |   35 +
 .../sw/applications/example_spi_read/main.c   |  300 ++++
 .../sw/applications/example_spi_write/main.c  |  351 ++++
 .../applications/example_virtual_flash/main.c |  222 ---
 .../sw/applications/minver/arch.cfg           |   67 +
 .../sw/applications/minver/beebsc.c           |  177 ++
 .../sw/applications/minver/beebsc.h           |   65 +
 .../sw/applications/minver/board.c            |   22 +
 .../sw/applications/minver/boardsupport.c     |   21 +
 .../sw/applications/minver/boardsupport.h     |   21 +
 .../sw/applications/minver/chip.c             |   32 +
 .../sw/applications/minver/chipsupport.c      |   73 +
 .../sw/applications/minver/chipsupport.h      |   25 +
 .../sw/applications/minver/libminver.c        |  292 ++++
 .../sw/applications/minver/main.c             |   50 +
 .../sw/applications/minver/support.h          |   72 +
 .../esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c | 1449 +++++++++++++++++
 .../sw/device/bsp/w25q/w25q128jw.h            |  433 +++++
 .../esl_epfl_x_heep/sw/device/lib/crt/crt0.S  |  208 +--
 .../sw/device/lib/drivers/dma/dma.c           |   38 +-
 .../sw/device/lib/drivers/dma/dma.h           |    4 +-
 .../sw/device/lib/drivers/gpio/gpio.c         |    4 +-
 .../sw/device/lib/drivers/iffifo/iffifo.h     |   56 +
 .../device/lib/drivers/iffifo/iffifo_regs.h   |   47 +
 .../sw/device/lib/drivers/rv_plic/rv_plic.c   |    2 +-
 .../sw/device/lib/drivers/spi_host/spi_host.h |    9 +
 .../sw/device/lib/runtime/core_v_mini_mcu.c   |   37 +
 .../device/lib/runtime/core_v_mini_mcu.h.tpl  |    4 +
 .../sw/device/lib/runtime/handler.c           |    2 +-
 .../sw/device/lib/runtime/syscalls.c          |   36 +-
 .../sw/device/target/nexys-a7-100t/x-heep.h   |   30 +
 .../sw/device/target/systemc/x-heep.h         |   30 +
 .../sw/device/target/zcu104/x-heep.h          |   28 +
 .../esl_epfl_x_heep/sw/linker/link.ld.tpl     |   55 +-
 .../sw/linker/link_flash_exec.ld.tpl          |    6 +-
 .../sw/linker/link_flash_load.ld.tpl          |   99 +-
 ...er-iceprog-custom-for-heep-with-gpio.patch |  136 +-
 .../vendor/yosyshq_icestorm/iceprog/iceprog.c |   64 +-
 .../tb/XHEEP_CmdLineOptions.cpp               |  100 ++
 .../tb/XHEEP_CmdLineOptions.hh                |   24 +
 .../tb/core-v-mini-mcu-pynq-z2-bscan.cfg      |   44 +
 .../esl_epfl_x_heep/tb/systemc_tb/Cache.h     |  221 +++
 .../tb/systemc_tb/MainMemory.h                |   68 +
 .../tb/systemc_tb/MemoryRequest.h             |  241 +++
 hw/vendor/esl_epfl_x_heep/tb/tb_sc_top.cpp    |  342 ++++
 hw/vendor/esl_epfl_x_heep/tb/tb_top.cpp       |   81 +-
 hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl  |    2 +-
 hw/vendor/esl_epfl_x_heep/tb/testharness.sv   |   98 +-
 .../esl_epfl_x_heep/tb/testharness_pkg.sv     |   27 +-
 hw/vendor/esl_epfl_x_heep/util/mcu_gen.py     |   27 +
 hw/vendor/esl_epfl_x_heep/util/structs_gen.py |    3 +-
 .../esl_epfl_x_heep/x-heep-tb-utils.core      |   13 +
 hw/vendor/eslepfl_x_heep.lock.hjson           |    2 +-
 288 files changed, 18886 insertions(+), 10886 deletions(-)
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/How_to/SystemC.md
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.lock.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.vendor.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/board.xml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/mig.prj
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/part0_pins.xml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/preset.xml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.lock.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.vendor.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/board.xml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/part0_pins.xml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/preset.xml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl
 rename hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/{ => pynq-z2}/xilinx_generate_clk_wizard.tcl (86%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/environment.yml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/data/iffifo.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.vlt
 create mode 100755 hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo_gen.sh
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.vlt
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/.readthedocs.yaml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cv32e20_manifest.flist
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_configs.yaml
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_core.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_icache.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_multdiv.core
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/{ibex_pkg.core => cve2_pkg.core} (73%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_top.core
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/{cve2.core => cve2_top_tracing.core} (52%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_tracer.core
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_alu.sv => cve2_alu.sv} (99%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_branch_predict.sv => cve2_branch_predict.sv} (98%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_compressed_decoder.sv => cve2_compressed_decoder.sv} (99%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_controller.sv => cve2_controller.sv} (82%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.f
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_core.sv => cve2_core.sv} (73%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_counter.sv => cve2_counter.sv} (99%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_cs_registers.sv => cve2_cs_registers.sv} (86%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_csr.sv => cve2_csr.sv} (98%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_decoder.sv => cve2_decoder.sv} (94%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_ex_block.sv => cve2_ex_block.sv} (80%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_fetch_fifo.sv => cve2_fetch_fifo.sv} (92%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_id_stage.sv => cve2_id_stage.sv} (60%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_if_stage.sv
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_load_store_unit.sv => cve2_load_store_unit.sv} (96%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_multdiv_fast.sv => cve2_multdiv_fast.sv} (96%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_multdiv_slow.sv => cve2_multdiv_slow.sv} (96%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_pkg.sv => cve2_pkg.sv} (74%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_pmp.sv => cve2_pmp.sv} (95%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_pmp_reset_default.svh => cve2_pmp_reset_default.svh} (100%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_prefetch_buffer.sv => cve2_prefetch_buffer.sv} (81%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_register_file_ff.sv => cve2_register_file_ff.sv} (66%)
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_sleep_unit.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top.sv
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_top_tracing.sv => cve2_top_tracing.sv} (66%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_tracer.sv => cve2_tracer.sv} (98%)
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/{ibex_tracer_pkg.sv => cve2_tracer_pkg.sv} (99%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_wb.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_core.f
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_dummy_instr.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_icache.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_if_stage.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_lockstep.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_fpga.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_latch.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_top.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_wb_stage.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/README.md
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/patches/esl_epfl_cv32e40px/0001-vendor-cv32e40px-Re-vendor.patch
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_assert.patch
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_core.patch
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_common_cells/clk_mux_glitch_free.patch
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/0002-spiflash_valueargs.patch
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/spiflash.patch
 rename hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/{0001-async.-lowactive-reset.patch => spimemio.patch} (100%)
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/README.md
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/README.md
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/gpio_bitbang.cfg
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/README.md
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.dtbo
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.dtsi
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.sh
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/Makefile
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.c
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.h
 delete mode 100755 hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/virtual_flash.cpp
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/constraints/constraints.xdc
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/constraints/pin_assign.xdc
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/pad_cfg.hjson
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/rtl/axi_address_hijacker.v
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/rtl/linux_femu.sv.tpl
 delete mode 100644 hw/vendor/esl_epfl_x_heep/linux_femu/scripts/xilinx_generate_processing_system.tcl
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_list_join.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_matrix.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_state.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_util.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/coremark/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_ext_memory/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/matrixAdd32.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/gen_stimuly.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/matrixMul8.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_flash_write/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/buffer.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_virtual_flash/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/arch.cfg
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/board.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/chip.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/libminver.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/minver/support.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo_regs.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/target/systemc/x-heep.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.cpp
 create mode 100644 hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.hh
 create mode 100644 hw/vendor/esl_epfl_x_heep/tb/core-v-mini-mcu-pynq-z2-bscan.cfg
 create mode 100644 hw/vendor/esl_epfl_x_heep/tb/systemc_tb/Cache.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MainMemory.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MemoryRequest.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/tb/tb_sc_top.cpp

diff --git a/hw/vendor/esl_epfl_x_heep/.gitignore b/hw/vendor/esl_epfl_x_heep/.gitignore
index a9a6e8c0..f2b85af8 100644
--- a/hw/vendor/esl_epfl_x_heep/.gitignore
+++ b/hw/vendor/esl_epfl_x_heep/.gitignore
@@ -7,16 +7,12 @@ build/
 *.dis
 *.map
 *.do
-.venv/*
+.venv/
 util/__pycache__/*
 
 # ignore apps output file
 run_verif_rtl_log.txt
 
-#ignore femu generated hw
-linux_femu/rtl/linux_femu.sv
-.venv/
-
 # ignore the following hw automatically generated files
 environment.yml
 core-v-mini-mcu.upf
diff --git a/hw/vendor/esl_epfl_x_heep/Makefile b/hw/vendor/esl_epfl_x_heep/Makefile
index fa6e81ef..2d67386a 100644
--- a/hw/vendor/esl_epfl_x_heep/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/Makefile
@@ -6,6 +6,7 @@ MAKE                       = make
 
 # Get the absolute path
 mkfile_path := $(shell dirname "$(realpath $(firstword $(MAKEFILE_LIST)))")
+$(info $$You are executing from: $(mkfile_path))
 
 # Include the self-documenting tool
 FILE=$(mkfile_path)/Makefile
@@ -33,7 +34,7 @@ PROJECT  ?= hello_world
 # Linker options are 'on_chip' (default),'flash_load','flash_exec','freertos'
 LINKER   ?= on_chip
 
-# Target options are 'sim' (default) and 'pynq-z2'
+# Target options are 'sim' (default) and 'pynq-z2' and 'nexys-a7-100t'
 TARGET   	?= sim
 MCU_CFG  	?= mcu_cfg.hjson
 PAD_CFG  	?= pad_cfg.hjson
@@ -49,7 +50,7 @@ COMPILER_PREFIX ?= riscv32-unknown-
 ARCH     ?= rv32imc
 
 # Path relative from the location of sw/Makefile from which to fetch source files. The directory of that file is the default value.
-SOURCE 	 ?= "."
+SOURCE 	 ?= $(".")
 
 # Simulation engines options are verilator (default) and questasim
 SIMULATOR ?= verilator
@@ -57,6 +58,31 @@ SIMULATOR ?= verilator
 # Timeout for simulation, default 120
 TIMEOUT ?= 120
 
+# Flash read address for testing, in hexadecimal format 0x0000
+FLASHREAD_ADDR ?= 0x0
+FLASHREAD_FILE ?= $(mkfile_path)/flashcontent.hex
+FLASHREAD_BYTES ?= 256
+
+#max address in the hex file, used to program the flash
+ifeq ($(wildcard sw/build/main.hex),)
+	MAX_HEX_ADDRESS  = 0
+	MAX_HEX_ADDRESS_DEC = 0
+	BYTES_AFTER_MAX_HEX_ADDRESS = 0
+	FLASHRWITE_BYTES = 0
+else
+	MAX_HEX_ADDRESS  = $(shell cat sw/build/main.hex | grep "@" | tail -1 | cut -c2-)
+	MAX_HEX_ADDRESS_DEC = $(shell printf "%d" 0x$(MAX_HEX_ADDRESS))
+	BYTES_AFTER_MAX_HEX_ADDRESS = $(shell tac sw/build/main.hex | awk 'BEGIN {count=0} /@/ {print count; exit} {count++}')
+	FLASHRWITE_BYTES = $(shell echo $(MAX_HEX_ADDRESS_DEC) + $(BYTES_AFTER_MAX_HEX_ADDRESS)*16 | bc)
+endif
+
+
+#binary to store in flash memory
+FLASHWRITE_FILE = $(mkfile_path)/sw/build/main.hex
+
+# Export variables to sub-makefiles
+export
+
 ## @section Conda
 conda: environment.yml
 	conda env create -f environment.yml
@@ -64,13 +90,6 @@ conda: environment.yml
 environment.yml: python-requirements.txt
 	util/python-requirements2conda.sh
 
-## @section Linux-Emulation
-
-## Generates FEMU
-linux-femu-gen: mcu-gen
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir linux_femu/rtl/ --tpl-sv linux_femu/rtl/linux_femu.sv.tpl
-	$(MAKE) verible
-
 ## @section Installation
 
 ## Generates mcu files core-v-mini-mcu files and build the design with fusesoc
@@ -115,7 +134,7 @@ verible:
 
 ## Generates the build folder in sw using CMake to build (compile and linking)
 ## @param PROJECT=<folder_name_of_the_project_to_be_built>
-## @param TARGET=sim(default),pynq-z2
+## @param TARGET=sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104
 ## @param LINKER=on_chip(default),flash_load,flash_exec
 ## @param COMPILER=gcc(default), clang
 ## @param COMPILER_PREFIX=riscv32-unknown-(default)
@@ -134,10 +153,14 @@ app-compile-all:
 
 ## @section Simulation
 
-## Verilator simulation
+## Verilator simulation with C++
 verilator-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
+## Verilator simulation with SystemC
+verilator-sim-sc:
+	$(FUSESOC) --cores-root . run --no-export --target=sim_sc --tool=verilator $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
+
 ## Questasim simulation
 questasim-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
@@ -161,6 +184,10 @@ vcs-sim:
 vcs-ams-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --flag "ams_sim" --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
+## xcelium simulation
+xcelium-sim:
+	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=xcelium $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
+
 ## Generates the build output for helloworld application
 ## Uses verilator to simulate the HW model and run the FW
 ## UART Dumping in uart0.log to show recollected results
@@ -175,7 +202,7 @@ run-helloworld: mcu-gen verilator-sim
 ## Uses verilator to simulate the HW model and run the FW
 ## UART Dumping in uart0.log to show recollected results
 run-blinkyfreertos: mcu-gen verilator-sim
-	$(MAKE) -C sw PROJECT=blinky_freertos TARGET=$(TARGET) LINKER=$(LINKER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH);
+	$(MAKE) -C sw PROJECT=example_freertos_blinky TARGET=$(TARGET) LINKER=$(LINKER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH);
 	cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator; \
 	./Vtestharness +firmware=../../../sw/build/main.hex; \
 	cat uart0.log; \
@@ -196,7 +223,7 @@ app-simulate-all:
 ## @section Vivado
 
 ## Builds (synthesis and implementation) the bitstream for the FPGA version using Vivado
-## @param FPGA_BOARD=nexys-a7-100t,pynq-z2
+## @param FPGA_BOARD=nexys-a7-100t,pynq-z2,zcu104
 ## @param FUSESOC_FLAGS=--flag=<flagname>
 vivado-fpga:
 	$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildvivado.log
@@ -204,6 +231,9 @@ vivado-fpga:
 vivado-fpga-nobuild:
 	$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildvivado.log
 
+vivado-fpga-pgm:
+	$(MAKE) -C build/openhwgroup.org_systems_core-v-mini-mcu_0/$(FPGA_BOARD)-vivado pgm
+
 ## @section ASIC
 ## Note that for this step you need to provide technology-dependent files (e.g., libs, constraints)
 asic:
@@ -220,18 +250,27 @@ openroad-sky130:
 
 ## Read the id from the EPFL_Programmer flash
 flash-readid:
-	cd sw/vendor/yosyshq_icestorm/iceprog; \
+	cd sw/vendor/yosyshq_icestorm/iceprog; make; \
 	./iceprog -d i:0x0403:0x6011 -I B -t;
 
 ## Loads the obtained binary to the EPFL_Programmer flash
 flash-prog:
-	cd sw/vendor/yosyshq_icestorm/iceprog; \
-	./iceprog -d i:0x0403:0x6011 -I B $(mkfile_path)/sw/build/main.hex;
+	cd sw/vendor/yosyshq_icestorm/iceprog; make; \
+	./iceprog -a $(FLASHRWITE_BYTES) -d i:0x0403:0x6011 -I B $(FLASHWRITE_FILE);
+
+## Read the EPFL_Programmer flash
+flash-read:
+	cd sw/vendor/yosyshq_icestorm/iceprog; make; \
+	./iceprog -d i:0x0403:0x6011 -I B -o $(shell printf "%d" $(FLASHREAD_ADDR)) -R $(FLASHREAD_BYTES) $(FLASHREAD_FILE);
 
 ## Run openOCD w/ EPFL_Programmer
 openOCD_epflp:
 	xterm -e openocd -f ./tb/core-v-mini-mcu-pynq-z2-esl-programmer.cfg;
 
+## Run openOCD w/ BSCAN of the Pynq-Z2 board
+openOCD_bscan:
+	xterm -e openocd -f ./tb/core-v-mini-mcu-pynq-z2-bscan.cfg;
+
 ## Start GDB
 gdb_connect:
 	$(MAKE) -C sw gdb_connect
diff --git a/hw/vendor/esl_epfl_x_heep/README.md b/hw/vendor/esl_epfl_x_heep/README.md
index 0e0130b7..c9705474 100644
--- a/hw/vendor/esl_epfl_x_heep/README.md
+++ b/hw/vendor/esl_epfl_x_heep/README.md
@@ -39,6 +39,21 @@ The block diagram below shows the `X-HEEP` MCU
 
 <p align="center"><img src="block_diagrams/core_v_mini_mcu.svg" width="650"></p>
 
+# Reference
+
+If you use X-HEEP in your academic work you can cite us: [X-HEEP Paper](https://arxiv.org/abs/2401.05548)
+
+```
+@misc{machetti2024xheep,
+      title={X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators},
+      author={Simone Machetti and Pasquale Davide Schiavone and Thomas Christoph Müller and Miguel Peón-Quirós and David Atienza},
+      year={2024},
+      eprint={2401.05548},
+      archivePrefix={arXiv},
+      primaryClass={cs.AR}
+}
+```
+
 # Self-documented Makefile
 
 Note that under `util` folder, the file `generate-makefile-help` is employed to generate a self-documented helping output. In case of including any other target or command under the main `Makefile`, follow the same general and parameter descriptions as already provided for every target. Check the `help` output by doing `make` or `make help`. Moreover, **note that some of the parameters required for some of the targets are initiated with _default values_**
@@ -59,7 +74,6 @@ It has been tested only on `Ubuntu 20`, and we know it does NOT WORK on `Ubuntu
 
 ## 2. Python
 
-
 We rely on either (a) `miniconda`, or (b) `virtual environment` enviroment.
 
 Choose between `2.a` or `2.b` to setup your enviroment.
@@ -79,7 +93,6 @@ You need to do it only the first time, then just activate the environment everyt
 conda activate core-v-mini-mcu
 ```
 
-
 ### 2.b Virtual Environment
 
 Install the python virtual environment just as:
@@ -153,13 +166,36 @@ sudo apt-get install -y gtkwave
 
 We use version v0.0-1824-ga3b5bedf
 
-See: [Install Verible](https://opentitan.org/guides/getting_started/index.html#step-6a-install-verible-optional)
+See: [Install Verible](https://opentitan.org/guides/getting_started/index.html#step-7a-install-verible-optional)
 
 To format your RTL code type:
 
 ```
 make verible
 ```
+
+## Docker alternative
+
+A docker image containing all the required software dependancies is available on [github-packages](https://github.com/orgs/esl-epfl/packages/container/package/x-heep-toolchain).
+
+It is only required to install [`docker`](https://docs.docker.com/get-docker/) and pull the image.
+
+```bash
+docker pull ghcr.io/esl-epfl/x-heep-toolchain:latest
+```
+
+Assuming that X-HEEP has been cloned to `X-HEEP-DIR=\absolute\path\to\x-HEEP\folder`, it is possible to directly run the docker mounting `X-HEEP-DIR` to the path `\workspace\x-heep` in the docker.
+
+```bash
+docker run -it -v ${X-HEEP-DIR}:/workspace/x-heep ghcr.io/esl-epfl/x-heep-toolchain
+```
+
+Take care to indicate the absolute path to the local clone of X-HEEP, otherwise `docker` will not be able to properly nount the local folder in the container.
+
+All the command listed in the README can be execute in the docker container, except for:
+- Simulation with Questasim and VCS, synthesis with Design Compiler (licenses are required to use these tools, so they are not installed in the container)
+- OpenRoad flow is not installed in the container, so it is not possible to run the related make commands
+
 ## Compilation Flow and Package Manager
 
 We use [FuseSoC](https://github.com/olofk/fusesoc) for all the tools we use.
@@ -168,7 +204,7 @@ The `fusesoc` commands are inside the Makefile.
 
 # Adding external IPs
 
-This repository relies on [Vendor](https://opentitan.org/book/util/doc/vendor.html) to add new IPs. The `vendor.py` script in the [`./util`](./util/) folder implements what is describeb above, while [this](./ExternalDevices.md) file contains additional information on how to connect external devices to the system.
+This repository relies on [Vendor](https://opentitan.org/book/util/doc/vendor.html) to add new IPs. The `vendor.py` script in the [`./util`](./util/) folder implements what is described above, while [this](./docs/source/How_to/ExternalDevices.md) file contains additional information on how to connect external devices to the system.
 
 # Compiling with Makefile
 
@@ -206,7 +242,6 @@ make mcu-gen MCU_CFG=mcu_cfg_minimal.hjson
 
 The `minimal` configuration is a work-in-progress, thus not all the APPs have been tested.
 
-
 ## Compiling Software
 
 Don't forget to set the `RISCV` env variable to the compiler folder (without the `/bin` included).
@@ -219,11 +254,11 @@ make app
 To run any other application, please use the following command with appropiate parameters:
 
 ```
-app PROJECT=<folder_name_of_the_project_to_be_built> TARGET=sim(default),pynq-z2 LINKER=on_chip(default),flash_load,flash_exec COMPILER=gcc(default),clang COMPILER_PREFIX=riscv32-unknown-(default) ARCH=rv32imc(default),<any RISC-V ISA string supported by the CPU>
+app PROJECT=<folder_name_of_the_project_to_be_built> TARGET=sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104 LINKER=on_chip(default),flash_load,flash_exec COMPILER=gcc(default),clang COMPILER_PREFIX=riscv32-unknown-(default) ARCH=rv32imc(default),<any RISC-V ISA string supported by the CPU>
 
 Params:
 - PROJECT (ex: <folder_name_of_the_project_to_be_built>, hello_world(default))
-- TARGET (ex: sim(default),pynq-z2)
+- TARGET (ex: sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104)
 - LINKER (ex: on_chip(default),flash_load,flash_exec)
 - COMPILER (ex: gcc(default),clang)
 - COMPILER_PREFIX (ex: riscv32-unknown-(default))
@@ -238,9 +273,8 @@ make app TARGET=pynq-z2
 
 Or, if you use the OpenHW Group [GCC](https://www.embecosm.com/resources/tool-chain-downloads/#corev) compiler with CORE_PULP extensions, make sure to point the `RISCV` env variable to the OpenHW Group compiler, then just run:
 
-
 ```
-make app COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_xcvhwlp1p0_xcvmem1p0_xcvmac1p0_xcvbi1p0_xcvalu1p0_xcvsimd1p0_xcvbitmanip1p0
+make app COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_xcvhwlp_xcvmem_xcvmac_xcvbi_xcvalu_xcvsimd_xcvbitmanip
 ```
 
 This will create the executable file to be loaded into your target system (ASIC, FPGA, Simulation).
@@ -264,13 +298,13 @@ Moreover, FreeRTOS is being fetch from 'https://github.com/FreeRTOS/FreeRTOS-Ker
 
 ## Simulating
 
-This project supports simulation with Verilator, Synopsys VCS, and Siemens Questasim.
+This project supports simulation with Verilator, Synopsys VCS, Siemens Questasim and Cadence Xcelium.
 It relies on `fusesoc` to handle multiple EDA tools and parameters.
 For example, if you want to set the `FPU` and `COREV_PULP` parameters of the `cv32e40p` CPU,
 you need to add next to your compilation command `FUSESOC_PARAM="--COREV_PULP=1 --FPU=1"`
 Below the different EDA examples commands.
 
-### Compiling for Verilator
+### Compiling for Verilator (C++ testbench)
 
 To simulate your application with Verilator, first compile the HDL:
 
@@ -296,6 +330,38 @@ or to execute all these three steps type:
 make run-helloworld
 ```
 
+### Compiling for Verilator (SystemC testbench)
+
+To simulate your application with Verilator using `SystemC`,
+
+make sure you have `SystemC 2.3.3` installed, if not, find it [here](https://www.accellera.org/downloads/standards/systemc).
+
+Make sure to have the following env variables set:
+
+```
+export SYSTEMC_INCLUDE=/your_path_to_systemc/systemc/include/
+export SYSTEMC_LIBDIR=/your_path_to_systemc/systemc/lib-linux64/
+```
+
+Compile the HDL:
+
+```
+make verilator-sim-sc
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim_sc-verilator
+```
+
+and type to run your compiled software:
+
+```
+./Vtestharness +firmware=../../../sw/build/main.hex
+```
+
+If you want to know what is special about the SystemC testbench, have a look [here](./docs/source/How_to/SystemC.md)
 
 ### Compiling for VCS
 
@@ -337,7 +403,7 @@ cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-vcs
 
 and running the same executable as for the digital simulation. Note that with Verdi you can view both the digital and the analog waveforms.
 
-Additional instructions on how to run an analog / mixed-signal simulation of X-HEEP can be found [here](AnalogMixedSignal.md). To try out the simulation, we provide an example SPICE netlist of an simple 1-bit ADC created by us and exported from [xschem](https://xschem.sourceforge.io/stefan/index.html) and which uses the PTM 65nm bulk CMOS model from [https://ptm.asu.edu](https://ptm.asu.edu/).
+Additional instructions on how to run an analog / mixed-signal simulation of X-HEEP can be found [here](./docs/source/How_to/AnalogMixedSignal.md). To try out the simulation, we provide an example SPICE netlist of an simple 1-bit ADC created by us and exported from [xschem](https://xschem.sourceforge.io/stefan/index.html) and which uses the PTM 65nm bulk CMOS model from [https://ptm.asu.edu](https://ptm.asu.edu/).
 
 ### Compiling for Questasim
 
@@ -390,6 +456,26 @@ make run RUN_OPT=1 RUN_UPF=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
 
 Questasim version must be >= Questasim 2020.4
 
+### Compiling for Xcelium
+
+To simulate your application with Xcelium, first compile the HDL:
+
+```
+make xcelium-sim
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-xcelium/
+```
+
+and type to run your compiled software:
+
+```
+make run PLUSARGS="c firmware=../../../sw/build/main.hex"
+```
+
 ### UART DPI
 
 To simulate the UART, we use the LowRISC OpenTitan [UART DPI](https://github.com/lowRISC/opentitan/tree/master/hw/dv/dpi/uartdpi).
@@ -427,7 +513,6 @@ The available parameters are:
 * LINKER: `on_chip`(default), `flash_load` or `flash_exec` (can provide more than one)
 * TIMEOUT: Integer number of seconds (default 120)
 
-
 #### Usage
 
 ##### Comands
@@ -440,7 +525,7 @@ make app-simulate-all
 ```
 Note that both commands allow the previous parameters to specify compiling or simulation options. E.g.:
 ```
-make app-simulate-all LINKER=on_chip SIMULATOR=questasim COMPILER=clang TIMEOUT=150 
+make app-simulate-all LINKER=on_chip SIMULATOR=questasim COMPILER=clang TIMEOUT=150
 ```
 
 ##### Manually
@@ -467,25 +552,27 @@ The success of the script is not required for merging of a PR.
 
 ## Debug
 
-Follow the [Debug](./Debug.md) guide to debug core-v-mini-mcu.
+Follow the [Debug](./docs/source/How_to/Debug.md) guide to debug core-v-mini-mcu.
 
 Alternatively, in case you are used to developing using Integrated Development Environments (IDEs), please check [the IDE readme](./IDEs.md).
 
 ## Execute From Flash
 
-Follow the [ExecuteFromFlash](./ExecuteFromFlash.md) guide to exxecute code directly from the FLASH with modelsim, FPGA, or ASIC.
+Follow the [ExecuteFromFlash](./docs/source/How_to/ExecuteFromFlash.md) guide to exxecute code directly from the FLASH with modelsim, FPGA, or ASIC.
 
 ## Emulation on Xilinx FPGAs
 
-This project offers two different X-HEEP implementetions on the Xilinx FPGAs, called Standalone-FEMU and Linux-FEMU.
+This project offers two different X-HEEP implementetions on Xilinx FPGAs, called Standalone and FEMU.
 
-### Standalone-FEMU (Standalone Fpga EMUlation)
+### Standalone
 
 In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the FPGA, and its input/output are connected to the available headers on the FPGA board.
 
+Three FPGA boards are supported: the Xilinx Pynq-z2, Nexys-A7-100t, Zynq Ultrascale+ ZCU104.
+
 Make sure you have the FPGA board files installed in your Vivado.
 
-For example, for the Xilinx Pynq-Z2 board, use the documentation provided at the following [link](https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html) to download and install them:
+For example, for the Pynq-Z2 board, use the documentation provided at the following [link](https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html) to download and install them:
 
 To build and program the bitstream for your FPGA with vivado, type:
 
@@ -493,6 +580,18 @@ To build and program the bitstream for your FPGA with vivado, type:
 make vivado-fpga FPGA_BOARD=pynq-z2
 ```
 
+or
+
+```
+make vivado-fpga FPGA_BOARD=nexys-a7-100t
+```
+
+or
+
+```
+make vivado-fpga FPGA_BOARD=zcu104
+```
+
 or add the flag `use_bscane_xilinx` to use the native Xilinx scanchain:
 
 ```
@@ -507,11 +606,23 @@ To program the bitstream, open Vivado,
 open --> Hardware Manager --> Open Target --> Autoconnect --> Program Device
 ```
 
-and choose the file `openhwgroup.org_systems_core-v-mini-mcu_0.bit`
+and choose the file `openhwgroup.org_systems_core-v-mini-mcu_0.bit`.
 
-To run SW, follow the [Debug](./Debug.md) guide
+Or simply type:
+
+```
+bash vivado-fpga-pgm FPGA_BOARD=pynq-z2
+```
+
+or
+
+```
+make vivado-fpga-pgm FPGA_BOARD=nexys-a7-100t
+```
+
+To run SW, follow the [Debug](./docs/source/How_to/Debug.md) guide
 to load the binaries with the HS2 cable over JTAG,
-or follow the [ExecuteFromFlash](./ExecuteFromFlash.md)
+or follow the [ExecuteFromFlash](./docs/source/How_to/ExecuteFromFlash.md)
 guide if you have a FLASH attached to the FPGA.
 
 Do not forget that the `pynq-z2` board requires you to have the ethernet cable attached to the board while running.
@@ -520,7 +631,7 @@ For example, if you want to run your application using flash_exec, do as follow:
 
 compile your application, e.g. `make app PROJECT=example_matfadd TARGET=pynq-z2 ARCH=rv32imfc LINKER=flash_exec`
 
-and then follow the [ExecuteFromFlash](./ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly.
+and then follow the [ExecuteFromFlash](./docs/source/How_to/ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly.
 
 To look at the output of your printf, run in another terminal:
 
@@ -528,13 +639,11 @@ To look at the output of your printf, run in another terminal:
 
 Please be sure to use the right `ttyUSB` number (you can discover it with `dmesg --time-format iso | grep FTDI` for example).
 
+### FPGA EMUlation Platform (FEMU)
 
-### Linux-FEMU (Linux Fpga EMUlation)
-
-In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the FPGA and Linux is run on the ARM-based processing system (PS) side of the same chip.
-
-Read the [following](./linux_femu/README.md) documentation to have more information about this implementation.
+In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the Xilinx Zynq-7020 chip on the Pynq-Z2 board and Linux is run on the ARM-based processing system (PS) side of the same chip.
 
+NOTE: This platform is not part of this repository, but you can access it with the following link: [FEMU](https://github.com/esl-epfl/x-heep-femu-sdk).
 
 # ASIC Implementation
 
@@ -555,6 +664,6 @@ make asic
 ## OpenRoad support for SkyWater 130nm
 
 We are working on supporting OpenRoad and SkyWater 130nm PDK, please refer to the
-[OpenRoadFlow](./OpenRoadFlow.md) page. This is not ready yet, it has not been tested.
+[Implement on ASIC](./docs/source/How_to/ImplementASIC.md) page. This is not ready yet, it has not been tested.
 
 This relies on a fork of [edalize](https://github.com/davideschiavone/edalize) that contains templates for Design Compiler and OpenRoad.
diff --git a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core
index 7bebad44..dd439888 100644
--- a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core
+++ b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core
@@ -13,7 +13,7 @@ filesets:
     - x-heep::packages
     - openhwgroup.org:ip:cv32e40p
     - openhwgroup.org:ip:cv32e40x
-    - openhwgroup.org:ip:cve2
+    - openhwgroup:cve2:cve2_top
     - esl_epfl:ip:cv32e40px
     - pulp-platform.org:ip:gpio
     - pulp-platform.org::common_cells
@@ -102,7 +102,6 @@ filesets:
 
   ip-fpga:
     files:
-    - hw/fpga/scripts/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
     - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
     - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource }
     - hw/fpga/cv32e40p_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
@@ -115,15 +114,20 @@ filesets:
     - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
     - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }
 
-  fpga-arm-emulation:
-    depend:
-    - pulp-platform.org::axi_spi_slave
+  ip-fpga-pynq-z2:
+    files:
+    - hw/fpga/scripts/pynq-z2/set_board.tcl: { file_type: tclSource }
+    - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+
+  ip-fpga-nexys:
     files:
-    - linux_femu/scripts/xilinx_generate_processing_system.tcl: {file_type: tclSource}
-    - linux_femu/rtl/axi_address_hijacker.v: {file_type: verilogSource}
-    - linux_femu/rtl/linux_femu.sv: {file_type: systemVerilogSource}
-    - linux_femu/constraints/pin_assign.xdc: {file_type: xdc}
-    - linux_femu/constraints/constraints.xdc: {file_type: xdc}
+    - hw/fpga/scripts/nexys/set_board.tcl: { file_type: tclSource }
+    - hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+
+  ip-fpga-zcu104:
+    files:
+    - hw/fpga/scripts/zcu104/set_board.tcl: { file_type: tclSource }
+    - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
 
   ip-asic:
     depend:
@@ -155,6 +159,11 @@ filesets:
     - hw/fpga/constraints/pynq-z2/constraints.xdc
     file_type: xdc
 
+  xdc-fpga-zcu104:
+    files:
+    - hw/fpga/constraints/zcu104/pin_assign.xdc
+    file_type: xdc
+
   netlist-fpga:
     files:
     - build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
@@ -194,6 +203,8 @@ filesets:
 
   tb-verilator:
     files:
+    - tb/XHEEP_CmdLineOptions.hh: { is_include_file: true }
+    - tb/XHEEP_CmdLineOptions.cpp
     - tb/tb_top.cpp
     file_type: cppSource
 
@@ -202,6 +213,14 @@ filesets:
     - tb/tb_top.sv
     file_type: systemVerilogSource
 
+  tb-sc-verilator:
+    files:
+    - tb/XHEEP_CmdLineOptions.hh: { is_include_file: true }
+    - tb/XHEEP_CmdLineOptions.cpp
+    - tb/tb_sc_top.cpp
+    file_type: cppSource
+
+
   openroad_base_files:
     files:
       - flow/OpenROAD-flow-scripts/flow/Makefile : {file_type: Makefile}
@@ -262,7 +281,15 @@ parameters:
     datatype: bool
     paramtype: vlogdefine
     default: false
-  FPGA_NETLIST:
+  SIM_SYSTEMC:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_NEXYS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_ZCU104:
     datatype: bool
     paramtype: vlogdefine
     default: false
@@ -302,6 +329,8 @@ targets:
     - files_rtl_generic
     - target_sim ? (rtl-simulation)
     - target_sim ? (tool_verilator? (files_verilator_waiver))
+    - target_sim_sc ? (rtl-simulation)
+    - target_sim_sc ? (tool_verilator? (files_verilator_waiver))
     toplevel: [core_v_mini_mcu]
 
   sim:
@@ -314,13 +343,17 @@ targets:
     - tool_modelsim? (pre_patch_modelsim_Makefile)
     - tool_vcs? (cfile_uartdpi)
     - tool_vcs? (pre_build_remote_bitbang)
+    - tool_xcelium? (pre_build_remote_bitbang)
+    - tool_xcelium? (pre_build_uartdpi)
     - tool_verilator? (tb-verilator)
     - tool_modelsim? (tb-sv)
     - tool_vcs? (tb-sv)
+    - tool_xcelium? (tb-sv)
     - "!integrated_heep? (x_heep_system)"
     toplevel:
     - tool_modelsim? (tb_top)
     - tool_vcs? (tb_top)
+    - tool_xcelium? (tb_top)
     - tool_verilator? (testharness)
     hooks:
       pre_build:
@@ -328,6 +361,8 @@ targets:
         - tool_modelsim? (pre_build_remote_bitbang)
         - tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
         - ams_sim? (pre_patch_vcs_ams_Makefile)
+        - tool_xcelium? (pre_build_uartdpi)
+        - tool_xcelium? (pre_build_remote_bitbang)
     parameters:
     - COREV_PULP
     - FPU
@@ -342,6 +377,7 @@ targets:
         - -override_timescale 1ns/1ps
         - -suppress vlog-2583
         - -suppress vlog-2577
+        - -suppress vlog-2720
         - -pedanticerrors
         - -define MODELSIM
         vsim_options:
@@ -364,6 +400,12 @@ targets:
          - -LDFLAGS "-pthread -lutil"
          - +lint=TFIPC-L
          - -V
+      xcelium:
+        xrun_options:
+        - -vtimescale 1ns/10ps
+        - -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.so
+        - -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs.so
+        - -define XCELIUM
       verilator:
         mode: cc
         verilator_options:
@@ -380,12 +422,48 @@ targets:
           - '-LDFLAGS "-pthread -lutil -lelf"'
           - "-Wall"
 
+  sim_sc:
+    <<: *default_target
+    default_tool: modelsim
+    filesets_append:
+    - tb-utils
+    - tool_verilator? (tb-sc-verilator)
+    - "!integrated_heep? (x_heep_system)"
+    toplevel:
+    - tool_verilator? (testharness)
+    parameters:
+    - COREV_PULP
+    - FPU
+    - JTAG_DPI
+    - X_EXT
+    - USE_EXTERNAL_DEVICE_EXAMPLE
+    - USE_UPF
+    - REMOVE_OBI_FIFO
+    - SIM_SYSTEMC=true
+    tools:
+      verilator:
+        mode: sc
+        verilator_options:
+          - '--sc'
+          - '--trace'
+          - '--trace-structs'
+          - '--trace-params'
+          - '--trace-max-array 1024'
+          - '--x-assign unique'
+          - '--x-initial unique'
+          - '--exe tb_sc_top.cpp'
+          - '-CFLAGS "-std=c++11 -Wall -g -fpermissive"'
+          - '-LDFLAGS "-pthread -lutil -lelf $(SYSTEMC_LIBDIR)/libsystemc.a"'
+          - "-Wall"
+
   nexys-a7-100t:
     <<: *default_target
     default_tool: vivado
     description: Digilent Nexys-A7-100T Board
     filesets_append:
+    - x_heep_system
     - rtl-fpga
+    - ip-fpga-nexys
     - ip-fpga
     - xdc-fpga-nexys
     parameters:
@@ -394,6 +472,7 @@ targets:
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
+    - FPGA_NEXYS=true
     tools:
       vivado:
         part: xc7a100tcsg324-1
@@ -406,6 +485,7 @@ targets:
     filesets_append:
     - x_heep_system
     - rtl-fpga
+    - ip-fpga-pynq-z2
     - ip-fpga
     - xdc-fpga-pynq-z2
     parameters:
@@ -419,27 +499,28 @@ targets:
         part: xc7z020clg400-1
     toplevel: [xilinx_core_v_mini_mcu_wrapper]
 
-  pynq-z2-arm-emulation:
+  zcu104:
     <<: *default_target
     default_tool: vivado
-    description: TUL Pynq-Z2 Board
+    description: ZCU104 Evaluation Board
     filesets_append:
     - x_heep_system
     - rtl-fpga
+    - ip-fpga-zcu104
     - ip-fpga
-    - fpga-arm-emulation
+    - xdc-fpga-zcu104
     parameters:
     - COREV_PULP
     - FPU
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
+    - FPGA_ZCU104=true
     tools:
       vivado:
-        part: xc7z020clg400-1
-        jobs: 4
-    toplevel: [linux_femu]
-
+        part: xczu7ev-ffvc1156-2-e
+    toplevel: [xilinx_core_v_mini_mcu_wrapper]
+    
   asic_synthesis:
     <<: *default_target
     default_tool: design_compiler
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile
index c0aab16c..2db8a17d 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile
@@ -107,7 +107,6 @@ or to execute all these three steps type:
 make run-helloworld
 ```
 
-
 ### Compiling for VCS
 
 To simulate your application with VCS, first compile the HDL:
@@ -238,7 +237,6 @@ The available parameters are:
 * LINKER: `on_chip`(default), `flash_load` or `flash_exec` (can provide more than one)
 * TIMEOUT: Integer number of seconds (default 120)
 
-
 #### Usage
 
 ##### Comands
@@ -286,15 +284,17 @@ Follow the [ExecuteFromFlash](./ExecuteFromFlash.md) guide to exxecute code dire
 
 ## Emulation on Xilinx FPGAs
 
-This project offers two different X-HEEP implementetions on the Xilinx FPGAs, called Standalone-FEMU and Linux-FEMU.
+This project offers two different X-HEEP implementetions on Xilinx FPGAs, called Standalone and FEMU.
 
-### Standalone-FEMU (Standalone Fpga EMUlation)
+### Standalone
 
 In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the FPGA, and its input/output are connected to the available headers on the FPGA board.
 
+Two FPGA boards are supported: the Xilinx Pynq-z2 and Nexys-A7-100t.
+
 Make sure you have the FPGA board files installed in your Vivado.
 
-For example, for the Xilinx Pynq-Z2 board, use the documentation provided at the following [link](https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html) to download and install them:
+For example, for the Pynq-Z2 board, use the documentation provided at the following [link](https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html) to download and install them:
 
 To build and program the bitstream for your FPGA with vivado, type:
 
@@ -302,6 +302,12 @@ To build and program the bitstream for your FPGA with vivado, type:
 make vivado-fpga FPGA_BOARD=pynq-z2
 ```
 
+or
+
+```
+make vivado-fpga FPGA_BOARD=nexys-a7-100t
+```
+
 or add the flag `use_bscane_xilinx` to use the native Xilinx scanchain:
 
 ```
@@ -323,12 +329,22 @@ to load the binaries with the HS2 cable over JTAG,
 or follow the [ExecuteFromFlash](./ExecuteFromFlash.md)
 guide if you have a FLASH attached to the FPGA.
 
-
 Do not forget that the `pynq-z2` board requires you to have the ethernet cable attached to the board while running.
 
+For example, if you want to run your application using flash_exec, do as follow:
+
+compile your application, e.g. `make app PROJECT=example_matfadd TARGET=pynq-z2 ARCH=rv32imfc LINKER=flash_exec`
+
+and then follow the [ExecuteFromFlash](./ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly.
+
+To look at the output of your printf, run in another terminal:
+
+`picocom -b 9600 -r -l --imap lfcrlf /dev/ttyUSB2`
+
+Please be sure to use the right `ttyUSB` number (you can discover it with `dmesg --time-format iso | grep FTDI` for example).
 
-### Linux-FEMU (Linux Fpga EMUlation)
+### FPGA EMUlation Platform (FEMU)
 
-In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the FPGA and Linux is run on the ARM-based processing system (PS) side of the same chip.
+In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the Xilinx Zynq-7020 chip on the Pynq-Z2 board and Linux is run on the ARM-based processing system (PS) side of the same chip.
 
-Read the [following](./linux_femu/README.md) documentation to have more information about this implementation.
+NOTE: This platform is not part of this repository, but you can access it with the following link: [FEMU](https://github.com/esl-epfl/x-heep-femu-sdk).
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md
index 4ec743f3..2a5882f6 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md
@@ -40,7 +40,7 @@ Now we are going to Simulate debugging with core-v-mini-mcu.
 In this setup, OpenOCD communicates with the remote bitbang server by means of DPIs.
 The remote bitbang server is simplemented in the folder ./hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang and it will be compiled using fusesoc.
 
-### Verilator
+### Verilator (C++ only)
 
 To simulate your application with Questasim using the remote_bitbang server, you need to compile you system adding the `JTAG DPI` functions:
 
@@ -130,24 +130,86 @@ Transfer rate: 67 bytes/sec, 798 bytes/write.
 
 `gdb` automatically set the `program counter` to start from `_start`, check with:
 
+Anytime you want to check the `disassemble`, just do:
+
+
+```
+(gdb) disassemble
+```
+
+and get an output that look like:
+
 ```
-(gdb) i r pc
+Dump of assembler code for function _start:
+=> 0x00000180 <+0>: auipc   gp,0xd
+   0x00000184 <+4>: addi    gp,gp,964 # 0xd544 <m_a+184>
+   0x00000188 <+8>: auipc   sp,0xf
+   0x0000018c <+12>:    addi    sp,sp,-1080 # 0xed50
+   0x00000190 <+16>:    lui a0,0x20000
+   ...
 ```
-It should give you `0x180`.
+
+```
+(gdb) info reg pc
+```
+Gives you the program counter.
 
 Now you can play with `gdb`
 
 e.g: Ask for the content of register `a0`
 
 ```
-(gdb) i r a0
+(gdb) info reg a0
 ```
-or just run the entire execution with the continue command and then check the `uart0.log` to see the printed hello world string:
+
+or set it to `15` as:
+
+```
+(gdb) set $a0=15
+```
+
+or just run the entire execution with the and then check the `uart0.log` to see the printed hello world string:
 
 ```
 (gdb) continue
 ```
 
+If you want to reset the non-debug modules (as the CPU):
+
+```
+(gdb) monitor reset halt
+```
+
+Set a breakpoint to a specific instruction address:
+
+```
+(gdb) b *0x0000019c
+Breakpoint 1 at 0x19c: file /x-heep/sw/device/lib/crt/crt0.S, line 38.
+```
+
+and continue the execution untill the breakpoint as:
+
+```
+(gdb) continue
+```
+
+Then check the breakpoint status:
+
+```
+(gdb) info b
+Num     Type           Disp Enb Address    What
+1       breakpoint     keep y   0x0000019c /x-heep/sw/device/lib/crt/crt0.S:38
+    breakpoint already hit 1 time
+```
+
+and finally delete it:
+
+```
+(gdb) delete 1
+(gdb) info b
+No breakpoints or watchpoints.
+```
+
 You can also run all the gdb steps by running:
 ```
 make gdb_connect MAINFILE=<main_file_name_of_the_project_that WAS_built WITHOUT EXTENSION>
@@ -202,6 +264,16 @@ or with the EPFL Programmer also using this other command (**strongly recommende
 make openOCD_epflp
 ```
 
+or with the BSCAN of the Pynq-Z2 board using this command:
+```
+openocd -f ./tb/core-v-mini-mcu-pynq-z2-bscan.cfg
+```
+
+or with the BSCAN of the Pynq-Z2 board also using this other command (**strongly recommended**):
+
+```
+make openOCD_bscan
+```
 
 If you get this error:
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md
index 530b9817..bbc89bd3 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md
@@ -97,3 +97,55 @@ For example, launching the script [`memcopy_periph_gen.sh`](./../../../hw/ip_exa
 1. `memcopy_periph_reg_top.sv`: the register file module. It can be directly instantiated inside your peripheral RTL code (e.g., [`memcopy_periph.sv`](./../../../hw/ip_examples/memcopy_periph/rtl/memcopy_periph.sv)) and connected to the peripheral device controller(s).
 2. `memcopy_periph_reg_pkg.sv`: SystemVerilog package containing the definitions used in the SystemVerilog module above.
 3. `memcopy_periph_regs.h`: C/C++ header file defining the address offset of the peripheral configuration registers. Take a look at the C code [here](./../../../sw/applications/example_external_peripheral/memcopy_periph.c) for a usage example.
+
+## External Interrupts
+
+X-HEEP includes several empty external interrupts slots that can be assigned both in HW and SW.
+
+Firstly, connect your external device's interrupt to one of the slots of the `external_interrupt_vector` of X-HEEP:
+
+```systemverilog
+
+logic [core_v_mini_mcu_pkg::NEXT_INT-1:0] ext_intr_vector;
+
+always_comb begin
+for (int i = 0; i < core_v_mini_mcu_pkg::NEXT_INT; i++) begin
+    ext_intr_vector[i] = 1'b0;    // All interrupt lines set to zero by default
+end
+ext_intr_vector[0] = my_device_int;  // Re-assign the interrupt lines used here
+end
+
+x_heep_system #(
+    . . .
+) x_heep_system_i (
+    .intr_vector_ext_i(ext_intr_vector),
+    . . .
+)
+
+```
+
+Then, when initializing the PLIC system in software, do not forget to assign the corresponding interrupt ID to your custom handler.
+
+```C
+#define MY_DEVICE_INTR EXT_INTR_0
+
+void handler_irq_my_device(uint32_t id) {
+    my_device_intr_flag = 1;
+    // Do whatever you need here
+}
+
+void main() {
+    plic_Init(); // Init the PLIC, this will clear all external interrupts assigned previously.
+    plic_irq_set_priority(MY_DEVICE_INTR, 1); // Set the priority of the external device's interrupt.
+    plic_irq_set_enabled(MY_DEVICE_INTR, kPlicToggleEnabled); // Enable the external device's interrupt.
+    plic_assign_external_irq_handler( MY_DEVICE_INTR, (void *) &handler_irq_my_device); // Assign a handler taht will be called when this interrupt is triggered.
+
+    // Enable global interrupt for machine-level interrupts
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+    // Set mie.MEIE bit to one to enable machine-level external interrupts
+    const uint32_t mask = 1 << 11;//IRQ_EXT_ENABLE_OFFSET;
+    CSR_SET_BITS(CSR_REG_MIE, mask);
+
+    . . .
+}
+```
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md
index 98c09221..7ed89d24 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md
@@ -92,30 +92,28 @@ Generate the C program you want to execute as described in the [ExecuteFromFlash
 then program the FLASH as:
 
 ```
-./iceprog -d i:0x0403:0x6011 -I B ../../../build/main.hex
+make flash-prog
 ```
 
-You can also program the FLASH by running:
+You can read the content of the FLASH as:
 
 ```
-make flash-prog MAINFILE=<main_file_name_of_the_project_that WAS_built WITHOUT EXTENSION>
+make flash-read FLASHREAD_ADDR=0x10000 FLASHREAD_BYTES=16; xxd flashcontent.hex
 ```
 
-You can read the content of the FLASH as:
+In this example, we are reading `16` bytes from the flash address `0x10000`.
 
-```
-./iceprog -d i:0x0403:0x6011 -I B -r flash_content.txt
-xxd flash_content.txt > flash_content.dump.txt
-```
 
 Now program the FPGA with the x-heep bitstream:
 
 
 ```
-cd build/openhwgroup.org_systems_core-v-mini-mcu_0/pynq-z2-vivado
+make vivado-fpga-pgm FPGA_BOARD=pynq-z2
 ```
 
-Remember to set the `boot_sel_i` and `execute_from_flash_i` switches to 1.
+Remember to set the `boot_sel_i` and `execute_from_flash_i` switches to `1` if you `execute from flash`,
+or just  `boot_sel_i` to `1` and `execute_from_flash_i` to `0`  if you `load from flash`.
+
 Reset the logic (so the x-heep reset and not the bitstream reset) and enjoy.
 
 Additional note: To use the flash directly from X-HEEP, you first need to execute from the PC any iceprog command targeting the Flash. On the exit of any iceprog program, the FTDI pins will be set to high impedance. If this is not performed, the pins from the FTDI won't be on high impedance and the SPI signals cannot be driven from X-HEEP (or any other device).
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/SystemC.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/SystemC.md
new file mode 100644
index 00000000..1a1aad57
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/SystemC.md
@@ -0,0 +1,16 @@
+#  SystemC model
+
+Supporting SystemC model in `X-HEEP` is still a work-in-progress.
+However, a simple example is provided in the SystemC testbench available in `tb/tb_sc_top.cpp`.
+
+When compiling the `X-HEEP` with Verilator using SystemC, the above testbench is used for simulation.
+The testbench gets an `X-HEEP` external-memory `obi` master port to communicate with a SystemC memory model.
+
+Such model is very simple as meant to be an example and is provided in `tb/systemc_tb`.
+For those who want to extend the functionality of `X-HEEP` with SystemC, such examples can be used as starting point.
+
+The SystemC modules leverages `TLM-2.0` as well as baseline SystemC functionalities.
+
+The `X-HEEP` `obi` port is connected to a `C++` direct-mapped cache who handles `hit` and `miss` with pre-defined latencies.
+It uses `TLM-2.0` to communicate with the external SystemC memory on `miss` cache-transactions.
+A module in SystemC then communicates with the RTL SystemC model compiled by Verilator to provides read/write data.
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
index 4a3073b8..504fed22 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
@@ -118,7 +118,10 @@ module ao_peripheral_subsystem
 
     // EXTERNAL PERIPH
     output reg_req_t ext_peripheral_slave_req_o,
-    input  reg_rsp_t ext_peripheral_slave_resp_i
+    input  reg_rsp_t ext_peripheral_slave_resp_i,
+
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -364,13 +367,15 @@ module ao_peripheral_subsystem
       .intr_timer_expired_1_0_o(rv_timer_1_intr_o)
   );
 
-  parameter DMA_TRIGGER_SLOT_NUM = 5;
+  parameter DMA_TRIGGER_SLOT_NUM = 7;
   logic [DMA_TRIGGER_SLOT_NUM-1:0] dma_trigger_slots;
   assign dma_trigger_slots[0] = spi_rx_valid;
   assign dma_trigger_slots[1] = spi_tx_ready;
   assign dma_trigger_slots[2] = spi_flash_rx_valid;
   assign dma_trigger_slots[3] = spi_flash_tx_ready;
   assign dma_trigger_slots[4] = i2s_rx_valid_i;
+  assign dma_trigger_slots[5] = ext_dma_slot_tx_i;
+  assign dma_trigger_slots[6] = ext_dma_slot_rx_i;
 
   dma #(
       .reg_req_t (reg_pkg::reg_req_t),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
index 4a1ef2e9..45f21d2c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
@@ -315,7 +315,10 @@ module core_v_mini_mcu
     output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_no,
 
-    output logic [31:0] exit_value_o
+    output logic [31:0] exit_value_o,
+
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -365,6 +368,7 @@ module core_v_mini_mcu
 
   // signals to debug unit
   logic debug_core_req;
+  logic debug_reset_n;
 
   // core
   logic core_sleep;
@@ -456,7 +460,7 @@ module core_v_mini_mcu
   ) cpu_subsystem_i (
       // Clock and Reset
       .clk_i,
-      .rst_ni(cpu_subsystem_rst_n),
+      .rst_ni(cpu_subsystem_rst_n && debug_reset_n),
       .core_instr_req_o(core_instr_req),
       .core_instr_resp_i(core_instr_resp),
       .core_data_req_o(core_data_req),
@@ -485,6 +489,7 @@ module core_v_mini_mcu
       .jtag_tdi_i,
       .jtag_tdo_o,
       .debug_core_req_o(debug_core_req),
+      .debug_ndmreset_no(debug_reset_n),
       .debug_slave_req_i(debug_slave_req),
       .debug_slave_resp_o(debug_slave_resp),
       .debug_master_req_o(debug_master_req),
@@ -496,7 +501,7 @@ module core_v_mini_mcu
       .EXT_XBAR_NMASTER(EXT_XBAR_NMASTER)
   ) system_bus_i (
       .clk_i,
-      .rst_ni,
+      .rst_ni(rst_ni && debug_reset_n),
       .core_instr_req_i(core_instr_req),
       .core_instr_resp_o(core_instr_resp),
       .core_data_req_i(core_data_req),
@@ -539,7 +544,7 @@ module core_v_mini_mcu
       .NUM_BANKS(core_v_mini_mcu_pkg::NUM_BANKS)
   ) memory_subsystem_i (
       .clk_i,
-      .rst_ni,
+      .rst_ni(rst_ni && debug_reset_n),
       .clk_gate_en_ni(memory_subsystem_clkgate_en_n),
       .ram_req_i(ram_slave_req),
       .ram_resp_o(ram_slave_resp),
@@ -548,7 +553,7 @@ module core_v_mini_mcu
 
   ao_peripheral_subsystem ao_peripheral_subsystem_i (
       .clk_i,
-      .rst_ni,
+      .rst_ni(rst_ni && debug_reset_n),
       .slave_req_i(ao_peripheral_slave_req),
       .slave_resp_o(ao_peripheral_slave_resp),
       .boot_select_i,
@@ -628,12 +633,14 @@ module core_v_mini_mcu
       .uart_intr_rx_parity_err_o(uart_intr_rx_parity_err),
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
-      .ext_peripheral_slave_resp_i
+      .ext_peripheral_slave_resp_i,
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (
       .clk_i,
-      .rst_ni(peripheral_subsystem_rst_n),
+      .rst_ni(peripheral_subsystem_rst_n && debug_reset_n),
       .clk_gate_en_ni(peripheral_subsystem_clkgate_en_n),
       .slave_req_i(peripheral_slave_req),
       .slave_resp_o(peripheral_slave_resp),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
index b4935df4..84255ec1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
@@ -69,7 +69,10 @@ ${pad.core_v_mini_mcu_interface}
     output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_no,
 
-    output logic [31:0] exit_value_o
+    output logic [31:0] exit_value_o,
+
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -119,6 +122,7 @@ ${pad.core_v_mini_mcu_interface}
 
   // signals to debug unit
   logic debug_core_req;
+  logic debug_reset_n;
 
   // core
   logic core_sleep;
@@ -210,7 +214,7 @@ ${pad.core_v_mini_mcu_interface}
   ) cpu_subsystem_i (
       // Clock and Reset
       .clk_i,
-      .rst_ni(cpu_subsystem_rst_n),
+      .rst_ni(cpu_subsystem_rst_n && debug_reset_n),
       .core_instr_req_o(core_instr_req),
       .core_instr_resp_i(core_instr_resp),
       .core_data_req_o(core_data_req),
@@ -239,6 +243,7 @@ ${pad.core_v_mini_mcu_interface}
       .jtag_tdi_i,
       .jtag_tdo_o,
       .debug_core_req_o(debug_core_req),
+      .debug_ndmreset_no(debug_reset_n),
       .debug_slave_req_i(debug_slave_req),
       .debug_slave_resp_o(debug_slave_resp),
       .debug_master_req_o(debug_master_req),
@@ -250,7 +255,7 @@ ${pad.core_v_mini_mcu_interface}
       .EXT_XBAR_NMASTER(EXT_XBAR_NMASTER)
   ) system_bus_i (
       .clk_i,
-      .rst_ni,
+      .rst_ni(rst_ni && debug_reset_n),
       .core_instr_req_i(core_instr_req),
       .core_instr_resp_o(core_instr_resp),
       .core_data_req_i(core_data_req),
@@ -293,7 +298,7 @@ ${pad.core_v_mini_mcu_interface}
       .NUM_BANKS(core_v_mini_mcu_pkg::NUM_BANKS)
   ) memory_subsystem_i (
       .clk_i,
-      .rst_ni,
+      .rst_ni(rst_ni && debug_reset_n),
       .clk_gate_en_ni(memory_subsystem_clkgate_en_n),
       .ram_req_i(ram_slave_req),
       .ram_resp_o(ram_slave_resp),
@@ -302,7 +307,7 @@ ${pad.core_v_mini_mcu_interface}
 
   ao_peripheral_subsystem ao_peripheral_subsystem_i (
       .clk_i,
-      .rst_ni,
+      .rst_ni(rst_ni && debug_reset_n),
       .slave_req_i(ao_peripheral_slave_req),
       .slave_resp_o(ao_peripheral_slave_resp),
       .boot_select_i,
@@ -380,12 +385,14 @@ ${pad.core_v_mini_mcu_interface}
       .uart_intr_rx_parity_err_o(uart_intr_rx_parity_err),
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
-      .ext_peripheral_slave_resp_i
+      .ext_peripheral_slave_resp_i,
+      .ext_dma_slot_tx_i,
+      .ext_dma_slot_rx_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (
       .clk_i,
-      .rst_ni(peripheral_subsystem_rst_n),
+      .rst_ni(peripheral_subsystem_rst_n && debug_reset_n),
       .clk_gate_en_ni(peripheral_subsystem_clkgate_en_n),
       .slave_req_i(peripheral_slave_req),
       .slave_resp_o(peripheral_slave_resp),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/cpu_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/cpu_subsystem.sv
index bbb62d75..256723f6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/cpu_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/cpu_subsystem.sv
@@ -59,21 +59,16 @@ module cpu_subsystem
 
   if (CPU_TYPE == cv32e20) begin : gen_cv32e20
 
-    logic [4:0] rf_raddr_a, rf_raddr_b, rf_waddr_wb;
-    logic [31:0] rf_rdata_a, rf_rdata_b, rf_wdata_wb;
-    logic rf_we_wb;
-
-    import ibex_pkg::*;
-
-    ibex_core #(
+    cve2_top #(
         .DmHaltAddr(DM_HALTADDRESS),
-        .DmExceptionAddr(32'h0),
-        .DbgTriggerEn(1'b1),
-        .ResetAll(1'b1)
+        .DmExceptionAddr('0)
     ) cv32e20_i (
         .clk_i (clk_i),
         .rst_ni(rst_ni),
 
+        .test_en_i(1'b0),
+        .ram_cfg_i('0),
+
         .hart_id_i  (32'h0),
         .boot_addr_i(BOOT_ADDR),
 
@@ -94,79 +89,20 @@ module cpu_subsystem
         .data_rvalid_i(core_data_resp_i.rvalid),
         .data_err_i   (1'b0),
 
-        .dummy_instr_id_o (),
-        .rf_raddr_a_o     (rf_raddr_a),
-        .rf_raddr_b_o     (rf_raddr_b),
-        .rf_waddr_wb_o    (rf_waddr_wb),
-        .rf_we_wb_o       (rf_we_wb),
-        .rf_wdata_wb_ecc_o(rf_wdata_wb),
-        .rf_rdata_a_ecc_i (rf_rdata_a),
-        .rf_rdata_b_ecc_i (rf_rdata_b),
-
-        .ic_tag_req_o      (),
-        .ic_tag_write_o    (),
-        .ic_tag_addr_o     (),
-        .ic_tag_wdata_o    (),
-        .ic_tag_rdata_i    (),
-        .ic_data_req_o     (),
-        .ic_data_write_o   (),
-        .ic_data_addr_o    (),
-        .ic_data_wdata_o   (),
-        .ic_data_rdata_i   (),
-        .ic_scr_key_valid_i(),
-
         .irq_software_i(irq_i[3]),
         .irq_timer_i   (irq_i[7]),
         .irq_external_i(irq_i[11]),
-        .irq_fast_i    (irq_i[30:16]),
-        .irq_nm_i      (irq_i[31]),
-        .irq_pending_o (),
+        .irq_fast_i    (irq_i[31:16]),
+        .irq_nm_i      (1'b0),
 
-        .debug_req_i(debug_req_i),
+        .debug_req_i (debug_req_i),
         .crash_dump_o(),
-        .double_fault_seen_o(),
 
         .fetch_enable_i(fetch_enable),
-        .alert_minor_o (),
-        .alert_major_o (),
-        .icache_inval_o(),
-        .core_sleep_o
-    );
-
-    cv32e40p_register_file #(
-        .ADDR_WIDTH(6)
-    ) cv32e20_register_file_i (
-        // Clock and Reset
-        .clk  (clk_i),
-        .rst_n(rst_ni),
-
-        .scan_cg_en_i(1'b0),
-
-        //Read port R1
-        .raddr_a_i({1'b0, rf_raddr_a}),
-        .rdata_a_o(rf_rdata_a),
-
-        //Read port R2
-        .raddr_b_i({1'b0, rf_raddr_b}),
-        .rdata_b_o(rf_rdata_b),
-
-        //Read port R3
-        .raddr_c_i('0),
-        .rdata_c_o(),
 
-        // Write port W1
-        .waddr_a_i({1'b0, rf_waddr_wb}),
-        .wdata_a_i(rf_wdata_wb),
-        .we_a_i(rf_we_wb),
-
-        // Write port W2
-        .waddr_b_i('0),
-        .wdata_b_i('0),
-        .we_b_i('0)
+        .core_sleep_o
     );
 
-
-
     assign irq_ack_o = '0;
     assign irq_id_o  = '0;
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv
index 392c12ad..673c1b31 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv
@@ -16,6 +16,7 @@ module debug_subsystem
     input  logic jtag_tdi_i,
     output logic jtag_tdo_o,
 
+    output logic debug_ndmreset_no,
     output logic debug_core_req_o,
 
     input  obi_req_t  debug_slave_req_i,
@@ -42,7 +43,9 @@ module debug_subsystem
   dm::dmi_resp_t dmi_resp;
   logic          dmi_resp_ready;
   logic          dmi_resp_valid;
+  logic          ndmreset;
 
+  assign debug_ndmreset_no = ~ndmreset;
 
   dmi_jtag #(
       .IdcodeValue(JTAG_IDCODE)
@@ -69,10 +72,10 @@ module debug_subsystem
       .clk_i        (clk_i),
       .rst_ni       (rst_ni),
       .testmode_i   (1'b0),
-      .ndmreset_o   (),
+      .ndmreset_o   (ndmreset),
       .dmactive_o   (),
       .debug_req_o  (debug_core_req_o),
-      .unavailable_i(~(1'b01)),
+      .unavailable_i(~(1'b1)),
       .hartinfo_i   (hartinfo),
 
       .slave_req_i   (debug_slave_req_i.req),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.lock.hjson
new file mode 100644
index 00000000..3a3e601c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.lock.hjson
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+  upstream:
+  {
+    url: https://github.com/esl-epfl/nexys-a7-100t_board_files.git
+    rev: 19e19ad6bd3b5a405d3e0ef98fee94e7e19e3bab
+  }
+}
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.vendor.hjson
new file mode 100644
index 00000000..af1e9c40
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys-a7-100t_board_files.vendor.hjson
@@ -0,0 +1,17 @@
+// Copyright 2022 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+{
+  name: "esl_epfl_nexys_a7_100t_board_files",
+  target_dir: "esl_epfl_nexys_a7_100t_board_files",
+
+  upstream: {
+    url: "https://github.com/esl-epfl/nexys-a7-100t_board_files.git",
+    rev: "19e19ad6bd3b5a405d3e0ef98fee94e7e19e3bab",
+  },
+
+  exclude_from_upstream: [
+    "README.md"
+  ]
+}
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/board.xml b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/board.xml
new file mode 100644
index 00000000..1ce62873
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/board.xml
@@ -0,0 +1,1301 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<board schema_version="2.0" vendor="digilentinc.com" name="nexys-a7-100t" display_name="Nexys A7-100T" url="https://digilent.com/reference/programmable-logic/nexys-a7/start" preset_file="preset.xml" >
+<compatible_board_revisions>
+  <revision id="0">D.0</revision>
+</compatible_board_revisions>
+<file_version>1.3</file_version>
+<description>Nexys A7-100T</description>
+<components>
+  <component name="part0" display_name="Nexys A7-100T" type="fpga" part_name="xc7a100tcsg324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/nexys-a7/start">
+    <interfaces>
+      <interface mode="master" name="acl_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="acl_spi" preset_proc="spi_preset">
+        <description>Accelerometer control through SPI</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="acl_mosi_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="acl_mosi_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="acl_mosi_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_mosi_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="acl_miso_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="acl_miso_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="acl_miso_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_miso_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_I" physical_port="acl_sclk_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_O" physical_port="acl_sclk_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCK_T" physical_port="acl_sclk_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_sclk_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="acl_ss_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="acl_ss_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="acl_ss_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="acl_ss_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="ddr2_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr2_sdram" preset_proc="ddr2_sdram_preset"> 
+      <description>DDR2 board interface, it can use MIG IP for connection.</description>
+	  <preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
+	  </preferred_ips>
+	  </interface>
+      <interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
+        <description>16 DIP Switches</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/> 
+              <pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/> 
+              <pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/> 
+              <pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/> 
+              <pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/> 
+              <pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/> 
+              <pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/> 
+              <pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/> 
+              <pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/> 
+              <pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/> 
+              <pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/> 
+              <pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="dual_seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dual_seven_seg_led_disp" preset_proc="output_8bits_preset">
+        <description>Dual 7 Seg LED Segments</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="dual_seven_seg_led_disp_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="dual_seven_seg_led_disp_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="dual_seven_seg_led_disp_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="dual_seven_seg_led_disp_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="dual_seven_seg_led_disp_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="dual_seven_seg_led_disp_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="dual_seven_seg_led_disp_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="dual_seven_seg_led_disp_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="dual_seven_seg_led_disp_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="output_16bits_preset">
+        <description>16 LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="led_16bits_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="led_16bits_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="led_16bits_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="led_16bits_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="led_16bits_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="led_16bits_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="led_16bits_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="led_16bits_tri_o_7"/> 
+              <pin_map port_index="8" component_pin="led_16bits_tri_o_8"/> 
+              <pin_map port_index="9" component_pin="led_16bits_tri_o_9"/> 
+              <pin_map port_index="10" component_pin="led_16bits_tri_o_10"/> 
+              <pin_map port_index="11" component_pin="led_16bits_tri_o_11"/> 
+              <pin_map port_index="12" component_pin="led_16bits_tri_o_12"/> 
+              <pin_map port_index="13" component_pin="led_16bits_tri_o_13"/> 
+              <pin_map port_index="14" component_pin="led_16bits_tri_o_14"/> 
+              <pin_map port_index="15" component_pin="led_16bits_tri_o_15"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="push_buttons_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_5bits" preset_proc="push_buttons_5bits_preset">
+        <description>5 Push Buttons</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri_i" dir="in" left="4" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/> 
+              <pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/> 
+              <pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/> 
+              <pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/> 
+              <pin_map port_index="4" component_pin="push_buttons_5bits_tri_i_4"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
+        <description>Quad SPI Flash</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db0_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db1_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db2_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_db3_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="qspi_csn_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+        <port_maps>
+          <port_map logical_port="RST" physical_port="reset" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="reset"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="rst_polarity" value="0" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
+        <description>2 RGB LEDs</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="rgb_led_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="rgb_led_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="rgb_led_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="rgb_led_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="rgb_led_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="rgb_led_tri_o_5"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="output_8bits_preset">
+        <description>7 Segment Display Anodes</description>
+		<preferred_ips>
+			<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="7" right="0"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/> 
+              <pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/> 
+              <pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/> 
+              <pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/> 
+              <pin_map port_index="4" component_pin="seven_seg_led_an_tri_o_4"/> 
+              <pin_map port_index="5" component_pin="seven_seg_led_an_tri_o_5"/> 
+              <pin_map port_index="6" component_pin="seven_seg_led_an_tri_o_6"/> 
+              <pin_map port_index="7" component_pin="seven_seg_led_an_tri_o_7"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock">
+        <port_maps>
+          <port_map logical_port="CLK" physical_port="clk" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="clk"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+        <parameters>
+          <parameter name="frequency" value="100000000" />
+       </parameters>
+      </interface>
+      <interface mode="master" name="temp_sensor" type="xilinx.com:interface:iic_rtl:1.0" of_component="temp_sensor">
+        <description>Temperature Sensor connected to I2C</description>
+		<port_maps>
+          <port_map logical_port="SDA_I" physical_port="temp_sda_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_O" physical_port="temp_sda_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SDA_T" physical_port="temp_sda_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_sda_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_I" physical_port="temp_scl_i" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_O" physical_port="temp_scl_o" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="SCL_T" physical_port="temp_scl_t" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="temp_scl_i"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+      <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
+        <description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+		<port_maps>
+          <port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_txd"/> 
+            </pin_maps>
+          </port_map>
+          <port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rxd"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="RTSn" physical_port="usb_uart_rts" dir="out">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_rts"/> 
+            </pin_maps>
+          </port_map>
+		  <port_map logical_port="CTSn" physical_port="usb_uart_cts" dir="in">
+            <pin_maps>
+              <pin_map port_index="0" component_pin="usb_uart_cts"/> 
+            </pin_maps>
+          </port_map>
+        </port_maps>
+      </interface>
+	  
+	  <interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JA1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JA1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JA2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JA2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JA3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JA3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JA4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JA4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JA7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JA7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JA8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JA8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JA9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JA9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JA10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JA10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JA10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JB1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JB1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JB2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JB2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JB3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JB3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JB4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JB4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JB7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JB7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JB8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JB8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JB9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JB9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JB10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JB10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JB10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jd">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JD10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
+        <port_maps>
+          <port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="JXADC10"/> 
+			</pin_maps>
+		  </port_map>
+        </port_maps>
+      </interface>
+	  <interface mode="master" name="sd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="sd">
+       <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="1"/>
+		</preferred_ips>
+		<port_maps>
+          <port_map logical_port="PIN1_I" physical_port="SD1" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_O" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN1_T" physical_port="SD1" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD1"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_I" physical_port="SD2" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_O" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN2_T" physical_port="SD2" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD2"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_I" physical_port="SD3" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_O" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN3_T" physical_port="SD3" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD3"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_I" physical_port="SD4" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_O" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN4_T" physical_port="SD4" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD4"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_I" physical_port="SD7" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_O" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN7_T" physical_port="SD7" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD7"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_I" physical_port="SD8" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_O" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN8_T" physical_port="SD8" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD8"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_I" physical_port="SD9" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_O" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN9_T" physical_port="SD9" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD9"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_I" physical_port="SD10" dir="in"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_O" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		  <port_map logical_port="PIN10_T" physical_port="SD10" dir="out"> 
+            <pin_maps>
+              <pin_map port_index="0" component_pin="SD10"/> 
+			</pin_maps>
+		  </port_map>
+		</port_maps>
+      </interface>
+    </interfaces>
+  </component>
+  <component name="acl_spi" display_name="Accelerometer" type="chip" sub_type="chip" major_group="Peripherals">
+	<description>Accelerometer controlled through SPI</description>
+  </component>
+  <component name="ddr2_sdram" display_name="DDR2 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
+  <description>256 MB Onboard DDR Memory </description>
+	<parameters>
+        <parameter name="ddr_type" value="ddr2"/>
+        <parameter name="size" value="256MB"/>
+	</parameters>
+  </component>
+  <component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
+	<description>16 Switches</description>
+  </component>
+  <component name="dual_seven_seg_led_disp" display_name="7 Segments" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Segment Control</description>
+  </component>
+  <component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>16 LEDs</description>
+  </component>
+  <component name="push_buttons_5bits" display_name="5 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
+	<description>Push Buttons 5 to 0 {Down Right Left Up Center} </description>
+  </component>
+  <component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
+	<description>QSPI Flash</description>
+  </component>
+  <component name="reset" display_name="Reset" type="chip" sub_type="reset" major_group="Reset">
+	<description>Onboard Reset Button</description>
+  </component>
+  <component name="rgb_led" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
+	<description>2 RGB LEDs</description>
+  </component>
+  <component name="seven_seg_led_an" display_name="8 Anodes" type="chip" sub_type="led" major_group="7 Segment Display">
+	<description>7 Segment Display Anodes</description>
+  </component>
+  <component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock">
+	<description>100 MHz Single-Ended System Clock</description>
+  </component>
+  <component name="temp_sensor" display_name="Temp Sensor" type="chip" sub_type="mux" major_group="Peripherals">
+	<description>SPI Controlled Temperature Sensor</description>
+  </component>
+  <component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
+	<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
+  </component>
+  <component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JA</description>
+  </component>
+  <component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JB</description>
+  </component>
+  <component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JC</description>
+  </component>
+  <component name="jd" display_name="Connector JD" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JD</description>
+  </component>
+  <component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
+	<description>Pmod Connector JXADC</description>
+  </component>
+  <component name="sd" display_name="Onboard Micro SD Slot" type="chip" sub_type="chip" major_group="External Memory">
+  <component_modes>
+	<component_mode name="apmodsd" display_name="Digilent PmodSD IP">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+			<preferred_ip vendor="digilentinc.com" library="ip" name="PmodSD" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+	<component_mode name="bpmodbridge" display_name="Pmod Bridge (Custom SPI/GPIO)">
+	  <interfaces>
+		<interface name="sd"/>
+	  </interfaces>
+	  <preferred_ips>
+		  <preferred_ip vendor="digilentinc.com" library="ip" name="pmod_bridge" order="0"/>
+	  </preferred_ips>
+	</component_mode>
+  </component_modes>
+	<description>Onboard MicroSD Card Slot</description>
+  </component>
+</components>
+<jtag_chains>
+  <jtag_chain name="chain1">
+    <position name="0" component="part0"/>
+  </jtag_chain>
+</jtag_chains>
+<connections>
+  <connection name="part0_acl_spi" component1="part0" component2="acl_spi">
+    <connection_map name="part0_acl_spi_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
+    <connection_map name="part0_dip_switches_16bits_1" c1_st_index="5" c1_end_index="20" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_dual_seven_seg_led_disp" component1="part0" component2="dual_seven_seg_led_disp">
+    <connection_map name="part0_dual_seven_seg_led_disp_1" c1_st_index="21" c1_end_index="28" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_led_16bits" component1="part0" component2="led_16bits">
+    <connection_map name="part0_led_16bits_1" c1_st_index="38" c1_end_index="53" c2_st_index="0" c2_end_index="15"/>
+  </connection>
+  <connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
+    <connection_map name="part0_push_buttons_5bits_1" c1_st_index="54" c1_end_index="58" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
+    <connection_map name="part0_qspi_flash_1" c1_st_index="59" c1_end_index="63" c2_st_index="0" c2_end_index="4"/>
+  </connection>
+  <connection name="part0_reset" component1="part0" component2="reset">
+    <connection_map name="part0_reset_1" c1_st_index="64" c1_end_index="64" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_rgb_led" component1="part0" component2="rgb_led">
+    <connection_map name="part0_rgb_led_1" c1_st_index="65" c1_end_index="70" c2_st_index="0" c2_end_index="5"/>
+  </connection>
+  <connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
+    <connection_map name="part0_seven_seg_led_an_1" c1_st_index="71" c1_end_index="78" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sys_clock" component1="part0" component2="sys_clock">
+    <connection_map name="part0_sys_clock_1" c1_st_index="4" c1_end_index="4" c2_st_index="0" c2_end_index="0"/>
+  </connection>
+  <connection name="part0_temp_sensor" component1="part0" component2="temp_sensor">
+    <connection_map name="part0_temp_sensor_1" c1_st_index="79" c1_end_index="80" c2_st_index="0" c2_end_index="1"/>
+  </connection>
+  <connection name="part0_usb_uart" component1="part0" component2="usb_uart">
+    <connection_map name="part0_usb_uart_1" c1_st_index="81" c1_end_index="82" c2_st_index="0" c2_end_index="1"/>
+	<connection_map name="part0_usb_uart_rts_cts" c1_st_index="179" c1_end_index="180" c2_st_index="2" c2_end_index="3"/>
+  </connection>
+  <connection name="part0_ja" component1="part0" component2="ja">
+    <connection_map name="part0_ja_1" c1_st_index="83" c1_end_index="90" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jb" component1="part0" component2="jb">
+    <connection_map name="part0_jb_1" c1_st_index="91" c1_end_index="98" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jc" component1="part0" component2="jc">
+    <connection_map name="part0_jc_1" c1_st_index="99" c1_end_index="106" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jd" component1="part0" component2="jd">
+    <connection_map name="part0_jd_1" c1_st_index="107" c1_end_index="114" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_jxadc" component1="part0" component2="jxadc">
+    <connection_map name="part0_jxadc_1" c1_st_index="115" c1_end_index="122" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  <connection name="part0_sd" component1="part0" component2="sd">
+    <connection_map name="part0_ja_1" c1_st_index="171" c1_end_index="178" c2_st_index="0" c2_end_index="7"/>
+  </connection>
+  
+ 
+</connections>
+</board>
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/mig.prj b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/mig.prj
new file mode 100644
index 00000000..301f5834
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/mig.prj
@@ -0,0 +1,157 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project NoOfControllers="1">
+
+  
+
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+
+  <ModuleName>design_1_mig_7series_0_0</ModuleName>
+
+  <dci_inouts_inputs>1</dci_inouts_inputs>
+
+  <dci_inputs>1</dci_inputs>
+
+  <Debug_En>OFF</Debug_En>
+
+  <DataDepth_En>1024</DataDepth_En>
+
+  <LowPower_En>ON</LowPower_En>
+
+  <XADC_En>Enabled</XADC_En>
+
+  <TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
+
+  <Version>4.2</Version>
+
+  <SystemClock>Single-Ended</SystemClock>
+
+  <ReferenceClock>No Buffer</ReferenceClock>
+
+  <SysResetPolarity>ACTIVE LOW</SysResetPolarity>
+
+  <BankSelectionFlag>FALSE</BankSelectionFlag>
+
+  <InternalVref>1</InternalVref>
+
+  <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+
+  <dci_cascade>0</dci_cascade>
+
+  <FPGADevice>
+    <selected>7a/xc7a50t-csg324</selected>
+  </FPGADevice>
+
+  <Controller number="0">
+    <MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice>
+    <TimePeriod>3077</TimePeriod>
+    <VccAuxIO>1.8V</VccAuxIO>
+    <PHYRatio>4:1</PHYRatio>
+    <InputClkFreq>99.997</InputClkFreq>
+    <UIExtraClocks>1</UIExtraClocks>
+    <MMCM_VCO>1200</MMCM_VCO>
+    <MMCMClkOut0> 6.000</MMCMClkOut0>
+    <MMCMClkOut1>1</MMCMClkOut1>
+    <MMCMClkOut2>1</MMCMClkOut2>
+    <MMCMClkOut3>1</MMCMClkOut3>
+    <MMCMClkOut4>1</MMCMClkOut4>
+    <DataWidth>16</DataWidth>
+    <DeepMemory>1</DeepMemory>
+    <DataMask>1</DataMask>
+    <ECC>Disabled</ECC>
+    <Ordering>Strict</Ordering>
+    <BankMachineCnt>4</BankMachineCnt>
+    <CustomPart>FALSE</CustomPart>
+    <NewPartName/>
+    <RowAddress>13</RowAddress>
+    <ColAddress>10</ColAddress>
+    <BankAddress>3</BankAddress>
+    <C0_MEM_SIZE>134217728</C0_MEM_SIZE>
+    <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
+    <PinSelection>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr2_addr[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr2_addr[10]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr2_addr[11]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr2_addr[12]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr2_addr[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr2_addr[2]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr2_addr[3]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr2_addr[4]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr2_addr[5]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr2_addr[6]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr2_addr[7]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr2_addr[8]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr2_addr[9]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr2_ba[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr2_ba[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr2_ba[2]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr2_cas_n"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="" VCCAUX_IO="" name="ddr2_ck_n[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr2_ck_p[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr2_cke[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr2_cs_n[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr2_dm[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr2_dm[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr2_dq[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr2_dq[10]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr2_dq[11]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr2_dq[12]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="" VCCAUX_IO="" name="ddr2_dq[13]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr2_dq[14]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr2_dq[15]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr2_dq[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr2_dq[2]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr2_dq[3]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr2_dq[4]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr2_dq[5]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr2_dq[6]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr2_dq[7]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr2_dq[8]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr2_dq[9]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr2_dqs_n[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr2_dqs_n[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr2_dqs_p[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr2_dqs_p[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr2_odt[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr2_ras_n"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr2_we_n"/>
+    </PinSelection>
+    <System_Clock>
+      <Pin Bank="35" PADName="E3(MRCC_P)" name="sys_clk_i"/>
+    </System_Clock>
+    <System_Control>
+      <Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
+      <Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
+      <Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
+    </System_Control>
+    <TimingParameters>
+      <Parameters tfaw="45" tras="40" trcd="15" trefi="7.8" trfc="127.5" trp="12.5" trrd="10" trtp="7.5" twtr="7.5"/>
+    </TimingParameters>
+    <mrBurstLength name="Burst Length">8</mrBurstLength>
+    <mrBurstType name="Burst Type">Sequential</mrBurstType>
+    <mrCasLatency name="CAS Latency">5</mrCasLatency>
+    <mrMode name="Mode">Normal</mrMode>
+    <mrDllReset name="DLL Reset">No</mrDllReset>
+    <mrPdMode name="PD Mode">Fast exit</mrPdMode>
+    <mrWriteRecovery name="Write Recovery">5</mrWriteRecovery>
+    <emrDllEnable name="DLL Enable">Enable-Normal</emrDllEnable>
+    <emrOutputDriveStrength name="Output Drive Strength">Fullstrength</emrOutputDriveStrength>
+    <emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
+    <emrCKSelection name="Memory Clock Selection">1</emrCKSelection>
+    <emrRTT name="RTT (nominal) - ODT">50ohms</emrRTT>
+    <emrPosted name="Additive Latency (AL)">0</emrPosted>
+    <emrOCD name="OCD Operation">OCD Exit</emrOCD>
+    <emrDQS name="DQS# Enable">Enable</emrDQS>
+    <emrRDQS name="RDQS Enable">Disable</emrRDQS>
+    <emrOutputs name="Outputs">Enable</emrOutputs>
+    <PortInterface>AXI</PortInterface>
+    <AXIParameters>
+      <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
+      <C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH>
+      <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+      <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+      <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
+    </AXIParameters>
+  </Controller>
+
+
+</Project>
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/part0_pins.xml b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/part0_pins.xml
new file mode 100644
index 00000000..43f20b5e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/part0_pins.xml
@@ -0,0 +1,153 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<part_info part_name="xc7a100tcsg324-1">
+<pins>
+  <pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
+  <pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
+  <pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
+  <pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
+  <pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
+  <pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
+  <pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
+  <pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
+  <pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
+  <pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
+  <pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
+  <pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
+  <pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
+  <pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
+  <pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
+  <pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
+  <pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
+  <pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
+  <pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
+  <pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
+  <pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
+  <pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
+  <pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
+  <pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
+  <pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
+  <pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
+  <pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
+  <pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
+  <pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
+  <pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
+  <pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
+  <pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
+  <pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
+  <pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
+  <pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
+  <pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
+  <pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
+  <pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
+  <pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
+  <pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
+  <pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
+  <pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
+  <pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
+  <pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
+  <pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
+  <pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
+  <pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
+  <pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
+  <pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
+  <pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
+  <pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
+  <pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
+  <pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
+  <pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
+  <pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
+  <pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
+  <pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
+  <pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
+  <pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
+  <pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
+  <pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
+  <pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
+  <pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
+  <pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
+  <pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
+  <pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
+  <pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
+  <pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
+  <pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
+  <pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
+  <pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
+  <pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
+  <pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
+  <pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
+  <pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
+  <pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
+  <pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
+  <pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
+  <pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
+  <pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
+  <pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
+  <pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
+  <pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
+  <pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
+  <pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
+  <pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
+  <pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
+  <pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
+  <pin index="99" name ="JC1"  iostandard="LVCMOS33" loc="K1"/>
+  <pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
+  <pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
+  <pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
+  <pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
+  <pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
+  <pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
+  <pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
+  <pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
+  <pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
+  <pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
+  <pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
+  <pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
+  <pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
+  <pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
+  <pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
+  <pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
+  <pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
+  <pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
+  <pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
+  <pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
+  <pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
+  <pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
+  <pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
+  <pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
+  <pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
+  <pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
+  <pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
+  <pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
+  <pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
+  <pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
+  <pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
+  <pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
+  <pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
+  
+</pins>
+</part_info>
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/preset.xml b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/preset.xml
new file mode 100644
index 00000000..7128ccee
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files/preset.xml
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<!--
+MIT License
+
+Copyright (c) 2021 Digilent, Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+-->
+<ip_presets schema="1.0">
+  <ip_preset preset_proc_name="ddr2_sdram_preset">
+    <ip vendor="xilinx.com" library="ip" name="mig_7series">
+      <user_parameters>
+        <user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/> 
+      </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="qspi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="spi_preset">
+	<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
+		<user_parameters>
+			<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
+			<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
+			<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
+		</user_parameters>
+	</ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="dip_switches_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="push_buttons_5bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="5"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+   <ip_preset preset_proc_name="output_8bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_6bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="6"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="output_16bits_preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/> 
+		  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+		  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
+        </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="16"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  <ip_preset preset_proc_name="uart_preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+</ip_presets>
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.lock.hjson
new file mode 100644
index 00000000..a05740cc
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.lock.hjson
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+  upstream:
+  {
+    url: https://github.com/esl-epfl/zcu104_board_files.git
+    rev: 53e4affbaeec73809304940be8f5351ae147227a
+  }
+}
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.vendor.hjson
new file mode 100644
index 00000000..69028826
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files.vendor.hjson
@@ -0,0 +1,16 @@
+// Copyright 2023 David Mallasén Quintana
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+{
+  name: "esl_epfl_zcu104_board_files",
+  target_dir: "esl_epfl_zcu104_board_files",
+
+  upstream: {
+    url: "https://github.com/esl-epfl/zcu104_board_files.git",
+    rev: "53e4affbaeec73809304940be8f5351ae147227a",
+  },
+
+  exclude_from_upstream: [
+    "README.md"
+  ]
+}
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/board.xml b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/board.xml
new file mode 100644
index 00000000..2206a918
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/board.xml
@@ -0,0 +1,657 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<board schema_version="2.1" vendor="xilinx.com" name="zcu104" display_name="Zynq UltraScale+ ZCU104 Evaluation Board" url="www.xilinx.com/zcu104" preset_file="preset.xml">
+ 
+  <images>
+    <image name="zcu104_board.jpeg" display_name="ZCU104 BOARD" sub_type="board">
+      <description>ZCU104 Board File Image</description>
+    </image>
+  </images>
+  
+  <compatible_board_revisions>
+	 <revision id="0">RevA</revision>
+	 <revision id="1">RevB</revision>
+	 <revision id="1">RevC</revision>
+  </compatible_board_revisions>
+
+  <file_version>1.0</file_version>
+
+  <description>Zynq UltraScale+ ZCU104 Evaluation Board</description>
+  <parameters>
+    <parameter name="heat_sink_type" value="medium" value_type="string"/>
+    <parameter name="heat_sink_temperature" value_type="range" value_min="20.0" value_max="30.0"/>
+  </parameters>
+
+  <jumpers>
+  </jumpers>
+
+
+  <components>
+  
+   
+  <component name="fmc_lpc_connector" display_name="FMC_LPC" type="connector" sub_type="fmc_lpc">
+  <pins>
+    <pin index="82" name="fmc_lpc_dp0_c2m_p"></pin>
+    <pin index="83" name="fmc_lpc_dp0_c2m_n"></pin> 
+    <pin index="86" name="fmc_lpc_dp0_m2c_p"></pin> 
+    <pin index="87" name="fmc_lpc_dp0_m2c_n"></pin> 
+    <pin index="90" name="fmc_lpc_la06_p"></pin> 
+    <pin index="91" name="fmc_lpc_la06_n"></pin> 
+    <pin index="94" name="fmc_lpc_la10_p"></pin> 
+    <pin index="95" name="fmc_lpc_la10_n"></pin> 
+    <pin index="98" name="fmc_lpc_la14_p"></pin> 
+    <pin index="99" name="fmc_lpc_la14_n"></pin> 
+    <pin index="102" name="fmc_lpc_la18_p"></pin> 
+    <pin index="103" name="fmc_lpc_la18_n"></pin> 
+    <pin index="106" name="fmc_lpc_la27_p"></pin> 
+    <pin index="107" name="fmc_lpc_la27_n"></pin> 
+    <pin index="124" name="fmc_lpc_gbtclk0_m2c_p"></pin> 
+    <pin index="125" name="fmc_lpc_gbtclk0_m2c_n"></pin> 
+    <pin index="128" name="fmc_lpc_la01_p"></pin> 
+    <pin index="129" name="fmc_lpc_la01_n"></pin> 
+    <pin index="131" name="fmc_lpc_la05_p"></pin> 
+    <pin index="132" name="fmc_lpc_la05_n"></pin> 
+    <pin index="134" name="fmc_lpc_la09_p"></pin> 
+    <pin index="135" name="fmc_lpc_la09_n"></pin> 
+    <pin index="137" name="fmc_lpc_la13_p"></pin> 
+    <pin index="138" name="fmc_lpc_la13_n"></pin> 
+    <pin index="140" name="fmc_lpc_la17_p"></pin> 
+    <pin index="141" name="fmc_lpc_la17_n"></pin> 
+    <pin index="143" name="fmc_lpc_la23_p"></pin> 
+    <pin index="144" name="fmc_lpc_la23_n"></pin> 
+    <pin index="146" name="fmc_lpc_la26_p"></pin> 
+    <pin index="147" name="fmc_lpc_la26_n"></pin> 
+    <pin index="242" name="fmc_lpc_clk1_m2c_p"></pin> 
+    <pin index="243" name="fmc_lpc_clk1_m2c_n"></pin> 
+    <pin index="246" name="fmc_lpc_la00_p"></pin> 
+    <pin index="247" name="fmc_lpc_la00_n"></pin> 
+	
+    <pin index="249" name="fmc_lpc_la03_p"></pin> 
+    <pin index="250" name="fmc_lpc_la03_n"></pin> 
+    <pin index="252" name="fmc_lpc_la08_p"></pin> 
+    <pin index="253" name="fmc_lpc_la08_n"></pin> 
+    <pin index="255" name="fmc_lpc_la12_p"></pin> 
+    <pin index="256" name="fmc_lpc_la12_n"></pin> 
+    <pin index="258" name="fmc_lpc_la16_p"></pin> 
+    <pin index="259" name="fmc_lpc_la16_n"></pin> 
+    <pin index="261" name="fmc_lpc_la20_p"></pin> 
+    <pin index="262" name="fmc_lpc_la20_n"></pin> 
+	
+    <pin index="264" name="fmc_lpc_la22_p"></pin> 
+    <pin index="265" name="fmc_lpc_la22_n"></pin> 
+    <pin index="267" name="fmc_lpc_la25_p"></pin> 
+    <pin index="268" name="fmc_lpc_la25_n"></pin> 
+    <pin index="270" name="fmc_lpc_la29_p"></pin> 
+    <pin index="271" name="fmc_lpc_la29_n"></pin> 
+    <pin index="273" name="fmc_lpc_la31_p"></pin> 
+    <pin index="274" name="fmc_lpc_la31_n"></pin> 
+    <pin index="276" name="fmc_lpc_la33_p"></pin> 
+    <pin index="277" name="fmc_lpc_la33_n"></pin> 
+	
+    <pin index="282" name="fmc_lpc_prsnt_m2c_b_ls"></pin> 
+    <pin index="284" name="fmc_lpc_clk0_m2c_p"></pin>
+    <pin index="285" name="fmc_lpc_clk0_m2c_n"></pin>
+	
+    <pin index="287" name="fmc_lpc_la02_p"></pin> 
+    <pin index="288" name="fmc_lpc_la02_n"></pin> 
+    <pin index="290" name="fmc_lpc_la04_p"></pin> 
+    <pin index="291" name="fmc_lpc_la04_n"></pin> 
+    <pin index="293" name="fmc_lpc_la07_p"></pin> 
+    <pin index="294" name="fmc_lpc_la07_n"></pin> 
+	
+    <pin index="296" name="fmc_lpc_la11_p"></pin> 
+    <pin index="297" name="fmc_lpc_la11_n"></pin> 
+    <pin index="299" name="fmc_lpc_la15_p"></pin> 
+    <pin index="300" name="fmc_lpc_la15_n"></pin> 
+    <pin index="302" name="fmc_lpc_la19_p"></pin> 
+    <pin index="303" name="fmc_lpc_la19_n"></pin> 
+    <pin index="305" name="fmc_lpc_la21_p"></pin> 
+    <pin index="306" name="fmc_lpc_la21_n"></pin> 
+    <pin index="308" name="fmc_lpc_la24_p"></pin> 
+    <pin index="309" name="fmc_lpc_la24_n"></pin> 
+    <pin index="311" name="fmc_lpc_la28_p"></pin> 
+    <pin index="312" name="fmc_lpc_la28_n"></pin> 
+    <pin index="314" name="fmc_lpc_la30_p"></pin> 
+    <pin index="315" name="fmc_lpc_la30_n"></pin> 
+    <pin index="317" name="fmc_lpc_la32_p"></pin> 
+    <pin index="318" name="fmc_lpc_la32_n"></pin> 
+  </pins>
+  </component>
+  
+  
+  
+  
+    <component name="part0" display_name="Zynq chip on board" type="fpga" part_name="xczu7ev-ffvc1156-2-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.xilinx.com/zcu104">
+      <description>FPGA part on the board</description>
+     
+
+	   <interfaces>
+	   
+        <interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset"> 
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
+          </preferred_ips>
+        </interface>
+		
+	    <interface mode="slave" name="clk_300mhz" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="clk_300mhz">
+          <parameters>
+            <parameter name="frequency" value="300000000"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="CLK_P" physical_port="CLK_300_P" dir="in">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="CLK_300_P"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="CLK_N" physical_port="CLK_300_N" dir="in">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="CLK_300_N"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+		
+	    <interface mode="master" name="uart2_pl" type="xilinx.com:interface:uart_rtl:1.0" of_component="uart2_pl" preset_proc="UART2_PL_Preset">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="TxD" physical_port="rs232_uart_txd" dir="out">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="uart2_PL_TX"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="RxD" physical_port="rs232_uart_rxd" dir="in">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="uart2_PL_RX"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+		
+	    <interface mode="master" name="iic1_pl" type="xilinx.com:interface:iic_rtl:1.0" of_component="iic1_pl">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="SDA_I" physical_port="iic1_main_sda_i" dir="inout">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="IIC1_SDA_MAIN"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="SDA_O" physical_port="iic1_main_sda_o" dir="inout">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="IIC1_SDA_MAIN"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="SDA_T" physical_port="iic1_main_sda_t" dir="inout">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="IIC1_SDA_MAIN"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="SCL_I" physical_port="iic1_main_scl_i" dir="inout">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="IIC1_SCL_MAIN"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="SCL_O" physical_port="iic1_main_scl_o" dir="inout">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="IIC1_SCL_MAIN"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="SCL_T" physical_port="iic1_main_scl_t" dir="inout">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="IIC1_SCL_MAIN"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+		
+		<interface mode="master" name="ddr4_sdram" type="xilinx.com:interface:ddr4_rtl:1.0" of_component="ddr4_sdram" preset_proc="DDR4_SDRAM_Preset">
+          <description>DDR4 board interface, it can use DDR4 controller IP for connection. </description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="ddr4" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="ACT_N" physical_port="c0_ddr4_act_n" dir="out">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_act_n"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="ADR" physical_port="c0_ddr4_adr" dir="out" left="16" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_adr0"/>
+                <pin_map port_index="1" component_pin="c0_ddr4_adr1"/>
+                <pin_map port_index="2" component_pin="c0_ddr4_adr2"/>
+                <pin_map port_index="3" component_pin="c0_ddr4_adr3"/>
+                <pin_map port_index="4" component_pin="c0_ddr4_adr4"/>
+                <pin_map port_index="5" component_pin="c0_ddr4_adr5"/>
+                <pin_map port_index="6" component_pin="c0_ddr4_adr6"/>
+                <pin_map port_index="7" component_pin="c0_ddr4_adr7"/>
+                <pin_map port_index="8" component_pin="c0_ddr4_adr8"/>
+                <pin_map port_index="9" component_pin="c0_ddr4_adr9"/>
+                <pin_map port_index="10" component_pin="c0_ddr4_adr10"/>
+                <pin_map port_index="11" component_pin="c0_ddr4_adr11"/>
+                <pin_map port_index="12" component_pin="c0_ddr4_adr12"/>
+                <pin_map port_index="13" component_pin="c0_ddr4_adr13"/>
+                <pin_map port_index="14" component_pin="c0_ddr4_adr14"/>
+                <pin_map port_index="15" component_pin="c0_ddr4_adr15"/>
+                <pin_map port_index="16" component_pin="c0_ddr4_adr16"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="BA" physical_port="c0_ddr4_ba" dir="out" left="1" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_ba0"/>
+                <pin_map port_index="1" component_pin="c0_ddr4_ba1"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="BG" physical_port="c0_ddr4_bg" dir="out" left="1" right="0"> 
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_bg0"/>
+				<pin_map port_index="1" component_pin="c0_ddr4_bg1"/>
+			  </pin_maps>
+            </port_map>
+            <port_map logical_port="CK_C" physical_port="c0_ddr4_ck_c" dir="out" > 
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_ck0_c"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="CK_T" physical_port="c0_ddr4_ck_t" dir="out" >
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_ck0_t"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="CKE" physical_port="c0_ddr4_cke" dir="out" >
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_cke0"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="CS_N" physical_port="c0_ddr4_cs_n" dir="out" >
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_cs0_n"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="DM_N" physical_port="c0_ddr4_dm_dbi_n" dir="inout" left="7" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_dm_dbi_n0"/>
+                <pin_map port_index="1" component_pin="c0_ddr4_dm_dbi_n1"/>
+				<pin_map port_index="2" component_pin="c0_ddr4_dm_dbi_n2"/>
+                <pin_map port_index="3" component_pin="c0_ddr4_dm_dbi_n3"/>
+				<pin_map port_index="4" component_pin="c0_ddr4_dm_dbi_n4"/>
+                <pin_map port_index="5" component_pin="c0_ddr4_dm_dbi_n5"/>
+				<pin_map port_index="6" component_pin="c0_ddr4_dm_dbi_n6"/>
+                <pin_map port_index="7" component_pin="c0_ddr4_dm_dbi_n7"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="DQ" physical_port="c0_ddr4_dq" dir="inout" left="63" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_dq0"/>
+                <pin_map port_index="1" component_pin="c0_ddr4_dq1"/>
+                <pin_map port_index="2" component_pin="c0_ddr4_dq2"/>
+                <pin_map port_index="3" component_pin="c0_ddr4_dq3"/>
+                <pin_map port_index="4" component_pin="c0_ddr4_dq4"/>
+                <pin_map port_index="5" component_pin="c0_ddr4_dq5"/>
+                <pin_map port_index="6" component_pin="c0_ddr4_dq6"/>
+                <pin_map port_index="7" component_pin="c0_ddr4_dq7"/>
+                <pin_map port_index="8" component_pin="c0_ddr4_dq8"/>
+                <pin_map port_index="9" component_pin="c0_ddr4_dq9"/>
+                <pin_map port_index="10" component_pin="c0_ddr4_dq10"/>
+                <pin_map port_index="11" component_pin="c0_ddr4_dq11"/>
+                <pin_map port_index="12" component_pin="c0_ddr4_dq12"/>
+                <pin_map port_index="13" component_pin="c0_ddr4_dq13"/>
+                <pin_map port_index="14" component_pin="c0_ddr4_dq14"/>
+                <pin_map port_index="15" component_pin="c0_ddr4_dq15"/>
+				
+                <pin_map port_index="16" component_pin="c0_ddr4_dq16"/>
+                <pin_map port_index="17" component_pin="c0_ddr4_dq17"/>
+                <pin_map port_index="18" component_pin="c0_ddr4_dq18"/>
+                <pin_map port_index="19" component_pin="c0_ddr4_dq19"/>
+                <pin_map port_index="20" component_pin="c0_ddr4_dq20"/>
+                <pin_map port_index="21" component_pin="c0_ddr4_dq21"/>
+                <pin_map port_index="22" component_pin="c0_ddr4_dq22"/>
+                <pin_map port_index="23" component_pin="c0_ddr4_dq23"/>
+                <pin_map port_index="24" component_pin="c0_ddr4_dq24"/>
+                <pin_map port_index="25" component_pin="c0_ddr4_dq25"/>
+                <pin_map port_index="26" component_pin="c0_ddr4_dq26"/>
+                <pin_map port_index="27" component_pin="c0_ddr4_dq27"/>
+                <pin_map port_index="28" component_pin="c0_ddr4_dq28"/>
+                <pin_map port_index="29" component_pin="c0_ddr4_dq29"/>
+                <pin_map port_index="30" component_pin="c0_ddr4_dq30"/>
+                <pin_map port_index="31" component_pin="c0_ddr4_dq31"/>	
+
+                <pin_map port_index="32" component_pin="c0_ddr4_dq32"/>
+                <pin_map port_index="33" component_pin="c0_ddr4_dq33"/>
+                <pin_map port_index="34" component_pin="c0_ddr4_dq34"/>
+                <pin_map port_index="35" component_pin="c0_ddr4_dq35"/>
+                <pin_map port_index="36" component_pin="c0_ddr4_dq36"/>
+                <pin_map port_index="37" component_pin="c0_ddr4_dq37"/>
+                <pin_map port_index="38" component_pin="c0_ddr4_dq38"/>
+                <pin_map port_index="39" component_pin="c0_ddr4_dq39"/>
+                <pin_map port_index="40" component_pin="c0_ddr4_dq40"/>
+                <pin_map port_index="41" component_pin="c0_ddr4_dq41"/>
+                <pin_map port_index="42" component_pin="c0_ddr4_dq42"/>
+                <pin_map port_index="43" component_pin="c0_ddr4_dq43"/>
+                <pin_map port_index="44" component_pin="c0_ddr4_dq44"/>
+                <pin_map port_index="45" component_pin="c0_ddr4_dq45"/>
+                <pin_map port_index="46" component_pin="c0_ddr4_dq46"/>
+                <pin_map port_index="47" component_pin="c0_ddr4_dq47"/>		
+
+                <pin_map port_index="48" component_pin="c0_ddr4_dq48"/>
+                <pin_map port_index="49" component_pin="c0_ddr4_dq49"/>
+                <pin_map port_index="50" component_pin="c0_ddr4_dq50"/>
+                <pin_map port_index="51" component_pin="c0_ddr4_dq51"/>
+                <pin_map port_index="52" component_pin="c0_ddr4_dq52"/>
+                <pin_map port_index="53" component_pin="c0_ddr4_dq53"/>
+                <pin_map port_index="54" component_pin="c0_ddr4_dq54"/>
+                <pin_map port_index="55" component_pin="c0_ddr4_dq55"/>
+                <pin_map port_index="56" component_pin="c0_ddr4_dq56"/>
+                <pin_map port_index="57" component_pin="c0_ddr4_dq57"/>
+                <pin_map port_index="58" component_pin="c0_ddr4_dq58"/>
+                <pin_map port_index="59" component_pin="c0_ddr4_dq59"/>
+                <pin_map port_index="60" component_pin="c0_ddr4_dq60"/>
+                <pin_map port_index="61" component_pin="c0_ddr4_dq61"/>
+                <pin_map port_index="62" component_pin="c0_ddr4_dq62"/>
+                <pin_map port_index="63" component_pin="c0_ddr4_dq63"/>						
+              </pin_maps>
+            </port_map>
+			
+            <port_map logical_port="DQS_C" physical_port="c0_ddr4_dqs_c" dir="inout" left="7" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_dqs0_c"/>
+                <pin_map port_index="1" component_pin="c0_ddr4_dqs1_c"/>
+				<pin_map port_index="2" component_pin="c0_ddr4_dqs2_c"/>
+                <pin_map port_index="3" component_pin="c0_ddr4_dqs3_c"/>
+				<pin_map port_index="4" component_pin="c0_ddr4_dqs4_c"/>
+                <pin_map port_index="5" component_pin="c0_ddr4_dqs5_c"/>
+				<pin_map port_index="6" component_pin="c0_ddr4_dqs6_c"/>
+                <pin_map port_index="7" component_pin="c0_ddr4_dqs7_c"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="DQS_T" physical_port="c0_ddr4_dqs_t" dir="out" left="7" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_dqs0_t"/>
+                <pin_map port_index="1" component_pin="c0_ddr4_dqs1_t"/>
+				<pin_map port_index="2" component_pin="c0_ddr4_dqs2_t"/>
+                <pin_map port_index="3" component_pin="c0_ddr4_dqs3_t"/>
+				<pin_map port_index="4" component_pin="c0_ddr4_dqs4_t"/>
+                <pin_map port_index="5" component_pin="c0_ddr4_dqs5_t"/>
+				<pin_map port_index="6" component_pin="c0_ddr4_dqs6_t"/>
+                <pin_map port_index="7" component_pin="c0_ddr4_dqs7_t"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="ODT" physical_port="c0_ddr4_odt" dir="out" >
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_odt0"/>
+              </pin_maps>
+            </port_map>
+            <port_map logical_port="RESET_N" physical_port="c0_ddr4_reset_n" dir="out">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="c0_ddr4_reset_n"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+		
+	    <interface mode="master" name="dip_switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switch_4bits" preset_proc="DIP_SWITCH_4Bits_Preset">
+          <description>4-Position User DIP Switch</description>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="TRI_I" physical_port="dip_switches_tri_i" dir="in" left="3" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="GPIO_DIP_SW0"/>
+                <pin_map port_index="1" component_pin="GPIO_DIP_SW1"/>
+                <pin_map port_index="2" component_pin="GPIO_DIP_SW2"/>
+                <pin_map port_index="3" component_pin="GPIO_DIP_SW3"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+		
+        <interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="LED_4Bits_Preset">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="TRI_O" physical_port="leds_8bits_tri_o" dir="out" left="3" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="GPIO_LED_0_LS"/>
+                <pin_map port_index="1" component_pin="GPIO_LED_1_LS"/>
+                <pin_map port_index="2" component_pin="GPIO_LED_2_LS"/>
+                <pin_map port_index="3" component_pin="GPIO_LED_3_LS"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+			
+	   <interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
+          <parameters>
+            <parameter name="rst_polarity" value="1"/>
+          </parameters>
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="RESET" physical_port="reset" dir="in">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="CPU_RESET"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+		
+        <interface mode="master" name="push_button_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_button_4bits" preset_proc="PUSH_BUTTON_4Bits_Preset">
+          <preferred_ips>
+            <preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
+          </preferred_ips>
+          <port_maps>
+            <port_map logical_port="TRI_I" physical_port="push_buttons_5bits_tri" dir="in" left="3" right="0">
+              <pin_maps>
+                <pin_map port_index="0" component_pin="GPIO_PB_SW0"/>
+                <pin_map port_index="1" component_pin="GPIO_PB_SW1"/>
+                <pin_map port_index="2" component_pin="GPIO_PB_SW2"/>
+                <pin_map port_index="3" component_pin="GPIO_PB_SW3"/>
+              </pin_maps>
+            </port_map>
+          </port_maps>
+        </interface>
+		
+       </interfaces>
+	   
+    </component>
+	
+    <component name="ps8_fixedio" display_name="PS8 fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
+	
+	<component name="clk_300mhz" display_name="Programmable Differential Clock (300MHz)" type="chip" sub_type="system_clock" major_group="Clock Sources" part_name="SI5341B" vendor="Silicon Labs" spec_url="www.silabs.com">
+      <description>SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock</description>
+      <parameters>
+        <parameter name="frequency" value="300000000"/>
+      </parameters>
+    </component>
+	
+    <component name="uart2_pl" display_name="UART" type="chip" sub_type="uart" major_group="Miscellaneous" part_name="CP2108" vendor="SiliconLabs">
+      <description>PL UART </description>
+      <pins>
+        <pin index="0" name="rs232_uart_txd" iostandard="LVCMOS18"/>
+        <pin index="1" name="rs232_uart_rxd" iostandard="LVCMOS18"/>
+      </pins>
+    </component>
+	
+	<component name="iic1_pl" display_name="PL IIC" type="chip" sub_type="mux" major_group="Miscellaneous">
+      <description>PL I2C</description>
+    </component>
+	    
+	
+    <component name="ddr4_sdram" display_name="DDR4 SDRAM" type="chip" sub_type="ddr" major_group="External Memory" part_name="MT40A256M16GE-075E" vendor="Micron" spec_url="https://www.micron.com/parts/dram/ddr4-sdram/mt40a256m16ge-075e">
+      <description>2GB DDR4 SDRAM memory SODIMM</description>
+      <parameters>
+        <parameter name="ddr_type" value="ddr4"/>
+        <parameter name="size" value="2GB"/>
+      </parameters>
+    </component>
+	
+    <component name="reset" display_name="FPGA Reset" type="chip" sub_type="system_reset" major_group="Reset" part_name="TL3301EP100QG" vendor="ESwitch">
+      <description>CPU Reset Push Button, Active High</description>
+    </component>
+	
+    <component name="dip_switch_4bits" display_name="DIP switches" type="chip" sub_type="switch" major_group="General Purpose Input or Output" part_name="SDA05H1SBD" vendor="CandK" spec_url="www.ck-components.com">
+      <description>DIP Switches 3 to 0</description>
+    </component>
+
+    <component name="led_4bits" display_name="LED" type="chip" sub_type="led" major_group="General Purpose Input or Output">
+      <description>LEDs, 3 to 0, Active High</description>
+    </component>
+
+    <component name="push_button_4bits" display_name="Push buttons" type="chip" sub_type="push_button" major_group="General Purpose Input or Output" part_name="TL3301EP100QG" vendor="ESwitch">
+      <description>Push Buttons, 3 to 0, Active High</description>
+    </component>
+	
+    </components>
+	
+	<jtag_chains>
+		<jtag_chain name="chain1">
+		  <position name="0" component="part0"/>
+		</jtag_chain>
+	</jtag_chains>
+  
+  
+  <connections>
+  
+  	<connection name="Part0_CLK_300MZ" component1="part0" component2="clk_300mhz">
+		  <connection_map name="Part0_CLK_300MZ_1" typical_delay="5" c1_st_index="0" c1_end_index="1" c2_st_index="0" c2_end_index="1"/>
+	</connection>
+	
+	<connection name="Part0_UART2_PL" component1="part0" component2="uart2_pl">
+      <connection_map name="Part0_UART2_PL_1" typical_delay="5" c1_st_index="2" c1_end_index="3" c2_st_index="0" c2_end_index="1"/>
+    </connection>
+	
+	<connection name="Part0_iic0_pl" component1="part0" component2="iic1_pl">
+      <connection_map name="Part0_iic0_pl_1" typical_delay="5" c1_st_index="4" c1_end_index="5" c2_st_index="0" c2_end_index="1"/>
+    </connection>
+
+    
+	<connection name="Part0_DDR4_SDRAM" component1="part0" component2="ddr4_sdram">
+      <connection_map name="Part0_DDR4_SDRAM_1" typical_delay="5" c1_st_index="6" c1_end_index="126" c2_st_index="0" c2_end_index="120"/>
+    </connection>
+    
+	<connection name="Part0_reset" component1="part0" component2="reset">
+      <connection_map name="Part0_reset_1" typical_delay="5" c1_st_index="127" c1_end_index="127" component2="reset" c2_st_index="0" c2_end_index="0"/>
+    </connection>
+	
+   
+	<connection name="Part0_DIP_SWITCH_4Bits" component1="part0" component2="dip_switch_4bits">
+      <connection_map name="Part0_DIP_SWITCH_4Bits_1" typical_delay="5" c1_st_index="128" c1_end_index="131" c2_st_index="0" c2_end_index="3"/>
+    </connection>
+    
+	<connection name="Part0_LED_4Bits" component1="part0" component2="led_4bits">
+      <connection_map name="Part0_LED_4Bits_1" typical_delay="5" c1_st_index="132" c1_end_index="135" c2_st_index="0" c2_end_index="3"/>
+    </connection>
+    
+	<connection name="Part0_PUSH_BUTTON_4Bits" component1="part0" component2="push_button_4bits">
+      <connection_map name="Part0_PUSH_BUTTON_4Bits_1" typical_delay="5" c1_st_index="136" c1_end_index="139" c2_st_index="0" c2_end_index="3"/>
+    </connection>
+	
+	
+	<connection name="part0_fmc_lpc" component1="part0" component2="fmc_lpc_connector">
+		<connection_map name="part0_fmc_lpc_la00_cc_n" c1_st_index="140" c1_end_index="140" c2_st_index="247" c2_end_index="247" />
+		<connection_map name="part0_fmc_lpc_la00_cc_p" c1_st_index="141" c1_end_index="141" c2_st_index="246" c2_end_index="246" />
+		<connection_map name="part0_fmc_lpc_la01_cc_n" c1_st_index="142" c1_end_index="142" c2_st_index="129" c2_end_index="129" />
+		<connection_map name="part0_fmc_lpc_la01_cc_p" c1_st_index="143" c1_end_index="143" c2_st_index="128" c2_end_index="128" />
+		
+		<connection_map name="part0_fmc_lpc_la02_n" c1_st_index="144" c1_end_index="144" c2_st_index="288" c2_end_index="288" />
+		<connection_map name="part0_fmc_lpc_la02_p" c1_st_index="145" c1_end_index="145" c2_st_index="287" c2_end_index="287" />
+		<connection_map name="part0_fmc_lpc_la03_n" c1_st_index="146" c1_end_index="146" c2_st_index="250" c2_end_index="250" />
+		<connection_map name="part0_fmc_lpc_la03_p" c1_st_index="147" c1_end_index="147" c2_st_index="249" c2_end_index="249" />		
+		<connection_map name="part0_fmc_lpc_la04_n" c1_st_index="148" c1_end_index="148" c2_st_index="291" c2_end_index="291" />
+		<connection_map name="part0_fmc_lpc_la04_p" c1_st_index="149" c1_end_index="149" c2_st_index="290" c2_end_index="290" />
+		<connection_map name="part0_fmc_lpc_la05_n" c1_st_index="150" c1_end_index="150" c2_st_index="132" c2_end_index="132" />
+		<connection_map name="part0_fmc_lpc_la05_p" c1_st_index="151" c1_end_index="151" c2_st_index="131" c2_end_index="131" />		
+		<connection_map name="part0_fmc_lpc_la06_n" c1_st_index="152" c1_end_index="152" c2_st_index="91" c2_end_index="91" />
+		<connection_map name="part0_fmc_lpc_la06_p" c1_st_index="153" c1_end_index="153" c2_st_index="90" c2_end_index="90" />
+		<connection_map name="part0_fmc_lpc_la07_n" c1_st_index="154" c1_end_index="154" c2_st_index="294" c2_end_index="294" />
+		<connection_map name="part0_fmc_lpc_la07_p" c1_st_index="155" c1_end_index="155" c2_st_index="293" c2_end_index="293" />		
+		<connection_map name="part0_fmc_lpc_la08_n" c1_st_index="156" c1_end_index="156" c2_st_index="253" c2_end_index="253" />
+		<connection_map name="part0_fmc_lpc_la08_p" c1_st_index="157" c1_end_index="157" c2_st_index="252" c2_end_index="252" />
+		<connection_map name="part0_fmc_lpc_la09_n" c1_st_index="158" c1_end_index="158" c2_st_index="135" c2_end_index="135" />
+		<connection_map name="part0_fmc_lpc_la09_p" c1_st_index="159" c1_end_index="159" c2_st_index="134" c2_end_index="134" />		
+		<connection_map name="part0_fmc_lpc_la10_n" c1_st_index="160" c1_end_index="160" c2_st_index="95" c2_end_index="95" />
+		<connection_map name="part0_fmc_lpc_la10_p" c1_st_index="161" c1_end_index="161" c2_st_index="94" c2_end_index="94" />
+		<connection_map name="part0_fmc_lpc_la11_n" c1_st_index="162" c1_end_index="162" c2_st_index="297" c2_end_index="297" />
+		<connection_map name="part0_fmc_lpc_la11_p" c1_st_index="163" c1_end_index="163" c2_st_index="296" c2_end_index="296" />		
+		<connection_map name="part0_fmc_lpc_la12_n" c1_st_index="164" c1_end_index="164" c2_st_index="256" c2_end_index="256" />
+		<connection_map name="part0_fmc_lpc_la12_p" c1_st_index="165" c1_end_index="165" c2_st_index="255" c2_end_index="255" />
+		<connection_map name="part0_fmc_lpc_la13_n" c1_st_index="166" c1_end_index="166" c2_st_index="138" c2_end_index="138" />
+		<connection_map name="part0_fmc_lpc_la13_p" c1_st_index="167" c1_end_index="167" c2_st_index="137" c2_end_index="137" />		
+		<connection_map name="part0_fmc_lpc_la14_n" c1_st_index="168" c1_end_index="168" c2_st_index="99" c2_end_index="99" />
+		<connection_map name="part0_fmc_lpc_la14_p" c1_st_index="169" c1_end_index="169" c2_st_index="98" c2_end_index="98" />
+		<connection_map name="part0_fmc_lpc_la15_n" c1_st_index="170" c1_end_index="170" c2_st_index="300" c2_end_index="300" />
+		<connection_map name="part0_fmc_lpc_la15_p" c1_st_index="171" c1_end_index="171" c2_st_index="299" c2_end_index="299" />		
+		<connection_map name="part0_fmc_lpc_la16_n" c1_st_index="172" c1_end_index="172" c2_st_index="259" c2_end_index="259" />
+		<connection_map name="part0_fmc_lpc_la16_p" c1_st_index="173" c1_end_index="173" c2_st_index="258" c2_end_index="258" />
+		
+		<connection_map name="part0_fmc_lpc_la17_cc_n" c1_st_index="174" c1_end_index="174" c2_st_index="141" c2_end_index="141" />
+		<connection_map name="part0_fmc_lpc_la17_cc_p" c1_st_index="175" c1_end_index="175" c2_st_index="140" c2_end_index="140" />		
+		<connection_map name="part0_fmc_lpc_la18_cc_n" c1_st_index="176" c1_end_index="176" c2_st_index="103" c2_end_index="103" />
+		<connection_map name="part0_fmc_lpc_la18_cc_p" c1_st_index="177" c1_end_index="177" c2_st_index="102" c2_end_index="102" />	
+
+		<connection_map name="part0_fmc_lpc_la19_n" c1_st_index="178" c1_end_index="178" c2_st_index="303" c2_end_index="303" />
+		<connection_map name="part0_fmc_lpc_la19_p" c1_st_index="179" c1_end_index="179" c2_st_index="302" c2_end_index="302" />		
+		<connection_map name="part0_fmc_lpc_la20_n" c1_st_index="180" c1_end_index="180" c2_st_index="262" c2_end_index="262" />
+		<connection_map name="part0_fmc_lpc_la20_p" c1_st_index="181" c1_end_index="181" c2_st_index="261" c2_end_index="261" />
+		<connection_map name="part0_fmc_lpc_la21_n" c1_st_index="182" c1_end_index="182" c2_st_index="306" c2_end_index="306" />
+		<connection_map name="part0_fmc_lpc_la21_p" c1_st_index="183" c1_end_index="183" c2_st_index="305" c2_end_index="305" />		
+		<connection_map name="part0_fmc_lpc_la22_n" c1_st_index="184" c1_end_index="184" c2_st_index="265" c2_end_index="265" />
+		<connection_map name="part0_fmc_lpc_la22_p" c1_st_index="185" c1_end_index="185" c2_st_index="264" c2_end_index="264" />
+		<connection_map name="part0_fmc_lpc_la23_n" c1_st_index="186" c1_end_index="186" c2_st_index="144" c2_end_index="144" />
+		<connection_map name="part0_fmc_lpc_la23_p" c1_st_index="187" c1_end_index="187" c2_st_index="143" c2_end_index="143" />		
+		<connection_map name="part0_fmc_lpc_la24_n" c1_st_index="188" c1_end_index="188" c2_st_index="309" c2_end_index="309" />
+		<connection_map name="part0_fmc_lpc_la24_p" c1_st_index="189" c1_end_index="189" c2_st_index="308" c2_end_index="308" />		
+		<connection_map name="part0_fmc_lpc_la25_n" c1_st_index="190" c1_end_index="190" c2_st_index="268" c2_end_index="268" />
+		<connection_map name="part0_fmc_lpc_la25_p" c1_st_index="191" c1_end_index="191" c2_st_index="267" c2_end_index="267" />		
+		<connection_map name="part0_fmc_lpc_la26_n" c1_st_index="192" c1_end_index="192" c2_st_index="147" c2_end_index="147" />
+		<connection_map name="part0_fmc_lpc_la26_p" c1_st_index="193" c1_end_index="193" c2_st_index="146" c2_end_index="146" />
+		<connection_map name="part0_fmc_lpc_la27_n" c1_st_index="194" c1_end_index="194" c2_st_index="107" c2_end_index="107" />
+		<connection_map name="part0_fmc_lpc_la27_p" c1_st_index="195" c1_end_index="195" c2_st_index="106" c2_end_index="106" />		
+		<connection_map name="part0_fmc_lpc_la28_n" c1_st_index="196" c1_end_index="196" c2_st_index="312" c2_end_index="312" />
+		<connection_map name="part0_fmc_lpc_la28_p" c1_st_index="197" c1_end_index="197" c2_st_index="311" c2_end_index="311" />
+		<connection_map name="part0_fmc_lpc_la29_n" c1_st_index="198" c1_end_index="198" c2_st_index="271" c2_end_index="271" />
+		<connection_map name="part0_fmc_lpc_la29_p" c1_st_index="199" c1_end_index="199" c2_st_index="270" c2_end_index="270" />		
+		<connection_map name="part0_fmc_lpc_la30_n" c1_st_index="200" c1_end_index="200" c2_st_index="315" c2_end_index="315" />
+		<connection_map name="part0_fmc_lpc_la30_p" c1_st_index="201" c1_end_index="201" c2_st_index="314" c2_end_index="314" />		
+		<connection_map name="part0_fmc_lpc_la31_n" c1_st_index="202" c1_end_index="202" c2_st_index="274" c2_end_index="274" />
+		<connection_map name="part0_fmc_lpc_la31_p" c1_st_index="203" c1_end_index="203" c2_st_index="273" c2_end_index="273" />		
+		<connection_map name="part0_fmc_lpc_la32_n" c1_st_index="204" c1_end_index="204" c2_st_index="318" c2_end_index="318" />
+		<connection_map name="part0_fmc_lpc_la32_p" c1_st_index="205" c1_end_index="205" c2_st_index="317" c2_end_index="317" />
+		<connection_map name="part0_fmc_lpc_la33_n" c1_st_index="206" c1_end_index="206" c2_st_index="277" c2_end_index="277" />
+		<connection_map name="part0_fmc_lpc_la33_p" c1_st_index="207" c1_end_index="207" c2_st_index="276" c2_end_index="276" />		
+		<connection_map name="part0_fmc_lpc_clk0_m2c_n" c1_st_index="208" c1_end_index="208" c2_st_index="285" c2_end_index="285" />		
+		<connection_map name="part0_fmc_lpc_clk0_m2c_p" c1_st_index="209" c1_end_index="209" c2_st_index="284" c2_end_index="284" />		
+		
+    </connection>		
+
+  </connections>
+
+  
+  <ip_associated_rules>
+	  <ip_associated_rule name="default">
+		<ip vendor="xilinx.com" library="ip" name="ddr4" version="*" ip_interface="C0_SYS_CLK">
+		  <associated_board_interfaces>
+		<associated_board_interface name="clk_300mhz" order="0"/> 
+		  </associated_board_interfaces>
+		</ip>
+	  </ip_associated_rule>
+ </ip_associated_rules>
+
+
+</board>
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/part0_pins.xml b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/part0_pins.xml
new file mode 100644
index 00000000..e5d6301c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/part0_pins.xml
@@ -0,0 +1,228 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> 
+<part_info part_name="xczu7ev-ffvc1156-2-e">
+<pins>
+  <pin index="0" name ="CLK_300_P" iostandard="DIFF_SSTL12" loc="AH18"/>
+  <pin index="1" name ="CLK_300_N" iostandard="DIFF_SSTL12" loc="AH17"/>
+  
+  <pin index="2" name ="uart2_PL_TX" loc="C19"/>
+  <pin index="3" name ="uart2_PL_RX" loc="A20"/>
+  
+  <pin index="4" name ="IIC1_SCL_MAIN" iostandard="LVCMOS33" loc="N12"/>
+  <pin index="5" name ="IIC1_SDA_MAIN" iostandard="LVCMOS33" loc="P12"/>
+  
+  <pin index="6" name ="c0_ddr4_act_n" iostandard="SSTL12_DCI" loc="AC17" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="7" name ="c0_ddr4_adr0" iostandard="SSTL12_DCI" loc="AH16" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="8" name ="c0_ddr4_adr1" iostandard="SSTL12_DCI" loc="AG14" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="9" name ="c0_ddr4_adr2" iostandard="SSTL12_DCI" loc="AG15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="10" name ="c0_ddr4_adr3" iostandard="SSTL12_DCI" loc="AF15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="11" name ="c0_ddr4_adr4" iostandard="SSTL12_DCI" loc="AF16" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="12" name ="c0_ddr4_adr5" iostandard="SSTL12_DCI" loc="AJ14" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="13" name ="c0_ddr4_adr6" iostandard="SSTL12_DCI" loc="AH14" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="14" name ="c0_ddr4_adr7" iostandard="SSTL12_DCI" loc="AF17" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="15" name ="c0_ddr4_adr8" iostandard="SSTL12_DCI" loc="AK17" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="16" name ="c0_ddr4_adr9" iostandard="SSTL12_DCI" loc="AJ17" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="17" name ="c0_ddr4_adr10" iostandard="SSTL12_DCI" loc="AK14" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="18" name ="c0_ddr4_adr11" iostandard="SSTL12_DCI" loc="AK15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="19" name ="c0_ddr4_adr12" iostandard="SSTL12_DCI" loc="AL18" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="20" name ="c0_ddr4_adr13" iostandard="SSTL12_DCI" loc="AK18" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="21" name ="c0_ddr4_adr14" iostandard="SSTL12_DCI" loc="AA16" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="22" name ="c0_ddr4_adr15" iostandard="SSTL12_DCI" loc="AA14" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="23" name ="c0_ddr4_adr16" iostandard="SSTL12_DCI" loc="AD15" output_impedance="RDRV_40_40" slew="FAST"/> 
+  
+  <pin index="24" name ="c0_ddr4_ba0" iostandard="SSTL12_DCI" loc="AL15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="25" name ="c0_ddr4_ba1" iostandard="SSTL12_DCI" loc="AL16" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="26" name ="c0_ddr4_bg0" iostandard="SSTL12_DCI" loc="AC16" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="27" name ="c0_ddr4_bg1" iostandard="SSTL12_DCI" loc="AB16" output_impedance="RDRV_40_40" slew="FAST"/>
+  
+  <pin index="28" name ="c0_ddr4_ck0_t" iostandard="DIFF_SSTL12_DCI" loc="AF18" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="29" name ="c0_ddr4_ck0_c" iostandard="DIFF_SSTL12_DCI" loc="AG18" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="30" name ="c0_ddr4_ck1_t" iostandard="DIFF_SSTL12_DCI" loc="AJ16" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="31" name ="c0_ddr4_ck1_c" iostandard="DIFF_SSTL12_DCI" loc="AJ15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="32" name ="c0_ddr4_cke0" iostandard="SSTL12_DCI" loc="AD17" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="33" name ="c0_ddr4_cke1" iostandard="SSTL12_DCI" loc="AM15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="34" name ="c0_ddr4_cs0_n" iostandard="SSTL12_DCI" loc="AA15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="35" name ="c0_ddr4_cs1_n" iostandard="SSTL12_DCI" loc="AL17" output_impedance="RDRV_40_40" slew="FAST"/>
+  
+  <pin index="36" name ="c0_ddr4_dm_dbi_n0" iostandard="POD12_DCI" loc="AH22" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="37" name ="c0_ddr4_dm_dbi_n1" iostandard="POD12_DCI" loc="AE18" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="38" name ="c0_ddr4_dm_dbi_n2" iostandard="POD12_DCI" loc="AL20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="39" name ="c0_ddr4_dm_dbi_n3" iostandard="POD12_DCI" loc="AP19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="40" name ="c0_ddr4_dm_dbi_n4" iostandard="POD12_DCI" loc="AF11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="41" name ="c0_ddr4_dm_dbi_n5" iostandard="POD12_DCI" loc="AH12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="42" name ="c0_ddr4_dm_dbi_n6" iostandard="POD12_DCI" loc="AK13" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="43" name ="c0_ddr4_dm_dbi_n7" iostandard="POD12_DCI" loc="AN12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="44" name ="c0_ddr4_dq0" iostandard="POD12_DCI" loc="AE24" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="45" name ="c0_ddr4_dq1" iostandard="POD12_DCI" loc="AE23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="46" name ="c0_ddr4_dq2" iostandard="POD12_DCI" loc="AF22" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="47" name ="c0_ddr4_dq3" iostandard="POD12_DCI" loc="AF21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="48" name ="c0_ddr4_dq4" iostandard="POD12_DCI" loc="AG20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="49" name ="c0_ddr4_dq5" iostandard="POD12_DCI" loc="AG19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="50" name ="c0_ddr4_dq6" iostandard="POD12_DCI" loc="AH21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="51" name ="c0_ddr4_dq7" iostandard="POD12_DCI" loc="AG21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="52" name ="c0_ddr4_dq8" iostandard="POD12_DCI" loc="AA20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="53" name ="c0_ddr4_dq9" iostandard="POD12_DCI" loc="AA19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="54" name ="c0_ddr4_dq10" iostandard="POD12_DCI" loc="AD19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="55" name ="c0_ddr4_dq11" iostandard="POD12_DCI" loc="AC18" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="56" name ="c0_ddr4_dq12" iostandard="POD12_DCI" loc="AE20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="57" name ="c0_ddr4_dq13" iostandard="POD12_DCI" loc="AD20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="58" name ="c0_ddr4_dq14" iostandard="POD12_DCI" loc="AC19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="59" name ="c0_ddr4_dq15" iostandard="POD12_DCI" loc="AB19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="60" name ="c0_ddr4_dq16" iostandard="POD12_DCI" loc="AJ22" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="61" name ="c0_ddr4_dq17" iostandard="POD12_DCI" loc="AJ21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="62" name ="c0_ddr4_dq18" iostandard="POD12_DCI" loc="AK20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="63" name ="c0_ddr4_dq19" iostandard="POD12_DCI" loc="AJ20" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="64" name ="c0_ddr4_dq20" iostandard="POD12_DCI" loc="AK19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="65" name ="c0_ddr4_dq21" iostandard="POD12_DCI" loc="AJ19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="66" name ="c0_ddr4_dq22" iostandard="POD12_DCI" loc="AL23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="67" name ="c0_ddr4_dq23" iostandard="POD12_DCI" loc="AL22" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="68" name ="c0_ddr4_dq24" iostandard="POD12_DCI" loc="AN23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="69" name ="c0_ddr4_dq25" iostandard="POD12_DCI" loc="AM23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="70" name ="c0_ddr4_dq26" iostandard="POD12_DCI" loc="AP23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="71" name ="c0_ddr4_dq27" iostandard="POD12_DCI" loc="AN22" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="72" name ="c0_ddr4_dq28" iostandard="POD12_DCI" loc="AP22" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="73" name ="c0_ddr4_dq29" iostandard="POD12_DCI" loc="AP21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="74" name ="c0_ddr4_dq30" iostandard="POD12_DCI" loc="AN19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="75" name ="c0_ddr4_dq31" iostandard="POD12_DCI" loc="AM19" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>  
+  <pin index="76" name ="c0_ddr4_dq32" iostandard="POD12_DCI" loc="AC13" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="77" name ="c0_ddr4_dq33" iostandard="POD12_DCI" loc="AB13" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="78" name ="c0_ddr4_dq34" iostandard="POD12_DCI" loc="AF12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="79" name ="c0_ddr4_dq35" iostandard="POD12_DCI" loc="AE12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="80" name ="c0_ddr4_dq36" iostandard="POD12_DCI" loc="AF13" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="81" name ="c0_ddr4_dq37" iostandard="POD12_DCI" loc="AE13" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="82" name ="c0_ddr4_dq38" iostandard="POD12_DCI" loc="AE14" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="83" name ="c0_ddr4_dq39" iostandard="POD12_DCI" loc="AD14" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="84" name ="c0_ddr4_dq40" iostandard="POD12_DCI" loc="AG8" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="85" name ="c0_ddr4_dq41" iostandard="POD12_DCI" loc="AF8" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="86" name ="c0_ddr4_dq42" iostandard="POD12_DCI" loc="AG10" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="87" name ="c0_ddr4_dq43" iostandard="POD12_DCI" loc="AG11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="88" name ="c0_ddr4_dq44" iostandard="POD12_DCI" loc="AH13" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="89" name ="c0_ddr4_dq45" iostandard="POD12_DCI" loc="AG13" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="90" name ="c0_ddr4_dq46" iostandard="POD12_DCI" loc="AJ11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="91" name ="c0_ddr4_dq47" iostandard="POD12_DCI" loc="AH11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="92" name ="c0_ddr4_dq48" iostandard="POD12_DCI" loc="AK9" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="93" name ="c0_ddr4_dq49" iostandard="POD12_DCI" loc="AJ9" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="94" name ="c0_ddr4_dq50" iostandard="POD12_DCI" loc="AK10" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="95" name ="c0_ddr4_dq51" iostandard="POD12_DCI" loc="AJ10" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="96" name ="c0_ddr4_dq52" iostandard="POD12_DCI" loc="AL12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="97" name ="c0_ddr4_dq53" iostandard="POD12_DCI" loc="AK12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="98" name ="c0_ddr4_dq54" iostandard="POD12_DCI" loc="AL10" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="99" name ="c0_ddr4_dq55" iostandard="POD12_DCI" loc="AL11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  
+  <pin index="100" name ="c0_ddr4_dq56" iostandard="POD12_DCI" loc="AM8" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="101" name ="c0_ddr4_dq57" iostandard="POD12_DCI" loc="AM9" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="102" name ="c0_ddr4_dq58" iostandard="POD12_DCI" loc="AM10" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="103" name ="c0_ddr4_dq59" iostandard="POD12_DCI" loc="AM11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="104" name ="c0_ddr4_dq60" iostandard="POD12_DCI" loc="AP11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="105" name ="c0_ddr4_dq61" iostandard="POD12_DCI" loc="AN11" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="106" name ="c0_ddr4_dq62" iostandard="POD12_DCI" loc="AP9" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="107" name ="c0_ddr4_dq63" iostandard="POD12_DCI" loc="AP10" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="108" name ="c0_ddr4_dqs0_c" iostandard="DIFF_POD12_DCI" loc="AG23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="109" name ="c0_ddr4_dqs0_t" iostandard="DIFF_POD12_DCI" loc="AF23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="110" name ="c0_ddr4_dqs1_c" iostandard="DIFF_POD12_DCI" loc="AB18" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="111" name ="c0_ddr4_dqs1_t" iostandard="DIFF_POD12_DCI" loc="AA18" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="112" name ="c0_ddr4_dqs2_c" iostandard="DIFF_POD12_DCI" loc="AK23" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="113" name ="c0_ddr4_dqs2_t" iostandard="DIFF_POD12_DCI" loc="AK22" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="114" name ="c0_ddr4_dqs3_c" iostandard="DIFF_POD12_DCI" loc="AN21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="115" name ="c0_ddr4_dqs3_t" iostandard="DIFF_POD12_DCI" loc="AM21" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/> 
+  <pin index="116" name ="c0_ddr4_dqs4_c" iostandard="DIFF_POD12_DCI" loc="AD12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="117" name ="c0_ddr4_dqs4_t" iostandard="DIFF_POD12_DCI" loc="AC12" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>  
+  <pin index="118" name ="c0_ddr4_dqs5_c" iostandard="DIFF_POD12_DCI" loc="AH9" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="119" name ="c0_ddr4_dqs5_t" iostandard="DIFF_POD12_DCI" loc="AG9" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="120" name ="c0_ddr4_dqs6_c" iostandard="DIFF_POD12_DCI" loc="AL8" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="121" name ="c0_ddr4_dqs6_t" iostandard="DIFF_POD12_DCI" loc="AK8" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="122" name ="c0_ddr4_dqs7_c" iostandard="DIFF_POD12_DCI" loc="AN8" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="123" name ="c0_ddr4_dqs7_t" iostandard="DIFF_POD12_DCI" loc="AN9" output_impedance="RDRV_40_40" slew="FAST" ibuf_low_pwr="FALSE" odt="RTT_40" equalization="EQ_LEVEL2" pre_emphasis="RDRV_240"/>
+  <pin index="124" name ="c0_ddr4_odt0" iostandard="SSTL12_DCI" loc="AE15" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="125" name ="c0_ddr4_odt1" iostandard="SSTL12_DCI" loc="AM16" output_impedance="RDRV_40_40" slew="FAST"/>
+  <pin index="126" name ="c0_ddr4_reset_n" iostandard="LVCMOS12" loc="AB14" DRIVE="8"/>
+  
+ 
+  <pin index="127" name ="CPU_RESET" iostandard="LVCMOS33" loc="M11"/>	
+  <pin index="128" name ="GPIO_DIP_SW0" iostandard="LVCMOS33" loc="E4"/>
+  <pin index="129" name ="GPIO_DIP_SW1" iostandard="LVCMOS33" loc="D4"/>
+  <pin index="130" name ="GPIO_DIP_SW2" iostandard="LVCMOS33" loc="F5"/>
+  <pin index="131" name ="GPIO_DIP_SW3" iostandard="LVCMOS33" loc="F4"/>
+  <pin index="132" name ="GPIO_LED_0_LS" iostandard="LVCMOS33" loc="D5"/>
+  <pin index="133" name ="GPIO_LED_1_LS" iostandard="LVCMOS33" loc="D6"/>
+  <pin index="134" name ="GPIO_LED_2_LS" iostandard="LVCMOS33" loc="A5"/>
+  <pin index="135" name ="GPIO_LED_3_LS" iostandard="LVCMOS33" loc="B5"/>
+  <pin index="136" name ="GPIO_PB_SW0" iostandard="LVCMOS33" loc="B4"/>		
+  <pin index="137" name ="GPIO_PB_SW1" iostandard="LVCMOS33" loc="C4"/>
+  <pin index="138" name ="GPIO_PB_SW2" iostandard="LVCMOS33" loc="B3"/>
+  <pin index="139" name ="GPIO_PB_SW3" iostandard="LVCMOS33" loc="C3"/>
+    
+    <pin index="140" name="fmc_lpc_la00_cc_n" iostandard="LVCMOS18" loc="F16"/>
+    <pin index="141" name="fmc_lpc_la00_cc_p" iostandard="LVCMOS18" loc="F17"/>
+    <pin index="142" name="fmc_lpc_la01_cc_n" iostandard="LVCMOS18" loc="H17"/>
+    <pin index="143" name="fmc_lpc_la01_cc_p" iostandard="LVCMOS18" loc="H18"/>	
+    <pin index="144" name="fmc_lpc_la02_n" iostandard="LVCMOS18" loc="K20"/>
+    <pin index="145" name="fmc_lpc_la02_p" iostandard="LVCMOS18" loc="L20"/>	
+    <pin index="146" name="fmc_lpc_la03_n" iostandard="LVCMOS18" loc="K18"/>
+    <pin index="147" name="fmc_lpc_la03_p" iostandard="LVCMOS18" loc="K19"/>	
+    <pin index="148" name="fmc_lpc_la04_n" iostandard="LVCMOS18" loc="L16"/>
+    <pin index="149" name="fmc_lpc_la04_p" iostandard="LVCMOS18" loc="L17"/>	
+    <pin index="150" name="fmc_lpc_la05_n" iostandard="LVCMOS18" loc="J17"/>
+    <pin index="151" name="fmc_lpc_la05_p" iostandard="LVCMOS18" loc="K17"/>	
+    <pin index="152" name="fmc_lpc_la06_n" iostandard="LVCMOS18" loc="G19"/>
+    <pin index="153" name="fmc_lpc_la06_p" iostandard="LVCMOS18" loc="H19"/>	
+    <pin index="154" name="fmc_lpc_la07_n" iostandard="LVCMOS18" loc="J15"/>
+    <pin index="155" name="fmc_lpc_la07_p" iostandard="LVCMOS18" loc="J16"/>
+    <pin index="156" name="fmc_lpc_la08_n" iostandard="LVCMOS18" loc="E17"/>
+    <pin index="157" name="fmc_lpc_la08_p" iostandard="LVCMOS18" loc="E18"/>	
+    <pin index="158" name="fmc_lpc_la09_n" iostandard="LVCMOS18" loc="G16"/>
+    <pin index="159" name="fmc_lpc_la09_p" iostandard="LVCMOS18" loc="H16"/>
+    <pin index="160" name="fmc_lpc_la10_n" iostandard="LVCMOS18" loc="K15"/>
+    <pin index="161" name="fmc_lpc_la10_p" iostandard="LVCMOS18" loc="L15"/>
+    <pin index="162" name="fmc_lpc_la11_n" iostandard="LVCMOS18" loc="A12"/>
+    <pin index="163" name="fmc_lpc_la11_p" iostandard="LVCMOS18" loc="A13"/>
+    <pin index="164" name="fmc_lpc_la12_n" iostandard="LVCMOS18" loc="F18"/>
+    <pin index="165" name="fmc_lpc_la12_p" iostandard="LVCMOS18" loc="G18"/>
+    <pin index="166" name="fmc_lpc_la13_n" iostandard="LVCMOS18" loc="F15"/>
+    <pin index="167" name="fmc_lpc_la13_p" iostandard="LVCMOS18" loc="G15"/>
+    <pin index="168" name="fmc_lpc_la14_n" iostandard="LVCMOS18" loc="C12"/>
+    <pin index="169" name="fmc_lpc_la14_p" iostandard="LVCMOS18" loc="C13"/>
+    <pin index="170" name="fmc_lpc_la15_n" iostandard="LVCMOS18" loc="C16"/>
+    <pin index="171" name="fmc_lpc_la15_p" iostandard="LVCMOS18" loc="D16"/>
+    <pin index="172" name="fmc_lpc_la16_n" iostandard="LVCMOS18" loc="C17"/>
+    <pin index="173" name="fmc_lpc_la16_p" iostandard="LVCMOS18" loc="D17"/>	
+    <pin index="174" name="fmc_lpc_la17_cc_n" iostandard="LVCMOS18" loc="E10"/>
+    <pin index="175" name="fmc_lpc_la17_cc_p" iostandard="LVCMOS18" loc="F11"/>
+    <pin index="176" name="fmc_lpc_la18_cc_n" iostandard="LVCMOS18" loc="D10"/>
+    <pin index="177" name="fmc_lpc_la18_cc_p" iostandard="LVCMOS18" loc="D11"/>	
+    <pin index="178" name="fmc_lpc_la19_n" iostandard="LVCMOS18" loc="C11"/>
+    <pin index="179" name="fmc_lpc_la19_p" iostandard="LVCMOS18" loc="D12"/>
+    <pin index="180" name="fmc_lpc_la20_n" iostandard="LVCMOS18" loc="E12"/>
+    <pin index="181" name="fmc_lpc_la20_p" iostandard="LVCMOS18" loc="F12"/>	
+    <pin index="182" name="fmc_lpc_la21_n" iostandard="LVCMOS18" loc="A10"/>
+    <pin index="183" name="fmc_lpc_la21_p" iostandard="LVCMOS18" loc="B10"/>
+    <pin index="184" name="fmc_lpc_la22_n" iostandard="LVCMOS18" loc="H12"/>
+    <pin index="185" name="fmc_lpc_la22_p" iostandard="LVCMOS18" loc="H13"/>
+    <pin index="186" name="fmc_lpc_la23_n" iostandard="LVCMOS18" loc="A11"/>
+    <pin index="187" name="fmc_lpc_la23_p" iostandard="LVCMOS18" loc="B11"/>
+    <pin index="188" name="fmc_lpc_la24_n" iostandard="LVCMOS18" loc="A6"/>
+    <pin index="189" name="fmc_lpc_la24_p" iostandard="LVCMOS18" loc="B6"/>
+    <pin index="190" name="fmc_lpc_la25_n" iostandard="LVCMOS18" loc="C6"/>
+    <pin index="191" name="fmc_lpc_la25_p" iostandard="LVCMOS18" loc="C7"/>
+    <pin index="192" name="fmc_lpc_la26_n" iostandard="LVCMOS18" loc="B8"/>
+    <pin index="193" name="fmc_lpc_la26_p" iostandard="LVCMOS18" loc="B9"/>
+    <pin index="194" name="fmc_lpc_la27_n" iostandard="LVCMOS18" loc="A7"/>
+    <pin index="195" name="fmc_lpc_la27_p" iostandard="LVCMOS18" loc="A8"/>
+    <pin index="196" name="fmc_lpc_la28_n" iostandard="LVCMOS18" loc="L13"/>
+    <pin index="197" name="fmc_lpc_la28_p" iostandard="LVCMOS18" loc="M13"/>	
+    <pin index="198" name="fmc_lpc_la29_n" iostandard="LVCMOS18" loc="J10"/>
+    <pin index="199" name="fmc_lpc_la29_p" iostandard="LVCMOS18" loc="K10"/>
+    <pin index="200" name="fmc_lpc_la30_n" iostandard="LVCMOS18" loc="D9"/>
+    <pin index="201" name="fmc_lpc_la30_p" iostandard="LVCMOS18" loc="E9"/>
+    <pin index="202" name="fmc_lpc_la31_n" iostandard="LVCMOS18" loc="E7"/>
+    <pin index="203" name="fmc_lpc_la31_p" iostandard="LVCMOS18" loc="F7"/>
+    <pin index="204" name="fmc_lpc_la32_n" iostandard="LVCMOS18" loc="E8"/>
+    <pin index="205" name="fmc_lpc_la32_p" iostandard="LVCMOS18" loc="F8"/>
+    <pin index="206" name="fmc_lpc_la33_n" iostandard="LVCMOS18" loc="C8"/>
+    <pin index="207" name="fmc_lpc_la33_p" iostandard="LVCMOS18" loc="C9"/>	
+	<pin index="208" name="fmc_lpc_clk0_m2c_n" iostandard="LVCMOS18" loc="E14"/>	
+	<pin index="209" name="fmc_lpc_clk0_m2c_p" iostandard="LVCMOS18" loc="E15"/>	
+	
+ 
+
+</pins>
+</part_info>
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/preset.xml b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/preset.xml
new file mode 100644
index 00000000..b8d89084
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files/preset.xml
@@ -0,0 +1,446 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?> 
+<ip_presets schema="1.0">
+
+    
+    <ip_preset preset_proc_name="DDR4_SDRAM_Preset">
+    <ip vendor="xilinx.com" library="ip" name="ddr4">
+      <user_parameters>
+        <user_parameter name="CONFIG.C0.DDR4_MemoryType" value="SODIMMs" />
+        <user_parameter name="CONFIG.C0.DDR4_MemoryPart" value="MTA8ATF51264HZ-2G1" />
+        <user_parameter name="CONFIG.C0.DDR4_DataWidth" value="64" />
+        <user_parameter name="CONFIG.C0.DDR4_TimePeriod" value="938" />
+        <user_parameter name="CONFIG.C0.DDR4_InputClockPeriod" value="3335" />
+        <user_parameter name="CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ" value="100" />
+      </user_parameters>
+    </ip>
+  </ip_preset>
+    
+  <ip_preset preset_proc_name="UART2_PL_Preset">
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
+      <user_parameters>
+        <user_parameter name="CONFIG.C_USE_UART_RX" value="1"/> 
+        <user_parameter name="CONFIG.C_USE_UART_TX" value="1"/> 
+      </user_parameters>
+    </ip>
+	<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+          <user_parameter name="CONFIG.USE_UART_RX" value="1"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+  <ip_preset preset_proc_name="zynq_ultra_ps_e_preset"> 
+    <ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" version="*"> 
+	
+    <user_parameters>
+	    <user_parameter name="CONFIG.PSU__PRESET_APPLIED" value="1"/> 
+		<user_parameter name="CONFIG.PSU_BANK_0_IO_STANDARD" value="LVCMOS18"/>
+		<user_parameter name="CONFIG.PSU_BANK_1_IO_STANDARD" value="LVCMOS18"/>
+		<user_parameter name="CONFIG.PSU_BANK_2_IO_STANDARD" value="LVCMOS18"/>
+		<user_parameter name="CONFIG.PSU__CAN1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__CAN1__PERIPHERAL__IO" value="MIO 24 .. 25"/>
+		<user_parameter name="CONFIG.PSU__ENET3__GRP_MDIO__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__ENET3__GRP_MDIO__IO" value="MIO 76 .. 77"/>
+		<user_parameter name="CONFIG.PSU__ENET3__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__ENET3__PERIPHERAL__IO" value="MIO 64 .. 75"/>
+		<user_parameter name="CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__IO" value="MIO 16 .. 17"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE" value="x4"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__IO" value="MIO 0 .. 5"/>
+		<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__MODE" value="Single"/>
+
+		<user_parameter name="CONFIG.PSU__SD1__GRP_CD__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SD1__GRP_CD__IO" value="MIO 45"/>
+		
+		<user_parameter name="CONFIG.PSU__SD1__GRP_POW__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD1__GRP_WP__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SD1__DATA_TRANSFER_MODE" value="4Bit"/> 
+		<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__IO" value="MIO 46 .. 51"/>
+		<user_parameter name="CONFIG.PSU__SD1__SLOT_TYPE" value="SD 2.0"/>
+
+		<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__UART0__PERIPHERAL__IO" value="MIO 18 .. 19"/>
+		<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__IO" value="MIO 20 .. 21"/>
+
+		<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__USB0__PERIPHERAL__IO" value="MIO 52 .. 63"/>
+
+		<user_parameter name="CONFIG.PSU__USE__IRQ0" value="1"/>
+		<user_parameter name="CONFIG.PSU__USE__M_AXI_GP0" value="1"/>
+		<user_parameter name="CONFIG.PSU__USE__M_AXI_GP1" value="1"/>
+		<user_parameter name="CONFIG.PSU__USE__M_AXI_GP2" value="0"/>
+
+		<user_parameter name="CONFIG.PSU__SATA__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SATA__LANE1__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SATA__LANE1__IO" value="GT Lane3"/>
+
+		<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__USB3_0__PERIPHERAL__IO" value="GT Lane2"/>
+
+<!-- 		<user_parameter name="CONFIG.PSU__PMU__PERIPHERAL__ENABLE" value="0"/> -->
+
+<!-- <user_parameter name="CONFIG.PSU__PMU__GPI0__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPI1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPI2__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPI3__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPI4__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPI5__ENABLE" value="0"/>
+
+		<user_parameter name="CONFIG.PSU__PMU__GPO0__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPO1__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPO2__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPO3__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPO4__ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__PMU__GPO5__ENABLE" value="0"/> -->
+
+		<user_parameter name="CONFIG.PSU__DDRC__VREF" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ECC" value="Disabled"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BUS_WIDTH" value="64 Bit"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DRAM_WIDTH" value="16 Bits"/>
+		<user_parameter name="CONFIG.PSU__DDRC__MEMORY_TYPE" value="DDR 4"/>
+		<user_parameter name="CONFIG.PSU__DDRC__COMPONENTS" value="Components"/>
+		<user_parameter name="CONFIG.PSU__DDRC__SPEED_BIN" value="DDR4_2133P"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ" value="1067"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DEVICE_CAPACITY" value="4096 MBits"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BG_ADDR_COUNT" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BANK_ADDR_COUNT" value="2"/>
+		<user_parameter name="CONFIG.PSU__DDRC__ROW_ADDR_COUNT" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__COL_ADDR_COUNT" value="10"/>
+		<user_parameter name="CONFIG.PSU__DDRC__CL" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__CWL" value="14"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RCD" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RP" value="15"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RC" value="47.06"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_RAS_MIN" value="33"/>
+		<user_parameter name="CONFIG.PSU__DDRC__T_FAW" value="30.0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_MODE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_T_REF_RANGE" value="Normal (0-85)"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PHY_DBI_MODE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PARITY_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__CLOCK_STOP_EN" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_CRC_CONTROL" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__TRAIN_DATA_EYE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__TRAIN_READ_GATE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL" value="1"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__BRC_MAPPING" value="ROW_BANK_COL"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DM_DBI" value="DM_NO_DBI"/>
+		<user_parameter name="CONFIG.PSU__DDRC__PER_BANK_REFRESH" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__FGRM" value="1X"/>
+		<user_parameter name="CONFIG.PSU__DDRC__LP_ASR" value="manual normal"/>
+		<user_parameter name="CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__STATIC_RD_MODE" value="0"/>
+		<user_parameter name="CONFIG.PSU__DDRC__SELF_REF_ABORT" value="0"/>
+
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE0__IO" value="GT Lane1"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__LANE1__IO" value="GT Lane0"/>
+		<user_parameter name="CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__IO" value="MIO 27 .. 30"/>
+		<user_parameter name="CONFIG.PSU__DP__LANE_SEL" value="Dual Lower"/>
+		<user_parameter name="CONFIG.PSU__DP__REF_CLK_FREQ" value="27"/>
+		<user_parameter name="CONFIG.PSU__DP__REF_CLK_SEL" value="Ref Clk3"/>
+
+		<user_parameter name="CONFIG.PSU__PSS_REF_CLK__FREQMHZ" value="33.333333"/>
+		<user_parameter name="CONFIG.PSU__SATA__REF_CLK_SEL" value="Ref Clk1"/>
+		<user_parameter name="CONFIG.PSU__USB0__REF_CLK_SEL" value="Ref Clk2"/>
+		<user_parameter name="CONFIG.PSU__SATA__REF_CLK_FREQ" value="125"/>
+		<user_parameter name="CONFIG.PSU__USB0__REF_CLK_FREQ" value="26"/>
+		<user_parameter name="CONFIG.PSU__OVERRIDE__BASIC_CLOCK" value="0"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__TTC1__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__TTC2__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__TTC3__PERIPHERAL__ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL" value="APB"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" value="20"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ" value="125"/>
+		<user_parameter name="CONFIG.PSU__FPGA_PL0_ENABLE" value="1"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL" value="APLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ" value="1200"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" value="250"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" value="RPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ" value="200"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" value="500"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" value="APLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ" value="600"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" value="APLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ" value="600"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" value="DPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" value="533.33"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" value="100"/>
+		<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" value="VPLL"/>
+	</user_parameters>
+
+    </ip>
+    </ip_preset>
+	
+	
+<ip_preset preset_proc_name="DIP_SWITCH_4Bits_Preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+     <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  
+  
+  <ip_preset preset_proc_name="LED_4Bits_Preset">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPO4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPO4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPO1" value="1"/> 
+          <user_parameter name="CONFIG.GPO1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPO2" value="1"/> 
+          <user_parameter name="CONFIG.GPO2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPO3" value="1"/> 
+          <user_parameter name="CONFIG.GPO3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPO4" value="1"/> 
+          <user_parameter name="CONFIG.GPO4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+  <ip_preset preset_proc_name="PUSH_BUTTON_4Bits">
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_IS_DUAL" value="1"/> 
+          <user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/> 
+          <user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/> 
+	  <user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.C_USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI1" value="1"/> 
+          <user_parameter name="CONFIG.GPI1_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI2" value="1"/> 
+          <user_parameter name="CONFIG.GPI2_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI3" value="1"/> 
+          <user_parameter name="CONFIG.GPI3_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+    <ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
+        <user_parameters>
+          <user_parameter name="CONFIG.USE_GPI4" value="1"/> 
+          <user_parameter name="CONFIG.GPI4_SIZE" value="4"/> 
+        </user_parameters>
+    </ip>
+  </ip_preset>
+
+</ip_presets>
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/constraints.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/constraints.xdc
index 5a3c1c4b..ed3a6e89 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/constraints.xdc
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/constraints.xdc
@@ -1 +1 @@
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets x_heep_system_i/pad_ring_i/pad_clk_i/xilinx_iobuf_i/O]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc
index 53e0eb8f..be620356 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc
@@ -1,213 +1,83 @@
-## This file is a general .xdc for the Nexys A7-100T
-## To use it in a project:
-## - uncomment the lines corresponding to used pins
-## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 ## Clock signal
-set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
-#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_i}]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
 
 
-##Switches
-set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { jtag_trst_ni }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
-set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { execute_from_flash_i }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
-set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { boot_select_i }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
-#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
-#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
-#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
-#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
-#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
-#set_property -dict { PACKAGE_PIN T8    IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
-#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
-#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
-#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
-#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
-#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
-#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
-#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports {rst_i}]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
 
 ## LEDs
-set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { rst_led }]; #IO_L18P_T2_A24_15 Sch=led[0]
-set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { clk_led }]; #IO_L24P_T3_RS1_15 Sch=led[1]
-set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { exit_value_o }]; #IO_L17N_T2_A25_15 Sch=led[2]
-set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { exit_valid_o }]; #IO_L8P_T1_D11_14 Sch=led[3]
-set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[29] }]; #IO_L7P_T1_D09_14 Sch=led[4]
-#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[30] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
-#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[31] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
-#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
-#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
-#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
-#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
-#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
-#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
-#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
-#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
-#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
-
-## RGB LEDs
-#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
-#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
-#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
-#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
-#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
-#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
-
-##7 segment display
-set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[8] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
-set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[9] }]; #IO_25_14 Sch=cb
-set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[10] }]; #IO_25_15 Sch=cc
-set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[11] }]; #IO_L17P_T2_A26_15 Sch=cd
-set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[12] }]; #IO_L13P_T2_MRCC_14 Sch=ce
-set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[13] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
-set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[14] }]; #IO_L4P_T0_D04_14 Sch=cg
-set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[15] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
-set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[16] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
-set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[17] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
-set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { gpio_io[18] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
-set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[19] }]; #IO_L19P_T3_A22_15 Sch=an[3]
-set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[20] }]; #IO_L8N_T1_D12_14 Sch=an[4]
-set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[21] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
-set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { gpio_io[22] }]; #IO_L23P_T3_35 Sch=an[6]
-set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[23] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
+set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {rst_led_o}];
+set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {clk_led_o}];
+set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {exit_valid_o}];
+set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {exit_value_o}];
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_OBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_out_OBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_led_OBUF]
 
-##CPU Reset Button
-set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33 } [get_ports { rst_i }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
-
-##Buttons
-set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[24] }]; #IO_L9P_T1_DQS_14 Sch=btnc
-set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[25] }]; #IO_L4N_T0_D05_14 Sch=btnu
-set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[26] }]; #IO_L12P_T1_MRCC_14 Sch=btnl
-set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[27] }]; #IO_L10N_T1_D15_14 Sch=btnr
-set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[28] }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
+##Switches
+set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {execute_from_flash_i}]; #Sch=sw[1]
+set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {boot_select_i}]; #Sch=sw[2]
 
+##Switches
+set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {jtag_trst_ni}]; #IO_L24N_T3_RS0_15 Sch=sw[0]
 
 ##Pmod Headers
 ##Pmod Header JA
-set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
-set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
-set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
-set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
-set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
-set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
-set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
-set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
-
-##Pmod Header JB
-#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
-#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
-#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
-set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { clk_out }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
-set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jtag_tms_i }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
-set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { jtag_tdi_i }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
-set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { jtag_tdo_o }]; #IO_0_15 Sch=jb[9]
-set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { jtag_tck_i }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
+set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports {spi_flash_csb_o}]; #IO_L20N_T3_A19_15 Sch=ja[1]
+set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sck_o}]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]; #IO_L18N_T2_A23_15 Sch=ja[4]
+set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]; #IO_L16N_T2_A27_15 Sch=ja[7]
+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]; #IO_L16P_T2_A28_15 Sch=ja[8]
+#set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports {gpio_io[6]}]; #IO_L22N_T3_A16_15 Sch=ja[9]
+#set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports {gpio_io[7]}]; #IO_L22P_T3_A17_15 Sch=ja[10]
 
 ##Pmod Header JC
-#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
-#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
-set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L22N_T3_35 Sch=jc[3]
-set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L19P_T3_35 Sch=jc[4]
-#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
-set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { spi_csb_o }]; #IO_L22P_T3_35 Sch=jc[8]
-#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
-#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
-
-##Pmod Header JD
-#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
-#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
-#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
-#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
-#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
-#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
-#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
-#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
+set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {spi_csb_o}]; #IO_L23N_T3_35 Sch=jc[1]
+set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {spi_sck_o}]; #IO_L19N_T3_VREF_35 Sch=jc[2]
+set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[0]}]; #IO_L22N_T3_35 Sch=jc[3]
+set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[1]}]; #IO_L19P_T3_35 Sch=jc[4]
+set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[2]}]; #IO_L6P_T0_35 Sch=jc[7]
+set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[3]}]; #IO_L22P_T3_35 Sch=jc[8]
+#set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {clk_out}]; #IO_L21P_T3_DQS_35 Sch=jc[9]
+#set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {JC[10]}]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
 
-##Pmod Header JXADC
-#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
-#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
-set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { spi_sd_io[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
-set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { spi_sd_io[0] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
-#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
-set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { spi_sd_io[1] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
-set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { spi_sd_io[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
-set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { spi_sck_o }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
-
-##VGA Connector
-#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
-#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
-#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
-#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
-#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
-#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
-#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
-#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
-#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
-#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
-#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
-#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
-#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
-#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
-
-##Micro SD Connector
-#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
-#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
-#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
-#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
-#set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
-#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
-#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
-#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
-
-##Accelerometer
-#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
-#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
-#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
-#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
-#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
-#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
-
-##Temperature Sensor
-#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
-#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
-#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
-#set_property -dict { PACKAGE_PIN B14   IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
-
-##Omnidirectional Microphone
-#set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
-#set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
-#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
+##USB-RS232 Interface
+set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports {uart_rx_i}]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {uart_tx_o}]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
 
-##PWM Audio Amplifier
-#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
-#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
+##Pmod Header JB
+#set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {JB[1]}]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {JB[2]}]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {uart_tx_o}]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {uart_rx_i}]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {jtag_tms_i}]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
+set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {jtag_tdi_i}]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
+set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports {jtag_tdo_o}]; #IO_0_15 Sch=jb[9]
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {jtag_tck_i}]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
 
-##USB-RS232 Interface
-set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
-set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
-#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
-#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
+## LEDs
+set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_io[1]}];
+set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_io[2]}];
+set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_io[3]}];
+set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {i2c_scl_io}];
+set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {i2c_sda_io}];
+set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[5]}];
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {gpio_io[6]}];
+set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {gpio_io[7]}];
+set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[8]}];
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {gpio_io[9]}];
+set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[10]}];
 
-##USB HID (PS/2)
-#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
-#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
+##Buttons
+set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[0]}]; #IO_L9P_T1_DQS_14 Sch=btnc
+set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {gpio_io[1]}]; #IO_L4N_T0_D05_14 Sch=btnu
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[2]}]; #IO_L12P_T1_MRCC_14 Sch=btnl
+set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[3]}]; #IO_L10N_T1_D15_14 Sch=btnr
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {gpio_io[4]}]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
 
-##SMSC Ethernet PHY
-#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
-#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
-#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
-#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
-#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
-#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
-#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
-#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
-#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
-#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
-#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
-#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]
 
-##Quad SPI Flash
-#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
-#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
-#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
-#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
-#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc
index 5a3c1c4b..ed3a6e89 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc
@@ -1 +1 @@
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets x_heep_system_i/pad_ring_i/pad_clk_i/xilinx_iobuf_i/O]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/pin_assign.xdc
index 116323f2..9f8f7ded 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/pin_assign.xdc
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/pin_assign.xdc
@@ -2,84 +2,97 @@
 # Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
+# Clock signal
 set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk_i]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]
+
 set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports rst_i]
-set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports rst_led]
-set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports clk_led]
-set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports clk_out]
+
+# LEDs
+set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports rst_led_o]
+set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports clk_led_o]
 set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
 set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_OBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_out_OBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_led_OBUF]
+
+# Switches
 set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports execute_from_flash_i]
 set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports boot_select_i]
 
-## Pmoda
-## RPi GPIO 7-0 are shared with pmoda_rpi_gpio_tri_io[7:0]
-
+# FLASH
 # QSPI
 # Q0 / MOSI
 # Q1 / MISO
 # Q2 / nWP
 # Q3 / nHLD
+set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o] ; # Pmoda[4]
+set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o] ; # Pmoda[0]
+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}] ; # Pmoda[5]
+set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}] ; # Pmoda[1]
+set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}] ; # Pmoda[6]
+set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}] ; # Pmoda[2]
 
-set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o]
-set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o]
-set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]
-set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]
-set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]
-set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]
-#set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {crst}]
-set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni]
+# UART
+set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports uart_tx_o] ; # Pmodb[0]
+set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports uart_rx_i] ; # Pmodb[4]
 
-set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_csb_o]
-set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_sck_o]
-set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[0]}]
-set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[1]}]
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[2]}]
-set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[3]}]
+# JTAG
+set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i] ; # Pmob[1]
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o] ; # Pmodb[6]
+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i] ; # Pmodb[2]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i] ; # Pmodb[5]
+set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni] ; # Pmoda[7]
 
-## Pmodb
-set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports uart_tx_o]
-set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports uart_rx_i]
-set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i]
-set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o]
-set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i]
-set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i]
+# I2C
+set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {i2c_scl_io}] ; # Pmodb[7]
+set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {i2c_sda_io}] ; # Pmodb[3]
 
-set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[0]}]
-set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[1]}]
-set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[2]}]
-set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[3]}]
-set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[4]}]
-set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {gpio_io[5]}]
-set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[6]}]
-set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[7]}]
-set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[8]}]
-set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[9]}]
-set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[10]}]
-set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[11]}]
-set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[12]}]
-set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[13]}]
-set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[14]}]
-set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {pdm2pcm_clk_io}]
-set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {pdm2pcm_pdm_io}]
-set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {i2s_sck_io}]
-set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {i2s_ws_io}]
-set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {i2s_sd_io}]
+# SPI SD
+set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_csb_o] ; # arduino_direct_spi_ss_io
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_sck_o] ; # arduino_direct_spi_sck_io
+set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[0]}] ; # arduino_direct_spi_io0_io
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[1]}] ; # arduino_direct_spi_io1_io
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[2]}] ; # arduino_gpio_tri_io[12]
+set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[3]}] ; # arduino_gpio_tri_io[13]
 
-## Tri-color LD5 for TARGET_PYNQ_Z2
-set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {gpio_io[15]}]
-set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[16]}]
-set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[17]}]
+# GPIOs
+set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[0]}] ; # arduino_gpio_tri_io[0]
+set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[1]}] ; # rpi_gpio_tri_io[11]
+set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[2]}] ; # rpi_gpio_tri_io[5]
+set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[3]}] ; # rpi_gpio_tri_io[16]
+set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[4]}] ; # rpi_gpio_tri_io[7]
+set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {gpio_io[5]}] ; # arduino_gpio_tri_io[1]
+set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[6]}] ; # rpi_gpio_tri_io[3]
+set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[7]}] ; # rpi_gpio_tri_io[1]
+set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[8]}] ; # rpi_gpio_tri_io[2]
+set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[9]}] ; # rpi_gpio_tri_io[14]
+set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[10]}] ; # rpi_gpio_tri_io[19]
+set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[11]}] ; # rpi_gpio_tri_io[9]
+set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[12]}] ; # rpi_gpio_tri_io[6]
+set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[13]}] ; # arduino_gpio_tri_io[2]
+set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[14]}] ; # arduino_gpio_tri_io[3]
 
-set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_o[0]}]
-set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_o[1]}]
-set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports {spi2_sck_o}]
-set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_0_io}]
-set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_1_io}]
-set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_2_io}]
-set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_3_io}]
-set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {i2c_scl_io}]
-set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {i2c_sda_io}]
+# PDM2PCM
+set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {pdm2pcm_clk_io}] ; # rpi_gpio_tri_io[13]
+set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {pdm2pcm_pdm_io}] ; # rpi_gpio_tri_io[12]
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]
+# I2S
+set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {i2s_sck_io}] ; # rpi_gpio_tri_io[8]
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {i2s_ws_io}] ; # rpi_gpio_tri_io[4]
+set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {i2s_sd_io}] ; # arduino_direct_iic_scl_io
+
+# SPI2
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_o[0]}] ; # rpi_gpio_tri_io[15]
+set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_o[1]}] ; # arduino_gpio_tri_io[5]
+set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports {spi2_sck_o}] ; # rpi_gpio_tri_io[10]
+set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_io[0]}] ; # arduino__gpio_tri_io[8]
+set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_io[1]}] ; # arduino_gpio_tri_io[9]
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_io[2]}] ; # arduino_gpio_tri_io[10]
+set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_io[3]}] ; # arduino_gpio_tri_io[11]
 
+# Tri-color LEDs for TARGET_PYNQ_Z2
+set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {gpio_io[15]}] ; # rgbleds_6bits_tri_o[5]
+set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[16]}] ; # rgbled_6bits_tri_o[3]
+set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[17]}] ; # rgbleds_6bits_tri_o[4]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
new file mode 100644
index 00000000..4b523cdf
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
@@ -0,0 +1,99 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# CLOCK
+set_property -dict {PACKAGE_PIN AH18 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
+set_property -dict {PACKAGE_PIN AH17 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i]
+
+# RESET
+set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports rst_i]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_i]
+
+# LEDS
+set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports rst_led_o]
+set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports clk_led_o]
+set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
+set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
+
+# SWITCHES
+set_property -dict {PACKAGE_PIN E4 IOSTANDARD LVCMOS33} [get_ports execute_from_flash_i]
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports boot_select_i]
+
+# FLASH
+# QSPI
+# Q0 / MOSI
+# Q1 / MISO
+# Q2 / nWP
+# Q3 / nHLD
+set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o]
+set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o]
+set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]
+set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]
+set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]
+set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]
+
+# UART
+set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports uart_tx_o]
+set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports uart_rx_i]
+
+# JTAG
+set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i]
+set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o]
+set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i]
+set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i]
+set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni]
+
+# I2C
+set_property -dict {PACKAGE_PIN J7 IOSTANDARD LVCMOS33} [get_ports i2c_scl_io]
+set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports i2c_sda_io]
+
+## The following pins are sent to the FMC connector, using the LA pins as single-ended.
+## The bank only supports up to 1.8 V.
+
+# SPI SD
+set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports spi_csb_o]
+set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports spi_sck_o]
+set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[0]}]
+set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[1]}]
+set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[2]}]
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[3]}]
+
+# GPIOs
+set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[0]}]
+set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[1]}]
+set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[2]}]
+set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports {gpio_io[3]}]
+set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[4]}]
+set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[5]}]
+set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[6]}]
+set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[7]}]
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[8]}]
+set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[9]}]
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[10]}]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[11]}]
+set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[12]}]
+set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[13]}]
+set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[14]}]
+set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[15]}]
+set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports {gpio_io[16]}]
+set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[17]}]
+
+# PDM2PCM
+set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_clk_io]
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_pdm_io]
+
+# I2S
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports i2s_sck_io]
+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports i2s_ws_io]
+set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports i2s_sd_io]
+
+# SPI2
+set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_o[0]}]
+set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_o[1]}]
+set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports spi2_sck_o]
+set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[0]}]
+set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[1]}]
+set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[2]}]
+set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[3]}]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv
index 349920c1..35165b88 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv
@@ -158,3 +158,12 @@ module tc_clk_xor2 (
   assign clk_o = clk0_i ^ clk1_i;
 
 endmodule
+
+module tc_clk_inverter (
+    input  logic clk_i,
+    output logic clk_o
+);
+
+  xilinx_clk_inverter clk_inv_i (.*);
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl
new file mode 100644
index 00000000..544cd11b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl
@@ -0,0 +1,3 @@
+# Select board
+set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
+set_property -name "board_part" -value "digilentinc.com:nexys-a7-100t:part0:1.3" -objects [current_project]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl
new file mode 100644
index 00000000..69dff9c3
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl
@@ -0,0 +1,43 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# Define design macros
+
+set design_name      xilinx_clk_wizard
+set in_clk_freq_MHz  100
+set out_clk_freq_MHz 15
+
+
+# Create block design
+create_bd_design $design_name
+
+# Create ports
+set clk_100MHz [ create_bd_port -dir I -type clk -freq_hz [ expr $in_clk_freq_MHz * 1000000 ] clk_100MHz ]
+set clk_out1_0 [ create_bd_port -dir O -type clk clk_out1_0 ]
+set_property -dict [ list CONFIG.FREQ_HZ [ expr $out_clk_freq_MHz * 1000000 ] ] $clk_out1_0
+
+# Create instance and set properties
+set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+set_property -dict [ list \
+ CONFIG.CLKOUT1_JITTER {333.843} \
+ CONFIG.CLKOUT1_PHASE_ERROR {293.793} \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {15} \
+ CONFIG.MMCM_DIVCLK_DIVIDE {5} \
+ CONFIG.MMCM_CLKFBOUT_MULT_F {49.875} \
+ CONFIG.MMCM_CLKOUT0_DIVIDE_F {66.500} \
+ CONFIG.PRIM_IN_FREQ $in_clk_freq_MHz \
+ CONFIG.USE_LOCKED {false} \
+ CONFIG.USE_RESET {false} \
+] $clk_wiz_0
+
+# Create port connections
+connect_bd_net -net clk_in1_0_1 [ get_bd_ports clk_100MHz ] [ get_bd_pins clk_wiz_0/clk_in1 ]
+connect_bd_net -net clk_wiz_0_clk_out1 [ get_bd_ports clk_out1_0 ] [ get_bd_pins clk_wiz_0/clk_out1 ]
+
+# Save and close block design
+save_bd_design
+close_bd_design $design_name
+
+# create wrapper
+set wrapper_path [ make_wrapper -fileset sources_1 -files [ get_files -norecurse xilinx_clk_wizard.bd ] -top ]
+add_files -norecurse -fileset sources_1 $wrapper_path
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl
new file mode 100644
index 00000000..f16f754f
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl
@@ -0,0 +1,3 @@
+# Select board
+set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
+set_property -name "board_part" -value "tul.com.tw:pynq-z2:part0:1.0" -objects [current_project]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl
similarity index 86%
rename from hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl
rename to hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl
index 1c2a41a0..e61c5832 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl
@@ -7,9 +7,6 @@ set design_name      xilinx_clk_wizard
 set in_clk_freq_MHz  125
 set out_clk_freq_MHz 15
 
-# Select board
-set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
-set_property -name "board_part" -value "tul.com.tw:pynq-z2:part0:1.0" -objects [current_project]
 
 # Create block design
 create_bd_design $design_name
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl
new file mode 100644
index 00000000..0108a4c8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl
@@ -0,0 +1,3 @@
+# Select board
+set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
+set_property -name "board_part" -value "xilinx.com:zcu104:part0:1.0" -objects [current_project]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl
new file mode 100644
index 00000000..d67e4054
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl
@@ -0,0 +1,40 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# Define design macros
+
+set design_name xilinx_clk_wizard
+
+# Create block design
+create_bd_design $design_name
+
+# Create instance and set properties
+create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
+set_property -dict [list \
+  CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \
+  CONFIG.CLKOUT1_JITTER {282.792} \
+  CONFIG.CLKOUT1_PHASE_ERROR {207.545} \
+  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {15} \
+  CONFIG.CLK_IN1_BOARD_INTERFACE {clk_300mhz} \
+  CONFIG.MMCM_CLKFBOUT_MULT_F {32.875} \
+  CONFIG.MMCM_CLKIN1_PERIOD {3.333} \
+  CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
+  CONFIG.MMCM_CLKOUT0_DIVIDE_F {65.750} \
+  CONFIG.MMCM_DIVCLK_DIVIDE {10} \
+  CONFIG.OPTIMIZE_CLOCKING_STRUCTURE_EN {true} \
+  CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
+  CONFIG.USE_LOCKED {false} \
+  CONFIG.USE_RESET {true} \
+] [get_bd_cells clk_wiz_0]
+
+# Create ports
+make_bd_pins_external [get_bd_cells clk_wiz_0]
+make_bd_intf_pins_external [get_bd_cells clk_wiz_0]
+
+# Save and close block design
+save_bd_design
+close_bd_design $design_name
+
+# Create wrapper
+set wrapper_path [ make_wrapper -fileset sources_1 -files [ get_files -norecurse xilinx_clk_wizard.bd ] -top ]
+add_files -norecurse -fileset sources_1 $wrapper_path
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
index 1324bfb1..fc9c53fb 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
@@ -13,13 +13,16 @@ module xilinx_core_v_mini_mcu_wrapper
     parameter CLK_LED_COUNT_LENGTH = 27
 ) (
 
+`ifdef FPGA_ZCU104
+    inout logic clk_300mhz_n,
+    inout logic clk_300mhz_p,
+`else
     inout logic clk_i,
+`endif
     inout logic rst_i,
 
-    //visibility signals
-    output logic rst_led,
-    output logic clk_led,
-    output logic clk_out,
+    output logic rst_led_o,
+    output logic clk_led_o,
 
     inout logic boot_select_i,
     inout logic execute_from_flash_i,
@@ -33,7 +36,7 @@ module xilinx_core_v_mini_mcu_wrapper
     inout logic uart_rx_i,
     inout logic uart_tx_o,
 
-    inout logic [19:0] gpio_io,
+    inout logic [17:0] gpio_io,
 
     output logic exit_value_o,
     inout  logic exit_valid_o,
@@ -46,10 +49,7 @@ module xilinx_core_v_mini_mcu_wrapper
     inout logic spi_csb_o,
     inout logic spi_sck_o,
 
-    inout logic spi2_sd_0_io,
-    inout logic spi2_sd_1_io,
-    inout logic spi2_sd_2_io,
-    inout logic spi2_sd_3_io,
+    inout logic [3:0] spi2_sd_io,
     inout logic [1:0] spi2_csb_o,
     inout logic spi2_sck_o,
 
@@ -71,13 +71,17 @@ module xilinx_core_v_mini_mcu_wrapper
   logic [CLK_LED_COUNT_LENGTH - 1:0] clk_count;
 
   // low active reset
-  assign rst_n   = !rst_i;
+`ifdef FPGA_NEXYS
+  assign rst_n = rst_i;
+`else
+  assign rst_n = !rst_i;
+`endif
 
   // reset LED for debugging
-  assign rst_led = rst_n;
+  assign rst_led_o = rst_n;
 
   // counter to blink an LED
-  assign clk_led = clk_count[CLK_LED_COUNT_LENGTH-1];
+  assign clk_led_o = clk_count[CLK_LED_COUNT_LENGTH-1];
 
   always_ff @(posedge clk_gen or negedge rst_n) begin : clk_count_process
     if (!rst_n) begin
@@ -90,13 +94,23 @@ module xilinx_core_v_mini_mcu_wrapper
   // eXtension Interface
   if_xif #() ext_if ();
 
-  // clock output for debugging
-  assign clk_out = clk_gen;
-
+`ifdef FPGA_ZCU104
+  xilinx_clk_wizard_wrapper xilinx_clk_wizard_wrapper_i (
+      .CLK_IN1_D_0_clk_n(clk_300mhz_n),
+      .CLK_IN1_D_0_clk_p(clk_300mhz_p),
+      .clk_out1_0(clk_gen)
+  );
+`elsif FPGA_NEXYS
+  xilinx_clk_wizard_wrapper xilinx_clk_wizard_wrapper_i (
+      .clk_100MHz(clk_i),
+      .clk_out1_0(clk_gen)
+  );
+`else  // FPGA PYNQ-Z2
   xilinx_clk_wizard_wrapper xilinx_clk_wizard_wrapper_i (
       .clk_125MHz(clk_i),
       .clk_out1_0(clk_gen)
   );
+`endif
 
   x_heep_system #(
       .X_EXT(X_EXT),
@@ -180,10 +194,10 @@ module xilinx_core_v_mini_mcu_wrapper
       .spi_sck_io(spi_sck_o),
       .i2c_scl_io,
       .i2c_sda_io,
-      .spi2_sd_0_io(spi2_sd_0_io),
-      .spi2_sd_1_io(spi2_sd_1_io),
-      .spi2_sd_2_io(spi2_sd_2_io),
-      .spi2_sd_3_io(spi2_sd_3_io),
+      .spi2_sd_0_io(spi2_sd_io[0]),
+      .spi2_sd_1_io(spi2_sd_io[1]),
+      .spi2_sd_2_io(spi2_sd_io[2]),
+      .spi2_sd_3_io(spi2_sd_io[3]),
       .spi2_cs_0_io(spi2_csb_o[0]),
       .spi2_cs_1_io(spi2_csb_o[1]),
       .spi2_sck_io(spi2_sck_o),
@@ -191,7 +205,9 @@ module xilinx_core_v_mini_mcu_wrapper
       .pdm2pcm_pdm_io,
       .i2s_sck_io(i2s_sck_io),
       .i2s_ws_io(i2s_ws_io),
-      .i2s_sd_io(i2s_sd_io)
+      .i2s_sd_io(i2s_sd_io),
+      .ext_dma_slot_tx_i('0),
+      .ext_dma_slot_rx_i('0)
   );
 
   assign exit_value_o = exit_value[0];
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/README.md b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/README.md
index dc07aef1..65b4b051 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/README.md
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/README.md
@@ -1,33 +1,5 @@
 ## boot_rom
 
-1. If you haven't done it yet, install [Conda](https://phoenixnap.com/kb/how-to-install-anaconda-ubuntu-18-04-or-20-04) as described in the link,
-and create the Conda enviroment with python 2.7:
-
-```bash
-conda update conda
-conda env create -f environment.yml
-```
-
-Activate the environment with
-
-```bash
-conda activate boot_rom
-```
-
-If you are already in the core-v-mini-mcu conda env, deactivate it first:
-
-```bash
-conda deactivate
-```
-
-2. Install the required Python tools:
-
-```
-pip install --user -r python-requirements.txt
-```
-
-3. Generate the boot_rom:
-
 If you modified the `boot_rom.S` file, generate it as:
 
 ```
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.S b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.S
index f154eec4..7b0fab66 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.S
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.S
@@ -99,7 +99,7 @@ _wait_spi_ready_tx_init:
 _wait_spi_ready_read_prog:
        lw     a5, SPI_HOST_STATUS_REG_OFFSET(a1)
        bgez   a5, _wait_spi_ready_read_prog
-       li     a3, 1024 # 1KB copy size
+       li     a3, 2048 # 2KB copy size
        li     s1, 0 # dst ptr (ram)
 
        // For loop until the 1KB copy from flash to ram is done
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.dump b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.dump
index c4a74476..025800d8 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.dump
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.dump
@@ -6,14 +6,14 @@ Disassembly of section .text:
 
 00000000 <entry>:
    0:	200405b7          	lui	a1,0x20040
-   4:	0005c503          	lbu	a0,0(a1) # 20040000 <_end+0x2003ff16>
+   4:	0005c503          	lbu	a0,0(a1) # 20040000 <_end+0x2003ff14>
    8:	c119                	beqz	a0,e <boot>
    a:	41c8                	lw	a0,4(a1)
    c:	9502                	jalr	a0
 
 0000000e <boot>:
    e:	200005b7          	lui	a1,0x20000
-  12:	0085c503          	lbu	a0,8(a1) # 20000008 <_end+0x1fffff1e>
+  12:	0085c503          	lbu	a0,8(a1) # 20000008 <_end+0x1fffff1c>
   16:	e511                	bnez	a0,22 <_jump_to_flash>
 
 00000018 <_jump_to_debug_rom>:
@@ -31,7 +31,7 @@ Disassembly of section .text:
   2c:	4505                	li	a0,1
   2e:	c188                	sw	a0,0(a1)
   30:	400005b7          	lui	a1,0x40000
-  34:	18058593          	addi	a1,a1,384 # 40000180 <_end+0x40000096>
+  34:	18058593          	addi	a1,a1,384 # 40000180 <_end+0x40000094>
   38:	9582                	jalr	a1
 
 0000003a <_copy_from_flash>:
@@ -73,41 +73,42 @@ Disassembly of section .text:
 0000008a <_wait_spi_ready_read_prog>:
   8a:	49dc                	lw	a5,20(a1)
   8c:	fe07dfe3          	bgez	a5,8a <_wait_spi_ready_read_prog>
-  90:	40000693          	li	a3,1024
-  94:	4481                	li	s1,0
-  96:	10000b13          	li	s6,256
-  9a:	09000437          	lui	s0,0x9000
-  9e:	0ff40a93          	addi	s5,s0,255 # 90000ff <_end+0x9000015>
-
-000000a2 <_32B_chunk_loop>:
-  a2:	00db4663          	blt	s6,a3,ae <_read_32B_chunk>
-  a6:	08000437          	lui	s0,0x8000
-  aa:	0ff40a93          	addi	s5,s0,255 # 80000ff <_end+0x8000015>
-
-000000ae <_read_32B_chunk>:
-  ae:	0355a223          	sw	s5,36(a1) # 20020024 <_end+0x2001ff3a>
-  b2:	0001                	nop
-
-000000b4 <_wait_spi_ready_read_32B_chunk>:
-  b4:	49dc                	lw	a5,20(a1)
-  b6:	fe07dfe3          	bgez	a5,b4 <_wait_spi_ready_read_32B_chunk>
-  ba:	10048b93          	addi	s7,s1,256
-
-000000be <_wait_spi_rxwm_8_words>:
-  be:	49dc                	lw	a5,20(a1)
-  c0:	83d1                	srli	a5,a5,0x14
-  c2:	8b85                	andi	a5,a5,1
-  c4:	dfed                	beqz	a5,be <_wait_spi_rxwm_8_words>
-  c6:	02048613          	addi	a2,s1,32
-
-000000ca <_spi_fifo_read_8_words>:
-  ca:	0285a883          	lw	a7,40(a1)
-  ce:	0114a023          	sw	a7,0(s1)
-  d2:	0491                	addi	s1,s1,4
-  d4:	fec49be3          	bne	s1,a2,ca <_spi_fifo_read_8_words>
-  d8:	ff7493e3          	bne	s1,s7,be <_wait_spi_rxwm_8_words>
-  dc:	f0068693          	addi	a3,a3,-256
-  e0:	f2e9                	bnez	a3,a2 <_32B_chunk_loop>
-  e2:	200005b7          	lui	a1,0x20000
-  e6:	4990                	lw	a2,16(a1)
-  e8:	9602                	jalr	a2
+  90:	6685                	lui	a3,0x1
+  92:	80068693          	addi	a3,a3,-2048 # 800 <_end+0x714>
+  96:	4481                	li	s1,0
+  98:	10000b13          	li	s6,256
+  9c:	09000437          	lui	s0,0x9000
+  a0:	0ff40a93          	addi	s5,s0,255 # 90000ff <_end+0x9000013>
+
+000000a4 <_32B_chunk_loop>:
+  a4:	00db4663          	blt	s6,a3,b0 <_read_32B_chunk>
+  a8:	08000437          	lui	s0,0x8000
+  ac:	0ff40a93          	addi	s5,s0,255 # 80000ff <_end+0x8000013>
+
+000000b0 <_read_32B_chunk>:
+  b0:	0355a223          	sw	s5,36(a1) # 20020024 <_end+0x2001ff38>
+  b4:	0001                	nop
+
+000000b6 <_wait_spi_ready_read_32B_chunk>:
+  b6:	49dc                	lw	a5,20(a1)
+  b8:	fe07dfe3          	bgez	a5,b6 <_wait_spi_ready_read_32B_chunk>
+  bc:	10048b93          	addi	s7,s1,256
+
+000000c0 <_wait_spi_rxwm_8_words>:
+  c0:	49dc                	lw	a5,20(a1)
+  c2:	83d1                	srli	a5,a5,0x14
+  c4:	8b85                	andi	a5,a5,1
+  c6:	dfed                	beqz	a5,c0 <_wait_spi_rxwm_8_words>
+  c8:	02048613          	addi	a2,s1,32
+
+000000cc <_spi_fifo_read_8_words>:
+  cc:	0285a883          	lw	a7,40(a1)
+  d0:	0114a023          	sw	a7,0(s1)
+  d4:	0491                	addi	s1,s1,4
+  d6:	fec49be3          	bne	s1,a2,cc <_spi_fifo_read_8_words>
+  da:	ff7493e3          	bne	s1,s7,c0 <_wait_spi_rxwm_8_words>
+  de:	f0068693          	addi	a3,a3,-256
+  e2:	f2e9                	bnez	a3,a4 <_32B_chunk_loop>
+  e4:	200005b7          	lui	a1,0x20000
+  e8:	4990                	lw	a2,16(a1)
+  ea:	9602                	jalr	a2
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.h b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.h
index 8f0e3d2b..bbb8198a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.h
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.h
@@ -39,27 +39,27 @@ uint32_t reset_vec[reset_vec_size] = {
     0xd1d8070d,
     0x49dc0001,
     0xfe07dfe3,
-    0x40000693,
-    0x0b134481,
-    0x04371000,
-    0x0a930900,
-    0x46630ff4,
-    0x043700db,
-    0x0a930800,
-    0xa2230ff4,
-    0x00010355,
-    0xdfe349dc,
-    0x8b93fe07,
-    0x49dc1004,
-    0x8b8583d1,
-    0x8613dfed,
-    0xa8830204,
-    0xa0230285,
-    0x04910114,
-    0xfec49be3,
-    0xff7493e3,
-    0xf0068693,
-    0x05b7f2e9,
-    0x49902000,
-    0x00009602
+    0x86936685,
+    0x44818006,
+    0x10000b13,
+    0x09000437,
+    0x0ff40a93,
+    0x00db4663,
+    0x08000437,
+    0x0ff40a93,
+    0x0355a223,
+    0x49dc0001,
+    0xfe07dfe3,
+    0x10048b93,
+    0x83d149dc,
+    0xdfed8b85,
+    0x02048613,
+    0x0285a883,
+    0x0114a023,
+    0x9be30491,
+    0x93e3fec4,
+    0x8693ff74,
+    0xf2e9f006,
+    0x200005b7,
+    0x96024990
 };
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.sv
index 07c74e3a..93983a15 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/boot_rom.sv
@@ -26,29 +26,29 @@ module boot_rom
 
   logic [RomSize-1:0][31:0] mem;
   assign mem = {
-    32'h00009602,
-    32'h49902000,
-    32'h05b7f2e9,
-    32'hf0068693,
-    32'hff7493e3,
-    32'hfec49be3,
-    32'h04910114,
-    32'ha0230285,
-    32'ha8830204,
-    32'h8613dfed,
-    32'h8b8583d1,
-    32'h49dc1004,
-    32'h8b93fe07,
-    32'hdfe349dc,
-    32'h00010355,
-    32'ha2230ff4,
-    32'h0a930800,
-    32'h043700db,
-    32'h46630ff4,
-    32'h0a930900,
-    32'h04371000,
-    32'h0b134481,
-    32'h40000693,
+    32'h96024990,
+    32'h200005b7,
+    32'hf2e9f006,
+    32'h8693ff74,
+    32'h93e3fec4,
+    32'h9be30491,
+    32'h0114a023,
+    32'h0285a883,
+    32'h02048613,
+    32'hdfed8b85,
+    32'h83d149dc,
+    32'h10048b93,
+    32'hfe07dfe3,
+    32'h49dc0001,
+    32'h0355a223,
+    32'h0ff40a93,
+    32'h08000437,
+    32'h00db4663,
+    32'h0ff40a93,
+    32'h09000437,
+    32'h10000b13,
+    32'h44818006,
+    32'h86936685,
     32'hfe07dfe3,
     32'h49dc0001,
     32'hd1d8070d,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/environment.yml b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/environment.yml
deleted file mode 100644
index 260ecf9a..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/environment.yml
+++ /dev/null
@@ -1,6 +0,0 @@
-name: boot_rom
-channels:
-  - defaults
-dependencies:
-  - python=2.7.18
-
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/gen_rom.py b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/gen_rom.py
index b52e22bd..b1a79b57 100755
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/gen_rom.py
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/boot_rom/gen_rom.py
@@ -89,9 +89,8 @@
 def read_bin():
 
     with open(filename + ".img", 'rb') as f:
-        rom = binascii.hexlify(f.read())
-        rom = map(''.join, zip(rom[::2], rom[1::2]))
-
+        rom = bytes.hex(f.read())
+        rom = list(map(''.join, zip(rom[::2], rom[1::2])))
 
     # align to 32 bit
     align = (int((len(rom) + 3) / 4 )) * 4;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_core.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_core.sv
index fb155575..2195a075 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_core.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_core.sv
@@ -7,8 +7,8 @@
 // Description: I2s core logic 
 
 module i2s_core #(
-    parameter MaxWordWidth,
-    parameter ClkDividerWidth
+    parameter MaxWordWidth = 32,
+    parameter ClkDividerWidth = 8
 ) (
     input logic clk_i,
     input logic rst_ni,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_ws_gen.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_ws_gen.sv
index ed85b649..a6ebeca2 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_ws_gen.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_ws_gen.sv
@@ -10,7 +10,7 @@
 // by Antonio Pullini (pullinia@iis.ee.ethz.ch)
 
 module i2s_ws_gen #(
-    parameter MaxWordWidth,
+    parameter MaxWordWidth = 32,
     localparam int unsigned CounterWidth = $clog2(MaxWordWidth)
 ) (
     input logic sck_i,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/data/iffifo.hjson b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/data/iffifo.hjson
new file mode 100644
index 00000000..919cceaf
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/data/iffifo.hjson
@@ -0,0 +1,76 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{ name: "iffifo"
+  clock_primary: "clk_i"
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: 32
+  registers: [
+  
+    { name:     "FIFO_OUT"
+      desc:     "Data coming from the FIFO (Fifo Output/Software RX)"
+      swaccess: "ro"
+      hwaccess: "hrw" # required for RE signal
+      hwext: "true"   # required for RE signal
+      hwre: "true"    # Used to emulate a window behaviour
+      fields: [
+        { bits: "31:0" }
+      ]
+    }
+    
+    { name:     "FIFO_IN"
+      desc:     "Data sent to the FIFO (Fifo Input/Software TX)"
+      hwaccess: "hro"
+      swaccess: "rw"  # required for QE signal
+      hwqe: "true"    # Used to emulate a window behaviour
+      fields: [
+        { bits: "31:0" }
+      ]
+    }
+    
+    { name:     "STATUS"
+      desc:     "General purpose status register"
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "0", name: "EMPTY",   desc: "Asserted when FIFO empty." }
+        { bits: "1", name: "AVAILABLE", desc: "Asserted when data is available in FIFO." }
+        { bits: "2", name: "REACHED", desc: "Asserted when occupied data slots count greater than threshold." }
+        { bits: "3", name: "FULL",    desc: "Asserted when all FIFO slots are occupied." }
+      ]
+    }
+    
+    { name:     "OCCUPANCY"
+      desc:     "Current number of occupied FIFO slots"
+      swaccess: "ro"
+      hwaccess: "hwo"
+      fields: [
+        { bits: "31:0" }
+      ]
+    }
+    
+    { name:     "WATERMARK"
+      desc:     "FIFO occupancy at which the STATUS:REACHED bit is asserted"
+      swaccess: "rw"
+      hwaccess: "hro"
+      fields: [
+        { bits: "31:0" }
+      ]
+    }
+    
+    { name:     "INTERRUPTS"
+      desc:     "Write any value to assert an interrupt. Write 0 or 1 to disable or enable an interrupt."
+      swaccess: "rw"
+      hwaccess: "hro"
+      hwqe: "true"    # Used to catch software writes
+      fields: [
+        { bits: "0", name: "REACHED",     desc: "Watermark reached interrupt" }
+      ]
+    }
+    
+  ]
+}
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.core b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.core
new file mode 100644
index 00000000..f0e23463
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.core
@@ -0,0 +1,26 @@
+CAPI=2:
+
+name: "example:ip:iffifo"
+description: "core-v-mini-mcu iffifo peripheral"
+
+# Copyright 2023 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# Author: Pierre Guillod <pierre.guillod@epfl.ch>, EPFL, STI-SEL
+# Date: 18.10.2023
+
+filesets:
+  files_rtl:
+    depend:
+      - pulp-platform.org::common_cells
+    files:
+    - rtl/iffifo_reg_pkg.sv
+    - rtl/iffifo_reg_top.sv
+    - rtl/iffifo.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+    - files_rtl
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.vlt b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.vlt
new file mode 100644
index 00000000..9820d038
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo.vlt
@@ -0,0 +1,15 @@
+// Copyright 2023 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Author: Pierre Guillod <pierre.guillod@epfl.ch>, EPFL, STI-SEL
+// Date: 18.10.2023
+
+`verilator_config
+
+lint_off -rule DECLFILENAME -file "*/iffifo/rtl/iffifo_reg_top.sv" -match "Filename 'iffifo_reg_top' does not match MODULE name: 'iffifo_reg_top_intf'*"
+lint_off -rule WIDTH -file "*/iffifo/rtl/iffifo_reg_top.sv" -match "Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's SEL generates 32*"
+lint_off -rule UNUSED -file "*/iffifo/rtl/iffifo.sv" -match "Bits of signal are not used: 'reg2hw'[0]*"
+
+lint_off -rule UNUSED -file "*/iffifo/rtl/iffifo_window.sv" -match "Bits of signal are not used: 'rx_win_i'[67:64,31:0]"
+lint_off -rule WIDTH -file "*/iffifo/rtl/iffifo_*.sv" -match "Operator ASSIGNW expects*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo_gen.sh b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo_gen.sh
new file mode 100755
index 00000000..45cc8f1c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/iffifo_gen.sh
@@ -0,0 +1,8 @@
+# Copyright EPFL contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+echo "Generating RTL"
+${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py -r -t rtl data/iffifo.hjson
+echo "Generating SW"
+${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py --cdefines -o ../../../sw/device/lib/drivers/iffifo/iffifo_regs.h data/iffifo.hjson
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo.sv
new file mode 100644
index 00000000..35a6b008
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo.sv
@@ -0,0 +1,115 @@
+// Copyright 2023 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Author: Pierre Guillod <pierre.guillod@epfl.ch>, EPFL, STI-SEL
+// Date: 18.10.2023
+
+module iffifo #(
+    parameter type reg_req_t = logic,
+    parameter type reg_rsp_t = logic,
+    localparam int WIDTH = 32,
+    localparam int DEPTH = 4,
+    localparam int DEPTHw = $clog2(DEPTH + 1)
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input reg_req_t reg_req_i,
+    output reg_rsp_t reg_rsp_o,
+
+    // DMA slots
+    output logic iffifo_in_ready_o,
+    output logic iffifo_out_valid_o,
+
+    // Interrupt lines
+    output logic iffifo_int_o
+);
+
+  import iffifo_reg_pkg::*;
+
+  iffifo_reg2hw_t reg2hw;
+  iffifo_hw2reg_t hw2reg;
+
+  logic [WIDTH-1:0] fifout;
+  logic [DEPTHw-1:0] occupancy;
+  logic empty, full, reached, available;
+
+  assign hw2reg.fifo_out.d = fifout + 1;
+
+  // Status (full/empty/watermark) reporting circuitry
+  assign empty = (occupancy == 0);
+  assign available = !empty;
+  assign hw2reg.status.empty.de = 1;
+  assign hw2reg.status.empty.d = empty;
+  assign hw2reg.status.available.de = 1;
+  assign hw2reg.status.available.d = available;
+  assign hw2reg.status.full.de = 1;
+  assign hw2reg.status.full.d = full;
+  assign hw2reg.status.reached.de = 1;
+  assign hw2reg.status.reached.d = reached;
+  assign hw2reg.occupancy.de = 1;
+  assign hw2reg.occupancy.d = {{32 - DEPTHw{1'b0}}, occupancy};
+  assign reached = ({{32 - DEPTHw{1'b0}}, occupancy} >= reg2hw.watermark.q);
+
+  // Interrupts circuitry
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (~rst_ni) begin
+
+      iffifo_int_o <= 0;
+
+    end else begin
+
+      // Interrupts firing
+      if (reached & reg2hw.interrupts.q) begin
+        iffifo_int_o <= 1;
+      end
+
+      // Interrupts assertion
+      if (reg2hw.interrupts.qe) begin
+        iffifo_int_o <= 0;
+      end
+
+    end
+  end
+
+  iffifo_reg_top #(
+      .reg_req_t(reg_req_t),
+      .reg_rsp_t(reg_rsp_t)
+  ) iffifo_reg_top_i (
+      .clk_i,
+      .rst_ni,
+      .reg2hw,
+      .hw2reg,
+      .reg_req_i,
+      .reg_rsp_o,
+      .devmode_i(1'b0)
+  );
+
+  prim_fifo_sync #(
+      .Width(WIDTH),
+      .Depth(DEPTH),
+      .Pass(1'b0),
+      .OutputZeroIfEmpty(1'b0)
+  ) iffifo_fifo_i (
+
+      .clk_i,
+      .rst_ni,
+      .clr_i(1'b0),
+
+      // From DMA (output) to FIFO (input, TX)
+      .wvalid_i(reg2hw.fifo_in.qe),
+      .wready_o(iffifo_in_ready_o),
+      .wdata_i (reg2hw.fifo_in.q),
+
+      // From FIFO (output) to DMA (input, RX)
+      .rvalid_o(iffifo_out_valid_o),
+      .rready_i(reg2hw.fifo_out.re),
+      .rdata_o (fifout),
+
+      .full_o (full),
+      .depth_o(occupancy)
+
+  );
+
+endmodule : iffifo
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv
new file mode 100644
index 00000000..e362798d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv
@@ -0,0 +1,106 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package iffifo_reg_pkg;
+
+  // Address widths within the block
+  parameter int BlockAw = 5;
+
+  ////////////////////////////
+  // Typedefs for registers //
+  ////////////////////////////
+
+  typedef struct packed {
+    logic [31:0] q;
+    logic        re;
+  } iffifo_reg2hw_fifo_out_reg_t;
+
+  typedef struct packed {
+    logic [31:0] q;
+    logic        qe;
+  } iffifo_reg2hw_fifo_in_reg_t;
+
+  typedef struct packed {logic [31:0] q;} iffifo_reg2hw_watermark_reg_t;
+
+  typedef struct packed {
+    logic q;
+    logic qe;
+  } iffifo_reg2hw_interrupts_reg_t;
+
+  typedef struct packed {logic [31:0] d;} iffifo_hw2reg_fifo_out_reg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic d;
+      logic de;
+    } empty;
+    struct packed {
+      logic d;
+      logic de;
+    } available;
+    struct packed {
+      logic d;
+      logic de;
+    } reached;
+    struct packed {
+      logic d;
+      logic de;
+    } full;
+  } iffifo_hw2reg_status_reg_t;
+
+  typedef struct packed {
+    logic [31:0] d;
+    logic        de;
+  } iffifo_hw2reg_occupancy_reg_t;
+
+  // Register -> HW type
+  typedef struct packed {
+    iffifo_reg2hw_fifo_out_reg_t fifo_out;  // [99:67]
+    iffifo_reg2hw_fifo_in_reg_t fifo_in;  // [66:34]
+    iffifo_reg2hw_watermark_reg_t watermark;  // [33:2]
+    iffifo_reg2hw_interrupts_reg_t interrupts;  // [1:0]
+  } iffifo_reg2hw_t;
+
+  // HW -> register type
+  typedef struct packed {
+    iffifo_hw2reg_fifo_out_reg_t fifo_out;  // [72:41]
+    iffifo_hw2reg_status_reg_t status;  // [40:33]
+    iffifo_hw2reg_occupancy_reg_t occupancy;  // [32:0]
+  } iffifo_hw2reg_t;
+
+  // Register offsets
+  parameter logic [BlockAw-1:0] IFFIFO_FIFO_OUT_OFFSET = 5'h0;
+  parameter logic [BlockAw-1:0] IFFIFO_FIFO_IN_OFFSET = 5'h4;
+  parameter logic [BlockAw-1:0] IFFIFO_STATUS_OFFSET = 5'h8;
+  parameter logic [BlockAw-1:0] IFFIFO_OCCUPANCY_OFFSET = 5'hc;
+  parameter logic [BlockAw-1:0] IFFIFO_WATERMARK_OFFSET = 5'h10;
+  parameter logic [BlockAw-1:0] IFFIFO_INTERRUPTS_OFFSET = 5'h14;
+
+  // Reset values for hwext registers and their fields
+  parameter logic [31:0] IFFIFO_FIFO_OUT_RESVAL = 32'h0;
+
+  // Register index
+  typedef enum int {
+    IFFIFO_FIFO_OUT,
+    IFFIFO_FIFO_IN,
+    IFFIFO_STATUS,
+    IFFIFO_OCCUPANCY,
+    IFFIFO_WATERMARK,
+    IFFIFO_INTERRUPTS
+  } iffifo_id_e;
+
+  // Register width information to check illegal writes
+  parameter logic [3:0] IFFIFO_PERMIT[6] = '{
+      4'b1111,  // index[0] IFFIFO_FIFO_OUT
+      4'b1111,  // index[1] IFFIFO_FIFO_IN
+      4'b0001,  // index[2] IFFIFO_STATUS
+      4'b1111,  // index[3] IFFIFO_OCCUPANCY
+      4'b1111,  // index[4] IFFIFO_WATERMARK
+      4'b0001  // index[5] IFFIFO_INTERRUPTS
+  };
+
+endpackage
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv
new file mode 100644
index 00000000..cd8d2f56
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv
@@ -0,0 +1,451 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+
+`include "common_cells/assertions.svh"
+
+module iffifo_reg_top #(
+    parameter type reg_req_t = logic,
+    parameter type reg_rsp_t = logic,
+    parameter int AW = 5
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input reg_req_t reg_req_i,
+    output reg_rsp_t reg_rsp_o,
+    // To HW
+    output iffifo_reg_pkg::iffifo_reg2hw_t reg2hw,  // Write
+    input iffifo_reg_pkg::iffifo_hw2reg_t hw2reg,  // Read
+
+
+    // Config
+    input devmode_i  // If 1, explicit error return for unmapped register access
+);
+
+  import iffifo_reg_pkg::*;
+
+  localparam int DW = 32;
+  localparam int DBW = DW / 8;  // Byte Width
+
+  // register signals
+  logic           reg_we;
+  logic           reg_re;
+  logic [ AW-1:0] reg_addr;
+  logic [ DW-1:0] reg_wdata;
+  logic [DBW-1:0] reg_be;
+  logic [ DW-1:0] reg_rdata;
+  logic           reg_error;
+
+  logic addrmiss, wr_err;
+
+  logic [DW-1:0] reg_rdata_next;
+
+  // Below register interface can be changed
+  reg_req_t reg_intf_req;
+  reg_rsp_t reg_intf_rsp;
+
+
+  assign reg_intf_req = reg_req_i;
+  assign reg_rsp_o = reg_intf_rsp;
+
+
+  assign reg_we = reg_intf_req.valid & reg_intf_req.write;
+  assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
+  assign reg_addr = reg_intf_req.addr;
+  assign reg_wdata = reg_intf_req.wdata;
+  assign reg_be = reg_intf_req.wstrb;
+  assign reg_intf_rsp.rdata = reg_rdata;
+  assign reg_intf_rsp.error = reg_error;
+  assign reg_intf_rsp.ready = 1'b1;
+
+  assign reg_rdata = reg_rdata_next;
+  assign reg_error = (devmode_i & addrmiss) | wr_err;
+
+
+  // Define SW related signals
+  // Format: <reg>_<field>_{wd|we|qs}
+  //        or <reg>_{wd|we|qs} if field == 1 or 0
+  logic [31:0] fifo_out_qs;
+  logic fifo_out_re;
+  logic [31:0] fifo_in_qs;
+  logic [31:0] fifo_in_wd;
+  logic fifo_in_we;
+  logic status_empty_qs;
+  logic status_available_qs;
+  logic status_reached_qs;
+  logic status_full_qs;
+  logic [31:0] occupancy_qs;
+  logic [31:0] watermark_qs;
+  logic [31:0] watermark_wd;
+  logic watermark_we;
+  logic interrupts_qs;
+  logic interrupts_wd;
+  logic interrupts_we;
+
+  // Register instances
+  // R[fifo_out]: V(True)
+
+  prim_subreg_ext #(
+      .DW(32)
+  ) u_fifo_out (
+      .re (fifo_out_re),
+      .we (1'b0),
+      .wd ('0),
+      .d  (hw2reg.fifo_out.d),
+      .qre(reg2hw.fifo_out.re),
+      .qe (),
+      .q  (reg2hw.fifo_out.q),
+      .qs (fifo_out_qs)
+  );
+
+
+  // R[fifo_in]: V(False)
+
+  prim_subreg #(
+      .DW      (32),
+      .SWACCESS("RW"),
+      .RESVAL  (32'h0)
+  ) u_fifo_in (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(fifo_in_we),
+      .wd(fifo_in_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.fifo_in.qe),
+      .q (reg2hw.fifo_in.q),
+
+      // to register interface (read)
+      .qs(fifo_in_qs)
+  );
+
+
+  // R[status]: V(False)
+
+  //   F[empty]: 0:0
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RO"),
+      .RESVAL  (1'h0)
+  ) u_status_empty (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      .we(1'b0),
+      .wd('0),
+
+      // from internal hardware
+      .de(hw2reg.status.empty.de),
+      .d (hw2reg.status.empty.d),
+
+      // to internal hardware
+      .qe(),
+      .q (),
+
+      // to register interface (read)
+      .qs(status_empty_qs)
+  );
+
+
+  //   F[available]: 1:1
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RO"),
+      .RESVAL  (1'h0)
+  ) u_status_available (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      .we(1'b0),
+      .wd('0),
+
+      // from internal hardware
+      .de(hw2reg.status.available.de),
+      .d (hw2reg.status.available.d),
+
+      // to internal hardware
+      .qe(),
+      .q (),
+
+      // to register interface (read)
+      .qs(status_available_qs)
+  );
+
+
+  //   F[reached]: 2:2
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RO"),
+      .RESVAL  (1'h0)
+  ) u_status_reached (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      .we(1'b0),
+      .wd('0),
+
+      // from internal hardware
+      .de(hw2reg.status.reached.de),
+      .d (hw2reg.status.reached.d),
+
+      // to internal hardware
+      .qe(),
+      .q (),
+
+      // to register interface (read)
+      .qs(status_reached_qs)
+  );
+
+
+  //   F[full]: 3:3
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RO"),
+      .RESVAL  (1'h0)
+  ) u_status_full (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      .we(1'b0),
+      .wd('0),
+
+      // from internal hardware
+      .de(hw2reg.status.full.de),
+      .d (hw2reg.status.full.d),
+
+      // to internal hardware
+      .qe(),
+      .q (),
+
+      // to register interface (read)
+      .qs(status_full_qs)
+  );
+
+
+  // R[occupancy]: V(False)
+
+  prim_subreg #(
+      .DW      (32),
+      .SWACCESS("RO"),
+      .RESVAL  (32'h0)
+  ) u_occupancy (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      .we(1'b0),
+      .wd('0),
+
+      // from internal hardware
+      .de(hw2reg.occupancy.de),
+      .d (hw2reg.occupancy.d),
+
+      // to internal hardware
+      .qe(),
+      .q (),
+
+      // to register interface (read)
+      .qs(occupancy_qs)
+  );
+
+
+  // R[watermark]: V(False)
+
+  prim_subreg #(
+      .DW      (32),
+      .SWACCESS("RW"),
+      .RESVAL  (32'h0)
+  ) u_watermark (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(watermark_we),
+      .wd(watermark_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.watermark.q),
+
+      // to register interface (read)
+      .qs(watermark_qs)
+  );
+
+
+  // R[interrupts]: V(False)
+
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RW"),
+      .RESVAL  (1'h0)
+  ) u_interrupts (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(interrupts_we),
+      .wd(interrupts_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.interrupts.qe),
+      .q (reg2hw.interrupts.q),
+
+      // to register interface (read)
+      .qs(interrupts_qs)
+  );
+
+
+
+
+  logic [5:0] addr_hit;
+  always_comb begin
+    addr_hit = '0;
+    addr_hit[0] = (reg_addr == IFFIFO_FIFO_OUT_OFFSET);
+    addr_hit[1] = (reg_addr == IFFIFO_FIFO_IN_OFFSET);
+    addr_hit[2] = (reg_addr == IFFIFO_STATUS_OFFSET);
+    addr_hit[3] = (reg_addr == IFFIFO_OCCUPANCY_OFFSET);
+    addr_hit[4] = (reg_addr == IFFIFO_WATERMARK_OFFSET);
+    addr_hit[5] = (reg_addr == IFFIFO_INTERRUPTS_OFFSET);
+  end
+
+  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0;
+
+  // Check sub-word write is permitted
+  always_comb begin
+    wr_err = (reg_we &
+              ((addr_hit[0] & (|(IFFIFO_PERMIT[0] & ~reg_be))) |
+               (addr_hit[1] & (|(IFFIFO_PERMIT[1] & ~reg_be))) |
+               (addr_hit[2] & (|(IFFIFO_PERMIT[2] & ~reg_be))) |
+               (addr_hit[3] & (|(IFFIFO_PERMIT[3] & ~reg_be))) |
+               (addr_hit[4] & (|(IFFIFO_PERMIT[4] & ~reg_be))) |
+               (addr_hit[5] & (|(IFFIFO_PERMIT[5] & ~reg_be)))));
+  end
+
+  assign fifo_out_re = addr_hit[0] & reg_re & !reg_error;
+
+  assign fifo_in_we = addr_hit[1] & reg_we & !reg_error;
+  assign fifo_in_wd = reg_wdata[31:0];
+
+  assign watermark_we = addr_hit[4] & reg_we & !reg_error;
+  assign watermark_wd = reg_wdata[31:0];
+
+  assign interrupts_we = addr_hit[5] & reg_we & !reg_error;
+  assign interrupts_wd = reg_wdata[0];
+
+  // Read data return
+  always_comb begin
+    reg_rdata_next = '0;
+    unique case (1'b1)
+      addr_hit[0]: begin
+        reg_rdata_next[31:0] = fifo_out_qs;
+      end
+
+      addr_hit[1]: begin
+        reg_rdata_next[31:0] = fifo_in_qs;
+      end
+
+      addr_hit[2]: begin
+        reg_rdata_next[0] = status_empty_qs;
+        reg_rdata_next[1] = status_available_qs;
+        reg_rdata_next[2] = status_reached_qs;
+        reg_rdata_next[3] = status_full_qs;
+      end
+
+      addr_hit[3]: begin
+        reg_rdata_next[31:0] = occupancy_qs;
+      end
+
+      addr_hit[4]: begin
+        reg_rdata_next[31:0] = watermark_qs;
+      end
+
+      addr_hit[5]: begin
+        reg_rdata_next[0] = interrupts_qs;
+      end
+
+      default: begin
+        reg_rdata_next = '1;
+      end
+    endcase
+  end
+
+  // Unused signal tieoff
+
+  // wdata / byte enable are not always fully used
+  // add a blanket unused statement to handle lint waivers
+  logic unused_wdata;
+  logic unused_be;
+  assign unused_wdata = ^reg_wdata;
+  assign unused_be = ^reg_be;
+
+  // Assertions for Register Interface
+  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+
+endmodule
+
+module iffifo_reg_top_intf #(
+    parameter  int AW = 5,
+    localparam int DW = 32
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    REG_BUS.in regbus_slave,
+    // To HW
+    output iffifo_reg_pkg::iffifo_reg2hw_t reg2hw,  // Write
+    input iffifo_reg_pkg::iffifo_hw2reg_t hw2reg,  // Read
+    // Config
+    input devmode_i  // If 1, explicit error return for unmapped register access
+);
+  localparam int unsigned STRB_WIDTH = DW / 8;
+
+  `include "register_interface/typedef.svh"
+  `include "register_interface/assign.svh"
+
+  // Define structs for reg_bus
+  typedef logic [AW-1:0] addr_t;
+  typedef logic [DW-1:0] data_t;
+  typedef logic [STRB_WIDTH-1:0] strb_t;
+  `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)
+
+  reg_bus_req_t s_reg_req;
+  reg_bus_rsp_t s_reg_rsp;
+
+  // Assign SV interface to structs
+  `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
+  `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
+
+
+
+  iffifo_reg_top #(
+      .reg_req_t(reg_bus_req_t),
+      .reg_rsp_t(reg_bus_rsp_t),
+      .AW(AW)
+  ) i_regs (
+      .clk_i,
+      .rst_ni,
+      .reg_req_i(s_reg_req),
+      .reg_rsp_o(s_reg_rsp),
+      .reg2hw,  // Write
+      .hw2reg,  // Read
+      .devmode_i
+  );
+
+endmodule
+
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.core b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.core
new file mode 100644
index 00000000..2ef913ea
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.core
@@ -0,0 +1,22 @@
+CAPI=2:
+
+name: "example:ip:simple_accelerator"
+description: "core-v-mini-mcu iffifo peripheral"
+
+# Copyright 2024 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# Author: Davide Schiavone <davide.schiavone@epfl.ch>, EPFL, STI-SEL
+# Date: 12.02.2024
+
+filesets:
+  files_rtl:
+    files:
+    - simple_accelerator.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+    - files_rtl
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.sv
new file mode 100644
index 00000000..846775af
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.sv
@@ -0,0 +1,421 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+module simple_accelerator #(
+    parameter int unsigned FIFO_DEPTH = 4,
+    parameter type reg_req_t = logic,
+    parameter type reg_rsp_t = logic,
+    parameter type obi_req_t = logic,
+    parameter type obi_resp_t = logic
+) (
+    input logic clk_i,
+    input logic rst_ni,
+
+    input  reg_req_t reg_req_i,
+    output reg_rsp_t reg_rsp_o,
+
+    output obi_req_t  acc_read_ch0_req_o,
+    input  obi_resp_t acc_read_ch0_resp_i,
+
+    output obi_req_t  acc_write_ch0_req_o,
+    input  obi_resp_t acc_write_ch0_resp_i
+
+);
+
+
+
+  logic status_ready_d, status_ready_q, status_start_q;
+  logic [31:0] address_read_q, address_write_q;
+  logic [31:0] threshold_q;
+  logic [ 9:0] size_q;
+
+  localparam int unsigned LastFifoUsage = FIFO_DEPTH - 1;
+  localparam int unsigned Addr_Fifo_Depth = (FIFO_DEPTH > 1) ? $clog2(FIFO_DEPTH) : 1;
+
+
+  logic [               31:0] read_ptr_reg;
+  logic [               31:0] read_ptr_valid_reg;
+  logic [               31:0] write_ptr_reg;
+  logic [               31:0] write_address;
+  logic [                9:0] dma_cnt;
+  logic                       dma_start;
+  logic                       dma_done;
+
+
+  logic [Addr_Fifo_Depth-1:0] fifo_usage;
+  logic                       fifo_alm_full;
+
+  logic                       data_in_req;
+  logic                       data_in_we;
+  logic [                3:0] data_in_be;
+  logic [               31:0] data_in_addr;
+  logic                       data_in_gnt;
+  logic                       data_in_rvalid;
+  logic [               31:0] data_in_rdata;
+
+  logic                       data_out_req;
+  logic                       data_out_we;
+  logic [                3:0] data_out_be;
+  logic [               31:0] data_out_addr;
+  logic [               31:0] data_out_wdata;
+  logic                       data_out_gnt;
+
+  logic                       fifo_flush;
+  logic                       fifo_full;
+  logic                       fifo_empty;
+
+
+  logic [               31:0] fifo_input;
+  logic [               31:0] fifo_output;
+
+  logic [                3:0] byte_enable_out;
+
+  logic                       dma_start_pending;
+
+  enum {
+    DMA_READY,
+    DMA_STARTING,
+    DMA_RUNNING
+  }
+      dma_state_q, dma_state_d;
+
+  logic [Addr_Fifo_Depth-1:0] outstanding_req;
+
+  enum logic {
+    DMA_READ_FSM_IDLE,
+    DMA_READ_FSM_ON
+  }
+      dma_read_fsm_state, dma_read_fsm_n_state;
+
+  enum logic {
+    DMA_WRITE_FSM_IDLE,
+    DMA_WRITE_FSM_ON
+  }
+      dma_write_fsm_state, dma_write_fsm_n_state;
+
+  assign acc_read_ch0_req_o.req = data_in_req;
+  assign acc_read_ch0_req_o.we = data_in_we;
+  assign acc_read_ch0_req_o.be = data_in_be;
+  assign acc_read_ch0_req_o.addr = data_in_addr;
+  assign acc_read_ch0_req_o.wdata = 32'h0;
+
+  assign data_in_gnt = acc_read_ch0_resp_i.gnt;
+  assign data_in_rvalid = acc_read_ch0_resp_i.rvalid;
+  assign data_in_rdata = acc_read_ch0_resp_i.rdata;
+
+  assign acc_write_ch0_req_o.req = data_out_req;
+  assign acc_write_ch0_req_o.we = data_out_we;
+  assign acc_write_ch0_req_o.be = data_out_be;
+  assign acc_write_ch0_req_o.addr = data_out_addr;
+
+  //complete the function
+  assign acc_write_ch0_req_o.wdata = data_out_wdata > threshold_q ? data_out_wdata : threshold_q;
+  //assign acc_write_ch0_req_o.wdata = data_out_wdata;
+
+  assign data_out_gnt = acc_write_ch0_resp_i.gnt;
+
+  assign status_ready_d = (dma_state_q == DMA_READY);
+
+  assign write_address = write_ptr_reg;
+
+  assign fifo_alm_full = (fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
+
+  assign dma_start = (dma_state_q == DMA_STARTING);
+
+  //decoder
+
+  //0 READ ADDRESS
+  //4 WRITE ADDRESS
+  //8 THRESHOLD
+  //C READY
+  //10 SIZE
+  //14 START
+  always_comb begin
+    reg_rsp_o.rdata = '0;
+    reg_rsp_o.error = 1'b0;
+    reg_rsp_o.ready = 1'b1;
+
+    if (reg_req_i.valid) begin
+      if (reg_req_i.addr[7:0] == 8'h14) begin
+        reg_rsp_o.rdata = {31'h0, status_start_q};
+      end
+      if (reg_req_i.addr[7:0] == 8'h10) begin
+        reg_rsp_o.rdata = {22'h0, size_q};
+      end
+      if (reg_req_i.addr[7:0] == 8'hC) begin
+        reg_rsp_o.rdata = {31'h0, status_ready_q};
+      end
+      if (reg_req_i.addr[7:0] == 8'h8) begin
+        reg_rsp_o.rdata = threshold_q;
+      end
+      if (reg_req_i.addr[7:0] == 8'h4) begin
+        reg_rsp_o.rdata = address_write_q;
+      end
+      if (reg_req_i.addr[7:0] == 8'h0) begin
+        reg_rsp_o.rdata = address_read_q;
+      end
+    end
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (~rst_ni) begin
+      status_start_q <= '0;
+      size_q <= '0;
+      status_ready_q <= '0;
+      threshold_q <= '0;
+      address_write_q <= '0;
+      address_read_q <= '0;
+    end else begin
+      if (reg_req_i.valid && reg_req_i.write) begin
+        if (reg_req_i.addr[7:0] == 8'h14) begin
+          status_start_q <= reg_req_i.wdata[0];
+        end
+        if (reg_req_i.addr[7:0] == 8'h10) begin
+          size_q <= reg_req_i.wdata[9:0];
+        end
+        if (reg_req_i.addr[7:0] == 8'hC) begin
+          status_ready_q <= reg_req_i.wdata[0];
+        end
+        if (reg_req_i.addr[7:0] == 8'h8) begin
+          threshold_q <= reg_req_i.wdata;
+        end
+        if (reg_req_i.addr[7:0] == 8'h4) begin
+          address_write_q <= reg_req_i.wdata;
+        end
+        if (reg_req_i.addr[7:0] == 8'h0) begin
+          address_read_q <= reg_req_i.wdata;
+        end
+      end else begin
+        if (dma_done) status_ready_q <= 1'b1;
+        status_start_q <= '0;
+      end
+    end
+  end
+
+
+  //
+  // Main DMA state machine
+  //
+  // READY   : idle, waiting for a write pulse to size registered in `dma_start_pending`
+  // STARTING: load transaction data
+  // RUNNING : waiting for transaction finish
+  //           when `dma_done` rises either enter ready or restart in circular mode
+  //
+  always_comb begin
+    dma_state_d = dma_state_q;
+    case (dma_state_q)
+      DMA_READY: begin
+        if (dma_start_pending) begin
+          dma_state_d = DMA_STARTING;
+        end
+      end
+      DMA_STARTING: begin
+        dma_state_d = DMA_RUNNING;
+      end
+      DMA_RUNNING: begin
+        if (dma_done) begin
+          dma_state_d = DMA_READY;
+        end
+      end
+    endcase
+  end
+
+  // update state
+  always_ff @(posedge clk_i, negedge rst_ni) begin
+    if (~rst_ni) begin
+      dma_state_q <= DMA_READY;
+    end else begin
+      dma_state_q <= dma_state_d;
+    end
+  end
+
+
+  // DMA pulse start when dma_start register is written
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_start
+    if (~rst_ni) begin
+      dma_start_pending <= 1'b0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        dma_start_pending <= 1'b0;
+      end else if (status_start_q && size_q != '0) begin
+        dma_start_pending <= 1'b1;
+      end
+    end
+  end
+
+  // Store input data pointer and increment everytime read request is granted
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_in_reg
+    if (~rst_ni) begin
+      read_ptr_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        read_ptr_reg <= address_read_q;
+      end else if (data_in_gnt == 1'b1) begin
+        read_ptr_reg <= read_ptr_reg + 32'h4;
+      end
+    end
+  end
+
+  // Only update read_ptr_valid_reg when the data is stored in the fifo
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_valid_in_reg
+    if (~rst_ni) begin
+      read_ptr_valid_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        read_ptr_valid_reg <= address_read_q;
+      end else if (data_in_rvalid == 1'b1) begin
+        read_ptr_valid_reg <= read_ptr_valid_reg + 32'h4;
+      end
+    end
+  end
+
+  // Store output data pointer and increment everytime write request is granted
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_out_reg
+    if (~rst_ni) begin
+      write_ptr_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        write_ptr_reg <= address_write_q;
+      end else if (data_out_gnt == 1'b1) begin
+        write_ptr_reg <= write_ptr_reg + 32'h4;
+      end
+    end
+  end
+
+  // Store dma transfer size and decrement it everytime input data rvalid is asserted
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_cnt_reg
+    if (~rst_ni) begin
+      dma_cnt <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        dma_cnt <= size_q;
+      end else if (data_in_gnt == 1'b1) begin
+        dma_cnt <= dma_cnt - 10'h1;
+      end
+    end
+  end
+
+  assign byte_enable_out = 4'b1111;
+
+  assign data_out_wdata = fifo_output;
+
+  assign fifo_input = data_in_rdata;
+
+  // FSM state update
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_fsm_state
+    if (~rst_ni) begin
+      dma_read_fsm_state <= DMA_READ_FSM_IDLE;
+      dma_write_fsm_state <= DMA_WRITE_FSM_IDLE;
+      outstanding_req <= '0;
+    end else begin
+      dma_read_fsm_state <= dma_read_fsm_n_state;
+      dma_write_fsm_state <= dma_write_fsm_n_state;
+      outstanding_req <= outstanding_req + (data_in_req && data_in_gnt) - data_in_rvalid;
+    end
+  end
+
+  // Read master FSM
+  always_comb begin : proc_dma_read_fsm_logic
+
+    dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+
+    data_in_req = '0;
+    data_in_we = '0;
+    data_in_be = '0;
+    data_in_addr = '0;
+
+    fifo_flush = 1'b0;
+
+    unique case (dma_read_fsm_state)
+
+      DMA_READ_FSM_IDLE: begin
+        // Wait for start signal
+        if (dma_start == 1'b1) begin
+          dma_read_fsm_n_state = DMA_READ_FSM_ON;
+          fifo_flush = 1'b1;
+        end else begin
+          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+        end
+      end
+      // Read one word
+      DMA_READ_FSM_ON: begin
+        // If all input data read exit
+        if (|dma_cnt == 1'b0) begin
+          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+        end else begin
+          dma_read_fsm_n_state = DMA_READ_FSM_ON;
+          // Wait if fifo is full, almost full (last data)
+          if (fifo_full == 1'b0 && fifo_alm_full == 1'b0) begin
+            data_in_req  = 1'b1;
+            data_in_we   = 1'b0;
+            data_in_be   = 4'b1111;  // always read all bytes
+            data_in_addr = read_ptr_reg;
+          end
+        end
+      end
+    endcase
+  end
+
+  // Write master FSM
+  always_comb begin : proc_dma_write_fsm_logic
+
+    dma_write_fsm_n_state = DMA_WRITE_FSM_IDLE;
+    dma_done = 1'b0;
+
+    data_out_req = '0;
+    data_out_we = '0;
+    data_out_be = '0;
+    data_out_addr = '0;
+
+    unique case (dma_write_fsm_state)
+
+      DMA_WRITE_FSM_IDLE: begin
+        // Wait for start signal
+        if (dma_start == 1'b1) begin
+          dma_write_fsm_n_state = DMA_WRITE_FSM_ON;
+        end else begin
+          dma_write_fsm_n_state = DMA_WRITE_FSM_IDLE;
+        end
+      end
+      // Read one word
+      DMA_WRITE_FSM_ON: begin
+        // If all input data read exit
+        if (fifo_empty == 1'b1 && dma_read_fsm_state == DMA_READ_FSM_IDLE) begin
+          dma_done = outstanding_req == '0;
+          dma_write_fsm_n_state = dma_done ? DMA_WRITE_FSM_IDLE : DMA_WRITE_FSM_ON;
+        end else begin
+          dma_write_fsm_n_state = DMA_WRITE_FSM_ON;
+          // Wait if fifo is empty
+          if (fifo_empty == 1'b0) begin
+            data_out_req  = 1'b1;
+            data_out_we   = 1'b1;
+            data_out_be   = byte_enable_out;
+            data_out_addr = write_address;
+          end
+        end
+      end
+    endcase
+  end
+
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH)
+  ) dma_fifo_i (
+      .clk_i,
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(fifo_full),
+      .empty_o(fifo_empty),
+      .usage_o(fifo_usage),
+      // as long as the queue is not full we can push new data
+      .data_i(fifo_input),
+      .push_i(data_in_rvalid),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(fifo_output),
+      .pop_i(data_out_gnt)
+  );
+
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.vlt b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.vlt
new file mode 100644
index 00000000..ac1ea03e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/simple_accelerator/simple_accelerator.vlt
@@ -0,0 +1,10 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Author: Davide Schiavone <davide.schiavone@epfl.ch>, EPFL, STI-SEL
+// Date: 12.02.2024
+
+`verilator_config
+
+lint_off -rule UNUSED -file "*/simple_accelerator/simple_accelerator.sv" -match "*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/slow_memory/rtl/slow_memory.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/slow_memory/rtl/slow_memory.sv
index 785ddd46..6cedd80a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/slow_memory/rtl/slow_memory.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/slow_memory/rtl/slow_memory.sv
@@ -79,12 +79,21 @@ module slow_memory #(
 
 
   always_comb begin
-    gnt_o = 1'b0;
-    rvalid_o = rvalid_q;
-    state_n = state_q;
-    counter_n = counter_q - 1;
-    rvalid_n = rvalid_q;
-
+    gnt_o       = 1'b0;
+    rvalid_o    = rvalid_q;
+    state_n     = state_q;
+    counter_n   = counter_q - 1;
+    rvalid_n    = rvalid_q;
+    mem_req     = '0;
+    mem_we      = '0;
+    mem_addr    = '0;
+    mem_wdata   = '0;
+    mem_be      = '0;
+    mem_req_n   = mem_req_q;
+    mem_we_n    = mem_we_q;
+    mem_addr_n  = mem_addr_q;
+    mem_wdata_n = mem_wdata_q;
+    mem_be_n    = mem_be_q;
     unique case (state_q)
 
       READY: begin
@@ -92,13 +101,13 @@ module slow_memory #(
         if (req_i) begin
           gnt_o = random1[0];
           if (gnt_o) begin
-            state_n   = WAIT_RVALID;
-            counter_n = random2[4:0] + 1;
-            mem_req_n <= req_i;
-            mem_we_n <= we_i;
-            mem_addr_n <= addr_i;
-            mem_wdata_n <= wdata_i;
-            mem_be_n <= be_i;
+            state_n     = WAIT_RVALID;
+            counter_n   = random2[4:0] + 1;
+            mem_req_n   = req_i;
+            mem_we_n    = we_i;
+            mem_addr_n  = addr_i;
+            mem_wdata_n = wdata_i;
+            mem_be_n    = be_i;
           end
         end
       end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
index 7d58ed79..c88bdaca 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
@@ -48,6 +48,9 @@ module x_heep_system
 
     output logic [31:0] exit_value_o,
 
+    input logic ext_dma_slot_tx_i,
+    input logic ext_dma_slot_rx_i,
+
     // eXtension interface
     if_xif.cpu_compressed xif_compressed_if,
     if_xif.cpu_issue      xif_issue_if,
@@ -137,7 +140,9 @@ ${pad.core_v_mini_mcu_bonding}
     .external_subsystem_rst_no,
     .external_ram_banks_set_retentive_no,
     .external_subsystem_clkgate_en_no,
-    .exit_value_o
+    .exit_value_o,
+    .ext_dma_slot_tx_i,
+    .ext_dma_slot_rx_i
   );
 
   pad_ring pad_ring_i (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.core
index 56a485a4..a31337d1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.core
@@ -60,3 +60,4 @@ targets:
     - files_rtl
     - ff_regfile
     - target_sim? (files_clk_gate)
+    - target_sim_sc? (files_clk_gate)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
index 39f77e7a..7248758f 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/cv32e40px.git
-    rev: acf3442b414725191fb7a2027facd0b5b4123c1c
+    rev: 49770e7dd5d569f440810866f4f33ce6a4f7ef1f
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
index b261db04..547959fe 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
@@ -7,11 +7,9 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/cv32e40px.git",
-    rev: "acf3442b414725191fb7a2027facd0b5b4123c1c",
+    rev: "49770e7dd5d569f440810866f4f33ce6a4f7ef1f",
   },
 
-  patch_dir: "patches/esl_epfl_cv32e40px",
-
   exclude_from_upstream: [
     "ci",
     ".github",
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh
index 8c4ae99f..a89ed4e4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh
@@ -679,22 +679,22 @@ class instr_trace_t;
       // decode and print instruction
       case (instr[11:8])
         // cv.starti, cv.endi
-        4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, rd[0], imm_iz_type);
+        4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, instr[7], imm_iz_type);
         // cv.counti
-        4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, rd[0], imm_iz_type);
+        4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, instr[7], imm_iz_type);
         // cv.start, cv.end, cv.count
         4'b0001, 4'b0011, 4'b0101: begin
           regs_read.push_back('{rs1, rs1_value, 0});
-          str = $sformatf("%-16s %d, %s", mnemonic, rd[0], regAddrToStr(rs1));
+          str = $sformatf("%-16s %d, %s", mnemonic, instr[7], regAddrToStr(rs1));
         end
         // cv.setupi
         4'b0110: begin
-          str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, rd[0], imm_iz_type, rs1);
+          str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, instr[7], imm_iz_type, rs1);
         end
         // cv.setup
         4'b0111: begin
           regs_read.push_back('{rs1, rs1_value, 0});
-          str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, rd[0], regAddrToStr(rs1), imm_iz_type);
+          str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, instr[7], regAddrToStr(rs1), imm_iz_type);
         end
       endcase
     end
@@ -861,7 +861,7 @@ class instr_trace_t;
           endcase
           str_sci  = "";
         end
-  
+
         // shuffle/pack
         6'b110000: begin
           if (instr[14:12] == 3'b111) begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv
index 868de33c..4effb2b8 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv
@@ -73,6 +73,10 @@ module cv32e40px_rvfi
     input logic        is_compressed_id_i,
 
     input logic ebrk_insn_dec_i,
+    input logic ecall_insn_dec_i,
+
+    input logic mret_insn_dec_i,
+    input logic mret_dec_i,
 
     input logic [5:0] csr_cause_i,
 
@@ -126,6 +130,9 @@ module cv32e40px_rvfi
     input logic [31:0] data_wdata_ex_i,
     input logic        lsu_split_q_ex_i,
 
+    input logic mult_ready_i,
+    input logic alu_ready_i,
+
     //// WB probes ////
     input logic [31:0] pc_wb_i,
     input logic        wb_ready_i,
@@ -202,6 +209,7 @@ module cv32e40px_rvfi
     input logic            csr_we_i,
     input logic     [31:0] csr_wdata_int_i,
 
+    input logic    csr_fregs_we_i,
     input logic    csr_jvt_we_i,
     input Status_t csr_mstatus_n_i,
     input Status_t csr_mstatus_q_i,
@@ -617,6 +625,8 @@ module cv32e40px_rvfi
   logic pc_mux_interrupt;
   logic pc_mux_nmi;
 
+  localparam logic [31:0] MSTATUS_WRITE_MASK = 32'h0000_6088;
+
   `include "pipe_freeze_trace.sv"
 
   `include "insn_trace.sv"
@@ -633,6 +643,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
   logic   [2:0] saved_debug_cause;
   integer       next_send;
 
+  event         e_empty_queue;
   function void empty_fifo();
     integer i, trace_q_size;
     trace_q_size = wb_bypass_trace_q.size();
@@ -648,6 +659,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           new_rvfi_trace.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
           rvfi_trace_q.push_back(new_rvfi_trace);
           next_send = next_send + 1;
+          ->e_empty_queue;
         end else begin
           wb_bypass_trace_q.push_back(new_rvfi_trace);
         end
@@ -658,6 +670,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
   /*
    * Function used to alocate a new insn and send it to the rvfi driver
    */
+  event e_add_to_bypass;
   function void send_rvfi(insn_trace_t m_wb_insn);
     insn_trace_t new_rvfi_trace;
     new_rvfi_trace = new();
@@ -667,6 +680,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       next_send = next_send + 1;
     end else begin
       wb_bypass_trace_q.push_back(new_rvfi_trace);
+      ->e_add_to_bypass;
     end
     empty_fifo();
   endfunction
@@ -837,7 +851,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
     //CSR
     rvfi_csr_mstatus_rmask = new_rvfi_trace.m_csr.mstatus_rmask | new_rvfi_trace.m_csr.mstatus_fs_rmask;
-    rvfi_csr_mstatus_wmask = new_rvfi_trace.m_csr.mstatus_wmask;
+    rvfi_csr_mstatus_wmask = new_rvfi_trace.m_csr.mstatus_wmask & MSTATUS_WRITE_MASK;
     rvfi_csr_mstatus_wmask[31] = new_rvfi_trace.m_csr.mstatus_fs_wmask[31];
     rvfi_csr_mstatus_wmask[14:13] = new_rvfi_trace.m_csr.mstatus_fs_wmask[14:13];
 
@@ -870,7 +884,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     end
     rvfi_csr_mstatus_wdata[30:18] = '0;
     // MPRV is not implemented in the target configuration, writes to it are ignored
-    rvfi_csr_mstatus_wdata[17] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.mprv;
+    rvfi_csr_mstatus_wdata[17] = 1'b0;  //new_rvfi_trace.m_csr.mstatus_wdata.mprv;
     rvfi_csr_mstatus_wdata[16:15] = '0;
     if (FPU == 1 && ZFINX == 0) begin
       rvfi_csr_mstatus_wdata[14:13] = new_rvfi_trace.m_csr.mstatus_fs_wdata;
@@ -882,11 +896,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     rvfi_csr_mstatus_wdata[7] = new_rvfi_trace.m_csr.mstatus_wdata.mpie;
     rvfi_csr_mstatus_wdata[6:5] = '0;
     // UPIE is not implemented in the target configuration, writes to it are ignored
-    rvfi_csr_mstatus_wdata[4] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.upie;
+    rvfi_csr_mstatus_wdata[4] = 1'b0;  //new_rvfi_trace.m_csr.mstatus_wdata.upie;
     rvfi_csr_mstatus_wdata[3] = new_rvfi_trace.m_csr.mstatus_wdata.mie;
     rvfi_csr_mstatus_wdata[2:1] = '0;
     // UIE is not implemented in the target configuration, writes to it are ignored
-    rvfi_csr_mstatus_wdata[0] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.uie;
+    rvfi_csr_mstatus_wdata[0] = 1'b0;  //new_rvfi_trace.m_csr.mstatus_wdata.uie;
 
     `SET_RVFI_CSR_FROM_INSN(misa)
     `SET_RVFI_CSR_FROM_INSN(mie)
@@ -1111,6 +1125,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
    * The third updates the rvfi interface
    */
   `define CSR_FROM_PIPE(TRACE_NAME, CSR_NAME) \
+    if(!trace_``TRACE_NAME``.m_csr.``CSR_NAME``_we) begin \
+      trace_``TRACE_NAME``.m_csr.``CSR_NAME``_wdata   = r_pipe_freeze_trace.csr.``CSR_NAME``_n; \
+    end\
     if (r_pipe_freeze_trace.csr.``CSR_NAME``_we) begin \
       trace_``TRACE_NAME``.m_csr.``CSR_NAME``_we      = r_pipe_freeze_trace.csr.``CSR_NAME``_we; \
       trace_``TRACE_NAME``.m_csr.``CSR_NAME``_wdata   = r_pipe_freeze_trace.csr.``CSR_NAME``_n; \
@@ -1120,9 +1137,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     trace_``TRACE_NAME``.m_csr.``CSR_NAME``_rmask   = '1;
 
   event e_mstatus_to_id;
+  event e_fregs_dirty_1, e_fregs_dirty_2, e_fregs_dirty_3;
   function void mstatus_to_id();
     `CSR_FROM_PIPE(id, mstatus)
     `CSR_FROM_PIPE(id, mstatus_fs)
+    if(r_pipe_freeze_trace.csr.fregs_we && !r_pipe_freeze_trace.csr.mstatus_fs_we && !(r_pipe_freeze_trace.csr.we && r_pipe_freeze_trace.csr.mstatus_fs_we)) begin //writes happening in ex that needs to be reported to id
+      trace_id.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
+      ->e_fregs_dirty_2;
+    end
     ->e_mstatus_to_id;
   endfunction
   //those event are for debug purpose
@@ -1133,10 +1155,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       e_dev_commit_rf_to_ex_3,
       e_dev_commit_rf_to_ex_4,
       e_dev_commit_rf_to_ex_5;
-  event e_if_2_id_1, e_if_2_id_2;
+  event e_if_2_id_1, e_if_2_id_2, e_if_2_id_3;
   event e_ex_to_wb_1, e_ex_to_wb_2;
   event e_id_to_ex_1, e_id_to_ex_2;
   event e_commit_dpc;
+  event e_csr_in_ex, e_csr_irq;
 
   event e_send_rvfi_trace_apu_resp;
   event
@@ -1160,12 +1183,17 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     `CSR_FROM_PIPE(apu_resp, fcsr)
     `CSR_FROM_PIPE(apu_resp, fflags)
 
-    // `CSR_FROM_PIPE(apu_resp, mstatus)
     `CSR_FROM_PIPE(apu_resp, mstatus_fs)
 
-    if (r_pipe_freeze_trace.csr.mstatus_we) begin
+    if (r_pipe_freeze_trace.csr.mstatus_fs_we && (trace_id.m_order > trace_apu_resp.m_order)) begin
+      trace_id.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
+    end
+    if (r_pipe_freeze_trace.csr.mstatus_fs_we && (trace_ex.m_order > trace_apu_resp.m_order)) begin
       trace_ex.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
     end
+    if (r_pipe_freeze_trace.csr.mstatus_fs_we && (trace_wb.m_order > trace_apu_resp.m_order)) begin
+      trace_wb.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
+    end
   endfunction
 
   function void csr_to_apu_req();
@@ -1243,6 +1271,15 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
   bit s_is_irq_start;
   bit s_id_done;
   function void if_to_id();
+    if (trace_id.m_valid) begin
+      minstret_to_id();
+      `CSR_FROM_PIPE(id, misa)
+      `CSR_FROM_PIPE(id, tdata1)
+      `CSR_FROM_PIPE(id, tdata2)
+      tinfo_to_id();
+      `CSR_FROM_PIPE(id, mip)
+      send_rvfi(trace_id);
+    end
     trace_id.init(trace_if);
     trace_id.m_trap       = ~r_pipe_freeze_trace.minstret;
     trace_id.m_is_illegal = r_pipe_freeze_trace.is_illegal;
@@ -1280,34 +1317,40 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
     bit s_core_is_decoding;  // For readability, ctrl_fsm is DECODE or DECODE_HWLOOP
 
-    trace_if            = new();
-    trace_id            = new();
-    trace_ex            = new();
-    trace_wb            = new();
-    s_new_valid_insn    = 1'b0;
-    s_ex_valid_adjusted = 1'b0;
+    bit s_ex_reg_we_adjusted;  //ex_reg_we
+    bit s_rf_we_wb_adjusted;  //
+
+    trace_if             = new();
+    trace_id             = new();
+    trace_ex             = new();
+    trace_wb             = new();
+    s_new_valid_insn     = 1'b0;
+    s_ex_valid_adjusted  = 1'b0;
 
-    s_id_done           = 1'b0;
-    s_apu_wb_ok         = 1'b0;
-    s_apu_0_cycle_reps  = 1'b0;
+    s_id_done            = 1'b0;
+    s_apu_wb_ok          = 1'b0;
+    s_apu_0_cycle_reps   = 1'b0;
 
-    next_send           = 1;
-    cnt_data_req        = 0;
-    cnt_data_resp       = 0;
-    cnt_apu_req         = 0;
-    cnt_apu_resp        = 0;
-    csr_is_irq          = '0;
-    is_dbg_taken        = '0;
-    s_was_flush         = 1'b0;
+    next_send            = 1;
+    cnt_data_req         = 0;
+    cnt_data_resp        = 0;
+    cnt_apu_req          = 0;
+    cnt_apu_resp         = 0;
+    csr_is_irq           = '0;
+    is_dbg_taken         = '0;
+    s_was_flush          = 1'b0;
 
-    s_is_pc_set         = 1'b0;
-    s_is_irq_start      = 1'b0;
+    s_is_pc_set          = 1'b0;
+    s_is_irq_start       = 1'b0;
 
-    s_is_pc_set         = 1'b0;
-    s_is_irq_start      = 1'b0;
-    s_skip_wb           = 1'b0;
+    s_is_pc_set          = 1'b0;
+    s_is_irq_start       = 1'b0;
+    s_skip_wb            = 1'b0;
 
-    s_core_is_decoding  = 1'b0;
+    s_core_is_decoding   = 1'b0;
+
+    s_ex_reg_we_adjusted = 1'b0;
+    s_rf_we_wb_adjusted  = 1'b0;
 
     forever begin
       wait(e_pipe_monitor_ok.triggered);  // event triggered
@@ -1387,7 +1430,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       s_new_valid_insn = r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.is_decoding;// && !r_pipe_freeze_trace.apu_rvalid;
 
-      s_wb_valid_adjusted = r_pipe_freeze_trace.wb_valid && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX));// && !r_pipe_freeze_trace.apu_rvalid;;
+      s_wb_valid_adjusted = r_pipe_freeze_trace.wb_valid && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_WB) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF));// && !r_pipe_freeze_trace.apu_rvalid;;
+      s_ex_reg_we_adjusted = r_pipe_freeze_trace.ex_reg_we && r_pipe_freeze_trace.mult_ready && r_pipe_freeze_trace.alu_ready && r_pipe_freeze_trace.lsu_ready_ex && !s_apu_to_alu_port;
+      s_rf_we_wb_adjusted = r_pipe_freeze_trace.rf_we_wb && (~r_pipe_freeze_trace.data_misaligned_ex && r_pipe_freeze_trace.wb_ready) && (!s_apu_to_lsu_port || r_pipe_freeze_trace.wb_contention_lsu);
 
       s_fflags_we_non_apu = 1'b0;
       if (r_pipe_freeze_trace.csr.fflags_we) begin
@@ -1418,40 +1463,34 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           s_skip_wb = 1'b1;
         end
       end
-      if (trace_wb.m_valid && !s_skip_wb) begin
-        if (r_pipe_freeze_trace.rf_we_wb) begin
-          if((trace_wb.m_rd_addr[0] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[0]) && trace_wb.m_mem_req_id_valid[0]) begin
-            trace_wb.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_wb.m_mem_req_id_valid[0] = 1'b0;
-          end else if (trace_wb.m_2_rd_insn && (trace_wb.m_rd_addr[1] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[1]) && trace_wb.m_mem_req_id_valid[1]) begin
-            trace_wb.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_wb.m_mem_req_id_valid[1] = 1'b0;
-          end
-        end
 
-        if (!trace_wb.m_data_missaligned) begin
-          send_rvfi(trace_wb);
-          ->e_dev_send_wb_1; ->e_send_rvfi_trace_wb_2;
-          trace_wb.m_valid = 1'b0;
+      if (trace_wb.m_valid && !s_skip_wb && s_rf_we_wb_adjusted) begin
+        if (trace_wb.m_2_rd_insn) begin
+          trace_wb.m_rd_addr[1]  = r_pipe_freeze_trace.rf_addr_wb;
+          trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
+        end else if (trace_wb.m_ex_fw) begin
+          trace_wb.m_rd_addr[1]  = r_pipe_freeze_trace.rf_addr_wb;
+          trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
+          trace_wb.m_2_rd_insn   = 1'b1;
         end else begin
-          if (s_wb_valid_adjusted) begin
-            if (r_pipe_freeze_trace.rf_we_wb) begin
-              if (!trace_wb.m_ex_fw) begin
-                trace_wb.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
-                trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-              end
-              if (trace_wb.m_data_missaligned && !trace_wb.m_got_first_data) begin
-                trace_wb.m_got_first_data = 1'b1;
-              end else begin
-                send_rvfi(trace_wb);
-                ->e_dev_send_wb_2; ->e_send_rvfi_trace_wb_3;
-                trace_wb.m_valid = 1'b0;
-              end
-            end  // rf_we_wb
+          trace_wb.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
+          trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
+        end
+
+        if (r_pipe_freeze_trace.csr.fregs_we) begin
+          `CSR_FROM_PIPE(wb, mstatus_fs)
+          trace_wb.m_csr.mstatus_fs_we = 1'b1;
+          trace_wb.m_csr.mstatus_fs_wmask = '1;
+          if(r_pipe_freeze_trace.csr.we && r_pipe_freeze_trace.csr.mstatus_fs_we) begin //In this specific case, two writes to mstatus_fs happen at the same time. We need to recreate the writes caused by fregs_we
+            trace_wb.m_csr.mstatus_fs_wdata = FS_DIRTY;
           end
+          ->e_fregs_dirty_1;
         end
+
+        send_rvfi(trace_wb);
+        ->e_dev_send_wb_1; ->e_send_rvfi_trace_wb_2;
+        trace_wb.m_valid = 1'b0;
+
       end
 
       if (trace_ex.m_valid) begin
@@ -1464,14 +1503,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         `CSR_FROM_PIPE(ex, tdata2)
         tinfo_to_ex();
 
-        if (r_pipe_freeze_trace.regfile_we_lsu) begin
+        if (s_rf_we_wb_adjusted) begin
           ->e_dev_commit_rf_to_ex_4;
-          if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg) && trace_ex.m_mem_req_id_valid[0]) begin
+          if (!(trace_ex.m_got_ex_reg) && trace_ex.m_mem_req_id_valid[0]) begin
             trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
             trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
             trace_ex.m_got_first_data = 1'b1;
             trace_ex.m_mem_req_id_valid[0] = 1'b0;
-          end else if ((cnt_data_resp == trace_ex.m_mem_req_id[1])  && trace_ex.m_mem_req_id_valid[1]) begin
+          end else if (trace_ex.m_mem_req_id_valid[1]) begin
             trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
             trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
             trace_ex.m_got_first_data = 1'b1;
@@ -1485,7 +1524,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_ex.m_valid = 1'b0;
             ->e_send_rvfi_trace_ex_2;
           end else begin
-            if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port) begin
+            if (!s_ex_valid_adjusted & !trace_ex.m_csr.got_minstret) begin
+              minstret_to_ex();
+            end
+
+            if (s_rf_we_wb_adjusted) begin
               ->e_dev_commit_rf_to_ex_1;
               if (trace_ex.m_got_ex_reg) begin
                 trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
@@ -1497,24 +1540,35 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
                 trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
                 trace_ex.m_got_first_data = 1'b1;
               end
-            end
 
-            if (!s_ex_valid_adjusted & !trace_ex.m_csr.got_minstret) begin
-              minstret_to_ex();
-            end
-            if (trace_ex.m_is_load) begin  // only move relevant instr in wb stage
-              ->e_ex_to_wb_1;
-              trace_wb.move_down_pipe(trace_ex);
-            end else begin
-              if (!trace_ex.m_csr.got_minstret) begin
-                minstret_to_ex();
+              if (r_pipe_freeze_trace.csr.fregs_we) begin
+                `CSR_FROM_PIPE(ex, mstatus_fs)
+                trace_ex.m_csr.mstatus_fs_we = 1'b1;
+                trace_ex.m_csr.mstatus_fs_wmask = '1;
+                if(r_pipe_freeze_trace.csr.we && r_pipe_freeze_trace.csr.mstatus_fs_we) begin //In this specific case, two writes to mstatus_fs happen at the same time. We need to recreate the writes caused by fregs_we
+                  trace_ex.m_csr.mstatus_fs_wdata = FS_DIRTY;
+                end
+                ->e_fregs_dirty_3;
               end
+
               send_rvfi(trace_ex);
-              ->e_send_rvfi_trace_ex_6;
+              trace_ex.m_valid = 1'b0;
+
+            end else begin
+              if (trace_ex.m_is_load) begin  // only move relevant instr in wb stage
+                ->e_ex_to_wb_1;
+                trace_wb.move_down_pipe(trace_ex);
+              end else begin
+                if (!trace_ex.m_csr.got_minstret) begin
+                  minstret_to_ex();
+                end
+                send_rvfi(trace_ex);
+                ->e_send_rvfi_trace_ex_6;
+              end
+              trace_ex.m_valid = 1'b0;
             end
-            trace_ex.m_valid = 1'b0;
           end
-        end else if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port && !s_was_flush) begin
+        end else if (s_rf_we_wb_adjusted && !s_was_flush) begin
           ->e_dev_commit_rf_to_ex_2;
           if (trace_ex.m_got_ex_reg) begin
             trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
@@ -1529,22 +1583,29 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         end
       end
 
-      s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex);
+      // If mret, we need to keep the instruction in Id during flush_ex because mstatus update happens at that time
+      s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || ((r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) && !r_pipe_freeze_trace.mret_insn_dec)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex);
       //EX_STAGE
       if (trace_id.m_valid) begin
+
+        if(trace_id.m_sample_csr_write_in_ex && !csr_is_irq && !s_is_irq_start) begin //First cycle after id_ready, csr write is asserted in this cycle
+          `CSR_FROM_PIPE(id, mstatus)
+          `CSR_FROM_PIPE(id, mstatus_fs)
+          `CSR_FROM_PIPE(id, mepc)
+          `CSR_FROM_PIPE(id, mcause)
+          `CSR_FROM_PIPE(id, dscratch0)
+          `CSR_FROM_PIPE(id, dscratch1)
+          ->e_csr_in_ex;
+        end
+
+        if(r_pipe_freeze_trace.is_decoding) begin
+            trace_id.m_sample_csr_write_in_ex = 1'b0;
+        end
         mtvec_to_id();
 
         `CSR_FROM_PIPE(id, mip)
         `CSR_FROM_PIPE(id, misa)
 
-        if (!csr_is_irq && !s_is_irq_start) begin
-          mstatus_to_id();
-          `CSR_FROM_PIPE(id, mepc)
-          if (trace_id.m_csr.mcause_we == '0) begin  //for debug purpose
-            `CSR_FROM_PIPE(id, mcause)
-          end
-        end
-
         `CSR_FROM_PIPE(id, mcountinhibit)
         `CSR_FROM_PIPE(id, mscratch)
         `CSR_FROM_PIPE(id, mie)
@@ -1603,10 +1664,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_id.m_rd_addr[0]  = r_pipe_freeze_trace.ex_reg_addr;
             trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.ex_reg_wdata;
             trace_id.m_got_ex_reg = 1'b1;
-          end else if (!trace_ex.m_valid & r_pipe_freeze_trace.rf_we_wb & !trace_id.m_ex_fw) begin
+          end else if (!trace_ex.m_valid & s_rf_we_wb_adjusted & !trace_id.m_ex_fw) begin
             trace_id.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
             trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-          end else if (r_pipe_freeze_trace.rf_we_wb) begin
+          end else if (s_rf_we_wb_adjusted) begin
             trace_id.m_rd_addr[1]  = r_pipe_freeze_trace.rf_addr_wb;
             trace_id.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
             trace_id.m_2_rd_insn   = 1'b1;
@@ -1621,19 +1682,16 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp;
             if (r_pipe_freeze_trace.data_misaligned) begin
               cnt_data_req = cnt_data_req + 1;
+              trace_id.m_mem_req_id[0] = cnt_data_req;
             end
+
             if (!r_pipe_freeze_trace.data_we_ex) begin
               trace_id.m_is_load   = 1'b1;
               trace_id.m_mem.wmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be);  //'1;
-              if (r_pipe_freeze_trace.data_misaligned) begin
-                trace_id.m_data_missaligned = 1'b1;
-                trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
-                trace_id.m_mem_req_id[0] = cnt_data_req;
-                trace_id.m_mem_req_id_valid[1] = 1'b1;
-              end
             end else begin
               trace_id.m_mem.rmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be);  //'1;
             end
+
             if (trace_id.m_got_ex_reg) begin  // Shift index 0 to 1
               trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
               trace_id.m_mem_req_id[0] = 0;
@@ -1692,15 +1750,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp;
             if (r_pipe_freeze_trace.data_misaligned) begin
               cnt_data_req = cnt_data_req + 1;
+              trace_id.m_mem_req_id[0] = cnt_data_req;
             end
             if (!r_pipe_freeze_trace.data_we_ex) begin
               trace_id.m_is_load = 1'b1;
-              if (r_pipe_freeze_trace.data_misaligned) begin
-                trace_id.m_data_missaligned = 1'b1;
-                trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
-                trace_id.m_mem_req_id[0] = cnt_data_req;
-                trace_id.m_mem_req_id_valid[1] = 1'b1;
-              end
             end
             if (trace_id.m_got_ex_reg) begin  // Shift index 0 to 1
               trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
@@ -1708,7 +1761,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
               trace_id.m_mem_req_id_valid[0] = 1'b0;
               trace_id.m_mem_req_id_valid[1] = 1'b1;
             end
-          end else if (r_pipe_freeze_trace.rf_we_wb && !r_pipe_freeze_trace.ex_reg_we) begin
+          end else if (s_rf_we_wb_adjusted && !r_pipe_freeze_trace.ex_reg_we) begin
             trace_id.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
             trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
           end
@@ -1734,12 +1787,21 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       //IF_STAGE
       if (r_pipe_freeze_trace.if_valid && r_pipe_freeze_trace.if_ready) begin
-        if(trace_if.m_valid && r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.id_ready && !trace_id.m_valid && r_pipe_freeze_trace.ebrk_insn_dec) begin
-          if_to_id();
-          trace_id.m_is_ebreak = '1;  //trace_if.m_is_ebreak;
-          ->e_if_2_id_2;
+        if (trace_if.m_valid) begin
+          if (r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.id_ready && !trace_id.m_valid && r_pipe_freeze_trace.ebrk_insn_dec) begin
+            if_to_id();
+            trace_id.m_is_ebreak = '1;  //trace_if.m_is_ebreak;
+            ->e_if_2_id_2;
+          end else if (r_pipe_freeze_trace.is_illegal) begin
+            if_to_id();
+            trace_id.m_is_illegal = 1'b1;
+            ->e_if_2_id_3;
+          end else if (r_pipe_freeze_trace.ecall_insn_dec) begin
+            if_to_id();
+          end
         end
 
+
         trace_if.m_insn = r_pipe_freeze_trace.instr_if;  //Instr comes from if, buffer for one cycle
         trace_if.m_pc_rdata = r_pipe_freeze_trace.pc_if;
         trace_if.m_dbg_taken = is_dbg_taken;
@@ -1754,6 +1816,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         mstatus_to_id();
         `CSR_FROM_PIPE(id, mepc)
         `CSR_FROM_PIPE(id, mcause)
+        ->e_csr_irq;
       end
 
       if (!s_id_done && r_pipe_freeze_trace.is_decoding) begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv
index 1b40b80e..d4aa94dc 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv
@@ -272,13 +272,19 @@ module cv32e40px_tb_wrapper
 
       .rs1_addr_id_i     (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_ra_id),
       .rs2_addr_id_i     (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_rb_id),
+      .rs3_addr_id_i     (cv32e40px_top_i.core_i.id_stage_i.regfile_addr_rc_id),
       .operand_a_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_a_fw_id),
       .operand_b_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_b_fw_id),
+      .operand_c_fw_id_i (cv32e40px_top_i.core_i.id_stage_i.operand_c_fw_id),
       // .instr         (cv32e40px_top_i.core_i.id_stage_i.instr     ),
       .is_compressed_id_i(cv32e40px_top_i.core_i.id_stage_i.is_compressed_i),
       .ebrk_insn_dec_i   (cv32e40px_top_i.core_i.id_stage_i.ebrk_insn_dec),
-      .csr_cause_i       (cv32e40px_top_i.core_i.csr_cause),
-      .debug_csr_save_i  (cv32e40px_top_i.core_i.debug_csr_save),
+      .ecall_insn_dec_i  (cv32e40px_top_i.core_i.id_stage_i.ecall_insn_dec),
+      .mret_insn_dec_i   (cv32e40px_top_i.core_i.id_stage_i.mret_insn_dec),
+      .mret_dec_i        (cv32e40px_top_i.core_i.id_stage_i.mret_dec),
+
+      .csr_cause_i     (cv32e40px_top_i.core_i.csr_cause),
+      .debug_csr_save_i(cv32e40px_top_i.core_i.debug_csr_save),
 
       // HWLOOP regs
       .hwlp_start_q_i  (hwlp_start_q),
@@ -298,14 +304,16 @@ module cv32e40px_tb_wrapper
       .apu_multicycle_i   (cv32e40px_top_i.core_i.ex_stage_i.apu_multicycle),
       .wb_contention_lsu_i(cv32e40px_top_i.core_i.ex_stage_i.wb_contention_lsu),
       .wb_contention_i    (cv32e40px_top_i.core_i.ex_stage_i.wb_contention),
-
+      .regfile_we_lsu_i   (cv32e40px_top_i.core_i.ex_stage_i.regfile_we_lsu),
       // .rf_we_alu_i    (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_we_fw_i),
       // .rf_addr_alu_i  (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i),
       // .rf_wdata_alu_i (cv32e40px_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i),
 
+      .mult_ready_i        (cv32e40px_top_i.core_i.ex_stage_i.mult_ready),
+      .alu_ready_i         (cv32e40px_top_i.core_i.ex_stage_i.alu_ready),
       //// WB probes ////
-      .wb_valid_i(cv32e40px_top_i.core_i.wb_valid),
-
+      .wb_valid_i          (cv32e40px_top_i.core_i.wb_valid),
+      .wb_ready_i          (cv32e40px_top_i.core_i.lsu_ready_wb),
       //// LSU probes ////
       .data_we_ex_i        (cv32e40px_top_i.core_i.data_we_ex),
       .data_atop_ex_i      (cv32e40px_top_i.core_i.data_atop_ex),
@@ -325,6 +333,8 @@ module cv32e40px_tb_wrapper
       .lsu_ready_ex_i      (cv32e40px_top_i.core_i.lsu_ready_ex),
       .lsu_ready_wb_i      (cv32e40px_top_i.core_i.lsu_ready_wb),
 
+      .lsu_data_be_i(cv32e40px_top_i.core_i.load_store_unit_i.data_be),
+
       .data_req_pmp_i(cv32e40px_top_i.core_i.data_req_pmp),
       .data_gnt_pmp_i(cv32e40px_top_i.core_i.data_gnt_pmp),
       .data_rvalid_i(cv32e40px_top_i.core_i.data_rvalid_i),
@@ -339,11 +349,12 @@ module cv32e40px_tb_wrapper
       .rf_we_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_we_wb_i),
       .rf_addr_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_waddr_wb_i),
       .rf_wdata_wb_i(cv32e40px_top_i.core_i.id_stage_i.regfile_wdata_wb_i),
+      .regfile_alu_we_ex_i(cv32e40px_top_i.core_i.id_stage_i.regfile_alu_we_ex_o),
 
       // APU
       .apu_req_i   (cv32e40px_top_i.core_i.apu_req_o),
       .apu_gnt_i   (cv32e40px_top_i.core_i.apu_gnt_i),
-      .apu_rvalid_i(cv32e40px_top_i.core_i.apu_rvalid_i),
+      .apu_rvalid_i(cv32e40px_top_i.core_i.ex_stage_i.apu_valid),
 
       // Controller FSM probes
       .ctrl_fsm_cs_i(cv32e40px_top_i.core_i.id_stage_i.controller_i.ctrl_fsm_cs),
@@ -355,6 +366,8 @@ module cv32e40px_tb_wrapper
       .csr_we_i       (cv32e40px_top_i.core_i.cs_registers_i.csr_we_int),
       .csr_wdata_int_i(cv32e40px_top_i.core_i.cs_registers_i.csr_wdata_int),
 
+      .csr_fregs_we_i(cv32e40px_top_i.core_i.cs_registers_i.fregs_we_i),
+
       .csr_mstatus_n_i   (cv32e40px_top_i.core_i.cs_registers_i.mstatus_n),
       .csr_mstatus_q_i   (cv32e40px_top_i.core_i.cs_registers_i.mstatus_q),
       .csr_mstatus_fs_n_i(cv32e40px_top_i.core_i.cs_registers_i.mstatus_fs_n),
@@ -367,6 +380,10 @@ module cv32e40px_tb_wrapper
       .csr_tdata1_q_i           (cv32e40px_top_i.core_i.cs_registers_i.tmatch_control_rdata),//gen_trigger_regs.tmatch_control_exec_q          ),
       .csr_tdata1_we_i(cv32e40px_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_control_we),
 
+      .csr_tdata2_n_i           (cv32e40px_top_i.core_i.cs_registers_i.tmatch_value_rdata),//csr_wdata_int                                   ),
+      .csr_tdata2_q_i           (cv32e40px_top_i.core_i.cs_registers_i.tmatch_value_rdata),//gen_trigger_regs.tmatch_control_exec_q          ),
+      .csr_tdata2_we_i(cv32e40px_top_i.core_i.cs_registers_i.gen_trigger_regs.tmatch_value_we),
+
       .csr_tinfo_n_i({16'h0, cv32e40px_top_i.core_i.cs_registers_i.tinfo_types}),
       .csr_tinfo_q_i({16'h0, cv32e40px_top_i.core_i.cs_registers_i.tinfo_types}),
 
@@ -424,6 +441,7 @@ module cv32e40px_tb_wrapper
   );
 `endif
 
+
 `ifdef CV32E40P_RVFI_TRACE_EXECUTION
   bind cv32e40px_rvfi: rvfi_i cv32e40px_rvfi_trace #(
       .FPU  (FPU),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv
index 40edce03..90ee5be9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv
@@ -196,8 +196,8 @@ package cv32e40px_tracer_pkg;
   parameter INSTR_CVEND0 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNTI0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNT0 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUPI0 = {12'b?, 5'b00000, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUP0 = {12'b?, 5'b00000, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUPI0 = {17'b?, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUP0 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1};
 
   parameter INSTR_CVSTARTI1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1};
   parameter INSTR_CVSTART1 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1};
@@ -205,8 +205,8 @@ package cv32e40px_tracer_pkg;
   parameter INSTR_CVEND1 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNTI1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNT1 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUPI1 = {12'b?, 5'b00000, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUP1 = {12'b?, 5'b00000, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUPI1 = {17'b?, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUP1 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1};
 
 
   parameter INSTR_FF1 = {7'b0100001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1};
@@ -449,8 +449,8 @@ package cv32e40px_tracer_pkg;
   parameter INSTR_CVSHUFFLE2H = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
   parameter INSTR_CVSHUFFLE2B = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
 
-  parameter INSTR_CVPACK = {5'b11101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
-  parameter INSTR_CVPACKH = {5'b11101, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
+  parameter INSTR_CVPACK = {5'b11110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
+  parameter INSTR_CVPACKH = {5'b11110, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
 
   parameter INSTR_CVPACKHIB = {5'b11111, 1'b0, 1'b1, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
   parameter INSTR_CVPACKLOB = {5'b11111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv
index 3db2a7ee..3fe7c184 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv
@@ -66,6 +66,8 @@
 
     int m_instret_cnt;
 
+    bit m_sample_csr_write_in_ex;
+
     struct {
       logic [31:0] addr ;
       logic [ 3:0] rmask;
@@ -145,32 +147,33 @@
 
 
     function new();
-      this.m_order             = 0;
-      this.m_skip_order        = 1'b0;
-      this.m_valid             = 1'b0;
-      this.m_move_down_pipe    = 1'b0;
-      this.m_data_missaligned  = 1'b0;
-      this.m_got_first_data    = 1'b0;
-      this.m_got_ex_reg        = 1'b0;
-      this.m_intr              = '0;
-      this.m_dbg_taken         = 1'b0;
-      this.m_dbg_cause         = '0;
-      this.m_is_ebreak         = '0;
-      this.m_is_illegal        = '0;
-      this.m_is_irq            = '0;
-      this.m_is_memory         = 1'b0;
-      this.m_is_load           = 1'b0;
-      this.m_is_apu            = 1'b0;
-      this.m_is_apu_ok         = 1'b0;
-      this.m_apu_req_id        = 0;
-      this.m_mem_req_id[0]     = 0;
-      this.m_mem_req_id[1]     = 0;
-      this.m_mem_req_id_valid  = '0;
-      this.m_trap              = 1'b0;
-      this.m_fflags_we_non_apu = 1'b0;
-      this.m_frm_we_non_apu    = 1'b0;
-      this.m_fcsr_we_non_apu   = 1'b0;
-      this.m_instret_cnt       = 0;
+      this.m_order                  = 0;
+      this.m_skip_order             = 1'b0;
+      this.m_valid                  = 1'b0;
+      this.m_move_down_pipe         = 1'b0;
+      this.m_data_missaligned       = 1'b0;
+      this.m_got_first_data         = 1'b0;
+      this.m_got_ex_reg             = 1'b0;
+      this.m_intr                   = '0;
+      this.m_dbg_taken              = 1'b0;
+      this.m_dbg_cause              = '0;
+      this.m_is_ebreak              = '0;
+      this.m_is_illegal             = '0;
+      this.m_is_irq                 = '0;
+      this.m_is_memory              = 1'b0;
+      this.m_is_load                = 1'b0;
+      this.m_is_apu                 = 1'b0;
+      this.m_is_apu_ok              = 1'b0;
+      this.m_apu_req_id             = 0;
+      this.m_mem_req_id[0]          = 0;
+      this.m_mem_req_id[1]          = 0;
+      this.m_mem_req_id_valid       = '0;
+      this.m_trap                   = 1'b0;
+      this.m_fflags_we_non_apu      = 1'b0;
+      this.m_frm_we_non_apu         = 1'b0;
+      this.m_fcsr_we_non_apu        = 1'b0;
+      this.m_instret_cnt            = 0;
+      this.m_sample_csr_write_in_ex = 1'b1;
     endfunction
 
     function void get_mnemonic();
@@ -875,37 +878,38 @@
       if(this.m_skip_order) begin
         this.m_order            = this.m_order + 64'h1;
       end
-      this.m_skip_order        = 1'b0;
-      this.m_pc_rdata          = r_pipe_freeze_trace.pc_id;
-      this.m_is_illegal        = 1'b0;
-      this.m_is_irq            = 1'b0;
-      this.m_is_memory         = 1'b0;
-      this.m_is_load           = 1'b0;
-      this.m_is_apu            = 1'b0;
-      this.m_is_apu_ok         = 1'b0;
-      this.m_apu_req_id        = 0;
-      this.m_mem_req_id[0]     = 0;
-      this.m_mem_req_id[1]     = 0;
-      this.m_mem_req_id_valid  = '0;
-      this.m_data_missaligned  = 1'b0;
-      this.m_got_first_data    = 1'b0;
-      this.m_got_ex_reg        = 1'b0;
-      this.m_got_regs_write    = 1'b0;
-      this.m_move_down_pipe    = 1'b0;
-      this.m_instret_cnt       = 0;
-      this.m_rd_addr[0]        = '0;
-      this.m_rd_addr[1]        = '0;
-      this.m_2_rd_insn         = 1'b0;
-      this.m_rs1_addr          = '0;
-      this.m_rs2_addr          = '0;
-      this.m_rs3_addr          = '0;
-      this.m_ex_fw             = '0;
-      this.m_csr.got_minstret  = '0;
-      this.m_dbg_taken         = '0;
-      this.m_trap              = 1'b0;
-      this.m_fflags_we_non_apu = 1'b0;
-      this.m_frm_we_non_apu    = 1'b0;
-      this.m_fcsr_we_non_apu   = 1'b0;
+      this.m_skip_order             = 1'b0;
+      this.m_pc_rdata               = r_pipe_freeze_trace.pc_id;
+      this.m_is_illegal             = 1'b0;
+      this.m_is_irq                 = 1'b0;
+      this.m_is_memory              = 1'b0;
+      this.m_is_load                = 1'b0;
+      this.m_is_apu                 = 1'b0;
+      this.m_is_apu_ok              = 1'b0;
+      this.m_apu_req_id             = 0;
+      this.m_mem_req_id[0]          = 0;
+      this.m_mem_req_id[1]          = 0;
+      this.m_mem_req_id_valid       = '0;
+      this.m_data_missaligned       = 1'b0;
+      this.m_got_first_data         = 1'b0;
+      this.m_got_ex_reg             = 1'b0;
+      this.m_got_regs_write         = 1'b0;
+      this.m_move_down_pipe         = 1'b0;
+      this.m_instret_cnt            = 0;
+      this.m_sample_csr_write_in_ex = 1'b1;
+      this.m_rd_addr[0]             = '0;
+      this.m_rd_addr[1]             = '0;
+      this.m_2_rd_insn              = 1'b0;
+      this.m_rs1_addr               = '0;
+      this.m_rs2_addr               = '0;
+      this.m_rs3_addr               = '0;
+      this.m_ex_fw                  = '0;
+      this.m_csr.got_minstret       = '0;
+      this.m_dbg_taken              = '0;
+      this.m_trap                   = 1'b0;
+      this.m_fflags_we_non_apu      = 1'b0;
+      this.m_frm_we_non_apu         = 1'b0;
+      this.m_fcsr_we_non_apu        = 1'b0;
       this.m_csr.mcause_we = '0;
       if (is_compressed_id_i) begin
         this.m_insn[31:16] = '0;
@@ -944,47 +948,48 @@
     endfunction
 
     function void copy_full(insn_trace_t m_source);
-      this.m_valid              = m_source.m_valid;
-      this.m_stage              = m_source.m_stage;
-      this.m_order              = m_source.m_order;
-      this.m_pc_rdata           = m_source.m_pc_rdata;
-      this.m_insn               = m_source.m_insn;
-      this.m_mnemonic           = m_source.m_mnemonic;
-      this.m_is_memory          = m_source.m_is_memory;
-      this.m_is_load            = m_source.m_is_load;
-      this.m_is_apu             = m_source.m_is_apu;
-      this.m_is_apu_ok          = m_source.m_is_apu_ok;
-      this.m_apu_req_id         = m_source.m_apu_req_id;
-      this.m_mem_req_id         = m_source.m_mem_req_id;
-      this.m_mem_req_id_valid   = m_source.m_mem_req_id_valid;
-      this.m_data_missaligned   = m_source.m_data_missaligned;
-      this.m_got_first_data     = m_source.m_got_first_data;
-      this.m_got_ex_reg         = m_source.m_got_ex_reg;
-      this.m_dbg_taken          = m_source.m_dbg_taken;
-      this.m_dbg_cause          = m_source.m_dbg_cause;
-      this.m_is_ebreak          = m_source.m_is_ebreak;
-      this.m_is_illegal         = m_source.m_is_illegal;
-      this.m_is_irq             = m_source.m_is_irq;
-      this.m_instret_cnt        = m_source.m_instret_cnt;
-      this.m_rs1_addr           = m_source.m_rs1_addr;
-      this.m_rs2_addr           = m_source.m_rs2_addr;
-      this.m_rs3_addr           = m_source.m_rs3_addr;
-      this.m_rs1_rdata          = m_source.m_rs1_rdata;
-      this.m_rs2_rdata          = m_source.m_rs2_rdata;
-      this.m_rs3_rdata          = m_source.m_rs3_rdata;
-
-      this.m_ex_fw              = m_source.m_ex_fw;
-      this.m_rd_addr            = m_source.m_rd_addr;
-      this.m_2_rd_insn          = m_source.m_2_rd_insn;
-      this.m_rd_wdata           = m_source.m_rd_wdata;
-
-      this.m_intr               = m_source.m_intr;
-      this.m_trap               = m_source.m_trap;
-      this.m_fflags_we_non_apu  = m_source.m_fflags_we_non_apu;
-      this.m_frm_we_non_apu     = m_source.m_frm_we_non_apu   ;
-      this.m_fcsr_we_non_apu    = m_source.m_fcsr_we_non_apu;
-
-      this.m_mem                = m_source.m_mem;
+      this.m_valid                  = m_source.m_valid;
+      this.m_stage                  = m_source.m_stage;
+      this.m_order                  = m_source.m_order;
+      this.m_pc_rdata               = m_source.m_pc_rdata;
+      this.m_insn                   = m_source.m_insn;
+      this.m_mnemonic               = m_source.m_mnemonic;
+      this.m_is_memory              = m_source.m_is_memory;
+      this.m_is_load                = m_source.m_is_load;
+      this.m_is_apu                 = m_source.m_is_apu;
+      this.m_is_apu_ok              = m_source.m_is_apu_ok;
+      this.m_apu_req_id             = m_source.m_apu_req_id;
+      this.m_mem_req_id             = m_source.m_mem_req_id;
+      this.m_mem_req_id_valid       = m_source.m_mem_req_id_valid;
+      this.m_data_missaligned       = m_source.m_data_missaligned;
+      this.m_got_first_data         = m_source.m_got_first_data;
+      this.m_got_ex_reg             = m_source.m_got_ex_reg;
+      this.m_dbg_taken              = m_source.m_dbg_taken;
+      this.m_dbg_cause              = m_source.m_dbg_cause;
+      this.m_is_ebreak              = m_source.m_is_ebreak;
+      this.m_is_illegal             = m_source.m_is_illegal;
+      this.m_is_irq                 = m_source.m_is_irq;
+      this.m_instret_cnt            = m_source.m_instret_cnt;
+      this.m_sample_csr_write_in_ex = m_source.m_sample_csr_write_in_ex;
+      this.m_rs1_addr               = m_source.m_rs1_addr;
+      this.m_rs2_addr               = m_source.m_rs2_addr;
+      this.m_rs3_addr               = m_source.m_rs3_addr;
+      this.m_rs1_rdata              = m_source.m_rs1_rdata;
+      this.m_rs2_rdata              = m_source.m_rs2_rdata;
+      this.m_rs3_rdata              = m_source.m_rs3_rdata;
+
+      this.m_ex_fw                  = m_source.m_ex_fw;
+      this.m_rd_addr                = m_source.m_rd_addr;
+      this.m_2_rd_insn              = m_source.m_2_rd_insn;
+      this.m_rd_wdata               = m_source.m_rd_wdata;
+
+      this.m_intr                   = m_source.m_intr;
+      this.m_trap                   = m_source.m_trap;
+      this.m_fflags_we_non_apu      = m_source.m_fflags_we_non_apu;
+      this.m_frm_we_non_apu         = m_source.m_frm_we_non_apu   ;
+      this.m_fcsr_we_non_apu        = m_source.m_fcsr_we_non_apu;
+
+      this.m_mem                    = m_source.m_mem;
       //CRS
       `ASSIGN_CSR(mstatus)
       `ASSIGN_CSR(mstatus_fs)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv
index 58051ab8..88d65d0b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv
@@ -64,6 +64,9 @@ typedef struct {
   logic is_compressed_id;
 
   logic ebrk_insn_dec;
+  logic ecall_insn_dec;
+  logic mret_insn_dec;
+  logic mret_dec;
 
   logic [5:0] csr_cause;
 
@@ -112,6 +115,9 @@ typedef struct {
   logic [31:0] data_wdata_ex;
   logic lsu_split_q_ex;
 
+  logic mult_ready;
+  logic alu_ready;
+
   //// WB probes ////
   logic [31:0] pc_wb;
   logic wb_ready;
@@ -198,6 +204,8 @@ typedef struct {
     logic mcause_we;
     logic dcsr_we;
 
+    logic fregs_we;
+
     logic jvt_we;
     Status_t mstatus_n;
     Status_t mstatus_q;
@@ -348,16 +356,24 @@ function compute_csr_we();
         r_pipe_freeze_trace.csr.mstatus_we    = 1'b1;
         r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
       end
-      CSR_MISA:     r_pipe_freeze_trace.csr.misa_we = 1'b1;
-      CSR_MTVEC:    r_pipe_freeze_trace.csr.mtvec_we = 1'b1;
-      CSR_MSCRATCH: r_pipe_freeze_trace.csr.mscratch_we = 1'b1;
-      CSR_MEPC:     r_pipe_freeze_trace.csr.mepc_we = 1'b1;
-      CSR_MCAUSE:   r_pipe_freeze_trace.csr.mcause_we = 1'b1;
-      CSR_DCSR:     r_pipe_freeze_trace.csr.dcsr_we = 1'b1;
-      CSR_FFLAGS:   r_pipe_freeze_trace.csr.fflags_we = 1'b1;
-      CSR_FRM:      r_pipe_freeze_trace.csr.frm_we = 1'b1;
-      CSR_FCSR:     r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
-      CSR_DPC:      r_pipe_freeze_trace.csr.dpc_we = 1'b1;
+      CSR_MISA:      r_pipe_freeze_trace.csr.misa_we = 1'b1;
+      CSR_MTVEC:     r_pipe_freeze_trace.csr.mtvec_we = 1'b1;
+      CSR_MSCRATCH:  r_pipe_freeze_trace.csr.mscratch_we = 1'b1;
+      CSR_MEPC:      r_pipe_freeze_trace.csr.mepc_we = 1'b1;
+      CSR_MCAUSE:    r_pipe_freeze_trace.csr.mcause_we = 1'b1;
+      CSR_DCSR:      r_pipe_freeze_trace.csr.dcsr_we = 1'b1;
+      CSR_FFLAGS: begin
+        r_pipe_freeze_trace.csr.fflags_we = 1'b1;
+        r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
+      end
+      CSR_FRM:       r_pipe_freeze_trace.csr.frm_we = 1'b1;
+      CSR_FCSR: begin
+        r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
+        r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
+      end
+      CSR_DPC:       r_pipe_freeze_trace.csr.dpc_we = 1'b1;
+      CSR_DSCRATCH0: r_pipe_freeze_trace.csr.dscratch0_we = 1'b1;
+      CSR_DSCRATCH1: r_pipe_freeze_trace.csr.dscratch1_we = 1'b1;
     endcase
   end
   // CSR_MCAUSE:   r_pipe_freeze_trace.csr.mcause_we = r_pipe_freeze_trace.csr.mcause_n != r_pipe_freeze_trace.csr.mcause_q; //for debug purpose
@@ -416,6 +432,9 @@ task monitor_pipeline();
     r_pipe_freeze_trace.jump_target_id = jump_target_id_i;
     r_pipe_freeze_trace.is_compressed_id = is_compressed_id_i;
     r_pipe_freeze_trace.ebrk_insn_dec = ebrk_insn_dec_i;
+    r_pipe_freeze_trace.ecall_insn_dec = ecall_insn_dec_i;
+    r_pipe_freeze_trace.mret_insn_dec = mret_insn_dec_i;
+    r_pipe_freeze_trace.mret_dec = mret_dec_i;
     r_pipe_freeze_trace.csr_cause = csr_cause_i;
     r_pipe_freeze_trace.debug_csr_save = debug_csr_save_i;
     r_pipe_freeze_trace.minstret = minstret_i;
@@ -462,6 +481,8 @@ task monitor_pipeline();
     r_pipe_freeze_trace.data_wdata_ex = data_wdata_ex_i;
     r_pipe_freeze_trace.lsu_split_q_ex = lsu_split_q_ex_i;
 
+    r_pipe_freeze_trace.mult_ready = mult_ready_i;
+    r_pipe_freeze_trace.alu_ready = alu_ready_i;
     //// WB probes ////
     r_pipe_freeze_trace.pc_wb = pc_wb_i;
     r_pipe_freeze_trace.wb_ready = wb_ready_i;
@@ -526,6 +547,8 @@ task monitor_pipeline();
     r_pipe_freeze_trace.csr.we = csr_we_i;
     r_pipe_freeze_trace.csr.wdata_int = csr_wdata_int_i;
 
+    r_pipe_freeze_trace.csr.fregs_we = csr_fregs_we_i;
+
     r_pipe_freeze_trace.csr.jvt_we = csr_jvt_we_i;
     r_pipe_freeze_trace.csr.mstatus_n = csr_mstatus_n_i;
     r_pipe_freeze_trace.csr.mstatus_q = csr_mstatus_q_i;
@@ -650,10 +673,6 @@ task monitor_pipeline();
     if (r_pipe_freeze_trace.csr.fcsr_we) begin
       r_pipe_freeze_trace.csr.fflags_we = 1'b1;
       r_pipe_freeze_trace.csr.frm_we    = 1'b1;
-    end else begin
-      if (r_pipe_freeze_trace.csr.fflags_we || r_pipe_freeze_trace.csr.frm_we) begin
-        r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
-      end
     end
 
     if (csr_fcsr_fflags_we_i) begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
index 6516f932..a3e3bac9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
@@ -491,6 +491,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
             if ( (debug_req_pending || trigger_match_i) & ~debug_mode_q )
               begin
                 //Serving the debug
+                is_decoding_o     = COREV_PULP ? 1'b0 : 1'b1;
                 halt_if_o         = 1'b1;
                 halt_id_o         = 1'b1;
                 ctrl_fsm_ns       = DBG_FLUSH;
@@ -712,6 +713,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
             if ( (debug_req_pending || trigger_match_i) & ~debug_mode_q )
               begin
                 //Serving the debug
+                is_decoding_o     = COREV_PULP ? 1'b0 : 1'b1;
                 halt_if_o         = 1'b1;
                 halt_id_o         = 1'b1;
                 ctrl_fsm_ns       = DBG_FLUSH;
@@ -764,7 +766,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
 
                     ebrk_insn_i: begin
                       halt_if_o     = 1'b1;
-                      halt_id_o     = 1'b1;
+                      halt_id_o     = 1'b0;
 
                       if (debug_mode_q)
                         // we got back to the park loop in the debug rom
@@ -776,15 +778,15 @@ module cv32e40px_controller import cv32e40px_pkg::*;
 
                       else begin
                         // otherwise just a normal ebreak exception
-                        ctrl_fsm_ns = FLUSH_EX;
+                        ctrl_fsm_ns = id_ready_i ? FLUSH_EX : DECODE_HWLOOP;
                       end
 
                     end
 
                     ecall_insn_i: begin
                       halt_if_o     = 1'b1;
-                      halt_id_o     = 1'b1;
-                      ctrl_fsm_ns   = FLUSH_EX;
+                      halt_id_o     = 1'b0;
+                      ctrl_fsm_ns   = id_ready_i ? FLUSH_EX : DECODE_HWLOOP;
                     end
 
                     csr_status_i: begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
index fc301b91..25aa6cc9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
@@ -194,6 +194,7 @@ module cv32e40px_core
   logic [31:0] jump_target_id, jump_target_ex;
   logic               branch_in_ex;
   logic               branch_decision;
+  logic        [ 1:0] ctrl_transfer_insn_in_dec;
 
   logic               ctrl_busy;
   logic               if_busy;
@@ -237,6 +238,7 @@ module cv32e40px_core
   logic        [            C_RM-1:0]       frm_csr;
   logic        [         C_FFLAG-1:0]       fflags_csr;
   logic                                     fflags_we;
+  logic                                     fregs_we;
 
   // APU
   logic                                     apu_en_ex;
@@ -272,6 +274,7 @@ module cv32e40px_core
   logic                                     regfile_we_ex;
   logic        [                 5:0]       regfile_waddr_fw_wb_o;  // From WB to ID
   logic                                     regfile_we_wb;
+  logic                                     regfile_we_wb_power;
   logic        [                31:0]       regfile_wdata;
 
   logic        [                 5:0]       regfile_alu_waddr_ex;
@@ -279,6 +282,7 @@ module cv32e40px_core
 
   logic        [                 5:0]       regfile_alu_waddr_fw;
   logic                                     regfile_alu_we_fw;
+  logic                                     regfile_alu_we_fw_power;
   logic        [                31:0]       regfile_alu_wdata_fw;
 
   // CSR control
@@ -596,9 +600,10 @@ module cv32e40px_core
       .instr_req_o  (instr_req_int),
 
       // Jumps and branches
-      .branch_in_ex_o   (branch_in_ex),
-      .branch_decision_i(branch_decision),
-      .jump_target_o    (jump_target_id),
+      .branch_in_ex_o             (branch_in_ex),
+      .branch_decision_i          (branch_decision),
+      .jump_target_o              (jump_target_id),
+      .ctrl_transfer_insn_in_dec_o(ctrl_transfer_insn_in_dec),
 
       // IF and ID control signals
       .clear_instr_valid_o(clear_instr_valid),
@@ -790,13 +795,15 @@ module cv32e40px_core
       .wake_from_sleep_o(wake_from_sleep),
 
       // Forward Signals
-      .regfile_waddr_wb_i(regfile_waddr_fw_wb_o),  // Write address ex-wb pipeline
-      .regfile_we_wb_i   (regfile_we_wb),  // write enable for the register file
-      .regfile_wdata_wb_i(regfile_wdata),  // write data to commit in the register file
+      .regfile_waddr_wb_i   (regfile_waddr_fw_wb_o),  // Write address ex-wb pipeline
+      .regfile_we_wb_i      (regfile_we_wb),  // write enable for the register file
+      .regfile_we_wb_power_i(regfile_we_wb_power),
+      .regfile_wdata_wb_i   (regfile_wdata),  // write data to commit in the register file
 
-      .regfile_alu_waddr_fw_i(regfile_alu_waddr_fw),
-      .regfile_alu_we_fw_i   (regfile_alu_we_fw),
-      .regfile_alu_wdata_fw_i(regfile_alu_wdata_fw),
+      .regfile_alu_waddr_fw_i   (regfile_alu_waddr_fw),
+      .regfile_alu_we_fw_i      (regfile_alu_we_fw),
+      .regfile_alu_we_fw_power_i(regfile_alu_we_fw_power),
+      .regfile_alu_wdata_fw_i   (regfile_alu_wdata_fw),
 
       // from ALU
       .mult_multicycle_i(mult_multicycle),
@@ -828,6 +835,7 @@ module cv32e40px_core
   //                                                 //
   /////////////////////////////////////////////////////
   cv32e40px_ex_stage #(
+      .COREV_PULP      (COREV_PULP),
       .FPU             (FPU),
       .APU_NARGS_CPU   (APU_NARGS_CPU),
       .APU_WOP_CPU     (APU_WOP_CPU),
@@ -876,6 +884,8 @@ module cv32e40px_core
       .data_misaligned_ex_i(data_misaligned_ex),  // from ID/EX pipeline
       .data_misaligned_i   (data_misaligned),
 
+      .ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec),
+
       // FPU
       .fpu_fflags_we_o(fflags_we),
       .fpu_fflags_o   (fflags_csr),
@@ -941,18 +951,20 @@ module cv32e40px_core
       .regfile_we_i   (regfile_we_ex),
 
       // Output of ex stage pipeline
-      .regfile_waddr_wb_o(regfile_waddr_fw_wb_o),
-      .regfile_we_wb_o   (regfile_we_wb),
-      .regfile_wdata_wb_o(regfile_wdata),
+      .regfile_waddr_wb_o   (regfile_waddr_fw_wb_o),
+      .regfile_we_wb_o      (regfile_we_wb),
+      .regfile_we_wb_power_o(regfile_we_wb_power),
+      .regfile_wdata_wb_o   (regfile_wdata),
 
       // To IF: Jump and branch target and decision
       .jump_target_o    (jump_target_ex),
       .branch_decision_o(branch_decision),
 
       // To ID stage: Forwarding signals
-      .regfile_alu_waddr_fw_o(regfile_alu_waddr_fw),
-      .regfile_alu_we_fw_o   (regfile_alu_we_fw),
-      .regfile_alu_wdata_fw_o(regfile_alu_wdata_fw),
+      .regfile_alu_waddr_fw_o   (regfile_alu_waddr_fw),
+      .regfile_alu_we_fw_o      (regfile_alu_we_fw),
+      .regfile_alu_we_fw_power_o(regfile_alu_we_fw_power),
+      .regfile_alu_wdata_fw_o   (regfile_alu_wdata_fw),
 
       // stall control
       .is_decoding_i (is_decoding),
@@ -1072,6 +1084,7 @@ module cv32e40px_core
       .frm_o      (frm_csr),
       .fflags_i   (fflags_csr),
       .fflags_we_i(fflags_we),
+      .fregs_we_i (fregs_we),
 
       // Interrupt related control signals
       .mie_bypass_o  (mie_bypass),
@@ -1140,13 +1153,16 @@ module cv32e40px_core
   );
 
   //  CSR access
-  assign csr_addr     = csr_addr_int;
-  assign csr_wdata    = alu_operand_a_ex;
-  assign csr_op       = csr_op_ex;
+  assign csr_addr = csr_addr_int;
+  assign csr_wdata = alu_operand_a_ex;
+  assign csr_op = csr_op_ex;
 
   assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0);
 
-
+  //  Floating-Point registers write
+  assign fregs_we     = (FPU & !ZFINX) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
+                                          (regfile_we_wb     && regfile_waddr_fw_wb_o[5]))
+                                       : 1'b0;
 
   ///////////////////////////
   //   ____  __  __ ____   //
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv
index 2d873452..f24b3bf9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv
@@ -68,6 +68,7 @@ module cv32e40px_cs_registers
     output logic [        2:0] frm_o,
     input  logic [C_FFLAG-1:0] fflags_i,
     input  logic               fflags_we_i,
+    input  logic               fregs_we_i,
 
     // Interrupts
     output logic [31:0] mie_bypass_o,
@@ -212,6 +213,7 @@ module cv32e40px_cs_registers
 
   logic [31:0] exception_pc;
   Status_t mstatus_q, mstatus_n;
+  logic mstatus_we_int;
   FS_t mstatus_fs_q, mstatus_fs_n;
   logic [5:0] mcause_q, mcause_n;
   logic [5:0] ucause_q, ucause_n;
@@ -897,6 +899,7 @@ module cv32e40px_cs_registers
       dscratch0_n = dscratch0_q;
       dscratch1_n = dscratch1_q;
 
+      mstatus_we_int = 1'b0;
       mstatus_n = mstatus_q;
       mcause_n = mcause_q;
       ucause_n = '0;  // Not used if PULP_SECURE == 0
@@ -957,7 +960,8 @@ module cv32e40px_cs_registers
               mprv: csr_wdata_int[MSTATUS_MPRV_BIT]
           };
           if (FPU == 1 && ZFINX == 0) begin
-            mstatus_fs_n = FS_t'(csr_wdata_int[MSTATUS_FS_BIT_HIGH:MSTATUS_FS_BIT_LOW]);
+            mstatus_we_int = 1'b1;
+            mstatus_fs_n   = FS_t'(csr_wdata_int[MSTATUS_FS_BIT_HIGH:MSTATUS_FS_BIT_LOW]);
           end
         end
         // mie: machine interrupt enable
@@ -1027,7 +1031,7 @@ module cv32e40px_cs_registers
 
         if (ZFINX == 0) begin
           // FPU Register File/Flags implicit update or modified by CSR instructions
-          if (fflags_we_i || fcsr_update) begin
+          if ((fregs_we_i && !(mstatus_we_int && mstatus_fs_n != FS_DIRTY)) || fflags_we_i || fcsr_update) begin
             mstatus_fs_n = FS_DIRTY;
           end
         end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv
index 6ab1b01b..3beaf022 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv
@@ -34,6 +34,7 @@ module cv32e40px_ex_stage
   import cv32e40px_apu_core_pkg::*;
   import cv32e40px_core_v_xif_pkg::*;
 #(
+    parameter COREV_PULP       = 0,
     parameter FPU              = 0,
     parameter APU_NARGS_CPU    = 3,
     parameter APU_WOP_CPU      = 6,
@@ -82,6 +83,8 @@ module cv32e40px_ex_stage
     input logic data_misaligned_ex_i,
     input logic data_misaligned_i,
 
+    input logic [1:0] ctrl_transfer_insn_in_dec_i,
+
     // FPU signals
     output logic fpu_fflags_we_o,
     output logic [APU_NUSFLAGS_CPU-1:0] fpu_fflags_o,
@@ -152,11 +155,13 @@ module cv32e40px_ex_stage
     // Output of EX stage pipeline
     output logic [ 5:0] regfile_waddr_wb_o,
     output logic        regfile_we_wb_o,
+    output logic        regfile_we_wb_power_o,
     output logic [31:0] regfile_wdata_wb_o,
 
     // Forwarding ports : to ID stage
     output logic [ 5:0] regfile_alu_waddr_fw_o,
     output logic        regfile_alu_we_fw_o,
+    output logic        regfile_alu_we_fw_power_o,
     output logic [31:0] regfile_alu_wdata_fw_o,  // forward to RF and ID/EX pipe, ALU & MUL
 
     // To IF: Jump and branch target and decision
@@ -204,30 +209,36 @@ module cv32e40px_ex_stage
 
   // ALU write port mux
   always_comb begin
-    regfile_alu_wdata_fw_o = '0;
-    regfile_alu_waddr_fw_o = '0;
-    regfile_alu_we_fw_o    = '0;
-    wb_contention          = 1'b0;
-    result_fw_to_x_o       = '0;
+    regfile_alu_wdata_fw_o    = '0;
+    regfile_alu_waddr_fw_o    = '0;
+    regfile_alu_we_fw_o       = '0;
+    wb_contention             = 1'b0;
+    result_fw_to_x_o          = '0;
+    regfile_alu_we_fw_power_o = 1'b0;
     if (x_result_valid_assigned_i & x_result_we_i & (x_result_rd_i != 5'b00000)) begin
-      regfile_alu_we_fw_o    = 1'b1;
-      regfile_alu_waddr_fw_o = {1'b0, x_result_rd_i};
-      regfile_alu_wdata_fw_o = x_result_data_i;
+      regfile_alu_we_fw_o       = 1'b1;
+      regfile_alu_we_fw_power_o = 1'b1;
+      regfile_alu_waddr_fw_o    = {1'b0, x_result_rd_i};
+      regfile_alu_wdata_fw_o    = x_result_data_i;
       if (regfile_alu_we_i) begin
         wb_contention = 1'b1;
       end
     end else begin
       // APU single cycle operations, and multicycle operations (>2cycles) are written back on ALU port
       if (apu_valid & (apu_singlecycle | apu_multicycle)) begin
-        regfile_alu_we_fw_o    = 1'b1;
-        regfile_alu_waddr_fw_o = apu_waddr;
-        regfile_alu_wdata_fw_o = apu_result;
-        result_fw_to_x_o       = apu_result;
+        regfile_alu_we_fw_o       = 1'b1;
+        regfile_alu_we_fw_power_o = 1'b1;
+        regfile_alu_waddr_fw_o    = apu_waddr;
+        regfile_alu_wdata_fw_o    = apu_result;
+        result_fw_to_x_o          = apu_result;
         if (regfile_alu_we_i & ~apu_en_i) begin
           wb_contention = 1'b1;
         end
       end else begin
-        regfile_alu_we_fw_o    = regfile_alu_we_i & ~apu_en_i;  // private fpu incomplete?
+        regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i;  // private fpu incomplete?
+        regfile_alu_we_fw_power_o = !COREV_PULP ? regfile_alu_we_i & ~apu_en_i :
+                                                regfile_alu_we_i & ~apu_en_i &
+                                                mult_ready & alu_ready & lsu_ready_ex_i;
         regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
         if (alu_en_i) begin
           regfile_alu_wdata_fw_o = alu_result;
@@ -247,21 +258,24 @@ module cv32e40px_ex_stage
 
   // LSU write port mux
   always_comb begin
-    regfile_we_wb_o    = 1'b0;
-    regfile_waddr_wb_o = regfile_waddr_lsu;
-    regfile_wdata_wb_o = lsu_rdata_i;
-    wb_contention_lsu  = 1'b0;
+    regfile_we_wb_o       = 1'b0;
+    regfile_we_wb_power_o = 1'b0;
+    regfile_waddr_wb_o    = regfile_waddr_lsu;
+    regfile_wdata_wb_o    = lsu_rdata_i;
+    wb_contention_lsu     = 1'b0;
 
     if (regfile_we_lsu) begin
-      regfile_we_wb_o = 1'b1;
+      regfile_we_wb_o       = 1'b1;
+      regfile_we_wb_power_o = !COREV_PULP ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
       if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin
         wb_contention_lsu = 1'b1;
       end
       // APU two-cycle operations are written back on LSU port
     end else if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin
-      regfile_we_wb_o    = 1'b1;
-      regfile_waddr_wb_o = apu_waddr;
-      regfile_wdata_wb_o = apu_result;
+      regfile_we_wb_o       = 1'b1;
+      regfile_we_wb_power_o = 1'b1;
+      regfile_waddr_wb_o    = apu_waddr;
+      regfile_wdata_wb_o    = apu_result;
     end
   end
 
@@ -406,11 +420,20 @@ module cv32e40px_ex_stage
           apu_result_q <= 'b0;
           apu_flags_q  <= 'b0;
         end else begin
-          if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || (data_req_i && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
+          if (apu_rvalid_i && apu_multicycle &&
+              (data_misaligned_i || data_misaligned_ex_i ||
+               ((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
+               (mulh_active && (mult_operator_i == MUL_H)) ||
+               ((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
+                regfile_alu_we_i && ~apu_read_dep_for_jalr_o))) begin
             apu_rvalid_q <= 1'b1;
             apu_result_q <= apu_result_i;
             apu_flags_q  <= apu_flags_i;
-          end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
+          end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i ||
+                                         ((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
+                                         (mulh_active && (mult_operator_i == MUL_H)) ||
+                                         ((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
+                                          regfile_alu_we_i && ~apu_read_dep_for_jalr_o))) begin
             apu_rvalid_q <= 1'b0;
           end
         end
@@ -418,7 +441,12 @@ module cv32e40px_ex_stage
 
       assign apu_req_o = apu_req;
       assign apu_gnt = apu_gnt_i;
-      assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
+      assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i ||
+                                             ((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
+                                             (mulh_active && (mult_operator_i == MUL_H)) ||
+                                             ((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
+                                              regfile_alu_we_i && ~apu_read_dep_for_jalr_o)))
+                         ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
       assign apu_operands_o = apu_operands_i;
       assign apu_op_o = apu_op_i;
       assign apu_result = apu_rvalid_q ? apu_result_q : apu_result_i;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
index 8502e341..54add99d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
@@ -111,7 +111,7 @@ module cv32e40px_fp_wrapper
       .int_fmt_i     (fpnew_pkg::int_format_e'(fpu_int_fmt)),
       .vectorial_op_i(fpu_vec_op),
       .tag_i         (1'b0),
-      .simd_mask_i   ('b0),
+      .simd_mask_i   (1'b0),
       .in_valid_i    (apu_req_i),
       .in_ready_o    (apu_gnt_o),
       .flush_i       (1'b0),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
index 4c513d27..6e996c32 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
@@ -72,6 +72,7 @@ module cv32e40px_id_stage
     output logic        branch_in_ex_o,
     input  logic        branch_decision_i,
     output logic [31:0] jump_target_o,
+    output logic [ 1:0] ctrl_transfer_insn_in_dec_o,
 
     // IF and ID stage signals
     output logic       clear_instr_valid_o,
@@ -263,10 +264,12 @@ module cv32e40px_id_stage
     // Forward Signals
     input logic [5:0] regfile_waddr_wb_i,
     input logic regfile_we_wb_i,
+    input logic regfile_we_wb_power_i,
     input  logic [31:0] regfile_wdata_wb_i, // From wb_stage: selects data from data memory, ex_stage result and sp rdata
 
     input logic [ 5:0] regfile_alu_waddr_fw_i,
     input logic        regfile_alu_we_fw_i,
+    input logic        regfile_alu_we_fw_power_i,
     input logic [31:0] regfile_alu_wdata_fw_i,
 
     // from ALU
@@ -302,6 +305,9 @@ module cv32e40px_id_stage
   localparam REG_D_MSB = 11;
   localparam REG_D_LSB = 7;
 
+
+  localparam REGFILE_NUM_READ_PORTS = ((COREV_X_IF == 1) & (X_DUALREAD == 1)) ? 2 : 1;
+
   logic [31:0] instr;
 
 
@@ -381,9 +387,9 @@ module cv32e40px_id_stage
   logic [ 5:0] regfile_alu_waddr_id;
   logic regfile_alu_we_id, regfile_alu_we_dec_id;
 
-  logic [31:0] regfile_data_ra_id;
-  logic [31:0] regfile_data_rb_id;
-  logic [31:0] regfile_data_rc_id;
+  logic [REGFILE_NUM_READ_PORTS-1:0][31:0] regfile_data_ra_id;
+  logic [REGFILE_NUM_READ_PORTS-1:0][31:0] regfile_data_rb_id;
+  logic [REGFILE_NUM_READ_PORTS-1:0][31:0] regfile_data_rc_id;
 
   // ALU Control
   logic alu_en;
@@ -438,8 +444,8 @@ module cv32e40px_id_stage
   logic [2:0][4:0] x_rs_addr;
   logic x_mem_data_req;
   logic x_mem_valid;
-  logic [2:0] x_ex_fwd;
-  logic [2:0] x_wb_fwd;
+  logic [RF_READ_PORTS-1:0] x_ex_fwd;
+  logic [RF_READ_PORTS-1:0] x_wb_fwd;
 
   // Register Write Control
   logic regfile_we_id;
@@ -622,17 +628,18 @@ module cv32e40px_id_stage
   //  \___/ \__,_|_| |_| |_| .__/    |_|\__,_|_|  \__, |\___|\__| //
   //                       |_|                    |___/           //
   //////////////////////////////////////////////////////////////////
-
-  always_comb begin : jump_target_mux
-    unique case (ctrl_transfer_target_mux_sel)
-      JT_JAL:  jump_target = pc_id_i + imm_uj_type;
-      JT_COND: jump_target = pc_id_i + imm_sb_type;
-
-      // JALR: Cannot forward RS1, since the path is too long
-      JT_JALR: jump_target = regfile_data_ra_id + imm_i_type;
-      default: jump_target = regfile_data_ra_id + imm_i_type;
-    endcase
-  end
+  generate
+    always_comb begin : jump_target_mux
+      unique case (ctrl_transfer_target_mux_sel)
+        JT_JAL:  jump_target = pc_id_i + imm_uj_type;
+        JT_COND: jump_target = pc_id_i + imm_sb_type;
+
+        // JALR: Cannot forward RS1, since the path is too long
+        JT_JALR: jump_target = regfile_data_ra_id[0] + imm_i_type;
+        default: jump_target = regfile_data_ra_id[0] + imm_i_type;
+      endcase
+    end
+  endgenerate
 
   assign jump_target_o = jump_target;
 
@@ -666,16 +673,18 @@ module cv32e40px_id_stage
     endcase
   end
 
-  // Operand a forwarding mux
-  always_comb begin : operand_a_fw_mux
-    case (operand_a_fw_mux_sel)
-      SEL_FW_EX:   operand_a_fw_id = regfile_alu_wdata_fw_i;
-      SEL_FW_WB:   operand_a_fw_id = regfile_wdata_wb_i;
-      SEL_REGFILE: operand_a_fw_id = regfile_data_ra_id;
-      default:     operand_a_fw_id = regfile_data_ra_id;
-    endcase
-    ;  // case (operand_a_fw_mux_sel)
-  end
+  generate
+    // Operand a forwarding mux
+    always_comb begin : operand_a_fw_mux
+      case (operand_a_fw_mux_sel)
+        SEL_FW_EX:   operand_a_fw_id = regfile_alu_wdata_fw_i;
+        SEL_FW_WB:   operand_a_fw_id = regfile_wdata_wb_i;
+        SEL_REGFILE: operand_a_fw_id = regfile_data_ra_id[0];
+        default:     operand_a_fw_id = regfile_data_ra_id[0];
+      endcase
+      ;  // case (operand_a_fw_mux_sel)
+    end
+  endgenerate
 
   //////////////////////////////////////////////////////
   //   ___                                 _   ____   //
@@ -732,16 +741,31 @@ module cv32e40px_id_stage
   assign alu_operand_b = (scalar_replication == 1'b1) ? operand_b_vec : operand_b;
 
 
-  // Operand b forwarding mux
-  always_comb begin : operand_b_fw_mux
-    case (operand_b_fw_mux_sel)
-      SEL_FW_EX:   operand_b_fw_id = regfile_alu_wdata_fw_i;
-      SEL_FW_WB:   operand_b_fw_id = regfile_wdata_wb_i;
-      SEL_REGFILE: operand_b_fw_id = regfile_data_rb_id;
-      default:     operand_b_fw_id = regfile_data_rb_id;
-    endcase
-    ;  // case (operand_b_fw_mux_sel)
-  end
+  generate
+    if (X_DUALREAD == 0) begin : no_dualread_fw_b
+      // Operand b forwarding mux
+      always_comb begin : operand_b_fw_mux
+        case (operand_b_fw_mux_sel)
+          SEL_FW_EX:   operand_b_fw_id = regfile_alu_wdata_fw_i;
+          SEL_FW_WB:   operand_b_fw_id = regfile_wdata_wb_i;
+          SEL_REGFILE: operand_b_fw_id = regfile_data_rb_id;
+          default:     operand_b_fw_id = regfile_data_rb_id;
+        endcase
+        ;  // case (operand_b_fw_mux_sel)
+      end
+    end else begin : dualread_fw_b
+      // Operand b forwarding mux
+      always_comb begin : operand_b_fw_mux
+        case (operand_b_fw_mux_sel)
+          SEL_FW_EX:   operand_b_fw_id = regfile_alu_wdata_fw_i;
+          SEL_FW_WB:   operand_b_fw_id = regfile_wdata_wb_i;
+          SEL_REGFILE: operand_b_fw_id = regfile_data_rb_id[0];
+          default:     operand_b_fw_id = regfile_data_rb_id[0];
+        endcase
+        ;  // case (operand_b_fw_mux_sel)
+      end
+    end
+  endgenerate
 
 
   //////////////////////////////////////////////////////
@@ -777,17 +801,31 @@ module cv32e40px_id_stage
   assign alu_operand_c = (scalar_replication_c == 1'b1) ? operand_c_vec : operand_c;
 
 
-  // Operand c forwarding mux
-  always_comb begin : operand_c_fw_mux
-    case (operand_c_fw_mux_sel)
-      SEL_FW_EX:   operand_c_fw_id = regfile_alu_wdata_fw_i;
-      SEL_FW_WB:   operand_c_fw_id = regfile_wdata_wb_i;
-      SEL_REGFILE: operand_c_fw_id = regfile_data_rc_id;
-      default:     operand_c_fw_id = regfile_data_rc_id;
-    endcase
-    ;  // case (operand_c_fw_mux_sel)
-  end
-
+  generate
+    if (X_DUALREAD == 0) begin : no_dualread_fw_c
+      // Operand c forwarding mux
+      always_comb begin : operand_c_fw_mux
+        case (operand_c_fw_mux_sel)
+          SEL_FW_EX:   operand_c_fw_id = regfile_alu_wdata_fw_i;
+          SEL_FW_WB:   operand_c_fw_id = regfile_wdata_wb_i;
+          SEL_REGFILE: operand_c_fw_id = regfile_data_rc_id;
+          default:     operand_c_fw_id = regfile_data_rc_id;
+        endcase
+        ;  // case (operand_c_fw_mux_sel)
+      end
+    end else begin : dualread_fw_c
+      // Operand c forwarding mux
+      always_comb begin : operand_c_fw_mux
+        case (operand_c_fw_mux_sel)
+          SEL_FW_EX:   operand_c_fw_id = regfile_alu_wdata_fw_i;
+          SEL_FW_WB:   operand_c_fw_id = regfile_wdata_wb_i;
+          SEL_REGFILE: operand_c_fw_id = regfile_data_rc_id[0];
+          default:     operand_c_fw_id = regfile_data_rc_id[0];
+        endcase
+        ;  // case (operand_c_fw_mux_sel)
+      end
+    end
+  endgenerate
 
   ///////////////////////////////////////////////////////////////////////////
   //  ___                              _ _       _              ___ ____   //
@@ -865,6 +903,9 @@ module cv32e40px_id_stage
             if (ctrl_transfer_target_mux_sel == JT_JALR) begin
               apu_read_regs[0]       = regfile_addr_ra_id;
               apu_read_regs_valid[0] = 1'b1;
+            end else begin
+              apu_read_regs[0]       = regfile_addr_ra_id;
+              apu_read_regs_valid[0] = 1'b0;
             end
           end  // OP_A_CURRPC:
           OP_A_REGA_OR_FWD: begin
@@ -982,13 +1023,17 @@ module cv32e40px_id_stage
       .ADDR_WIDTH(6),
       .DATA_WIDTH(32),
       .FPU       (FPU),
-      .ZFINX     (ZFINX)
+      .ZFINX     (ZFINX),
+      .COREV_X_IF(COREV_X_IF),
+      .X_DUALREAD(X_DUALREAD)
   ) register_file_i (
       .clk  (clk),
       .rst_n(rst_n),
 
       .scan_cg_en_i(scan_cg_en_i),
 
+      .dualread_i(x_issue_resp_i.dualread),
+
       // Read port a
       .raddr_a_i(regfile_addr_ra_id),
       .rdata_a_o(regfile_data_ra_id),
@@ -1004,12 +1049,12 @@ module cv32e40px_id_stage
       // Write port a
       .waddr_a_i(regfile_waddr_wb_i),
       .wdata_a_i(regfile_wdata_wb_i),
-      .we_a_i   (regfile_we_wb_i),
+      .we_a_i   (regfile_we_wb_power_i),
 
       // Write port b
       .waddr_b_i(regfile_alu_waddr_fw_i),
       .wdata_b_i(regfile_alu_wdata_fw_i),
-      .we_b_i   (regfile_alu_we_fw_i)
+      .we_b_i   (regfile_alu_we_fw_power_i)
   );
 
   logic [1:0] x_mem_data_type_id;
@@ -1037,6 +1082,7 @@ module cv32e40px_id_stage
           .x_issue_valid_o         (x_issue_valid_o),
           .x_issue_ready_i         (x_issue_ready_i),
           .x_issue_resp_writeback_i(x_issue_resp_i.writeback),
+          .x_issue_resp_dualread_i (x_issue_resp_i.dualread),
           .x_issue_resp_accept_i   (x_issue_resp_i.accept),
           .x_issue_resp_loadstore_i(x_issue_resp_i.loadstore),
           .x_issue_req_rs_valid_o  (x_issue_req_o.rs_valid),
@@ -1118,22 +1164,25 @@ module cv32e40px_id_stage
       assign x_mem_valid = x_mem_valid_i;
 
       // xif integer souce operand selection
-      for (genvar i = 0; i < 3; i++) begin : xif_operand_assignment
-        always_comb begin
-          if (i == 0) begin
-            x_issue_req_o.rs[i] = regfile_data_ra_id;
-          end else if (i == 1) begin
-            x_issue_req_o.rs[i] = regfile_data_rb_id;
-          end else begin
-            x_issue_req_o.rs[i] = regfile_data_rc_id;
-          end
-          if (x_ex_fwd[i]) begin
-            x_issue_req_o.rs[i] = result_fw_to_x_i;
-          end else if (x_wb_fwd[i]) begin
-            x_issue_req_o.rs[i] = regfile_wdata_wb_i;
+      for (genvar j = 0; j < REGFILE_NUM_READ_PORTS; j++) begin : xif_operand_assignment_dualread
+        for (genvar i = 0; i < 3; i++) begin : xif_operand_assignment
+          always_comb begin
+            if (i == 0) begin
+              x_issue_req_o.rs[i+3*j] = regfile_data_ra_id[j];
+            end else if (i == 1) begin
+              x_issue_req_o.rs[i+3*j] = regfile_data_rb_id[j];
+            end else begin
+              x_issue_req_o.rs[i+3*j] = regfile_data_rc_id[j];
+            end
+            if (x_ex_fwd[i+3*j]) begin
+              x_issue_req_o.rs[i+3*j] = result_fw_to_x_i;
+            end else if (x_wb_fwd[i+3*j]) begin
+              x_issue_req_o.rs[i+3*j] = regfile_wdata_wb_i;
+            end
           end
         end
       end
+
       // LSU signal assignment/MUX
       always_comb begin
         x_mem_data_type_id = 2'b00;
@@ -1300,7 +1349,7 @@ module cv32e40px_id_stage
       .debug_wfi_no_sleep_i(debug_wfi_no_sleep),
 
       // jump/branches
-      .ctrl_transfer_insn_in_dec_o   (ctrl_transfer_insn_in_dec),
+      .ctrl_transfer_insn_in_dec_o   (ctrl_transfer_insn_in_dec_o),
       .ctrl_transfer_insn_in_id_o    (ctrl_transfer_insn_in_id),
       .ctrl_transfer_target_mux_sel_o(ctrl_transfer_target_mux_sel),
 
@@ -1400,7 +1449,7 @@ module cv32e40px_id_stage
       // jump/branch control
       .branch_taken_ex_i          (branch_taken_ex),
       .ctrl_transfer_insn_in_id_i (ctrl_transfer_insn_in_id),
-      .ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec),
+      .ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec_o),
 
       // Interrupt signals
       .irq_wu_ctrl_i     (irq_wu_ctrl),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_ff.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_ff.sv
index 1543f6e9..d0aad583 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_ff.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_ff.sv
@@ -31,7 +31,9 @@ module cv32e40px_register_file #(
     parameter ADDR_WIDTH = 5,
     parameter DATA_WIDTH = 32,
     parameter FPU        = 0,
-    parameter ZFINX      = 0
+    parameter ZFINX      = 0,
+    parameter COREV_X_IF = 0,
+    parameter X_DUALREAD = 0
 ) (
     // Clock and Reset
     input logic clk,
@@ -39,17 +41,19 @@ module cv32e40px_register_file #(
 
     input logic scan_cg_en_i,
 
+    input logic [2:0] dualread_i,
+
     //Read port R1
-    input  logic [ADDR_WIDTH-1:0] raddr_a_i,
-    output logic [DATA_WIDTH-1:0] rdata_a_o,
+    input logic [ADDR_WIDTH-1:0] raddr_a_i,
+    output logic [X_DUALREAD:0][DATA_WIDTH-1:0] rdata_a_o,
 
     //Read port R2
-    input  logic [ADDR_WIDTH-1:0] raddr_b_i,
-    output logic [DATA_WIDTH-1:0] rdata_b_o,
+    input logic [ADDR_WIDTH-1:0] raddr_b_i,
+    output logic [X_DUALREAD:0][DATA_WIDTH-1:0] rdata_b_o,
 
     //Read port R3
-    input  logic [ADDR_WIDTH-1:0] raddr_c_i,
-    output logic [DATA_WIDTH-1:0] rdata_c_o,
+    input logic [ADDR_WIDTH-1:0] raddr_c_i,
+    output logic [X_DUALREAD:0][DATA_WIDTH-1:0] rdata_c_o,
 
     // Write port W1
     input logic [ADDR_WIDTH-1:0] waddr_a_i,
@@ -86,17 +90,53 @@ module cv32e40px_register_file #(
   //-----------------------------------------------------------------------------
   //-- READ : Read address decoder RAD
   //-----------------------------------------------------------------------------
-  assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
-  assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
-  assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
-
+  generate
+    if (COREV_X_IF != 0) begin
+      if (X_DUALREAD) begin
+        always_comb begin
+          rdata_a_o[0] = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
+          rdata_b_o[0] = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
+          rdata_c_o[0] = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
+          if (dualread_i[0] == 1)
+            rdata_a_o[1] = raddr_a_i[5] ? (mem_fp[{
+              raddr_a_i[4:1], raddr_a_i[0]|1'b1
+            }]) : (mem[{
+              raddr_a_i[4:1], raddr_a_i[0]|1'b1
+            }]);
+          else rdata_a_o[1] = '0;
+          if (dualread_i[1] == 1)
+            rdata_b_o[1] = raddr_b_i[5] ? (mem_fp[{
+              raddr_b_i[4:1], raddr_b_i[0]|1'b1
+            }]) : (mem[{
+              raddr_b_i[4:1], raddr_b_i[0]|1'b1
+            }]);
+          else rdata_b_o[1] = '0;
+          if (dualread_i[2] == 1)
+            rdata_c_o[1] = raddr_c_i[5] ? (mem_fp[{
+              raddr_c_i[4:1], raddr_c_i[0]|1'b1
+            }]) : (mem[{
+              raddr_c_i[4:1], raddr_c_i[0]|1'b1
+            }]);
+          else rdata_c_o[1] = '0;
+        end
+      end else begin
+        assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
+        assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
+        assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
+      end
+    end else begin
+      assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
+      assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
+      assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
+    end
+  endgenerate
   //-----------------------------------------------------------------------------
   //-- WRITE : Write Address Decoder (WAD), combinatorial process
   //-----------------------------------------------------------------------------
 
   // Mask top bit of write address to disable fp regfile
-  assign waddr_a   = waddr_a_i;
-  assign waddr_b   = waddr_b_i;
+  assign waddr_a = waddr_a_i;
+  assign waddr_b = waddr_b_i;
 
   genvar gidx;
   generate
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv
index 037db7c4..217150c0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv
@@ -33,7 +33,9 @@ module cv32e40px_register_file #(
     parameter ADDR_WIDTH = 5,
     parameter DATA_WIDTH = 32,
     parameter FPU        = 0,
-    parameter ZFINX      = 0
+    parameter ZFINX      = 0,
+    parameter COREV_X_IF = 0,
+    parameter X_DUALREAD = 0
 ) (
     // Clock and Reset
     input logic clk,
@@ -41,17 +43,19 @@ module cv32e40px_register_file #(
 
     input logic scan_cg_en_i,
 
+    input logic dualread_i,
+
     //Read port R1
-    input  logic [ADDR_WIDTH-1:0] raddr_a_i,
-    output logic [DATA_WIDTH-1:0] rdata_a_o,
+    input logic [ADDR_WIDTH-1:0] raddr_a_i,
+    output logic [X_DUALREAD:0][DATA_WIDTH-1:0] rdata_a_o,
 
     //Read port R2
-    input  logic [ADDR_WIDTH-1:0] raddr_b_i,
-    output logic [DATA_WIDTH-1:0] rdata_b_o,
+    input logic [ADDR_WIDTH-1:0] raddr_b_i,
+    output logic [X_DUALREAD:0][DATA_WIDTH-1:0] rdata_b_o,
 
     //Read port R3
-    input  logic [ADDR_WIDTH-1:0] raddr_c_i,
-    output logic [DATA_WIDTH-1:0] rdata_c_o,
+    input logic [ADDR_WIDTH-1:0] raddr_c_i,
+    output logic [X_DUALREAD:0][DATA_WIDTH-1:0] rdata_c_o,
 
     // Write port W1
     input logic [ADDR_WIDTH-1:0] waddr_a_i,
@@ -98,10 +102,37 @@ module cv32e40px_register_file #(
   //-----------------------------------------------------------------------------
   //-- READ : Read address decoder RAD
   //-----------------------------------------------------------------------------
-  assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
-  assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
-  assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
-
+  generate
+    if (COREV_X_IF != 0) begin
+      if (X_DUALREAD) begin
+        always_comb begin
+          if (dualread_i) begin
+            rdata_a_o[0] = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
+            rdata_b_o[0] = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
+            rdata_c_o[0] = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
+            rdata_a_o[1] = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0] | 5'b00001] : mem[raddr_a_i[4:0] | 5'b00001];
+            rdata_b_o[1] = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0] | 5'b00001] : mem[raddr_b_i[4:0] | 5'b00001];
+            rdata_c_o[1] = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0] | 5'b00001] : mem[raddr_c_i[4:0] | 5'b00001];
+          end else begin
+            rdata_a_o[0] = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
+            rdata_b_o[0] = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
+            rdata_c_o[0] = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
+            rdata_b_o[1] = '0;
+            rdata_a_o[1] = '0;
+            rdata_c_o[1] = '0;
+          end
+        end
+      end else begin
+        assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
+        assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
+        assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
+      end
+    end else begin
+      assign rdata_a_o = raddr_a_i[5] ? mem_fp[raddr_a_i[4:0]] : mem[raddr_a_i[4:0]];
+      assign rdata_b_o = raddr_b_i[5] ? mem_fp[raddr_b_i[4:0]] : mem[raddr_b_i[4:0]];
+      assign rdata_c_o = raddr_c_i[5] ? mem_fp[raddr_c_i[4:0]] : mem[raddr_c_i[4:0]];
+    end
+  endgenerate
   //-----------------------------------------------------------------------------
   // WRITE : SAMPLE INPUT DATA
   //---------------------------------------------------------------------------
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
index 71bbf665..fe147124 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
@@ -33,11 +33,13 @@ module cv32e40px_x_disp
     input  logic       x_issue_ready_i,
     input  logic       x_issue_resp_accept_i,
     input  logic       x_issue_resp_writeback_i,
-    input  logic       x_issue_resp_loadstore_i,  // unused
-    output logic [2:0] x_issue_req_rs_valid_o,
-    output logic [3:0] x_issue_req_id_o,
-    output logic [1:0] x_issue_req_mode_o,
-    output logic       x_issue_req_ecs_valid,
+
+    input  logic [              2:0] x_issue_resp_dualread_i,
+    input  logic                     x_issue_resp_loadstore_i,  // unused
+    output logic [RF_READ_PORTS-1:0] x_issue_req_rs_valid_o,
+    output logic [              3:0] x_issue_req_id_o,
+    output logic [              1:0] x_issue_req_mode_o,
+    output logic                     x_issue_req_ecs_valid,
 
     // commit interface
     output logic       x_commit_valid_o,
@@ -65,19 +67,19 @@ module cv32e40px_x_disp
     input  logic       x_result_we_i,
 
     // scoreboard, dependency check, stall, forwarding
-    input  logic [4:0]      waddr_id_i,
-    input  logic [4:0]      waddr_ex_i,
-    input  logic [4:0]      waddr_wb_i,
-    input  logic            we_ex_i,
-    input  logic            we_wb_i,
-    input  logic [4:0]      mem_instr_waddr_ex_i,
-    input  logic            mem_instr_we_ex_i,
-    input  logic [2:0]      regs_used_i,
-    input  logic            branch_or_jump_i,
-    input  logic            instr_valid_i,
-    input  logic [2:0][4:0] x_rs_addr_i,
-    output logic [2:0]      x_ex_fwd_o,
-    output logic [2:0]      x_wb_fwd_o,
+    input  logic [              4:0]      waddr_id_i,
+    input  logic [              4:0]      waddr_ex_i,
+    input  logic [              4:0]      waddr_wb_i,
+    input  logic                          we_ex_i,
+    input  logic                          we_wb_i,
+    input  logic [              4:0]      mem_instr_waddr_ex_i,
+    input  logic                          mem_instr_we_ex_i,
+    input  logic [              2:0]      regs_used_i,
+    input  logic                          branch_or_jump_i,
+    input  logic                          instr_valid_i,
+    input  logic [              2:0][4:0] x_rs_addr_i,
+    output logic [RF_READ_PORTS-1:0]      x_ex_fwd_o,
+    output logic [RF_READ_PORTS-1:0]      x_wb_fwd_o,
 
     // memory request core-internal status signals
     output logic x_mem_data_req_o,
@@ -109,14 +111,31 @@ module cv32e40px_x_disp
   // issue interface
   assign x_issue_valid_o = x_illegal_insn_dec_i & ~branch_or_jump_i & ~instr_offloaded_q & instr_valid_i & ~illegal_forwarding_prevention;
   assign x_issue_req_id_o = id_q;
-  assign x_issue_req_rs_valid_o[0] = (~scoreboard_q[x_rs_addr_i[0]] | x_ex_fwd_o[0] | x_wb_fwd_o[0])
-                                     & ~(x_rs_addr_i[0] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[0] == waddr_wb_i & ~ex_valid_i);
-  assign x_issue_req_rs_valid_o[1] = (~scoreboard_q[x_rs_addr_i[1]] | x_ex_fwd_o[1] | x_wb_fwd_o[1])
-                                     & ~(x_rs_addr_i[1] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[1] == waddr_wb_i & ~ex_valid_i);
-  assign x_issue_req_rs_valid_o[2] = (~scoreboard_q[x_rs_addr_i[2]] | x_ex_fwd_o[2] | x_wb_fwd_o[2])
-                                     & ~(x_rs_addr_i[2] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[2] == waddr_wb_i & ~ex_valid_i);
-  assign x_issue_req_ecs_valid = 1'b1;  // extension context status is not implemented in cv32e40px
-
+  generate
+    if (X_DUALREAD != 0) begin
+      assign x_issue_req_rs_valid_o[0] = (~scoreboard_q[x_rs_addr_i[0]] | x_ex_fwd_o[0] | x_wb_fwd_o[0])
+                                         & ~(x_rs_addr_i[0] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[0] == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_rs_valid_o[1] = (~scoreboard_q[x_rs_addr_i[1]] | x_ex_fwd_o[1] | x_wb_fwd_o[1])
+                                         & ~(x_rs_addr_i[1] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[1] == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_rs_valid_o[2] = (~scoreboard_q[x_rs_addr_i[2]] | x_ex_fwd_o[2] | x_wb_fwd_o[2])
+                                         & ~(x_rs_addr_i[2] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[2] == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_rs_valid_o[3] = (~scoreboard_q[x_rs_addr_i[0] | 5'b00001] | x_ex_fwd_o[3] | x_wb_fwd_o[3])
+                                         & ~((x_rs_addr_i[0] | 5'b00001) == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~((x_rs_addr_i[0] | 5'b00001) == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_rs_valid_o[4] = (~scoreboard_q[x_rs_addr_i[1] | 5'b00001] | x_ex_fwd_o[4] | x_wb_fwd_o[4])
+                                         & ~((x_rs_addr_i[1] | 5'b00001) == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~((x_rs_addr_i[1] | 5'b00001) == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_rs_valid_o[5] = (~scoreboard_q[x_rs_addr_i[2] | 5'b00001] | x_ex_fwd_o[5] | x_wb_fwd_o[5])
+                                         & ~((x_rs_addr_i[2] | 5'b00001) == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~((x_rs_addr_i[2] | 5'b00001) == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_ecs_valid = 1'b1;  // extension context status is not implemented in cv32e40px
+    end else begin
+      assign x_issue_req_rs_valid_o[0] = (~scoreboard_q[x_rs_addr_i[0]] | x_ex_fwd_o[0] | x_wb_fwd_o[0])
+                                         & ~(x_rs_addr_i[0] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[0] == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_rs_valid_o[1] = (~scoreboard_q[x_rs_addr_i[1]] | x_ex_fwd_o[1] | x_wb_fwd_o[1])
+                                         & ~(x_rs_addr_i[1] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[1] == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_rs_valid_o[2] = (~scoreboard_q[x_rs_addr_i[2]] | x_ex_fwd_o[2] | x_wb_fwd_o[2])
+                                         & ~(x_rs_addr_i[2] == mem_instr_waddr_ex_i & mem_instr_we_ex_i) & ~(x_rs_addr_i[2] == waddr_wb_i & ~ex_valid_i);
+      assign x_issue_req_ecs_valid = 1'b1;  // extension context status is not implemented in cv32e40px
+    end
+  endgenerate
   // commit interface
   assign x_commit_valid_o = x_issue_valid_o;
   assign x_commit_id_o = id_q;
@@ -140,22 +159,46 @@ module cv32e40px_x_disp
 
   // core stall signal
   assign x_stall_o = dep | outstanding_mem | x_if_not_ready | x_if_memory_instr | illegal_forwarding_prevention;
-  assign dep = ~x_illegal_insn_o & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0]))
-                                  | (regs_used_i[1] & scoreboard_q[x_rs_addr_i[1]] & (x_result_rd_i != x_rs_addr_i[1]))
-                                  | (regs_used_i[2] & scoreboard_q[x_rs_addr_i[2]] & (x_result_rd_i != x_rs_addr_i[2])));
+
   assign outstanding_mem = data_req_dec_i & (mem_counter_q != '0);
   assign x_if_memory_instr = x_mem_data_req_o & ~(x_issue_valid_o & x_issue_ready_i);
   assign x_if_not_ready = x_issue_valid_o & ~x_issue_ready_i;
 
-  assign illegal_forwarding_prevention = x_result_valid_i & (x_ex_fwd_o[0] | x_ex_fwd_o[1] | x_ex_fwd_o[2]);
+  assign illegal_forwarding_prevention = x_result_valid_i & (|x_ex_fwd_o);
 
   // forwarding
-  assign x_ex_fwd_o[0] = x_rs_addr_i[0] == waddr_ex_i & we_ex_i & ex_valid_i;
-  assign x_ex_fwd_o[1] = x_rs_addr_i[1] == waddr_ex_i & we_ex_i & ex_valid_i;
-  assign x_ex_fwd_o[2] = x_rs_addr_i[2] == waddr_ex_i & we_ex_i & ex_valid_i;
-  assign x_wb_fwd_o[0] = x_rs_addr_i[0] == waddr_wb_i & we_wb_i & ex_valid_i;
-  assign x_wb_fwd_o[1] = x_rs_addr_i[1] == waddr_wb_i & we_wb_i & ex_valid_i;
-  assign x_wb_fwd_o[2] = x_rs_addr_i[2] == waddr_wb_i & we_wb_i & ex_valid_i;
+  generate
+    if (X_DUALREAD != 0) begin
+      assign x_ex_fwd_o[0] = x_rs_addr_i[0] == waddr_ex_i & we_ex_i & ex_valid_i;
+      assign x_ex_fwd_o[1] = x_rs_addr_i[1] == waddr_ex_i & we_ex_i & ex_valid_i;
+      assign x_ex_fwd_o[2] = x_rs_addr_i[2] == waddr_ex_i & we_ex_i & ex_valid_i;
+      assign x_ex_fwd_o[3] = (x_rs_addr_i[0] | 5'b00001) == waddr_ex_i & we_ex_i & ex_valid_i & x_issue_resp_dualread_i[0];
+      assign x_ex_fwd_o[4] = (x_rs_addr_i[1] | 5'b00001) == waddr_ex_i & we_ex_i & ex_valid_i & x_issue_resp_dualread_i[1];
+      assign x_ex_fwd_o[5] = (x_rs_addr_i[2] | 5'b00001) == waddr_ex_i & we_ex_i & ex_valid_i & x_issue_resp_dualread_i[2];
+      assign x_wb_fwd_o[0] = x_rs_addr_i[0] == waddr_wb_i & we_wb_i & ex_valid_i;
+      assign x_wb_fwd_o[1] = x_rs_addr_i[1] == waddr_wb_i & we_wb_i & ex_valid_i;
+      assign x_wb_fwd_o[2] = x_rs_addr_i[2] == waddr_wb_i & we_wb_i & ex_valid_i;
+      assign x_wb_fwd_o[3] = (x_rs_addr_i[0] | 5'b00001) == waddr_wb_i & we_wb_i & ex_valid_i & x_issue_resp_dualread_i[0];
+      assign x_wb_fwd_o[4] = (x_rs_addr_i[1] | 5'b00001) == waddr_wb_i & we_wb_i & ex_valid_i & x_issue_resp_dualread_i[1];
+      assign x_wb_fwd_o[5] = (x_rs_addr_i[2] | 5'b00001) == waddr_wb_i & we_wb_i & ex_valid_i & x_issue_resp_dualread_i[2];
+      assign dep = ~x_illegal_insn_o & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0]))
+                                  |     (regs_used_i[1] & scoreboard_q[x_rs_addr_i[1]] & (x_result_rd_i != x_rs_addr_i[1]))
+                                  |     (regs_used_i[2] & scoreboard_q[x_rs_addr_i[2]] & (x_result_rd_i != x_rs_addr_i[2]))
+                                  |     (((regs_used_i[0] & x_issue_resp_dualread_i[0]) & scoreboard_q[x_rs_addr_i[0] | 5'b00001] & (x_result_rd_i != (x_rs_addr_i[0] | 5'b00001))) & x_issue_resp_dualread_i[0])
+                                  |     (((regs_used_i[1] & x_issue_resp_dualread_i[1]) & scoreboard_q[x_rs_addr_i[1] | 5'b00001] & (x_result_rd_i != (x_rs_addr_i[1] | 5'b00001))) & x_issue_resp_dualread_i[1])
+                                  |     (((regs_used_i[2] & x_issue_resp_dualread_i[2]) & scoreboard_q[x_rs_addr_i[2] | 5'b00001] & (x_result_rd_i != (x_rs_addr_i[2] | 5'b00001))) & x_issue_resp_dualread_i[2]));
+    end else begin
+      assign x_ex_fwd_o[0] = x_rs_addr_i[0] == waddr_ex_i & we_ex_i & ex_valid_i;
+      assign x_ex_fwd_o[1] = x_rs_addr_i[1] == waddr_ex_i & we_ex_i & ex_valid_i;
+      assign x_ex_fwd_o[2] = x_rs_addr_i[2] == waddr_ex_i & we_ex_i & ex_valid_i;
+      assign x_wb_fwd_o[0] = x_rs_addr_i[0] == waddr_wb_i & we_wb_i & ex_valid_i;
+      assign x_wb_fwd_o[1] = x_rs_addr_i[1] == waddr_wb_i & we_wb_i & ex_valid_i;
+      assign x_wb_fwd_o[2] = x_rs_addr_i[2] == waddr_wb_i & we_wb_i & ex_valid_i;
+      assign dep = ~x_illegal_insn_o & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0]))
+                                  |     (regs_used_i[1] & scoreboard_q[x_rs_addr_i[1]] & (x_result_rd_i != x_rs_addr_i[1]))
+                                  |     (regs_used_i[2] & scoreboard_q[x_rs_addr_i[2]] & (x_result_rd_i != x_rs_addr_i[2])));
+    end
+  endgenerate
 
   // id generation
   assign x_compressed_id_o = id_d;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/include/cv32e40px_core_v_xif_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/include/cv32e40px_core_v_xif_pkg.sv
index 499fec31..678635d0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/include/cv32e40px_core_v_xif_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/include/cv32e40px_core_v_xif_pkg.sv
@@ -15,6 +15,7 @@ package cv32e40px_core_v_xif_pkg;
 
   // cv-x-if parameters
   parameter int X_NUM_RS = 3;
+  parameter int X_DUALREAD = 0;  // 0: single read, 1: dual read
   parameter int X_ID_WIDTH = 4;
   parameter int X_MEM_WIDTH = 32;
   parameter int X_RFR_WIDTH = 32;
@@ -23,6 +24,8 @@ package cv32e40px_core_v_xif_pkg;
   parameter logic [1:0] X_ECS_XS = '0;
 
   localparam int XLEN = 32;
+  localparam int RF_READ_PORTS = (X_DUALREAD == 1) ? 2 * X_NUM_RS : X_NUM_RS;
+
 
   typedef struct packed {
     logic [15:0] instr;  // Offloaded compressed instruction
@@ -39,8 +42,8 @@ package cv32e40px_core_v_xif_pkg;
     logic [31:0] instr;  // Offloaded instruction
     logic [1:0] mode;  // Privilege level
     logic [X_ID_WIDTH-1:0] id;  // Identification of the offloaded instruction
-    logic [X_NUM_RS  -1:0][X_RFR_WIDTH-1:0] rs;        // Register file source operands for the offloaded instruction
-    logic [X_NUM_RS  -1:0] rs_valid;  // Validity of the register file source operand(s)
+    logic [RF_READ_PORTS-1:0][X_RFR_WIDTH-1:0] rs;        // Register file source operands for the offloaded instruction
+    logic [RF_READ_PORTS-1:0] rs_valid;  // Validity of the register file source operand(s)
     logic [5:0] ecs;  // Extension Context Status ({mstatus.xs, mstatus.fs, mstatus.vs})
     logic ecs_valid;  // Validity of the Extension Context Status
   } x_issue_req_t;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.sv
index 07c75cf8..2be4df54 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.sv
@@ -84,11 +84,13 @@ module uartdpi #(
 
 `ifndef VCS
 `ifndef MODELSIM
+`ifndef XCELIUM
   initial begin
     // Prevent falling edges of rx_i before reset causing spurious characters
     seen_reset = 0;
   end
 `endif
+`endif
 `endif
 
   // RX
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/.readthedocs.yaml b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/.readthedocs.yaml
new file mode 100644
index 00000000..00178f19
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/.readthedocs.yaml
@@ -0,0 +1,23 @@
+# Copyright 2023 OpenHW Group
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# Read the Docs configuration file
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+# Required
+version: 2
+
+build:
+  os: "ubuntu-20.04"
+  tools:
+    python: "3.9"
+
+# Build from the docs directory with Sphinx
+sphinx:
+  configuration: doc/conf.py
+
+# Explicitly set the Python requirements
+python:
+  install:
+    - requirements: doc/requirements.txt
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/bhv/cve2_sim_clock_gate.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/bhv/cve2_sim_clock_gate.sv
index 8cc81dd3..7974cf92 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/bhv/cve2_sim_clock_gate.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/bhv/cve2_sim_clock_gate.sv
@@ -27,4 +27,4 @@ module cve2_clock_gate (
 
   assign clk_o = clk_i & clk_en;
 
-endmodule  // cv32e40p_clock_gate
+endmodule  // cve2_clock_gate
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cv32e20_manifest.flist b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cv32e20_manifest.flist
new file mode 100644
index 00000000..4a0142d8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cv32e20_manifest.flist
@@ -0,0 +1,63 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Copyright 2022 OpenHW Group
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+///////////////////////////////////////////////////////////////////////////////
+//
+// Manifest for the CV32E20 RTL model.
+//   - Format based on manifest used by other CORE-V cores.
+//   - Intended to be used by both synthesis and simulation.
+//   - Relevent synthesis and simulation scripts/Makefiles must set the shell
+//     ENV variable DESIGN_RTL_DIR as required.
+//
+// TODO: Replace once-and-for-all with unified manifest (FuseSoc?)
+//
+///////////////////////////////////////////////////////////////////////////////
+
++incdir+${DESIGN_RTL_DIR}/../shared/rtl/
++incdir+${DESIGN_RTL_DIR}/../rtl
++incdir+${DESIGN_RTL_DIR}/../shared/rtl/sim
++incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl
++incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/dv/sv/dv_utils
+
+${DESIGN_RTL_DIR}/cve2_pkg.sv
+${DESIGN_RTL_DIR}/cve2_tracer_pkg.sv
+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
+${DESIGN_RTL_DIR}/cve2_alu.sv
+${DESIGN_RTL_DIR}/cve2_compressed_decoder.sv
+${DESIGN_RTL_DIR}/cve2_controller.sv
+${DESIGN_RTL_DIR}/cve2_cs_registers.sv
+${DESIGN_RTL_DIR}/cve2_csr.sv
+${DESIGN_RTL_DIR}/cve2_counter.sv
+${DESIGN_RTL_DIR}/cve2_decoder.sv
+${DESIGN_RTL_DIR}/cve2_ex_block.sv
+${DESIGN_RTL_DIR}/cve2_fetch_fifo.sv
+${DESIGN_RTL_DIR}/cve2_id_stage.sv
+${DESIGN_RTL_DIR}/cve2_if_stage.sv
+${DESIGN_RTL_DIR}/cve2_load_store_unit.sv
+${DESIGN_RTL_DIR}/cve2_multdiv_fast.sv
+${DESIGN_RTL_DIR}/cve2_multdiv_slow.sv
+${DESIGN_RTL_DIR}/cve2_prefetch_buffer.sv
+${DESIGN_RTL_DIR}/cve2_pmp.sv
+${DESIGN_RTL_DIR}/cve2_register_file_ff.sv
+${DESIGN_RTL_DIR}/cve2_wb.sv
+${DESIGN_RTL_DIR}/cve2_core.sv
+${DESIGN_RTL_DIR}/cve2_top.sv
+${DESIGN_RTL_DIR}/cve2_top_tracing.sv
+${DESIGN_RTL_DIR}/cve2_tracer.sv
+
+${DESIGN_RTL_DIR}/../bhv/cve2_sim_clock_gate.sv
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_configs.yaml b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_configs.yaml
new file mode 100644
index 00000000..1dba358d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_configs.yaml
@@ -0,0 +1,94 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Ibex configurations files, holds the parameter sets that are tested under CI.
+# Each configuration must specify the same set of parameters
+
+# Two-stage pipeline without additional branch target ALU and 3 cycle multiplier
+# (4 cycles for mulh), resulting in 2 stall cycles for mul (3 for mulh)
+small:
+  RV32E                    : 0
+  RV32M                    : "cve2_pkg::RV32MFast"
+  RV32B                    : "cve2_pkg::RV32BNone"
+  RegFile                  : "cve2_pkg::RegFileFF"
+  WritebackStage           : 0
+  PMPEnable                : 0
+  PMPGranularity           : 0
+  PMPNumRegions            : 4
+
+# Configuration to match that used in the OpenTitan project
+opentitan:
+  RV32E                    : 0
+  RV32M                    : "cve2_pkg::RV32MSingleCycle"
+  RV32B                    : "cve2_pkg::RV32BOTEarlGrey"
+  RegFile                  : "cve2_pkg::RegFileFF"
+  WritebackStage           : 1
+  PMPEnable                : 1
+  PMPGranularity           : 0
+  PMPNumRegions            : 16
+
+# ===============================
+# * EXPERIMENTAL CONFIGURATIONS *
+# ===============================
+
+# Three-stage pipeline with additional branch traget ALU and 1 cycle multiplier
+# (2 cycles for mulh) so mul does not stall (mulh stall 1 cycles). This is the
+# maximum performance configuration.
+experimental-maxperf:
+  RV32E                    : 0
+  RV32M                    : "cve2_pkg::RV32MSingleCycle"
+  RV32B                    : "cve2_pkg::RV32BNone"
+  RegFile                  : "cve2_pkg::RegFileFF"
+  WritebackStage           : 1
+  PMPEnable                : 0
+  PMPGranularity           : 0
+  PMPNumRegions            : 4
+
+# experimental-maxperf config above plus PMP enabled with 16 regions.
+experimental-maxperf-pmp:
+  RV32E                    : 0
+  RV32M                    : "cve2_pkg::RV32MSingleCycle"
+  RV32B                    : "cve2_pkg::RV32BNone"
+  RegFile                  : "cve2_pkg::RegFileFF"
+  WritebackStage           : 1
+  PMPEnable                : 1
+  PMPGranularity           : 0
+  PMPNumRegions            : 16
+
+# experimental-maxperf-pmp config above with balanced bitmanip extension
+experimental-maxperf-pmp-bmbalanced:
+  RV32E                    : 0
+  RV32M                    : "cve2_pkg::RV32MSingleCycle"
+  RV32B                    : "cve2_pkg::RV32BBalanced"
+  RegFile                  : "cve2_pkg::RegFileFF"
+  WritebackStage           : 1
+  PMPEnable                : 1
+  PMPGranularity           : 0
+  PMPNumRegions            : 16
+
+# experimental-maxperf-pmp config above with full bitmanip extension
+experimental-maxperf-pmp-bmfull:
+  RV32E                    : 0
+  RV32M                    : "cve2_pkg::RV32MSingleCycle"
+  RV32B                    : "cve2_pkg::RV32BFull"
+  RegFile                  : "cve2_pkg::RegFileFF"
+  WritebackStage           : 1
+  PMPEnable                : 1
+  PMPGranularity           : 0
+  PMPNumRegions            : 16
+
+# experimental-maxperf with branch predictor switched on. This exists to allow
+# easy use of Ibex with the branch predictor in particular for CI runs. The
+# branch predictor will be enabled in all the 'maxperf' configs after further
+# development.
+experimental-branch-predictor:
+  RV32E                    : 0
+  RV32M                    : "cve2_pkg::RV32MSingleCycle"
+  RV32B                    : "cve2_pkg::RV32BNone"
+  RegFile                  : "cve2_pkg::RegFileFF"
+  WritebackStage           : 1
+  PMPEnable                : 0
+  PMPGranularity           : 0
+  PMPNumRegions            : 4
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_core.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_core.core
new file mode 100644
index 00000000..6d621a43
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_core.core
@@ -0,0 +1,115 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "openhwgroup:cve2:cve2_core:0.1"
+description: "Ibex CPU Core Components"
+
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+      - openhwgroup:cve2:cve2_pkg
+      - lowrisc:dv:dv_fcov_macros
+    files:
+      - rtl/cve2_alu.sv
+      - rtl/cve2_branch_predict.sv
+      - rtl/cve2_compressed_decoder.sv
+      - rtl/cve2_controller.sv
+      - rtl/cve2_cs_registers.sv
+      - rtl/cve2_csr.sv
+      - rtl/cve2_counter.sv
+      - rtl/cve2_decoder.sv
+      - rtl/cve2_ex_block.sv
+      - rtl/cve2_fetch_fifo.sv
+      - rtl/cve2_id_stage.sv
+      - rtl/cve2_if_stage.sv
+      - rtl/cve2_load_store_unit.sv
+      - rtl/cve2_multdiv_fast.sv
+      - rtl/cve2_multdiv_slow.sv
+      - rtl/cve2_prefetch_buffer.sv
+      - rtl/cve2_pmp.sv
+      - rtl/cve2_wb.sv
+      - rtl/cve2_core.sv
+      - rtl/cve2_pmp_reset_default.svh: {is_include_file: true}
+    file_type: systemVerilogSource
+
+  files_lint_verilator:
+    files:
+      - lint/verilator_waiver.vlt: {file_type: vlt}
+
+  files_lint_verible:
+    files:
+      - lint/verible_waiver.vbw: {file_type: veribleLintWaiver}
+
+  files_check_tool_requirements:
+    depend:
+     - lowrisc:tool:check_tool_requirements
+
+parameters:
+  RVFI:
+    datatype: bool
+    paramtype: vlogdefine
+
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+  FPGA_XILINX:
+    datatype: bool
+    description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
+    default: false
+    paramtype: vlogdefine
+
+  RV32E:
+    datatype: int
+    default: 0
+    paramtype: vlogparam
+
+  RV32M:
+    datatype: str
+    default: cve2_pkg::RV32MFast
+    paramtype: vlogdefine
+    description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
+
+  RV32B:
+    datatype: str
+    default: cve2_pkg::RV32BNone
+    paramtype: vlogdefine
+    description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
+
+targets:
+  default: &default_target
+    filesets:
+      - tool_verilator ? (files_lint_verilator)
+      - tool_veriblelint ? (files_lint_verible)
+      - files_rtl
+    toplevel: cve2_core
+    parameters:
+      - tool_vivado ? (FPGA_XILINX=true)
+  lint:
+    <<: *default_target
+    parameters:
+      - SYNTHESIS=true
+      - RVFI=true
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"
+          # RAM primitives wider than 64bit (required for ECC) fail to build in
+          # Verilator without increasing the unroll count (see Verilator#1266)
+          - "--unroll-count 72"
+  format:
+    filesets:
+      - files_rtl
+    parameters:
+      - SYNTHESIS=true
+      - RVFI=true
+    default_tool: veribleformat
+    toplevel: cve2_core
+    tools:
+      veribleformat:
+        verible_format_args:
+          - "--inplace"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_icache.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_icache.core
new file mode 100644
index 00000000..ad2c2617
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_icache.core
@@ -0,0 +1,22 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:cve2:cve2_icache:0.1"
+description: "Ibex instruction cache"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:secded
+      - lowrisc:prim:assert
+      - lowrisc:cve2:cve2_pkg
+    files:
+      - rtl/cve2_icache.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl
+    toplevel: cve2_icache
+    default_tool: vcs
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_multdiv.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_multdiv.core
new file mode 100644
index 00000000..700e6c9e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_multdiv.core
@@ -0,0 +1,28 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:cve2:cve2_multdiv:0.1"
+description: "Multiplier and divider"
+
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+      - lowrisc:cve2:cve2_pkg
+    files:
+      - rtl/cve2_multdiv_fast.sv
+      - rtl/cve2_multdiv_slow.sv
+    file_type: systemVerilogSource
+
+parameters:
+  RV32M:
+    datatype: int
+    default: 2
+    paramtype: vlogparam
+    description: "Selection of multiplication implementation. Switch to enable single cycle multiplications."
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/ibex_pkg.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_pkg.core
similarity index 73%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/ibex_pkg.core
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_pkg.core
index 17f47e08..a89c9e12 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/ibex_pkg.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_pkg.core
@@ -2,13 +2,13 @@ CAPI=2:
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:ibex:ibex_pkg:0.1"
-description: "Header package for Ibex"
+name: "openhwgroup:cve2:cve2_pkg:0.1"
+description: "Header package for CVE2"
 
 filesets:
   files_rtl:
     files:
-      - rtl/ibex_pkg.sv
+      - rtl/cve2_pkg.sv
     file_type: systemVerilogSource
 
 targets:
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_top.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_top.core
new file mode 100644
index 00000000..0d9d2c5c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_top.core
@@ -0,0 +1,115 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "openhwgroup:cve2:cve2_top:0.1"
+description: "Ibex, a small RV32 CPU core"
+
+filesets:
+  files_rtl:
+    depend:
+      - openhwgroup:cve2:cve2_pkg
+      - openhwgroup:cve2:cve2_core
+      - lowrisc:prim:buf
+      - lowrisc:prim:clock_mux2
+      - lowrisc:prim:flop
+      - lowrisc:prim:ram_1p_scr
+    files:
+      - rtl/cve2_register_file_ff.sv # generic FF-based
+      - rtl/cve2_top.sv
+    file_type: systemVerilogSource
+
+  files_lint_verilator:
+    files:
+      - lint/verilator_waiver.vlt: {file_type: vlt}
+
+  files_lint_verible:
+    files:
+      - lint/verible_waiver.vbw: {file_type: veribleLintWaiver}
+
+  files_check_tool_requirements:
+    depend:
+     - lowrisc:tool:check_tool_requirements
+
+  files_clk_gate:
+    files:
+      - bhv/cve2_sim_clock_gate.sv
+    file_type: systemVerilogSource
+
+parameters:
+  RVFI:
+    datatype: bool
+    paramtype: vlogdefine
+
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+  FPGA_XILINX:
+    datatype: bool
+    description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
+    default: false
+    paramtype: vlogdefine
+
+  RV32E:
+    datatype: int
+    default: 0
+    paramtype: vlogparam
+
+  RV32M:
+    datatype: str
+    default: cve2_pkg::RV32MFast
+    paramtype: vlogdefine
+    description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
+
+  RV32B:
+    datatype: str
+    default: cve2_pkg::RV32BNone
+    paramtype: vlogdefine
+    description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
+
+targets:
+  default: &default_target
+    filesets:
+      - tool_verilator ? (files_lint_verilator)
+      - tool_veriblelint ? (files_lint_verible)
+      - files_rtl
+      - target_sim ? (files_clk_gate)
+      - target_sim_sc ? (files_clk_gate)
+    toplevel: cve2_top
+    parameters:
+      - tool_vivado ? (FPGA_XILINX=true)
+
+  lint:
+    <<: *default_target
+    parameters:
+      - SYNTHESIS=true
+      - RVFI=true
+    filesets_append:
+    - files_clk_gate
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"
+          # RAM primitives wider than 64bit (required for ECC) fail to build in
+          # Verilator without increasing the unroll count (see Verilator#1266)
+          - "--unroll-count 72"
+
+  format:
+    filesets:
+      - files_rtl
+    parameters:
+      - SYNTHESIS=true
+      - RVFI=true
+    default_tool: veribleformat
+    toplevel: cve2_top
+    tools:
+      veribleformat:
+        verible_format_args:
+          - "--inplace"
+          - "--formal_parameters_indentation=indent"
+          - "--named_parameter_indentation=indent"
+          - "--named_port_indentation=indent"
+          - "--port_declarations_indentation=indent"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_top_tracing.core
similarity index 52%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2.core
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_top_tracing.core
index ec43f9cb..65d2b5b7 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_top_tracing.core
@@ -2,68 +2,28 @@ CAPI=2:
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-
-name: "openhwgroup.org:ip:cve2"
-description: "OpenHW Group RISC-V Core CVE2"
-
+name: "lowrisc:cve2:cve2_top_tracing:0.1"
+description: "Ibex, a small RV32 CPU core with tracing enabled"
 filesets:
   files_rtl:
     depend:
-      - lowrisc:prim:assert
-      - lowrisc:ibex:ibex_pkg
-    files:
-      - rtl/ibex_alu.sv
-      - rtl/ibex_branch_predict.sv
-      - rtl/ibex_compressed_decoder.sv
-      - rtl/ibex_controller.sv
-      - rtl/ibex_cs_registers.sv
-      - rtl/ibex_csr.sv
-      - rtl/ibex_counter.sv
-      - rtl/ibex_decoder.sv
-      - rtl/ibex_ex_block.sv
-      - rtl/ibex_fetch_fifo.sv
-      - rtl/ibex_id_stage.sv
-      - rtl/ibex_if_stage.sv
-      - rtl/ibex_load_store_unit.sv
-      - rtl/ibex_multdiv_fast.sv
-      - rtl/ibex_multdiv_slow.sv
-      - rtl/ibex_prefetch_buffer.sv
-      - rtl/ibex_pmp.sv
-      - rtl/ibex_wb_stage.sv
-      - rtl/ibex_dummy_instr.sv
-      - rtl/ibex_core.sv
-      - rtl/cve2_sleep_unit.sv
-      - rtl/ibex_pmp_reset_default.svh: {is_include_file: true}
-    file_type: systemVerilogSource
-
-  files_lint_verilator:
-    files:
-      - lint/verilator_waiver.vlt: {file_type: vlt}
-
-  files_lint_verible:
-    files:
-      - lint/verible_waiver.vbw: {file_type: veribleLintWaiver}
-
-  files_clk_gate:
+      - lowrisc:cve2:cve2_top
+      - lowrisc:cve2:cve2_tracer
     files:
-    - bhv/cve2_sim_clock_gate.sv
+      - rtl/cve2_top_tracing.sv
     file_type: systemVerilogSource
 
 parameters:
+  # The tracer uses the RISC-V Formal Interface (RVFI) to collect trace signals.
   RVFI:
     datatype: bool
     paramtype: vlogdefine
+    default: true
 
   SYNTHESIS:
     datatype: bool
     paramtype: vlogdefine
 
-  FPGA_XILINX:
-    datatype: bool
-    description: Identifies Xilinx FPGA targets to set DSP pragmas for performance counters.
-    default: false
-    paramtype: vlogdefine
-
   RV32E:
     datatype: int
     default: 0
@@ -71,21 +31,21 @@ parameters:
 
   RV32M:
     datatype: str
-    default: ibex_pkg::RV32MFast
+    default: cve2_pkg::RV32MFast
     paramtype: vlogdefine
-    description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
+    description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
 
   RV32B:
     datatype: str
-    default: ibex_pkg::RV32BNone
+    default: cve2_pkg::RV32BNone
     paramtype: vlogdefine
-    description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
+    description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
 
   RegFile:
     datatype: str
-    default: ibex_pkg::RegFileFF
+    default: cve2_pkg::RegFileFF
     paramtype: vlogdefine
-    description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
+    description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
 
   ICache:
     datatype: int
@@ -99,29 +59,23 @@ parameters:
     paramtype: vlogparam
     description: "Enable ECC protection in instruction cache"
 
-  BranchTargetALU:
-    datatype: int
-    default: 0
-    paramtype: vlogparam
-    description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
-
   WritebackStage:
     datatype: int
     default: 0
     paramtype: vlogparam
     description: "Enables third pipeline stage (EXPERIMENTAL) [0/1]"
 
-  BranchPredictor:
+  SecureCVE2:
     datatype: int
-    paramtype: vlogparam
     default: 0
-    description: "Enables static branch prediction (EXPERIMENTAL)"
+    paramtype: vlogparam
+    description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
 
-  SecureIbex:
+  ICacheScramble:
     datatype: int
     default: 0
     paramtype: vlogparam
-    description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
+    description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]"
 
   PMPEnable:
     datatype: int
@@ -144,19 +98,28 @@ parameters:
 targets:
   default: &default_target
     filesets:
-      - tool_verilator ? (files_lint_verilator)
-      - tool_veriblelint ? (files_lint_verible)
       - files_rtl
-      - target_sim? (files_clk_gate)
-      - target_sim-opt? (files_clk_gate)
-    toplevel: ibex_core
     parameters:
-      - tool_vivado ? (FPGA_XILINX=true)
+      - RVFI=true
+    toplevel: cve2_top_tracing
+
   lint:
     <<: *default_target
     parameters:
-      - SYNTHESIS=true
       - RVFI=true
+      - SYNTHESIS=true
+      - RV32E
+      - RV32M
+      - RV32B
+      - RegFile
+      - ICache
+      - ICacheECC
+      - WritebackStage
+      - SecureCVE2
+      - ICacheScramble
+      - PMPEnable
+      - PMPGranularity
+      - PMPNumRegions
     default_tool: verilator
     tools:
       verilator:
@@ -173,8 +136,12 @@ targets:
       - SYNTHESIS=true
       - RVFI=true
     default_tool: veribleformat
-    toplevel: ibex_core
+    toplevel: cve2_top_tracing
     tools:
       veribleformat:
         verible_format_args:
           - "--inplace"
+          - "--formal_parameters_indentation=indent"
+          - "--named_parameter_indentation=indent"
+          - "--named_port_indentation=indent"
+          - "--port_declarations_indentation=indent"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_tracer.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_tracer.core
new file mode 100644
index 00000000..0e43a806
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/cve2_tracer.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:cve2:cve2_tracer:0.1"
+description: "Tracer for use with Ibex using the RVFI interface"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+      - lowrisc:cve2:cve2_pkg
+    files:
+      - rtl/cve2_tracer_pkg.sv
+      - rtl/cve2_tracer.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/lint/verilator_waiver.vlt b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/lint/verilator_waiver.vlt
index b7c952ca..bac40c20 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/lint/verilator_waiver.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/lint/verilator_waiver.vlt
@@ -12,7 +12,7 @@
 `verilator_config
 lint_off -rule PINCONNECTEMPTY
 
-// We have some boolean top-level parameters in e.g. ibex_core_tracing.sv.
+// We have some boolean top-level parameters in e.g. cve2_core_tracing.sv.
 // When building with fusesoc, these get set with defines like
 // -GRV32M=1 (rather than -GRV32M=1'b1), leading to warnings like:
 //
@@ -23,13 +23,13 @@ lint_off -rule PINCONNECTEMPTY
 // matches when you set a 1-bit value to a literal 1, so it won't hide
 // silly mistakes like setting it to 2.
 //
-lint_off -rule WIDTH -file "*/rtl/ibex_top_tracing.sv"
+lint_off -rule WIDTH -file "*/rtl/cve2_top_tracing.sv"
          -match "*expects 1 bits*Initial value's CONST '32'h1'*"
 
 // Operator expects 1 bit on initial value but initial value's CONST generates
 // 32 bits, need a specific RV32B waiver as it uses enums so the above catch-all
 // waiver doesn't work.
-lint_off -rule WIDTH -file "*/rtl/ibex_top_tracing.sv" -match "*'RV32B'*"
+lint_off -rule WIDTH -file "*/rtl/cve2_top_tracing.sv" -match "*'RV32B'*"
 
 // Bits of signal are not used: be_i[3:1]
 // Bits of signal are not used: addr_i[31:10,1:0]
@@ -52,21 +52,25 @@ lint_off -rule UNUSED -file "*/rtl/timer.sv" -match "*'timer_addr_i'[31:10]*"
 
 // Signal is not used: clk_i
 // leaving clk and reset connected in-case we want to add assertions
-lint_off -rule UNUSED -file "*/rtl/ibex_pmp.sv" -match "*clk_i*"
-lint_off -rule UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -match "*clk_i*"
-lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*clk_i*"
-lint_off -rule UNUSED -file "*/rtl/ibex_branch_predict.sv" -match "*clk_i*"
+lint_off -rule UNUSED -file "*/rtl/cve2_pmp.sv" -match "*clk_i*"
+lint_off -rule UNUSED -file "*/rtl/cve2_compressed_decoder.sv" -match "*clk_i*"
+lint_off -rule UNUSED -file "*/rtl/cve2_decoder.sv" -match "*clk_i*"
+lint_off -rule UNUSED -file "*/rtl/cve2_branch_predict.sv" -match "*clk_i*"
 
 // Signal is not used: rst_ni
 // leaving clk and reset connected in-case we want to add assertions
-lint_off -rule UNUSED -file "*/rtl/ibex_pmp.sv" -match "*rst_ni*"
-lint_off -rule UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -match "*rst_ni*"
-lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*rst_ni*"
-lint_off -rule UNUSED -file "*/rtl/ibex_branch_predict.sv" -match "*rst_ni*"
+lint_off -rule UNUSED -file "*/rtl/cve2_pmp.sv" -match "*rst_ni*"
+lint_off -rule UNUSED -file "*/rtl/cve2_compressed_decoder.sv" -match "*rst_ni*"
+lint_off -rule UNUSED -file "*/rtl/cve2_decoder.sv" -match "*rst_ni*"
+lint_off -rule UNUSED -file "*/rtl/cve2_branch_predict.sv" -match "*rst_ni*"
 
 // Temporary waivers until OpenTitan primitives are lint-clean
 // https://github.com/lowRISC/opentitan/issues/2313
 lint_off -file "*/lowrisc_prim_*/rtl/*.sv"
 
-lint_off -rule UNUSED -file "*/rtl/ibex_top_tracing.sv" -match "*RndCnstLfsrSeed*"
-lint_off -rule UNUSED -file "*/rtl/ibex_top_tracing.sv" -match "*RndCnstLfsrPerm*"
+lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrSeed*"
+lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrPerm*"
+lint_off -rule DECLFILENAME -file "*/bhv/cve2_sim_clock_gate.sv" -match "Filename 'cve2_sim_clock_gate' does not match MODULE name: 'cve2_clock_gate'"
+lint_off -rule UNOPTFLAT -file "*/rtl/cve2_core.sv" -match "Signal unoptimizable: Feedback to clock or circular logic: 'cve2_top.u_cve2_core.irqs'"
+lint_off -rule UNUSED -file "*/rtl/cve2_wb.sv" -match "Signal is not used: 'clk_i'*"
+lint_off -rule UNUSED -file "*/rtl/cve2_wb.sv" -match "Signal is not used: 'rst_ni'*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_alu.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_alu.sv
similarity index 99%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_alu.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_alu.sv
index eb6afcae..2471c621 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_alu.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_alu.sv
@@ -6,10 +6,10 @@
 /**
  * Arithmetic logic unit
  */
-module ibex_alu #(
-  parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
+module cve2_alu #(
+  parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
 ) (
-  input  ibex_pkg::alu_op_e operator_i,
+  input  cve2_pkg::alu_op_e operator_i,
   input  logic [31:0]       operand_a_i,
   input  logic [31:0]       operand_b_i,
 
@@ -31,7 +31,7 @@ module ibex_alu #(
   output logic              comparison_result_o,
   output logic              is_equal_result_o
 );
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   logic [31:0] operand_a_rev;
   logic [32:0] operand_b_neg;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_branch_predict.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_branch_predict.sv
similarity index 98%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_branch_predict.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_branch_predict.sv
index 87f83836..e49c7007 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_branch_predict.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_branch_predict.sv
@@ -17,7 +17,7 @@
 
 `include "prim_assert.sv"
 
-module ibex_branch_predict (
+module cve2_branch_predict (
   input  logic clk_i,
   input  logic rst_ni,
 
@@ -30,7 +30,7 @@ module ibex_branch_predict (
   output logic        predict_branch_taken_o,
   output logic [31:0] predict_branch_pc_o
 );
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   logic [31:0] imm_j_type;
   logic [31:0] imm_b_type;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_compressed_decoder.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_compressed_decoder.sv
similarity index 99%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_compressed_decoder.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_compressed_decoder.sv
index e3c6aa52..1b5b17ff 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_compressed_decoder.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_compressed_decoder.sv
@@ -13,7 +13,7 @@
 
 `include "prim_assert.sv"
 
-module ibex_compressed_decoder (
+module cve2_compressed_decoder (
   input  logic        clk_i,
   input  logic        rst_ni,
   input  logic        valid_i,
@@ -22,7 +22,7 @@ module ibex_compressed_decoder (
   output logic        is_compressed_o,
   output logic        illegal_instr_o
 );
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   // valid_i indicates if instr_i is valid and is used for assertions only.
   // The following signal is used to avoid possible lint errors.
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_controller.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_controller.sv
similarity index 82%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_controller.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_controller.sv
index 0f2ae7bc..fba4352f 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_controller.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_controller.sv
@@ -8,15 +8,14 @@
  */
 
 `include "prim_assert.sv"
-//`include "dv_fcov_macros.svh"
+`include "dv_fcov_macros.svh"
 
-module ibex_controller #(
-  parameter bit WritebackStage  = 0,
-  parameter bit BranchPredictor = 0
+module cve2_controller #(
  ) (
   input  logic                  clk_i,
   input  logic                  rst_ni,
 
+  input  logic                  fetch_enable_i,          // core can fetch instructions leave RESET state
   output logic                  ctrl_busy_o,             // core is busy processing instrs
 
   // decoder related signals
@@ -33,7 +32,6 @@ module ibex_controller #(
   input  logic [31:0]           instr_i,                 // uncompressed instr data for mtval
   input  logic [15:0]           instr_compressed_i,      // instr compressed data for mtval
   input  logic                  instr_is_compressed_i,   // instr is compressed
-  input  logic                  instr_bp_taken_i,        // instr was predicted taken branch
   input  logic                  instr_fetch_err_i,       // instr has error
   input  logic                  instr_fetch_err_plus2_i, // instr error is x32
   input  logic [31:0]           pc_id_i,                 // instr address
@@ -47,37 +45,32 @@ module ibex_controller #(
   // to prefetcher
   output logic                  instr_req_o,             // start fetching instructions
   output logic                  pc_set_o,                // jump to address set by pc_mux
-  output ibex_pkg::pc_sel_e     pc_mux_o,                // IF stage fetch address selector
+  output cve2_pkg::pc_sel_e     pc_mux_o,                // IF stage fetch address selector
                                                          // (boot, normal, exception...)
-  output logic                  nt_branch_mispredict_o,  // Not-taken branch in ID/EX was
-                                                         // mispredicted (predicted taken)
-  output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,            // IF stage selector for exception PC
-  output ibex_pkg::exc_cause_e  exc_cause_o,             // for IF stage, CSRs
+  output cve2_pkg::exc_pc_sel_e exc_pc_mux_o,            // IF stage selector for exception PC
+  output cve2_pkg::exc_cause_e  exc_cause_o,             // for IF stage, CSRs
 
   // LSU
   input  logic [31:0]           lsu_addr_last_i,         // for mtval
   input  logic                  load_err_i,
   input  logic                  store_err_i,
-  output logic                  wb_exception_o,          // Instruction in WB taking an exception
-  output logic                  id_exception_o,          // Instruction in ID taking an exception
 
   // jump/branch signals
   input  logic                  branch_set_i,            // branch set signal (branch definitely
                                                          // taken)
-  input  logic                  branch_not_set_i,        // branch is definitely not taken
   input  logic                  jump_set_i,              // jump taken set signal
 
   // interrupt signals
   input  logic                  csr_mstatus_mie_i,       // M-mode interrupt enable bit
   input  logic                  irq_pending_i,           // interrupt request pending
-  input  ibex_pkg::irqs_t       irqs_i,                  // interrupt requests qualified with
+  input  cve2_pkg::irqs_t       irqs_i,                  // interrupt requests qualified with
                                                          // mie CSR
   input  logic                  irq_nm_i,                // non-maskeable interrupt
   output logic                  nmi_mode_o,              // core executing NMI handler
 
   // debug signals
   input  logic                  debug_req_i,
-  output ibex_pkg::dbg_cause_e  debug_cause_o,
+  output cve2_pkg::dbg_cause_e  debug_cause_o,
   output logic                  debug_csr_save_o,
   output logic                  debug_mode_o,
   input  logic                  debug_single_step_i,
@@ -85,24 +78,18 @@ module ibex_controller #(
   input  logic                  debug_ebreaku_i,
   input  logic                  trigger_match_i,
 
-  // Wakeup Signal
-  output logic                  wake_from_sleep_o,
-
   output logic                  csr_save_if_o,
   output logic                  csr_save_id_o,
-  output logic                  csr_save_wb_o,
   output logic                  csr_restore_mret_id_o,
   output logic                  csr_restore_dret_id_o,
   output logic                  csr_save_cause_o,
   output logic [31:0]           csr_mtval_o,
-  input  ibex_pkg::priv_lvl_e   priv_mode_i,
+  input  cve2_pkg::priv_lvl_e   priv_mode_i,
   input  logic                  csr_mstatus_tw_i,
 
   // stall & flush signals
   input  logic                  stall_id_i,
-  input  logic                  stall_wb_i,
   output logic                  flush_id_o,
-  input  logic                  ready_wb_i,
 
   // performance monitors
   output logic                  perf_jump_o,             // we are executing a jump
@@ -110,7 +97,7 @@ module ibex_controller #(
   output logic                  perf_tbranch_o           // we are executing a taken branch
                                                          // instruction
 );
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   // FSM state encoding
   typedef enum logic [3:0] {
@@ -153,8 +140,6 @@ module ibex_controller #(
   logic enter_debug_mode;
   logic ebreak_into_debug;
   logic handle_irq;
-  logic id_wb_pending;
-
   logic [3:0] mfip_id;
   logic       unused_irq_timer;
 
@@ -173,8 +158,8 @@ module ibex_controller #(
   always_ff @(negedge clk_i) begin
     // print warning in case of decoding errors
     if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin
-      $display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, ibex_core.hart_id_i,
-               ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);
+     $display("%m @ %t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, cve2_core.hart_id_i,
+               cve2_id_stage.pc_id_i, cve2_id_stage.instr_rdata_i);
     end
   end
   // synopsys translate_on
@@ -206,7 +191,7 @@ module ibex_controller #(
                          (mret_insn | (csr_mstatus_tw_i & wfi_insn));
 
   // This is recorded in the illegal_insn_q flop to help timing.  Specifically
-  // it is needed to break the path from ibex_cs_registers/illegal_csr_insn_o
+  // it is needed to break the path from cve2_cs_registers/illegal_csr_insn_o
   // to pc_set_o.  Clear when controller is in FLUSH so it won't remain set
   // once illegal instruction is handled.
   // All terms in this expression are qualified by instr_valid_i
@@ -223,8 +208,6 @@ module ibex_controller #(
   // LSU exception requests
   assign exc_req_lsu = store_err_i | load_err_i;
 
-  assign id_exception_o = exc_req_d;
-
   // special requests: special instructions, pipeline flushes, exceptions...
   // All terms in these expressions are qualified by instr_valid_i except exc_req_lsu which can come
   // from the Writeback stage with no instr_valid_i from the ID stage
@@ -239,40 +222,7 @@ module ibex_controller #(
   // generic special request signal, applies to all instructions
   assign special_req = special_req_pc_change | special_req_flush_only;
 
-  // Is there an instruction in ID or WB that has yet to complete?
-  assign id_wb_pending = instr_valid_i | ~ready_wb_i;
-
   // Exception/fault prioritisation is taken from Table 3.7 of Priviledged Spec v1.11
-  if (WritebackStage) begin : g_wb_exceptions
-    always_comb begin
-      instr_fetch_err_prio = 0;
-      illegal_insn_prio    = 0;
-      ecall_insn_prio      = 0;
-      ebrk_insn_prio       = 0;
-      store_err_prio       = 0;
-      load_err_prio        = 0;
-
-      // Note that with the writeback stage store/load errors occur on the instruction in writeback,
-      // all other exception/faults occur on the instruction in ID/EX. The faults from writeback
-      // must take priority as that instruction is architecurally ordered before the one in ID/EX.
-      if (store_err_q) begin
-        store_err_prio = 1'b1;
-      end else if (load_err_q) begin
-        load_err_prio  = 1'b1;
-      end else if (instr_fetch_err) begin
-        instr_fetch_err_prio = 1'b1;
-      end else if (illegal_insn_q) begin
-        illegal_insn_prio = 1'b1;
-      end else if (ecall_insn) begin
-        ecall_insn_prio = 1'b1;
-      end else if (ebrk_insn) begin
-        ebrk_insn_prio = 1'b1;
-      end
-    end
-
-    // Instruction in writeback is generating an exception so instruction in ID must not execute
-    assign wb_exception_o = load_err_q | store_err_q | load_err_i | store_err_i;
-  end else begin : g_no_wb_exceptions
     always_comb begin
       instr_fetch_err_prio = 0;
       illegal_insn_prio    = 0;
@@ -295,8 +245,6 @@ module ibex_controller #(
         load_err_prio  = 1'b1;
       end
     end
-    assign wb_exception_o = 1'b0;
-  end
 
   `ASSERT_IF(IbexExceptionPrioOnehot,
              $onehot({instr_fetch_err_prio,
@@ -346,6 +294,7 @@ module ibex_controller #(
   // - while in debug mode [Debug Spec v0.13.2, p.39],
   // - while in NMI mode (nested NMIs are not supported, NMI has highest priority and
   //   cannot be interrupted by regular interrupts).
+  // - while single stepping.
   assign handle_irq = ~debug_mode_q & ~nmi_mode_q &
       (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i));
 
@@ -353,7 +302,7 @@ module ibex_controller #(
   always_comb begin : gen_mfip_id
     mfip_id = 4'd0;
 
-    for (int i = 14; i >= 0; i--) begin
+    for (int i = 15; i >= 0; i--) begin
       if (irqs_i.irq_fast[i]) begin
         mfip_id = i[3:0];
       end
@@ -372,7 +321,6 @@ module ibex_controller #(
 
     csr_save_if_o         = 1'b0;
     csr_save_id_o         = 1'b0;
-    csr_save_wb_o         = 1'b0;
     csr_restore_mret_id_o = 1'b0;
     csr_restore_dret_id_o = 1'b0;
     csr_save_cause_o      = 1'b0;
@@ -384,7 +332,6 @@ module ibex_controller #(
     // helping timing.
     pc_mux_o               = PC_BOOT;
     pc_set_o               = 1'b0;
-    nt_branch_mispredict_o = 1'b0;
 
     exc_pc_mux_o           = EXC_PC_IRQ;
     exc_cause_o            = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
@@ -412,9 +359,11 @@ module ibex_controller #(
         instr_req_o   = 1'b0;
         pc_mux_o      = PC_BOOT;
         pc_set_o      = 1'b1;
-        ctrl_fsm_ns   = BOOT_SET;
+        if (fetch_enable_i == 1'b1)
+        begin
+          ctrl_fsm_ns = BOOT_SET;
+        end
       end
-
       BOOT_SET: begin
         // copy boot address to instr fetch address
         instr_req_o   = 1'b1;
@@ -441,13 +390,12 @@ module ibex_controller #(
 
         // normal execution flow
         // in debug mode or single step mode we leave immediately (wfi=nop)
-        if (wake_from_sleep_o) begin
-          ctrl_fsm_ns  = FIRST_FETCH;
+        if (irq_nm_i || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i) begin
+          ctrl_fsm_ns = FIRST_FETCH;
         end else begin
           // Make sure clock remains disabled.
           ctrl_busy_o = 1'b0;
         end
-
       end
 
       FIRST_FETCH: begin
@@ -497,40 +445,25 @@ module ibex_controller #(
           // FLUSH state.
           retain_id = 1'b1;
 
-          // Wait for the writeback stage to either be ready for a new instruction or raise its own
-          // exception before going to FLUSH. If the instruction in writeback raises an exception it
-          // must take priority over any exception from an instruction in ID/EX. Only once the
-          // writeback stage is ready can we be certain that won't happen. Without a writeback
-          // stage ready_wb_i == 1 so the FSM will always go directly to FLUSH.
+          // The FSM will always go directly to FLUSH.
 
-          if (ready_wb_i | wb_exception_o) begin
-            ctrl_fsm_ns = FLUSH;
-          end
+          ctrl_fsm_ns = FLUSH;
         end
 
         if (branch_set_i || jump_set_i) begin
-          // Only set the PC if the branch predictor hasn't already done the branch for us
-          pc_set_o       = BranchPredictor ? ~instr_bp_taken_i : 1'b1;
+          pc_set_o       = 1'b1;
 
           perf_tbranch_o = branch_set_i;
           perf_jump_o    = jump_set_i;
         end
 
-        if (BranchPredictor) begin
-          if (instr_bp_taken_i & branch_not_set_i) begin
-            // If the instruction is a branch that was predicted to be taken but was not taken
-            // signal a mispredict.
-            nt_branch_mispredict_o = 1'b1;
-          end
-        end
-
         // If entering debug mode or handling an IRQ the core needs to wait until any instruction in
-        // ID or WB has finished executing. Stall IF during that time.
-        if ((enter_debug_mode || handle_irq) && (stall || id_wb_pending)) begin
+        // ID has finished executing. Stall IF during that time.
+        if ((enter_debug_mode || handle_irq) && (stall || instr_valid_i)) begin
           halt_if = 1'b1;
         end
 
-        if (!stall && !special_req && !id_wb_pending) begin
+        if (!stall && !special_req && !instr_valid_i) begin
           if (enter_debug_mode) begin
             // enter debug mode
             ctrl_fsm_ns = DBG_TAKEN_IF;
@@ -565,12 +498,13 @@ module ibex_controller #(
           if (irq_nm_i && !nmi_mode_q) begin
             exc_cause_o = EXC_CAUSE_IRQ_NM;
             nmi_mode_d  = 1'b1; // enter NMI mode
-          end else if (irqs_i.irq_fast != 15'b0) begin
+          end else if (irqs_i.irq_fast != 16'b0) begin
             // generate exception cause ID from fast interrupt ID:
             // - first bit distinguishes interrupts from exceptions,
-            // - second bit adds 16 to fast interrupt ID
-            // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}
-            exc_cause_o = exc_cause_e'({2'b11, mfip_id});
+            // - third bit adds 16 to fast interrupt ID so that the interrup 0 becomes 16 and the interrupt 15 becomes 31 (hence 5bits)
+            // - second bit is always 0 as the FAST interrupts are represented in the first 5bits, the 6th is always 0 cause is used by the NMI (in that case is 1 as represented by the number 32)
+            // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 6'd16}
+            exc_cause_o = exc_cause_e'({3'b101, mfip_id});
           end else if (irqs_i.irq_external) begin
             exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M;
           end else if (irqs_i.irq_software) begin
@@ -597,11 +531,11 @@ module ibex_controller #(
 
         csr_save_cause_o = 1'b1;
         if (trigger_match_i) begin
-          debug_cause_o = DBG_CAUSE_TRIGGER;
-        end else if (debug_single_step_i) begin
-          debug_cause_o = DBG_CAUSE_STEP;
+          debug_cause_o = DBG_CAUSE_TRIGGER;     // (priority 4)
+        end else if (debug_req_i) begin
+          debug_cause_o = DBG_CAUSE_HALTREQ;     // (priority 1)
         end else begin
-          debug_cause_o = DBG_CAUSE_HALTREQ;
+          debug_cause_o = DBG_CAUSE_STEP;        // (priority 0, lowest)
         end
 
         // enter debug mode
@@ -657,13 +591,7 @@ module ibex_controller #(
           pc_mux_o         = PC_EXC;
           exc_pc_mux_o     = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC;
 
-          if (WritebackStage) begin : g_writeback_mepc_save
-            // With the writeback stage present whether an instruction accessing memory will cause
-            // an exception is only known when it is in writeback. So when taking such an exception
-            // epc must come from writeback.
-            csr_save_id_o  = ~(store_err_q | load_err_q);
-            csr_save_wb_o  = store_err_q | load_err_q;
-          end else begin : g_no_writeback_mepc_save
+          begin : g_no_writeback_mepc_save
             csr_save_id_o  = 1'b0;
           end
 
@@ -742,9 +670,6 @@ module ibex_controller #(
             csr_restore_dret_id_o = 1'b1;
           end else if (wfi_insn) begin
             ctrl_fsm_ns           = WAIT_SLEEP;
-          end else if (csr_pipe_flush && handle_irq) begin
-            // start handling IRQs when doing CSR-related pipeline flushes
-            ctrl_fsm_ns           = IRQ_TAKEN;
           end
         end // exc_req_q
 
@@ -754,9 +679,14 @@ module ibex_controller #(
         // Leave all other signals as is to ensure CSRs and PC get set as if
         // core was entering exception handler, entry to debug mode will then
         // see the appropriate state and setup dpc correctly.
+
         // If an EBREAK instruction is causing us to enter debug mode on the
         // same cycle as a debug_req or single step, honor the EBREAK and
-        // proceed to DBG_TAKEN_ID.
+        // proceed to DBG_TAKEN_ID, as it has the highest priority.
+        // [Debug Spec v1.0.0-STABLE, p.53]
+        // cause==EBREAK    -> prio 3 (highest)
+        // cause==debug_req -> prio 2
+        // cause==step      -> prio 1 (lowest)
         if (enter_debug_mode_prio_q && !(ebrk_insn_prio && ebreak_into_debug)) begin
           ctrl_fsm_ns = DBG_TAKEN_IF;
         end
@@ -782,9 +712,8 @@ module ibex_controller #(
   ///////////////////
 
   // If high current instruction cannot complete this cycle. Either because it needs more cycles to
-  // finish (stall_id_i) or because the writeback stage cannot accept it yet (stall_wb_i). If there
-  // is no writeback stage stall_wb_i is a constant 0.
-  assign stall = stall_id_i | stall_wb_i;
+  // finish (stall_id_i)
+  assign stall = stall_id_i;
 
   // signal to IF stage that ID stage is ready for next instr
   assign id_in_ready_o = ~stall & ~halt_if & ~retain_id;
@@ -821,27 +750,22 @@ module ibex_controller #(
     end
   end
 
-  assign wake_from_sleep_o = irq_nm_i || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i;
-
-
   //////////
   // FCOV //
   //////////
 
-  //`DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
-  //`DV_FCOV_SIGNAL(logic, debug_entry_if,
-  //    (ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF))
-  //`DV_FCOV_SIGNAL(logic, debug_entry_id,
-  //    (ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID))
-  //`DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))
-  //`DV_FCOV_SIGNAL(logic, debug_req, debug_req_i & ~debug_mode_q)
+  `DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
+  `DV_FCOV_SIGNAL(logic, debug_entry_if,
+      (ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF))
+  `DV_FCOV_SIGNAL(logic, debug_entry_id,
+      (ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID))
+  `DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))
+  `DV_FCOV_SIGNAL(logic, debug_req, debug_req_i & ~debug_mode_q)
 
   ////////////////
   // Assertions //
   ////////////////
 
-  `ASSERT(AlwaysInstrClearOnMispredict, nt_branch_mispredict_o |-> instr_valid_clear_o)
-
   // Selectors must be known/valid.
   `ASSERT(IbexCtrlStateValid, ctrl_fsm_cs inside {
       RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,
@@ -923,7 +847,7 @@ module ibex_controller #(
 
   `ifdef RVFI
     // Workaround for internal verilator error when using hierarchical refers to calcuate this
-    // directly in ibex_core
+    // directly in cve2_core
     logic rvfi_flush_next;
 
     assign rvfi_flush_next = ctrl_fsm_ns == FLUSH;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.f b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.f
new file mode 100644
index 00000000..3250f707
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.f
@@ -0,0 +1,17 @@
+cve2_pkg.sv
+cve2_alu.sv
+cve2_compressed_decoder.sv
+cve2_controller.sv
+cve2_counter.sv
+cve2_cs_registers.sv
+cve2_decoder.sv
+cve2_ex_block.sv
+cve2_id_stage.sv
+cve2_if_stage.sv
+cve2_load_store_unit.sv
+cve2_multdiv_slow.sv
+cve2_multdiv_fast.sv
+cve2_prefetch_buffer.sv
+cve2_fetch_fifo.sv
+cve2_register_file_ff.sv
+cve2_core.sv
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_core.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.sv
similarity index 73%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_core.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.sv
index f57c87d9..4f79b67f 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_core.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.sv
@@ -12,7 +12,7 @@
 /**
  * Top level module of the ibex RISC-V core
  */
-module ibex_core import ibex_pkg::*; #(
+module cve2_core import cve2_pkg::*; #(
   parameter bit          PMPEnable         = 1'b0,
   parameter int unsigned PMPGranularity    = 0,
   parameter int unsigned PMPNumRegions     = 4,
@@ -21,23 +21,8 @@ module ibex_core import ibex_pkg::*; #(
   parameter bit          RV32E             = 1'b0,
   parameter rv32m_e      RV32M             = RV32MFast,
   parameter rv32b_e      RV32B             = RV32BNone,
-  parameter bit          BranchTargetALU   = 1'b0,
-  parameter bit          WritebackStage    = 1'b0,
-  parameter bit          ICache            = 1'b0,
-  parameter bit          ICacheECC         = 1'b0,
-  parameter int unsigned BusSizeECC        = BUS_SIZE,
-  parameter int unsigned TagSizeECC        = IC_TAG_SIZE,
-  parameter int unsigned LineSizeECC       = IC_LINE_SIZE,
-  parameter bit          BranchPredictor   = 1'b0,
   parameter bit          DbgTriggerEn      = 1'b0,
   parameter int unsigned DbgHwBreakNum     = 1,
-  parameter bit          ResetAll          = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed   = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm   = RndCnstLfsrPermDefault,
-  parameter bit          SecureIbex        = 1'b0,
-  parameter bit          DummyInstructions = 1'b0,
-  parameter bit          RegFileECC        = 1'b0,
-  parameter int unsigned RegFileDataWidth  = 32,
   parameter int unsigned DmHaltAddr        = 32'h1A110800,
   parameter int unsigned DmExceptionAddr   = 32'h1A110808
 ) (
@@ -45,6 +30,8 @@ module ibex_core import ibex_pkg::*; #(
   input  logic                         clk_i,
   input  logic                         rst_ni,
 
+  input  logic                         test_en_i,
+
   input  logic [31:0]                  hart_id_i,
   input  logic [31:0]                  boot_addr_i,
 
@@ -67,34 +54,11 @@ module ibex_core import ibex_pkg::*; #(
   input  logic [31:0]                  data_rdata_i,
   input  logic                         data_err_i,
 
-  // Register file interface
-  output logic                         dummy_instr_id_o,
-  output logic [4:0]                   rf_raddr_a_o,
-  output logic [4:0]                   rf_raddr_b_o,
-  output logic [4:0]                   rf_waddr_wb_o,
-  output logic                         rf_we_wb_o,
-  output logic [RegFileDataWidth-1:0]  rf_wdata_wb_ecc_o,
-  input  logic [RegFileDataWidth-1:0]  rf_rdata_a_ecc_i,
-  input  logic [RegFileDataWidth-1:0]  rf_rdata_b_ecc_i,
-
-  // RAMs interface
-  output logic [IC_NUM_WAYS-1:0]       ic_tag_req_o,
-  output logic                         ic_tag_write_o,
-  output logic [IC_INDEX_W-1:0]        ic_tag_addr_o,
-  output logic [TagSizeECC-1:0]        ic_tag_wdata_o,
-  input  logic [TagSizeECC-1:0]        ic_tag_rdata_i [IC_NUM_WAYS],
-  output logic [IC_NUM_WAYS-1:0]       ic_data_req_o,
-  output logic                         ic_data_write_o,
-  output logic [IC_INDEX_W-1:0]        ic_data_addr_o,
-  output logic [LineSizeECC-1:0]       ic_data_wdata_o,
-  input  logic [LineSizeECC-1:0]       ic_data_rdata_i [IC_NUM_WAYS],
-  input  logic                         ic_scr_key_valid_i,
-
   // Interrupt inputs
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
   input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
+  input  logic [15:0]                  irq_fast_i,
   input  logic                         irq_nm_i,       // non-maskeable interrupt
   output logic                         irq_pending_o,
 
@@ -103,7 +67,6 @@ module ibex_core import ibex_pkg::*; #(
   output crash_dump_t                  crash_dump_o,
   // SEC_CM: EXCEPTION.CTRL_FLOW.LOCAL_ESC
   // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC
-  output logic                         double_fault_seen_o,
 
   // RISC-V Formal Interface
   // Does not comply with the coding standards of _i/_o suffixes, but follows
@@ -139,22 +102,14 @@ module ibex_core import ibex_pkg::*; #(
 `endif
 
   // CPU Control Signals
-  // SEC_CM: FETCH.CTRL.LC_GATED
   input  logic                         fetch_enable_i,
-  output logic                         alert_minor_o,
-  output logic                         alert_major_o,
-  output logic                         icache_inval_o,
-  output logic                         core_sleep_o
+  output logic                         core_busy_o
 );
 
   localparam int unsigned PMP_NUM_CHAN      = 3;
   // SEC_CM: CORE.DATA_REG_SW.SCA
-  localparam bit          DataIndTiming     = SecureIbex;
-  localparam bit          PCIncrCheck       = SecureIbex;
-  localparam bit          ShadowCSR         = 1'b0;
 
   // IF/ID signals
-  logic        dummy_instr_id;
   logic        instr_valid_id;
   logic        instr_new_id;
   logic [31:0] instr_rdata_id;                 // Instruction sampled inside IF stage
@@ -163,33 +118,18 @@ module ibex_core import ibex_pkg::*; #(
   logic [15:0] instr_rdata_c_id;               // Compressed instruction sampled inside IF stage
   logic        instr_is_compressed_id;
   logic        instr_perf_count_id;
-  logic        instr_bp_taken_id;
   logic        instr_fetch_err;                // Bus error on instr fetch
   logic        instr_fetch_err_plus2;          // Instruction error is misaligned
   logic        illegal_c_insn_id;              // Illegal compressed instruction sent to ID stage
   logic [31:0] pc_if;                          // Program counter in IF stage
   logic [31:0] pc_id;                          // Program counter in ID stage
-  logic [31:0] pc_wb;                          // Program counter in WB stage
   logic [33:0] imd_val_d_ex[2];                // Intermediate register for multicycle Ops
   logic [33:0] imd_val_q_ex[2];                // Intermediate register for multicycle Ops
   logic [1:0]  imd_val_we_ex;
 
-  logic        data_ind_timing;
-  logic        dummy_instr_en;
-  logic [2:0]  dummy_instr_mask;
-  logic        dummy_instr_seed_en;
-  logic [31:0] dummy_instr_seed;
-  logic        icache_enable;
-  logic        icache_inval;
-  logic        icache_ecc_error;
-  logic        pc_mismatch_alert;
-  logic        csr_shadow_err;
-
   logic        instr_first_cycle_id;
   logic        instr_valid_clear;
   logic        pc_set;
-  logic        nt_branch_mispredict;
-  logic [31:0] nt_branch_addr;
   pc_sel_e     pc_mux_id;                      // Mux selector for next PC
   exc_pc_sel_e exc_pc_mux_id;                  // Mux selector for exception PC
   exc_cause_e  exc_cause;                      // Exception cause
@@ -221,26 +161,19 @@ module ibex_core import ibex_pkg::*; #(
   logic [31:0] rf_wdata_wb;
   // Writeback register write data that can be used on the forwarding path (doesn't factor in memory
   // read data as this is too late for the forwarding path)
-  logic [31:0] rf_wdata_fwd_wb;
   logic [31:0] rf_wdata_lsu;
   logic        rf_we_wb;
   logic        rf_we_lsu;
-  logic        rf_ecc_err_comb;
 
   logic [4:0]  rf_waddr_id;
   logic [31:0] rf_wdata_id;
   logic        rf_we_id;
-  logic        rf_rd_a_wb_match;
-  logic        rf_rd_b_wb_match;
 
   // ALU Control
   alu_op_e     alu_operator_ex;
   logic [31:0] alu_operand_a_ex;
   logic [31:0] alu_operand_b_ex;
 
-  logic [31:0] bt_a_operand;
-  logic [31:0] bt_b_operand;
-
   logic [31:0] alu_adder_result_ex;    // Used to forward computed address to LSU
   logic [31:0] result_ex;
 
@@ -253,7 +186,6 @@ module ibex_core import ibex_pkg::*; #(
   logic [1:0]  multdiv_signed_mode_ex;
   logic [31:0] multdiv_operand_a_ex;
   logic [31:0] multdiv_operand_b_ex;
-  logic        multdiv_ready_id;
 
   // CSR control
   logic        csr_access;
@@ -272,7 +204,6 @@ module ibex_core import ibex_pkg::*; #(
   logic        lsu_sign_ext;
   logic        lsu_req;
   logic [31:0] lsu_wdata;
-  logic        lsu_req_done;
 
   // stall control
   logic        id_in_ready;
@@ -285,13 +216,8 @@ module ibex_core import ibex_pkg::*; #(
   logic        instr_req_int;          // Id stage asserts a req to instruction core interface
   logic        instr_req_gated;
 
-  // Writeback stage
-  logic           en_wb;
-  wb_instr_type_e instr_type_wb;
-  logic           ready_wb;
-  logic           rf_write_wb;
-  logic           outstanding_load_wb;
-  logic           outstanding_store_wb;
+  // Writeback
+  logic        en_wb;
 
   // Interrupts
   logic        nmi_mode;
@@ -308,7 +234,6 @@ module ibex_core import ibex_pkg::*; #(
 
   logic        csr_save_if;
   logic        csr_save_id;
-  logic        csr_save_wb;
   logic        csr_restore_mret_id;
   logic        csr_restore_dret_id;
   logic        csr_save_cause;
@@ -331,15 +256,12 @@ module ibex_core import ibex_pkg::*; #(
   // signals relating to instruction movements between pipeline stages
   // used by performance counters and RVFI
   logic        instr_id_done;
-  logic        instr_done_wb;
 
   logic        perf_instr_ret_wb;
   logic        perf_instr_ret_compressed_wb;
-  logic        perf_instr_ret_wb_spec;
-  logic        perf_instr_ret_compressed_wb_spec;
   logic        perf_iside_wait;
   logic        perf_dside_wait;
-  logic        perf_mul_wait;
+  logic        perf_wfi_wait;
   logic        perf_div_wait;
   logic        perf_jump;
   logic        perf_branch;
@@ -350,63 +272,23 @@ module ibex_core import ibex_pkg::*; #(
   // for RVFI
   logic        illegal_insn_id, unused_illegal_insn_id; // ID stage sees an illegal instruction
 
-  //////////////////////////////////////////////////////////////////////////////////////////////
-  //   ____ _            _      __  __                                                   _    //
-  //  / ___| | ___   ___| | __ |  \/  | __ _ _ __   __ _  __ _  ___ _ __ ___   ___ _ __ | |_  //
-  // | |   | |/ _ \ / __| |/ / | |\/| |/ _` | '_ \ / _` |/ _` |/ _ \ '_ ` _ \ / _ \ '_ \| __| //
-  // | |___| | (_) | (__|   <  | |  | | (_| | | | | (_| | (_| |  __/ | | | | |  __/ | | | |_  //
-  //  \____|_|\___/ \___|_|\_\ |_|  |_|\__,_|_| |_|\__,_|\__, |\___|_| |_| |_|\___|_| |_|\__| //
-  //                                                     |___/                                //
-  //////////////////////////////////////////////////////////////////////////////////////////////
-
-  logic clk;
-  logic fetch_enable;
-  logic wake_from_sleep;
-
-  cve2_sleep_unit sleep_unit_i (
-      // Clock, reset interface
-      .clk_ungated_i(clk_i),  // Ungated clock
-      .rst_n        (rst_ni),
-      .clk_gated_o  (clk),  // Gated clock
-      .scan_cg_en_i (1'b0),
-
-      // Core sleep
-      .core_sleep_o(core_sleep_o),
-
-      // Fetch enable
-      .fetch_enable_i(fetch_enable_i),
-      .fetch_enable_o(fetch_enable),
-
-      // Core status
-      .if_busy_i  (if_busy),
-      .ctrl_busy_i(ctrl_busy),
-      .lsu_busy_i (lsu_busy),
-
-      // WFI wake
-      .wake_from_sleep_i(wake_from_sleep)
-  );
+  //////////////////////
+  // Clock management //
+  //////////////////////
 
+  // Before going to sleep, wait for I- and D-side
+  // interfaces to finish ongoing operations.
+  assign core_busy_o = ctrl_busy | if_busy | lsu_busy;
 
   //////////////
   // IF stage //
   //////////////
 
-  ibex_if_stage #(
+  cve2_if_stage #(
     .DmHaltAddr       (DmHaltAddr),
-    .DmExceptionAddr  (DmExceptionAddr),
-    .DummyInstructions(DummyInstructions),
-    .ICache           (ICache),
-    .ICacheECC        (ICacheECC),
-    .BusSizeECC       (BusSizeECC),
-    .TagSizeECC       (TagSizeECC),
-    .LineSizeECC      (LineSizeECC),
-    .PCIncrCheck      (PCIncrCheck),
-    .ResetAll          ( ResetAll          ),
-    .RndCnstLfsrSeed   ( RndCnstLfsrSeed   ),
-    .RndCnstLfsrPerm   ( RndCnstLfsrPerm   ),
-    .BranchPredictor  (BranchPredictor)
+    .DmExceptionAddr  (DmExceptionAddr)
   ) if_stage_i (
-    .clk_i (clk),
+    .clk_i (clk_i),
     .rst_ni(rst_ni),
 
     .boot_addr_i(boot_addr_i),
@@ -420,18 +302,6 @@ module ibex_core import ibex_pkg::*; #(
     .instr_rdata_i  (instr_rdata_i),
     .instr_err_i    (instr_err_i),
 
-    .ic_tag_req_o      (ic_tag_req_o),
-    .ic_tag_write_o    (ic_tag_write_o),
-    .ic_tag_addr_o     (ic_tag_addr_o),
-    .ic_tag_wdata_o    (ic_tag_wdata_o),
-    .ic_tag_rdata_i    (ic_tag_rdata_i),
-    .ic_data_req_o     (ic_data_req_o),
-    .ic_data_write_o   (ic_data_write_o),
-    .ic_data_addr_o    (ic_data_addr_o),
-    .ic_data_wdata_o   (ic_data_wdata_o),
-    .ic_data_rdata_i   (ic_data_rdata_i),
-    .ic_scr_key_valid_i(ic_scr_key_valid_i),
-
     // outputs to ID stage
     .instr_valid_id_o        (instr_valid_id),
     .instr_new_id_o          (instr_new_id),
@@ -439,11 +309,9 @@ module ibex_core import ibex_pkg::*; #(
     .instr_rdata_alu_id_o    (instr_rdata_alu_id),
     .instr_rdata_c_id_o      (instr_rdata_c_id),
     .instr_is_compressed_id_o(instr_is_compressed_id),
-    .instr_bp_taken_o        (instr_bp_taken_id),
     .instr_fetch_err_o       (instr_fetch_err),
     .instr_fetch_err_plus2_o (instr_fetch_err_plus2),
     .illegal_c_insn_id_o     (illegal_c_insn_id),
-    .dummy_instr_id_o        (dummy_instr_id),
     .pc_if_o                 (pc_if),
     .pc_id_o                 (pc_id),
     .pmp_err_if_i            (pmp_req_err[PMP_I]),
@@ -453,20 +321,11 @@ module ibex_core import ibex_pkg::*; #(
     .instr_valid_clear_i   (instr_valid_clear),
     .pc_set_i              (pc_set),
     .pc_mux_i              (pc_mux_id),
-    .nt_branch_mispredict_i(nt_branch_mispredict),
     .exc_pc_mux_i          (exc_pc_mux_id),
     .exc_cause             (exc_cause),
-    .dummy_instr_en_i      (dummy_instr_en),
-    .dummy_instr_mask_i    (dummy_instr_mask),
-    .dummy_instr_seed_en_i (dummy_instr_seed_en),
-    .dummy_instr_seed_i    (dummy_instr_seed),
-    .icache_enable_i       (icache_enable),
-    .icache_inval_i        (icache_inval),
-    .icache_ecc_error_o    (icache_ecc_error),
 
     // branch targets
     .branch_target_ex_i(branch_target_ex),
-    .nt_branch_addr_i  (nt_branch_addr),
 
     // CSRs
     .csr_mepc_i      (csr_mepc),  // exception return address
@@ -477,7 +336,6 @@ module ibex_core import ibex_pkg::*; #(
     // pipeline stalls
     .id_in_ready_i(id_in_ready),
 
-    .pc_mismatch_alert_o(pc_mismatch_alert),
     .if_busy_o          (if_busy)
   );
 
@@ -485,27 +343,23 @@ module ibex_core import ibex_pkg::*; #(
   // available
   assign perf_iside_wait = id_in_ready & ~instr_valid_id;
 
-  // fetch_enable_i can be used to stop the core fetching new instructions
-  assign instr_req_gated = instr_req_int & fetch_enable;
+  // For non secure Ibex only the bottom bit of fetch enable is considered
+  assign instr_req_gated = instr_req_int;
 
   //////////////
   // ID stage //
   //////////////
 
-  ibex_id_stage #(
+  cve2_id_stage #(
     .RV32E          (RV32E),
     .RV32M          (RV32M),
-    .RV32B          (RV32B),
-    .BranchTargetALU(BranchTargetALU),
-    .DataIndTiming  (DataIndTiming),
-    .WritebackStage (WritebackStage),
-    .BranchPredictor(BranchPredictor)
+    .RV32B          (RV32B)
   ) id_stage_i (
-
-    .clk_i(clk),
+    .clk_i (clk_i),
     .rst_ni(rst_ni),
 
     // Processor Enable
+    .fetch_enable_i(fetch_enable_i),
     .ctrl_busy_o   (ctrl_busy),
     .illegal_insn_o(illegal_insn_id),
 
@@ -515,7 +369,6 @@ module ibex_core import ibex_pkg::*; #(
     .instr_rdata_alu_i    (instr_rdata_alu_id),
     .instr_rdata_c_i      (instr_rdata_c_id),
     .instr_is_compressed_i(instr_is_compressed_id),
-    .instr_bp_taken_i     (instr_bp_taken_id),
 
     // Jumps and branches
     .branch_decision_i(branch_decision),
@@ -527,11 +380,8 @@ module ibex_core import ibex_pkg::*; #(
     .instr_req_o           (instr_req_int),
     .pc_set_o              (pc_set),
     .pc_mux_o              (pc_mux_id),
-    .nt_branch_mispredict_o(nt_branch_mispredict),
-    .nt_branch_addr_o      (nt_branch_addr),
     .exc_pc_mux_o          (exc_pc_mux_id),
     .exc_cause_o           (exc_cause),
-    .icache_inval_o        (icache_inval),
 
     .instr_fetch_err_i      (instr_fetch_err),
     .instr_fetch_err_plus2_i(instr_fetch_err_plus2),
@@ -551,9 +401,6 @@ module ibex_core import ibex_pkg::*; #(
     .imd_val_d_ex_i (imd_val_d_ex),
     .imd_val_we_ex_i(imd_val_we_ex),
 
-    .bt_a_operand_o(bt_a_operand),
-    .bt_b_operand_o(bt_b_operand),
-
     .mult_en_ex_o            (mult_en_ex),
     .div_en_ex_o             (div_en_ex),
     .mult_sel_ex_o           (mult_sel_ex),
@@ -562,7 +409,6 @@ module ibex_core import ibex_pkg::*; #(
     .multdiv_signed_mode_ex_o(multdiv_signed_mode_ex),
     .multdiv_operand_a_ex_o  (multdiv_operand_a_ex),
     .multdiv_operand_b_ex_o  (multdiv_operand_b_ex),
-    .multdiv_ready_id_o      (multdiv_ready_id),
 
     // CSR ID/EX
     .csr_access_o         (csr_access),
@@ -570,7 +416,6 @@ module ibex_core import ibex_pkg::*; #(
     .csr_op_en_o          (csr_op_en),
     .csr_save_if_o        (csr_save_if),  // control signal to save PC
     .csr_save_id_o        (csr_save_id),  // control signal to save PC
-    .csr_save_wb_o        (csr_save_wb),  // control signal to save PC
     .csr_restore_mret_id_o(csr_restore_mret_id),  // restore mstatus upon MRET
     .csr_restore_dret_id_o(csr_restore_dret_id),  // restore mstatus upon MRET
     .csr_save_cause_o     (csr_save_cause),
@@ -578,7 +423,6 @@ module ibex_core import ibex_pkg::*; #(
     .priv_mode_i          (priv_mode_id),
     .csr_mstatus_tw_i     (csr_mstatus_tw),
     .illegal_csr_insn_i   (illegal_csr_insn_id),
-    .data_ind_timing_i    (data_ind_timing),
 
     // LSU
     .lsu_req_o     (lsu_req),  // to load store unit
@@ -586,7 +430,6 @@ module ibex_core import ibex_pkg::*; #(
     .lsu_type_o    (lsu_type),  // to load store unit
     .lsu_sign_ext_o(lsu_sign_ext),  // to load store unit
     .lsu_wdata_o   (lsu_wdata),  // to load store unit
-    .lsu_req_done_i(lsu_req_done),  // from load store unit
 
     .lsu_addr_incr_req_i(lsu_addr_incr_req),
     .lsu_addr_last_i    (lsu_addr_last),
@@ -611,9 +454,6 @@ module ibex_core import ibex_pkg::*; #(
     .debug_ebreaku_i    (debug_ebreaku),
     .trigger_match_i    (trigger_match),
 
-    // Wakeup Signal
-    .wake_from_sleep_o(wake_from_sleep),
-
     // write data to commit in the register file
     .result_ex_i(result_ex),
     .csr_rdata_i(csr_rdata),
@@ -627,40 +467,28 @@ module ibex_core import ibex_pkg::*; #(
     .rf_waddr_id_o     (rf_waddr_id),
     .rf_wdata_id_o     (rf_wdata_id),
     .rf_we_id_o        (rf_we_id),
-    .rf_rd_a_wb_match_o(rf_rd_a_wb_match),
-    .rf_rd_b_wb_match_o(rf_rd_b_wb_match),
-
-    .rf_waddr_wb_i    (rf_waddr_wb),
-    .rf_wdata_fwd_wb_i(rf_wdata_fwd_wb),
-    .rf_write_wb_i    (rf_write_wb),
 
-    .en_wb_o               (en_wb),
-    .instr_type_wb_o       (instr_type_wb),
+    .en_wb_o           (en_wb),
     .instr_perf_count_id_o (instr_perf_count_id),
-    .ready_wb_i            (ready_wb),
-    .outstanding_load_wb_i (outstanding_load_wb),
-    .outstanding_store_wb_i(outstanding_store_wb),
 
     // Performance Counters
     .perf_jump_o      (perf_jump),
     .perf_branch_o    (perf_branch),
     .perf_tbranch_o   (perf_tbranch),
     .perf_dside_wait_o(perf_dside_wait),
-    .perf_mul_wait_o  (perf_mul_wait),
+    .perf_wfi_wait_o  (perf_wfi_wait),
     .perf_div_wait_o  (perf_div_wait),
     .instr_id_done_o  (instr_id_done)
   );
 
-  assign icache_inval_o = icache_inval;
   // for RVFI only
   assign unused_illegal_insn_id = illegal_insn_id;
 
-  ibex_ex_block #(
+  cve2_ex_block #(
     .RV32M          (RV32M),
-    .RV32B          (RV32B),
-    .BranchTargetALU(BranchTargetALU)
+    .RV32B          (RV32B)
   ) ex_block_i (
-    .clk_i (clk),
+    .clk_i (clk_i),
     .rst_ni(rst_ni),
 
     // ALU signal from ID stage
@@ -669,10 +497,6 @@ module ibex_core import ibex_pkg::*; #(
     .alu_operand_b_i        (alu_operand_b_ex),
     .alu_instr_first_cycle_i(instr_first_cycle_id),
 
-    // Branch target ALU signal from ID stage
-    .bt_a_operand_i(bt_a_operand),
-    .bt_b_operand_i(bt_b_operand),
-
     // Multipler/Divider signal from ID stage
     .multdiv_operator_i   (multdiv_operator_ex),
     .mult_en_i            (mult_en_ex),
@@ -682,8 +506,6 @@ module ibex_core import ibex_pkg::*; #(
     .multdiv_signed_mode_i(multdiv_signed_mode_ex),
     .multdiv_operand_a_i  (multdiv_operand_a_ex),
     .multdiv_operand_b_i  (multdiv_operand_b_ex),
-    .multdiv_ready_id_i   (multdiv_ready_id),
-    .data_ind_timing_i    (data_ind_timing),
 
     // Intermediate value register
     .imd_val_we_o(imd_val_we_ex),
@@ -707,8 +529,8 @@ module ibex_core import ibex_pkg::*; #(
   assign data_req_o   = data_req_out & ~pmp_req_err[PMP_D];
   assign lsu_resp_err = lsu_load_err | lsu_store_err;
 
-  ibex_load_store_unit load_store_unit_i (
-    .clk_i (clk),
+  cve2_load_store_unit load_store_unit_i (
+    .clk_i (clk_i),
     .rst_ni(rst_ni),
 
     // data interface
@@ -733,7 +555,6 @@ module ibex_core import ibex_pkg::*; #(
     .lsu_rdata_o      (rf_wdata_lsu),
     .lsu_rdata_valid_o(rf_we_lsu),
     .lsu_req_i        (lsu_req),
-    .lsu_req_done_o   (lsu_req_done),
 
     .adder_result_ex_i(alu_adder_result_ex),
 
@@ -753,27 +574,17 @@ module ibex_core import ibex_pkg::*; #(
     .perf_store_o(perf_store)
   );
 
-  ibex_wb_stage #(
-    .ResetAll       ( ResetAll       ),
-    .WritebackStage(WritebackStage)
-  ) wb_stage_i (
-    .clk_i                   (clk),
-    .rst_ni                  (rst_ni),
-    .en_wb_i                 (en_wb),
-    .instr_type_wb_i         (instr_type_wb),
-    .pc_id_i                 (pc_id),
+  cve2_wb #(
+  ) wb_i (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+    .en_wb_i (en_wb),
+
     .instr_is_compressed_id_i(instr_is_compressed_id),
     .instr_perf_count_id_i   (instr_perf_count_id),
 
-    .ready_wb_o                         (ready_wb),
-    .rf_write_wb_o                      (rf_write_wb),
-    .outstanding_load_wb_o              (outstanding_load_wb),
-    .outstanding_store_wb_o             (outstanding_store_wb),
-    .pc_wb_o                            (pc_wb),
     .perf_instr_ret_wb_o                (perf_instr_ret_wb),
     .perf_instr_ret_compressed_wb_o     (perf_instr_ret_compressed_wb),
-    .perf_instr_ret_wb_spec_o           (perf_instr_ret_wb_spec),
-    .perf_instr_ret_compressed_wb_spec_o(perf_instr_ret_compressed_wb_spec),
 
     .rf_waddr_id_i(rf_waddr_id),
     .rf_wdata_id_i(rf_wdata_id),
@@ -782,79 +593,14 @@ module ibex_core import ibex_pkg::*; #(
     .rf_wdata_lsu_i(rf_wdata_lsu),
     .rf_we_lsu_i   (rf_we_lsu),
 
-    .rf_wdata_fwd_wb_o(rf_wdata_fwd_wb),
-
     .rf_waddr_wb_o(rf_waddr_wb),
     .rf_wdata_wb_o(rf_wdata_wb),
     .rf_we_wb_o   (rf_we_wb),
 
     .lsu_resp_valid_i(lsu_resp_valid),
-    .lsu_resp_err_i  (lsu_resp_err),
-
-    .instr_done_wb_o(instr_done_wb)
+    .lsu_resp_err_i  (lsu_resp_err)
   );
 
-  /////////////////////////////
-  // Register file interface //
-  /////////////////////////////
-
-  assign dummy_instr_id_o = dummy_instr_id;
-  assign rf_raddr_a_o     = rf_raddr_a;
-  assign rf_waddr_wb_o    = rf_waddr_wb;
-  assign rf_we_wb_o       = rf_we_wb;
-  assign rf_raddr_b_o     = rf_raddr_b;
-
-  if (RegFileECC) begin : gen_regfile_ecc
-
-    // SEC_CM: DATA_REG_SW.INTEGRITY
-    logic [1:0] rf_ecc_err_a, rf_ecc_err_b;
-    logic       rf_ecc_err_a_id, rf_ecc_err_b_id;
-
-    // ECC checkbit generation for regiter file wdata
-    prim_secded_inv_39_32_enc regfile_ecc_enc (
-      .data_i(rf_wdata_wb),
-      .data_o(rf_wdata_wb_ecc_o)
-    );
-
-    // ECC checking on register file rdata
-    prim_secded_inv_39_32_dec regfile_ecc_dec_a (
-      .data_i    (rf_rdata_a_ecc_i),
-      .data_o    (),
-      .syndrome_o(),
-      .err_o     (rf_ecc_err_a)
-    );
-    prim_secded_inv_39_32_dec regfile_ecc_dec_b (
-      .data_i    (rf_rdata_b_ecc_i),
-      .data_o    (),
-      .syndrome_o(),
-      .err_o     (rf_ecc_err_b)
-    );
-
-    // Assign read outputs - no error correction, just trigger an alert
-    assign rf_rdata_a = rf_rdata_a_ecc_i[31:0];
-    assign rf_rdata_b = rf_rdata_b_ecc_i[31:0];
-
-    // Calculate errors - qualify with WB forwarding to avoid xprop into the alert signal
-    assign rf_ecc_err_a_id = |rf_ecc_err_a & rf_ren_a & ~rf_rd_a_wb_match;
-    assign rf_ecc_err_b_id = |rf_ecc_err_b & rf_ren_b & ~rf_rd_b_wb_match;
-
-    // Combined error
-    assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id);
-
-  end else begin : gen_no_regfile_ecc
-    logic unused_rf_ren_a, unused_rf_ren_b;
-    logic unused_rf_rd_a_wb_match, unused_rf_rd_b_wb_match;
-
-    assign unused_rf_ren_a         = rf_ren_a;
-    assign unused_rf_ren_b         = rf_ren_b;
-    assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match;
-    assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match;
-    assign rf_wdata_wb_ecc_o       = rf_wdata_wb;
-    assign rf_rdata_a              = rf_rdata_a_ecc_i;
-    assign rf_rdata_b              = rf_rdata_b_ecc_i;
-    assign rf_ecc_err_comb         = 1'b0;
-  end
-
   ///////////////////////
   // Crash dump output //
   ///////////////////////
@@ -864,15 +610,6 @@ module ibex_core import ibex_pkg::*; #(
   assign crash_dump_o.last_data_addr = lsu_addr_last;
   assign crash_dump_o.exception_addr = csr_mepc;
 
-  ///////////////////
-  // Alert outputs //
-  ///////////////////
-
-  // Minor alert - core is in a recoverable state
-  assign alert_minor_o = icache_ecc_error;
-
-  // Major alert - core is unrecoverable
-  assign alert_major_o = rf_ecc_err_comb | pc_mismatch_alert | csr_shadow_err;
 
   // Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
   `ifdef INC_ASSERT
@@ -888,19 +625,7 @@ module ibex_core import ibex_pkg::*; #(
   assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec &
                                 id_stage_i.lsu_we;
 
-  if (WritebackStage) begin : gen_wb_stage
-    // When the writeback stage is present a load/store could be in ID or WB. A Load/store in ID can
-    // see a response before it moves to WB when it is unaligned otherwise we should only see
-    // a response when load/store is in WB.
-    assign outstanding_load_resp  = outstanding_load_wb |
-      (outstanding_load_id  & load_store_unit_i.split_misaligned_access);
-
-    assign outstanding_store_resp = outstanding_store_wb |
-      (outstanding_store_id & load_store_unit_i.split_misaligned_access);
-
-    // When writing back the result of a load, the load must have made it to writeback
-    `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_wb, clk_i, !rst_ni)
-  end else begin : gen_no_wb_stage
+  begin : gen_no_wb_stage
     // Without writeback stage only look into whether load or store is in ID to determine if
     // a response is expected.
     assign outstanding_load_resp  = outstanding_load_id;
@@ -916,8 +641,24 @@ module ibex_core import ibex_pkg::*; #(
   ////////////////////////
   // RF (Register File) //
   ////////////////////////
-`ifdef RVFI
-`endif
+  cve2_register_file_ff #(
+    .RV32E            (RV32E),
+    .DataWidth        (32),
+    .WordZeroVal      (32'h0)
+  ) register_file_i (
+    .clk_i (clk_i),
+    .rst_ni(rst_ni),
+
+    .test_en_i(test_en_i),
+
+    .raddr_a_i(rf_raddr_a),
+    .rdata_a_o(rf_rdata_a),
+    .raddr_b_i(rf_raddr_b),
+    .rdata_b_o(rf_rdata_b),
+    .waddr_a_i(rf_waddr_wb),
+    .wdata_a_i(rf_wdata_wb),
+    .we_a_i   (rf_we_wb)
+  );
 
 
   /////////////////////////////////////////
@@ -927,13 +668,9 @@ module ibex_core import ibex_pkg::*; #(
   assign csr_wdata  = alu_operand_a_ex;
   assign csr_addr   = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0);
 
-  ibex_cs_registers #(
+  cve2_cs_registers #(
     .DbgTriggerEn     (DbgTriggerEn),
     .DbgHwBreakNum    (DbgHwBreakNum),
-    .DataIndTiming    (DataIndTiming),
-    .DummyInstructions(DummyInstructions),
-    .ShadowCSR        (ShadowCSR),
-    .ICache           (ICache),
     .MHPMCounterNum   (MHPMCounterNum),
     .MHPMCounterWidth (MHPMCounterWidth),
     .PMPEnable        (PMPEnable),
@@ -943,7 +680,7 @@ module ibex_core import ibex_pkg::*; #(
     .RV32M            (RV32M),
     .RV32B            (RV32B)
   ) cs_registers_i (
-    .clk_i (clk),
+    .clk_i (clk_i),
     .rst_ni(rst_ni),
 
     // Hart ID from outside
@@ -993,19 +730,9 @@ module ibex_core import ibex_pkg::*; #(
 
     .pc_if_i(pc_if),
     .pc_id_i(pc_id),
-    .pc_wb_i(pc_wb),
-
-    .data_ind_timing_o    (data_ind_timing),
-    .dummy_instr_en_o     (dummy_instr_en),
-    .dummy_instr_mask_o   (dummy_instr_mask),
-    .dummy_instr_seed_en_o(dummy_instr_seed_en),
-    .dummy_instr_seed_o   (dummy_instr_seed),
-    .icache_enable_o      (icache_enable),
-    .csr_shadow_err_o     (csr_shadow_err),
 
     .csr_save_if_i     (csr_save_if),
     .csr_save_id_i     (csr_save_id),
-    .csr_save_wb_i     (csr_save_wb),
     .csr_restore_mret_i(csr_restore_mret_id),
     .csr_restore_dret_i(csr_restore_dret_id),
     .csr_save_cause_i  (csr_save_cause),
@@ -1013,13 +740,9 @@ module ibex_core import ibex_pkg::*; #(
     .csr_mtval_i       (csr_mtval),
     .illegal_csr_insn_o(illegal_csr_insn_id),
 
-    .double_fault_seen_o,
-
     // performance counter related signals
     .instr_ret_i                (perf_instr_ret_wb),
     .instr_ret_compressed_i     (perf_instr_ret_compressed_wb),
-    .instr_ret_spec_i           (perf_instr_ret_wb_spec),
-    .instr_ret_compressed_spec_i(perf_instr_ret_compressed_wb_spec),
     .iside_wait_i               (perf_iside_wait),
     .jump_i                     (perf_jump),
     .branch_i                   (perf_branch),
@@ -1027,7 +750,7 @@ module ibex_core import ibex_pkg::*; #(
     .mem_load_i                 (perf_load),
     .mem_store_i                (perf_store),
     .dside_wait_i               (perf_dside_wait),
-    .mul_wait_i                 (perf_mul_wait),
+    .wfi_wait_i                 (perf_wfi_wait),
     .div_wait_i                 (perf_div_wait)
   );
 
@@ -1055,7 +778,7 @@ module ibex_core import ibex_pkg::*; #(
     assign pmp_req_type[PMP_D]  = data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ;
     assign pmp_priv_lvl[PMP_D]  = priv_mode_lsu;
 
-    ibex_pmp #(
+    cve2_pmp #(
       .PMPGranularity(PMPGranularity),
       .PMPNumChan    (PMP_NUM_CHAN),
       .PMPNumRegions (PMPNumRegions)
@@ -1096,7 +819,7 @@ module ibex_core import ibex_pkg::*; #(
   // second stage. RVFI outputs are all straight from flops. So 2 stage pipeline requires a single
   // set of flops (instr_info => RVFI_out), 3 stage pipeline requires two sets (instr_info => wb
   // => RVFI_out)
-  localparam int RVFI_STAGES = WritebackStage ? 2 : 1;
+  localparam int RVFI_STAGES = 1;
 
   logic        rvfi_stage_valid     [RVFI_STAGES];
   logic [63:0] rvfi_stage_order     [RVFI_STAGES];
@@ -1153,22 +876,20 @@ module ibex_core import ibex_pkg::*; #(
   logic [31:0] rvfi_mem_addr_d;
   logic [31:0] rvfi_mem_addr_q;
   logic        rvfi_trap_id;
-  logic        rvfi_trap_wb;
   logic [63:0] rvfi_stage_order_d;
   logic        rvfi_id_done;
-  logic        rvfi_wb_done;
 
   logic            new_debug_req;
   logic            new_nmi;
   logic            new_irq;
-  ibex_pkg::irqs_t captured_mip;
+  cve2_pkg::irqs_t captured_mip;
   logic            captured_nmi;
   logic            captured_debug_req;
   logic            captured_valid;
 
   // RVFI extension for co-simulation support
   // debug_req and MIP captured at IF -> ID transition so one extra stage
-  ibex_pkg::irqs_t rvfi_ext_stage_mip          [RVFI_STAGES+1];
+  cve2_pkg::irqs_t rvfi_ext_stage_mip          [RVFI_STAGES+1];
   logic            rvfi_ext_stage_nmi          [RVFI_STAGES+1];
   logic            rvfi_ext_stage_debug_req    [RVFI_STAGES+1];
   logic [63:0]     rvfi_ext_stage_mcycle       [RVFI_STAGES];
@@ -1226,56 +947,20 @@ module ibex_core import ibex_pkg::*; #(
 
   // Factor in exceptions taken in ID so RVFI tracking picks up flushed instructions that took
   // a trap
-  assign rvfi_id_done = instr_id_done | (id_stage_i.controller_i.rvfi_flush_next &
-                                         id_stage_i.controller_i.id_exception_o);
-
-  if (WritebackStage) begin : gen_rvfi_wb_stage
-    logic unused_instr_new_id;
+  // MRET causes MSTATUS to get written one clock later. Fix rvfi_valid when executing MRET
+  assign rvfi_id_done = (instr_id_done & !id_stage_i.controller_i.mret_insn)|
+                         id_stage_i.csr_restore_mret_id_o |
+                        (id_stage_i.controller_i.rvfi_flush_next & id_stage_i.controller_i.exc_req_d);
 
-    assign unused_instr_new_id = instr_new_id;
+  // Without writeback stage first RVFI stage is output stage so simply valid the cycle after
+  // instruction leaves ID/EX (and so has retired)
+  assign rvfi_stage_valid_d[0] = rvfi_id_done;
+  // Without writeback stage signal new instr_new_wb when instruction enters ID/EX to correctly
+  // setup register write signals
+  assign rvfi_instr_new_wb = instr_new_id;
+  assign rvfi_trap_id = id_stage_i.controller_i.exc_req_d | id_stage_i.controller_i.exc_req_lsu;
 
-    // With writeback stage first RVFI stage buffers instruction information captured in ID/EX
-    // awaiting instruction retirement and RF Write data/Mem read data whilst instruction is in WB
-    // So first stage becomes valid when instruction leaves ID/EX stage and remains valid until
-    // instruction leaves WB
-    assign rvfi_stage_valid_d[0] = (rvfi_id_done & ~dummy_instr_id) |
-                                   (rvfi_stage_valid[0] & ~rvfi_wb_done);
-    // Second stage is output stage so simple valid cycle after instruction leaves WB (and so has
-    // retired)
-    assign rvfi_stage_valid_d[1] = rvfi_wb_done;
-
-    // Signal new instruction in WB cycle after instruction leaves ID/EX (to enter WB)
-    logic rvfi_instr_new_wb_q;
-
-    // Signal new instruction in WB either when one has just entered or when a trap is progressing
-    // through the tracking pipeline
-    assign rvfi_instr_new_wb = rvfi_instr_new_wb_q | (rvfi_stage_valid[0] & rvfi_stage_trap[0]);
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        rvfi_instr_new_wb_q <= 0;
-      end else begin
-        rvfi_instr_new_wb_q <= rvfi_id_done;
-      end
-    end
-
-    assign rvfi_trap_id = id_stage_i.controller_i.id_exception_o;
-    assign rvfi_trap_wb = id_stage_i.controller_i.exc_req_lsu;
-    // WB is instantly done in the tracking pipeline when a trap is progress through the pipeline
-    assign rvfi_wb_done = instr_done_wb | (rvfi_stage_valid[0] & rvfi_stage_trap[0]);
-  end else begin : gen_rvfi_no_wb_stage
-    // Without writeback stage first RVFI stage is output stage so simply valid the cycle after
-    // instruction leaves ID/EX (and so has retired)
-    assign rvfi_stage_valid_d[0] = rvfi_id_done & ~dummy_instr_id;
-    // Without writeback stage signal new instr_new_wb when instruction enters ID/EX to correctly
-    // setup register write signals
-    assign rvfi_instr_new_wb = instr_new_id;
-    assign rvfi_trap_id = id_stage_i.controller_i.exc_req_d | id_stage_i.controller_i.exc_req_lsu;
-    assign rvfi_trap_wb = 1'b0;
-    assign rvfi_wb_done = instr_done_wb;
-  end
-
-  assign rvfi_stage_order_d = dummy_instr_id ? rvfi_stage_order[0] : rvfi_stage_order[0] + 64'd1;
+  assign rvfi_stage_order_d = rvfi_stage_order[0] + 64'd1;
 
   // For interrupts and debug Ibex will take the relevant trap as soon as whatever instruction in ID
   // finishes or immediately if the ID stage is empty. The rvfi_ext interface provides the DV
@@ -1410,9 +1095,8 @@ module ibex_core import ibex_pkg::*; #(
             rvfi_ext_stage_mcycle[i]      <= cs_registers_i.mcycle_counter_i.counter_val_o;
           end
         end else begin
-          if (rvfi_wb_done) begin
             rvfi_stage_halt[i]      <= rvfi_stage_halt[i-1];
-            rvfi_stage_trap[i]      <= rvfi_stage_trap[i-1] | rvfi_trap_wb;
+            rvfi_stage_trap[i]      <= rvfi_stage_trap[i-1];
             rvfi_stage_intr[i]      <= rvfi_stage_intr[i-1];
             rvfi_stage_order[i]     <= rvfi_stage_order[i-1];
             rvfi_stage_insn[i]      <= rvfi_stage_insn[i-1];
@@ -1443,7 +1127,6 @@ module ibex_core import ibex_pkg::*; #(
             rvfi_ext_stage_nmi[i+1]       <= rvfi_ext_stage_nmi[i];
             rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
             rvfi_ext_stage_mcycle[i]      <= rvfi_ext_stage_mcycle[i-1];
-          end
         end
       end
     end
@@ -1596,13 +1279,9 @@ module ibex_core import ibex_pkg::*; #(
   end
 
 `else
-  logic unused_instr_new_id, unused_instr_id_done, unused_instr_done_wb;
+  logic unused_instr_new_id, unused_instr_id_done;
   assign unused_instr_id_done = instr_id_done;
   assign unused_instr_new_id = instr_new_id;
-  assign unused_instr_done_wb = instr_done_wb;
 `endif
 
-  // Certain parameter combinations are not supported
-  `ASSERT_INIT(IllegalParamSecure, !(SecureIbex && (RV32M == RV32MNone)))
-
 endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_counter.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_counter.sv
similarity index 99%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_counter.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_counter.sv
index a6187b78..417614b1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_counter.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_counter.sv
@@ -1,4 +1,4 @@
-module ibex_counter #(
+module cve2_counter #(
   parameter int CounterWidth = 32,
   // When set `counter_val_upd_o` provides an incremented version of the counter value, otherwise
   // the output is hard-wired to 0. This is required to allow Xilinx DSP inference to work
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_cs_registers.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_cs_registers.sv
similarity index 86%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_cs_registers.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_cs_registers.sv
index aa328205..dfce0985 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_cs_registers.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_cs_registers.sv
@@ -12,21 +12,17 @@
 
 `include "prim_assert.sv"
 
-module ibex_cs_registers #(
+module cve2_cs_registers #(
   parameter bit               DbgTriggerEn      = 0,
   parameter int unsigned      DbgHwBreakNum     = 1,
-  parameter bit               DataIndTiming     = 1'b0,
-  parameter bit               DummyInstructions = 1'b0,
-  parameter bit               ShadowCSR         = 1'b0,
-  parameter bit               ICache            = 1'b0,
   parameter int unsigned      MHPMCounterNum    = 10,
   parameter int unsigned      MHPMCounterWidth  = 40,
   parameter bit               PMPEnable         = 0,
   parameter int unsigned      PMPGranularity    = 0,
   parameter int unsigned      PMPNumRegions     = 4,
   parameter bit               RV32E             = 0,
-  parameter ibex_pkg::rv32m_e RV32M             = ibex_pkg::RV32MFast,
-  parameter ibex_pkg::rv32b_e RV32B             = ibex_pkg::RV32BNone
+  parameter cve2_pkg::rv32m_e RV32M             = cve2_pkg::RV32MFast,
+  parameter cve2_pkg::rv32b_e RV32B             = cve2_pkg::RV32BNone
 ) (
   // Clock and Reset
   input  logic                 clk_i,
@@ -36,8 +32,8 @@ module ibex_cs_registers #(
   input  logic [31:0]          hart_id_i,
 
   // Privilege mode
-  output ibex_pkg::priv_lvl_e  priv_mode_id_o,
-  output ibex_pkg::priv_lvl_e  priv_mode_lsu_o,
+  output cve2_pkg::priv_lvl_e  priv_mode_id_o,
+  output cve2_pkg::priv_lvl_e  priv_mode_lsu_o,
   output logic                 csr_mstatus_tw_o,
 
   // mtvec
@@ -47,9 +43,9 @@ module ibex_cs_registers #(
 
   // Interface to registers (SRAM like)
   input  logic                 csr_access_i,
-  input  ibex_pkg::csr_num_e   csr_addr_i,
+  input  cve2_pkg::csr_num_e   csr_addr_i,
   input  logic [31:0]          csr_wdata_i,
-  input  ibex_pkg::csr_op_e    csr_op_i,
+  input  cve2_pkg::csr_op_e    csr_op_i,
   input                        csr_op_en_i,
   output logic [31:0]          csr_rdata_o,
 
@@ -57,21 +53,21 @@ module ibex_cs_registers #(
   input  logic                 irq_software_i,
   input  logic                 irq_timer_i,
   input  logic                 irq_external_i,
-  input  logic [14:0]          irq_fast_i,
+  input  logic [15:0]          irq_fast_i,
   input  logic                 nmi_mode_i,
   output logic                 irq_pending_o,          // interrupt request pending
-  output ibex_pkg::irqs_t      irqs_o,                 // interrupt requests qualified with mie
+  output cve2_pkg::irqs_t      irqs_o,                 // interrupt requests qualified with mie
   output logic                 csr_mstatus_mie_o,
   output logic [31:0]          csr_mepc_o,
 
   // PMP
-  output ibex_pkg::pmp_cfg_t     csr_pmp_cfg_o  [PMPNumRegions],
+  output cve2_pkg::pmp_cfg_t     csr_pmp_cfg_o  [PMPNumRegions],
   output logic [33:0]            csr_pmp_addr_o [PMPNumRegions],
-  output ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_o,
+  output cve2_pkg::pmp_mseccfg_t csr_pmp_mseccfg_o,
 
   // debug
   input  logic                 debug_mode_i,
-  input  ibex_pkg::dbg_cause_e debug_cause_i,
+  input  cve2_pkg::dbg_cause_e debug_cause_i,
   input  logic                 debug_csr_save_i,
   output logic [31:0]          csr_depc_o,
   output logic                 debug_single_step_o,
@@ -81,35 +77,21 @@ module ibex_cs_registers #(
 
   input  logic [31:0]          pc_if_i,
   input  logic [31:0]          pc_id_i,
-  input  logic [31:0]          pc_wb_i,
-
-  // CPU control bits
-  output logic                 data_ind_timing_o,
-  output logic                 dummy_instr_en_o,
-  output logic [2:0]           dummy_instr_mask_o,
-  output logic                 dummy_instr_seed_en_o,
-  output logic [31:0]          dummy_instr_seed_o,
-  output logic                 icache_enable_o,
-  output logic                 csr_shadow_err_o,
 
   // Exception save/restore
   input  logic                 csr_save_if_i,
   input  logic                 csr_save_id_i,
-  input  logic                 csr_save_wb_i,
   input  logic                 csr_restore_mret_i,
   input  logic                 csr_restore_dret_i,
   input  logic                 csr_save_cause_i,
-  input  ibex_pkg::exc_cause_e csr_mcause_i,
+  input  cve2_pkg::exc_cause_e csr_mcause_i,
   input  logic [31:0]          csr_mtval_i,
   output logic                 illegal_csr_insn_o,     // access to non-existent CSR,
                                                         // with wrong priviledge level, or
                                                         // missing write permissions
-  output logic                 double_fault_seen_o,
   // Performance Counters
   input  logic                 instr_ret_i,                 // instr retired in ID/EX stage
   input  logic                 instr_ret_compressed_i,      // compressed instr retired
-  input  logic                 instr_ret_spec_i,            // speculative instr_ret_i
-  input  logic                 instr_ret_compressed_spec_i, // speculative instr_ret_compressed_i
   input  logic                 iside_wait_i,                // core waiting for the iside
   input  logic                 jump_i,                      // jump instr seen (j, jr, jal, jalr)
   input  logic                 branch_i,                    // branch instr seen (bf, bnf)
@@ -117,11 +99,11 @@ module ibex_cs_registers #(
   input  logic                 mem_load_i,                  // load from memory in this cycle
   input  logic                 mem_store_i,                 // store to memory in this cycle
   input  logic                 dside_wait_i,                // core waiting for the dside
-  input  logic                 mul_wait_i,                  // core waiting for multiply
+  input  logic                 wfi_wait_i,                  // core waiting for interrupt
   input  logic                 div_wait_i                   // core waiting for divide
 );
 
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   localparam int unsigned RV32BEnabled = (RV32B == RV32BNone) ? 0 : 1;
   localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1;
@@ -174,23 +156,12 @@ module ibex_cs_registers #(
       priv_lvl_e    prv;
   } dcsr_t;
 
-  // CPU control register fields
-  typedef struct packed {
-    logic        double_fault_seen;
-    logic        sync_exc_seen;
-    logic [2:0]  dummy_instr_mask;
-    logic        dummy_instr_en;
-    logic        data_ind_timing;
-    logic        icache_enable;
-  } cpu_ctrl_t;
-
   // Interrupt and exception control signals
   logic [31:0] exception_pc;
 
   // CSRs
   priv_lvl_e   priv_lvl_q, priv_lvl_d;
   status_t     mstatus_q, mstatus_d;
-  logic        mstatus_err;
   logic        mstatus_en;
   irqs_t       mie_q, mie_d;
   logic        mie_en;
@@ -198,12 +169,11 @@ module ibex_cs_registers #(
   logic        mscratch_en;
   logic [31:0] mepc_q, mepc_d;
   logic        mepc_en;
-  logic  [5:0] mcause_q, mcause_d;
+  logic  [6:0] mcause_q, mcause_d;
   logic        mcause_en;
   logic [31:0] mtval_q, mtval_d;
   logic        mtval_en;
   logic [31:0] mtvec_q, mtvec_d;
-  logic        mtvec_err;
   logic        mtvec_en;
   irqs_t       mip;
   dcsr_t       dcsr_q, dcsr_d;
@@ -219,12 +189,11 @@ module ibex_cs_registers #(
   status_stk_t mstack_q, mstack_d;
   logic        mstack_en;
   logic [31:0] mstack_epc_q, mstack_epc_d;
-  logic  [5:0] mstack_cause_q, mstack_cause_d;
+  logic  [6:0] mstack_cause_q, mstack_cause_d;
 
   // PMP Signals
   logic [31:0]                 pmp_addr_rdata  [PMP_MAX_REGIONS];
   logic [PMP_CFG_W-1:0]        pmp_cfg_rdata   [PMP_MAX_REGIONS];
-  logic                        pmp_csr_err;
   pmp_mseccfg_t                pmp_mseccfg;
 
   // Hardware performance monitor signals
@@ -246,18 +215,13 @@ module ibex_cs_registers #(
   logic        unused_mhpmcounterh_we_1;
   logic        unused_mhpmcounter_incr_1;
 
-  logic [63:0] minstret_next, minstret_raw;
+  logic [63:0] minstret_raw;
 
   // Debug / trigger registers
   logic [31:0] tselect_rdata;
   logic [31:0] tmatch_control_rdata;
   logic [31:0] tmatch_value_rdata;
 
-  // CPU control bits
-  cpu_ctrl_t   cpuctrl_q, cpuctrl_d, cpuctrl_wdata_raw, cpuctrl_wdata;
-  logic        cpuctrl_we;
-  logic        cpuctrl_err;
-
   // CSR update logic
   logic [31:0] csr_wdata_int;
   logic [31:0] csr_rdata_int;
@@ -308,6 +272,8 @@ module ibex_cs_registers #(
       CSR_MIMPID: csr_rdata_int = CSR_MIMPID_VALUE;
       // mhartid: unique hardware thread id
       CSR_MHARTID: csr_rdata_int = hart_id_i;
+      // mconfigptr: pointer to configuration data structre
+      CSR_MCONFIGPTR: csr_rdata_int = CSR_MCONFIGPTR_VALUE;
 
       // mstatus: always M-mode, contains IE bit
       CSR_MSTATUS: begin
@@ -319,6 +285,13 @@ module ibex_cs_registers #(
         csr_rdata_int[CSR_MSTATUS_TW_BIT]                               = mstatus_q.tw;
       end
 
+      // mstatush: All zeros for Ibex (fixed little endian and all other bits reserved)
+      CSR_MSTATUSH: csr_rdata_int = '0;
+
+      // menvcfg: machine environment configuration, all zeros for Ibex (none of the relevant
+      // features are implemented)
+      CSR_MENVCFG, CSR_MENVCFGH: csr_rdata_int = '0;
+
       // misa
       CSR_MISA: csr_rdata_int = MISA_VALUE;
 
@@ -345,7 +318,7 @@ module ibex_cs_registers #(
       CSR_MEPC: csr_rdata_int = mepc_q;
 
       // mcause: exception cause
-      CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b0, mcause_q[4:0]};
+      CSR_MCAUSE: csr_rdata_int = {mcause_q[6], 25'b0, mcause_q[5:0]};
 
       // mtval: trap value
       CSR_MTVAL: csr_rdata_int = mtval_q;
@@ -486,11 +459,6 @@ module ibex_cs_registers #(
         illegal_csr   = ~DbgTriggerEn;
       end
 
-      // Custom CSR for controlling CPU features
-      CSR_CPUCTRL: begin
-        csr_rdata_int = {{32 - $bits(cpu_ctrl_t) {1'b0}}, cpuctrl_q};
-      end
-
       // Custom CSR for LFSR re-seeding (cannot be read)
       CSR_SECURESEED: begin
         csr_rdata_int = '0;
@@ -500,6 +468,16 @@ module ibex_cs_registers #(
         illegal_csr = 1'b1;
       end
     endcase
+
+    if (!PMPEnable) begin
+      if (csr_addr inside {CSR_PMPCFG0,   CSR_PMPCFG1,   CSR_PMPCFG2,   CSR_PMPCFG3,
+                           CSR_PMPADDR0,  CSR_PMPADDR1,  CSR_PMPADDR2,  CSR_PMPADDR3,
+                           CSR_PMPADDR4,  CSR_PMPADDR5,  CSR_PMPADDR6,  CSR_PMPADDR7,
+                           CSR_PMPADDR8,  CSR_PMPADDR9,  CSR_PMPADDR10, CSR_PMPADDR11,
+                           CSR_PMPADDR12, CSR_PMPADDR13, CSR_PMPADDR14, CSR_PMPADDR15}) begin
+        illegal_csr = 1'b1;
+      end
+    end
   end
 
   // write logic
@@ -514,7 +492,7 @@ module ibex_cs_registers #(
     mepc_en      = 1'b0;
     mepc_d       = {csr_wdata_int[31:1], 1'b0};
     mcause_en    = 1'b0;
-    mcause_d     = {csr_wdata_int[31], csr_wdata_int[4:0]};
+    mcause_d     = {csr_wdata_int[31], csr_wdata_int[5:0]};
     mtval_en     = 1'b0;
     mtval_d      = csr_wdata_int;
     mtvec_en     = csr_mtvec_init_i;
@@ -539,11 +517,6 @@ module ibex_cs_registers #(
     mhpmcounter_we   = '0;
     mhpmcounterh_we  = '0;
 
-    cpuctrl_we       = 1'b0;
-    cpuctrl_d        = cpuctrl_q;
-
-    double_fault_seen_o = 1'b0;
-
     if (csr_we_int) begin
       unique case (csr_addr_i)
         // mstatus: IE bit
@@ -641,11 +614,6 @@ module ibex_cs_registers #(
           mhpmcounterh_we[mhpmcounter_idx] = 1'b1;
         end
 
-        CSR_CPUCTRL: begin
-          cpuctrl_d  = cpuctrl_wdata;
-          cpuctrl_we = 1'b1;
-        end
-
         default:;
       endcase
     end
@@ -661,9 +629,6 @@ module ibex_cs_registers #(
           csr_save_id_i: begin
             exception_pc = pc_id_i;
           end
-          csr_save_wb_i: begin
-            exception_pc = pc_wb_i;
-          end
           default:;
         endcase
 
@@ -695,17 +660,6 @@ module ibex_cs_registers #(
           // save previous status for recoverable NMI
           mstack_en      = 1'b1;
 
-          if (!mcause_d[5]) begin
-            // SEC_CM: EXCEPTION.CTRL_FLOW.LOCAL_ESC
-            // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC
-            cpuctrl_we = 1'b1;
-
-            cpuctrl_d.sync_exc_seen = 1'b1;
-            if (cpuctrl_q.sync_exc_seen) begin
-              double_fault_seen_o         = 1'b1;
-              cpuctrl_d.double_fault_seen = 1'b1;
-            end
-          end
         end
       end // csr_save_cause_i
 
@@ -718,10 +672,12 @@ module ibex_cs_registers #(
         mstatus_en     = 1'b1;
         mstatus_d.mie  = mstatus_q.mpie; // re-enable interrupts
 
+        if (mstatus_q.mpp != PRIV_LVL_M) begin
+          mstatus_d.mprv = 1'b0;
+        end
+
         // SEC_CM: EXCEPTION.CTRL_FLOW.LOCAL_ESC
         // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC
-        cpuctrl_we              = 1'b1;
-        cpuctrl_d.sync_exc_seen = 1'b0;
 
         if (nmi_mode_i) begin
           // when returning from an NMI restore state from mstack CSR
@@ -797,13 +753,12 @@ module ibex_cs_registers #(
 
   // MSTATUS
   localparam status_t MSTATUS_RST_VAL = '{mie:  1'b0,
-                                          mpie: 1'b1,
-                                          mpp:  PRIV_LVL_U,
+                                          mpie: 1'b0,
+                                          mpp:  PRIV_LVL_M,
                                           mprv: 1'b0,
                                           tw:   1'b0};
-  ibex_csr #(
+  cve2_csr #(
     .Width     ($bits(status_t)),
-    .ShadowCopy(ShadowCSR),
     .ResetValue({MSTATUS_RST_VAL})
   ) u_mstatus_csr (
     .clk_i     (clk_i),
@@ -811,11 +766,11 @@ module ibex_cs_registers #(
     .wr_data_i ({mstatus_d}),
     .wr_en_i   (mstatus_en),
     .rd_data_o (mstatus_q),
-    .rd_error_o(mstatus_err)
+    .rd_error_o()
   );
 
   // MEPC
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -833,7 +788,7 @@ module ibex_cs_registers #(
   assign mie_d.irq_timer    = csr_wdata_int[CSR_MTIX_BIT];
   assign mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT];
   assign mie_d.irq_fast     = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW];
-  ibex_csr #(
+  cve2_csr #(
     .Width     ($bits(irqs_t)),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -847,7 +802,7 @@ module ibex_cs_registers #(
   );
 
   // MSCRATCH
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -861,8 +816,8 @@ module ibex_cs_registers #(
   );
 
   // MCAUSE
-  ibex_csr #(
-    .Width     (6),
+  cve2_csr #(
+    .Width     (7),
     .ShadowCopy(1'b0),
     .ResetValue('0)
   ) u_mcause_csr (
@@ -875,7 +830,7 @@ module ibex_cs_registers #(
   );
 
   // MTVAL
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -889,9 +844,8 @@ module ibex_cs_registers #(
   );
 
   // MTVEC
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
-    .ShadowCopy(ShadowCSR),
     .ResetValue(32'd1)
   ) u_mtvec_csr (
     .clk_i     (clk_i),
@@ -899,7 +853,7 @@ module ibex_cs_registers #(
     .wr_data_i (mtvec_d),
     .wr_en_i   (mtvec_en),
     .rd_data_o (mtvec_q),
-    .rd_error_o(mtvec_err)
+    .rd_error_o()
   );
 
   // DCSR
@@ -909,7 +863,7 @@ module ibex_cs_registers #(
       prv: PRIV_LVL_M,
       default: '0
   };
-  ibex_csr #(
+  cve2_csr #(
     .Width     ($bits(dcsr_t)),
     .ShadowCopy(1'b0),
     .ResetValue({DCSR_RESET_VAL})
@@ -923,7 +877,7 @@ module ibex_cs_registers #(
   );
 
   // DEPC
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -937,7 +891,7 @@ module ibex_cs_registers #(
   );
 
   // DSCRATCH0
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -951,7 +905,7 @@ module ibex_cs_registers #(
   );
 
   // DSCRATCH1
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -966,7 +920,7 @@ module ibex_cs_registers #(
 
   // MSTACK
   localparam status_stk_t MSTACK_RESET_VAL = '{mpie: 1'b1, mpp: PRIV_LVL_U};
-  ibex_csr #(
+  cve2_csr #(
     .Width     ($bits(status_stk_t)),
     .ShadowCopy(1'b0),
     .ResetValue({MSTACK_RESET_VAL})
@@ -980,7 +934,7 @@ module ibex_cs_registers #(
   );
 
   // MSTACK_EPC
-  ibex_csr #(
+  cve2_csr #(
     .Width     (32),
     .ShadowCopy(1'b0),
     .ResetValue('0)
@@ -994,8 +948,8 @@ module ibex_cs_registers #(
   );
 
   // MSTACK_CAUSE
-  ibex_csr #(
-    .Width     (6),
+  cve2_csr #(
+    .Width     (7),
     .ShadowCopy(1'b0),
     .ResetValue('0)
   ) u_mstack_cause_csr (
@@ -1013,10 +967,10 @@ module ibex_cs_registers #(
 
   if (PMPEnable) begin : g_pmp_registers
     // PMP reset values
-    `ifdef IBEX_CUSTOM_PMP_RESET_VALUES
-      `include "ibex_pmp_reset.svh"
+    `ifdef CVE2_CUSTOM_PMP_RESET_VALUES
+      `include "cve2_pmp_reset.svh"
     `else
-      `include "ibex_pmp_reset_default.svh"
+      `include "cve2_pmp_reset_default.svh"
     `endif
 
     pmp_mseccfg_t                pmp_mseccfg_q, pmp_mseccfg_d;
@@ -1102,9 +1056,8 @@ module ibex_cs_registers #(
                                                           &csr_wdata_int[(i%4)*PMP_CFG_W+:2];
       assign pmp_cfg_wdata[i].read  = csr_wdata_int[(i%4)*PMP_CFG_W];
 
-      ibex_csr #(
+      cve2_csr #(
         .Width     ($bits(pmp_cfg_t)),
-        .ShadowCopy(ShadowCSR),
         .ResetValue(pmp_cfg_rst[i])
       ) u_pmp_cfg_csr (
         .clk_i     (clk_i),
@@ -1131,9 +1084,8 @@ module ibex_cs_registers #(
                                 (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0]));
       end
 
-      ibex_csr #(
+      cve2_csr #(
         .Width     (PMPAddrWidth),
-        .ShadowCopy(ShadowCSR),
         .ResetValue(pmp_addr_rst[i][33-:PMPAddrWidth])
       ) u_pmp_addr_csr (
         .clk_i     (clk_i),
@@ -1164,9 +1116,8 @@ module ibex_cs_registers #(
     // MSECCFG.RLB cannot be set again
     assign pmp_mseccfg_d.rlb = any_pmp_entry_locked ? 1'b0 : csr_wdata_int[CSR_MSECCFG_RLB_BIT];
 
-    ibex_csr #(
+    cve2_csr #(
       .Width     ($bits(pmp_mseccfg_t)),
-      .ShadowCopy(ShadowCSR),
       .ResetValue(pmp_mseccfg_rst)
     ) u_pmp_mseccfg (
       .clk_i     (clk_i),
@@ -1177,7 +1128,6 @@ module ibex_cs_registers #(
       .rd_error_o(pmp_mseccfg_err)
     );
 
-    assign pmp_csr_err = (|pmp_cfg_err) | (|pmp_addr_err) | pmp_mseccfg_err;
     assign pmp_mseccfg = pmp_mseccfg_q;
 
   end else begin : g_no_pmp_tieoffs
@@ -1190,7 +1140,6 @@ module ibex_cs_registers #(
       assign csr_pmp_cfg_o[i]  = pmp_cfg_t'(1'b0);
       assign csr_pmp_addr_o[i] = '0;
     end
-    assign pmp_csr_err = 1'b0;
     assign pmp_mseccfg = '0;
   end
 
@@ -1219,7 +1168,7 @@ module ibex_cs_registers #(
     end
 
     // When adding or altering performance counter meanings and default
-    // mappings please update dv/verilator/pcount/cpp/ibex_pcounts.cc
+    // mappings please update dv/verilator/pcount/cpp/cve2_pcounts.cc
     // appropriately.
     //
     // active counters
@@ -1234,7 +1183,7 @@ module ibex_cs_registers #(
     mhpmcounter_incr[8]  = branch_i;               // num of branches (conditional)
     mhpmcounter_incr[9]  = branch_taken_i;         // num of taken branches (conditional)
     mhpmcounter_incr[10] = instr_ret_compressed_i; // num of compressed instr
-    mhpmcounter_incr[11] = mul_wait_i;             // cycles waiting for multiply
+    mhpmcounter_incr[11] = wfi_wait_i;             // cycles waiting for multiply
     mhpmcounter_incr[12] = div_wait_i;             // cycles waiting for divide
   end
 
@@ -1255,7 +1204,7 @@ module ibex_cs_registers #(
   end
 
   // mcycle
-  ibex_counter #(
+  cve2_counter #(
     .CounterWidth(64)
   ) mcycle_counter_i (
     .clk_i(clk_i),
@@ -1270,7 +1219,7 @@ module ibex_cs_registers #(
 
 
   // minstret
-  ibex_counter #(
+  cve2_counter #(
     .CounterWidth(64),
     .ProvideValUpd(1)
   ) minstret_counter_i (
@@ -1281,7 +1230,7 @@ module ibex_cs_registers #(
     .counter_we_i(mhpmcounter_we[2]),
     .counter_val_i(csr_wdata_int),
     .counter_val_o(minstret_raw),
-    .counter_val_upd_o(minstret_next)
+    .counter_val_upd_o()
   );
 
   // Where the writeback stage is present instruction in ID observing value of minstret must take
@@ -1291,7 +1240,7 @@ module ibex_cs_registers #(
   // so the incorrect value doesn't matter. A similar behaviour is required for the compressed
   // instruction retired counter below. When the writeback stage isn't present the speculative
   // signals are always 0.
-  assign mhpmcounter[2] = instr_ret_spec_i & ~mcountinhibit[2] ? minstret_next : minstret_raw;
+  assign mhpmcounter[2] = minstret_raw;
 
   // reserved:
   assign mhpmcounter[1]            = '0;
@@ -1306,7 +1255,7 @@ module ibex_cs_registers #(
     if (i < MHPMCounterNum) begin : gen_imp
       logic [63:0] mhpmcounter_raw, mhpmcounter_next;
 
-      ibex_counter #(
+      cve2_counter #(
         .CounterWidth(MHPMCounterWidth),
         .ProvideValUpd(Cnt == 10)
       ) mcounters_variable_i (
@@ -1324,7 +1273,6 @@ module ibex_cs_registers #(
         // Special behaviour for reading compressed instruction retired counter, see comment on
         // `mhpmcounter[2]` above for further information.
         assign mhpmcounter[Cnt] =
-          instr_ret_compressed_spec_i & ~mcountinhibit[Cnt] ? mhpmcounter_next:
                                                               mhpmcounter_raw;
       end else begin : gen_other_cnts
         logic [63:0] unused_mhpmcounter_next;
@@ -1334,11 +1282,6 @@ module ibex_cs_registers #(
       end
     end else begin : gen_unimp
       assign mhpmcounter[Cnt] = '0;
-
-      if (Cnt == 10) begin : gen_no_compressed_instr_cnt
-        logic unused_instr_ret_compressed_spec_i;
-        assign unused_instr_ret_compressed_spec_i = instr_ret_compressed_spec_i;
-      end
     end
   end
 
@@ -1407,7 +1350,7 @@ module ibex_cs_registers #(
     assign tmatch_value_d   = csr_wdata_int[31:0];
 
     // Registers
-    ibex_csr #(
+    cve2_csr #(
       .Width     (DbgHwNumLen),
       .ShadowCopy(1'b0),
       .ResetValue('0)
@@ -1421,7 +1364,7 @@ module ibex_cs_registers #(
     );
 
     for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_reg
-      ibex_csr #(
+      cve2_csr #(
         .Width     (1),
         .ShadowCopy(1'b0),
         .ResetValue('0)
@@ -1434,7 +1377,7 @@ module ibex_cs_registers #(
         .rd_error_o()
       );
 
-      ibex_csr #(
+      cve2_csr #(
         .Width     (32),
         .ShadowCopy(1'b0),
         .ResetValue('0)
@@ -1501,88 +1444,12 @@ module ibex_cs_registers #(
   // CPU control register //
   //////////////////////////
 
-  // Cast register write data
-  assign cpuctrl_wdata_raw = cpu_ctrl_t'(csr_wdata_int[$bits(cpu_ctrl_t)-1:0]);
-
-  // Generate fixed time execution bit
-  if (DataIndTiming) begin : gen_dit
-    // SEC_CM: CORE.DATA_REG_SW.SCA
-    assign cpuctrl_wdata.data_ind_timing = cpuctrl_wdata_raw.data_ind_timing;
-
-  end else begin : gen_no_dit
-    // tieoff for the unused bit
-    logic unused_dit;
-    assign unused_dit = cpuctrl_wdata_raw.data_ind_timing;
-
-    // field will always read as zero if not configured
-    assign cpuctrl_wdata.data_ind_timing = 1'b0;
-  end
-
-  assign data_ind_timing_o = cpuctrl_q.data_ind_timing;
-
-  // Generate dummy instruction signals
-  if (DummyInstructions) begin : gen_dummy
-    // SEC_CM: CTRL_FLOW.UNPREDICTABLE
-    assign cpuctrl_wdata.dummy_instr_en   = cpuctrl_wdata_raw.dummy_instr_en;
-    assign cpuctrl_wdata.dummy_instr_mask = cpuctrl_wdata_raw.dummy_instr_mask;
-
-    // Signal a write to the seed register
-    assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == CSR_SECURESEED);
-    assign dummy_instr_seed_o    = csr_wdata_int;
-
-  end else begin : gen_no_dummy
-    // tieoff for the unused bit
-    logic       unused_dummy_en;
-    logic [2:0] unused_dummy_mask;
-    assign unused_dummy_en   = cpuctrl_wdata_raw.dummy_instr_en;
-    assign unused_dummy_mask = cpuctrl_wdata_raw.dummy_instr_mask;
-
-    // field will always read as zero if not configured
-    assign cpuctrl_wdata.dummy_instr_en   = 1'b0;
-    assign cpuctrl_wdata.dummy_instr_mask = 3'b000;
-    assign dummy_instr_seed_en_o      = 1'b0;
-    assign dummy_instr_seed_o         = '0;
-  end
-
-  assign dummy_instr_en_o   = cpuctrl_q.dummy_instr_en;
-  assign dummy_instr_mask_o = cpuctrl_q.dummy_instr_mask;
-
-  // Generate icache enable bit
-  if (ICache) begin : gen_icache_enable
-    assign cpuctrl_wdata.icache_enable = cpuctrl_wdata_raw.icache_enable;
-  end else begin : gen_no_icache
-    // tieoff for the unused icen bit
-    logic unused_icen;
-    assign unused_icen = cpuctrl_wdata_raw.icache_enable;
-
-    // icen field will always read as zero if ICache not configured
-    assign cpuctrl_wdata.icache_enable = 1'b0;
-  end
-
-  assign cpuctrl_wdata.double_fault_seen = cpuctrl_wdata_raw.double_fault_seen;
-  assign cpuctrl_wdata.sync_exc_seen     = cpuctrl_wdata_raw.sync_exc_seen;
-
-  assign icache_enable_o = cpuctrl_q.icache_enable;
-
-  ibex_csr #(
-    .Width     ($bits(cpu_ctrl_t)),
-    .ShadowCopy(ShadowCSR),
-    .ResetValue('0)
-  ) u_cpuctrl_csr (
-    .clk_i     (clk_i),
-    .rst_ni    (rst_ni),
-    .wr_data_i ({cpuctrl_d}),
-    .wr_en_i   (cpuctrl_we),
-    .rd_data_o (cpuctrl_q),
-    .rd_error_o(cpuctrl_err)
-  );
-
-  assign csr_shadow_err_o = mstatus_err | mtvec_err | pmp_csr_err | cpuctrl_err;
+  // Removed
 
   ////////////////
   // Assertions //
   ////////////////
 
-  `ASSERT(IbexCsrOpEnRequiresAccess, csr_op_en_i |-> csr_access_i)
+  `ASSERT(CVE2CsrOpEnRequiresAccess, csr_op_en_i |-> csr_access_i)
 
 endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_csr.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_csr.sv
similarity index 98%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_csr.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_csr.sv
index 309a325f..b464bcce 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_csr.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_csr.sv
@@ -8,7 +8,7 @@
 
 `include "prim_assert.sv"
 
-module ibex_csr #(
+module cve2_csr #(
   parameter int unsigned    Width      = 32,
   parameter bit             ShadowCopy = 1'b0,
   parameter bit [Width-1:0] ResetValue = '0
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_decoder.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_decoder.sv
similarity index 94%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_decoder.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_decoder.sv
index 4b019593..5b9cbca1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_decoder.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_decoder.sv
@@ -13,11 +13,10 @@
 
 `include "prim_assert.sv"
 
-module ibex_decoder #(
+module cve2_decoder #(
   parameter bit RV32E               = 0,
-  parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
-  parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
-  parameter bit BranchTargetALU     = 0
+  parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
+  parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
 ) (
   input  logic                 clk_i,
   input  logic                 rst_ni,
@@ -31,8 +30,6 @@ module ibex_decoder #(
   output logic                 ecall_insn_o,          // syscall instr encountered
   output logic                 wfi_insn_o,            // wait for interrupt instr encountered
   output logic                 jump_set_o,            // jump taken set signal
-  input  logic                 branch_taken_i,        // registered branch decision
-  output logic                 icache_inval_o,
 
   // from IF-ID pipeline register
   input  logic                 instr_first_cycle_i,   // instruction read is in its first cycle
@@ -43,10 +40,8 @@ module ibex_decoder #(
   input  logic                 illegal_c_insn_i,      // compressed instruction decode failed
 
   // immediates
-  output ibex_pkg::imm_a_sel_e  imm_a_mux_sel_o,       // immediate selection for operand a
-  output ibex_pkg::imm_b_sel_e  imm_b_mux_sel_o,       // immediate selection for operand b
-  output ibex_pkg::op_a_sel_e   bt_a_mux_sel_o,        // branch target selection operand a
-  output ibex_pkg::imm_b_sel_e  bt_b_mux_sel_o,        // branch target selection operand b
+  output cve2_pkg::imm_a_sel_e  imm_a_mux_sel_o,       // immediate selection for operand a
+  output cve2_pkg::imm_b_sel_e  imm_b_mux_sel_o,       // immediate selection for operand b
   output logic [31:0]           imm_i_type_o,
   output logic [31:0]           imm_s_type_o,
   output logic [31:0]           imm_b_type_o,
@@ -55,7 +50,7 @@ module ibex_decoder #(
   output logic [31:0]           zimm_rs1_type_o,
 
   // register file
-  output ibex_pkg::rf_wd_sel_e rf_wdata_sel_o,   // RF write data selection
+  output cve2_pkg::rf_wd_sel_e rf_wdata_sel_o,   // RF write data selection
   output logic                 rf_we_o,          // write enable for regfile
   output logic [4:0]           rf_raddr_a_o,
   output logic [4:0]           rf_raddr_b_o,
@@ -64,10 +59,10 @@ module ibex_decoder #(
   output logic                 rf_ren_b_o,          // Instruction reads from RF addr B
 
   // ALU
-  output ibex_pkg::alu_op_e    alu_operator_o,        // ALU operation selection
-  output ibex_pkg::op_a_sel_e  alu_op_a_mux_sel_o,    // operand a selection: reg value, PC,
+  output cve2_pkg::alu_op_e    alu_operator_o,        // ALU operation selection
+  output cve2_pkg::op_a_sel_e  alu_op_a_mux_sel_o,    // operand a selection: reg value, PC,
                                                       // immediate or zero
-  output ibex_pkg::op_b_sel_e  alu_op_b_mux_sel_o,    // operand b selection: reg value or
+  output cve2_pkg::op_b_sel_e  alu_op_b_mux_sel_o,    // operand b selection: reg value or
                                                       // immediate
   output logic                 alu_multicycle_o,      // ternary bitmanip instruction
 
@@ -77,12 +72,12 @@ module ibex_decoder #(
   output logic                 mult_sel_o,            // as above but static, for data muxes
   output logic                 div_sel_o,             // as above but static, for data muxes
 
-  output ibex_pkg::md_op_e     multdiv_operator_o,
+  output cve2_pkg::md_op_e     multdiv_operator_o,
   output logic [1:0]           multdiv_signed_mode_o,
 
   // CSRs
   output logic                 csr_access_o,          // access to CSR
-  output ibex_pkg::csr_op_e    csr_op_o,              // operation to perform on CSR
+  output cve2_pkg::csr_op_e    csr_op_o,              // operation to perform on CSR
 
   // LSU
   output logic                 data_req_o,            // start transaction to data memory
@@ -97,7 +92,7 @@ module ibex_decoder #(
   output logic                 branch_in_dec_o
 );
 
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   logic        illegal_insn;
   logic        illegal_reg_rv32e;
@@ -206,7 +201,6 @@ module ibex_decoder #(
     jump_in_dec_o         = 1'b0;
     jump_set_o            = 1'b0;
     branch_in_dec_o       = 1'b0;
-    icache_inval_o        = 1'b0;
 
     multdiv_operator_o    = MD_OP_MULL;
     multdiv_signed_mode_o = 2'b00;
@@ -244,8 +238,8 @@ module ibex_decoder #(
         jump_in_dec_o      = 1'b1;
 
         if (instr_first_cycle_i) begin
-          // Calculate jump target (and store PC + 4 if BranchTargetALU is configured)
-          rf_we            = BranchTargetALU;
+          // Calculate jump target (and store PC)
+          rf_we            = 1'b0;
           jump_set_o       = 1'b1;
         end else begin
           // Calculate and store PC+4
@@ -257,8 +251,8 @@ module ibex_decoder #(
         jump_in_dec_o      = 1'b1;
 
         if (instr_first_cycle_i) begin
-          // Calculate jump target (and store PC + 4 if BranchTargetALU is configured)
-          rf_we            = BranchTargetALU;
+          // Calculate jump target (and store PC)
+          rf_we            = 1'b0;
           jump_set_o       = 1'b1;
         end else begin
           // Calculate and store PC+4
@@ -572,14 +566,12 @@ module ibex_decoder #(
             // FENCE.I is implemented as a jump to the next PC, this gives the required flushing
             // behaviour (iside prefetch buffer flushed and response to any outstanding iside
             // requests will be ignored).
-            // If present, the ICache will also be flushed.
             jump_in_dec_o   = 1'b1;
 
             rf_we           = 1'b0;
 
             if (instr_first_cycle_i) begin
               jump_set_o       = 1'b1;
-              icache_inval_o   = 1'b1;
             end
           end
           default: begin
@@ -676,10 +668,6 @@ module ibex_decoder #(
     imm_a_mux_sel_o    = IMM_A_ZERO;
     imm_b_mux_sel_o    = IMM_B_I;
 
-    bt_a_mux_sel_o     = OP_A_CURRPC;
-    bt_b_mux_sel_o     = IMM_B_I;
-
-
     opcode_alu         = opcode_e'(instr_alu[6:0]);
 
     use_rs3_d          = 1'b0;
@@ -694,13 +682,8 @@ module ibex_decoder #(
       ///////////
 
       OPCODE_JAL: begin // Jump and Link
-        if (BranchTargetALU) begin
-          bt_a_mux_sel_o = OP_A_CURRPC;
-          bt_b_mux_sel_o = IMM_B_J;
-        end
-
         // Jumps take two cycles without the BTALU
-        if (instr_first_cycle_i && !BranchTargetALU) begin
+        if (instr_first_cycle_i) begin
           // Calculate jump target
           alu_op_a_mux_sel_o  = OP_A_CURRPC;
           alu_op_b_mux_sel_o  = OP_B_IMM;
@@ -716,13 +699,8 @@ module ibex_decoder #(
       end
 
       OPCODE_JALR: begin // Jump and Link Register
-        if (BranchTargetALU) begin
-          bt_a_mux_sel_o = OP_A_REG_A;
-          bt_b_mux_sel_o = IMM_B_I;
-        end
-
         // Jumps take two cycles without the BTALU
-        if (instr_first_cycle_i && !BranchTargetALU) begin
+        if (instr_first_cycle_i) begin
           // Calculate jump target
           alu_op_a_mux_sel_o  = OP_A_REG_A;
           alu_op_b_mux_sel_o  = OP_B_IMM;
@@ -749,24 +727,18 @@ module ibex_decoder #(
           default: ;
         endcase
 
-        if (BranchTargetALU) begin
-          bt_a_mux_sel_o = OP_A_CURRPC;
-          // Not-taken branch will jump to next instruction (used in secure mode)
-          bt_b_mux_sel_o = branch_taken_i ? IMM_B_B : IMM_B_INCR_PC;
-        end
-
         // Without branch target ALU, a branch is a two-stage operation using the Main ALU in both
         // stages
         if (instr_first_cycle_i) begin
           // First evaluate the branch condition
           alu_op_a_mux_sel_o  = OP_A_REG_A;
           alu_op_b_mux_sel_o  = OP_B_REG_B;
-        end else if (!BranchTargetALU) begin
+        end else begin
           // Then calculate jump target
           alu_op_a_mux_sel_o  = OP_A_CURRPC;
           alu_op_b_mux_sel_o  = OP_B_IMM;
           // Not-taken branch will jump to next instruction (used in secure mode)
-          imm_b_mux_sel_o     = branch_taken_i ? IMM_B_B : IMM_B_INCR_PC;
+          imm_b_mux_sel_o     = IMM_B_B;
           alu_operator_o      = ALU_ADD;
         end
       end
@@ -1147,15 +1119,10 @@ module ibex_decoder #(
           end
           3'b001: begin
             // FENCE.I will flush the IF stage, prefetch buffer and ICache if present.
-            if (BranchTargetALU) begin
-              bt_a_mux_sel_o     = OP_A_CURRPC;
-              bt_b_mux_sel_o     = IMM_B_INCR_PC;
-            end else begin
               alu_op_a_mux_sel_o = OP_A_CURRPC;
               alu_op_b_mux_sel_o = OP_B_IMM;
               imm_b_mux_sel_o    = IMM_B_INCR_PC;
               alu_operator_o     = ALU_ADD;
-            end
           end
           default: ;
         endcase
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_ex_block.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_ex_block.sv
similarity index 80%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_ex_block.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_ex_block.sv
index ee900164..98713a3d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_ex_block.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_ex_block.sv
@@ -8,27 +8,21 @@
  *
  * Execution block: Hosts ALU and MUL/DIV unit
  */
-module ibex_ex_block #(
-  parameter ibex_pkg::rv32m_e RV32M           = ibex_pkg::RV32MFast,
-  parameter ibex_pkg::rv32b_e RV32B           = ibex_pkg::RV32BNone,
-  parameter bit               BranchTargetALU = 0
+module cve2_ex_block #(
+  parameter cve2_pkg::rv32m_e RV32M           = cve2_pkg::RV32MFast,
+  parameter cve2_pkg::rv32b_e RV32B           = cve2_pkg::RV32BNone
 ) (
   input  logic                  clk_i,
   input  logic                  rst_ni,
 
   // ALU
-  input  ibex_pkg::alu_op_e     alu_operator_i,
+  input  cve2_pkg::alu_op_e     alu_operator_i,
   input  logic [31:0]           alu_operand_a_i,
   input  logic [31:0]           alu_operand_b_i,
   input  logic                  alu_instr_first_cycle_i,
 
-  // Branch Target ALU
-  // All of these signals are unusued when BranchTargetALU == 0
-  input  logic [31:0]           bt_a_operand_i,
-  input  logic [31:0]           bt_b_operand_i,
-
   // Multiplier/Divider
-  input  ibex_pkg::md_op_e      multdiv_operator_i,
+  input  cve2_pkg::md_op_e      multdiv_operator_i,
   input  logic                  mult_en_i,             // dynamic enable signal, for FSM control
   input  logic                  div_en_i,              // dynamic enable signal, for FSM control
   input  logic                  mult_sel_i,            // static decoder output, for data muxes
@@ -36,8 +30,6 @@ module ibex_ex_block #(
   input  logic  [1:0]           multdiv_signed_mode_i,
   input  logic [31:0]           multdiv_operand_a_i,
   input  logic [31:0]           multdiv_operand_b_i,
-  input  logic                  multdiv_ready_id_i,
-  input  logic                  data_ind_timing_i,
 
   // intermediate val reg
   output logic [1:0]            imd_val_we_o,
@@ -53,7 +45,7 @@ module ibex_ex_block #(
   output logic                  ex_valid_o             // EX has valid output
 );
 
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   logic [31:0] alu_result, multdiv_result;
 
@@ -91,29 +83,16 @@ module ibex_ex_block #(
   // branch handling
   assign branch_decision_o  = alu_cmp_result;
 
-  if (BranchTargetALU) begin : g_branch_target_alu
-    logic [32:0] bt_alu_result;
-    logic        unused_bt_carry;
-
-    assign bt_alu_result   = bt_a_operand_i + bt_b_operand_i;
-
-    assign unused_bt_carry = bt_alu_result[32];
-    assign branch_target_o = bt_alu_result[31:0];
-  end else begin : g_no_branch_target_alu
-    // Unused bt_operand signals cause lint errors, this avoids them
-    logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
+  // Unused bt_operand signals cause lint errors, this avoids them
+  //logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
 
-    assign unused_bt_a_operand = bt_a_operand_i;
-    assign unused_bt_b_operand = bt_b_operand_i;
-
-    assign branch_target_o = alu_adder_result_ex_o;
-  end
+  assign branch_target_o = alu_adder_result_ex_o;
 
   /////////
   // ALU //
   /////////
 
-  ibex_alu #(
+  cve2_alu #(
     .RV32B(RV32B)
   ) alu_i (
     .operator_i         (alu_operator_i),
@@ -138,7 +117,7 @@ module ibex_ex_block #(
   ////////////////
 
   if (RV32M == RV32MSlow) begin : gen_multdiv_slow
-    ibex_multdiv_slow multdiv_i (
+    cve2_multdiv_slow multdiv_i (
       .clk_i             (clk_i),
       .rst_ni            (rst_ni),
       .mult_en_i         (mult_en_i),
@@ -152,18 +131,17 @@ module ibex_ex_block #(
       .alu_adder_ext_i   (alu_adder_result_ext),
       .alu_adder_i       (alu_adder_result_ex_o),
       .equal_to_zero_i   (alu_is_equal_result),
-      .data_ind_timing_i (data_ind_timing_i),
       .valid_o           (multdiv_valid),
       .alu_operand_a_o   (multdiv_alu_operand_a),
       .alu_operand_b_o   (multdiv_alu_operand_b),
       .imd_val_q_i       (imd_val_q_i),
       .imd_val_d_o       (multdiv_imd_val_d),
       .imd_val_we_o      (multdiv_imd_val_we),
-      .multdiv_ready_id_i(multdiv_ready_id_i),
+      .multdiv_ready_id_i(1'b1),
       .multdiv_result_o  (multdiv_result)
     );
   end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast
-    ibex_multdiv_fast #(
+    cve2_multdiv_fast #(
       .RV32M(RV32M)
     ) multdiv_i (
       .clk_i             (clk_i),
@@ -181,11 +159,9 @@ module ibex_ex_block #(
       .alu_adder_ext_i   (alu_adder_result_ext),
       .alu_adder_i       (alu_adder_result_ex_o),
       .equal_to_zero_i   (alu_is_equal_result),
-      .data_ind_timing_i (data_ind_timing_i),
       .imd_val_q_i       (imd_val_q_i),
       .imd_val_d_o       (multdiv_imd_val_d),
       .imd_val_we_o      (multdiv_imd_val_we),
-      .multdiv_ready_id_i(multdiv_ready_id_i),
       .valid_o           (multdiv_valid),
       .multdiv_result_o  (multdiv_result)
     );
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_fetch_fifo.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_fetch_fifo.sv
similarity index 92%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_fetch_fifo.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_fetch_fifo.sv
index 61179ed0..20b2b62b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_fetch_fifo.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_fetch_fifo.sv
@@ -12,9 +12,8 @@
 
 `include "prim_assert.sv"
 
-module ibex_fetch_fifo #(
-  parameter int unsigned NUM_REQS = 2,
-  parameter bit          ResetAll = 1'b0
+module cve2_fetch_fifo #(
+  parameter int unsigned NUM_REQS = 2
 ) (
   input  logic                clk_i,
   input  logic                rst_ni,
@@ -149,19 +148,11 @@ module ibex_fetch_fifo #(
   assign instr_addr_d = clear_i ? in_addr_i[31:1] :
                                   instr_addr_next;
 
-  if (ResetAll) begin : g_instr_addr_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        instr_addr_q <= '0;
-      end else if (instr_addr_en) begin
-        instr_addr_q <= instr_addr_d;
-      end
-    end
-  end else begin : g_instr_addr_nr
-    always_ff @(posedge clk_i) begin
-      if (instr_addr_en) begin
-        instr_addr_q <= instr_addr_d;
-      end
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      instr_addr_q <= '0;
+    end else if (instr_addr_en) begin
+      instr_addr_q <= instr_addr_d;
     end
   end
 
@@ -234,7 +225,7 @@ module ibex_fetch_fifo #(
   end
 
   for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs
-    if (ResetAll) begin : g_rdata_ra
+    begin : g_rdata
       always_ff @(posedge clk_i or negedge rst_ni) begin
         if (!rst_ni) begin
           rdata_q[i] <= '0;
@@ -244,13 +235,6 @@ module ibex_fetch_fifo #(
           err_q[i]   <= err_d[i];
         end
       end
-    end else begin : g_rdata_nr
-      always_ff @(posedge clk_i) begin
-        if (entry_en[i]) begin
-          rdata_q[i] <= rdata_d[i];
-          err_q[i]   <= err_d[i];
-        end
-      end
     end
   end
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_id_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_id_stage.sv
similarity index 60%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_id_stage.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_id_stage.sv
index 1644d072..e989ff29 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_id_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_id_stage.sv
@@ -15,20 +15,17 @@
  */
 
 `include "prim_assert.sv"
-//`include "dv_fcov_macros.svh"
+`include "dv_fcov_macros.svh"
 
-module ibex_id_stage #(
+module cve2_id_stage #(
   parameter bit               RV32E           = 0,
-  parameter ibex_pkg::rv32m_e RV32M           = ibex_pkg::RV32MFast,
-  parameter ibex_pkg::rv32b_e RV32B           = ibex_pkg::RV32BNone,
-  parameter bit               DataIndTiming   = 1'b0,
-  parameter bit               BranchTargetALU = 0,
-  parameter bit               WritebackStage  = 0,
-  parameter bit               BranchPredictor = 0
+  parameter cve2_pkg::rv32m_e RV32M           = cve2_pkg::RV32MFast,
+  parameter cve2_pkg::rv32b_e RV32B           = cve2_pkg::RV32BNone
 ) (
   input  logic                      clk_i,
   input  logic                      rst_ni,
 
+  input  logic                      fetch_enable_i,
   output logic                      ctrl_busy_o,
   output logic                      illegal_insn_o,
 
@@ -38,23 +35,19 @@ module ibex_id_stage #(
   input  logic [31:0]               instr_rdata_alu_i,     // from IF-ID pipeline registers
   input  logic [15:0]               instr_rdata_c_i,       // from IF-ID pipeline registers
   input  logic                      instr_is_compressed_i,
-  input  logic                      instr_bp_taken_i,
   output logic                      instr_req_o,
   output logic                      instr_first_cycle_id_o,
   output logic                      instr_valid_clear_o,   // kill instr in IF-ID reg
   output logic                      id_in_ready_o,         // ID stage is ready for next instr
-  output logic                      icache_inval_o,
 
   // Jumps and branches
   input  logic                      branch_decision_i,
 
   // IF and ID stage signals
   output logic                      pc_set_o,
-  output ibex_pkg::pc_sel_e         pc_mux_o,
-  output logic                      nt_branch_mispredict_o,
-  output logic [31:0]               nt_branch_addr_o,
-  output ibex_pkg::exc_pc_sel_e     exc_pc_mux_o,
-  output ibex_pkg::exc_cause_e      exc_cause_o,
+  output cve2_pkg::pc_sel_e         pc_mux_o,
+  output cve2_pkg::exc_pc_sel_e     exc_pc_mux_o,
+  output cve2_pkg::exc_cause_e      exc_cause_o,
 
   input  logic                      illegal_c_insn_i,
   input  logic                      instr_fetch_err_i,
@@ -66,7 +59,7 @@ module ibex_id_stage #(
   input  logic                      ex_valid_i,       // EX stage has valid output
   input  logic                      lsu_resp_valid_i, // LSU has valid output, or is done
   // ALU
-  output ibex_pkg::alu_op_e         alu_operator_ex_o,
+  output cve2_pkg::alu_op_e         alu_operator_ex_o,
   output logic [31:0]               alu_operand_a_ex_o,
   output logic [31:0]               alu_operand_b_ex_o,
 
@@ -75,36 +68,29 @@ module ibex_id_stage #(
   input  logic [33:0]               imd_val_d_ex_i[2],
   output logic [33:0]               imd_val_q_ex_o[2],
 
-  // Branch target ALU
-  output logic [31:0]               bt_a_operand_o,
-  output logic [31:0]               bt_b_operand_o,
-
   // MUL, DIV
   output logic                      mult_en_ex_o,
   output logic                      div_en_ex_o,
   output logic                      mult_sel_ex_o,
   output logic                      div_sel_ex_o,
-  output ibex_pkg::md_op_e          multdiv_operator_ex_o,
+  output cve2_pkg::md_op_e          multdiv_operator_ex_o,
   output logic  [1:0]               multdiv_signed_mode_ex_o,
   output logic [31:0]               multdiv_operand_a_ex_o,
   output logic [31:0]               multdiv_operand_b_ex_o,
-  output logic                      multdiv_ready_id_o,
 
   // CSR
   output logic                      csr_access_o,
-  output ibex_pkg::csr_op_e         csr_op_o,
+  output cve2_pkg::csr_op_e         csr_op_o,
   output logic                      csr_op_en_o,
   output logic                      csr_save_if_o,
   output logic                      csr_save_id_o,
-  output logic                      csr_save_wb_o,
   output logic                      csr_restore_mret_id_o,
   output logic                      csr_restore_dret_id_o,
   output logic                      csr_save_cause_o,
   output logic [31:0]               csr_mtval_o,
-  input  ibex_pkg::priv_lvl_e       priv_mode_i,
+  input  cve2_pkg::priv_lvl_e       priv_mode_i,
   input  logic                      csr_mstatus_tw_i,
   input  logic                      illegal_csr_insn_i,
-  input  logic                      data_ind_timing_i,
 
   // Interface to load store unit
   output logic                      lsu_req_o,
@@ -113,18 +99,13 @@ module ibex_id_stage #(
   output logic                      lsu_sign_ext_o,
   output logic [31:0]               lsu_wdata_o,
 
-  input  logic                      lsu_req_done_i, // Data req to LSU is complete and
-                                                    // instruction can move to writeback
-                                                    // (only relevant where writeback stage is
-                                                    // present)
-
   input  logic                      lsu_addr_incr_req_i,
   input  logic [31:0]               lsu_addr_last_i,
 
   // Interrupt signals
   input  logic                      csr_mstatus_mie_i,
   input  logic                      irq_pending_i,
-  input  ibex_pkg::irqs_t           irqs_i,
+  input  cve2_pkg::irqs_t           irqs_i,
   input  logic                      irq_nm_i,
   output logic                      nmi_mode_o,
 
@@ -133,7 +114,7 @@ module ibex_id_stage #(
 
   // Debug Signal
   output logic                      debug_mode_o,
-  output ibex_pkg::dbg_cause_e      debug_cause_o,
+  output cve2_pkg::dbg_cause_e      debug_cause_o,
   output logic                      debug_csr_save_o,
   input  logic                      debug_req_i,
   input  logic                      debug_single_step_i,
@@ -141,9 +122,6 @@ module ibex_id_stage #(
   input  logic                      debug_ebreaku_i,
   input  logic                      trigger_match_i,
 
-  // Wakeup Signal
-  output logic                      wake_from_sleep_o,
-
   // Write back signal
   input  logic [31:0]               result_ex_i,
   input  logic [31:0]               csr_rdata_i,
@@ -160,20 +138,9 @@ module ibex_id_stage #(
   output logic [4:0]                rf_waddr_id_o,
   output logic [31:0]               rf_wdata_id_o,
   output logic                      rf_we_id_o,
-  output logic                      rf_rd_a_wb_match_o,
-  output logic                      rf_rd_b_wb_match_o,
-
-  // Register write information from writeback (for resolving data hazards)
-  input  logic [4:0]                rf_waddr_wb_i,
-  input  logic [31:0]               rf_wdata_fwd_wb_i,
-  input  logic                      rf_write_wb_i,
 
   output  logic                     en_wb_o,
-  output  ibex_pkg::wb_instr_type_e instr_type_wb_o,
   output  logic                     instr_perf_count_id_o,
-  input logic                       ready_wb_i,
-  input logic                       outstanding_load_wb_i,
-  input logic                       outstanding_store_wb_i,
 
   // Performance Counters
   output logic                      perf_jump_o,    // executing a jump instr
@@ -181,12 +148,12 @@ module ibex_id_stage #(
   output logic                      perf_tbranch_o, // executing a taken branch instr
   output logic                      perf_dside_wait_o, // instruction in ID/EX is awaiting memory
                                                         // access to finish before proceeding
-  output logic                      perf_mul_wait_o,
+  output logic                      perf_wfi_wait_o,
   output logic                      perf_div_wait_o,
   output logic                      instr_id_done_o
 );
 
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   // Decoder/Controller, ID stage internal signals
   logic        illegal_insn_dec;
@@ -196,14 +163,9 @@ module ibex_id_stage #(
   logic        ecall_insn_dec;
   logic        wfi_insn_dec;
 
-  logic        wb_exception;
-  logic        id_exception;
-
   logic        branch_in_dec;
   logic        branch_set, branch_set_raw, branch_set_raw_d;
   logic        branch_jump_set_done_q, branch_jump_set_done_d;
-  logic        branch_not_set;
-  logic        branch_taken;
   logic        jump_in_dec;
   logic        jump_set_dec;
   logic        jump_set, jump_set_raw;
@@ -213,13 +175,11 @@ module ibex_id_stage #(
   logic        instr_executing;
   logic        instr_done;
   logic        controller_run;
-  logic        stall_ld_hz;
   logic        stall_mem;
   logic        stall_multdiv;
   logic        stall_branch;
   logic        stall_jump;
   logic        stall_id;
-  logic        stall_wb;
   logic        flush_id;
   logic        multicycle_done;
 
@@ -260,9 +220,6 @@ module ibex_id_stage #(
 
   logic [33:0] imd_val_q[2];
 
-  op_a_sel_e   bt_a_mux_sel;
-  imm_b_sel_e  bt_b_mux_sel;
-
   imm_a_sel_e  imm_a_mux_sel;
   imm_b_sel_e  imm_b_mux_sel, imm_b_mux_sel_dec;
 
@@ -313,75 +270,30 @@ module ibex_id_stage #(
     endcase
   end
 
-  if (BranchTargetALU) begin : g_btalu_muxes
-    // Branch target ALU operand A mux
-    always_comb begin : bt_operand_a_mux
-      unique case (bt_a_mux_sel)
-        OP_A_REG_A:  bt_a_operand_o = rf_rdata_a_fwd;
-        OP_A_CURRPC: bt_a_operand_o = pc_id_i;
-        default:     bt_a_operand_o = pc_id_i;
-      endcase
-    end
-
-    // Branch target ALU operand B mux
-    always_comb begin : bt_immediate_b_mux
-      unique case (bt_b_mux_sel)
-        IMM_B_I:         bt_b_operand_o = imm_i_type;
-        IMM_B_B:         bt_b_operand_o = imm_b_type;
-        IMM_B_J:         bt_b_operand_o = imm_j_type;
-        IMM_B_INCR_PC:   bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4;
-        default:         bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4;
-      endcase
-    end
-
-    // Reduced main ALU immediate MUX for Operand B
-    always_comb begin : immediate_b_mux
-      unique case (imm_b_mux_sel)
-        IMM_B_I:         imm_b = imm_i_type;
-        IMM_B_S:         imm_b = imm_s_type;
-        IMM_B_U:         imm_b = imm_u_type;
-        IMM_B_INCR_PC:   imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
-        IMM_B_INCR_ADDR: imm_b = 32'h4;
-        default:         imm_b = 32'h4;
-      endcase
-    end
-    `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
-        IMM_B_I,
-        IMM_B_S,
-        IMM_B_U,
-        IMM_B_INCR_PC,
-        IMM_B_INCR_ADDR})
-  end else begin : g_nobtalu
-    op_a_sel_e  unused_a_mux_sel;
-    imm_b_sel_e unused_b_mux_sel;
-
-    assign unused_a_mux_sel = bt_a_mux_sel;
-    assign unused_b_mux_sel = bt_b_mux_sel;
-    assign bt_a_operand_o   = '0;
-    assign bt_b_operand_o   = '0;
-
-    // Full main ALU immediate MUX for Operand B
-    always_comb begin : immediate_b_mux
-      unique case (imm_b_mux_sel)
-        IMM_B_I:         imm_b = imm_i_type;
-        IMM_B_S:         imm_b = imm_s_type;
-        IMM_B_B:         imm_b = imm_b_type;
-        IMM_B_U:         imm_b = imm_u_type;
-        IMM_B_J:         imm_b = imm_j_type;
-        IMM_B_INCR_PC:   imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
-        IMM_B_INCR_ADDR: imm_b = 32'h4;
-        default:         imm_b = 32'h4;
-      endcase
-    end
-    `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
-        IMM_B_I,
-        IMM_B_S,
-        IMM_B_B,
-        IMM_B_U,
-        IMM_B_J,
-        IMM_B_INCR_PC,
-        IMM_B_INCR_ADDR})
+  op_a_sel_e  unused_a_mux_sel;
+  imm_b_sel_e unused_b_mux_sel;
+
+  // Full main ALU immediate MUX for Operand B
+  always_comb begin : immediate_b_mux
+    unique case (imm_b_mux_sel)
+      IMM_B_I:         imm_b = imm_i_type;
+      IMM_B_S:         imm_b = imm_s_type;
+      IMM_B_B:         imm_b = imm_b_type;
+      IMM_B_U:         imm_b = imm_u_type;
+      IMM_B_J:         imm_b = imm_j_type;
+      IMM_B_INCR_PC:   imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
+      IMM_B_INCR_ADDR: imm_b = 32'h4;
+      default:         imm_b = 32'h4;
+    endcase
   end
+  `ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
+      IMM_B_I,
+      IMM_B_S,
+      IMM_B_B,
+      IMM_B_U,
+      IMM_B_J,
+      IMM_B_INCR_PC,
+      IMM_B_INCR_ADDR})
 
   // ALU MUX for Operand B
   assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : rf_rdata_b_fwd;
@@ -422,11 +334,10 @@ module ibex_id_stage #(
   // Decoder //
   /////////////
 
-  ibex_decoder #(
+  cve2_decoder #(
     .RV32E          (RV32E),
     .RV32M          (RV32M),
-    .RV32B          (RV32B),
-    .BranchTargetALU(BranchTargetALU)
+    .RV32B          (RV32B)
   ) decoder_i (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
@@ -439,8 +350,6 @@ module ibex_id_stage #(
     .ecall_insn_o  (ecall_insn_dec),
     .wfi_insn_o    (wfi_insn_dec),
     .jump_set_o    (jump_set_dec),
-    .branch_taken_i(branch_taken),
-    .icache_inval_o(icache_inval_o),
 
     // from IF-ID pipeline register
     .instr_first_cycle_i(instr_first_cycle),
@@ -451,8 +360,6 @@ module ibex_id_stage #(
     // immediates
     .imm_a_mux_sel_o(imm_a_mux_sel),
     .imm_b_mux_sel_o(imm_b_mux_sel_dec),
-    .bt_a_mux_sel_o (bt_a_mux_sel),
-    .bt_b_mux_sel_o (bt_b_mux_sel),
 
     .imm_i_type_o   (imm_i_type),
     .imm_s_type_o   (imm_s_type),
@@ -501,7 +408,7 @@ module ibex_id_stage #(
   );
 
   /////////////////////////////////
-  // CSR-related pipline flushes //
+  // CSR-related pipeline flushes //
   /////////////////////////////////
   always_comb begin : csr_pipeline_flushes
     csr_pipe_flush = 1'b0;
@@ -510,10 +417,15 @@ module ibex_id_stage #(
     // - When enabling interrupts, pending IRQs become visible to the controller only during
     //   the next cycle. If during that cycle the core disables interrupts again, it does not
     //   see any pending IRQs and consequently does not start to handle interrupts.
+    // - When modifying any PMP CSR, PMP check of the next instruction might get invalidated.
+    //   Hence, a pipeline flush is needed to instantiate another PMP check with the updated CSRs.
     // - When modifying debug CSRs - TODO: Check if this is really needed
     if (csr_op_en_o == 1'b1 && (csr_op_o == CSR_OP_WRITE || csr_op_o == CSR_OP_SET)) begin
-      if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS   ||
-          csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE) begin
+      if (csr_num_e'(instr_rdata_i[31:20]) == CSR_MSTATUS ||
+          csr_num_e'(instr_rdata_i[31:20]) == CSR_MIE     ||
+          csr_num_e'(instr_rdata_i[31:20]) == CSR_MSECCFG ||
+          // To catch all PMPCFG/PMPADDR registers, get the shared top most 7 bits.
+          instr_rdata_i[31:25] == 7'h1D) begin
         csr_pipe_flush = 1'b1;
       end
     end else if (csr_op_en_o == 1'b1 && csr_op_o != CSR_OP_READ) begin
@@ -532,13 +444,12 @@ module ibex_id_stage #(
 
   assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
 
-  ibex_controller #(
-    .WritebackStage (WritebackStage),
-    .BranchPredictor(BranchPredictor)
+  cve2_controller #(
   ) controller_i (
     .clk_i (clk_i),
     .rst_ni(rst_ni),
 
+    .fetch_enable_i(fetch_enable_i),
     .ctrl_busy_o(ctrl_busy_o),
 
     // decoder related signals
@@ -555,7 +466,6 @@ module ibex_id_stage #(
     .instr_i                (instr_rdata_i),
     .instr_compressed_i     (instr_rdata_c_i),
     .instr_is_compressed_i  (instr_is_compressed_i),
-    .instr_bp_taken_i       (instr_bp_taken_i),
     .instr_fetch_err_i      (instr_fetch_err_i),
     .instr_fetch_err_plus2_i(instr_fetch_err_plus2_i),
     .pc_id_i                (pc_id_i),
@@ -569,7 +479,6 @@ module ibex_id_stage #(
     .instr_req_o           (instr_req_o),
     .pc_set_o              (pc_set_o),
     .pc_mux_o              (pc_mux_o),
-    .nt_branch_mispredict_o(nt_branch_mispredict_o),
     .exc_pc_mux_o          (exc_pc_mux_o),
     .exc_cause_o           (exc_cause_o),
 
@@ -577,12 +486,8 @@ module ibex_id_stage #(
     .lsu_addr_last_i(lsu_addr_last_i),
     .load_err_i     (lsu_load_err_i),
     .store_err_i    (lsu_store_err_i),
-    .wb_exception_o (wb_exception),
-    .id_exception_o (id_exception),
-
     // jump/branch control
     .branch_set_i     (branch_set),
-    .branch_not_set_i (branch_not_set),
     .jump_set_i       (jump_set),
 
     // interrupt signals
@@ -595,7 +500,6 @@ module ibex_id_stage #(
     // CSR Controller Signals
     .csr_save_if_o        (csr_save_if_o),
     .csr_save_id_o        (csr_save_id_o),
-    .csr_save_wb_o        (csr_save_wb_o),
     .csr_restore_mret_id_o(csr_restore_mret_id_o),
     .csr_restore_dret_id_o(csr_restore_dret_id_o),
     .csr_save_cause_o     (csr_save_cause_o),
@@ -613,13 +517,8 @@ module ibex_id_stage #(
     .debug_ebreaku_i    (debug_ebreaku_i),
     .trigger_match_i    (trigger_match_i),
 
-    // Wakeup Signal
-    .wake_from_sleep_o(wake_from_sleep_o),
-
     .stall_id_i(stall_id),
-    .stall_wb_i(stall_wb),
     .flush_id_o(flush_id),
-    .ready_wb_i(ready_wb_i),
 
     // Performance Counters
     .perf_jump_o   (perf_jump_o),
@@ -659,31 +558,24 @@ module ibex_id_stage #(
   // Branch set control //
   ////////////////////////
 
-  if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct
-    // Branch set fed straight to controller with branch target ALU
-    // (condition pass/fail used same cycle as generated instruction request)
-    assign branch_set_raw      = branch_set_raw_d;
-  end else begin : g_branch_set_flop
-    // SEC_CM: CORE.DATA_REG_SW.SCA
-    // Branch set flopped without branch target ALU, or in fixed time execution mode
-    // (condition pass/fail used next cycle where branch target is calculated)
-    logic branch_set_raw_q;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        branch_set_raw_q <= 1'b0;
-      end else begin
-        branch_set_raw_q <= branch_set_raw_d;
-      end
+  // SEC_CM: CORE.DATA_REG_SW.SCA
+  // Branch set flopped without branch target ALU, or in fixed time execution mode
+  // (condition pass/fail used next cycle where branch target is calculated)
+  logic branch_set_raw_q;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      branch_set_raw_q <= 1'b0;
+    end else begin
+      branch_set_raw_q <= branch_set_raw_d;
     end
+  end
 
-    // Branches always take two cycles in fixed time execution mode, with or without the branch
-    // target ALU (to avoid a path from the branch decision into the branch target ALU operand
-    // muxing).
-    assign branch_set_raw      = (BranchTargetALU && !data_ind_timing_i) ? branch_set_raw_d :
-                                                                           branch_set_raw_q;
+  // Branches always take two cycles in fixed time execution mode, with or without the branch
+  // target ALU (to avoid a path from the branch decision into the branch target ALU operand
+  // muxing).
+  assign branch_set_raw      = branch_set_raw_q;
 
-  end
 
   // Track whether the current instruction in ID/EX has done a branch or jump set.
   assign branch_jump_set_done_d = (branch_set_raw | jump_set_raw | branch_jump_set_done_q) &
@@ -707,46 +599,6 @@ module ibex_id_stage #(
   assign jump_set        = jump_set_raw        & ~branch_jump_set_done_q;
   assign branch_set      = branch_set_raw      & ~branch_jump_set_done_q;
 
-  // Branch condition is calculated in the first cycle and flopped for use in the second cycle
-  // (only used in fixed time execution mode to determine branch destination).
-  if (DataIndTiming) begin : g_sec_branch_taken
-    // SEC_CM: CORE.DATA_REG_SW.SCA
-    logic branch_taken_q;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        branch_taken_q <= 1'b0;
-      end else begin
-        branch_taken_q <= branch_decision_i;
-      end
-    end
-
-    assign branch_taken = ~data_ind_timing_i | branch_taken_q;
-
-  end else begin : g_nosec_branch_taken
-
-    // Signal unused without fixed time execution mode - only taken branches will trigger
-    // branch_set_raw
-    assign branch_taken = 1'b1;
-
-  end
-
-  // Holding branch_set/jump_set high for more than one cycle should not cause a functional issue.
-  // However it could generate needless prefetch buffer flushes and instruction fetches. The ID/EX
-  // designs ensures that this never happens for non-predicted branches.
-  `ASSERT(NeverDoubleBranch, branch_set & ~instr_bp_taken_i |=> ~branch_set)
-  `ASSERT(NeverDoubleJump, jump_set & ~instr_bp_taken_i |=> ~jump_set)
-
-  //////////////////////////////
-  // Branch not-taken address //
-  //////////////////////////////
-
-  if (BranchPredictor) begin : g_calc_nt_addr
-    assign nt_branch_addr_o = pc_id_i + (instr_is_compressed_i ? 32'd2 : 32'd4);
-  end else begin : g_n_calc_nt_addr
-    assign nt_branch_addr_o = 32'd0;
-  end
-
   ///////////////
   // ID-EX FSM //
   ///////////////
@@ -775,7 +627,6 @@ module ibex_id_stage #(
     stall_branch            = 1'b0;
     stall_alu               = 1'b0;
     branch_set_raw_d        = 1'b0;
-    branch_not_set          = 1'b0;
     jump_set_raw            = 1'b0;
     perf_branch_o           = 1'b0;
 
@@ -784,13 +635,9 @@ module ibex_id_stage #(
         FIRST_CYCLE: begin
           unique case (1'b1)
             lsu_req_dec: begin
-              if (!WritebackStage) begin
+              begin
                 // LSU operation
                 id_fsm_d    = MULTI_CYCLE;
-              end else begin
-                if(~lsu_req_done_i) begin
-                  id_fsm_d  = MULTI_CYCLE;
-                end
               end
             end
             multdiv_en_dec: begin
@@ -808,22 +655,17 @@ module ibex_id_stage #(
               // All branches take two cycles in fixed time execution mode, regardless of branch
               // condition.
               // SEC_CM: CORE.DATA_REG_SW.SCA
-              id_fsm_d         = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i)) ?
+              id_fsm_d         = (branch_decision_i) ?
                                      MULTI_CYCLE : FIRST_CYCLE;
-              stall_branch     = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i;
-              branch_set_raw_d = (branch_decision_i | data_ind_timing_i);
-
-              if (BranchPredictor) begin
-                branch_not_set = ~branch_decision_i;
-              end
+              stall_branch     = branch_decision_i;
+              branch_set_raw_d = branch_decision_i;
 
               perf_branch_o = 1'b1;
             end
             jump_in_dec: begin
               // uncond branch operation
-              // BTALU means jumps only need one cycle
-              id_fsm_d      = BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE;
-              stall_jump    = ~BranchTargetALU;
+              id_fsm_d      = MULTI_CYCLE;
+              stall_jump    = 1'b1;
               jump_set_raw  = jump_set_dec;
             end
             alu_multicycle_dec: begin
@@ -842,7 +684,7 @@ module ibex_id_stage #(
             rf_we_raw       = rf_we_dec & ex_valid_i;
           end
 
-          if (multicycle_done & ready_wb_i) begin
+          if (multicycle_done) begin
             id_fsm_d        = FIRST_CYCLE;
           end else begin
             stall_multdiv   = multdiv_en_dec;
@@ -858,22 +700,19 @@ module ibex_id_stage #(
     end
   end
 
-  // Note for the two-stage configuration ready_wb_i is always set
-  assign multdiv_ready_id_o = ready_wb_i;
-
   `ASSERT(StallIDIfMulticycle, (id_fsm_q == FIRST_CYCLE) & (id_fsm_d == MULTI_CYCLE) |-> stall_id)
 
 
   // Stall ID/EX stage for reason that relates to instruction in ID/EX, update assertion below if
   // modifying this.
-  assign stall_id = stall_ld_hz | stall_mem | stall_multdiv | stall_jump | stall_branch |
+  assign stall_id = stall_mem | stall_multdiv | stall_jump | stall_branch |
                       stall_alu;
 
   // Generally illegal instructions have no reason to stall, however they must still stall waiting
   // for outstanding memory requests so exceptions related to them take priority over the illegal
   // instruction exception.
   `ASSERT(IllegalInsnStallMustBeMemStall, illegal_insn_o & stall_id |-> stall_mem &
-    ~(stall_ld_hz | stall_multdiv | stall_jump | stall_branch | stall_alu))
+    ~(stall_multdiv | stall_jump | stall_branch | stall_alu))
 
   assign instr_done = ~stall_id & ~flush_id & instr_executing;
 
@@ -884,119 +723,6 @@ module ibex_id_stage #(
   // Used by ALU to access RS3 if ternary instruction.
   assign instr_first_cycle_id_o = instr_first_cycle;
 
-  if (WritebackStage) begin : gen_stall_mem
-    // Register read address matches write address in WB
-    logic rf_rd_a_wb_match;
-    logic rf_rd_b_wb_match;
-    // Hazard between registers being read and written
-    logic rf_rd_a_hz;
-    logic rf_rd_b_hz;
-
-    logic outstanding_memory_access;
-
-    logic instr_kill;
-
-    assign multicycle_done = lsu_req_dec ? ~stall_mem : ex_valid_i;
-
-    // Is a memory access ongoing that isn't finishing this cycle
-    assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) &
-                                       ~lsu_resp_valid_i;
-
-    // Can start a new memory access if any previous one has finished or is finishing
-    assign data_req_allowed = ~outstanding_memory_access;
-
-    // Instruction won't execute because:
-    // - There is a pending exception in writeback
-    //   The instruction in ID/EX will be flushed and the core will jump to an exception handler
-    // - The controller isn't running instructions
-    //   This either happens in preparation for a flush and jump to an exception handler e.g. in
-    //   response to an IRQ or debug request or whilst the core is sleeping or resetting/fetching
-    //   first instruction in which case any valid instruction in ID/EX should be ignored.
-    // - There was an error on instruction fetch
-    assign instr_kill = instr_fetch_err_i |
-                        wb_exception      |
-                        id_exception      |
-                        ~controller_run;
-
-    // With writeback stage instructions must be prevented from executing if there is:
-    // - A load hazard
-    // - A pending memory access
-    //   If it receives an error response this results in a precise exception from WB so ID/EX
-    //   instruction must not execute until error response is known).
-    // - A load/store error
-    //   This will cause a precise exception for the instruction in WB so ID/EX instruction must not
-    //   execute
-    //
-    // instr_executing_spec is a speculative signal. It indicates an instruction can execute
-    // assuming there are no exceptions from writeback and any outstanding memory access won't
-    // receive an error. It is required so branch and jump requests don't factor in an incoming dmem
-    // error (that in turn would factor directly into imem requests leading to a feedthrough path).
-    //
-    // instr_executing is the full signal, it will only allow execution once any potential
-    // exceptions from writeback have been resolved.
-    assign instr_executing_spec = instr_valid_i      &
-                                  ~instr_fetch_err_i &
-                                  controller_run     &
-                                  ~stall_ld_hz;
-
-    assign instr_executing = instr_valid_i              &
-                             ~instr_kill                &
-                             ~stall_ld_hz               &
-                             ~outstanding_memory_access;
-
-    `ASSERT(IbexExecutingSpecIfExecuting, instr_executing |-> instr_executing_spec)
-
-    `ASSERT(IbexStallIfValidInstrNotExecuting,
-      instr_valid_i & ~instr_kill & ~instr_executing |-> stall_id)
-
-    `ASSERT(IbexCannotRetireWithPendingExceptions,
-      instr_done |-> ~(wb_exception | outstanding_memory_access))
-
-    // Stall for reasons related to memory:
-    // * There is an outstanding memory access that won't resolve this cycle (need to wait to allow
-    //   precise exceptions)
-    // * There is a load/store request not being granted or which is unaligned and waiting to issue
-    //   a second request (needs to stay in ID for the address calculation)
-    assign stall_mem = instr_valid_i &
-                       (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i));
-
-    // If we stall a load in ID for any reason, it must not make an LSU request
-    // (otherwide we might issue two requests for the same instruction)
-    `ASSERT(IbexStallMemNoRequest,
-      instr_valid_i & lsu_req_dec & ~instr_done |-> ~lsu_req_done_i)
-
-    assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o;
-    assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o;
-
-    assign rf_rd_a_wb_match_o = rf_rd_a_wb_match;
-    assign rf_rd_b_wb_match_o = rf_rd_b_wb_match;
-
-    // If instruction is reading register that load will be writing stall in
-    // ID until load is complete. No need to stall when reading zero register.
-    assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a;
-    assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b;
-
-    // If instruction is read register that writeback is writing forward writeback data to read
-    // data. Note this doesn't factor in load data as it arrives too late, such hazards are
-    // resolved via a stall (see above).
-    assign rf_rdata_a_fwd = rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i;
-    assign rf_rdata_b_fwd = rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i;
-
-    assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz);
-
-    assign instr_type_wb_o = ~lsu_req_dec ? WB_INSTR_OTHER :
-                              lsu_we      ? WB_INSTR_STORE :
-                                            WB_INSTR_LOAD;
-
-    assign instr_id_done_o = en_wb_o & ready_wb_i;
-
-    // Stall ID/EX as instruction in ID/EX cannot proceed to writeback yet
-    assign stall_wb = en_wb_o & ~ready_wb_i;
-
-    assign perf_dside_wait_o = instr_valid_i & ~instr_kill &
-                               (outstanding_memory_access | stall_ld_hz);
-  end else begin : gen_no_stall_mem
-
     assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i;
 
     assign data_req_allowed = instr_first_cycle;
@@ -1005,9 +731,6 @@ module ibex_id_stage #(
     // Then stall until it is complete
     assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle));
 
-    // No load hazards without Writeback Stage
-    assign stall_ld_hz   = 1'b0;
-
     // Without writeback stage any valid instruction that hasn't seen an error will execute
     assign instr_executing_spec = instr_valid_i & ~instr_fetch_err_i & controller_run;
     assign instr_executing = instr_executing_spec;
@@ -1020,60 +743,34 @@ module ibex_id_stage #(
     assign rf_rdata_a_fwd = rf_rdata_a_i;
     assign rf_rdata_b_fwd = rf_rdata_b_i;
 
-    assign rf_rd_a_wb_match_o = 1'b0;
-    assign rf_rd_b_wb_match_o = 1'b0;
-
     // Unused Writeback stage only IO & wiring
     // Assign inputs and internal wiring to unused signals to satisfy lint checks
     // Tie-off outputs to constant values
     logic unused_data_req_done_ex;
-    logic [4:0] unused_rf_waddr_wb;
-    logic unused_rf_write_wb;
-    logic unused_outstanding_load_wb;
-    logic unused_outstanding_store_wb;
-    logic unused_wb_exception;
-    logic [31:0] unused_rf_wdata_fwd_wb;
-    logic unused_id_exception;
-
-    assign unused_data_req_done_ex     = lsu_req_done_i;
-    assign unused_rf_waddr_wb          = rf_waddr_wb_i;
-    assign unused_rf_write_wb          = rf_write_wb_i;
-    assign unused_outstanding_load_wb  = outstanding_load_wb_i;
-    assign unused_outstanding_store_wb = outstanding_store_wb_i;
-    assign unused_wb_exception         = wb_exception;
-    assign unused_rf_wdata_fwd_wb      = rf_wdata_fwd_wb_i;
-    assign unused_id_exception         = id_exception;
-
-    assign instr_type_wb_o = WB_INSTR_OTHER;
-    assign stall_wb        = 1'b0;
 
     assign perf_dside_wait_o = instr_executing & lsu_req_dec & ~lsu_resp_valid_i;
 
     assign instr_id_done_o = instr_done;
-  end
 
   // Signal which instructions to count as retired in minstret, all traps along with ebrk and
   // ecall instructions are not counted.
   assign instr_perf_count_id_o = ~ebrk_insn & ~ecall_insn_dec & ~illegal_insn_dec &
       ~illegal_csr_insn_i & ~instr_fetch_err_i;
 
-  // An instruction is ready to move to the writeback stage (or retire if there is no writeback
-  // stage)
+  // An instruction is ready to move to the writeback
   assign en_wb_o = instr_done;
 
-  assign perf_mul_wait_o = stall_multdiv & mult_en_dec;
+  assign perf_wfi_wait_o = wfi_insn_dec;
   assign perf_div_wait_o = stall_multdiv & div_en_dec;
 
   //////////
   // FCOV //
   //////////
 
-  //`DV_FCOV_SIGNAL_GEN_IF(logic, rf_rd_wb_hz,
-  //  (gen_stall_mem.rf_rd_a_hz | gen_stall_mem.rf_rd_b_hz) & instr_valid_i, WritebackStage)
-  //`DV_FCOV_SIGNAL(logic, branch_taken,
-  //  instr_executing & (id_fsm_q == FIRST_CYCLE) & branch_decision_i)
-  //`DV_FCOV_SIGNAL(logic, branch_not_taken,
-  //  instr_executing & (id_fsm_q == FIRST_CYCLE) & ~branch_decision_i)
+  `DV_FCOV_SIGNAL(logic, branch_taken,
+    instr_executing & (id_fsm_q == FIRST_CYCLE) & branch_decision_i)
+  `DV_FCOV_SIGNAL(logic, branch_not_taken,
+    instr_executing & (id_fsm_q == FIRST_CYCLE) & ~branch_decision_i)
 
   ////////////////
   // Assertions //
@@ -1086,16 +783,6 @@ module ibex_id_stage #(
       OP_A_FWD,
       OP_A_CURRPC,
       OP_A_IMM})
-  `ASSERT_KNOWN_IF(IbexBTAluAOpMuxSelKnown, bt_a_mux_sel, instr_valid_i)
-  `ASSERT(IbexBTAluAOpMuxSelValid, instr_valid_i |-> bt_a_mux_sel inside {
-      OP_A_REG_A,
-      OP_A_CURRPC})
-  `ASSERT_KNOWN_IF(IbexBTAluBOpMuxSelKnown, bt_b_mux_sel, instr_valid_i)
-  `ASSERT(IbexBTAluBOpMuxSelValid, instr_valid_i |-> bt_b_mux_sel inside {
-      IMM_B_I,
-      IMM_B_B,
-      IMM_B_J,
-      IMM_B_INCR_PC})
   `ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside {
       RF_WD_EX,
       RF_WD_CSR})
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_if_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_if_stage.sv
new file mode 100644
index 00000000..cbb05054
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_if_stage.sv
@@ -0,0 +1,278 @@
+// Copyright lowRISC contributors.
+// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Instruction Fetch Stage
+ *
+ * Instruction fetch unit: Selection of the next PC, and buffering (sampling) of
+ * the read instruction.
+ */
+
+`include "prim_assert.sv"
+
+module cve2_if_stage import cve2_pkg::*; #(
+  parameter int unsigned DmHaltAddr        = 32'h1A110800,
+  parameter int unsigned DmExceptionAddr   = 32'h1A110808
+) (
+  input  logic                         clk_i,
+  input  logic                         rst_ni,
+
+  input  logic [31:0]                  boot_addr_i,              // also used for mtvec
+  input  logic                         req_i,                    // instruction request control
+
+  // instruction cache interface
+  output logic                        instr_req_o,
+  output logic [31:0]                 instr_addr_o,
+  input  logic                        instr_gnt_i,
+  input  logic                        instr_rvalid_i,
+  input  logic [31:0]                 instr_rdata_i,
+  input  logic                        instr_err_i,
+
+  // output of ID stage
+  output logic                        instr_valid_id_o,         // instr in IF-ID is valid
+  output logic                        instr_new_id_o,           // instr in IF-ID is new
+  output logic [31:0]                 instr_rdata_id_o,         // instr for ID stage
+  output logic [31:0]                 instr_rdata_alu_id_o,     // replicated instr for ID stage
+                                                                // to reduce fan-out
+  output logic [15:0]                 instr_rdata_c_id_o,       // compressed instr for ID stage
+                                                                // (mtval), meaningful only if
+                                                                // instr_is_compressed_id_o = 1'b1
+  output logic                        instr_is_compressed_id_o, // compressed decoder thinks this
+                                                                // is a compressed instr
+  output logic                        instr_fetch_err_o,        // bus error on fetch
+  output logic                        instr_fetch_err_plus2_o,  // bus error misaligned
+  output logic                        illegal_c_insn_id_o,      // compressed decoder thinks this
+                                                                // is an invalid instr
+  output logic [31:0]                 pc_if_o,
+  output logic [31:0]                 pc_id_o,
+  input  logic                        pmp_err_if_i,
+  input  logic                        pmp_err_if_plus2_i,
+
+  // control signals
+  input  logic                        instr_valid_clear_i,      // clear instr valid bit in IF-ID
+  input  logic                        pc_set_i,                 // set the PC to a new value
+  input  pc_sel_e                     pc_mux_i,                 // selector for PC multiplexer
+  input  exc_pc_sel_e                 exc_pc_mux_i,             // selects ISR address
+  input  exc_cause_e                  exc_cause,                // selects ISR address for
+                                                                // vectorized interrupt lines
+  // jump and branch target
+  input  logic [31:0]                 branch_target_ex_i,       // branch/jump target address
+
+  // CSRs
+  input  logic [31:0]                 csr_mepc_i,               // PC to restore after handling
+                                                                // the interrupt/exception
+  input  logic [31:0]                 csr_depc_i,               // PC to restore after handling
+                                                                // the debug request
+  input  logic [31:0]                 csr_mtvec_i,              // base PC to jump to on exception
+  output logic                        csr_mtvec_init_o,         // tell CS regfile to init mtvec
+
+  // pipeline stall
+  input  logic                        id_in_ready_i,            // ID stage is ready for new instr
+
+  // misc signals
+  output logic                        if_busy_o                 // IF stage is busy fetching instr
+);
+
+  logic              instr_valid_id_d, instr_valid_id_q;
+  logic              instr_new_id_d, instr_new_id_q;
+
+  // prefetch buffer related signals
+  logic              prefetch_busy;
+  logic              branch_req;
+  logic       [31:0] fetch_addr_n;
+  logic              unused_fetch_addr_n0;
+
+  logic              fetch_valid;
+  logic              fetch_ready;
+  logic       [31:0] fetch_rdata;
+  logic       [31:0] fetch_addr;
+  logic              fetch_err;
+  logic              fetch_err_plus2;
+
+  logic [31:0]       instr_decompressed;
+  logic              illegal_c_insn;
+  logic              instr_is_compressed;
+
+  logic              if_instr_pmp_err;
+  logic              if_instr_err;
+  logic              if_instr_err_plus2;
+
+  logic       [31:0] exc_pc;
+
+  logic        [6:0] irq_id;
+  logic              unused_irq_bit;
+
+  logic              if_id_pipe_reg_we; // IF-ID pipeline reg write enable
+
+  cve2_pkg::pc_sel_e pc_mux_internal;
+
+  logic        [7:0] unused_boot_addr;
+  logic        [7:0] unused_csr_mtvec;
+
+  assign unused_boot_addr = boot_addr_i[7:0];
+  assign unused_csr_mtvec = csr_mtvec_i[7:0];
+
+  // extract interrupt ID from exception cause
+  assign irq_id         = {exc_cause};
+  assign unused_irq_bit = irq_id[6];   // MSB distinguishes interrupts from exceptions
+
+  // exception PC selection mux
+  always_comb begin : exc_pc_mux
+    unique case (exc_pc_mux_i)
+      EXC_PC_EXC:     exc_pc = { csr_mtvec_i[31:8], 8'h00              };
+      EXC_PC_IRQ:     exc_pc = { csr_mtvec_i[31:8], irq_id[5:0], 2'b00 };
+      EXC_PC_DBD:     exc_pc = DmHaltAddr;
+      EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr;
+      default:        exc_pc = { csr_mtvec_i[31:8], 8'h00              };
+    endcase
+  end
+
+  assign pc_mux_internal =
+    pc_mux_i;
+
+  // fetch address selection mux
+  always_comb begin : fetch_addr_mux
+    unique case (pc_mux_internal)
+      PC_BOOT: fetch_addr_n = { boot_addr_i[31:8], 8'h00 };
+      PC_JUMP: fetch_addr_n = branch_target_ex_i;
+      PC_EXC:  fetch_addr_n = exc_pc;                       // set PC to exception handler
+      PC_ERET: fetch_addr_n = csr_mepc_i;                   // restore PC when returning from EXC
+      PC_DRET: fetch_addr_n = csr_depc_i;
+      default: fetch_addr_n = { boot_addr_i[31:8], 8'h00 };
+    endcase
+  end
+
+  // tell CS register file to initialize mtvec on boot
+  assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i;
+
+  // prefetch buffer, caches a fixed number of instructions
+  cve2_prefetch_buffer #(
+  ) prefetch_buffer_i (
+      .clk_i               ( clk_i                      ),
+      .rst_ni              ( rst_ni                     ),
+
+      .req_i               ( req_i                      ),
+
+      .branch_i            ( branch_req                 ),
+      .addr_i              ( {fetch_addr_n[31:1], 1'b0} ),
+
+      .ready_i             ( fetch_ready                ),
+      .valid_o             ( fetch_valid                ),
+      .rdata_o             ( fetch_rdata                ),
+      .addr_o              ( fetch_addr                 ),
+      .err_o               ( fetch_err                  ),
+      .err_plus2_o         ( fetch_err_plus2            ),
+
+      .instr_req_o         ( instr_req_o                ),
+      .instr_addr_o        ( instr_addr_o               ),
+      .instr_gnt_i         ( instr_gnt_i                ),
+      .instr_rvalid_i      ( instr_rvalid_i             ),
+      .instr_rdata_i       ( instr_rdata_i              ),
+      .instr_err_i         ( instr_err_i                ),
+
+      .busy_o              ( prefetch_busy              )
+  );
+
+  assign unused_fetch_addr_n0 = fetch_addr_n[0];
+
+  assign branch_req  = pc_set_i;
+
+  assign pc_if_o     = fetch_addr;
+  assign if_busy_o   = prefetch_busy;
+
+  // PMP errors
+  // An error can come from the instruction address, or the next instruction address for unaligned,
+  // uncompressed instructions.
+  assign if_instr_pmp_err = pmp_err_if_i |
+                            (fetch_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i);
+
+  // Combine bus errors and pmp errors
+  assign if_instr_err = fetch_err | if_instr_pmp_err;
+
+  // Capture the second half of the address for errors on the second part of an instruction
+  assign if_instr_err_plus2 = ((fetch_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i) |
+                               fetch_err_plus2) & ~pmp_err_if_i;
+
+  // compressed instruction decoding, or more precisely compressed instruction
+  // expander
+  //
+  // since it does not matter where we decompress instructions, we do it here
+  // to ease timing closure
+  cve2_compressed_decoder compressed_decoder_i (
+    .clk_i          (clk_i),
+    .rst_ni         (rst_ni),
+    .valid_i        (fetch_valid & ~fetch_err),
+    .instr_i        (fetch_rdata),
+    .instr_o        (instr_decompressed),
+    .is_compressed_o(instr_is_compressed),
+    .illegal_instr_o(illegal_c_insn)
+  );
+
+  // The ID stage becomes valid as soon as any instruction is registered in the ID stage flops.
+  // Note that the current instruction is squashed by the incoming pc_set_i signal.
+  // Valid is held until it is explicitly cleared (due to an instruction completing or an exception)
+  assign instr_valid_id_d = (fetch_valid & id_in_ready_i & ~pc_set_i) |
+                            (instr_valid_id_q & ~instr_valid_clear_i);
+  assign instr_new_id_d   = fetch_valid & id_in_ready_i;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      instr_valid_id_q <= 1'b0;
+      instr_new_id_q   <= 1'b0;
+    end else begin
+      instr_valid_id_q <= instr_valid_id_d;
+      instr_new_id_q   <= instr_new_id_d;
+    end
+  end
+
+  assign instr_valid_id_o = instr_valid_id_q;
+  // Signal when a new instruction enters the ID stage (only used for RVFI signalling).
+  assign instr_new_id_o   = instr_new_id_q;
+
+  // IF-ID pipeline registers, frozen when the ID stage is stalled
+  assign if_id_pipe_reg_we = instr_new_id_d;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      instr_rdata_id_o         <= '0;
+      instr_rdata_alu_id_o     <= '0;
+      instr_fetch_err_o        <= '0;
+      instr_fetch_err_plus2_o  <= '0;
+      instr_rdata_c_id_o       <= '0;
+      instr_is_compressed_id_o <= '0;
+      illegal_c_insn_id_o      <= '0;
+      pc_id_o                  <= '0;
+    end else if (if_id_pipe_reg_we) begin
+      instr_rdata_id_o         <= instr_decompressed;
+      // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
+      instr_rdata_alu_id_o     <= instr_decompressed;
+      instr_fetch_err_o        <= if_instr_err;
+      instr_fetch_err_plus2_o  <= if_instr_err_plus2;
+      instr_rdata_c_id_o       <= fetch_rdata[15:0]; //if_instr_rdata[15:0];
+      instr_is_compressed_id_o <= instr_is_compressed;
+      illegal_c_insn_id_o      <= illegal_c_insn;
+      pc_id_o                  <= pc_if_o;
+    end
+  end
+
+  assign fetch_ready = id_in_ready_i;
+
+  ////////////////
+  // Assertions //
+  ////////////////
+
+  // Selectors must be known/valid.
+  `ASSERT_KNOWN(IbexExcPcMuxKnown, exc_pc_mux_i)
+
+  // Boot address must be aligned to 256 bytes.
+  `ASSERT(IbexBootAddrUnaligned, boot_addr_i[7:0] == 8'h00)
+
+  // Address must not contain X when request is sent.
+  `ASSERT(IbexInstrAddrUnknown, instr_req_o |-> !$isunknown(instr_addr_o))
+
+  // Address must be word aligned when request is sent.
+  `ASSERT(IbexInstrAddrUnaligned, instr_req_o |-> (instr_addr_o[1:0] == 2'b00))
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_load_store_unit.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_load_store_unit.sv
similarity index 96%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_load_store_unit.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_load_store_unit.sv
index 6ec55b07..3575fadf 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_load_store_unit.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_load_store_unit.sv
@@ -12,9 +12,9 @@
  */
 
 `include "prim_assert.sv"
-//`include "dv_fcov_macros.svh"
+`include "dv_fcov_macros.svh"
 
-module ibex_load_store_unit
+module cve2_load_store_unit
 (
   input  logic         clk_i,
   input  logic         rst_ni,
@@ -50,10 +50,6 @@ module ibex_load_store_unit
                                               // -> mtval
                                               // -> AGU for misaligned accesses
 
-  output logic         lsu_req_done_o,       // Signals that data request is complete
-                                              // (only need to await final data
-                                              // response)                        -> to ID/EX
-
   output logic         lsu_resp_valid_o,     // LSU has response from transaction -> to ID/EX
 
   // exception signals
@@ -453,8 +449,6 @@ module ibex_load_store_unit
     endcase
   end
 
-  assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE);
-
   // registers for FSM
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
@@ -503,8 +497,8 @@ module ibex_load_store_unit
   // FCOV //
   //////////
 
-  //`DV_FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q)
-  //`DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
+  `DV_FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q)
+  `DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
 
   ////////////////
   // Assertions //
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_multdiv_fast.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_multdiv_fast.sv
similarity index 96%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_multdiv_fast.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_multdiv_fast.sv
index 3f0d27ac..d1d400a3 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_multdiv_fast.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_multdiv_fast.sv
@@ -14,8 +14,8 @@
 
 `include "prim_assert.sv"
 
-module ibex_multdiv_fast #(
-  parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast
+module cve2_multdiv_fast #(
+  parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast
   ) (
   input  logic             clk_i,
   input  logic             rst_ni,
@@ -23,14 +23,13 @@ module ibex_multdiv_fast #(
   input  logic             div_en_i,   // dynamic enable signal, for FSM control
   input  logic             mult_sel_i, // static decoder output, for data muxes
   input  logic             div_sel_i,  // static decoder output, for data muxes
-  input  ibex_pkg::md_op_e operator_i,
+  input  cve2_pkg::md_op_e operator_i,
   input  logic  [1:0]      signed_mode_i,
   input  logic [31:0]      op_a_i,
   input  logic [31:0]      op_b_i,
   input  logic [33:0]      alu_adder_ext_i,
   input  logic [31:0]      alu_adder_i,
   input  logic             equal_to_zero_i,
-  input  logic             data_ind_timing_i,
 
   output logic [32:0]      alu_operand_a_o,
   output logic [32:0]      alu_operand_b_o,
@@ -39,13 +38,11 @@ module ibex_multdiv_fast #(
   output logic [33:0]      imd_val_d_o[2],
   output logic [1:0]       imd_val_we_o,
 
-  input  logic             multdiv_ready_id_i,
-
   output logic [31:0]      multdiv_result_o,
   output logic             valid_o
 );
 
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   // Both multiplier variants
   logic signed [34:0] mac_res_signed;
@@ -210,7 +207,7 @@ module ibex_multdiv_fast #(
             mult_valid = 1'b0;
             mult_state_d = MULH;
           end else begin
-            mult_hold = ~multdiv_ready_id_i;
+            mult_hold = 1'b0;
           end
         end
 
@@ -229,7 +226,7 @@ module ibex_multdiv_fast #(
           mult_state_d = MULL;
           mult_valid = 1'b1;
 
-          mult_hold = ~multdiv_ready_id_i;
+          mult_hold = 1'b0;
         end
 
         default: begin
@@ -328,7 +325,7 @@ module ibex_multdiv_fast #(
 
             // Note no state transition will occur if mult_hold is set
             mult_state_d = ALBL;
-            mult_hold    = ~multdiv_ready_id_i;
+            mult_hold    = 1'b0;
           end else begin
             accum        = imd_val_q_i[0];
             mac_res_d    = mac_res;
@@ -351,7 +348,7 @@ module ibex_multdiv_fast #(
 
           // Note no state transition will occur if mult_hold is set
           mult_state_d = ALBL;
-          mult_hold    = ~multdiv_ready_id_i;
+          mult_hold    = 1'b0;
         end
         default: begin
           mult_state_d = ALBL;
@@ -424,7 +421,7 @@ module ibex_multdiv_fast #(
           // normal and will naturally return -1
           op_remainder_d = '1;
           // SEC_CM: CORE.DATA_REG_SW.SCA
-          md_state_d     = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
+          md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;
           // Record that this is a div by zero to stop the sign change at the end of the
           // division (in data_ind_timing mode).
           div_by_zero_d  = equal_to_zero_i;
@@ -435,7 +432,7 @@ module ibex_multdiv_fast #(
           // normal and will naturally return operand a
           op_remainder_d = {2'b0, op_a_i};
           // SEC_CM: CORE.DATA_REG_SW.SCA
-          md_state_d     = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
+          md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;
         end
         // 0 - B = 0 iff B == 0
         alu_operand_a_o  = {32'h0  , 1'b1};
@@ -508,7 +505,7 @@ module ibex_multdiv_fast #(
         // Hold result until ID stage is ready to accept it
         // Note no state transition will occur if div_hold is set
         md_state_d = MD_IDLE;
-        div_hold   = ~multdiv_ready_id_i;
+        div_hold   = 1'b0;
         div_valid   = 1'b1;
       end
 
@@ -530,4 +527,4 @@ module ibex_multdiv_fast #(
   `endif
 `endif
 
-endmodule // ibex_mult
+endmodule // cve2_mult
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_multdiv_slow.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_multdiv_slow.sv
similarity index 96%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_multdiv_slow.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_multdiv_slow.sv
index 214d3f59..70732cc6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_multdiv_slow.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_multdiv_slow.sv
@@ -11,7 +11,7 @@
 
 `include "prim_assert.sv"
 
-module ibex_multdiv_slow
+module cve2_multdiv_slow
 (
   input  logic             clk_i,
   input  logic             rst_ni,
@@ -19,14 +19,13 @@ module ibex_multdiv_slow
   input  logic             div_en_i,   // dynamic enable signal, for FSM control
   input  logic             mult_sel_i, // static decoder output, for data muxes
   input  logic             div_sel_i,  // static decoder output, for data muxes
-  input  ibex_pkg::md_op_e operator_i,
+  input  cve2_pkg::md_op_e operator_i,
   input  logic  [1:0]      signed_mode_i,
   input  logic [31:0]      op_a_i,
   input  logic [31:0]      op_b_i,
   input  logic [33:0]      alu_adder_ext_i,
   input  logic [31:0]      alu_adder_i,
   input  logic             equal_to_zero_i,
-  input  logic             data_ind_timing_i,
 
   output logic [32:0]      alu_operand_a_o,
   output logic [32:0]      alu_operand_b_o,
@@ -42,7 +41,7 @@ module ibex_multdiv_slow
   output logic             valid_o
 );
 
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   typedef enum logic [2:0] {
     MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH
@@ -191,7 +190,7 @@ module ibex_multdiv_slow
               op_b_shift_d   = op_b_ext >> 1;
               // Proceed with multiplication by 0/1 in data-independent time mode
               // SEC_CM: CORE.DATA_REG_SW.SCA
-              md_state_d     = (!data_ind_timing_i && ((op_b_ext >> 1) == 0)) ? MD_LAST : MD_COMP;
+              md_state_d     = ((op_b_ext >> 1) == 0) ? MD_LAST : MD_COMP;
             end
             MD_OP_MULH: begin
               op_a_shift_d   = op_a_ext;
@@ -207,7 +206,7 @@ module ibex_multdiv_slow
               // normal and will naturally return -1
               accum_window_d = {33{1'b1}};
               // SEC_CM: CORE.DATA_REG_SW.SCA
-              md_state_d     = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
+              md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;
               // Record that this is a div by zero to stop the sign change at the end of the
               // division (in data_ind_timing mode).
               div_by_zero_d  = equal_to_zero_i;
@@ -219,7 +218,7 @@ module ibex_multdiv_slow
               // normal and will naturally return operand a
               accum_window_d = op_a_ext;
               // SEC_CM: CORE.DATA_REG_SW.SCA
-              md_state_d     = (!data_ind_timing_i && equal_to_zero_i) ? MD_FINISH : MD_ABS_A;
+              md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;
             end
             default:;
           endcase
@@ -252,7 +251,7 @@ module ibex_multdiv_slow
               // Multiplication is complete once op_b is zero, unless in data_ind_timing mode where
               // the maximum possible shift-add operations will be completed regardless of op_b
               // SEC_CM: CORE.DATA_REG_SW.SCA
-              md_state_d     = ((!data_ind_timing_i && (op_b_shift_d == 0)) ||
+              md_state_d     = ((op_b_shift_d == 0) ||
                                 (multdiv_count_q == 5'd1)) ? MD_LAST : MD_COMP;
             end
             MD_OP_MULH: begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pkg.sv
similarity index 74%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pkg.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pkg.sv
index fec80fdf..6cd8f4b1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pkg.sv
@@ -6,7 +6,7 @@
 /**
  * Package with constants used by Ibex
  */
-package ibex_pkg;
+package cve2_pkg;
 
   ////////////////
   // IO Structs //
@@ -31,12 +31,6 @@ package ibex_pkg;
   // Parameter Enums //
   /////////////////////
 
-  typedef enum integer {
-    RegFileFF    = 0,
-    RegFileFPGA  = 1,
-    RegFileLatch = 2
-  } regfile_e;
-
   typedef enum integer {
     RV32MNone        = 0,
     RV32MSlow        = 1,
@@ -298,26 +292,25 @@ package ibex_pkg;
     logic        irq_software;
     logic        irq_timer;
     logic        irq_external;
-    logic [14:0] irq_fast; // 15 fast interrupts,
-                          // one interrupt is reserved for NMI (not visible through mip/mie)
+    logic [15:0] irq_fast; // 16 fast interrupts
   } irqs_t;
 
   // Exception cause
-  typedef enum logic [5:0] {
-    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 5'd03},
-    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 5'd07},
-    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 5'd11},
-    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 5'd16},
-    // EXC_CAUSE_IRQ_FAST_14     = {1'b1, 5'd30},
-    EXC_CAUSE_IRQ_NM             = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15
-    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 5'd00},
-    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01},
-    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 5'd02},
-    EXC_CAUSE_BREAKPOINT         = {1'b0, 5'd03},
-    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 5'd05},
-    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07},
-    EXC_CAUSE_ECALL_UMODE        = {1'b0, 5'd08},
-    EXC_CAUSE_ECALL_MMODE        = {1'b0, 5'd11}
+  typedef enum logic [6:0] {
+    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},
+    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},
+    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},
+    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},
+    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},
+    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},
+    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},
+    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},
+    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},
+    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},
+    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},
+    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},
+    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},
+    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}
   } exc_cause_e;
 
   // Debug cause
@@ -329,27 +322,6 @@ package ibex_pkg;
     DBG_CAUSE_STEP    = 3'h4
   } dbg_cause_e;
 
-  // ICache constants
-  parameter int unsigned ADDR_W           = 32;
-  parameter int unsigned BUS_SIZE         = 32;
-  parameter int unsigned BUS_BYTES        = BUS_SIZE/8;
-  parameter int unsigned BUS_W            = $clog2(BUS_BYTES);
-  parameter int unsigned IC_SIZE_BYTES    = 4096;
-  parameter int unsigned IC_NUM_WAYS      = 2;
-  parameter int unsigned IC_LINE_SIZE     = 64;
-  parameter int unsigned IC_LINE_BYTES    = IC_LINE_SIZE/8;
-  parameter int unsigned IC_LINE_W        = $clog2(IC_LINE_BYTES);
-  parameter int unsigned IC_NUM_LINES     = IC_SIZE_BYTES / IC_NUM_WAYS / IC_LINE_BYTES;
-  parameter int unsigned IC_LINE_BEATS    = IC_LINE_BYTES / BUS_BYTES;
-  parameter int unsigned IC_LINE_BEATS_W  = $clog2(IC_LINE_BEATS);
-  parameter int unsigned IC_INDEX_W       = $clog2(IC_NUM_LINES);
-  parameter int unsigned IC_INDEX_HI      = IC_INDEX_W + IC_LINE_W - 1;
-  parameter int unsigned IC_TAG_SIZE      = ADDR_W - IC_INDEX_W - IC_LINE_W + 1; // 1 valid bit
-  parameter int unsigned IC_OUTPUT_BEATS  = (BUS_BYTES / 2); // number of halfwords
-  // ICache Scrambling Parameters
-  parameter int unsigned SCRAMBLE_KEY_W   = 128;
-  parameter int unsigned SCRAMBLE_NONCE_W = 64;
-
   // PMP constants
   parameter int unsigned PMP_MAX_REGIONS      = 16;
   parameter int unsigned PMP_CFG_W            = 8;
@@ -391,10 +363,11 @@ package ibex_pkg;
   // CSRs
   typedef enum logic[11:0] {
     // Machine information
-    CSR_MVENDORID = 12'hF11,
-    CSR_MARCHID   = 12'hF12,
-    CSR_MIMPID    = 12'hF13,
-    CSR_MHARTID   = 12'hF14,
+    CSR_MVENDORID  = 12'hF11,
+    CSR_MARCHID    = 12'hF12,
+    CSR_MIMPID     = 12'hF13,
+    CSR_MHARTID    = 12'hF14,
+    CSR_MCONFIGPTR = 12'hF15,
 
     // Machine trap setup
     CSR_MSTATUS   = 12'h300,
@@ -402,6 +375,10 @@ package ibex_pkg;
     CSR_MIE       = 12'h304,
     CSR_MTVEC     = 12'h305,
     CSR_MCOUNTEREN= 12'h306,
+    CSR_MSTATUSH  = 12'h310,
+
+    CSR_MENVCFG   = 12'h30A,
+    CSR_MENVCFGH  = 12'h31A,
 
     // Machine trap handling
     CSR_MSCRATCH  = 12'h340,
@@ -569,52 +546,33 @@ package ibex_pkg;
   parameter int unsigned CSR_MTIX_BIT      = 7;
   parameter int unsigned CSR_MEIX_BIT      = 11;
   parameter int unsigned CSR_MFIX_BIT_LOW  = 16;
-  parameter int unsigned CSR_MFIX_BIT_HIGH = 30;
+  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;
 
   // CSR Machine Security Configuration bits
   parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;
   parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;
   parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;
 
-  // Vendor ID
-  // No JEDEC ID has been allocated to lowRISC so the value is 0 to indicate the field is not
-  // implemented
-  localparam logic [31:0] CSR_MVENDORID_VALUE  = 32'b0;
+  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'
+  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit
+  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes
+
+  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
+  parameter MARCHID = 32'd35;
 
-  // Architecture ID
-  // Top bit is unset to indicate an open source project. The lower bits are an ID allocated by the
-  // RISC-V Foundation. Note this is allocated specifically to Ibex, should significant changes be
-  // made a different architecture ID should be supplied.
-  localparam logic [31:0] CSR_MARCHID_VALUE = {1'b0, 31'd22};
+  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};
+  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;
 
   // Implementation ID
-  // 0 indicates this field is not implemeted. Ibex implementors may wish to indicate an RTL/netlist
+  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist
   // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented
   // commit).
   localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;
 
-  // These LFSR parameters have been generated with
-  // $ opentitan/util/design/gen-lfsr-seed.py --width 32 --seed 2480124384 --prefix ""
-  parameter int LfsrWidth = 32;
-  typedef logic [LfsrWidth-1:0] lfsr_seed_t;
-  typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
-  parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'hac533bf4;
-  parameter lfsr_perm_t RndCnstLfsrPermDefault = {
-    160'h1e35ecba467fd1b12e958152c04fa43878a8daed
-  };
-  parameter logic [SCRAMBLE_KEY_W-1:0]   RndCnstIbexKeyDefault =
-      128'h14e8cecae3040d5e12286bb3cc113298;
-  parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonceDefault =
-      64'hf79780bc735f3843;
-
-  // Fetch enable. Mult-bit signal used for security hardening. For non-secure implementation all
-  // bits other than the bottom bit are ignored.
-  typedef logic [3:0] fetch_enable_t;
-
-  // Note that if adjusting these parameters it is assumed the bottom bit is set for On and unset
-  // for Off. This allows the use of FetchEnableOn/FetchEnableOff to work for both secure and
-  // non-secure Ibex. If this assumption is broken the RTL that uses the fetch_enable signal within
-  // `ibex_core` may need adjusting.
-  parameter fetch_enable_t FetchEnableOn  = 4'b1001;
-  parameter fetch_enable_t FetchEnableOff = 4'b0110;
+  // Machine Configuration Pointer
+  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to
+  // alter this to point to their system specific configuration data structure.
+  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;
+
 endpackage
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pmp.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pmp.sv
similarity index 95%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pmp.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pmp.sv
index 16e806a2..b531eefd 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pmp.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pmp.sv
@@ -2,7 +2,7 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-module ibex_pmp #(
+module cve2_pmp #(
   // Granularity of NAPOT access,
   // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
   parameter int unsigned PMPGranularity = 0,
@@ -16,19 +16,19 @@ module ibex_pmp #(
   input  logic                    rst_ni,
 
   // Interface to CSRs
-  input  ibex_pkg::pmp_cfg_t      csr_pmp_cfg_i     [PMPNumRegions],
+  input  cve2_pkg::pmp_cfg_t      csr_pmp_cfg_i     [PMPNumRegions],
   input  logic [33:0]             csr_pmp_addr_i    [PMPNumRegions],
-  input  ibex_pkg::pmp_mseccfg_t  csr_pmp_mseccfg_i,
+  input  cve2_pkg::pmp_mseccfg_t  csr_pmp_mseccfg_i,
 
-  input  ibex_pkg::priv_lvl_e     priv_mode_i    [PMPNumChan],
+  input  cve2_pkg::priv_lvl_e     priv_mode_i    [PMPNumChan],
   // Access checking channels
   input  logic [33:0]             pmp_req_addr_i [PMPNumChan],
-  input  ibex_pkg::pmp_req_e      pmp_req_type_i [PMPNumChan],
+  input  cve2_pkg::pmp_req_e      pmp_req_type_i [PMPNumChan],
   output logic                    pmp_req_err_o  [PMPNumChan]
 
 );
 
-  import ibex_pkg::*;
+  import cve2_pkg::*;
 
   // Access Checking Signals
   logic [33:0]                                region_start_addr [PMPNumRegions];
@@ -177,7 +177,7 @@ module ibex_pmp #(
     assign pmp_req_err_o[c] = access_fault[c];
   end
 
-  // RLB, rule locking bypass, is only relevant to ibex_cs_registers which controls writes to the
+  // RLB, rule locking bypass, is only relevant to cve2_cs_registers which controls writes to the
   // PMP CSRs. Tie to unused signal here to prevent lint warnings.
   logic unused_csr_pmp_mseccfg_rlb;
   assign unused_csr_pmp_mseccfg_rlb = csr_pmp_mseccfg_i.rlb;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pmp_reset_default.svh b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pmp_reset_default.svh
similarity index 100%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_pmp_reset_default.svh
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pmp_reset_default.svh
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_prefetch_buffer.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_prefetch_buffer.sv
similarity index 81%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_prefetch_buffer.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_prefetch_buffer.sv
index 5b834ce2..51b1195c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_prefetch_buffer.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_prefetch_buffer.sv
@@ -9,8 +9,7 @@
  * Prefetch Buffer that caches instructions. This cuts overly long critical
  * paths to the instruction cache.
  */
-module ibex_prefetch_buffer #(
-  parameter bit ResetAll        = 1'b0
+module cve2_prefetch_buffer #(
 ) (
   input  logic        clk_i,
   input  logic        rst_ni,
@@ -18,8 +17,6 @@ module ibex_prefetch_buffer #(
   input  logic        req_i,
 
   input  logic        branch_i,
-  input  logic        branch_mispredict_i,
-  input  logic [31:0] mispredict_addr_i,
   input  logic [31:0] addr_i,
 
 
@@ -65,16 +62,12 @@ module ibex_prefetch_buffer #(
 
   logic                valid_raw;
 
-  logic                branch_or_mispredict;
-
   ////////////////////////////
   // Prefetch buffer status //
   ////////////////////////////
 
   assign busy_o = (|rdata_outstanding_q) | instr_req_o;
 
-  assign branch_or_mispredict = branch_i | branch_mispredict_i;
-
   //////////////////////////////////////////////
   // Fetch fifo - consumes addresses and data //
   //////////////////////////////////////////////
@@ -82,7 +75,7 @@ module ibex_prefetch_buffer #(
   // A branch will invalidate any previously fetched instructions.
   // Note that the FENCE.I instruction relies on this flushing behaviour on branch. If it is
   // altered the FENCE.I implementation may require changes.
-  assign fifo_clear = branch_or_mispredict;
+  assign fifo_clear = branch_i;
 
   // Reversed version of rdata_outstanding_q which can be overlaid with fifo fill state
   for (genvar i = 0; i < NUM_REQS; i++) begin : gen_rd_rev
@@ -94,9 +87,8 @@ module ibex_prefetch_buffer #(
   // Overlay the fifo fill state with the outstanding requests to see if there is space.
   assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev);
 
-  ibex_fetch_fifo #(
-    .NUM_REQS (NUM_REQS),
-    .ResetAll (ResetAll)
+  cve2_fetch_fifo #(
+    .NUM_REQS (NUM_REQS)
   ) fifo_i (
       .clk_i                 ( clk_i             ),
       .rst_ni                ( rst_ni            ),
@@ -122,7 +114,7 @@ module ibex_prefetch_buffer #(
   //////////////
 
   // Make a new request any time there is space in the FIFO, and space in the request queue
-  assign valid_new_req = req_i & (fifo_ready | branch_or_mispredict) &
+  assign valid_new_req = req_i & (fifo_ready | branch_i) &
                          ~rdata_outstanding_q[NUM_REQS-1];
 
   assign valid_req = valid_req_q | valid_new_req;
@@ -131,7 +123,7 @@ module ibex_prefetch_buffer #(
   assign valid_req_d = valid_req & ~instr_gnt_i;
 
   // Record whether an outstanding bus request is cancelled by a branch
-  assign discard_req_d = valid_req_q & (branch_or_mispredict | discard_req_q);
+  assign discard_req_d = valid_req_q & (branch_i | discard_req_q);
 
   ////////////////
   // Fetch addr //
@@ -156,52 +148,34 @@ module ibex_prefetch_buffer #(
   assign stored_addr_d = instr_addr;
 
   // CPU resets with a branch, so no need to reset these addresses
-  if (ResetAll) begin : g_stored_addr_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        stored_addr_q <= '0;
-      end else if (stored_addr_en) begin
-        stored_addr_q <= stored_addr_d;
-      end
-    end
-  end else begin : g_stored_addr_nr
-    always_ff @(posedge clk_i) begin
-      if (stored_addr_en) begin
-        stored_addr_q <= stored_addr_d;
-      end
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      stored_addr_q <= '0;
+    end else if (stored_addr_en) begin
+      stored_addr_q <= stored_addr_d;
     end
   end
   // 2. fetch_addr_q
 
   // Update on a branch or as soon as a request is issued
-  assign fetch_addr_en = branch_or_mispredict | (valid_new_req & ~valid_req_q);
+  assign fetch_addr_en = branch_i | (valid_new_req & ~valid_req_q);
 
   assign fetch_addr_d = (branch_i            ? addr_i :
-                         branch_mispredict_i ? {mispredict_addr_i[31:2], 2'b00} :
                                                {fetch_addr_q[31:2], 2'b00}) +
                         // Current address + 4
                         {{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00};
 
-  if (ResetAll) begin : g_fetch_addr_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        fetch_addr_q <= '0;
-      end else if (fetch_addr_en) begin
-        fetch_addr_q <= fetch_addr_d;
-      end
-    end
-  end else begin : g_fetch_addr_nr
-    always_ff @(posedge clk_i) begin
-      if (fetch_addr_en) begin
-        fetch_addr_q <= fetch_addr_d;
-      end
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      fetch_addr_q <= '0;
+    end else if (fetch_addr_en) begin
+      fetch_addr_q <= fetch_addr_d;
     end
   end
 
   // Address mux
   assign instr_addr = valid_req_q         ? stored_addr_q :
                       branch_i            ? addr_i :
-                      branch_mispredict_i ? mispredict_addr_i :
                                             fetch_addr_q;
 
   assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};
@@ -220,7 +194,7 @@ module ibex_prefetch_buffer #(
       // If a branch is received at any point while a request is outstanding, it must be tracked
       // to ensure we discard the data once received
       assign branch_discard_n[i]    = (valid_req & instr_gnt_i & discard_req_d) |
-                                      (branch_or_mispredict & rdata_outstanding_q[i]) |
+                                      (branch_i & rdata_outstanding_q[i]) |
                                       branch_discard_q[i];
 
     end else begin : g_reqtop
@@ -232,7 +206,7 @@ module ibex_prefetch_buffer #(
                                       rdata_outstanding_q[i];
       assign branch_discard_n[i]    = (valid_req & instr_gnt_i & discard_req_d &
                                        rdata_outstanding_q[i-1]) |
-                                      (branch_or_mispredict & rdata_outstanding_q[i]) |
+                                      (branch_i & rdata_outstanding_q[i]) |
                                       branch_discard_q[i];
     end
   end
@@ -246,7 +220,7 @@ module ibex_prefetch_buffer #(
   // Push a new entry to the FIFO once complete (and not cancelled by a branch)
   assign fifo_valid = instr_rvalid_i & ~branch_discard_q[0];
 
-  assign fifo_addr = branch_i ? addr_i : mispredict_addr_i;
+  assign fifo_addr = addr_i;
 
   ///////////////
   // Registers //
@@ -273,6 +247,6 @@ module ibex_prefetch_buffer #(
   assign instr_req_o  = valid_req;
   assign instr_addr_o = instr_addr_w_aligned;
 
-  assign valid_o = valid_raw & ~branch_mispredict_i;
+  assign valid_o = valid_raw;
 
 endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_ff.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_register_file_ff.sv
similarity index 66%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_ff.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_register_file_ff.sv
index 90b0c719..148ba225 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_ff.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_register_file_ff.sv
@@ -10,10 +10,9 @@
  * This register file is based on flip flops. Use this register file when
  * targeting FPGA synthesis or Verilator simulation.
  */
-module ibex_register_file_ff #(
+module cve2_register_file_ff #(
   parameter bit                   RV32E             = 0,
   parameter int unsigned          DataWidth         = 32,
-  parameter bit                   DummyInstructions = 0,
   parameter logic [DataWidth-1:0] WordZeroVal       = '0
 ) (
   // Clock and Reset
@@ -21,7 +20,6 @@ module ibex_register_file_ff #(
   input  logic                 rst_ni,
 
   input  logic                 test_en_i,
-  input  logic                 dummy_instr_id_i,
 
   //Read port R1
   input  logic [4:0]           raddr_a_i,
@@ -63,34 +61,8 @@ module ibex_register_file_ff #(
     end
   end
 
-  // With dummy instructions enabled, R0 behaves as a real register but will always return 0 for
-  // real instructions.
-  if (DummyInstructions) begin : g_dummy_r0
-    // SEC_CM: CTRL_FLOW.UNPREDICTABLE
-    logic                 we_r0_dummy;
-    logic [DataWidth-1:0] rf_r0_q;
-
-    // Write enable for dummy R0 register (waddr_a_i will always be 0 for dummy instructions)
-    assign we_r0_dummy = we_a_i & dummy_instr_id_i;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        rf_r0_q <= WordZeroVal;
-      end else if (we_r0_dummy) begin
-        rf_r0_q <= wdata_a_i;
-      end
-    end
-
-    // Output the dummy data for dummy instructions, otherwise R0 reads as zero
-    assign rf_reg[0] = dummy_instr_id_i ? rf_r0_q : WordZeroVal;
-
-  end else begin : g_normal_r0
-    logic unused_dummy_instr_id;
-    assign unused_dummy_instr_id = dummy_instr_id_i;
-
-    // R0 is nil
-    assign rf_reg[0] = WordZeroVal;
-  end
+  // R0 is nil
+  assign rf_reg[0] = WordZeroVal;
 
   assign rf_reg[NUM_WORDS-1:1] = rf_reg_q[NUM_WORDS-1:1];
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_sleep_unit.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_sleep_unit.sv
deleted file mode 100644
index 80388031..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_sleep_unit.sv
+++ /dev/null
@@ -1,118 +0,0 @@
-// Copyright 2020 Silicon Labs, Inc.
-//
-// This file, and derivatives thereof are licensed under the
-// Solderpad License, Version 2.0 (the "License").
-//
-// Use of this file means you agree to the terms and conditions
-// of the license and are in full compliance with the License.
-//
-// You may obtain a copy of the License at:
-//
-//     https://solderpad.org/licenses/SHL-2.0/
-//
-// Unless required by applicable law or agreed to in writing, software
-// and hardware implementations thereof distributed under the License
-// is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
-// OF ANY KIND, EITHER EXPRESSED OR IMPLIED.
-//
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-////////////////////////////////////////////////////////////////////////////////
-// Engineer:       Arjan Bink - arjan.bink@silabs.com                         //
-//                                                                            //
-// Design Name:    Sleep Unit                                                 //
-// Project Name:   CVE2                                                       //
-// Language:       SystemVerilog                                              //
-//                                                                            //
-// Description:    Sleep unit containing the instantiated clock gate which    //
-//                 provides the gated clock (clk_gated_o) for the rest        //
-//                 of the design. Forked version of cv32e40p                  //
-//                                                                            //
-//                 The clock is gated for the following scenarios:            //
-//                                                                            //
-//                 - While waiting for fetch to become enabled                //
-//                 - While blocked on a WFI (PULP_CLUSTER = 0)                //
-//                 - While clock_en_i = 0 during a p.elw (PULP_CLUSTER = 1)   //
-//                                                                            //
-//                 Sleep is signaled via core_sleep_o when:                   //
-//                 - During a WFI (except in debug)                           //
-//                                                                            //
-//                                                                            //
-////////////////////////////////////////////////////////////////////////////////
-
-module cve2_sleep_unit (
-    // Clock, reset interface
-    input  logic clk_ungated_i,  // Free running clock
-    input  logic rst_n,
-    output logic clk_gated_o,  // Gated clock
-    input  logic scan_cg_en_i,  // Enable all clock gates for testing
-
-    // Core sleep
-    output logic core_sleep_o,
-
-    // Fetch enable
-    input  logic fetch_enable_i,
-    output logic fetch_enable_o,
-
-    // Core status
-    input logic if_busy_i,
-    input logic ctrl_busy_i,
-    input logic lsu_busy_i,
-
-    // WFI wake
-    input logic wake_from_sleep_i
-);
-
-  logic fetch_enable_q;  // Sticky version of fetch_enable_i
-  logic fetch_enable_d;
-  logic core_busy_q; // Is core still busy (and requires a clock) with what needs to finish before entering sleep?
-  logic core_busy_d;
-  logic clock_en;  // Final clock enable
-
-  //////////////////////////////////////////////////////////////////////////////
-  // Sleep FSM
-  //////////////////////////////////////////////////////////////////////////////
-
-  // Make sticky version of fetch_enable_i
-  assign fetch_enable_d = fetch_enable_i ? 1'b1 : fetch_enable_q;
-
-
-  // Busy when any of the sub units is busy (typically wait for the instruction buffer to fill up)
-  assign core_busy_d = if_busy_i || ctrl_busy_i || lsu_busy_i;
-
-  // Enable the clock only after the initial fetch enable while busy or waking up to become busy
-  assign clock_en = fetch_enable_q && (wake_from_sleep_i || core_busy_q);
-
-  // Sleep only in response to WFI which leads to clock disable; debug_wfi_no_sleep_o in
-  // cv32e40p_controller determines the scenarios for which WFI can(not) cause sleep.
-  assign core_sleep_o = fetch_enable_q && !clock_en;
-
-
-  always_ff @(posedge clk_ungated_i, negedge rst_n) begin
-    if (rst_n == 1'b0) begin
-      core_busy_q    <= 1'b0;
-      fetch_enable_q <= 1'b0;
-    end else begin
-      core_busy_q    <= core_busy_d;
-      fetch_enable_q <= fetch_enable_d;
-    end
-  end
-
-  // Fetch enable for Controller
-  assign fetch_enable_o = fetch_enable_q;
-
-  // Main clock gate of CV32E40P
-  cve2_clock_gate core_clock_gate_i (
-      .clk_i       (clk_ungated_i),
-      .en_i        (clock_en),
-      .scan_cg_en_i(scan_cg_en_i),
-      .clk_o       (clk_gated_o)
-  );
-
-  //----------------------------------------------------------------------------
-  // Assertions - TODO
-  //----------------------------------------------------------------------------
-
-
-endmodule  // cve2_sleep_unit
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top.sv
new file mode 100644
index 00000000..00c38a4a
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top.sv
@@ -0,0 +1,272 @@
+// Copyright lowRISC contributors.
+// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`ifdef RISCV_FORMAL
+  `define RVFI
+`endif
+
+`include "prim_assert.sv"
+
+/**
+ * Top level module of the ibex RISC-V core
+ */
+module cve2_top import cve2_pkg::*; #(
+  parameter int unsigned MHPMCounterNum   = 0,
+  parameter int unsigned MHPMCounterWidth = 40,
+  parameter bit          RV32E            = 1'b0,
+  parameter rv32m_e      RV32M            = RV32MFast,
+  parameter int unsigned DmHaltAddr       = 32'h1A110800,
+  parameter int unsigned DmExceptionAddr  = 32'h1A110808
+) (
+  // Clock and Reset
+  input  logic                         clk_i,
+  input  logic                         rst_ni,
+
+  input  logic                         test_en_i,     // enable all clock gates for testing
+  input  prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
+
+  input  logic [31:0]                  hart_id_i,
+  input  logic [31:0]                  boot_addr_i,
+
+  // Instruction memory interface
+  output logic                         instr_req_o,
+  input  logic                         instr_gnt_i,
+  input  logic                         instr_rvalid_i,
+  output logic [31:0]                  instr_addr_o,
+  input  logic [31:0]                  instr_rdata_i,
+  input  logic                         instr_err_i,
+
+  // Data memory interface
+  output logic                         data_req_o,
+  input  logic                         data_gnt_i,
+  input  logic                         data_rvalid_i,
+  output logic                         data_we_o,
+  output logic [3:0]                   data_be_o,
+  output logic [31:0]                  data_addr_o,
+  output logic [31:0]                  data_wdata_o,
+  input  logic [31:0]                  data_rdata_i,
+  input  logic                         data_err_i,
+
+  // Interrupt inputs
+  input  logic                         irq_software_i,
+  input  logic                         irq_timer_i,
+  input  logic                         irq_external_i,
+  input  logic [15:0]                  irq_fast_i,
+  input  logic                         irq_nm_i,       // non-maskeable interrupt
+
+  // Debug Interface
+  input  logic                         debug_req_i,
+  output crash_dump_t                  crash_dump_o,
+
+  // RISC-V Formal Interface
+  // Does not comply with the coding standards of _i/_o suffixes, but follows
+  // the convention of RISC-V Formal Interface Specification.
+`ifdef RVFI
+  output logic                         rvfi_valid,
+  output logic [63:0]                  rvfi_order,
+  output logic [31:0]                  rvfi_insn,
+  output logic                         rvfi_trap,
+  output logic                         rvfi_halt,
+  output logic                         rvfi_intr,
+  output logic [ 1:0]                  rvfi_mode,
+  output logic [ 1:0]                  rvfi_ixl,
+  output logic [ 4:0]                  rvfi_rs1_addr,
+  output logic [ 4:0]                  rvfi_rs2_addr,
+  output logic [ 4:0]                  rvfi_rs3_addr,
+  output logic [31:0]                  rvfi_rs1_rdata,
+  output logic [31:0]                  rvfi_rs2_rdata,
+  output logic [31:0]                  rvfi_rs3_rdata,
+  output logic [ 4:0]                  rvfi_rd_addr,
+  output logic [31:0]                  rvfi_rd_wdata,
+  output logic [31:0]                  rvfi_pc_rdata,
+  output logic [31:0]                  rvfi_pc_wdata,
+  output logic [31:0]                  rvfi_mem_addr,
+  output logic [ 3:0]                  rvfi_mem_rmask,
+  output logic [ 3:0]                  rvfi_mem_wmask,
+  output logic [31:0]                  rvfi_mem_rdata,
+  output logic [31:0]                  rvfi_mem_wdata,
+  output logic [31:0]                  rvfi_ext_mip,
+  output logic                         rvfi_ext_nmi,
+  output logic                         rvfi_ext_debug_req,
+  output logic [63:0]                  rvfi_ext_mcycle,
+`endif
+
+  // CPU Control Signals
+  input  logic                         fetch_enable_i,
+  output logic                         core_sleep_o
+);
+
+  // Scrambling Parameter
+  localparam int unsigned NumAddrScrRounds  = 0;
+
+  // Physical Memory Protection
+  localparam bit          PMPEnable        = 1'b0;
+  localparam int unsigned PMPGranularity   = 0;
+  localparam int unsigned PMPNumRegions    = 4;
+
+  // Trigger support
+  localparam bit          DbgTriggerEn     = 1'b1;
+  localparam int unsigned DbgHwBreakNum    = 1;
+
+  // Bit manipulation extension
+  localparam rv32b_e      RV32B            = RV32BNone;
+
+  // Clock signals
+  logic                        clk;
+  logic                        core_busy_d, core_busy_q;
+  logic                        clock_en;
+  logic                        fetch_enable_d, fetch_enable_q;
+  logic                        irq_pending;
+
+  /////////////////////
+  // Main clock gate //
+  /////////////////////
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      core_busy_q <= 1'b0;
+      fetch_enable_q <= 1'b0;
+    end else begin
+      core_busy_q <= core_busy_d;
+      fetch_enable_q <= fetch_enable_d;
+    end
+  end
+
+  assign clock_en = fetch_enable_q & (core_busy_q | debug_req_i | irq_pending | irq_nm_i);
+  assign core_sleep_o = fetch_enable_q & !clock_en;
+  assign fetch_enable_d = fetch_enable_i ? 1'b1 : fetch_enable_q;
+
+  cve2_clock_gate core_clock_gate_i (
+    .clk_i    (clk_i),
+    .en_i     (clock_en),
+    .scan_cg_en_i(test_en_i),
+    .clk_o    (clk)
+  );
+
+  ////////////////////////
+  // Core instantiation //
+  ////////////////////////
+
+  cve2_core #(
+    .PMPEnable        (PMPEnable),
+    .PMPGranularity   (PMPGranularity),
+    .PMPNumRegions    (PMPNumRegions),
+    .MHPMCounterNum   (MHPMCounterNum),
+    .MHPMCounterWidth (MHPMCounterWidth),
+    .RV32E            (RV32E),
+    .RV32M            (RV32M),
+    .RV32B            (RV32B),
+    .DbgTriggerEn     (DbgTriggerEn),
+    .DbgHwBreakNum    (DbgHwBreakNum),
+    .DmHaltAddr       (DmHaltAddr),
+    .DmExceptionAddr  (DmExceptionAddr)
+  ) u_cve2_core (
+    .clk_i(clk),
+    .rst_ni,
+    .test_en_i,
+
+    .hart_id_i,
+    .boot_addr_i,
+
+    .instr_req_o,
+    .instr_gnt_i,
+    .instr_rvalid_i,
+    .instr_addr_o,
+    .instr_rdata_i,
+    .instr_err_i,
+
+    .data_req_o,
+    .data_gnt_i,
+    .data_rvalid_i,
+    .data_we_o,
+    .data_be_o,
+    .data_addr_o,
+    .data_wdata_o,
+    .data_rdata_i,
+    .data_err_i,
+
+    .irq_software_i,
+    .irq_timer_i,
+    .irq_external_i,
+    .irq_fast_i,
+    .irq_nm_i,
+    .irq_pending_o(irq_pending),
+
+    .debug_req_i,
+    .crash_dump_o,
+
+`ifdef RVFI
+    .rvfi_valid,
+    .rvfi_order,
+    .rvfi_insn,
+    .rvfi_trap,
+    .rvfi_halt,
+    .rvfi_intr,
+    .rvfi_mode,
+    .rvfi_ixl,
+    .rvfi_rs1_addr,
+    .rvfi_rs2_addr,
+    .rvfi_rs3_addr,
+    .rvfi_rs1_rdata,
+    .rvfi_rs2_rdata,
+    .rvfi_rs3_rdata,
+    .rvfi_rd_addr,
+    .rvfi_rd_wdata,
+    .rvfi_pc_rdata,
+    .rvfi_pc_wdata,
+    .rvfi_mem_addr,
+    .rvfi_mem_rmask,
+    .rvfi_mem_wmask,
+    .rvfi_mem_rdata,
+    .rvfi_mem_wdata,
+    .rvfi_ext_mip,
+    .rvfi_ext_nmi,
+    .rvfi_ext_debug_req,
+    .rvfi_ext_mcycle,
+`endif
+
+    .fetch_enable_i (fetch_enable_q),
+    .core_busy_o    (core_busy_d)
+  );
+
+  ////////////////////////
+  // Rams Instantiation //
+  ////////////////////////
+
+  prim_ram_1p_pkg::ram_1p_cfg_t unused_ram_cfg;
+  logic unused_ram_inputs;
+
+  assign unused_ram_cfg    = ram_cfg_i;
+  assign unused_ram_inputs = (|NumAddrScrRounds);
+
+
+  // X checks for top-level outputs
+  `ASSERT_KNOWN(IbexInstrReqX, instr_req_o)
+  `ASSERT_KNOWN_IF(IbexInstrReqPayloadX, instr_addr_o, instr_req_o)
+
+  `ASSERT_KNOWN(IbexDataReqX, data_req_o)
+  `ASSERT_KNOWN_IF(IbexDataReqPayloadX,
+    {data_we_o, data_be_o, data_addr_o, data_wdata_o}, data_req_o)
+
+  `ASSERT_KNOWN(IbexCoreSleepX, core_sleep_o)
+
+  // X check for top-level inputs
+  `ASSERT_KNOWN(IbexTestEnX, test_en_i)
+  `ASSERT_KNOWN(IbexRamCfgX, ram_cfg_i)
+  `ASSERT_KNOWN(IbexHartIdX, hart_id_i)
+  `ASSERT_KNOWN(IbexBootAddrX, boot_addr_i)
+
+  `ASSERT_KNOWN(IbexInstrGntX, instr_gnt_i)
+  `ASSERT_KNOWN(IbexInstrRValidX, instr_rvalid_i)
+  `ASSERT_KNOWN_IF(IbexInstrRPayloadX,
+    {instr_rdata_i, instr_err_i}, instr_rvalid_i)
+
+  `ASSERT_KNOWN(IbexDataGntX, data_gnt_i)
+  `ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i)
+
+  `ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i})
+
+  `ASSERT_KNOWN(IbexDebugReqX, debug_req_i)
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_top_tracing.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top_tracing.sv
similarity index 66%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_top_tracing.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top_tracing.sv
index f4384653..989e83d7 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_top_tracing.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top_tracing.sv
@@ -3,30 +3,15 @@
 // SPDX-License-Identifier: Apache-2.0
 
 /**
- * Top level module of the ibex RISC-V core with tracing enabled
+ * Top level module of the cve2 RISC-V core with tracing enabled
  */
 
-module ibex_top_tracing import ibex_pkg::*; #(
-  parameter bit          PMPEnable        = 1'b0,
-  parameter int unsigned PMPGranularity   = 0,
-  parameter int unsigned PMPNumRegions    = 4,
+module cve2_top_tracing import cve2_pkg::*; #(
   parameter int unsigned MHPMCounterNum   = 0,
   parameter int unsigned MHPMCounterWidth = 40,
   parameter bit          RV32E            = 1'b0,
   parameter rv32m_e      RV32M            = RV32MFast,
-  parameter rv32b_e      RV32B            = RV32BNone,
-  parameter regfile_e    RegFile          = RegFileFF,
-  parameter bit          BranchTargetALU  = 1'b0,
-  parameter bit          WritebackStage   = 1'b0,
-  parameter bit          ICache           = 1'b0,
-  parameter bit          ICacheECC        = 1'b0,
   parameter bit          BranchPredictor  = 1'b0,
-  parameter bit          DbgTriggerEn     = 1'b0,
-  parameter int unsigned DbgHwBreakNum    = 1,
-  parameter bit          SecureIbex       = 1'b0,
-  parameter bit          ICacheScramble   = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed  = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm  = RndCnstLfsrPermDefault,
   parameter int unsigned DmHaltAddr       = 32'h1A110800,
   parameter int unsigned DmExceptionAddr  = 32'h1A110808
 ) (
@@ -35,7 +20,6 @@ module ibex_top_tracing import ibex_pkg::*; #(
   input  logic                         rst_ni,
 
   input  logic                         test_en_i,     // enable all clock gates for testing
-  input  logic                         scan_rst_ni,
   input  prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
 
 
@@ -48,7 +32,6 @@ module ibex_top_tracing import ibex_pkg::*; #(
   input  logic                         instr_rvalid_i,
   output logic [31:0]                  instr_addr_o,
   input  logic [31:0]                  instr_rdata_i,
-  input  logic [6:0]                   instr_rdata_intg_i,
   input  logic                         instr_err_i,
 
   // Data memory interface
@@ -59,39 +42,27 @@ module ibex_top_tracing import ibex_pkg::*; #(
   output logic [3:0]                   data_be_o,
   output logic [31:0]                  data_addr_o,
   output logic [31:0]                  data_wdata_o,
-  output logic [6:0]                   data_wdata_intg_o,
   input  logic [31:0]                  data_rdata_i,
-  input  logic [6:0]                   data_rdata_intg_i,
   input  logic                         data_err_i,
 
   // Interrupt inputs
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
   input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
+  input  logic [15:0]                  irq_fast_i,
   input  logic                         irq_nm_i,       // non-maskeable interrupt
 
-  // Scrambling Interface
-  input  logic                         scramble_key_valid_i,
-  input  logic [SCRAMBLE_KEY_W-1:0]    scramble_key_i,
-  input  logic [SCRAMBLE_NONCE_W-1:0]  scramble_nonce_i,
-  output logic                         scramble_req_o,
-
   // Debug Interface
   input  logic                         debug_req_i,
   output crash_dump_t                  crash_dump_o,
-  output logic                         double_fault_seen_o,
 
   // CPU Control Signals
-  input  fetch_enable_t                fetch_enable_i,
-  output logic                         alert_minor_o,
-  output logic                         alert_major_internal_o,
-  output logic                         alert_major_bus_o,
+  input  logic                         fetch_enable_i,
   output logic                         core_sleep_o
 
 );
 
-  // ibex_tracer relies on the signals from the RISC-V Formal Interface
+  // cve2_tracer relies on the signals from the RISC-V Formal Interface
   `ifndef RVFI
     $fatal("Fatal error: RVFI needs to be defined globally.");
   `endif
@@ -136,35 +107,19 @@ module ibex_top_tracing import ibex_pkg::*; #(
   assign unused_rvfi_ext_debug_req = rvfi_ext_debug_req;
   assign unused_rvfi_ext_mcycle = rvfi_ext_mcycle;
 
-  ibex_top #(
-    .PMPEnable        ( PMPEnable        ),
-    .PMPGranularity   ( PMPGranularity   ),
-    .PMPNumRegions    ( PMPNumRegions    ),
+  cve2_top #(
     .MHPMCounterNum   ( MHPMCounterNum   ),
     .MHPMCounterWidth ( MHPMCounterWidth ),
     .RV32E            ( RV32E            ),
     .RV32M            ( RV32M            ),
-    .RV32B            ( RV32B            ),
-    .RegFile          ( RegFile          ),
-    .BranchTargetALU  ( BranchTargetALU  ),
-    .ICache           ( ICache           ),
-    .ICacheECC        ( ICacheECC        ),
     .BranchPredictor  ( BranchPredictor  ),
-    .DbgTriggerEn     ( DbgTriggerEn     ),
-    .DbgHwBreakNum    ( DbgHwBreakNum    ),
-    .WritebackStage   ( WritebackStage   ),
-    .SecureIbex       ( SecureIbex       ),
-    .ICacheScramble   ( ICacheScramble   ),
-    .RndCnstLfsrSeed  ( RndCnstLfsrSeed  ),
-    .RndCnstLfsrPerm  ( RndCnstLfsrPerm  ),
     .DmHaltAddr       ( DmHaltAddr       ),
     .DmExceptionAddr  ( DmExceptionAddr  )
-  ) u_ibex_top (
+  ) u_cve2_top (
     .clk_i,
     .rst_ni,
 
     .test_en_i,
-    .scan_rst_ni,
     .ram_cfg_i,
 
     .hart_id_i,
@@ -175,7 +130,6 @@ module ibex_top_tracing import ibex_pkg::*; #(
     .instr_rvalid_i,
     .instr_addr_o,
     .instr_rdata_i,
-    .instr_rdata_intg_i,
     .instr_err_i,
 
     .data_req_o,
@@ -185,9 +139,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
     .data_be_o,
     .data_addr_o,
     .data_wdata_o,
-    .data_wdata_intg_o,
     .data_rdata_i,
-    .data_rdata_intg_i,
     .data_err_i,
 
     .irq_software_i,
@@ -196,14 +148,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
     .irq_fast_i,
     .irq_nm_i,
 
-    .scramble_key_valid_i,
-    .scramble_key_i,
-    .scramble_nonce_i,
-    .scramble_req_o,
-
     .debug_req_i,
     .crash_dump_o,
-    .double_fault_seen_o,
 
     .rvfi_valid,
     .rvfi_order,
@@ -234,14 +180,11 @@ module ibex_top_tracing import ibex_pkg::*; #(
     .rvfi_ext_mcycle,
 
     .fetch_enable_i,
-    .alert_minor_o,
-    .alert_major_internal_o,
-    .alert_major_bus_o,
     .core_sleep_o
   );
 
-  ibex_tracer
-  u_ibex_tracer (
+  cve2_tracer
+  u_cve2_tracer (
     .clk_i,
     .rst_ni,
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_tracer.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_tracer.sv
similarity index 98%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_tracer.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_tracer.sv
index bd36a214..707419e4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_tracer.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_tracer.sv
@@ -12,12 +12,12 @@
  * All traced instructions are written to a log file. By default, the log file is named
  * trace_core_<HARTID>.log, with <HARTID> being the 8 digit hart ID of the core being traced.
  *
- * The file name base, defaulting to "trace_core" can be set using the "ibex_tracer_file_base"
- * plusarg passed to the simulation, e.g. "+ibex_tracer_file_base=ibex_my_trace". The exact syntax
+ * The file name base, defaulting to "trace_core" can be set using the "cve2_tracer_file_base"
+ * plusarg passed to the simulation, e.g. "+cve2_tracer_file_base=cve2_my_trace". The exact syntax
  * of passing plusargs to a simulation depends on the simulator.
  *
  * The creation of the instruction trace is enabled by default but can be disabled for a simulation.
- * This behaviour is controlled by the plusarg "ibex_tracer_enable". Use "ibex_tracer_enable=0" to
+ * This behaviour is controlled by the plusarg "cve2_tracer_enable". Use "cve2_tracer_enable=0" to
  * disable the tracer.
  *
  * The trace contains six columns, separated by tabs:
@@ -34,7 +34,7 @@
  * to the one produced by objdump. This simplifies the correlation between the static program
  * information from the objdump-generated disassembly, and the runtime information from this tracer.
  */
-module ibex_tracer (
+module cve2_tracer (
   input logic        clk_i,
   input logic        rst_ni,
 
@@ -79,7 +79,7 @@ module ibex_tracer (
   logic [ 1:0] unused_rvfi_mode = rvfi_mode;
   logic [ 1:0] unused_rvfi_ixl = rvfi_ixl;
 
-  import ibex_tracer_pkg::*;
+  import cve2_tracer_pkg::*;
 
   int          file_handle;
   string       file_name;
@@ -98,7 +98,7 @@ module ibex_tracer (
 
   logic trace_log_enable;
   initial begin
-    if ($value$plusargs("ibex_tracer_enable=%b", trace_log_enable)) begin
+    if ($value$plusargs("cve2_tracer_enable=%b", trace_log_enable)) begin
       if (trace_log_enable == 1'b0) begin
         $display("%m: Instruction trace disabled.");
       end
@@ -112,7 +112,7 @@ module ibex_tracer (
 
     if (file_handle == 32'h0) begin
       string file_name_base = "trace_core";
-      void'($value$plusargs("ibex_tracer_file_base=%s", file_name_base));
+      void'($value$plusargs("cve2_tracer_file_base=%s", file_name_base));
       $sformat(file_name, "%s_%h.log", file_name_base, hart_id_i);
 
       $display("%m: Writing execution trace to %s", file_name);
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_tracer_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_tracer_pkg.sv
similarity index 99%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_tracer_pkg.sv
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_tracer_pkg.sv
index 6dbbfc90..700dd37b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_tracer_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_tracer_pkg.sv
@@ -3,8 +3,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-package ibex_tracer_pkg;
-  import ibex_pkg::*;
+package cve2_tracer_pkg;
+  import cve2_pkg::*;
 
   parameter logic [1:0] OPCODE_C0 = 2'b00;
   parameter logic [1:0] OPCODE_C1 = 2'b01;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_wb.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_wb.sv
new file mode 100644
index 00000000..dee73f74
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_wb.sv
@@ -0,0 +1,69 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Writeback passthrough
+ *
+ * The writeback stage is not present therefore this module acts as
+ * a simple passthrough to write data direct to the register file.
+ */
+
+`include "prim_assert.sv"
+`include "dv_fcov_macros.svh"
+
+module cve2_wb #(
+) (
+  input  logic                     clk_i,
+  input  logic                     rst_ni,
+  input  logic                     en_wb_i,
+
+  input  logic                     instr_is_compressed_id_i,
+  input  logic                     instr_perf_count_id_i,
+
+  output logic                     perf_instr_ret_wb_o,
+  output logic                     perf_instr_ret_compressed_wb_o,
+
+  input  logic [4:0]               rf_waddr_id_i,
+  input  logic [31:0]              rf_wdata_id_i,
+  input  logic                     rf_we_id_i,
+
+  input  logic [31:0]              rf_wdata_lsu_i,
+  input  logic                     rf_we_lsu_i,
+
+  output logic [4:0]               rf_waddr_wb_o,
+  output logic [31:0]              rf_wdata_wb_o,
+  output logic                     rf_we_wb_o,
+
+  input logic                      lsu_resp_valid_i,
+  input logic                      lsu_resp_err_i
+);
+
+  import cve2_pkg::*;
+
+  // 0 == RF write from ID
+  // 1 == RF write from LSU
+  logic [31:0] rf_wdata_wb_mux    [2];
+  logic [1:0]  rf_wdata_wb_mux_we;
+
+    // without writeback stage just pass through register write signals
+    assign rf_waddr_wb_o         = rf_waddr_id_i;
+    assign rf_wdata_wb_mux[0]    = rf_wdata_id_i;
+    assign rf_wdata_wb_mux_we[0] = rf_we_id_i;
+
+    // Increment instruction retire counters for valid instructions which are not lsu errors.
+    assign perf_instr_ret_wb_o                 = instr_perf_count_id_i & en_wb_i &
+                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);
+    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & instr_is_compressed_id_i;
+
+  assign rf_wdata_wb_mux[1]    = rf_wdata_lsu_i;
+  assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
+
+  // RF write data can come from ID results (all RF writes that aren't because of loads will come
+  // from here) or the LSU (RF writes for load data)
+  assign rf_wdata_wb_o = ({32{rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) |
+                         ({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
+  assign rf_we_wb_o    = |rf_wdata_wb_mux_we;
+
+  `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_core.f b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_core.f
deleted file mode 100644
index 83e8396b..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_core.f
+++ /dev/null
@@ -1,17 +0,0 @@
-ibex_pkg.sv
-ibex_alu.sv
-ibex_compressed_decoder.sv
-ibex_controller.sv
-ibex_counter.sv
-ibex_cs_registers.sv
-ibex_decoder.sv
-ibex_ex_block.sv
-ibex_id_stage.sv
-ibex_if_stage.sv
-ibex_load_store_unit.sv
-ibex_multdiv_slow.sv
-ibex_multdiv_fast.sv
-ibex_prefetch_buffer.sv
-ibex_fetch_fifo.sv
-ibex_register_file_ff.sv
-ibex_core.sv
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_dummy_instr.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_dummy_instr.sv
deleted file mode 100644
index ba33adc4..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_dummy_instr.sv
+++ /dev/null
@@ -1,150 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-/**
- * Dummy instruction module
- *
- * Provides pseudo-randomly inserted fake instructions for secure code obfuscation
- */
-
-// SEC_CM: CTRL_FLOW.UNPREDICTABLE
-module ibex_dummy_instr import ibex_pkg::*; #(
-    parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
-    parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
-) (
-  // Clock and reset
-  input  logic        clk_i,
-  input  logic        rst_ni,
-
-  // Interface to CSRs
-  input  logic        dummy_instr_en_i,
-  input  logic [2:0]  dummy_instr_mask_i,
-  input  logic        dummy_instr_seed_en_i,
-  input  logic [31:0] dummy_instr_seed_i,
-
-  // Interface to IF stage
-  input  logic        fetch_valid_i,
-  input  logic        id_in_ready_i,
-  output logic        insert_dummy_instr_o,
-  output logic [31:0] dummy_instr_data_o
-);
-
-  localparam int unsigned TIMEOUT_CNT_W = 5;
-  localparam int unsigned OP_W          = 5;
-
-  typedef enum logic [1:0] {
-    DUMMY_ADD = 2'b00,
-    DUMMY_MUL = 2'b01,
-    DUMMY_DIV = 2'b10,
-    DUMMY_AND = 2'b11
-  } dummy_instr_e;
-
-  typedef struct packed {
-    dummy_instr_e             instr_type;
-    logic [OP_W-1:0]          op_b;
-    logic [OP_W-1:0]          op_a;
-    logic [TIMEOUT_CNT_W-1:0] cnt;
-  } lfsr_data_t;
-  localparam int unsigned LFSR_OUT_W = $bits(lfsr_data_t);
-
-  lfsr_data_t               lfsr_data;
-  logic [TIMEOUT_CNT_W-1:0] dummy_cnt_incr, dummy_cnt_threshold;
-  logic [TIMEOUT_CNT_W-1:0] dummy_cnt_d, dummy_cnt_q;
-  logic                     dummy_cnt_en;
-  logic                     lfsr_en;
-  logic [LFSR_OUT_W-1:0]    lfsr_state;
-  logic                     insert_dummy_instr;
-  logic [6:0]               dummy_set;
-  logic [2:0]               dummy_opcode;
-  logic [31:0]              dummy_instr;
-  logic [31:0]              dummy_instr_seed_q, dummy_instr_seed_d;
-
-  // Shift the LFSR every time we insert an instruction
-  assign lfsr_en = insert_dummy_instr & id_in_ready_i;
-
-  assign dummy_instr_seed_d = dummy_instr_seed_q ^ dummy_instr_seed_i;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      dummy_instr_seed_q <= '0;
-    end else if (dummy_instr_seed_en_i) begin
-      dummy_instr_seed_q <= dummy_instr_seed_d;
-    end
-  end
-
-  prim_lfsr #(
-      .LfsrDw      ( LfsrWidth       ),
-      .StateOutDw  ( LFSR_OUT_W      ),
-      .DefaultSeed ( RndCnstLfsrSeed ),
-      .StatePermEn ( 1'b1            ),
-      .StatePerm   ( RndCnstLfsrPerm )
-  ) lfsr_i (
-      .clk_i     ( clk_i                 ),
-      .rst_ni    ( rst_ni                ),
-      .seed_en_i ( dummy_instr_seed_en_i ),
-      .seed_i    ( dummy_instr_seed_d    ),
-      .lfsr_en_i ( lfsr_en               ),
-      .entropy_i ( '0                    ),
-      .state_o   ( lfsr_state            )
-  );
-
-  // Extract fields from LFSR
-  assign lfsr_data = lfsr_data_t'(lfsr_state);
-
-  // Set count threshold for inserting a new instruction. This is the pseudo-random value from the
-  // LFSR with a mask applied (based on CSR config data) to shorten the period if required.
-  assign dummy_cnt_threshold = lfsr_data.cnt & {dummy_instr_mask_i,{TIMEOUT_CNT_W-3{1'b1}}};
-  assign dummy_cnt_incr      = dummy_cnt_q + {{TIMEOUT_CNT_W-1{1'b0}},1'b1};
-  // Clear the counter everytime a new instruction is inserted
-  assign dummy_cnt_d         = insert_dummy_instr ? '0 : dummy_cnt_incr;
-  // Increment the counter for each executed instruction while dummy instuctions are
-  // enabled.
-  assign dummy_cnt_en        = dummy_instr_en_i & id_in_ready_i &
-                               (fetch_valid_i | insert_dummy_instr);
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      dummy_cnt_q <= '0;
-    end else if (dummy_cnt_en) begin
-      dummy_cnt_q <= dummy_cnt_d;
-    end
-  end
-
-  // Insert a dummy instruction each time the counter hits the threshold
-  assign insert_dummy_instr = dummy_instr_en_i & (dummy_cnt_q == dummy_cnt_threshold);
-
-  // Encode instruction
-  always_comb begin
-    unique case (lfsr_data.instr_type)
-      DUMMY_ADD: begin
-        dummy_set    = 7'b0000000;
-        dummy_opcode = 3'b000;
-      end
-      DUMMY_MUL: begin
-        dummy_set    = 7'b0000001;
-        dummy_opcode = 3'b000;
-      end
-      DUMMY_DIV: begin
-        dummy_set    = 7'b0000001;
-        dummy_opcode = 3'b100;
-      end
-      DUMMY_AND: begin
-        dummy_set    = 7'b0000000;
-        dummy_opcode = 3'b111;
-      end
-      default: begin
-        dummy_set    = 7'b0000000;
-        dummy_opcode = 3'b000;
-      end
-    endcase
-  end
-
-  //                    SET        RS2             RS1             OP            RD
-  assign dummy_instr = {dummy_set, lfsr_data.op_b, lfsr_data.op_a, dummy_opcode, 5'h00, 7'h33};
-
-  // Assign outputs
-  assign insert_dummy_instr_o = insert_dummy_instr;
-  assign dummy_instr_data_o   = dummy_instr;
-
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_icache.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_icache.sv
deleted file mode 100644
index c15a29b5..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_icache.sv
+++ /dev/null
@@ -1,1165 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-/**
- * Instruction cache
- *
- * Provides an instruction cache along with cache management, instruction buffering and prefetching
- */
-
-`include "prim_assert.sv"
-
-module ibex_icache import ibex_pkg::*; #(
-  parameter bit          ICacheECC       = 1'b0,
-  parameter bit          ResetAll        = 1'b0,
-  parameter int unsigned BusSizeECC      = BUS_SIZE,
-  parameter int unsigned TagSizeECC      = IC_TAG_SIZE,
-  parameter int unsigned LineSizeECC     = IC_LINE_SIZE,
-  // Only cache branch targets
-  parameter bit          BranchCache     = 1'b0
-) (
-  // Clock and reset
-  input  logic                           clk_i,
-  input  logic                           rst_ni,
-
-  // Signal that the core would like instructions
-  input  logic                           req_i,
-
-  // Set the cache's address counter
-  input  logic                           branch_i,
-  input  logic                           branch_mispredict_i,
-  input  logic [31:0]                    mispredict_addr_i,
-  input  logic [31:0]                    addr_i,
-
-  // IF stage interface: Pass fetched instructions to the core
-  input  logic                           ready_i,
-  output logic                           valid_o,
-  output logic [31:0]                    rdata_o,
-  output logic [31:0]                    addr_o,
-  output logic                           err_o,
-  output logic                           err_plus2_o,
-
-  // Instruction memory / interconnect interface: Fetch instruction data from memory
-  output logic                           instr_req_o,
-  input  logic                           instr_gnt_i,
-  output logic [31:0]                    instr_addr_o,
-  input  logic [BUS_SIZE-1:0]            instr_rdata_i,
-  input  logic                           instr_err_i,
-  input  logic                           instr_rvalid_i,
-
-  // RAM IO
-  output logic [IC_NUM_WAYS-1:0]         ic_tag_req_o,
-  output logic                           ic_tag_write_o,
-  output logic [IC_INDEX_W-1:0]          ic_tag_addr_o,
-  output logic [TagSizeECC-1:0]          ic_tag_wdata_o,
-  input  logic [TagSizeECC-1:0]          ic_tag_rdata_i [IC_NUM_WAYS],
-  output logic [IC_NUM_WAYS-1:0]         ic_data_req_o,
-  output logic                           ic_data_write_o,
-  output logic [IC_INDEX_W-1:0]          ic_data_addr_o,
-  output logic [LineSizeECC-1:0]         ic_data_wdata_o,
-  input  logic [LineSizeECC-1:0]         ic_data_rdata_i [IC_NUM_WAYS],
-  input  logic                           ic_scr_key_valid_i,
-
-  // Cache status
-  input  logic                           icache_enable_i,
-  input  logic                           icache_inval_i,
-  output logic                           busy_o,
-  output logic                           ecc_error_o
-);
-
-  // Number of fill buffers (must be >= 2)
-  localparam int unsigned NUM_FB        = 4;
-  // Request throttling threshold
-  localparam int unsigned FB_THRESHOLD  = NUM_FB - 2;
-
-  // Prefetch signals
-  logic [ADDR_W-1:0]                      lookup_addr_aligned;
-  logic [ADDR_W-1:0]                      prefetch_addr_d, prefetch_addr_q;
-  logic                                   prefetch_addr_en;
-  logic                                   branch_or_mispredict;
-  // Cache pipelipe IC0 signals
-  logic                                   lookup_throttle;
-  logic                                   lookup_req_ic0;
-  logic [ADDR_W-1:0]                      lookup_addr_ic0;
-  logic [IC_INDEX_W-1:0]                  lookup_index_ic0;
-  logic                                   fill_req_ic0;
-  logic [IC_INDEX_W-1:0]                  fill_index_ic0;
-  logic [IC_TAG_SIZE-1:0]                 fill_tag_ic0;
-  logic [IC_LINE_SIZE-1:0]                fill_wdata_ic0;
-  logic                                   lookup_grant_ic0;
-  logic                                   lookup_actual_ic0;
-  logic                                   fill_grant_ic0;
-  logic                                   tag_req_ic0;
-  logic [IC_INDEX_W-1:0]                  tag_index_ic0;
-  logic [IC_NUM_WAYS-1:0]                 tag_banks_ic0;
-  logic                                   tag_write_ic0;
-  logic [TagSizeECC-1:0]                  tag_wdata_ic0;
-  logic                                   data_req_ic0;
-  logic [IC_INDEX_W-1:0]                  data_index_ic0;
-  logic [IC_NUM_WAYS-1:0]                 data_banks_ic0;
-  logic                                   data_write_ic0;
-  logic [LineSizeECC-1:0]                 data_wdata_ic0;
-  // Cache pipelipe IC1 signals
-  logic [TagSizeECC-1:0]                  tag_rdata_ic1  [IC_NUM_WAYS];
-  logic [LineSizeECC-1:0]                 data_rdata_ic1 [IC_NUM_WAYS];
-  logic [LineSizeECC-1:0]                 hit_data_ecc_ic1;
-  logic [IC_LINE_SIZE-1:0]                hit_data_ic1;
-  logic                                   lookup_valid_ic1;
-  logic [ADDR_W-1:IC_INDEX_HI+1]          lookup_addr_ic1;
-  logic [IC_NUM_WAYS-1:0]                 tag_match_ic1;
-  logic                                   tag_hit_ic1;
-  logic [IC_NUM_WAYS-1:0]                 tag_invalid_ic1;
-  logic [IC_NUM_WAYS-1:0]                 lowest_invalid_way_ic1;
-  logic [IC_NUM_WAYS-1:0]                 round_robin_way_ic1, round_robin_way_q;
-  logic [IC_NUM_WAYS-1:0]                 sel_way_ic1;
-  logic                                   ecc_err_ic1;
-  logic                                   ecc_write_req;
-  logic [IC_NUM_WAYS-1:0]                 ecc_write_ways;
-  logic [IC_INDEX_W-1:0]                  ecc_write_index;
-  // Fill buffer signals
-  logic [$clog2(NUM_FB)-1:0]              fb_fill_level;
-  logic                                   fill_cache_new;
-  logic                                   fill_new_alloc;
-  logic                                   fill_spec_req, fill_spec_done, fill_spec_hold;
-  logic [NUM_FB-1:0][NUM_FB-1:0]          fill_older_d, fill_older_q;
-  logic [NUM_FB-1:0]                      fill_alloc_sel, fill_alloc;
-  logic [NUM_FB-1:0]                      fill_busy_d, fill_busy_q;
-  logic [NUM_FB-1:0]                      fill_done;
-  logic [NUM_FB-1:0]                      fill_in_ic1;
-  logic [NUM_FB-1:0]                      fill_stale_d, fill_stale_q;
-  logic [NUM_FB-1:0]                      fill_cache_d, fill_cache_q;
-  logic [NUM_FB-1:0]                      fill_hit_ic1, fill_hit_d, fill_hit_q;
-  logic [NUM_FB-1:0][IC_LINE_BEATS_W:0]   fill_ext_cnt_d, fill_ext_cnt_q;
-  logic [NUM_FB-1:0]                      fill_ext_hold_d, fill_ext_hold_q;
-  logic [NUM_FB-1:0]                      fill_ext_done_d, fill_ext_done_q;
-  logic [NUM_FB-1:0][IC_LINE_BEATS_W:0]   fill_rvd_cnt_d, fill_rvd_cnt_q;
-  logic [NUM_FB-1:0]                      fill_rvd_done;
-  logic [NUM_FB-1:0]                      fill_ram_done_d, fill_ram_done_q;
-  logic [NUM_FB-1:0]                      fill_out_grant;
-  logic [NUM_FB-1:0][IC_LINE_BEATS_W:0]   fill_out_cnt_d, fill_out_cnt_q;
-  logic [NUM_FB-1:0]                      fill_out_done;
-  logic [NUM_FB-1:0]                      fill_ext_req, fill_rvd_exp, fill_ram_req, fill_out_req;
-  logic [NUM_FB-1:0]                      fill_data_sel, fill_data_reg;
-  logic [NUM_FB-1:0]                      fill_data_hit, fill_data_rvd;
-  logic [NUM_FB-1:0][IC_LINE_BEATS_W-1:0] fill_ext_off, fill_rvd_off;
-  logic [NUM_FB-1:0][IC_LINE_BEATS_W:0]   fill_ext_beat, fill_rvd_beat;
-  logic [NUM_FB-1:0]                      fill_ext_arb, fill_ram_arb, fill_out_arb;
-  logic [NUM_FB-1:0]                      fill_rvd_arb;
-  logic [NUM_FB-1:0]                      fill_entry_en;
-  logic [NUM_FB-1:0]                      fill_addr_en;
-  logic [NUM_FB-1:0]                      fill_way_en;
-  logic [NUM_FB-1:0][IC_LINE_BEATS-1:0]   fill_data_en;
-  logic [NUM_FB-1:0][IC_LINE_BEATS-1:0]   fill_err_d, fill_err_q;
-  logic [ADDR_W-1:0]                      fill_addr_q [NUM_FB];
-  logic [IC_NUM_WAYS-1:0]                 fill_way_q  [NUM_FB];
-  logic [IC_LINE_SIZE-1:0]                fill_data_d [NUM_FB];
-  logic [IC_LINE_SIZE-1:0]                fill_data_q [NUM_FB];
-  logic [ADDR_W-1:BUS_W]                  fill_ext_req_addr;
-  logic [ADDR_W-1:0]                      fill_ram_req_addr;
-  logic [IC_NUM_WAYS-1:0]                 fill_ram_req_way;
-  logic [IC_LINE_SIZE-1:0]                fill_ram_req_data;
-  logic [IC_LINE_SIZE-1:0]                fill_out_data;
-  logic [IC_LINE_BEATS-1:0]               fill_out_err;
-  // External req signals
-  logic                                   instr_req;
-  logic [ADDR_W-1:BUS_W]                  instr_addr;
-  // Data output signals
-  logic                                   skid_complete_instr;
-  logic                                   skid_ready;
-  logic                                   output_compressed;
-  logic                                   skid_valid_d, skid_valid_q, skid_en;
-  logic [15:0]                            skid_data_d, skid_data_q;
-  logic                                   skid_err_q;
-  logic                                   output_valid;
-  logic                                   addr_incr_two;
-  logic                                   output_addr_en;
-  logic [ADDR_W-1:1]                      output_addr_incr;
-  logic [ADDR_W-1:1]                      output_addr_d, output_addr_q;
-  logic [15:0]                            output_data_lo, output_data_hi;
-  logic                                   data_valid, output_ready;
-  logic [IC_LINE_SIZE-1:0]                line_data;
-  logic [IC_LINE_BEATS-1:0]               line_err;
-  logic [31:0]                            line_data_muxed;
-  logic                                   line_err_muxed;
-  logic [31:0]                            output_data;
-  logic                                   output_err;
-  // Invalidations
-  logic                                   start_inval, inval_done;
-  logic                                   inval_lock, inval_req_d, inval_req_q;
-  logic                                   reset_inval_q;
-  logic                                   inval_prog_d, inval_prog_q;
-  logic [IC_INDEX_W-1:0]                  inval_index_d, inval_index_q;
-
-  //////////////////////////
-  // Instruction prefetch //
-  //////////////////////////
-
-  assign branch_or_mispredict = branch_i | branch_mispredict_i;
-
-  assign lookup_addr_aligned = {lookup_addr_ic0[ADDR_W-1:IC_LINE_W], {IC_LINE_W{1'b0}}};
-
-  // The prefetch address increments by one cache line for each granted request.
-  // This address is also updated if there is a branch that is not granted, since the target
-  // address (addr_i) is only valid for one cycle while branch_i is high.
-
-  // The captured branch target address is not forced to be aligned since the offset in the cache
-  // line must also be recorded for later use by the fill buffers.
-  assign prefetch_addr_d     =
-      lookup_grant_ic0 ? (lookup_addr_aligned +
-                          {{ADDR_W-IC_LINE_W-1{1'b0}}, 1'b1, {IC_LINE_W{1'b0}}}) :
-      branch_i         ? addr_i :
-                         mispredict_addr_i;
-
-  assign prefetch_addr_en    = branch_or_mispredict | lookup_grant_ic0;
-
-  if (ResetAll) begin : g_prefetch_addr_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        prefetch_addr_q <= '0;
-      end else if (prefetch_addr_en) begin
-        prefetch_addr_q <= prefetch_addr_d;
-      end
-    end
-  end else begin : g_prefetch_addr_nr
-    always_ff @(posedge clk_i) begin
-      if (prefetch_addr_en) begin
-        prefetch_addr_q <= prefetch_addr_d;
-      end
-    end
-  end
-
-  ////////////////////////
-  // Pipeline stage IC0 //
-  ////////////////////////
-
-  // Cache lookup
-  assign lookup_throttle  = (fb_fill_level > FB_THRESHOLD[$clog2(NUM_FB)-1:0]);
-
-  assign lookup_req_ic0   = req_i & ~&fill_busy_q & (branch_or_mispredict | ~lookup_throttle) &
-                            ~ecc_write_req;
-  assign lookup_addr_ic0  = branch_i            ? addr_i :
-                            branch_mispredict_i ? mispredict_addr_i :
-                                                  prefetch_addr_q;
-  assign lookup_index_ic0 = lookup_addr_ic0[IC_INDEX_HI:IC_LINE_W];
-
-  // Cache write
-  assign fill_req_ic0   = (|fill_ram_req);
-  assign fill_index_ic0 = fill_ram_req_addr[IC_INDEX_HI:IC_LINE_W];
-  assign fill_tag_ic0   = {(~inval_prog_q & ~ecc_write_req),
-                           fill_ram_req_addr[ADDR_W-1:IC_INDEX_HI+1]};
-  assign fill_wdata_ic0 = fill_ram_req_data;
-
-  // Arbitrated signals - lookups have highest priority
-  assign lookup_grant_ic0  = lookup_req_ic0;
-  assign fill_grant_ic0    = fill_req_ic0 & ~lookup_req_ic0 & ~inval_prog_q &
-                             ~ecc_write_req;
-  // Qualified lookup grant to mask ram signals in IC1 if access was not made
-  assign lookup_actual_ic0 = lookup_grant_ic0 & icache_enable_i & ~inval_prog_q &
-                             ~icache_inval_i & ~inval_lock & ~start_inval;
-
-  // Tagram
-  assign tag_req_ic0   = lookup_req_ic0 | fill_req_ic0 | inval_prog_q | ecc_write_req;
-  assign tag_index_ic0 = inval_prog_q   ? inval_index_q :
-                         ecc_write_req  ? ecc_write_index :
-                         fill_grant_ic0 ? fill_index_ic0 :
-                                          lookup_index_ic0;
-  assign tag_banks_ic0 = ecc_write_req  ? ecc_write_ways :
-                         fill_grant_ic0 ? fill_ram_req_way :
-                                          {IC_NUM_WAYS{1'b1}};
-  assign tag_write_ic0 = fill_grant_ic0 | inval_prog_q | ecc_write_req;
-
-  // Dataram
-  assign data_req_ic0   = lookup_req_ic0 | fill_req_ic0;
-  assign data_index_ic0 = tag_index_ic0;
-  assign data_banks_ic0 = tag_banks_ic0;
-  assign data_write_ic0 = tag_write_ic0;
-
-  // Append ECC checkbits to write data if required
-  if (ICacheECC) begin : gen_ecc_wdata
-    // SEC_CM: ICACHE.MEM.INTEGRITY
-    // Tagram ECC
-    // Reuse the same ecc encoding module for larger cache sizes by padding with zeros
-    logic [21:0]             tag_ecc_input_padded;
-    logic [27:0]             tag_ecc_output_padded;
-    logic [22-IC_TAG_SIZE:0] unused_tag_ecc_output;
-
-    assign tag_ecc_input_padded  = {{22-IC_TAG_SIZE{1'b0}},fill_tag_ic0};
-    assign unused_tag_ecc_output = tag_ecc_output_padded[21:IC_TAG_SIZE-1];
-
-    prim_secded_inv_28_22_enc tag_ecc_enc (
-      .data_i (tag_ecc_input_padded),
-      .data_o (tag_ecc_output_padded)
-    );
-
-    assign tag_wdata_ic0 = {tag_ecc_output_padded[27:22],tag_ecc_output_padded[IC_TAG_SIZE-1:0]};
-
-    // Dataram ECC
-    for (genvar bank = 0; bank < IC_LINE_BEATS; bank++) begin : gen_ecc_banks
-      prim_secded_inv_39_32_enc data_ecc_enc (
-        .data_i (fill_wdata_ic0[bank*BUS_SIZE+:BUS_SIZE]),
-        .data_o (data_wdata_ic0[bank*BusSizeECC+:BusSizeECC])
-      );
-    end
-
-  end else begin : gen_noecc_wdata
-    assign tag_wdata_ic0  = fill_tag_ic0;
-    assign data_wdata_ic0 = fill_wdata_ic0;
-  end
-
-  ////////////////
-  // IC0 -> IC1 //
-  ////////////////
-
-  // Tag RAMs outputs
-  assign ic_tag_req_o    = {IC_NUM_WAYS{tag_req_ic0}} & tag_banks_ic0;
-  assign ic_tag_write_o  = tag_write_ic0;
-  assign ic_tag_addr_o   = tag_index_ic0;
-  assign ic_tag_wdata_o  = tag_wdata_ic0;
-
-  // Tag RAMs inputs
-  assign tag_rdata_ic1   = ic_tag_rdata_i;
-
-  // Data RAMs outputs
-  assign ic_data_req_o   = {IC_NUM_WAYS{data_req_ic0}} & data_banks_ic0;
-  assign ic_data_write_o = data_write_ic0;
-  assign ic_data_addr_o  = data_index_ic0;
-  assign ic_data_wdata_o = data_wdata_ic0;
-
-  // Data RAMs inputs
-  assign data_rdata_ic1  = ic_data_rdata_i;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      lookup_valid_ic1 <= 1'b0;
-    end else begin
-      lookup_valid_ic1 <= lookup_actual_ic0;
-    end
-  end
-
-  if (ResetAll) begin : g_lookup_addr_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        lookup_addr_ic1 <= '0;
-        fill_in_ic1     <= '0;
-      end else if (lookup_grant_ic0) begin
-        lookup_addr_ic1 <= lookup_addr_ic0[ADDR_W-1:IC_INDEX_HI+1];
-        fill_in_ic1     <= fill_alloc_sel;
-      end
-    end
-  end else begin : g_lookup_addr_nr
-    always_ff @(posedge clk_i) begin
-      if (lookup_grant_ic0) begin
-        lookup_addr_ic1 <= lookup_addr_ic0[ADDR_W-1:IC_INDEX_HI+1];
-        fill_in_ic1     <= fill_alloc_sel;
-      end
-    end
-  end
-
-  ////////////////////////
-  // Pipeline stage IC1 //
-  ////////////////////////
-
-  // Tag matching
-  for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_tag_match
-    assign tag_match_ic1[way]   = (tag_rdata_ic1[way][IC_TAG_SIZE-1:0] ==
-                                   {1'b1,lookup_addr_ic1[ADDR_W-1:IC_INDEX_HI+1]});
-    assign tag_invalid_ic1[way] = ~tag_rdata_ic1[way][IC_TAG_SIZE-1];
-  end
-
-  assign tag_hit_ic1 = |tag_match_ic1;
-
-  // Hit data mux
-  always_comb begin
-    hit_data_ecc_ic1 = 'b0;
-    for (int way = 0; way < IC_NUM_WAYS; way++) begin
-      if (tag_match_ic1[way]) begin
-        hit_data_ecc_ic1 |= data_rdata_ic1[way];
-      end
-    end
-  end
-
-  // Way selection for allocations to the cache (onehot signals)
-  // 1 first invalid way
-  // 2 global round-robin (pseudorandom) way
-  assign lowest_invalid_way_ic1[0] = tag_invalid_ic1[0];
-  assign round_robin_way_ic1[0]    = round_robin_way_q[IC_NUM_WAYS-1];
-  for (genvar way = 1; way < IC_NUM_WAYS; way++) begin : gen_lowest_way
-    assign lowest_invalid_way_ic1[way] = tag_invalid_ic1[way] & ~|tag_invalid_ic1[way-1:0];
-    assign round_robin_way_ic1[way]    = round_robin_way_q[way-1];
-  end
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      round_robin_way_q <= {{IC_NUM_WAYS-1{1'b0}}, 1'b1};
-    end else if (lookup_valid_ic1) begin
-      round_robin_way_q <= round_robin_way_ic1;
-    end
-  end
-
-  assign sel_way_ic1 = |tag_invalid_ic1 ? lowest_invalid_way_ic1 :
-                                          round_robin_way_q;
-
-  // ECC checking logic
-  if (ICacheECC) begin : gen_data_ecc_checking
-    // SEC_CM: ICACHE.MEM.INTEGRITY
-    logic [IC_NUM_WAYS-1:0]     tag_err_ic1;
-    logic [IC_LINE_BEATS*2-1:0] data_err_ic1;
-    logic                       ecc_correction_write_d, ecc_correction_write_q;
-    logic [IC_NUM_WAYS-1:0]     ecc_correction_ways_d, ecc_correction_ways_q;
-    logic [IC_INDEX_W-1:0]      lookup_index_ic1, ecc_correction_index_q;
-
-    // Tag ECC checking
-    for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_tag_ecc
-      logic [1:0]  tag_err_bank_ic1;
-      logic [27:0] tag_rdata_padded_ic1;
-
-      // Expand the tag rdata with extra padding if the tag size is less than the maximum
-      assign tag_rdata_padded_ic1 = {tag_rdata_ic1[way][TagSizeECC-1-:6],
-                                     {22-IC_TAG_SIZE{1'b0}},
-                                     tag_rdata_ic1[way][IC_TAG_SIZE-1:0]};
-
-      prim_secded_inv_28_22_dec data_ecc_dec (
-        .data_i     (tag_rdata_padded_ic1),
-        .data_o     (),
-        .syndrome_o (),
-        .err_o      (tag_err_bank_ic1)
-      );
-      assign tag_err_ic1[way] = |tag_err_bank_ic1;
-    end
-
-    // Data ECC checking
-    // Note - could generate for all ways and mux after
-    for (genvar bank = 0; bank < IC_LINE_BEATS; bank++) begin : gen_ecc_banks
-      prim_secded_inv_39_32_dec data_ecc_dec (
-        .data_i     (hit_data_ecc_ic1[bank*BusSizeECC+:BusSizeECC]),
-        .data_o     (),
-        .syndrome_o (),
-        .err_o      (data_err_ic1[bank*2+:2])
-      );
-
-      assign hit_data_ic1[bank*BUS_SIZE+:BUS_SIZE] =
-          hit_data_ecc_ic1[bank*BusSizeECC+:BUS_SIZE];
-
-    end
-
-    // Tag ECC across all ways is always expected to be correct so the check does not need to be
-    // qualified by hit or tag valid. Initial (invalid with correct ECC) tags are written on reset
-    // and all further tag writes produce correct ECC. For data ECC no initialisation is done on
-    // reset so unused data (in particular those ways that don't have a valid tag) may have
-    // incorrect ECC. We only check data ECC where tags indicate it is valid and we have hit on it.
-    assign ecc_err_ic1 = lookup_valid_ic1 & (((|data_err_ic1) & tag_hit_ic1) | (|tag_err_ic1));
-
-    // Error correction
-    // All ways will be invalidated on a tag error to prevent X-propagation from data_err_ic1 on
-    // spurious hits. Also prevents the same line being allocated twice when there was a true
-    // hit and a spurious hit.
-    assign ecc_correction_ways_d  = {IC_NUM_WAYS{|tag_err_ic1}} |
-                                    (tag_match_ic1 & {IC_NUM_WAYS{|data_err_ic1}});
-    assign ecc_correction_write_d = ecc_err_ic1;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        ecc_correction_write_q <= 1'b0;
-      end else begin
-        ecc_correction_write_q <= ecc_correction_write_d;
-      end
-    end
-
-    // The index is required in IC1 only when ECC is configured so is registered here
-    if (ResetAll) begin : g_lookup_ind_ra
-      always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (!rst_ni) begin
-          lookup_index_ic1 <= '0;
-        end else if (lookup_grant_ic0) begin
-          lookup_index_ic1 <= lookup_addr_ic0[IC_INDEX_HI-:IC_INDEX_W];
-        end
-      end
-    end else begin : g_lookup_ind_nr
-      always_ff @(posedge clk_i) begin
-        if (lookup_grant_ic0) begin
-          lookup_index_ic1 <= lookup_addr_ic0[IC_INDEX_HI-:IC_INDEX_W];
-        end
-      end
-    end
-
-    // Store the ways with errors to be invalidated
-    if (ResetAll) begin : g_ecc_correction_ra
-      always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (!rst_ni) begin
-          ecc_correction_ways_q  <= '0;
-          ecc_correction_index_q <= '0;
-        end else if (ecc_err_ic1) begin
-          ecc_correction_ways_q  <= ecc_correction_ways_d;
-          ecc_correction_index_q <= lookup_index_ic1;
-        end
-      end
-    end else begin : g_ecc_correction_nr
-      always_ff @(posedge clk_i) begin
-        if (ecc_err_ic1) begin
-          ecc_correction_ways_q  <= ecc_correction_ways_d;
-          ecc_correction_index_q <= lookup_index_ic1;
-        end
-      end
-    end
-
-    assign ecc_write_req   = ecc_correction_write_q;
-    assign ecc_write_ways  = ecc_correction_ways_q;
-    assign ecc_write_index = ecc_correction_index_q;
-
-    assign ecc_error_o = ecc_err_ic1;
-  end else begin : gen_no_data_ecc
-    assign ecc_err_ic1     = 1'b0;
-    assign ecc_write_req   = 1'b0;
-    assign ecc_write_ways  = '0;
-    assign ecc_write_index = '0;
-    assign hit_data_ic1    = hit_data_ecc_ic1;
-
-    assign ecc_error_o = 1'b0;
-  end
-
-  ///////////////////////////////
-  // Cache allocation decision //
-  ///////////////////////////////
-
-  if (BranchCache) begin : gen_caching_logic
-
-    // Cache branch target + a number of subsequent lines
-    localparam int unsigned CACHE_AHEAD = 2;
-    localparam int unsigned CACHE_CNT_W = (CACHE_AHEAD == 1) ? 1 : $clog2(CACHE_AHEAD) + 1;
-    logic                   cache_cnt_dec;
-    logic [CACHE_CNT_W-1:0] cache_cnt_d, cache_cnt_q;
-
-    assign cache_cnt_dec = lookup_grant_ic0 & (|cache_cnt_q);
-    assign cache_cnt_d   = branch_i ? CACHE_AHEAD[CACHE_CNT_W-1:0] :
-                                      (cache_cnt_q - {{CACHE_CNT_W-1{1'b0}},cache_cnt_dec});
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        cache_cnt_q <= '0;
-      end else begin
-        cache_cnt_q <= cache_cnt_d;
-      end
-    end
-
-    assign fill_cache_new = (branch_i | (|cache_cnt_q)) & icache_enable_i &
-                            ~icache_inval_i & ~inval_lock & ~inval_prog_q;
-
-  end else begin : gen_cache_all
-
-    // Cache all missing fetches
-    assign fill_cache_new = icache_enable_i & ~start_inval & ~inval_prog_q;
-  end
-
-  //////////////////////////
-  // Fill buffer tracking //
-  //////////////////////////
-
-  always_comb begin
-    fb_fill_level = '0;
-    for (int i = 0; i < NUM_FB; i++) begin
-      if (fill_busy_q[i] & ~fill_stale_q[i]) begin
-        fb_fill_level += {{$clog2(NUM_FB) - 1{1'b0}}, 1'b1};
-      end
-    end
-  end
-
-  // Allocate a new buffer for every granted lookup
-  assign fill_new_alloc = lookup_grant_ic0;
-  // Track whether a speculative external request was made from IC0, and whether it was granted
-  // Speculative requests are only made for branches, or if the cache is disabled
-  assign fill_spec_req  = (~icache_enable_i | branch_or_mispredict) & ~|fill_ext_req;
-  assign fill_spec_done = fill_spec_req & instr_gnt_i;
-  assign fill_spec_hold = fill_spec_req & ~instr_gnt_i;
-
-  for (genvar fb = 0; fb < NUM_FB; fb++) begin : gen_fbs
-
-    /////////////////////////////
-    // Fill buffer allocations //
-    /////////////////////////////
-
-    // Allocate the lowest available buffer
-    if (fb == 0) begin : gen_fb_zero
-      assign fill_alloc_sel[fb] = ~fill_busy_q[fb];
-    end else begin : gen_fb_rest
-      assign fill_alloc_sel[fb] = ~fill_busy_q[fb] & (&fill_busy_q[fb-1:0]);
-    end
-
-    assign fill_alloc[fb]      = fill_alloc_sel[fb] & fill_new_alloc;
-    assign fill_busy_d[fb]     = fill_alloc[fb] | (fill_busy_q[fb] & ~fill_done[fb]);
-
-    // Track which other fill buffers are older than this one (for age-based arbitration)
-    // TODO sparsify
-    assign fill_older_d[fb]    = (fill_alloc[fb] ? fill_busy_q : fill_older_q[fb]) & ~fill_done;
-
-    // A fill buffer can release once all its actions are completed
-                                 // all data written to the cache (unless hit or error)
-    assign fill_done[fb]       = (fill_ram_done_q[fb] | fill_hit_q[fb] | ~fill_cache_q[fb] |
-                                  (|fill_err_q[fb])) &
-                                 // all data output unless stale due to intervening branch
-                                 (fill_out_done[fb] | fill_stale_q[fb] | branch_or_mispredict) &
-                                 // all external requests completed
-                                 fill_rvd_done[fb];
-
-    /////////////////////////////////
-    // Fill buffer status tracking //
-    /////////////////////////////////
-
-    // Track staleness (requests become stale when a branch intervenes)
-    assign fill_stale_d[fb]    = fill_busy_q[fb] & (branch_or_mispredict | fill_stale_q[fb]);
-    // Track whether or not this request should allocate to the cache
-    // Any invalidation or disabling of the cache while the buffer is busy will stop allocation
-    assign fill_cache_d[fb]    = (fill_alloc[fb] & fill_cache_new) |
-                                 (fill_cache_q[fb] & fill_busy_q[fb] &
-                                  icache_enable_i & ~icache_inval_i & ~inval_lock);
-    // Record whether the request hit in the cache
-    assign fill_hit_ic1[fb]    = lookup_valid_ic1 & fill_in_ic1[fb] & tag_hit_ic1 & ~ecc_err_ic1;
-    assign fill_hit_d[fb]      = fill_hit_ic1[fb] | (fill_hit_q[fb] & fill_busy_q[fb]);
-
-    ///////////////////////////////////////////
-    // Fill buffer external request tracking //
-    ///////////////////////////////////////////
-
-    // Make an external request
-    assign fill_ext_req[fb]    = fill_busy_q[fb] & ~fill_ext_done_d[fb];
-
-    // Count the number of completed external requests (each line requires IC_LINE_BEATS requests)
-    assign fill_ext_cnt_d[fb]  = fill_alloc[fb] ?
-                                   {{IC_LINE_BEATS_W{1'b0}},fill_spec_done} :
-                                   (fill_ext_cnt_q[fb] + {{IC_LINE_BEATS_W{1'b0}},
-                                                          fill_ext_arb[fb] & instr_gnt_i});
-    // External request must be held until granted
-    assign fill_ext_hold_d[fb] = (fill_alloc[fb] & fill_spec_hold) |
-                                 (fill_ext_arb[fb] & ~instr_gnt_i);
-    // External requests are completed when the counter is filled or when the request is cancelled
-    assign fill_ext_done_d[fb] = (fill_ext_cnt_q[fb][IC_LINE_BEATS_W] |
-                                  // external requests are considered complete if the request hit
-                                  fill_hit_ic1[fb] | fill_hit_q[fb] |
-                                  // cancel if the line won't be cached and, it is stale
-                                  (~fill_cache_q[fb] & (branch_or_mispredict | fill_stale_q[fb] |
-                                   // or we're already at the end of the line
-                                                        fill_ext_beat[fb][IC_LINE_BEATS_W]))) &
-                                 // can't cancel while we are waiting for a grant on the bus
-                                 ~fill_ext_hold_q[fb] & fill_busy_q[fb];
-    // Track whether this fill buffer expects to receive beats of data
-    assign fill_rvd_exp[fb]    = fill_busy_q[fb] & ~fill_rvd_done[fb];
-    // Count the number of rvalid beats received
-    assign fill_rvd_cnt_d[fb]  = fill_alloc[fb] ? '0 :
-                                                  (fill_rvd_cnt_q[fb] +
-                                                   {{IC_LINE_BEATS_W{1'b0}},fill_rvd_arb[fb]});
-    // External data is complete when all issued external requests have received their data
-    assign fill_rvd_done[fb]   = (fill_ext_done_q[fb] & ~fill_ext_hold_q[fb]) &
-                                 (fill_rvd_cnt_q[fb] == fill_ext_cnt_q[fb]);
-
-    //////////////////////////////////////
-    // Fill buffer data output tracking //
-    //////////////////////////////////////
-
-    // Send data to the IF stage for requests that are not stale, have not completed their
-    // data output, and have data available to send.
-    // Data is available if:
-    // - The request hit in the cache
-    // - Buffered data is available (fill_rvd_cnt_q is ahead of fill_out_cnt_q)
-    // - Data is available from the bus this cycle (fill_rvd_arb)
-    assign fill_out_req[fb]    = fill_busy_q[fb] & ~fill_stale_q[fb] & ~fill_out_done[fb] &
-                                 (fill_hit_ic1[fb] | fill_hit_q[fb] |
-                                  (fill_rvd_beat[fb] > fill_out_cnt_q[fb]) | fill_rvd_arb[fb]);
-
-    // Calculate when a beat of data is output. Any ECC error squashes the output that cycle.
-    assign fill_out_grant[fb]  = fill_out_arb[fb] & output_ready;
-
-    // Count the beats of data output to the IF stage
-    assign fill_out_cnt_d[fb]  = fill_alloc[fb] ? {1'b0,lookup_addr_ic0[IC_LINE_W-1:BUS_W]} :
-                                                  (fill_out_cnt_q[fb] +
-                                                   {{IC_LINE_BEATS_W{1'b0}},fill_out_grant[fb]});
-    // Data output complete when the counter fills
-    assign fill_out_done[fb]   = fill_out_cnt_q[fb][IC_LINE_BEATS_W];
-
-    //////////////////////////////////////
-    // Fill buffer ram request tracking //
-    //////////////////////////////////////
-
-                                 // make a fill request once all data beats received
-    assign fill_ram_req[fb]    = fill_busy_q[fb] & fill_rvd_cnt_q[fb][IC_LINE_BEATS_W] &
-                                 // unless the request hit, was non-allocating or got an error
-                                 ~fill_hit_q[fb] & fill_cache_q[fb] & ~|fill_err_q[fb] &
-                                 // or the request was already completed
-                                 ~fill_ram_done_q[fb];
-
-    // Record when a cache allocation request has been completed
-    assign fill_ram_done_d[fb] = fill_ram_arb[fb] | (fill_ram_done_q[fb] & fill_busy_q[fb]);
-
-    //////////////////////////////
-    // Fill buffer line offsets //
-    //////////////////////////////
-
-    // When we branch into the middle of a line, the output count will not start from zero. This
-    // beat count is used to know which incoming rdata beats are relevant.
-    assign fill_ext_beat[fb]   = {1'b0,fill_addr_q[fb][IC_LINE_W-1:BUS_W]} +
-                                 fill_ext_cnt_q[fb][IC_LINE_BEATS_W:0];
-    assign fill_ext_off[fb]    = fill_ext_beat[fb][IC_LINE_BEATS_W-1:0];
-    assign fill_rvd_beat[fb]   = {1'b0,fill_addr_q[fb][IC_LINE_W-1:BUS_W]} +
-                                 fill_rvd_cnt_q[fb][IC_LINE_BEATS_W:0];
-    assign fill_rvd_off[fb]    = fill_rvd_beat[fb][IC_LINE_BEATS_W-1:0];
-
-    /////////////////////////////
-    // Fill buffer arbitration //
-    /////////////////////////////
-
-    // Age based arbitration - all these signals are one-hot
-    assign fill_ext_arb[fb]    = fill_ext_req[fb] & ~|(fill_ext_req & fill_older_q[fb]);
-    assign fill_ram_arb[fb]    = fill_ram_req[fb] & fill_grant_ic0 &
-                                 ~|(fill_ram_req & fill_older_q[fb]);
-    // Calculate which fill buffer is the oldest one which still needs to output data to IF
-    assign fill_data_sel[fb]   = ~|(fill_busy_q & ~fill_out_done & ~fill_stale_q &
-                                    fill_older_q[fb]);
-    // Arbitrate the request which has data available to send, and is the oldest outstanding
-    assign fill_out_arb[fb]    = fill_out_req[fb] & fill_data_sel[fb];
-    // Assign incoming rvalid data to the oldest fill buffer expecting it
-    assign fill_rvd_arb[fb]    = instr_rvalid_i & fill_rvd_exp[fb] &
-                                 ~|(fill_rvd_exp & fill_older_q[fb]);
-
-    /////////////////////////////
-    // Fill buffer data muxing //
-    /////////////////////////////
-
-    // Output data muxing controls
-    // 1. Select data from the fill buffer data register
-    assign fill_data_reg[fb]   = fill_busy_q[fb] & ~fill_stale_q[fb] &
-                                 ~fill_out_done[fb] & fill_data_sel[fb] &
-    //                           The incoming data is already ahead of the output count
-                                 ((fill_rvd_beat[fb] > fill_out_cnt_q[fb]) | fill_hit_q[fb] |
-                                  (|fill_err_q[fb]));
-    // 2. Select IC1 hit data
-    assign fill_data_hit[fb]   = fill_busy_q[fb] & fill_hit_ic1[fb] & fill_data_sel[fb];
-    // 3. Select incoming instr_rdata_i
-    assign fill_data_rvd[fb]   = fill_busy_q[fb] & fill_rvd_arb[fb] & ~fill_hit_q[fb] &
-                                 ~fill_hit_ic1[fb] & ~fill_stale_q[fb] & ~fill_out_done[fb] &
-    //                           The incoming data lines up with the output count
-                                 (fill_rvd_beat[fb] == fill_out_cnt_q[fb]) & fill_data_sel[fb];
-
-
-    ///////////////////////////
-    // Fill buffer registers //
-    ///////////////////////////
-
-    // Fill buffer general enable
-    assign fill_entry_en[fb]   = fill_alloc[fb] | fill_busy_q[fb];
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        fill_busy_q[fb]     <= 1'b0;
-        fill_older_q[fb]    <= '0;
-        fill_stale_q[fb]    <= 1'b0;
-        fill_cache_q[fb]    <= 1'b0;
-        fill_hit_q[fb]      <= 1'b0;
-        fill_ext_cnt_q[fb]  <= '0;
-        fill_ext_hold_q[fb] <= 1'b0;
-        fill_ext_done_q[fb] <= 1'b0;
-        fill_rvd_cnt_q[fb]  <= '0;
-        fill_ram_done_q[fb] <= 1'b0;
-        fill_out_cnt_q[fb]  <= '0;
-      end else if (fill_entry_en[fb]) begin
-        fill_busy_q[fb]     <= fill_busy_d[fb];
-        fill_older_q[fb]    <= fill_older_d[fb];
-        fill_stale_q[fb]    <= fill_stale_d[fb];
-        fill_cache_q[fb]    <= fill_cache_d[fb];
-        fill_hit_q[fb]      <= fill_hit_d[fb];
-        fill_ext_cnt_q[fb]  <= fill_ext_cnt_d[fb];
-        fill_ext_hold_q[fb] <= fill_ext_hold_d[fb];
-        fill_ext_done_q[fb] <= fill_ext_done_d[fb];
-        fill_rvd_cnt_q[fb]  <= fill_rvd_cnt_d[fb];
-        fill_ram_done_q[fb] <= fill_ram_done_d[fb];
-        fill_out_cnt_q[fb]  <= fill_out_cnt_d[fb];
-      end
-    end
-
-    ////////////////////////////////////////
-    // Fill buffer address / data storage //
-    ////////////////////////////////////////
-
-    assign fill_addr_en[fb]    = fill_alloc[fb];
-    assign fill_way_en[fb]     = (lookup_valid_ic1 & fill_in_ic1[fb]);
-
-    if (ResetAll) begin : g_fill_addr_ra
-      always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (!rst_ni) begin
-          fill_addr_q[fb] <= '0;
-        end else if (fill_addr_en[fb]) begin
-          fill_addr_q[fb] <= lookup_addr_ic0;
-        end
-      end
-    end else begin : g_fill_addr_nr
-      always_ff @(posedge clk_i) begin
-        if (fill_addr_en[fb]) begin
-          fill_addr_q[fb] <= lookup_addr_ic0;
-        end
-      end
-    end
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        fill_way_q[fb]  <= '0;
-      end else if (fill_way_en[fb]) begin
-        fill_way_q[fb]  <= sel_way_ic1;
-      end
-    end
-
-    // Data either comes from the cache or the bus. If there was an ECC error, we must take
-    // the incoming bus data since the cache hit data is corrupted.
-    assign fill_data_d[fb] = fill_hit_ic1[fb] ? hit_data_ic1 :
-                                                {IC_LINE_BEATS{instr_rdata_i}};
-
-    for (genvar b = 0; b < IC_LINE_BEATS; b++) begin : gen_data_buf
-      // Error tracking (per beat)
-      assign fill_err_d[fb][b]   = (fill_rvd_arb[fb] & instr_err_i &
-                                    (fill_rvd_off[fb] == b[IC_LINE_BEATS_W-1:0])) |
-      //                           Hold the error once recorded
-                                   (fill_busy_q[fb] & fill_err_q[fb][b]);
-
-      always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (!rst_ni) begin
-          fill_err_q[fb][b] <= '0;
-        end else if (fill_entry_en[fb]) begin
-          fill_err_q[fb][b] <= fill_err_d[fb][b];
-        end
-      end
-
-      // Enable the relevant part of the data register (or all for cache hits)
-      // Ignore incoming rvalid data when we already have cache hit data
-      assign fill_data_en[fb][b] = fill_hit_ic1[fb] |
-                                   (fill_rvd_arb[fb] & ~fill_hit_q[fb] &
-                                    (fill_rvd_off[fb] == b[IC_LINE_BEATS_W-1:0]));
-
-      if (ResetAll) begin : g_fill_data_ra
-        always_ff @(posedge clk_i or negedge rst_ni) begin
-          if (!rst_ni) begin
-            fill_data_q[fb][b*BUS_SIZE+:BUS_SIZE] <= '0;
-          end else if (fill_data_en[fb][b]) begin
-            fill_data_q[fb][b*BUS_SIZE+:BUS_SIZE] <= fill_data_d[fb][b*BUS_SIZE+:BUS_SIZE];
-          end
-        end
-      end else begin : g_fill_data_nr
-        always_ff @(posedge clk_i) begin
-          if (fill_data_en[fb][b]) begin
-            fill_data_q[fb][b*BUS_SIZE+:BUS_SIZE] <= fill_data_d[fb][b*BUS_SIZE+:BUS_SIZE];
-          end
-        end
-      end
-
-    end
-  end
-
-  ////////////////////////////////
-  // Fill buffer one-hot muxing //
-  ////////////////////////////////
-
-  // External req info
-  always_comb begin
-    fill_ext_req_addr = '0;
-    for (int i = 0; i < NUM_FB; i++) begin
-      if (fill_ext_arb[i]) begin
-        fill_ext_req_addr |= {fill_addr_q[i][ADDR_W-1:IC_LINE_W], fill_ext_off[i]};
-      end
-    end
-  end
-
-  // Cache req info
-  always_comb begin
-    fill_ram_req_addr = '0;
-    fill_ram_req_way  = '0;
-    fill_ram_req_data = '0;
-    for (int i = 0; i < NUM_FB; i++) begin
-      if (fill_ram_arb[i]) begin
-        fill_ram_req_addr |= fill_addr_q[i];
-        fill_ram_req_way  |= fill_way_q[i];
-        fill_ram_req_data |= fill_data_q[i];
-      end
-    end
-  end
-
-  // IF stage output data
-  always_comb begin
-    fill_out_data = '0;
-    fill_out_err  = '0;
-    for (int i = 0; i < NUM_FB; i++) begin
-      if (fill_data_reg[i]) begin
-        fill_out_data |= fill_data_q[i];
-        // Ignore any speculative errors accumulated on cache hits
-        fill_out_err  |= (fill_err_q[i] & ~{IC_LINE_BEATS{fill_hit_q[i]}});
-      end
-    end
-  end
-
-  ///////////////////////
-  // External requests //
-  ///////////////////////
-
-  assign instr_req  = ((~icache_enable_i | branch_or_mispredict) & lookup_grant_ic0) |
-                      (|fill_ext_req);
-
-  assign instr_addr = |fill_ext_req ? fill_ext_req_addr :
-                                      lookup_addr_ic0[ADDR_W-1:BUS_W];
-
-  assign instr_req_o  = instr_req;
-  assign instr_addr_o = {instr_addr[ADDR_W-1:BUS_W],{BUS_W{1'b0}}};
-
-  ////////////////////////
-  // Output data muxing //
-  ////////////////////////
-
-  // Mux between line-width data sources
-  assign line_data = |fill_data_hit ? hit_data_ic1 : fill_out_data;
-  assign line_err  = |fill_data_hit ? {IC_LINE_BEATS{1'b0}} : fill_out_err;
-
-  // Mux the relevant beat of line data, based on the output address
-  always_comb begin
-    line_data_muxed = '0;
-    line_err_muxed  = 1'b0;
-    for (int unsigned i = 0; i < IC_LINE_BEATS; i++) begin
-      // When data has been skidded, the output address is behind by one
-      if ((output_addr_q[IC_LINE_W-1:BUS_W] + {{IC_LINE_BEATS_W-1{1'b0}},skid_valid_q}) ==
-          i[IC_LINE_BEATS_W-1:0]) begin
-        line_data_muxed |= line_data[i*32+:32];
-        line_err_muxed  |= line_err[i];
-      end
-    end
-  end
-
-  // Mux between incoming rdata and the muxed line data
-  assign output_data = |fill_data_rvd ? instr_rdata_i : line_data_muxed;
-  assign output_err  = |fill_data_rvd ? instr_err_i   : line_err_muxed;
-
-  // Output data is valid (from any of the three possible sources). Note that fill_out_arb
-  // must be used here rather than fill_out_req because data can become valid out of order
-  // (e.g. cache hit data can become available ahead of an older outstanding miss).
-  assign data_valid = |fill_out_arb;
-
-  // Skid buffer data
-  assign skid_data_d = output_data[31:16];
-
-  assign skid_en     = data_valid & (ready_i | skid_ready);
-
-  if (ResetAll) begin : g_skid_data_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        skid_data_q <= '0;
-        skid_err_q  <= '0;
-      end else if (skid_en) begin
-        skid_data_q <= skid_data_d;
-        skid_err_q  <= output_err;
-      end
-    end
-  end else begin : g_skid_data_nr
-    always_ff @(posedge clk_i) begin
-      if (skid_en) begin
-        skid_data_q <= skid_data_d;
-        skid_err_q  <= output_err;
-      end
-    end
-  end
-
-  // The data in the skid buffer is ready if it's a complete compressed instruction or if there's
-  // an error (no need to wait for the second half)
-  assign skid_complete_instr = skid_valid_q & ((skid_data_q[1:0] != 2'b11) | skid_err_q);
-
-  // Data can be loaded into the skid buffer for an unaligned uncompressed instruction
-  assign skid_ready = output_addr_q[1] & ~skid_valid_q & (~output_compressed | output_err);
-
-  assign output_ready = (ready_i | skid_ready) & ~skid_complete_instr;
-
-  assign output_compressed = (rdata_o[1:0] != 2'b11);
-
-  assign skid_valid_d =
-      // Branches invalidate the skid buffer
-      branch_or_mispredict ? 1'b0 :
-      // Once valid, the skid buffer stays valid until a compressed instruction realigns the stream
-      (skid_valid_q ? ~(ready_i & ((skid_data_q[1:0] != 2'b11) | skid_err_q)) :
-      // The skid buffer becomes valid when:
-                        // - we branch to an unaligned uncompressed instruction
-                      (data_valid &
-                       (((output_addr_q[1] & (~output_compressed | output_err)) |
-                        // - a compressed instruction misaligns the stream
-                        (~output_addr_q[1] & output_compressed & ~output_err & ready_i)))));
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      skid_valid_q <= 1'b0;
-    end else begin
-      skid_valid_q <= skid_valid_d;
-    end
-  end
-
-  // Signal that valid data is available to the IF stage
-  // Note that if the first half of an unaligned instruction reports an error, we do not need
-  // to wait for the second half
-                        // Compressed instruction completely satisfied by skid buffer
-  assign output_valid = skid_complete_instr |
-                        // Output data available and, output stream aligned, or skid data available,
-                        (data_valid & (~output_addr_q[1] | skid_valid_q |
-                                       // or this is an error or an unaligned compressed instruction
-                                       output_err | (output_data[17:16] != 2'b11)));
-
-  // Update the address on branches and every time an instruction is driven
-  assign output_addr_en = branch_or_mispredict | (ready_i & valid_o);
-
-  // Increment the address by two every time a compressed instruction is popped
-  assign addr_incr_two = output_compressed & ~err_o;
-
-  // Next IF stage PC
-  assign output_addr_incr = (output_addr_q[31:1] +
-                             // Increment address by 4 or 2
-                             {29'd0, ~addr_incr_two, addr_incr_two});
-
-  // Redirect the address on branches or mispredicts
-  assign output_addr_d = branch_i            ? addr_i[31:1] :
-                         branch_mispredict_i ? mispredict_addr_i[31:1] :
-                                               output_addr_incr;
-
-  if (ResetAll) begin : g_output_addr_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        output_addr_q <= '0;
-      end else if (output_addr_en) begin
-        output_addr_q <= output_addr_d;
-      end
-    end
-  end else begin : g_output_addr_nr
-    always_ff @(posedge clk_i) begin
-      if (output_addr_en) begin
-        output_addr_q <= output_addr_d;
-      end
-    end
-  end
-
-  // Mux the data from BUS_SIZE to halfword
-  // This muxing realigns data when instruction words are split across BUS_W e.g.
-  // word 1 |----|*h1*|
-  // word 0 |*h0*|----| --> |*h1*|*h0*|
-  //        31   15   0     31   15   0
-  always_comb begin
-    output_data_lo = '0;
-    for (int unsigned i = 0; i < IC_OUTPUT_BEATS; i++) begin
-      if (output_addr_q[BUS_W-1:1] == i[BUS_W-2:0]) begin
-        output_data_lo |= output_data[i*16+:16];
-      end
-    end
-  end
-
-  always_comb begin
-    output_data_hi = '0;
-    for (int unsigned i = 0; i < IC_OUTPUT_BEATS - 1; i++) begin
-      if (output_addr_q[BUS_W-1:1] == i[BUS_W-2:0]) begin
-        output_data_hi |= output_data[(i+1)*16+:16];
-      end
-    end
-    if (&output_addr_q[BUS_W-1:1]) begin
-      output_data_hi |= output_data[15:0];
-    end
-  end
-
-  assign valid_o     = output_valid & ~branch_mispredict_i;
-  assign rdata_o     = {output_data_hi, (skid_valid_q ? skid_data_q : output_data_lo)};
-  assign addr_o      = {output_addr_q, 1'b0};
-  assign err_o       = (skid_valid_q & skid_err_q) | (~skid_complete_instr & output_err);
-  // Error caused by the second half of a misaligned uncompressed instruction
-  // (only relevant when err_o is set)
-  assign err_plus2_o = skid_valid_q & ~skid_err_q;
-
-  ///////////////////
-  // Invalidations //
-  ///////////////////
-
-
-  // We need to save the invalidation request inside a register. That way we can wait
-  // until we have a valid scrambling key to do it. Since the key itself is needed for
-  // starting to fill in the RAMs and read from them, ICache also needs to stop operating.
-  assign inval_req_d = (inval_req_q | icache_inval_i) & ~(inval_done & inval_prog_q);
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      inval_req_q  <= 1'b0;
-    end else begin
-      inval_req_q  <= inval_req_d;
-    end
-  end
-
-  // This will act like a lock mechanism.
-  // Main idea is to lock the invalidation request until we got a valid scrambling key.
-  assign inval_lock = inval_req_d & ~ic_scr_key_valid_i;
-
-  // Invalidate on reset, or when instructed. If an invalidation request is received while a
-  // previous invalidation is ongoing, it does not need to be restarted. Do not start
-  // this process until inval lock is removed meaning the scrambling key is valid.
-  assign start_inval   = ~inval_lock & (~reset_inval_q | inval_req_q) & ~inval_prog_q ;
-  assign inval_prog_d  = ~inval_lock & (start_inval | (inval_prog_q & ~inval_done));
-  assign inval_done    = &inval_index_q;
-  assign inval_index_d = start_inval ? '0 : (inval_index_q + {{IC_INDEX_W-1{1'b0}},1'b1});
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      inval_prog_q  <= 1'b0;
-      reset_inval_q <= 1'b0;
-    end else begin
-      inval_prog_q  <= inval_prog_d;
-      reset_inval_q <= 1'b1;
-    end
-  end
-
-  if (ResetAll) begin : g_inval_index_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        inval_index_q <= '0;
-      end else if (inval_prog_d) begin
-        inval_index_q <= inval_index_d;
-      end
-    end
-  end else begin : g_inval_index_nr
-    always_ff @(posedge clk_i) begin
-      if (inval_prog_d) begin
-        inval_index_q <= inval_index_d;
-      end
-    end
-  end
-
-  /////////////////
-  // Busy status //
-  /////////////////
-
-  // Only busy (for WFI purposes) while an invalidation is in-progress, or external requests are
-  // outstanding.
-  assign busy_o = inval_req_q | (|(fill_busy_q & ~fill_rvd_done));
-
-  ////////////////
-  // Assertions //
-  ////////////////
-
-  `ASSERT_INIT(size_param_legal, (IC_LINE_SIZE > 32))
-
-  // ECC primitives will need to be changed for different sizes
-  `ASSERT_INIT(ecc_tag_param_legal, (IC_TAG_SIZE <= 27))
-  `ASSERT_INIT(ecc_data_param_legal, !ICacheECC || (BUS_SIZE == 32))
-
-  // Lookups in the tag ram should always give a known result
-  `ASSERT_KNOWN(TagHitKnown,     lookup_valid_ic1 & tag_hit_ic1)
-  `ASSERT_KNOWN(TagInvalidKnown, lookup_valid_ic1 & tag_invalid_ic1)
-
-  // This is only used for the Yosys-based formal flow. Once we have working bind support, we can
-  // get rid of it.
-`ifdef FORMAL
- `ifdef YOSYS
-  // Unfortunately, Yosys doesn't support passing unpacked arrays as ports. Explicitly pack up the
-  // signals we need.
-  logic [NUM_FB-1:0][ADDR_W-1:0] packed_fill_addr_q;
-  always_comb begin
-    for (int i = 0; i < NUM_FB; i++) begin
-      packed_fill_addr_q[i][ADDR_W-1:0] = fill_addr_q[i];
-    end
-  end
-
-  `include "formal_tb_frag.svh"
- `endif
-`endif
-
-
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_if_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_if_stage.sv
deleted file mode 100644
index c430b669..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_if_stage.sv
+++ /dev/null
@@ -1,750 +0,0 @@
-// Copyright lowRISC contributors.
-// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-/**
- * Instruction Fetch Stage
- *
- * Instruction fetch unit: Selection of the next PC, and buffering (sampling) of
- * the read instruction.
- */
-
-`include "prim_assert.sv"
-
-module ibex_if_stage import ibex_pkg::*; #(
-  parameter int unsigned DmHaltAddr        = 32'h1A110800,
-  parameter int unsigned DmExceptionAddr   = 32'h1A110808,
-  parameter bit          DummyInstructions = 1'b0,
-  parameter bit          ICache            = 1'b0,
-  parameter bit          ICacheECC         = 1'b0,
-  parameter int unsigned BusSizeECC        = BUS_SIZE,
-  parameter int unsigned TagSizeECC        = IC_TAG_SIZE,
-  parameter int unsigned LineSizeECC       = IC_LINE_SIZE,
-  parameter bit          PCIncrCheck       = 1'b0,
-  parameter bit          ResetAll          = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed   = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm   = RndCnstLfsrPermDefault,
-  parameter bit          BranchPredictor   = 1'b0
-) (
-  input  logic                         clk_i,
-  input  logic                         rst_ni,
-
-  input  logic [31:0]                  boot_addr_i,              // also used for mtvec
-  input  logic                         req_i,                    // instruction request control
-
-  // instruction cache interface
-  output logic                        instr_req_o,
-  output logic [31:0]                 instr_addr_o,
-  input  logic                        instr_gnt_i,
-  input  logic                        instr_rvalid_i,
-  input  logic [31:0]                 instr_rdata_i,
-  input  logic                        instr_err_i,
-
-  // ICache RAM IO
-  output logic [IC_NUM_WAYS-1:0]      ic_tag_req_o,
-  output logic                        ic_tag_write_o,
-  output logic [IC_INDEX_W-1:0]       ic_tag_addr_o,
-  output logic [TagSizeECC-1:0]       ic_tag_wdata_o,
-  input  logic [TagSizeECC-1:0]       ic_tag_rdata_i [IC_NUM_WAYS],
-  output logic [IC_NUM_WAYS-1:0]      ic_data_req_o,
-  output logic                        ic_data_write_o,
-  output logic [IC_INDEX_W-1:0]       ic_data_addr_o,
-  output logic [LineSizeECC-1:0]      ic_data_wdata_o,
-  input  logic [LineSizeECC-1:0]      ic_data_rdata_i [IC_NUM_WAYS],
-  input  logic                        ic_scr_key_valid_i,
-
-  // output of ID stage
-  output logic                        instr_valid_id_o,         // instr in IF-ID is valid
-  output logic                        instr_new_id_o,           // instr in IF-ID is new
-  output logic [31:0]                 instr_rdata_id_o,         // instr for ID stage
-  output logic [31:0]                 instr_rdata_alu_id_o,     // replicated instr for ID stage
-                                                                // to reduce fan-out
-  output logic [15:0]                 instr_rdata_c_id_o,       // compressed instr for ID stage
-                                                                // (mtval), meaningful only if
-                                                                // instr_is_compressed_id_o = 1'b1
-  output logic                        instr_is_compressed_id_o, // compressed decoder thinks this
-                                                                // is a compressed instr
-  output logic                        instr_bp_taken_o,         // instruction was predicted to be
-                                                                // a taken branch
-  output logic                        instr_fetch_err_o,        // bus error on fetch
-  output logic                        instr_fetch_err_plus2_o,  // bus error misaligned
-  output logic                        illegal_c_insn_id_o,      // compressed decoder thinks this
-                                                                // is an invalid instr
-  output logic                        dummy_instr_id_o,         // Instruction is a dummy
-  output logic [31:0]                 pc_if_o,
-  output logic [31:0]                 pc_id_o,
-  input  logic                        pmp_err_if_i,
-  input  logic                        pmp_err_if_plus2_i,
-
-  // control signals
-  input  logic                        instr_valid_clear_i,      // clear instr valid bit in IF-ID
-  input  logic                        pc_set_i,                 // set the PC to a new value
-  input  pc_sel_e                     pc_mux_i,                 // selector for PC multiplexer
-  input  logic                        nt_branch_mispredict_i,   // Not-taken branch in ID/EX was
-                                                                // mispredicted (predicted taken)
-  input  logic [31:0]                 nt_branch_addr_i,         // Not-taken branch address in ID/EX
-  input  exc_pc_sel_e                 exc_pc_mux_i,             // selects ISR address
-  input  exc_cause_e                  exc_cause,                // selects ISR address for
-                                                                // vectorized interrupt lines
-  input  logic                        dummy_instr_en_i,
-  input  logic [2:0]                  dummy_instr_mask_i,
-  input  logic                        dummy_instr_seed_en_i,
-  input  logic [31:0]                 dummy_instr_seed_i,
-  input  logic                        icache_enable_i,
-  input  logic                        icache_inval_i,
-  output logic                        icache_ecc_error_o,
-
-  // jump and branch target
-  input  logic [31:0]                 branch_target_ex_i,       // branch/jump target address
-
-  // CSRs
-  input  logic [31:0]                 csr_mepc_i,               // PC to restore after handling
-                                                                // the interrupt/exception
-  input  logic [31:0]                 csr_depc_i,               // PC to restore after handling
-                                                                // the debug request
-  input  logic [31:0]                 csr_mtvec_i,              // base PC to jump to on exception
-  output logic                        csr_mtvec_init_o,         // tell CS regfile to init mtvec
-
-  // pipeline stall
-  input  logic                        id_in_ready_i,            // ID stage is ready for new instr
-
-  // misc signals
-  output logic                        pc_mismatch_alert_o,
-  output logic                        if_busy_o                 // IF stage is busy fetching instr
-);
-
-  logic              instr_valid_id_d, instr_valid_id_q;
-  logic              instr_new_id_d, instr_new_id_q;
-
-  // prefetch buffer related signals
-  logic              prefetch_busy;
-  logic              branch_req;
-  logic       [31:0] fetch_addr_n;
-  logic              unused_fetch_addr_n0;
-
-  logic              fetch_valid;
-  logic              fetch_ready;
-  logic       [31:0] fetch_rdata;
-  logic       [31:0] fetch_addr;
-  logic              fetch_err;
-  logic              fetch_err_plus2;
-
-  logic [31:0]       instr_decompressed;
-  logic              illegal_c_insn;
-  logic              instr_is_compressed;
-
-  logic              if_instr_valid;
-  logic       [31:0] if_instr_rdata;
-  logic       [31:0] if_instr_addr;
-  logic              if_instr_bus_err;
-  logic              if_instr_pmp_err;
-  logic              if_instr_err;
-  logic              if_instr_err_plus2;
-
-  logic       [31:0] exc_pc;
-
-  logic        [5:0] irq_id;
-  logic              unused_irq_bit;
-
-  logic              if_id_pipe_reg_we; // IF-ID pipeline reg write enable
-
-  // Dummy instruction signals
-  logic              stall_dummy_instr;
-  logic [31:0]       instr_out;
-  logic              instr_is_compressed_out;
-  logic              illegal_c_instr_out;
-  logic              instr_err_out;
-
-  logic              predict_branch_taken;
-  logic       [31:0] predict_branch_pc;
-
-  ibex_pkg::pc_sel_e pc_mux_internal;
-
-  logic        [7:0] unused_boot_addr;
-  logic        [7:0] unused_csr_mtvec;
-
-  assign unused_boot_addr = boot_addr_i[7:0];
-  assign unused_csr_mtvec = csr_mtvec_i[7:0];
-
-  // extract interrupt ID from exception cause
-  assign irq_id         = {exc_cause};
-  assign unused_irq_bit = irq_id[5];   // MSB distinguishes interrupts from exceptions
-
-  // exception PC selection mux
-  always_comb begin : exc_pc_mux
-    unique case (exc_pc_mux_i)
-      EXC_PC_EXC:     exc_pc = { csr_mtvec_i[31:8], 8'h00                    };
-      EXC_PC_IRQ:     exc_pc = { csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00 };
-      EXC_PC_DBD:     exc_pc = DmHaltAddr;
-      EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr;
-      default:        exc_pc = { csr_mtvec_i[31:8], 8'h00                    };
-    endcase
-  end
-
-  // The Branch predictor can provide a new PC which is internal to if_stage. Only override the mux
-  // select to choose this if the core isn't already trying to set a PC.
-  assign pc_mux_internal =
-    (BranchPredictor && predict_branch_taken && !pc_set_i) ? PC_BP : pc_mux_i;
-
-  // fetch address selection mux
-  always_comb begin : fetch_addr_mux
-    unique case (pc_mux_internal)
-      PC_BOOT: fetch_addr_n = { boot_addr_i[31:8], 8'h00 };
-      PC_JUMP: fetch_addr_n = branch_target_ex_i;
-      PC_EXC:  fetch_addr_n = exc_pc;                       // set PC to exception handler
-      PC_ERET: fetch_addr_n = csr_mepc_i;                   // restore PC when returning from EXC
-      PC_DRET: fetch_addr_n = csr_depc_i;
-      // Without branch predictor will never get pc_mux_internal == PC_BP. We still handle no branch
-      // predictor case here to ensure redundant mux logic isn't synthesised.
-      PC_BP:   fetch_addr_n = BranchPredictor ? predict_branch_pc : { boot_addr_i[31:8], 8'h00 };
-      default: fetch_addr_n = { boot_addr_i[31:8], 8'h00 };
-    endcase
-  end
-
-  // tell CS register file to initialize mtvec on boot
-  assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i;
-
-  if (ICache) begin : gen_icache
-    // Full I-Cache option
-    ibex_icache #(
-      .ICacheECC       (ICacheECC),
-      .ResetAll        (ResetAll),
-      .BusSizeECC      (BusSizeECC),
-      .TagSizeECC      (TagSizeECC),
-      .LineSizeECC     (LineSizeECC)
-    ) icache_i (
-        .clk_i               ( clk_i                      ),
-        .rst_ni              ( rst_ni                     ),
-
-        .req_i               ( req_i                      ),
-
-        .branch_i            ( branch_req                 ),
-        .branch_mispredict_i ( nt_branch_mispredict_i     ),
-        .mispredict_addr_i   ( nt_branch_addr_i           ),
-        .addr_i              ( {fetch_addr_n[31:1], 1'b0} ),
-
-        .ready_i             ( fetch_ready                ),
-        .valid_o             ( fetch_valid                ),
-        .rdata_o             ( fetch_rdata                ),
-        .addr_o              ( fetch_addr                 ),
-        .err_o               ( fetch_err                  ),
-        .err_plus2_o         ( fetch_err_plus2            ),
-
-        .instr_req_o         ( instr_req_o                ),
-        .instr_addr_o        ( instr_addr_o               ),
-        .instr_gnt_i         ( instr_gnt_i                ),
-        .instr_rvalid_i      ( instr_rvalid_i             ),
-        .instr_rdata_i       ( instr_rdata_i              ),
-        .instr_err_i         ( instr_err_i                ),
-
-        .ic_tag_req_o        ( ic_tag_req_o               ),
-        .ic_tag_write_o      ( ic_tag_write_o             ),
-        .ic_tag_addr_o       ( ic_tag_addr_o              ),
-        .ic_tag_wdata_o      ( ic_tag_wdata_o             ),
-        .ic_tag_rdata_i      ( ic_tag_rdata_i             ),
-        .ic_data_req_o       ( ic_data_req_o              ),
-        .ic_data_write_o     ( ic_data_write_o            ),
-        .ic_data_addr_o      ( ic_data_addr_o             ),
-        .ic_data_wdata_o     ( ic_data_wdata_o            ),
-        .ic_data_rdata_i     ( ic_data_rdata_i            ),
-        .ic_scr_key_valid_i  ( ic_scr_key_valid_i         ),
-
-        .icache_enable_i     ( icache_enable_i            ),
-        .icache_inval_i      ( icache_inval_i             ),
-        .busy_o              ( prefetch_busy              ),
-        .ecc_error_o         ( icache_ecc_error_o         )
-    );
-  end else begin : gen_prefetch_buffer
-    // prefetch buffer, caches a fixed number of instructions
-    ibex_prefetch_buffer #(
-      .ResetAll        (ResetAll)
-    ) prefetch_buffer_i (
-        .clk_i               ( clk_i                      ),
-        .rst_ni              ( rst_ni                     ),
-
-        .req_i               ( req_i                      ),
-
-        .branch_i            ( branch_req                 ),
-        .branch_mispredict_i ( nt_branch_mispredict_i     ),
-        .mispredict_addr_i   ( nt_branch_addr_i           ),
-        .addr_i              ( {fetch_addr_n[31:1], 1'b0} ),
-
-        .ready_i             ( fetch_ready                ),
-        .valid_o             ( fetch_valid                ),
-        .rdata_o             ( fetch_rdata                ),
-        .addr_o              ( fetch_addr                 ),
-        .err_o               ( fetch_err                  ),
-        .err_plus2_o         ( fetch_err_plus2            ),
-
-        .instr_req_o         ( instr_req_o                ),
-        .instr_addr_o        ( instr_addr_o               ),
-        .instr_gnt_i         ( instr_gnt_i                ),
-        .instr_rvalid_i      ( instr_rvalid_i             ),
-        .instr_rdata_i       ( instr_rdata_i              ),
-        .instr_err_i         ( instr_err_i                ),
-
-        .busy_o              ( prefetch_busy              )
-    );
-    // ICache tieoffs
-    logic                   unused_icen, unused_icinv, unused_scr_key_valid;
-    logic [TagSizeECC-1:0]  unused_tag_ram_input [IC_NUM_WAYS];
-    logic [LineSizeECC-1:0] unused_data_ram_input [IC_NUM_WAYS];
-    assign unused_icen           = icache_enable_i;
-    assign unused_icinv          = icache_inval_i;
-    assign unused_tag_ram_input  = ic_tag_rdata_i;
-    assign unused_data_ram_input = ic_data_rdata_i;
-    assign unused_scr_key_valid  = ic_scr_key_valid_i;
-    assign ic_tag_req_o          = 'b0;
-    assign ic_tag_write_o        = 'b0;
-    assign ic_tag_addr_o         = 'b0;
-    assign ic_tag_wdata_o        = 'b0;
-    assign ic_data_req_o         = 'b0;
-    assign ic_data_write_o       = 'b0;
-    assign ic_data_addr_o        = 'b0;
-    assign ic_data_wdata_o       = 'b0;
-    assign icache_ecc_error_o    = 'b0;
-
-`ifndef SYNTHESIS
-    // If we don't instantiate an icache and this is a simulation then we have a problem because the
-    // simulator might discard the icache module entirely, including some DPI exports that it
-    // implies. This then causes problems for linking against C++ testbench code that expected them.
-    // As a slightly ugly hack, let's define the DPI functions here (the real versions are defined
-    // in prim_util_get_scramble_params.svh)
-    export "DPI-C" function simutil_get_scramble_key;
-    export "DPI-C" function simutil_get_scramble_nonce;
-    function automatic int simutil_get_scramble_key(output bit [127:0] val);
-      return 0;
-    endfunction
-    function automatic int simutil_get_scramble_nonce(output bit [319:0] nonce);
-      return 0;
-    endfunction
-`endif
-  end
-
-  assign unused_fetch_addr_n0 = fetch_addr_n[0];
-
-  assign branch_req  = pc_set_i | predict_branch_taken;
-
-  assign pc_if_o     = if_instr_addr;
-  assign if_busy_o   = prefetch_busy;
-
-  // PMP errors
-  // An error can come from the instruction address, or the next instruction address for unaligned,
-  // uncompressed instructions.
-  assign if_instr_pmp_err = pmp_err_if_i |
-                            (if_instr_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i);
-
-  // Combine bus errors and pmp errors
-  assign if_instr_err = if_instr_bus_err | if_instr_pmp_err;
-
-  // Capture the second half of the address for errors on the second part of an instruction
-  assign if_instr_err_plus2 = ((if_instr_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i) |
-                               fetch_err_plus2) & ~pmp_err_if_i;
-
-  // compressed instruction decoding, or more precisely compressed instruction
-  // expander
-  //
-  // since it does not matter where we decompress instructions, we do it here
-  // to ease timing closure
-  ibex_compressed_decoder compressed_decoder_i (
-    .clk_i          (clk_i),
-    .rst_ni         (rst_ni),
-    .valid_i        (fetch_valid & ~fetch_err),
-    .instr_i        (if_instr_rdata),
-    .instr_o        (instr_decompressed),
-    .is_compressed_o(instr_is_compressed),
-    .illegal_instr_o(illegal_c_insn)
-  );
-
-  // Dummy instruction insertion
-  if (DummyInstructions) begin : gen_dummy_instr
-    // SEC_CM: CTRL_FLOW.UNPREDICTABLE
-    logic        insert_dummy_instr;
-    logic [31:0] dummy_instr_data;
-
-    ibex_dummy_instr #(
-      .RndCnstLfsrSeed (RndCnstLfsrSeed),
-      .RndCnstLfsrPerm (RndCnstLfsrPerm)
-    ) dummy_instr_i (
-      .clk_i                (clk_i),
-      .rst_ni               (rst_ni),
-      .dummy_instr_en_i     (dummy_instr_en_i),
-      .dummy_instr_mask_i   (dummy_instr_mask_i),
-      .dummy_instr_seed_en_i(dummy_instr_seed_en_i),
-      .dummy_instr_seed_i   (dummy_instr_seed_i),
-      .fetch_valid_i        (fetch_valid),
-      .id_in_ready_i        (id_in_ready_i),
-      .insert_dummy_instr_o (insert_dummy_instr),
-      .dummy_instr_data_o   (dummy_instr_data)
-    );
-
-    // Mux between actual instructions and dummy instructions
-    assign instr_out               = insert_dummy_instr ? dummy_instr_data : instr_decompressed;
-    assign instr_is_compressed_out = insert_dummy_instr ? 1'b0 : instr_is_compressed;
-    assign illegal_c_instr_out     = insert_dummy_instr ? 1'b0 : illegal_c_insn;
-    assign instr_err_out           = insert_dummy_instr ? 1'b0 : if_instr_err;
-
-    // Stall the IF stage if we insert a dummy instruction. The dummy will execute between whatever
-    // is currently in the ID stage and whatever is valid from the prefetch buffer this cycle. The
-    // PC of the dummy instruction will match whatever is next from the prefetch buffer.
-    assign stall_dummy_instr = insert_dummy_instr;
-
-    // Register the dummy instruction indication into the ID stage
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        dummy_instr_id_o <= 1'b0;
-      end else if (if_id_pipe_reg_we) begin
-        dummy_instr_id_o <= insert_dummy_instr;
-      end
-    end
-
-  end else begin : gen_no_dummy_instr
-    logic        unused_dummy_en;
-    logic [2:0]  unused_dummy_mask;
-    logic        unused_dummy_seed_en;
-    logic [31:0] unused_dummy_seed;
-
-    assign unused_dummy_en         = dummy_instr_en_i;
-    assign unused_dummy_mask       = dummy_instr_mask_i;
-    assign unused_dummy_seed_en    = dummy_instr_seed_en_i;
-    assign unused_dummy_seed       = dummy_instr_seed_i;
-    assign instr_out               = instr_decompressed;
-    assign instr_is_compressed_out = instr_is_compressed;
-    assign illegal_c_instr_out     = illegal_c_insn;
-    assign instr_err_out           = if_instr_err;
-    assign stall_dummy_instr       = 1'b0;
-    assign dummy_instr_id_o        = 1'b0;
-  end
-
-  // The ID stage becomes valid as soon as any instruction is registered in the ID stage flops.
-  // Note that the current instruction is squashed by the incoming pc_set_i signal.
-  // Valid is held until it is explicitly cleared (due to an instruction completing or an exception)
-  assign instr_valid_id_d = (if_instr_valid & id_in_ready_i & ~pc_set_i) |
-                            (instr_valid_id_q & ~instr_valid_clear_i);
-  assign instr_new_id_d   = if_instr_valid & id_in_ready_i;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      instr_valid_id_q <= 1'b0;
-      instr_new_id_q   <= 1'b0;
-    end else begin
-      instr_valid_id_q <= instr_valid_id_d;
-      instr_new_id_q   <= instr_new_id_d;
-    end
-  end
-
-  assign instr_valid_id_o = instr_valid_id_q;
-  // Signal when a new instruction enters the ID stage (only used for RVFI signalling).
-  assign instr_new_id_o   = instr_new_id_q;
-
-  // IF-ID pipeline registers, frozen when the ID stage is stalled
-  assign if_id_pipe_reg_we = instr_new_id_d;
-
-  if (ResetAll) begin : g_instr_rdata_ra
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        instr_rdata_id_o         <= '0;
-        instr_rdata_alu_id_o     <= '0;
-        instr_fetch_err_o        <= '0;
-        instr_fetch_err_plus2_o  <= '0;
-        instr_rdata_c_id_o       <= '0;
-        instr_is_compressed_id_o <= '0;
-        illegal_c_insn_id_o      <= '0;
-        pc_id_o                  <= '0;
-      end else if (if_id_pipe_reg_we) begin
-        instr_rdata_id_o         <= instr_out;
-        // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
-        instr_rdata_alu_id_o     <= instr_out;
-        instr_fetch_err_o        <= instr_err_out;
-        instr_fetch_err_plus2_o  <= if_instr_err_plus2;
-        instr_rdata_c_id_o       <= if_instr_rdata[15:0];
-        instr_is_compressed_id_o <= instr_is_compressed_out;
-        illegal_c_insn_id_o      <= illegal_c_instr_out;
-        pc_id_o                  <= pc_if_o;
-      end
-    end
-  end else begin : g_instr_rdata_nr
-    always_ff @(posedge clk_i) begin
-      if (if_id_pipe_reg_we) begin
-        instr_rdata_id_o         <= instr_out;
-        // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
-        instr_rdata_alu_id_o     <= instr_out;
-        instr_fetch_err_o        <= instr_err_out;
-        instr_fetch_err_plus2_o  <= if_instr_err_plus2;
-        instr_rdata_c_id_o       <= if_instr_rdata[15:0];
-        instr_is_compressed_id_o <= instr_is_compressed_out;
-        illegal_c_insn_id_o      <= illegal_c_instr_out;
-        pc_id_o                  <= pc_if_o;
-      end
-    end
-  end
-
-  // Check for expected increments of the PC when security hardening enabled
-  if (PCIncrCheck) begin : g_secure_pc
-    // SEC_CM: PC.CTRL_FLOW.CONSISTENCY
-    logic [31:0] prev_instr_addr_incr, prev_instr_addr_incr_buf;
-    logic        prev_instr_seq_q, prev_instr_seq_d;
-
-    // Do not check for sequential increase after a branch, jump, exception, interrupt or debug
-    // request, all of which will set branch_req. Also do not check after reset or for dummys.
-    assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) &
-        ~branch_req & ~if_instr_err & ~stall_dummy_instr;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        prev_instr_seq_q <= 1'b0;
-      end else begin
-        prev_instr_seq_q <= prev_instr_seq_d;
-      end
-    end
-
-    assign prev_instr_addr_incr = pc_id_o + (instr_is_compressed_id_o ? 32'd2 : 32'd4);
-
-    // Buffer anticipated next PC address to ensure optimiser cannot remove the check.
-    prim_buf #(.Width(32)) u_prev_instr_addr_incr_buf (
-      .in_i (prev_instr_addr_incr),
-      .out_o(prev_instr_addr_incr_buf)
-    );
-
-    // Check that the address equals the previous address +2/+4
-    assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr_buf);
-
-  end else begin : g_no_secure_pc
-    assign pc_mismatch_alert_o = 1'b0;
-  end
-
-  if (BranchPredictor) begin : g_branch_predictor
-    logic [31:0] instr_skid_data_q;
-    logic [31:0] instr_skid_addr_q;
-    logic        instr_skid_bp_taken_q;
-    logic        instr_skid_valid_q, instr_skid_valid_d;
-    logic        instr_skid_en;
-    logic        instr_bp_taken_q, instr_bp_taken_d;
-
-    logic        predict_branch_taken_raw;
-
-    // ID stages needs to know if branch was predicted taken so it can signal mispredicts
-    if (ResetAll) begin : g_bp_taken_ra
-      always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (!rst_ni) begin
-          instr_bp_taken_q <= '0;
-        end else if (if_id_pipe_reg_we) begin
-          instr_bp_taken_q <= instr_bp_taken_d;
-        end
-      end
-    end else begin : g_bp_taken_nr
-      always_ff @(posedge clk_i) begin
-        if (if_id_pipe_reg_we) begin
-          instr_bp_taken_q <= instr_bp_taken_d;
-        end
-      end
-    end
-
-    // When branch prediction is enabled a skid buffer between the IF and ID/EX stage is introduced.
-    // If an instruction in IF is predicted to be a taken branch and ID/EX is not ready the
-    // instruction in IF is moved to the skid buffer which becomes the output of the IF stage until
-    // the ID/EX stage accepts the instruction. The skid buffer is required as otherwise the ID/EX
-    // ready signal is coupled to the instr_req_o output which produces a feedthrough path from
-    // data_gnt_i -> instr_req_o (which needs to be avoided as for some interconnects this will
-    // result in a combinational loop).
-
-    assign instr_skid_en = predict_branch_taken & ~pc_set_i & ~id_in_ready_i & ~instr_skid_valid_q;
-
-    assign instr_skid_valid_d = (instr_skid_valid_q & ~id_in_ready_i & ~stall_dummy_instr) |
-                                instr_skid_en;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        instr_skid_valid_q <= 1'b0;
-      end else begin
-        instr_skid_valid_q <= instr_skid_valid_d;
-      end
-    end
-
-    if (ResetAll) begin : g_instr_skid_ra
-      always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (!rst_ni) begin
-          instr_skid_bp_taken_q <= '0;
-          instr_skid_data_q     <= '0;
-          instr_skid_addr_q     <= '0;
-        end else if (instr_skid_en) begin
-          instr_skid_bp_taken_q <= predict_branch_taken;
-          instr_skid_data_q     <= fetch_rdata;
-          instr_skid_addr_q     <= fetch_addr;
-        end
-      end
-    end else begin : g_instr_skid_nr
-      always_ff @(posedge clk_i) begin
-        if (instr_skid_en) begin
-          instr_skid_bp_taken_q <= predict_branch_taken;
-          instr_skid_data_q     <= fetch_rdata;
-          instr_skid_addr_q     <= fetch_addr;
-        end
-      end
-    end
-
-    ibex_branch_predict branch_predict_i (
-      .clk_i        (clk_i),
-      .rst_ni       (rst_ni),
-      .fetch_rdata_i(fetch_rdata),
-      .fetch_pc_i   (fetch_addr),
-      .fetch_valid_i(fetch_valid),
-
-      .predict_branch_taken_o(predict_branch_taken_raw),
-      .predict_branch_pc_o   (predict_branch_pc)
-    );
-
-    // If there is an instruction in the skid buffer there must be no branch prediction.
-    // Instructions are only placed in the skid after they have been predicted to be a taken branch
-    // so with the skid valid any prediction has already occurred.
-    // Do not branch predict on instruction errors.
-    assign predict_branch_taken = predict_branch_taken_raw & ~instr_skid_valid_q & ~fetch_err;
-
-    assign if_instr_valid   = fetch_valid | (instr_skid_valid_q & ~nt_branch_mispredict_i);
-    assign if_instr_rdata   = instr_skid_valid_q ? instr_skid_data_q : fetch_rdata;
-    assign if_instr_addr    = instr_skid_valid_q ? instr_skid_addr_q : fetch_addr;
-
-    // Don't branch predict on instruction error so only instructions without errors end up in the
-    // skid buffer.
-    assign if_instr_bus_err = ~instr_skid_valid_q & fetch_err;
-    assign instr_bp_taken_d = instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken;
-
-    assign fetch_ready = id_in_ready_i & ~stall_dummy_instr & ~instr_skid_valid_q;
-
-    assign instr_bp_taken_o = instr_bp_taken_q;
-
-    `ASSERT(NoPredictSkid, instr_skid_valid_q |-> ~predict_branch_taken)
-    `ASSERT(NoPredictIllegal, predict_branch_taken |-> ~illegal_c_insn)
-  end else begin : g_no_branch_predictor
-    assign instr_bp_taken_o     = 1'b0;
-    assign predict_branch_taken = 1'b0;
-    assign predict_branch_pc    = 32'b0;
-
-    assign if_instr_valid = fetch_valid;
-    assign if_instr_rdata = fetch_rdata;
-    assign if_instr_addr  = fetch_addr;
-    assign if_instr_bus_err = fetch_err;
-    assign fetch_ready = id_in_ready_i & ~stall_dummy_instr;
-  end
-
-  ////////////////
-  // Assertions //
-  ////////////////
-
-  // Selectors must be known/valid.
-  `ASSERT_KNOWN(IbexExcPcMuxKnown, exc_pc_mux_i)
-
-  if (BranchPredictor) begin : g_branch_predictor_asserts
-    `ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside {
-        PC_BOOT,
-        PC_JUMP,
-        PC_EXC,
-        PC_ERET,
-        PC_DRET,
-        PC_BP},
-      pc_set_i)
-
-`ifdef INC_ASSERT
-    /**
-     * Checks for branch prediction interface to fetch_fifo/icache
-     *
-     * The interface has two signals:
-     * - predicted_branch_i: When set with a branch (branch_i) indicates the branch is a predicted
-     *   one, it should be ignored when a branch_i isn't set.
-     * - branch_mispredict_i: Indicates the previously predicted branch was mis-predicted and
-     *   execution should resume with the not-taken side of the branch (i.e. continue with the PC
-     *   that followed the predicted branch). This must be raised before the instruction that is
-     *   made available following a predicted branch is accepted (Following a cycle with branch_i
-     *   & predicted_branch_i, branch_mispredict_i can only be asserted before or on the same cycle
-     *   as seeing fetch_valid & fetch_ready). When branch_mispredict_i is asserted, fetch_valid may
-     *   be asserted in response. If fetch_valid is asserted on the same cycle as
-     *   branch_mispredict_i this indicates the fetch_fifo/icache has the not-taken side of the
-     *   branch immediately ready for use
-     */
-    logic        predicted_branch_live_q, predicted_branch_live_d;
-    logic [31:0] predicted_branch_nt_pc_q, predicted_branch_nt_pc_d;
-    logic [31:0] awaiting_instr_after_mispredict_q, awaiting_instr_after_mispredict_d;
-    logic [31:0] next_pc;
-
-    logic mispredicted, mispredicted_d, mispredicted_q;
-
-    assign next_pc = fetch_addr + (instr_is_compressed_out ? 32'd2 : 32'd4);
-
-    logic predicted_branch;
-
-    // pc_set_i takes precendence over branch prediction
-    assign predicted_branch = predict_branch_taken & ~pc_set_i;
-
-    always_comb begin
-      predicted_branch_live_d = predicted_branch_live_q;
-      mispredicted_d          = mispredicted_q;
-
-      if (branch_req & predicted_branch) begin
-        predicted_branch_live_d = 1'b1;
-        mispredicted_d          = 1'b0;
-      end else if (predicted_branch_live_q) begin
-        if (fetch_valid & fetch_ready) begin
-          predicted_branch_live_d = 1'b0;
-        end else if (nt_branch_mispredict_i) begin
-          mispredicted_d = 1'b1;
-        end
-      end
-    end
-
-    always @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        predicted_branch_live_q <= 1'b0;
-        mispredicted_q          <= 1'b0;
-      end else begin
-        predicted_branch_live_q <= predicted_branch_live_d;
-        mispredicted_q          <= mispredicted_d;
-      end
-    end
-
-    always @(posedge clk_i) begin
-      if (branch_req & predicted_branch) begin
-        predicted_branch_nt_pc_q <= next_pc;
-      end
-    end
-
-    // Must only see mispredict after we've performed a predicted branch but before we've accepted
-    // any instruction (with fetch_ready & fetch_valid) that follows that predicted branch.
-    `ASSERT(MispredictOnlyImmediatelyAfterPredictedBranch,
-      nt_branch_mispredict_i |-> predicted_branch_live_q)
-    // Check that on mispredict we get the correct PC for the non-taken side of the branch when
-    // prefetch buffer/icache makes that PC available.
-    `ASSERT(CorrectPCOnMispredict,
-      predicted_branch_live_q & mispredicted_d & fetch_valid |->
-      fetch_addr == predicted_branch_nt_pc_q)
-    // Must not signal mispredict over multiple cycles but it's possible to have back to back
-    // mispredicts for different branches (core signals mispredict, prefetch buffer/icache immediate
-    // has not-taken side of the mispredicted branch ready, which itself is a predicted branch,
-    // following cycle core signal that that branch has mispredicted).
-    `ASSERT(MispredictSingleCycle,
-      nt_branch_mispredict_i & ~(fetch_valid & fetch_ready) |=> ~nt_branch_mispredict_i)
-    // Note that we should never see a mispredict and an incoming branch on the same cycle.
-    // The mispredict also cancels any predicted branch so overall branch_req must be low.
-    `ASSERT(NoMispredBranch, nt_branch_mispredict_i |-> ~branch_req)
-`endif
-
-  end else begin : g_no_branch_predictor_asserts
-    `ASSERT_IF(IbexPcMuxValid, pc_mux_internal inside {
-        PC_BOOT,
-        PC_JUMP,
-        PC_EXC,
-        PC_ERET,
-        PC_DRET},
-      pc_set_i)
-  end
-
-  // Boot address must be aligned to 256 bytes.
-  `ASSERT(IbexBootAddrUnaligned, boot_addr_i[7:0] == 8'h00)
-
-  // Address must not contain X when request is sent.
-  `ASSERT(IbexInstrAddrUnknown, instr_req_o |-> !$isunknown(instr_addr_o))
-
-  // Address must be word aligned when request is sent.
-  `ASSERT(IbexInstrAddrUnaligned, instr_req_o |-> (instr_addr_o[1:0] == 2'b00))
-
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_lockstep.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_lockstep.sv
deleted file mode 100644
index 4f986d0c..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_lockstep.sv
+++ /dev/null
@@ -1,491 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// Ibex lockstep module
-// This module instantiates a second copy of the core logic, and compares it's outputs against
-// those from the main core. The second core runs synchronously with the main core, delayed by
-// LockstepOffset cycles.
-
-// SEC_CM: LOGIC.SHADOW
-module ibex_lockstep import ibex_pkg::*; #(
-  parameter int unsigned LockstepOffset    = 2,
-  parameter bit          PMPEnable         = 1'b0,
-  parameter int unsigned PMPGranularity    = 0,
-  parameter int unsigned PMPNumRegions     = 4,
-  parameter int unsigned MHPMCounterNum    = 0,
-  parameter int unsigned MHPMCounterWidth  = 40,
-  parameter bit          RV32E             = 1'b0,
-  parameter rv32m_e      RV32M             = RV32MFast,
-  parameter rv32b_e      RV32B             = RV32BNone,
-  parameter bit          BranchTargetALU   = 1'b0,
-  parameter bit          WritebackStage    = 1'b0,
-  parameter bit          ICache            = 1'b0,
-  parameter bit          ICacheECC         = 1'b0,
-  parameter int unsigned BusSizeECC        = BUS_SIZE,
-  parameter int unsigned TagSizeECC        = IC_TAG_SIZE,
-  parameter int unsigned LineSizeECC       = IC_LINE_SIZE,
-  parameter bit          BranchPredictor   = 1'b0,
-  parameter bit          DbgTriggerEn      = 1'b0,
-  parameter int unsigned DbgHwBreakNum     = 1,
-  parameter bit          ResetAll          = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed   = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm   = RndCnstLfsrPermDefault,
-  parameter bit          SecureIbex        = 1'b0,
-  parameter bit          DummyInstructions = 1'b0,
-  parameter bit          RegFileECC        = 1'b0,
-  parameter int unsigned RegFileDataWidth  = 32,
-  parameter int unsigned DmHaltAddr        = 32'h1A110800,
-  parameter int unsigned DmExceptionAddr   = 32'h1A110808
-) (
-  input  logic                         clk_i,
-  input  logic                         rst_ni,
-
-  input  logic [31:0]                  hart_id_i,
-  input  logic [31:0]                  boot_addr_i,
-
-  input  logic                         instr_req_i,
-  input  logic                         instr_gnt_i,
-  input  logic                         instr_rvalid_i,
-  input  logic [31:0]                  instr_addr_i,
-  input  logic [31:0]                  instr_rdata_i,
-  input  logic [6:0]                   instr_rdata_intg_i,
-  input  logic                         instr_err_i,
-
-  input  logic                         data_req_i,
-  input  logic                         data_gnt_i,
-  input  logic                         data_rvalid_i,
-  input  logic                         data_we_i,
-  input  logic [3:0]                   data_be_i,
-  input  logic [31:0]                  data_addr_i,
-  input  logic [31:0]                  data_wdata_i,
-  output logic [6:0]                   data_wdata_intg_o,
-  input  logic [31:0]                  data_rdata_i,
-  input  logic [6:0]                   data_rdata_intg_i,
-  input  logic                         data_err_i,
-
-  input  logic                         dummy_instr_id_i,
-  input  logic [4:0]                   rf_raddr_a_i,
-  input  logic [4:0]                   rf_raddr_b_i,
-  input  logic [4:0]                   rf_waddr_wb_i,
-  input  logic                         rf_we_wb_i,
-  input  logic [RegFileDataWidth-1:0]  rf_wdata_wb_ecc_i,
-  input  logic [RegFileDataWidth-1:0]  rf_rdata_a_ecc_i,
-  input  logic [RegFileDataWidth-1:0]  rf_rdata_b_ecc_i,
-
-  input  logic [IC_NUM_WAYS-1:0]       ic_tag_req_i,
-  input  logic                         ic_tag_write_i,
-  input  logic [IC_INDEX_W-1:0]        ic_tag_addr_i,
-  input  logic [TagSizeECC-1:0]        ic_tag_wdata_i,
-  input  logic [TagSizeECC-1:0]        ic_tag_rdata_i [IC_NUM_WAYS],
-  input  logic [IC_NUM_WAYS-1:0]       ic_data_req_i,
-  input  logic                         ic_data_write_i,
-  input  logic [IC_INDEX_W-1:0]        ic_data_addr_i,
-  input  logic [LineSizeECC-1:0]       ic_data_wdata_i,
-  input  logic [LineSizeECC-1:0]       ic_data_rdata_i [IC_NUM_WAYS],
-  input  logic                         ic_scr_key_valid_i,
-
-  input  logic                         irq_software_i,
-  input  logic                         irq_timer_i,
-  input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
-  input  logic                         irq_nm_i,
-  input  logic                         irq_pending_i,
-
-  input  logic                         debug_req_i,
-  input  crash_dump_t                  crash_dump_i,
-  input  logic                         double_fault_seen_i,
-
-  input  fetch_enable_t                fetch_enable_i,
-  output logic                         alert_minor_o,
-  output logic                         alert_major_internal_o,
-  output logic                         alert_major_bus_o,
-  input  logic                         icache_inval_i,
-  input  logic                         core_busy_i,
-  input  logic                         test_en_i,
-  input  logic                         scan_rst_ni
-);
-
-  localparam int unsigned LockstepOffsetW = $clog2(LockstepOffset);
-  // Core outputs are delayed for an extra cycle due to shadow output registers
-  localparam int unsigned OutputsOffset = LockstepOffset + 1;
-
-  //////////////////////
-  // Reset generation //
-  //////////////////////
-
-  // Upon reset, the comparison is stopped and the shadow core is reset, both immediately. A
-  // counter is started. After LockstepOffset clock cycles:
-  // - The counter is stopped.
-  // - The reset of the shadow core is synchronously released.
-  // The comparison is started in the following clock cycle.
-
-  logic [LockstepOffsetW-1:0] rst_shadow_cnt_d, rst_shadow_cnt_q, rst_shadow_cnt_incr;
-  // Internally generated resets cause IMPERFECTSCH warnings
-  /* verilator lint_off IMPERFECTSCH */
-  logic                       rst_shadow_set_d, rst_shadow_set_q;
-  logic                       rst_shadow_n, enable_cmp_q;
-  /* verilator lint_on IMPERFECTSCH */
-
-  assign rst_shadow_cnt_incr = rst_shadow_cnt_q + LockstepOffsetW'(1);
-
-  assign rst_shadow_set_d = (rst_shadow_cnt_q == LockstepOffsetW'(LockstepOffset - 1));
-  assign rst_shadow_cnt_d = rst_shadow_set_d ? rst_shadow_cnt_q : rst_shadow_cnt_incr;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      rst_shadow_cnt_q <= '0;
-      enable_cmp_q     <= '0;
-    end else begin
-      rst_shadow_cnt_q <= rst_shadow_cnt_d;
-      enable_cmp_q     <= rst_shadow_set_q;
-    end
-  end
-
-  // The primitives below are used to place size-only constraints in order to prevent
-  // synthesis optimizations and preserve anchor points for constraining backend tools.
-  prim_flop #(
-    .Width(1),
-    .ResetValue(1'b0)
-  ) u_prim_rst_shadow_set_flop (
-    .clk_i (clk_i),
-    .rst_ni(rst_ni),
-    .d_i   (rst_shadow_set_d),
-    .q_o   (rst_shadow_set_q)
-  );
-
-  prim_clock_mux2 #(
-    .NoFpgaBufG(1'b1)
-  ) u_prim_rst_shadow_n_mux2 (
-    .clk0_i(rst_shadow_set_q),
-    .clk1_i(scan_rst_ni),
-    .sel_i (test_en_i),
-    .clk_o (rst_shadow_n)
-  );
-
-  //////////////////
-  // Input delays //
-  //////////////////
-
-  typedef struct packed {
-    logic                        instr_gnt;
-    logic                        instr_rvalid;
-    logic [31:0]                 instr_rdata;
-    logic                        instr_err;
-    logic                        data_gnt;
-    logic                        data_rvalid;
-    logic [31:0]                 data_rdata;
-    logic                        data_err;
-    logic [RegFileDataWidth-1:0] rf_rdata_a_ecc;
-    logic [RegFileDataWidth-1:0] rf_rdata_b_ecc;
-    logic                        irq_software;
-    logic                        irq_timer;
-    logic                        irq_external;
-    logic [14:0]                 irq_fast;
-    logic                        irq_nm;
-    logic                        debug_req;
-    fetch_enable_t               fetch_enable;
-    logic                        ic_scr_key_valid;
-  } delayed_inputs_t;
-
-  delayed_inputs_t [LockstepOffset-1:0] shadow_inputs_q;
-  delayed_inputs_t                      shadow_inputs_in;
-  logic [6:0]                           instr_rdata_intg_q, data_rdata_intg_q;
-  // Packed arrays must be dealt with separately
-  logic [TagSizeECC-1:0]                shadow_tag_rdata_q [IC_NUM_WAYS][LockstepOffset];
-  logic [LineSizeECC-1:0]               shadow_data_rdata_q [IC_NUM_WAYS][LockstepOffset];
-
-  // Assign the inputs to the delay structure
-  assign shadow_inputs_in.instr_gnt        = instr_gnt_i;
-  assign shadow_inputs_in.instr_rvalid     = instr_rvalid_i;
-  assign shadow_inputs_in.instr_rdata      = instr_rdata_i;
-  assign shadow_inputs_in.instr_err        = instr_err_i;
-  assign shadow_inputs_in.data_gnt         = data_gnt_i;
-  assign shadow_inputs_in.data_rvalid      = data_rvalid_i;
-  assign shadow_inputs_in.data_rdata       = data_rdata_i;
-  assign shadow_inputs_in.data_err         = data_err_i;
-  assign shadow_inputs_in.rf_rdata_a_ecc   = rf_rdata_a_ecc_i;
-  assign shadow_inputs_in.rf_rdata_b_ecc   = rf_rdata_b_ecc_i;
-  assign shadow_inputs_in.irq_software     = irq_software_i;
-  assign shadow_inputs_in.irq_timer        = irq_timer_i;
-  assign shadow_inputs_in.irq_external     = irq_external_i;
-  assign shadow_inputs_in.irq_fast         = irq_fast_i;
-  assign shadow_inputs_in.irq_nm           = irq_nm_i;
-  assign shadow_inputs_in.debug_req        = debug_req_i;
-  assign shadow_inputs_in.fetch_enable     = fetch_enable_i;
-  assign shadow_inputs_in.ic_scr_key_valid = ic_scr_key_valid_i;
-
-  // Delay the inputs
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      instr_rdata_intg_q <= '0;
-      data_rdata_intg_q  <= '0;
-      for (int unsigned i = 0; i < LockstepOffset; i++) begin
-        shadow_inputs_q[i]     <= delayed_inputs_t'('0);
-        shadow_tag_rdata_q[i]  <= '{default: 0};
-        shadow_data_rdata_q[i] <= '{default: 0};
-      end
-    end else begin
-      instr_rdata_intg_q <= instr_rdata_intg_i;
-      data_rdata_intg_q  <= data_rdata_intg_i;
-      for (int unsigned i = 0; i < LockstepOffset - 1; i++) begin
-        shadow_inputs_q[i]     <= shadow_inputs_q[i+1];
-        shadow_tag_rdata_q[i]  <= shadow_tag_rdata_q[i+1];
-        shadow_data_rdata_q[i] <= shadow_data_rdata_q[i+1];
-      end
-      shadow_inputs_q[LockstepOffset-1]     <= shadow_inputs_in;
-      shadow_tag_rdata_q[LockstepOffset-1]  <= ic_tag_rdata_i;
-      shadow_data_rdata_q[LockstepOffset-1] <= ic_data_rdata_i;
-    end
-  end
-
-  ////////////////////////////
-  // Bus integrity checking //
-  ////////////////////////////
-
-  // SEC_CM: BUS.INTEGRITY
-  logic        bus_intg_err;
-  logic [1:0]  instr_intg_err, data_intg_err;
-  logic [31:0] unused_wdata;
-
-  // Checks on incoming data
-  prim_secded_inv_39_32_dec u_instr_intg_dec (
-    .data_i     ({instr_rdata_intg_q, shadow_inputs_q[LockstepOffset-1].instr_rdata}),
-    .data_o     (),
-    .syndrome_o (),
-    .err_o      (instr_intg_err)
-  );
-
-  prim_secded_inv_39_32_dec u_data_intg_dec (
-    .data_i     ({data_rdata_intg_q, shadow_inputs_q[LockstepOffset-1].data_rdata}),
-    .data_o     (),
-    .syndrome_o (),
-    .err_o      (data_intg_err)
-  );
-
-  assign bus_intg_err = (shadow_inputs_q[LockstepOffset-1].instr_rvalid & |instr_intg_err) |
-                        (shadow_inputs_q[LockstepOffset-1].data_rvalid  & |data_intg_err);
-
-  // Generate integrity bits
-  prim_secded_inv_39_32_enc u_data_gen (
-    .data_i (data_wdata_i),
-    .data_o ({data_wdata_intg_o, unused_wdata})
-  );
-
-  ///////////////////
-  // Output delays //
-  ///////////////////
-
-  typedef struct packed {
-    logic                        instr_req;
-    logic [31:0]                 instr_addr;
-    logic                        data_req;
-    logic                        data_we;
-    logic [3:0]                  data_be;
-    logic [31:0]                 data_addr;
-    logic [31:0]                 data_wdata;
-    logic                        dummy_instr_id;
-    logic [4:0]                  rf_raddr_a;
-    logic [4:0]                  rf_raddr_b;
-    logic [4:0]                  rf_waddr_wb;
-    logic                        rf_we_wb;
-    logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc;
-    logic [IC_NUM_WAYS-1:0]      ic_tag_req;
-    logic                        ic_tag_write;
-    logic [IC_INDEX_W-1:0]       ic_tag_addr;
-    logic [TagSizeECC-1:0]       ic_tag_wdata;
-    logic [IC_NUM_WAYS-1:0]      ic_data_req;
-    logic                        ic_data_write;
-    logic [IC_INDEX_W-1:0]       ic_data_addr;
-    logic [LineSizeECC-1:0]      ic_data_wdata;
-    logic                        irq_pending;
-    crash_dump_t                 crash_dump;
-    logic                        double_fault_seen;
-    logic                        icache_inval;
-    logic                        core_busy;
-  } delayed_outputs_t;
-
-  delayed_outputs_t [OutputsOffset-1:0]  core_outputs_q;
-  delayed_outputs_t                      core_outputs_in;
-  delayed_outputs_t                      shadow_outputs_d, shadow_outputs_q;
-
-  // Assign core outputs to the structure
-  assign core_outputs_in.instr_req           = instr_req_i;
-  assign core_outputs_in.instr_addr          = instr_addr_i;
-  assign core_outputs_in.data_req            = data_req_i;
-  assign core_outputs_in.data_we             = data_we_i;
-  assign core_outputs_in.data_be             = data_be_i;
-  assign core_outputs_in.data_addr           = data_addr_i;
-  assign core_outputs_in.data_wdata          = data_wdata_i;
-  assign core_outputs_in.dummy_instr_id      = dummy_instr_id_i;
-  assign core_outputs_in.rf_raddr_a          = rf_raddr_a_i;
-  assign core_outputs_in.rf_raddr_b          = rf_raddr_b_i;
-  assign core_outputs_in.rf_waddr_wb         = rf_waddr_wb_i;
-  assign core_outputs_in.rf_we_wb            = rf_we_wb_i;
-  assign core_outputs_in.rf_wdata_wb_ecc     = rf_wdata_wb_ecc_i;
-  assign core_outputs_in.ic_tag_req          = ic_tag_req_i;
-  assign core_outputs_in.ic_tag_write        = ic_tag_write_i;
-  assign core_outputs_in.ic_tag_addr         = ic_tag_addr_i;
-  assign core_outputs_in.ic_tag_wdata        = ic_tag_wdata_i;
-  assign core_outputs_in.ic_data_req         = ic_data_req_i;
-  assign core_outputs_in.ic_data_write       = ic_data_write_i;
-  assign core_outputs_in.ic_data_addr        = ic_data_addr_i;
-  assign core_outputs_in.ic_data_wdata       = ic_data_wdata_i;
-  assign core_outputs_in.irq_pending         = irq_pending_i;
-  assign core_outputs_in.crash_dump          = crash_dump_i;
-  assign core_outputs_in.double_fault_seen   = double_fault_seen_i;
-  assign core_outputs_in.icache_inval        = icache_inval_i;
-  assign core_outputs_in.core_busy           = core_busy_i;
-
-  // Delay the outputs
-  always_ff @(posedge clk_i) begin
-    for (int unsigned i = 0; i < OutputsOffset - 1; i++) begin
-      core_outputs_q[i] <= core_outputs_q[i+1];
-    end
-    core_outputs_q[OutputsOffset-1] <= core_outputs_in;
-  end
-
-  ///////////////////////////////
-  // Shadow core instantiation //
-  ///////////////////////////////
-
-  logic shadow_alert_minor, shadow_alert_major;
-
-  ibex_core #(
-    .PMPEnable         ( PMPEnable         ),
-    .PMPGranularity    ( PMPGranularity    ),
-    .PMPNumRegions     ( PMPNumRegions     ),
-    .MHPMCounterNum    ( MHPMCounterNum    ),
-    .MHPMCounterWidth  ( MHPMCounterWidth  ),
-    .RV32E             ( RV32E             ),
-    .RV32M             ( RV32M             ),
-    .RV32B             ( RV32B             ),
-    .BranchTargetALU   ( BranchTargetALU   ),
-    .ICache            ( ICache            ),
-    .ICacheECC         ( ICacheECC         ),
-    .BusSizeECC        ( BusSizeECC        ),
-    .TagSizeECC        ( TagSizeECC        ),
-    .LineSizeECC       ( LineSizeECC       ),
-    .BranchPredictor   ( BranchPredictor   ),
-    .DbgTriggerEn      ( DbgTriggerEn      ),
-    .DbgHwBreakNum     ( DbgHwBreakNum     ),
-    .WritebackStage    ( WritebackStage    ),
-    .ResetAll          ( ResetAll          ),
-    .RndCnstLfsrSeed   ( RndCnstLfsrSeed   ),
-    .RndCnstLfsrPerm   ( RndCnstLfsrPerm   ),
-    .SecureIbex        ( SecureIbex        ),
-    .DummyInstructions ( DummyInstructions ),
-    .RegFileECC        ( RegFileECC        ),
-    .RegFileDataWidth  ( RegFileDataWidth  ),
-    .DmHaltAddr        ( DmHaltAddr        ),
-    .DmExceptionAddr   ( DmExceptionAddr   )
-  ) u_shadow_core (
-    .clk_i               (clk_i),
-    .rst_ni              (rst_shadow_n),
-
-    .hart_id_i           (hart_id_i),
-    .boot_addr_i         (boot_addr_i),
-
-    .instr_req_o         (shadow_outputs_d.instr_req),
-    .instr_gnt_i         (shadow_inputs_q[0].instr_gnt),
-    .instr_rvalid_i      (shadow_inputs_q[0].instr_rvalid),
-    .instr_addr_o        (shadow_outputs_d.instr_addr),
-    .instr_rdata_i       (shadow_inputs_q[0].instr_rdata),
-    .instr_err_i         (shadow_inputs_q[0].instr_err),
-
-    .data_req_o          (shadow_outputs_d.data_req),
-    .data_gnt_i          (shadow_inputs_q[0].data_gnt),
-    .data_rvalid_i       (shadow_inputs_q[0].data_rvalid),
-    .data_we_o           (shadow_outputs_d.data_we),
-    .data_be_o           (shadow_outputs_d.data_be),
-    .data_addr_o         (shadow_outputs_d.data_addr),
-    .data_wdata_o        (shadow_outputs_d.data_wdata),
-    .data_rdata_i        (shadow_inputs_q[0].data_rdata),
-    .data_err_i          (shadow_inputs_q[0].data_err),
-
-    .dummy_instr_id_o    (shadow_outputs_d.dummy_instr_id),
-    .rf_raddr_a_o        (shadow_outputs_d.rf_raddr_a),
-    .rf_raddr_b_o        (shadow_outputs_d.rf_raddr_b),
-    .rf_waddr_wb_o       (shadow_outputs_d.rf_waddr_wb),
-    .rf_we_wb_o          (shadow_outputs_d.rf_we_wb),
-    .rf_wdata_wb_ecc_o   (shadow_outputs_d.rf_wdata_wb_ecc),
-    .rf_rdata_a_ecc_i    (shadow_inputs_q[0].rf_rdata_a_ecc),
-    .rf_rdata_b_ecc_i    (shadow_inputs_q[0].rf_rdata_b_ecc),
-
-    .ic_tag_req_o        (shadow_outputs_d.ic_tag_req),
-    .ic_tag_write_o      (shadow_outputs_d.ic_tag_write),
-    .ic_tag_addr_o       (shadow_outputs_d.ic_tag_addr),
-    .ic_tag_wdata_o      (shadow_outputs_d.ic_tag_wdata),
-    .ic_tag_rdata_i      (shadow_tag_rdata_q[0]),
-    .ic_data_req_o       (shadow_outputs_d.ic_data_req),
-    .ic_data_write_o     (shadow_outputs_d.ic_data_write),
-    .ic_data_addr_o      (shadow_outputs_d.ic_data_addr),
-    .ic_data_wdata_o     (shadow_outputs_d.ic_data_wdata),
-    .ic_data_rdata_i     (shadow_data_rdata_q[0]),
-    .ic_scr_key_valid_i  (shadow_inputs_q[0].ic_scr_key_valid),
-
-    .irq_software_i      (shadow_inputs_q[0].irq_software),
-    .irq_timer_i         (shadow_inputs_q[0].irq_timer),
-    .irq_external_i      (shadow_inputs_q[0].irq_external),
-    .irq_fast_i          (shadow_inputs_q[0].irq_fast),
-    .irq_nm_i            (shadow_inputs_q[0].irq_nm),
-    .irq_pending_o       (shadow_outputs_d.irq_pending),
-
-    .debug_req_i         (shadow_inputs_q[0].debug_req),
-    .crash_dump_o        (shadow_outputs_d.crash_dump),
-    .double_fault_seen_o (shadow_outputs_d.double_fault_seen),
-
-`ifdef RVFI
-    .rvfi_valid         (),
-    .rvfi_order         (),
-    .rvfi_insn          (),
-    .rvfi_trap          (),
-    .rvfi_halt          (),
-    .rvfi_intr          (),
-    .rvfi_mode          (),
-    .rvfi_ixl           (),
-    .rvfi_rs1_addr      (),
-    .rvfi_rs2_addr      (),
-    .rvfi_rs3_addr      (),
-    .rvfi_rs1_rdata     (),
-    .rvfi_rs2_rdata     (),
-    .rvfi_rs3_rdata     (),
-    .rvfi_rd_addr       (),
-    .rvfi_rd_wdata      (),
-    .rvfi_pc_rdata      (),
-    .rvfi_pc_wdata      (),
-    .rvfi_mem_addr      (),
-    .rvfi_mem_rmask     (),
-    .rvfi_mem_wmask     (),
-    .rvfi_mem_rdata     (),
-    .rvfi_mem_wdata     (),
-    .rvfi_ext_mip       (),
-    .rvfi_ext_nmi       (),
-    .rvfi_ext_debug_req (),
-    .rvfi_ext_mcycle    (),
-`endif
-
-    .fetch_enable_i    (shadow_inputs_q[0].fetch_enable),
-    .alert_minor_o     (shadow_alert_minor),
-    .alert_major_o     (shadow_alert_major),
-    .icache_inval_o    (shadow_outputs_d.icache_inval),
-    .core_busy_o       (shadow_outputs_d.core_busy)
-  );
-
-  // Register the shadow core outputs
-  always_ff @(posedge clk_i) begin
-    shadow_outputs_q <= shadow_outputs_d;
-  end
-
-  /////////////////////////
-  // Compare the outputs //
-  /////////////////////////
-
-  logic outputs_mismatch;
-
-  assign outputs_mismatch       = enable_cmp_q & (shadow_outputs_q != core_outputs_q[0]);
-  assign alert_major_internal_o = outputs_mismatch | shadow_alert_major;
-  assign alert_major_bus_o      = bus_intg_err;
-  assign alert_minor_o          = shadow_alert_minor;
-
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_fpga.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_fpga.sv
deleted file mode 100644
index 678549ab..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_fpga.sv
+++ /dev/null
@@ -1,83 +0,0 @@
-// Copyright lowRISC contributors.
-// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-/**
- * RISC-V register file
- *
- * Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
- *
- * This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx
- * FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested.
- */
-module ibex_register_file_fpga #(
-    parameter bit                   RV32E             = 0,
-    parameter int unsigned          DataWidth         = 32,
-    parameter bit                   DummyInstructions = 0,
-    parameter logic [DataWidth-1:0] WordZeroVal       = '0
-) (
-  // Clock and Reset
-  input  logic                 clk_i,
-  input  logic                 rst_ni,
-
-  input  logic                 test_en_i,
-  input  logic                 dummy_instr_id_i,
-
-  //Read port R1
-  input  logic [          4:0] raddr_a_i,
-  output logic [DataWidth-1:0] rdata_a_o,
-  //Read port R2
-  input  logic [          4:0] raddr_b_i,
-  output logic [DataWidth-1:0] rdata_b_o,
-  // Write port W1
-  input  logic [          4:0] waddr_a_i,
-  input  logic [DataWidth-1:0] wdata_a_i,
-  input  logic                 we_a_i
-);
-
-  localparam int ADDR_WIDTH = RV32E ? 4 : 5;
-  localparam int NUM_WORDS = 2 ** ADDR_WIDTH;
-
-  logic [DataWidth-1:0] mem[NUM_WORDS];
-  logic we; // write enable if writing to any register other than R0
-
-  // async_read a
-  assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i];
-
-  // async_read b
-  assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i];
-
-  // we select
-  assign we = (waddr_a_i == '0) ? 1'b0 : we_a_i;
-
-  // Note that the SystemVerilog LRM requires variables on the LHS of assignments within
-  // "always_ff" to not be written to by any other process. However, to enable the initialization
-  // of the inferred RAM32M primitives with non-zero values, below "initial" procedure is needed.
-  // Therefore, we use "always" instead of the generally preferred "always_ff" for the synchronous
-  // write procedure.
-  always @(posedge clk_i) begin : sync_write
-    if (we == 1'b1) begin
-      mem[waddr_a_i] <= wdata_a_i;
-    end
-  end : sync_write
-
-  // Make sure we initialize the BRAM with the correct register reset value.
-  initial begin
-    for (int k = 0; k < NUM_WORDS; k++) begin
-      mem[k] = WordZeroVal;
-    end
-  end
-
-  // Reset not used in this register file version
-  logic unused_rst_ni;
-  assign unused_rst_ni = rst_ni;
-
-  // Dummy instruction changes not relevant for FPGA implementation
-  logic unused_dummy_instr;
-  assign unused_dummy_instr = dummy_instr_id_i;
-  // Test enable signal not used in FPGA implementation
-  logic unused_test_en;
-  assign unused_test_en = test_en_i;
-
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_latch.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_latch.sv
deleted file mode 100644
index f1e4df75..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_register_file_latch.sv
+++ /dev/null
@@ -1,164 +0,0 @@
-// Copyright lowRISC contributors.
-// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-/**
- * RISC-V register file
- *
- * Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
- * This register file is based on latches and is thus smaller than the flip-flop
- * based RF. It requires a target technology-specific clock gating cell. Use this
- * register file when targeting ASIC synthesis or event-based simulators.
- */
-module ibex_register_file_latch #(
-  parameter bit                   RV32E             = 0,
-  parameter int unsigned          DataWidth         = 32,
-  parameter bit                   DummyInstructions = 0,
-  parameter logic [DataWidth-1:0] WordZeroVal       = '0
-) (
-  // Clock and Reset
-  input  logic                 clk_i,
-  input  logic                 rst_ni,
-
-  input  logic                 test_en_i,
-  input  logic                 dummy_instr_id_i,
-
-  //Read port R1
-  input  logic [4:0]           raddr_a_i,
-  output logic [DataWidth-1:0] rdata_a_o,
-
-  //Read port R2
-  input  logic [4:0]           raddr_b_i,
-  output logic [DataWidth-1:0] rdata_b_o,
-
-  // Write port W1
-  input  logic [4:0]           waddr_a_i,
-  input  logic [DataWidth-1:0] wdata_a_i,
-  input  logic                 we_a_i
-
-);
-
-  localparam int unsigned ADDR_WIDTH = RV32E ? 4 : 5;
-  localparam int unsigned NUM_WORDS  = 2**ADDR_WIDTH;
-
-  logic [DataWidth-1:0] mem[NUM_WORDS];
-
-  logic [NUM_WORDS-1:1] waddr_onehot_a;
-
-  logic [NUM_WORDS-1:1] mem_clocks;
-  logic [DataWidth-1:0] wdata_a_q;
-
-  // internal addresses
-  logic [ADDR_WIDTH-1:0] raddr_a_int, raddr_b_int, waddr_a_int;
-
-  assign raddr_a_int = raddr_a_i[ADDR_WIDTH-1:0];
-  assign raddr_b_int = raddr_b_i[ADDR_WIDTH-1:0];
-  assign waddr_a_int = waddr_a_i[ADDR_WIDTH-1:0];
-
-  logic clk_int;
-
-  //////////
-  // READ //
-  //////////
-  assign rdata_a_o = mem[raddr_a_int];
-  assign rdata_b_o = mem[raddr_b_int];
-
-  ///////////
-  // WRITE //
-  ///////////
-  // Global clock gating
-  prim_clock_gating cg_we_global (
-      .clk_i     ( clk_i     ),
-      .en_i      ( we_a_i    ),
-      .test_en_i ( test_en_i ),
-      .clk_o     ( clk_int   )
-  );
-
-  // Sample input data
-  // Use clk_int here, since otherwise we don't want to write anything anyway.
-  always_ff @(posedge clk_int or negedge rst_ni) begin : sample_wdata
-    if (!rst_ni) begin
-      wdata_a_q   <= WordZeroVal;
-    end else begin
-      if (we_a_i) begin
-        wdata_a_q <= wdata_a_i;
-      end
-    end
-  end
-
-  // Write address decoding
-  always_comb begin : wad
-    for (int i = 1; i < NUM_WORDS; i++) begin : wad_word_iter
-      if (we_a_i && (waddr_a_int == 5'(i))) begin
-        waddr_onehot_a[i] = 1'b1;
-      end else begin
-        waddr_onehot_a[i] = 1'b0;
-      end
-    end
-  end
-
-  // Individual clock gating (if integrated clock-gating cells are available)
-  for (genvar x = 1; x < NUM_WORDS; x++) begin : gen_cg_word_iter
-    prim_clock_gating cg_i (
-        .clk_i     ( clk_int           ),
-        .en_i      ( waddr_onehot_a[x] ),
-        .test_en_i ( test_en_i         ),
-        .clk_o     ( mem_clocks[x]     )
-    );
-  end
-
-  // Actual write operation:
-  // Generate the sequential process for the NUM_WORDS words of the memory.
-  // The process is synchronized with the clocks mem_clocks[i], i = 1, ..., NUM_WORDS-1.
-  for (genvar i = 1; i < NUM_WORDS; i++) begin : g_rf_latches
-    always_latch begin
-      if (mem_clocks[i]) begin
-        mem[i] = wdata_a_q;
-      end
-    end
-  end
-
-  // With dummy instructions enabled, R0 behaves as a real register but will always return 0 for
-  // real instructions.
-  if (DummyInstructions) begin : g_dummy_r0
-    // SEC_CM: CTRL_FLOW.UNPREDICTABLE
-    logic                 we_r0_dummy;
-    logic                 r0_clock;
-    logic [DataWidth-1:0] mem_r0;
-
-    // Write enable for dummy R0 register (waddr_a_i will always be 0 for dummy instructions)
-    assign we_r0_dummy = we_a_i & dummy_instr_id_i;
-
-    // R0 clock gate
-    prim_clock_gating cg_i (
-        .clk_i     ( clk_int     ),
-        .en_i      ( we_r0_dummy ),
-        .test_en_i ( test_en_i   ),
-        .clk_o     ( r0_clock    )
-    );
-
-    always_latch begin : latch_wdata
-      if (r0_clock) begin
-        mem_r0 = wdata_a_q;
-      end
-    end
-
-    // Output the dummy data for dummy instructions, otherwise R0 reads as zero
-    assign mem[0] = dummy_instr_id_i ? mem_r0 : WordZeroVal;
-
-  end else begin : g_normal_r0
-    logic unused_dummy_instr_id;
-    assign unused_dummy_instr_id = dummy_instr_id_i;
-
-    assign mem[0] = WordZeroVal;
-  end
-
-`ifdef VERILATOR
-  initial begin
-    $display("Latch-based register file not supported for Verilator simulation");
-    $fatal;
-  end
-`endif
-
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_top.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_top.sv
deleted file mode 100644
index b566bb17..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_top.sv
+++ /dev/null
@@ -1,978 +0,0 @@
-// Copyright lowRISC contributors.
-// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-`ifdef RISCV_FORMAL
-  `define RVFI
-`endif
-
-`include "prim_assert.sv"
-
-/**
- * Top level module of the ibex RISC-V core
- */
-module ibex_top import ibex_pkg::*; #(
-  parameter bit          PMPEnable        = 1'b0,
-  parameter int unsigned PMPGranularity   = 0,
-  parameter int unsigned PMPNumRegions    = 4,
-  parameter int unsigned MHPMCounterNum   = 0,
-  parameter int unsigned MHPMCounterWidth = 40,
-  parameter bit          RV32E            = 1'b0,
-  parameter rv32m_e      RV32M            = RV32MFast,
-  parameter rv32b_e      RV32B            = RV32BNone,
-  parameter regfile_e    RegFile          = RegFileFF,
-  parameter bit          BranchTargetALU  = 1'b0,
-  parameter bit          WritebackStage   = 1'b0,
-  parameter bit          ICache           = 1'b0,
-  parameter bit          ICacheECC        = 1'b0,
-  parameter bit          BranchPredictor  = 1'b0,
-  parameter bit          DbgTriggerEn     = 1'b0,
-  parameter int unsigned DbgHwBreakNum    = 1,
-  parameter bit          SecureIbex       = 1'b0,
-  parameter bit          ICacheScramble   = 1'b0,
-  parameter lfsr_seed_t  RndCnstLfsrSeed  = RndCnstLfsrSeedDefault,
-  parameter lfsr_perm_t  RndCnstLfsrPerm  = RndCnstLfsrPermDefault,
-  parameter int unsigned DmHaltAddr       = 32'h1A110800,
-  parameter int unsigned DmExceptionAddr  = 32'h1A110808,
-  // Default seed and nonce for scrambling
-  parameter logic [SCRAMBLE_KEY_W-1:0]   RndCnstIbexKey   = RndCnstIbexKeyDefault,
-  parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonce = RndCnstIbexNonceDefault
-) (
-  // Clock and Reset
-  input  logic                         clk_i,
-  input  logic                         rst_ni,
-
-  input  logic                         test_en_i,     // enable all clock gates for testing
-  input  prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
-
-  input  logic [31:0]                  hart_id_i,
-  input  logic [31:0]                  boot_addr_i,
-
-  // Instruction memory interface
-  output logic                         instr_req_o,
-  input  logic                         instr_gnt_i,
-  input  logic                         instr_rvalid_i,
-  output logic [31:0]                  instr_addr_o,
-  input  logic [31:0]                  instr_rdata_i,
-  input  logic [6:0]                   instr_rdata_intg_i,
-  input  logic                         instr_err_i,
-
-  // Data memory interface
-  output logic                         data_req_o,
-  input  logic                         data_gnt_i,
-  input  logic                         data_rvalid_i,
-  output logic                         data_we_o,
-  output logic [3:0]                   data_be_o,
-  output logic [31:0]                  data_addr_o,
-  output logic [31:0]                  data_wdata_o,
-  output logic [6:0]                   data_wdata_intg_o,
-  input  logic [31:0]                  data_rdata_i,
-  input  logic [6:0]                   data_rdata_intg_i,
-  input  logic                         data_err_i,
-
-  // Interrupt inputs
-  input  logic                         irq_software_i,
-  input  logic                         irq_timer_i,
-  input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
-  input  logic                         irq_nm_i,       // non-maskeable interrupt
-
-  // Scrambling Interface
-  input  logic                         scramble_key_valid_i,
-  input  logic [SCRAMBLE_KEY_W-1:0]    scramble_key_i,
-  input  logic [SCRAMBLE_NONCE_W-1:0]  scramble_nonce_i,
-  output logic                         scramble_req_o,
-
-  // Debug Interface
-  input  logic                         debug_req_i,
-  output crash_dump_t                  crash_dump_o,
-  output logic                         double_fault_seen_o,
-
-  // RISC-V Formal Interface
-  // Does not comply with the coding standards of _i/_o suffixes, but follows
-  // the convention of RISC-V Formal Interface Specification.
-`ifdef RVFI
-  output logic                         rvfi_valid,
-  output logic [63:0]                  rvfi_order,
-  output logic [31:0]                  rvfi_insn,
-  output logic                         rvfi_trap,
-  output logic                         rvfi_halt,
-  output logic                         rvfi_intr,
-  output logic [ 1:0]                  rvfi_mode,
-  output logic [ 1:0]                  rvfi_ixl,
-  output logic [ 4:0]                  rvfi_rs1_addr,
-  output logic [ 4:0]                  rvfi_rs2_addr,
-  output logic [ 4:0]                  rvfi_rs3_addr,
-  output logic [31:0]                  rvfi_rs1_rdata,
-  output logic [31:0]                  rvfi_rs2_rdata,
-  output logic [31:0]                  rvfi_rs3_rdata,
-  output logic [ 4:0]                  rvfi_rd_addr,
-  output logic [31:0]                  rvfi_rd_wdata,
-  output logic [31:0]                  rvfi_pc_rdata,
-  output logic [31:0]                  rvfi_pc_wdata,
-  output logic [31:0]                  rvfi_mem_addr,
-  output logic [ 3:0]                  rvfi_mem_rmask,
-  output logic [ 3:0]                  rvfi_mem_wmask,
-  output logic [31:0]                  rvfi_mem_rdata,
-  output logic [31:0]                  rvfi_mem_wdata,
-  output logic [31:0]                  rvfi_ext_mip,
-  output logic                         rvfi_ext_nmi,
-  output logic                         rvfi_ext_debug_req,
-  output logic [63:0]                  rvfi_ext_mcycle,
-`endif
-
-  // CPU Control Signals
-  input  fetch_enable_t                fetch_enable_i,
-  output logic                         alert_minor_o,
-  output logic                         alert_major_internal_o,
-  output logic                         alert_major_bus_o,
-  output logic                         core_sleep_o,
-
-  // DFT bypass controls
-  input logic                          scan_rst_ni
-);
-
-  localparam bit          Lockstep          = SecureIbex;
-  localparam bit          ResetAll          = Lockstep;
-  localparam bit          DummyInstructions = SecureIbex;
-  localparam bit          RegFileECC        = SecureIbex;
-  localparam int unsigned RegFileDataWidth  = RegFileECC ? 32 + 7 : 32;
-  // Icache parameters
-  localparam int unsigned BusSizeECC        = ICacheECC ? (BUS_SIZE + 7) : BUS_SIZE;
-  localparam int unsigned LineSizeECC       = BusSizeECC * IC_LINE_BEATS;
-  localparam int unsigned TagSizeECC        = ICacheECC ? (IC_TAG_SIZE + 6) : IC_TAG_SIZE;
-  // Scrambling Parameter
-  localparam int unsigned NumAddrScrRounds  = ICacheScramble ? 2 : 0;
-  localparam int unsigned NumDiffRounds     = NumAddrScrRounds;
-
-  // Clock signals
-  logic                        clk;
-  logic                        core_busy_d, core_busy_q;
-  logic                        clock_en;
-  logic                        irq_pending;
-  // Core <-> Register file signals
-  logic                        dummy_instr_id;
-  logic [4:0]                  rf_raddr_a;
-  logic [4:0]                  rf_raddr_b;
-  logic [4:0]                  rf_waddr_wb;
-  logic                        rf_we_wb;
-  logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc;
-  logic [RegFileDataWidth-1:0] rf_rdata_a_ecc, rf_rdata_a_ecc_buf;
-  logic [RegFileDataWidth-1:0] rf_rdata_b_ecc, rf_rdata_b_ecc_buf;
-  // Core <-> RAMs signals
-  logic [IC_NUM_WAYS-1:0]      ic_tag_req;
-  logic                        ic_tag_write;
-  logic [IC_INDEX_W-1:0]       ic_tag_addr;
-  logic [TagSizeECC-1:0]       ic_tag_wdata;
-  logic [TagSizeECC-1:0]       ic_tag_rdata [IC_NUM_WAYS];
-  logic [IC_NUM_WAYS-1:0]      ic_data_req;
-  logic                        ic_data_write;
-  logic [IC_INDEX_W-1:0]       ic_data_addr;
-  logic [LineSizeECC-1:0]      ic_data_wdata;
-  logic [LineSizeECC-1:0]      ic_data_rdata [IC_NUM_WAYS];
-  // Alert signals
-  logic                        core_alert_major, core_alert_minor;
-  logic                        lockstep_alert_major_internal, lockstep_alert_major_bus;
-  logic                        lockstep_alert_minor;
-  // Scramble signals
-  logic                         icache_inval;
-  logic [SCRAMBLE_KEY_W-1:0]    scramble_key_q;
-  logic [SCRAMBLE_NONCE_W-1:0]  scramble_nonce_q;
-  logic                         scramble_key_valid_d, scramble_key_valid_q;
-  logic                         scramble_req_d, scramble_req_q;
-
-  fetch_enable_t fetch_enable_buf;
-
-  /////////////////////
-  // Main clock gate //
-  /////////////////////
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      core_busy_q <= 1'b0;
-    end else begin
-      core_busy_q <= core_busy_d;
-    end
-  end
-
-  assign clock_en     = core_busy_q | debug_req_i | irq_pending | irq_nm_i;
-  assign core_sleep_o = ~clock_en;
-
-  prim_clock_gating core_clock_gate_i (
-    .clk_i    (clk_i),
-    .en_i     (clock_en),
-    .test_en_i(test_en_i),
-    .clk_o    (clk)
-  );
-
-  ////////////////////////
-  // Core instantiation //
-  ////////////////////////
-
-  // Buffer security critical signals to prevent synthesis optimisation removing them
-  prim_buf #(.Width($bits(fetch_enable_t))) u_fetch_enable_buf (
-    .in_i (fetch_enable_i),
-    .out_o(fetch_enable_buf)
-  );
-
-  prim_buf #(.Width(RegFileDataWidth)) u_rf_rdata_a_ecc_buf (
-    .in_i (rf_rdata_a_ecc),
-    .out_o(rf_rdata_a_ecc_buf)
-  );
-
-  prim_buf #(.Width(RegFileDataWidth)) u_rf_rdata_b_ecc_buf (
-    .in_i (rf_rdata_b_ecc),
-    .out_o(rf_rdata_b_ecc_buf)
-  );
-
-  ibex_core #(
-    .PMPEnable        (PMPEnable),
-    .PMPGranularity   (PMPGranularity),
-    .PMPNumRegions    (PMPNumRegions),
-    .MHPMCounterNum   (MHPMCounterNum),
-    .MHPMCounterWidth (MHPMCounterWidth),
-    .RV32E            (RV32E),
-    .RV32M            (RV32M),
-    .RV32B            (RV32B),
-    .BranchTargetALU  (BranchTargetALU),
-    .ICache           (ICache),
-    .ICacheECC        (ICacheECC),
-    .BusSizeECC       (BusSizeECC),
-    .TagSizeECC       (TagSizeECC),
-    .LineSizeECC      (LineSizeECC),
-    .BranchPredictor  (BranchPredictor),
-    .DbgTriggerEn     (DbgTriggerEn),
-    .DbgHwBreakNum    (DbgHwBreakNum),
-    .WritebackStage   (WritebackStage),
-    .ResetAll         (ResetAll),
-    .RndCnstLfsrSeed  (RndCnstLfsrSeed),
-    .RndCnstLfsrPerm  (RndCnstLfsrPerm),
-    .SecureIbex       (SecureIbex),
-    .DummyInstructions(DummyInstructions),
-    .RegFileECC       (RegFileECC),
-    .RegFileDataWidth (RegFileDataWidth),
-    .DmHaltAddr       (DmHaltAddr),
-    .DmExceptionAddr  (DmExceptionAddr)
-  ) u_ibex_core (
-    .clk_i(clk),
-    .rst_ni,
-
-    .hart_id_i,
-    .boot_addr_i,
-
-    .instr_req_o,
-    .instr_gnt_i,
-    .instr_rvalid_i,
-    .instr_addr_o,
-    .instr_rdata_i,
-    .instr_err_i,
-
-    .data_req_o,
-    .data_gnt_i,
-    .data_rvalid_i,
-    .data_we_o,
-    .data_be_o,
-    .data_addr_o,
-    .data_wdata_o,
-    .data_rdata_i,
-    .data_err_i,
-
-    .dummy_instr_id_o (dummy_instr_id),
-    .rf_raddr_a_o     (rf_raddr_a),
-    .rf_raddr_b_o     (rf_raddr_b),
-    .rf_waddr_wb_o    (rf_waddr_wb),
-    .rf_we_wb_o       (rf_we_wb),
-    .rf_wdata_wb_ecc_o(rf_wdata_wb_ecc),
-    .rf_rdata_a_ecc_i (rf_rdata_a_ecc_buf),
-    .rf_rdata_b_ecc_i (rf_rdata_b_ecc_buf),
-
-    .ic_tag_req_o      (ic_tag_req),
-    .ic_tag_write_o    (ic_tag_write),
-    .ic_tag_addr_o     (ic_tag_addr),
-    .ic_tag_wdata_o    (ic_tag_wdata),
-    .ic_tag_rdata_i    (ic_tag_rdata),
-    .ic_data_req_o     (ic_data_req),
-    .ic_data_write_o   (ic_data_write),
-    .ic_data_addr_o    (ic_data_addr),
-    .ic_data_wdata_o   (ic_data_wdata),
-    .ic_data_rdata_i   (ic_data_rdata),
-    .ic_scr_key_valid_i(scramble_key_valid_q),
-
-    .irq_software_i,
-    .irq_timer_i,
-    .irq_external_i,
-    .irq_fast_i,
-    .irq_nm_i,
-    .irq_pending_o(irq_pending),
-
-    .debug_req_i,
-    .crash_dump_o,
-    .double_fault_seen_o,
-
-`ifdef RVFI
-    .rvfi_valid,
-    .rvfi_order,
-    .rvfi_insn,
-    .rvfi_trap,
-    .rvfi_halt,
-    .rvfi_intr,
-    .rvfi_mode,
-    .rvfi_ixl,
-    .rvfi_rs1_addr,
-    .rvfi_rs2_addr,
-    .rvfi_rs3_addr,
-    .rvfi_rs1_rdata,
-    .rvfi_rs2_rdata,
-    .rvfi_rs3_rdata,
-    .rvfi_rd_addr,
-    .rvfi_rd_wdata,
-    .rvfi_pc_rdata,
-    .rvfi_pc_wdata,
-    .rvfi_mem_addr,
-    .rvfi_mem_rmask,
-    .rvfi_mem_wmask,
-    .rvfi_mem_rdata,
-    .rvfi_mem_wdata,
-    .rvfi_ext_mip,
-    .rvfi_ext_nmi,
-    .rvfi_ext_debug_req,
-    .rvfi_ext_mcycle,
-`endif
-
-    .fetch_enable_i(fetch_enable_buf),
-    .alert_minor_o (core_alert_minor),
-    .alert_major_o (core_alert_major),
-    .icache_inval_o(icache_inval),
-    .core_busy_o   (core_busy_d)
-  );
-
-  /////////////////////////////////
-  // Register file Instantiation //
-  /////////////////////////////////
-
-  if (RegFile == RegFileFF) begin : gen_regfile_ff
-    ibex_register_file_ff #(
-      .RV32E            (RV32E),
-      .DataWidth        (RegFileDataWidth),
-      .DummyInstructions(DummyInstructions),
-      .WordZeroVal      (RegFileDataWidth'(prim_secded_pkg::SecdedInv3932ZeroWord))
-    ) register_file_i (
-      .clk_i (clk),
-      .rst_ni(rst_ni),
-
-      .test_en_i       (test_en_i),
-      .dummy_instr_id_i(dummy_instr_id),
-
-      .raddr_a_i(rf_raddr_a),
-      .rdata_a_o(rf_rdata_a_ecc),
-      .raddr_b_i(rf_raddr_b),
-      .rdata_b_o(rf_rdata_b_ecc),
-      .waddr_a_i(rf_waddr_wb),
-      .wdata_a_i(rf_wdata_wb_ecc),
-      .we_a_i   (rf_we_wb)
-    );
-  end else if (RegFile == RegFileFPGA) begin : gen_regfile_fpga
-    ibex_register_file_fpga #(
-      .RV32E            (RV32E),
-      .DataWidth        (RegFileDataWidth),
-      .DummyInstructions(DummyInstructions),
-      .WordZeroVal      (RegFileDataWidth'(prim_secded_pkg::SecdedInv3932ZeroWord))
-    ) register_file_i (
-      .clk_i (clk),
-      .rst_ni(rst_ni),
-
-      .test_en_i       (test_en_i),
-      .dummy_instr_id_i(dummy_instr_id),
-
-      .raddr_a_i(rf_raddr_a),
-      .rdata_a_o(rf_rdata_a_ecc),
-      .raddr_b_i(rf_raddr_b),
-      .rdata_b_o(rf_rdata_b_ecc),
-      .waddr_a_i(rf_waddr_wb),
-      .wdata_a_i(rf_wdata_wb_ecc),
-      .we_a_i   (rf_we_wb)
-    );
-  end else if (RegFile == RegFileLatch) begin : gen_regfile_latch
-    ibex_register_file_latch #(
-      .RV32E            (RV32E),
-      .DataWidth        (RegFileDataWidth),
-      .DummyInstructions(DummyInstructions),
-      .WordZeroVal      (RegFileDataWidth'(prim_secded_pkg::SecdedInv3932ZeroWord))
-    ) register_file_i (
-      .clk_i (clk),
-      .rst_ni(rst_ni),
-
-      .test_en_i       (test_en_i),
-      .dummy_instr_id_i(dummy_instr_id),
-
-      .raddr_a_i(rf_raddr_a),
-      .rdata_a_o(rf_rdata_a_ecc),
-      .raddr_b_i(rf_raddr_b),
-      .rdata_b_o(rf_rdata_b_ecc),
-      .waddr_a_i(rf_waddr_wb),
-      .wdata_a_i(rf_wdata_wb_ecc),
-      .we_a_i   (rf_we_wb)
-    );
-  end
-
-  ///////////////////////////////
-  // Scrambling Infrastructure //
-  ///////////////////////////////
-
-  if (ICacheScramble) begin : gen_scramble
-
-    // SEC_CM: ICACHE.MEM.SCRAMBLE
-    // Scramble key valid starts with OTP returning new valid key and stays high
-    // until we request a new valid key.
-    assign scramble_key_valid_d = scramble_req_q ? scramble_key_valid_i :
-                                  icache_inval   ? 1'b0                 :
-                                                   scramble_key_valid_q;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        scramble_key_q       <= RndCnstIbexKey;
-        scramble_nonce_q     <= RndCnstIbexNonce;
-      end else if (scramble_key_valid_i) begin
-        scramble_key_q       <= scramble_key_i;
-        scramble_nonce_q     <= scramble_nonce_i;
-      end
-    end
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        scramble_key_valid_q <= 1'b1;
-        scramble_req_q       <= '0;
-      end else begin
-        scramble_key_valid_q <= scramble_key_valid_d;
-        scramble_req_q       <= scramble_req_d;
-      end
-    end
-
-  // Scramble key request starts with invalidate signal from ICache and stays high
-  // until we got a valid key.
-    assign scramble_req_d = scramble_req_q ? ~scramble_key_valid_i : icache_inval;
-    assign scramble_req_o = scramble_req_q;
-
-  end else begin : gen_noscramble
-
-    logic unused_scramble_inputs = scramble_key_valid_i & (|scramble_key_i) & (|RndCnstIbexKey) &
-                                   (|scramble_nonce_i) & (|RndCnstIbexNonce) & scramble_req_q &
-                                   icache_inval & scramble_key_valid_d & scramble_req_d;
-
-    assign scramble_req_d       = 1'b0;
-    assign scramble_req_q       = 1'b0;
-    assign scramble_req_o       = 1'b0;
-    assign scramble_key_q       = '0;
-    assign scramble_nonce_q     = '0;
-    assign scramble_key_valid_q = 1'b1;
-    assign scramble_key_valid_d = 1'b1;
-  end
-
-  ////////////////////////
-  // Rams Instantiation //
-  ////////////////////////
-
-  if (ICache) begin : gen_rams
-
-    for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_rams_inner
-
-      // SEC_CM: ICACHE.MEM.SCRAMBLE
-      // Tag RAM instantiation
-      prim_ram_1p_scr #(
-        .Width            (TagSizeECC),
-        .Depth            (IC_NUM_LINES),
-        .DataBitsPerMask  (TagSizeECC),
-        .EnableParity     (0),
-        .DiffWidth        (TagSizeECC),
-        .NumAddrScrRounds (NumAddrScrRounds),
-        .NumDiffRounds    (NumDiffRounds)
-      ) tag_bank (
-        .clk_i,
-        .rst_ni,
-
-        .key_valid_i (scramble_key_valid_q),
-        .key_i       (scramble_key_q),
-        .nonce_i     (scramble_nonce_q),
-
-        .req_i       (ic_tag_req[way]),
-
-        .gnt_o       (),
-        .write_i     (ic_tag_write),
-        .addr_i      (ic_tag_addr),
-        .wdata_i     (ic_tag_wdata),
-        .wmask_i     ({TagSizeECC{1'b1}}),
-        .intg_error_i(1'b0),
-
-        .rdata_o     (ic_tag_rdata[way]),
-        .rvalid_o    (),
-        .raddr_o     (),
-        .rerror_o    (),
-        .cfg_i       (ram_cfg_i)
-      );
-
-      // Data RAM instantiation
-      prim_ram_1p_scr #(
-        .Width              (LineSizeECC),
-        .Depth              (IC_NUM_LINES),
-        .DataBitsPerMask    (LineSizeECC),
-        .ReplicateKeyStream (1),
-        .EnableParity       (0),
-        .DiffWidth          (LineSizeECC),
-        .NumAddrScrRounds   (NumAddrScrRounds),
-        .NumDiffRounds      (NumDiffRounds)
-      ) data_bank (
-        .clk_i,
-        .rst_ni,
-
-        .key_valid_i (scramble_key_valid_q),
-        .key_i       (scramble_key_q),
-        .nonce_i     (scramble_nonce_q),
-
-        .req_i       (ic_data_req[way]),
-
-        .gnt_o       (),
-        .write_i     (ic_data_write),
-        .addr_i      (ic_data_addr),
-        .wdata_i     (ic_data_wdata),
-        .wmask_i     ({LineSizeECC{1'b1}}),
-        .intg_error_i(1'b0),
-
-        .rdata_o     (ic_data_rdata[way]),
-        .rvalid_o    (),
-        .raddr_o     (),
-        .rerror_o    (),
-        .cfg_i       (ram_cfg_i)
-      );
-    end
-
-  end else begin : gen_norams
-
-    prim_ram_1p_pkg::ram_1p_cfg_t unused_ram_cfg;
-    logic unused_ram_inputs;
-
-    assign unused_ram_cfg    = ram_cfg_i;
-    assign unused_ram_inputs = (|ic_tag_req) & ic_tag_write & (|ic_tag_addr) & (|ic_tag_wdata) &
-                               (|ic_data_req) & ic_data_write & (|ic_data_addr) & (|ic_data_wdata) &
-                               (|scramble_key_q) & (|scramble_nonce_q) & scramble_key_valid_q &
-                               scramble_key_valid_d & (|scramble_nonce_q) &
-                               (|NumAddrScrRounds);
-
-    assign ic_tag_rdata      = '{default:'b0};
-    assign ic_data_rdata     = '{default:'b0};
-
-  end
-
-  // Redundant lockstep core implementation
-  if (Lockstep) begin : gen_lockstep
-    // SEC_CM: LOGIC.SHADOW
-    // Note: certain synthesis tools like DC are very smart at optimizing away redundant logic.
-    // Hence, we have to insert an optimization barrier at the IOs of the lockstep Ibex.
-    // This is achieved by manually buffering each bit using prim_buf.
-    // Our Xilinx and DC synthesis flows make sure that these buffers cannot be optimized away
-    // using keep attributes (Vivado) and size_only constraints (DC).
-
-    localparam int NumBufferBits = $bits({
-      hart_id_i,
-      boot_addr_i,
-      instr_req_o,
-      instr_gnt_i,
-      instr_rvalid_i,
-      instr_addr_o,
-      instr_rdata_i,
-      instr_rdata_intg_i,
-      instr_err_i,
-      data_req_o,
-      data_gnt_i,
-      data_rvalid_i,
-      data_we_o,
-      data_be_o,
-      data_addr_o,
-      data_wdata_o,
-      data_rdata_i,
-      data_rdata_intg_i,
-      data_err_i,
-      dummy_instr_id,
-      rf_raddr_a,
-      rf_raddr_b,
-      rf_waddr_wb,
-      rf_we_wb,
-      rf_wdata_wb_ecc,
-      rf_rdata_a_ecc,
-      rf_rdata_b_ecc,
-      ic_tag_req,
-      ic_tag_write,
-      ic_tag_addr,
-      ic_tag_wdata,
-      ic_data_req,
-      ic_data_write,
-      ic_data_addr,
-      ic_data_wdata,
-      scramble_key_valid_i,
-      irq_software_i,
-      irq_timer_i,
-      irq_external_i,
-      irq_fast_i,
-      irq_nm_i,
-      irq_pending,
-      debug_req_i,
-      crash_dump_o,
-      double_fault_seen_o,
-      fetch_enable_i,
-      icache_inval,
-      core_busy_d
-    });
-
-    logic [NumBufferBits-1:0] buf_in, buf_out;
-
-    logic [31:0]                  hart_id_local;
-    logic [31:0]                  boot_addr_local;
-
-    logic                         instr_req_local;
-    logic                         instr_gnt_local;
-    logic                         instr_rvalid_local;
-    logic [31:0]                  instr_addr_local;
-    logic [31:0]                  instr_rdata_local;
-    logic [6:0]                   instr_rdata_intg_local;
-    logic                         instr_err_local;
-
-    logic                         data_req_local;
-    logic                         data_gnt_local;
-    logic                         data_rvalid_local;
-    logic                         data_we_local;
-    logic [3:0]                   data_be_local;
-    logic [31:0]                  data_addr_local;
-    logic [31:0]                  data_wdata_local;
-    logic [6:0]                   data_wdata_intg_local;
-    logic [31:0]                  data_rdata_local;
-    logic [6:0]                   data_rdata_intg_local;
-    logic                         data_err_local;
-
-    logic                         dummy_instr_id_local;
-    logic [4:0]                   rf_raddr_a_local;
-    logic [4:0]                   rf_raddr_b_local;
-    logic [4:0]                   rf_waddr_wb_local;
-    logic                         rf_we_wb_local;
-    logic [RegFileDataWidth-1:0]  rf_wdata_wb_ecc_local;
-    logic [RegFileDataWidth-1:0]  rf_rdata_a_ecc_local;
-    logic [RegFileDataWidth-1:0]  rf_rdata_b_ecc_local;
-
-    logic [IC_NUM_WAYS-1:0]       ic_tag_req_local;
-    logic                         ic_tag_write_local;
-    logic [IC_INDEX_W-1:0]        ic_tag_addr_local;
-    logic [TagSizeECC-1:0]        ic_tag_wdata_local;
-    logic [IC_NUM_WAYS-1:0]       ic_data_req_local;
-    logic                         ic_data_write_local;
-    logic [IC_INDEX_W-1:0]        ic_data_addr_local;
-    logic [LineSizeECC-1:0]       ic_data_wdata_local;
-    logic                         scramble_key_valid_local;
-
-    logic                         irq_software_local;
-    logic                         irq_timer_local;
-    logic                         irq_external_local;
-    logic [14:0]                  irq_fast_local;
-    logic                         irq_nm_local;
-    logic                         irq_pending_local;
-
-    logic                         debug_req_local;
-    crash_dump_t                  crash_dump_local;
-    logic                         double_fault_seen_local;
-    fetch_enable_t                fetch_enable_local;
-
-    logic                         icache_inval_local;
-    logic                         core_busy_local;
-
-    assign buf_in = {
-      hart_id_i,
-      boot_addr_i,
-      instr_req_o,
-      instr_gnt_i,
-      instr_rvalid_i,
-      instr_addr_o,
-      instr_rdata_i,
-      instr_rdata_intg_i,
-      instr_err_i,
-      data_req_o,
-      data_gnt_i,
-      data_rvalid_i,
-      data_we_o,
-      data_be_o,
-      data_addr_o,
-      data_wdata_o,
-      data_rdata_i,
-      data_rdata_intg_i,
-      data_err_i,
-      dummy_instr_id,
-      rf_raddr_a,
-      rf_raddr_b,
-      rf_waddr_wb,
-      rf_we_wb,
-      rf_wdata_wb_ecc,
-      rf_rdata_a_ecc,
-      rf_rdata_b_ecc,
-      ic_tag_req,
-      ic_tag_write,
-      ic_tag_addr,
-      ic_tag_wdata,
-      ic_data_req,
-      ic_data_write,
-      ic_data_addr,
-      ic_data_wdata,
-      scramble_key_valid_q,
-      irq_software_i,
-      irq_timer_i,
-      irq_external_i,
-      irq_fast_i,
-      irq_nm_i,
-      irq_pending,
-      debug_req_i,
-      crash_dump_o,
-      double_fault_seen_o,
-      fetch_enable_i,
-      icache_inval,
-      core_busy_d
-    };
-
-    assign {
-      hart_id_local,
-      boot_addr_local,
-      instr_req_local,
-      instr_gnt_local,
-      instr_rvalid_local,
-      instr_addr_local,
-      instr_rdata_local,
-      instr_rdata_intg_local,
-      instr_err_local,
-      data_req_local,
-      data_gnt_local,
-      data_rvalid_local,
-      data_we_local,
-      data_be_local,
-      data_addr_local,
-      data_wdata_local,
-      data_rdata_local,
-      data_rdata_intg_local,
-      data_err_local,
-      dummy_instr_id_local,
-      rf_raddr_a_local,
-      rf_raddr_b_local,
-      rf_waddr_wb_local,
-      rf_we_wb_local,
-      rf_wdata_wb_ecc_local,
-      rf_rdata_a_ecc_local,
-      rf_rdata_b_ecc_local,
-      ic_tag_req_local,
-      ic_tag_write_local,
-      ic_tag_addr_local,
-      ic_tag_wdata_local,
-      ic_data_req_local,
-      ic_data_write_local,
-      ic_data_addr_local,
-      ic_data_wdata_local,
-      scramble_key_valid_local,
-      irq_software_local,
-      irq_timer_local,
-      irq_external_local,
-      irq_fast_local,
-      irq_nm_local,
-      irq_pending_local,
-      debug_req_local,
-      crash_dump_local,
-      double_fault_seen_local,
-      fetch_enable_local,
-      icache_inval_local,
-      core_busy_local
-    } = buf_out;
-
-    // Manually buffer all input signals.
-    prim_buf #(.Width(NumBufferBits)) u_signals_prim_buf (
-      .in_i(buf_in),
-      .out_o(buf_out)
-    );
-
-    logic [TagSizeECC-1:0]  ic_tag_rdata_local [IC_NUM_WAYS];
-    logic [LineSizeECC-1:0] ic_data_rdata_local [IC_NUM_WAYS];
-    for (genvar k = 0; k < IC_NUM_WAYS; k++) begin : gen_ways
-      prim_buf #(.Width(TagSizeECC)) u_tag_prim_buf (
-        .in_i(ic_tag_rdata[k]),
-        .out_o(ic_tag_rdata_local[k])
-      );
-      prim_buf #(.Width(LineSizeECC)) u_data_prim_buf (
-        .in_i(ic_data_rdata[k]),
-        .out_o(ic_data_rdata_local[k])
-      );
-    end
-
-    logic lockstep_alert_minor_local, lockstep_alert_major_internal_local;
-    logic lockstep_alert_major_bus_local;
-
-    ibex_lockstep #(
-      .PMPEnable        (PMPEnable),
-      .PMPGranularity   (PMPGranularity),
-      .PMPNumRegions    (PMPNumRegions),
-      .MHPMCounterNum   (MHPMCounterNum),
-      .MHPMCounterWidth (MHPMCounterWidth),
-      .RV32E            (RV32E),
-      .RV32M            (RV32M),
-      .RV32B            (RV32B),
-      .BranchTargetALU  (BranchTargetALU),
-      .ICache           (ICache),
-      .ICacheECC        (ICacheECC),
-      .BusSizeECC       (BusSizeECC),
-      .TagSizeECC       (TagSizeECC),
-      .LineSizeECC      (LineSizeECC),
-      .BranchPredictor  (BranchPredictor),
-      .DbgTriggerEn     (DbgTriggerEn),
-      .DbgHwBreakNum    (DbgHwBreakNum),
-      .WritebackStage   (WritebackStage),
-      .ResetAll         (ResetAll),
-      .RndCnstLfsrSeed  (RndCnstLfsrSeed),
-      .RndCnstLfsrPerm  (RndCnstLfsrPerm),
-      .SecureIbex       (SecureIbex),
-      .DummyInstructions(DummyInstructions),
-      .RegFileECC       (RegFileECC),
-      .RegFileDataWidth (RegFileDataWidth),
-      .DmHaltAddr       (DmHaltAddr),
-      .DmExceptionAddr  (DmExceptionAddr)
-    ) u_ibex_lockstep (
-      .clk_i                  (clk),
-      .rst_ni                 (rst_ni),
-
-      .hart_id_i              (hart_id_local),
-      .boot_addr_i            (boot_addr_local),
-
-      .instr_req_i            (instr_req_local),
-      .instr_gnt_i            (instr_gnt_local),
-      .instr_rvalid_i         (instr_rvalid_local),
-      .instr_addr_i           (instr_addr_local),
-      .instr_rdata_i          (instr_rdata_local),
-      .instr_rdata_intg_i     (instr_rdata_intg_local),
-      .instr_err_i            (instr_err_local),
-
-      .data_req_i             (data_req_local),
-      .data_gnt_i             (data_gnt_local),
-      .data_rvalid_i          (data_rvalid_local),
-      .data_we_i              (data_we_local),
-      .data_be_i              (data_be_local),
-      .data_addr_i            (data_addr_local),
-      .data_wdata_i           (data_wdata_local),
-      .data_wdata_intg_o      (data_wdata_intg_local),
-      .data_rdata_i           (data_rdata_local),
-      .data_rdata_intg_i      (data_rdata_intg_local),
-      .data_err_i             (data_err_local),
-
-      .dummy_instr_id_i       (dummy_instr_id_local),
-      .rf_raddr_a_i           (rf_raddr_a_local),
-      .rf_raddr_b_i           (rf_raddr_b_local),
-      .rf_waddr_wb_i          (rf_waddr_wb_local),
-      .rf_we_wb_i             (rf_we_wb_local),
-      .rf_wdata_wb_ecc_i      (rf_wdata_wb_ecc_local),
-      .rf_rdata_a_ecc_i       (rf_rdata_a_ecc_local),
-      .rf_rdata_b_ecc_i       (rf_rdata_b_ecc_local),
-
-      .ic_tag_req_i           (ic_tag_req_local),
-      .ic_tag_write_i         (ic_tag_write_local),
-      .ic_tag_addr_i          (ic_tag_addr_local),
-      .ic_tag_wdata_i         (ic_tag_wdata_local),
-      .ic_tag_rdata_i         (ic_tag_rdata_local),
-      .ic_data_req_i          (ic_data_req_local),
-      .ic_data_write_i        (ic_data_write_local),
-      .ic_data_addr_i         (ic_data_addr_local),
-      .ic_data_wdata_i        (ic_data_wdata_local),
-      .ic_data_rdata_i        (ic_data_rdata_local),
-      .ic_scr_key_valid_i     (scramble_key_valid_local),
-
-      .irq_software_i         (irq_software_local),
-      .irq_timer_i            (irq_timer_local),
-      .irq_external_i         (irq_external_local),
-      .irq_fast_i             (irq_fast_local),
-      .irq_nm_i               (irq_nm_local),
-      .irq_pending_i          (irq_pending_local),
-
-      .debug_req_i            (debug_req_local),
-      .crash_dump_i           (crash_dump_local),
-      .double_fault_seen_i    (double_fault_seen_local),
-
-      .fetch_enable_i         (fetch_enable_local),
-      .alert_minor_o          (lockstep_alert_minor_local),
-      .alert_major_internal_o (lockstep_alert_major_internal_local),
-      .alert_major_bus_o      (lockstep_alert_major_bus_local),
-      .icache_inval_i         (icache_inval_local),
-      .core_busy_i            (core_busy_local),
-      .test_en_i              (test_en_i),
-      .scan_rst_ni            (scan_rst_ni)
-    );
-
-    // Manually buffer the output signals.
-    prim_buf #(.Width (7)) u_prim_buf_wdata_intg (
-      .in_i(data_wdata_intg_local),
-      .out_o(data_wdata_intg_o)
-    );
-
-    prim_buf u_prim_buf_alert_minor (
-      .in_i (lockstep_alert_minor_local),
-      .out_o(lockstep_alert_minor)
-    );
-
-    prim_buf u_prim_buf_alert_major_internal (
-      .in_i (lockstep_alert_major_internal_local),
-      .out_o(lockstep_alert_major_internal)
-    );
-
-    prim_buf u_prim_buf_alert_major_bus (
-      .in_i (lockstep_alert_major_bus_local),
-      .out_o(lockstep_alert_major_bus)
-    );
-
-  end else begin : gen_no_lockstep
-    assign lockstep_alert_major_internal = 1'b0;
-    assign lockstep_alert_major_bus      = 1'b0;
-    assign lockstep_alert_minor          = 1'b0;
-    assign data_wdata_intg_o             = 'b0;
-    logic unused_scan, unused_intg;
-    assign unused_scan = scan_rst_ni;
-    assign unused_intg = |{instr_rdata_intg_i, data_rdata_intg_i};
-  end
-
-  assign alert_major_internal_o = core_alert_major | lockstep_alert_major_internal;
-  assign alert_major_bus_o      = lockstep_alert_major_bus;
-  assign alert_minor_o          = core_alert_minor | lockstep_alert_minor;
-
-  // X checks for top-level outputs
-  `ASSERT_KNOWN(IbexInstrReqX, instr_req_o)
-  `ASSERT_KNOWN_IF(IbexInstrReqPayloadX, instr_addr_o, instr_req_o)
-
-  `ASSERT_KNOWN(IbexDataReqX, data_req_o)
-  `ASSERT_KNOWN_IF(IbexDataReqPayloadX,
-    {data_we_o, data_be_o, data_addr_o, data_wdata_o, data_wdata_intg_o}, data_req_o)
-
-  `ASSERT_KNOWN(IbexScrambleReqX, scramble_req_o)
-  `ASSERT_KNOWN(IbexDoubleFaultSeenX, double_fault_seen_o)
-  `ASSERT_KNOWN(IbexAlertMinorX, alert_minor_o)
-  `ASSERT_KNOWN(IbexAlertMajorInternalX, alert_major_internal_o)
-  `ASSERT_KNOWN(IbexAlertMajorBusX, alert_major_bus_o)
-  `ASSERT_KNOWN(IbexCoreSleepX, core_sleep_o)
-
-  // X check for top-level inputs
-  `ASSERT_KNOWN(IbexTestEnX, test_en_i)
-  `ASSERT_KNOWN(IbexRamCfgX, ram_cfg_i)
-  `ASSERT_KNOWN(IbexHartIdX, hart_id_i)
-  `ASSERT_KNOWN(IbexBootAddrX, boot_addr_i)
-
-  `ASSERT_KNOWN(IbexInstrGntX, instr_gnt_i)
-  `ASSERT_KNOWN(IbexInstrRValidX, instr_rvalid_i)
-  `ASSERT_KNOWN_IF(IbexInstrRPayloadX,
-    {instr_rdata_i, instr_rdata_intg_i, instr_err_i}, instr_rvalid_i)
-
-  `ASSERT_KNOWN(IbexDataGntX, data_gnt_i)
-  `ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i)
-  `ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_rdata_intg_i, data_err_i}, data_rvalid_i)
-
-  `ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i})
-
-  `ASSERT_KNOWN(IbexScrambleKeyValidX, scramble_key_valid_i)
-  `ASSERT_KNOWN_IF(IbexScramblePayloadX, {scramble_key_i, scramble_nonce_i}, scramble_key_valid_i)
-
-  `ASSERT_KNOWN(IbexDebugReqX, debug_req_i)
-  `ASSERT_KNOWN(IbexFetchEnableX, fetch_enable_i)
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_wb_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_wb_stage.sv
deleted file mode 100644
index 14364c57..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/ibex_wb_stage.sv
+++ /dev/null
@@ -1,214 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-/**
- * Writeback Stage
- *
- * Writeback is an optional third pipeline stage. It writes data back to the register file that was
- * produced in the ID/EX stage or awaits a response to a load/store (LSU writes direct to register
- * file for load data). If the writeback stage is not present (WritebackStage == 0) this acts as
- * a simple passthrough to write data direct to the register file.
- */
-
-`include "prim_assert.sv"
-//`include "dv_fcov_macros.svh"
-
-module ibex_wb_stage #(
-  parameter bit ResetAll       = 1'b0,
-  parameter bit WritebackStage = 1'b0
-) (
-  input  logic                     clk_i,
-  input  logic                     rst_ni,
-
-  input  logic                     en_wb_i,
-  input  ibex_pkg::wb_instr_type_e instr_type_wb_i,
-  input  logic [31:0]              pc_id_i,
-  input  logic                     instr_is_compressed_id_i,
-  input  logic                     instr_perf_count_id_i,
-
-  output logic                     ready_wb_o,
-  output logic                     rf_write_wb_o,
-  output logic                     outstanding_load_wb_o,
-  output logic                     outstanding_store_wb_o,
-  output logic [31:0]              pc_wb_o,
-  output logic                     perf_instr_ret_wb_o,
-  output logic                     perf_instr_ret_compressed_wb_o,
-  output logic                     perf_instr_ret_wb_spec_o,
-  output logic                     perf_instr_ret_compressed_wb_spec_o,
-
-  input  logic [4:0]               rf_waddr_id_i,
-  input  logic [31:0]              rf_wdata_id_i,
-  input  logic                     rf_we_id_i,
-
-  input  logic [31:0]              rf_wdata_lsu_i,
-  input  logic                     rf_we_lsu_i,
-
-  output logic [31:0]              rf_wdata_fwd_wb_o,
-
-  output logic [4:0]               rf_waddr_wb_o,
-  output logic [31:0]              rf_wdata_wb_o,
-  output logic                     rf_we_wb_o,
-
-  input logic                      lsu_resp_valid_i,
-  input logic                      lsu_resp_err_i,
-
-  output logic                     instr_done_wb_o
-);
-
-  import ibex_pkg::*;
-
-  // 0 == RF write from ID
-  // 1 == RF write from LSU
-  logic [31:0] rf_wdata_wb_mux    [2];
-  logic [1:0]  rf_wdata_wb_mux_we;
-
-  if (WritebackStage) begin : g_writeback_stage
-    logic [31:0]    rf_wdata_wb_q;
-    logic           rf_we_wb_q;
-    logic [4:0]     rf_waddr_wb_q;
-
-    logic           wb_done;
-
-    logic           wb_valid_q;
-    logic [31:0]    wb_pc_q;
-    logic           wb_compressed_q;
-    logic           wb_count_q;
-    wb_instr_type_e wb_instr_type_q;
-
-    logic           wb_valid_d;
-
-    // Stage becomes valid if an instruction enters for ID/EX and valid is cleared when instruction
-    // is done
-    assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);
-
-    // Writeback for non load/store instructions always completes in a cycle (so instantly done)
-    // Writeback for load/store must wait for response to be received by the LSU
-    // Signal only relevant if wb_valid_q set
-    assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i;
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-      if (!rst_ni) begin
-        wb_valid_q <= 1'b0;
-      end else begin
-        wb_valid_q <= wb_valid_d;
-      end
-    end
-
-    if (ResetAll) begin : g_wb_regs_ra
-      always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (!rst_ni) begin
-          rf_we_wb_q      <= '0;
-          rf_waddr_wb_q   <= '0;
-          rf_wdata_wb_q   <= '0;
-          wb_instr_type_q <= wb_instr_type_e'(0);
-          wb_pc_q         <= '0;
-          wb_compressed_q <= '0;
-          wb_count_q      <= '0;
-        end else if (en_wb_i) begin
-          rf_we_wb_q      <= rf_we_id_i;
-          rf_waddr_wb_q   <= rf_waddr_id_i;
-          rf_wdata_wb_q   <= rf_wdata_id_i;
-          wb_instr_type_q <= instr_type_wb_i;
-          wb_pc_q         <= pc_id_i;
-          wb_compressed_q <= instr_is_compressed_id_i;
-          wb_count_q      <= instr_perf_count_id_i;
-        end
-      end
-    end else begin : g_wb_regs_nr
-      always_ff @(posedge clk_i) begin
-        if (en_wb_i) begin
-          rf_we_wb_q      <= rf_we_id_i;
-          rf_waddr_wb_q   <= rf_waddr_id_i;
-          rf_wdata_wb_q   <= rf_wdata_id_i;
-          wb_instr_type_q <= instr_type_wb_i;
-          wb_pc_q         <= pc_id_i;
-          wb_compressed_q <= instr_is_compressed_id_i;
-          wb_count_q      <= instr_perf_count_id_i;
-        end
-      end
-    end
-
-    assign rf_waddr_wb_o         = rf_waddr_wb_q;
-    assign rf_wdata_wb_mux[0]    = rf_wdata_wb_q;
-    assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q;
-
-    assign ready_wb_o = ~wb_valid_q | wb_done;
-
-    // Instruction in writeback will be writing to register file if either rf_we is set or writeback
-    // is awaiting load data. This is used for determining RF read hazards in ID/EX
-    assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD));
-
-    assign outstanding_load_wb_o  = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD);
-    assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE);
-
-    assign pc_wb_o = wb_pc_q;
-
-    assign instr_done_wb_o = wb_valid_q & wb_done;
-
-    // Increment instruction retire counters for valid instructions which are not lsu errors.
-    // Speculative versions of the signals do not factor in exceptions and whether the instruction
-    // is done yet. These are used to get correct values for instructions reading the relevant
-    // performance counters in the ID stage.
-    assign perf_instr_ret_wb_spec_o            = wb_count_q;
-    assign perf_instr_ret_compressed_wb_spec_o = perf_instr_ret_wb_spec_o & wb_compressed_q;
-    assign perf_instr_ret_wb_o                 = instr_done_wb_o & wb_count_q &
-                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);
-    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & wb_compressed_q;
-
-    // Forward data that will be written to the RF back to ID to resolve data hazards. The flopped
-    // rf_wdata_wb_q is used rather than rf_wdata_wb_o as the latter includes read data from memory
-    // that returns too late to be used on the forwarding path.
-    assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
-  end else begin : g_bypass_wb
-    // without writeback stage just pass through register write signals
-    assign rf_waddr_wb_o         = rf_waddr_id_i;
-    assign rf_wdata_wb_mux[0]    = rf_wdata_id_i;
-    assign rf_wdata_wb_mux_we[0] = rf_we_id_i;
-
-    // Increment instruction retire counters for valid instructions which are not lsu errors.
-    // The speculative signals are always 0 when no writeback stage is present as the raw counter
-    // values will be correct.
-    assign perf_instr_ret_wb_spec_o            = 1'b0;
-    assign perf_instr_ret_compressed_wb_spec_o = 1'b0;
-    assign perf_instr_ret_wb_o                 = instr_perf_count_id_i & en_wb_i &
-                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);
-    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & instr_is_compressed_id_i;
-
-    // ready needs to be constant 1 without writeback stage (otherwise ID/EX stage will stall)
-    assign ready_wb_o    = 1'b1;
-
-    // Unused Writeback stage only IO & wiring
-    // Assign inputs and internal wiring to unused signals to satisfy lint checks
-    // Tie-off outputs to constant values
-    logic           unused_clk;
-    logic           unused_rst;
-    wb_instr_type_e unused_instr_type_wb;
-    logic [31:0]    unused_pc_id;
-
-    assign unused_clk            = clk_i;
-    assign unused_rst            = rst_ni;
-    assign unused_instr_type_wb  = instr_type_wb_i;
-    assign unused_pc_id          = pc_id_i;
-
-    assign outstanding_load_wb_o  = 1'b0;
-    assign outstanding_store_wb_o = 1'b0;
-    assign pc_wb_o                = '0;
-    assign rf_write_wb_o          = 1'b0;
-    assign rf_wdata_fwd_wb_o      = 32'b0;
-    assign instr_done_wb_o        = 1'b0;
-  end
-
-  assign rf_wdata_wb_mux[1]    = rf_wdata_lsu_i;
-  assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
-
-  // RF write data can come from ID results (all RF writes that aren't because of loads will come
-  // from here) or the LSU (RF writes for load data)
-  assign rf_wdata_wb_o = ({32{rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) |
-                         ({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
-  assign rf_we_wb_o    = |rf_wdata_wb_mux_we;
-
-  //`DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)
-
-  `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/README.md b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/README.md
new file mode 100644
index 00000000..e69de29b
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core
new file mode 100644
index 00000000..02c03356
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core
@@ -0,0 +1,17 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dv_fcov_macros"
+description: "DV FCOV macros"
+
+filesets:
+  files_fcov:
+    files:
+      - dv_fcov_macros.svh: {is_include_file: true}
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_fcov
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
new file mode 100644
index 00000000..8ca12cdc
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh
@@ -0,0 +1,112 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include FCOV RTL by default. Disable it for synthesis and where explicitly requested (by defining
+// DV_FCOV_DISABLE).
+`ifdef SYNTHESIS
+  `define DV_FCOV_DISABLE
+`elsif YOSYS
+  `define DV_FCOV_DISABLE
+`endif
+
+// Disable instantiations of FCOV coverpoints or covergroups.
+`ifdef VERILATOR
+  `define DV_FCOV_DISABLE_CP
+`elsif DV_FCOV_DISABLE
+  `define DV_FCOV_DISABLE_CP
+`endif
+
+// Instantiates a covergroup in an interface or module.
+//
+// This macro assumes that a covergroup of the same name as the NAME_ arg is defined in the
+// interface or module. It just adds some extra signals and logic to control the creation of the
+// covergroup instance with ~bit en_<cg_name>~. This defaults to 0. It is ORed with the external
+// COND_ signal. The testbench can modify it at t = 0 based on the test being run.
+// NOTE: This is not meant to be invoked inside a class.
+//
+// NAME_ : Name of the covergroup.
+// COND_ : External condition / expr that controls the creation of the covergroup.
+// ARGS_ : Arguments to covergroup instance, if any. Args MUST BE wrapped in (..).
+`ifndef DV_FCOV_INSTANTIATE_CG
+`ifdef DV_FCOV_DISABLE_CP
+  `define DV_FCOV_INSTANTIATE_CG(NAME_, COND_ = 1'b1, ARGS_ = ())
+`else
+  `define DV_FCOV_INSTANTIATE_CG(NAME_, COND_ = 1'b1, ARGS_ = ()) \
+    bit en_``NAME_ = 1'b0; \
+    NAME_ NAME_``_inst; \
+    initial begin \
+      /* The #1 delay below allows any part of the tb to control the conditions first at t = 0. */ \
+      #1; \
+      if ((en_``NAME_) || (COND_)) begin \
+        $display("%0t: (%0s:%0d) [%m] %0s", $time, `__FILE__, `__LINE__, \
+                 {"Creating covergroup ", `"NAME_`"}); \
+        NAME_``_inst = new``ARGS_; \
+      end \
+    end
+`endif
+`endif
+
+// Creates a coverpoint for an expression where only the expression true case is of interest for
+// coverage (e.g. where the expression indicates an event has occured).
+`ifndef DV_FCOV_EXPR_SEEN
+`ifdef DV_FCOV_DISABLE_CP
+  `define DV_FCOV_EXPR_SEEN(NAME_, EXPR_)
+`else
+  `define DV_FCOV_EXPR_SEEN(NAME_, EXPR_) cp_``NAME_: coverpoint EXPR_ { bins seen = {1}; }
+`endif
+`endif
+
+// Creates a SVA cover that can be used in a covergroup.
+//
+// This macro creates an unnamed SVA cover from the property (or an expression) `PROP_` and an event
+// with the name `EV_NAME_`. When the SVA cover is hit, the event is triggered. A coverpoint can
+// cover the `triggered` property of the event.
+`ifndef DV_FCOV_SVA
+`ifdef DV_FCOV_DISABLE
+  `define DV_FCOV_SVA(EV_NAME_, PROP_, CLK_ = clk_i, RST_ = rst_ni)
+`else
+  `define DV_FCOV_SVA(EV_NAME_, PROP_, CLK_ = clk_i, RST_ = rst_ni) \
+    event EV_NAME_; \
+    cover property (@(posedge CLK_) disable iff (RST_ == 0) (PROP_)) begin \
+      -> EV_NAME_; \
+    end
+`endif
+`endif
+
+// Coverage support is not always available but it's useful to include extra fcov signals for
+// linting purposes. They need to be marked as unused to avoid warnings.
+`ifndef DV_FCOV_MARK_UNUSED
+  `define DV_FCOV_MARK_UNUSED(TYPE_, NAME_) \
+    TYPE_ unused_fcov_``NAME_; \
+    assign unused_fcov_``NAME_ = fcov_``NAME_;
+`endif
+
+// Define a signal and expression in the design for capture in functional coverage
+`ifndef DV_FCOV_SIGNAL
+`ifdef DV_FCOV_DISABLE
+  `define DV_FCOV_SIGNAL(TYPE_, NAME_, EXPR_)
+`else
+  `define DV_FCOV_SIGNAL(TYPE_, NAME_, EXPR_) \
+    TYPE_ fcov_``NAME_; \
+    assign fcov_``NAME_ = EXPR_; \
+    `DV_FCOV_MARK_UNUSED(TYPE_, NAME_)
+`endif
+`endif
+
+// Define a signal and expression in the design for capture in functional coverage depending on
+// design configuration. The input GEN_COND_ must be a constant or parameter.
+`ifndef DV_FCOV_SIGNAL_GEN_IF
+`ifdef DV_FCOV_DISABLE
+  `define DV_FCOV_SIGNAL_GEN_IF(TYPE_, NAME_, EXPR_, GEN_COND_, DEFAULT_ = '0)
+`else
+  `define DV_FCOV_SIGNAL_GEN_IF(TYPE_, NAME_, EXPR_, GEN_COND_, DEFAULT_ = '0) \
+    TYPE_ fcov_``NAME_; \
+    if (GEN_COND_) begin : g_fcov_``NAME_ \
+      assign fcov_``NAME_ = EXPR_; \
+    end else begin : g_no_fcov_``NAME_ \
+      assign fcov_``NAME_ = DEFAULT_; \
+    end \
+    `DV_FCOV_MARK_UNUSED(TYPE_, NAME_)
+`endif
+`endif
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core
new file mode 100644
index 00000000..5f2fb800
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.core
@@ -0,0 +1,17 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dv_macros"
+description: "A collection of macros used in DV."
+
+filesets:
+  files_dv:
+    files:
+      - dv_macros.svh: {is_include_file: true}
+    file_type: systemVerilogSource
+
+targets:
+  default: &default_target
+    filesets:
+      - files_dv
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
new file mode 100644
index 00000000..2e5e1375
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh
@@ -0,0 +1,536 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`ifdef UVM
+  `include "uvm_macros.svh"
+`endif
+
+// UVM speficic macros
+`ifndef gfn
+`ifdef UVM
+  // verilog_lint: waive macro-name-style
+  `define gfn get_full_name()
+`else
+  // verilog_lint: waive macro-name-style
+  `define gfn $sformatf("%m")
+`endif
+`endif
+
+`ifndef gtn
+  // verilog_lint: waive macro-name-style
+  `define gtn get_type_name()
+`endif
+
+`ifndef gn
+  // verilog_lint: waive macro-name-style
+  `define gn get_name()
+`endif
+
+`ifndef gmv
+  // verilog_lint: waive macro-name-style
+  `define gmv(csr) csr.get_mirrored_value()
+`endif
+
+// cast base class obj holding extended class handle to extended class handle;
+// throw error if cast fails
+`ifndef downcast
+  // verilog_lint: waive macro-name-style
+  `define downcast(EXT_, BASE_, MSG_="", SEV_=fatal, ID_=`gfn) \
+    begin \
+      if (!$cast(EXT_, BASE_)) begin \
+        `dv_``SEV_($sformatf({"Cast failed: base class variable %0s ", \
+                              "does not hold extended class %0s handle %s"}, \
+                              `"BASE_`", `"EXT_`", MSG_), ID_) \
+      end \
+    end
+`endif
+
+// Note, UVM provides a macro `uvm_new_func -- which only applies to uvm_components
+`ifndef uvm_object_new
+  `define uvm_object_new \
+    function new (string name=""); \
+      super.new(name); \
+    endfunction : new
+`endif
+
+`ifndef uvm_create_obj
+  `define uvm_create_obj(_type_name_, _inst_name_) \
+    _inst_name_ = _type_name_::type_id::create(`"_inst_name_`");
+`endif
+
+`ifndef uvm_component_new
+  `define uvm_component_new \
+    function new (string name="", uvm_component parent=null); \
+      super.new(name, parent); \
+    endfunction : new
+`endif
+
+`ifndef uvm_create_comp
+  `define uvm_create_comp(_type_name_, _inst_name_) \
+    _inst_name_ = _type_name_::type_id::create(`"_inst_name_`", this);
+`endif
+
+// Convert arbitrary text / expression to string.
+`ifndef DV_STRINGIFY
+  `define DV_STRINGIFY(I_) `"I_`"
+`endif
+
+`ifndef DUT_HIER_STR
+  `define DUT_HIER_STR `DV_STRINGIFY(`DUT_HIER)
+`endif
+
+// Common check macros used by DV_CHECK error and fatal macros.
+// Note: Should not be called by user code
+`ifndef DV_CHECK
+  `define DV_CHECK(T_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!(T_)) begin \
+        `dv_``SEV_($sformatf("Check failed (%s) %s ", `"T_`", MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_EQ
+  `define DV_CHECK_EQ(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) == (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s == %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_NE
+  `define DV_CHECK_NE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) != (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s != %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_CASE_EQ
+  `define DV_CHECK_CASE_EQ(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) === (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s === %s (0x%0h [%0b] vs 0x%0h [%0b]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_CASE_NE
+  `define DV_CHECK_CASE_NE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) !== (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s !== %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_LT
+  `define DV_CHECK_LT(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) < (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s < %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_GT
+  `define DV_CHECK_GT(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) > (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s > %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_LE
+  `define DV_CHECK_LE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) <= (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s <= %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_GE
+  `define DV_CHECK_GE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
+      if (!((ACT_) >= (EXP_))) begin \
+        `dv_``SEV_($sformatf("Check failed %s >= %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
+                             `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_), ID_) \
+      end \
+    end
+`endif
+
+`ifndef DV_CHECK_STREQ
+  `define DV_CHECK_STREQ(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    if (!((ACT_) == (EXP_))) begin \
+      `dv_``SEV_($sformatf("Check failed \"%s\" == \"%s\" %s", ACT_, EXP_, MSG_), ID_) \
+    end
+`endif
+
+`ifndef DV_CHECK_STRNE
+  `define DV_CHECK_STRNE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    if (!((ACT_) != (EXP_))) begin \
+      `dv_``SEV_($sformatf("Check failed \"%s\" != \"%s\" %s", ACT_, EXP_, MSG_), ID_) \
+    end
+`endif
+
+// Fatal version of the checks
+`ifndef DV_CHECK_FATAL
+  `define DV_CHECK_FATAL(T_, MSG_="", ID_=`gfn) \
+    `DV_CHECK(T_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_EQ_FATAL
+  `define DV_CHECK_EQ_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_EQ(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_NE_FATAL
+  `define DV_CHECK_NE_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_NE(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_LT_FATAL
+  `define DV_CHECK_LT_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_LT(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_GT_FATAL
+  `define DV_CHECK_GT_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_GT(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_LE_FATAL
+  `define DV_CHECK_LE_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_LE(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_GE_FATAL
+  `define DV_CHECK_GE_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_GE(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_STREQ_FATAL
+  `define DV_CHECK_STREQ_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_STREQ(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+`ifndef DV_CHECK_STRNE_FATAL
+  `define DV_CHECK_STRNE_FATAL(ACT_, EXP_, MSG_="", ID_=`gfn) \
+    `DV_CHECK_STRNE(ACT_, EXP_, MSG_, fatal, ID_)
+`endif
+
+// Shorthand for common foo.randomize() + fatal check
+`ifndef DV_CHECK_RANDOMIZE_FATAL
+  `define DV_CHECK_RANDOMIZE_FATAL(VAR_, MSG_="Randomization failed!", ID_=`gfn) \
+    `DV_CHECK_FATAL(VAR_.randomize(), MSG_, ID_)
+`endif
+
+// Shorthand for common foo.randomize() with { } + fatal check
+`ifndef DV_CHECK_RANDOMIZE_WITH_FATAL
+  `define DV_CHECK_RANDOMIZE_WITH_FATAL(VAR_, WITH_C_, MSG_="Randomization failed!", ID_=`gfn) \
+    `DV_CHECK_FATAL(VAR_.randomize() with {WITH_C_}, MSG_, ID_)
+`endif
+
+// Shorthand for common std::randomize(foo) + fatal check
+`ifndef DV_CHECK_STD_RANDOMIZE_FATAL
+  `define DV_CHECK_STD_RANDOMIZE_FATAL(VAR_, MSG_="Randomization failed!", ID_=`gfn) \
+    `DV_CHECK_FATAL(std::randomize(VAR_), MSG_, ID_)
+`endif
+
+// Shorthand for common std::randomize(foo) with { } + fatal check
+`ifndef DV_CHECK_STD_RANDOMIZE_WITH_FATAL
+  `define DV_CHECK_STD_RANDOMIZE_WITH_FATAL(VAR_, WITH_C_, MSG_="Randomization failed!",ID_=`gfn) \
+    `DV_CHECK_FATAL(std::randomize(VAR_) with {WITH_C_}, MSG_, ID_)
+`endif
+
+// Shorthand for common cls_inst.randomize(member) + fatal check
+// Randomizes a specific member of a class instance.
+`ifndef DV_CHECK_MEMBER_RANDOMIZE_FATAL
+  `define DV_CHECK_MEMBER_RANDOMIZE_FATAL(VAR_, CLS_INST_=this, MSG_="Randomization failed!", ID_=`gfn) \
+    `DV_CHECK_FATAL(CLS_INST_.randomize(VAR_), MSG_, ID_)
+`endif
+
+// Shorthand for common cls_inst.randomize(member) with { } + fatal check
+// Randomizes a specific member of a class instance with inline constraints.
+`ifndef DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL
+  `define DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(VAR_, C_, CLS_INST_=this, MSG_="Randomization failed!", ID_=`gfn) \
+    `DV_CHECK_FATAL(CLS_INST_.randomize(VAR_) with {C_}, MSG_, ID_)
+`endif
+
+// print static/dynamic 1d array or queue
+`ifndef DV_PRINT_ARR_CONTENTS
+`define DV_PRINT_ARR_CONTENTS(ARR_, V_=uvm_pkg::UVM_MEDIUM, ID_=`gfn) \
+  begin \
+    foreach (ARR_[i]) begin \
+      `dv_info($sformatf("%s[%0d] = %0d (0x%0h)", `"ARR_`", i, ARR_[i], ARR_[i]), V_, ID_) \
+    end \
+  end
+`endif
+
+// print non-empty tlm fifos that were uncompared at end of test
+`ifndef DV_EOT_PRINT_TLM_FIFO_CONTENTS
+`define DV_EOT_PRINT_TLM_FIFO_CONTENTS(TYP_, FIFO_, SEV_=error, ID_=`gfn) \
+  begin \
+    while (!FIFO_.is_empty()) begin \
+      TYP_ item; \
+      void'(FIFO_.try_get(item)); \
+      `dv_``SEV_($sformatf("%s item uncompared:\n%s", `"FIFO_`", item.sprint()), ID_) \
+    end \
+  end
+`endif
+
+// print non-empty tlm fifos that were uncompared at end of test
+`ifndef DV_EOT_PRINT_TLM_FIFO_ARR_CONTENTS
+`define DV_EOT_PRINT_TLM_FIFO_ARR_CONTENTS(TYP_, FIFO_, SEV_=error, ID_=`gfn) \
+  begin \
+    foreach (FIFO_[i]) begin \
+      while (!FIFO_[i].is_empty()) begin \
+        TYP_ item; \
+        void'(FIFO_[i].try_get(item)); \
+        `dv_``SEV_($sformatf("%s[%0d] item uncompared:\n%s", `"FIFO_`", i, item.sprint()), ID_) \
+      end \
+    end \
+  end
+`endif
+
+// print non-empty tlm fifos that were uncompared at end of test
+`ifndef DV_EOT_PRINT_Q_CONTENTS
+`define DV_EOT_PRINT_Q_CONTENTS(TYP_, Q_, SEV_=error, ID_=`gfn) \
+  begin \
+    while (Q_.size() != 0) begin \
+      TYP_ item = Q_.pop_front(); \
+      `dv_``SEV_($sformatf("%s item uncompared:\n%s", `"Q_`", item.sprint()), ID_) \
+    end \
+  end
+`endif
+
+// print non-empty tlm fifos that were uncompared at end of test
+`ifndef DV_EOT_PRINT_Q_ARR_CONTENTS
+`define DV_EOT_PRINT_Q_ARR_CONTENTS(TYP_, Q_, SEV_=error, ID_=`gfn) \
+  begin \
+    foreach (Q_[i]) begin \
+      while (Q_[i].size() != 0) begin \
+        TYP_ item = Q_[i].pop_front(); \
+        `dv_``SEV_($sformatf("%s[%0d] item uncompared:\n%s", `"Q_`", i, item.sprint()), ID_) \
+      end \
+    end \
+  end
+`endif
+
+// check for non-empty mailbox and print items that were uncompared at end of test
+`ifndef DV_EOT_PRINT_MAILBOX_CONTENTS
+`define DV_EOT_PRINT_MAILBOX_CONTENTS(TYP_, MAILBOX_, SEV_=error, ID_=`gfn) \
+  begin \
+    while (MAILBOX_.num() != 0) begin \
+      TYP_ item; \
+      void'(MAILBOX_.try_get(item)); \
+      `dv_``SEV_($sformatf("%s item uncompared:\n%s", `"MAILBOX_`", item.sprint()), ID_) \
+    end \
+  end
+`endif
+
+// get parity - implemented as a macro so that it can be invoked in constraints as well
+`ifndef GET_PARITY
+  `define GET_PARITY(val, odd=0) (^val ^ odd)
+`endif
+
+// Wait a task or statement with exit condition
+// Kill the thread when either the wait statement is completed or exit condition occurs
+// input WAIT_ need to be a statement. Here are some examples
+// `DV_SPINWAIT(wait(...);, "Wait for ...")
+// `DV_SPINWAIT(
+//              while (1) begin
+//                ...
+//              end)
+`ifndef DV_SPINWAIT_EXIT
+`define DV_SPINWAIT_EXIT(WAIT_, EXIT_, MSG_ = "exit condition occurred!", ID_ =`gfn) \
+  begin \
+    fork begin \
+      fork \
+        begin \
+          WAIT_ \
+        end \
+        begin \
+          EXIT_ \
+          if (MSG_ != "") begin \
+            `dv_info(MSG_, uvm_pkg::UVM_HIGH, ID_) \
+          end \
+        end \
+      join_any \
+      disable fork; \
+    end join \
+  end
+`endif
+
+// wait a task or statement with timer watchdog
+`ifndef DV_SPINWAIT
+`define DV_SPINWAIT(WAIT_, MSG_ = "timeout occurred!", TIMEOUT_NS_ = default_spinwait_timeout_ns, ID_ =`gfn) \
+  `DV_SPINWAIT_EXIT(WAIT_, wait_timeout(TIMEOUT_NS_, ID_, MSG_);, "", ID_)
+`endif
+
+// Control assertions in the DUT.
+//
+// This macro is invoked in top level testbench that instantiates the DUT. It spawns off an initial
+// block that forever waits for a resource of type bit named by the string arg ~LABEL_~ that
+// can be set by any entity in the testbench. Based on the value set, it enables or disables the
+// assertions at the hierarchy of the provided path. The entity setting the resource value invokes
+// uvm_config_db#(bit)::set(...) and this macro calls the corresponding get.
+//
+// LABEL_ : Name of the assertion control resource bit (string).
+// HIER_  : Path to the module within which the assertion is controlled.
+// LEVELS_: Number of levels within the module to control the assertions.
+// SCOPE_ : Hierarchical string path to the testbench where this macro is invoked, example: %m.
+// ID_    : Identifier string used for UVM logs.
+`ifndef DV_ASSERT_CTRL
+`define DV_ASSERT_CTRL(LABEL_, HIER_, LEVELS_ = 0, SCOPE_ = "", ID_ = $sformatf("%m")) \
+  initial begin \
+    bit assert_en; \
+    forever begin \
+      uvm_config_db#(bit)::wait_modified(null, SCOPE_, LABEL_); \
+      if (!uvm_config_db#(bit)::get(null, SCOPE_, LABEL_, assert_en)) begin \
+        `uvm_fatal(ID_, $sformatf("Failed to get \"%0s\" from uvm_config_db", LABEL_)) \
+      end \
+      if (assert_en) begin \
+        `uvm_info(ID_, $sformatf("Enabling assertions: %0s", `DV_STRINGIFY(HIER_)), UVM_LOW) \
+        $asserton(LEVELS_, HIER_); \
+      end else begin \
+        `uvm_info(ID_, $sformatf("Disabling assertions: %0s", `DV_STRINGIFY(HIER_)), UVM_LOW) \
+        $assertoff(LEVELS_, HIER_); \
+      end \
+    end \
+  end
+`endif
+
+// Retrieves a plusarg value representing an enum literal.
+//
+// The plusarg is parsed as a string, which needs to be converted into the enum literal whose name
+// matches the string. This functionality is provided by the UVM helper function below.
+//
+// ENUM_: The enum type.
+// VAR_: The enum variable to which the plusarg value will be set (must be declared already).
+// PLUSARG_: the name of the plusarg (as raw text). This is typically the same as the enum variable.
+// CHECK_EXISTS_: Throws a fatal error if the plusarg is not set.
+`ifndef DV_GET_ENUM_PLUSARG
+`define DV_GET_ENUM_PLUSARG(ENUM_, VAR_, PLUSARG_ = VAR_, CHECK_EXISTS_ = 0, ID_ = `gfn) \
+  begin \
+    string str; \
+    if ($value$plusargs("``PLUSARG_``=%0s", str)) begin \
+      if (!uvm_enum_wrapper#(ENUM_)::from_name(str, VAR_)) begin \
+        `uvm_fatal(ID_, $sformatf("Cannot find %s from enum ``ENUM_``", VAR_.name())) \
+      end \
+    end else if (CHECK_EXISTS_) begin \
+      `uvm_fatal(ID_, "Please pass the plusarg +``PLUSARG_``=<``ENUM_``-literal>") \
+    end \
+  end
+`endif
+
+// Enable / disable assertions at a module hierarchy identified by LABEL_.
+//
+// This goes in conjunction with `DV_ASSERT_CTRL() macro above, but is invoked in the entity that is
+// sending the req to turn on / off the assertions. Note that that piece of code invoking this macro
+// does not have the information on the actual hierarchical path to the module or the levels - this
+// is 'wrapped' into the LABEL_ instead. DV user needs to uniquify the label sufficienly enough to
+// reflect it.
+//
+// LABEL_ : Name of the assertion control resource bit (string).
+// VALUE_ : Value of the control bit - 1 - enable assertions, 0 - disable assertions.
+// SCOPE_ : Hierarchical string path to the testbench where this macro is invoked, example: %m.
+`ifndef DV_ASSERT_CTRL_REQ
+`define DV_ASSERT_CTRL_REQ(LABEL_, VALUE_, SCOPE_="") \
+  begin \
+    uvm_config_db#(bit)::set(null, SCOPE_, LABEL_, VALUE_); \
+  end
+`endif
+
+// Macros for logging (info, warning, error and fatal severities).
+//
+// These are meant to be invoked in modules and interfaces that are shared between DV and Verilator
+// testbenches. We waive the lint requirement for these to be in uppercase, since they are
+// UVM-adjacent.
+`ifdef UVM
+`ifndef dv_info
+  // verilog_lint: waive macro-name-style
+  `define dv_info(MSG_,  VERBOSITY_ = uvm_pkg::UVM_LOW, ID_ = $sformatf("%m")) \
+    if (uvm_pkg::uvm_report_enabled(VERBOSITY_, uvm_pkg::UVM_INFO, ID_)) begin \
+        uvm_pkg::uvm_report_info(ID_, MSG_, VERBOSITY_, `uvm_file, `uvm_line, "", 1); \
+    end
+`endif
+
+`ifndef dv_warning
+  // verilog_lint: waive macro-name-style
+  `define dv_warning(MSG_, ID_ = $sformatf("%m")) \
+    if (uvm_pkg::uvm_report_enabled(uvm_pkg::UVM_NONE, uvm_pkg::UVM_WARNING, ID_)) begin \
+        uvm_pkg::uvm_report_warning(ID_, MSG_, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \
+    end
+`endif
+
+`ifndef dv_error
+  // verilog_lint: waive macro-name-style
+  `define dv_error(MSG_, ID_ = $sformatf("%m")) \
+    if (uvm_pkg::uvm_report_enabled(uvm_pkg::UVM_NONE, uvm_pkg::UVM_ERROR, ID_)) begin \
+        uvm_pkg::uvm_report_error(ID_, MSG_, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \
+    end
+`endif
+
+`ifndef dv_fatal
+  // verilog_lint: waive macro-name-style
+  `define dv_fatal(MSG_, ID_ = $sformatf("%m")) \
+    if (uvm_pkg::uvm_report_enabled(uvm_pkg::UVM_NONE, uvm_pkg::UVM_FATAL, ID_)) begin \
+        uvm_pkg::uvm_report_fatal(ID_, MSG_, uvm_pkg::UVM_NONE, `uvm_file, `uvm_line, "", 1); \
+    end
+`endif
+
+`else // UVM
+
+`ifndef dv_info
+  // verilog_lint: waive macro-name-style
+  `define dv_info(MSG_, VERBOSITY = DUMMY_, ID_ = $sformatf("%m")) \
+    $display("%0t: (%0s:%0d) [%0s] %0s", $time, `__FILE__, `__LINE__, ID_, MSG_);
+`endif
+
+`ifndef dv_warning
+  // verilog_lint: waive macro-name-style
+  `define dv_warning(MSG_, ID_ = $sformatf("%m")) \
+    $warning("%0t: (%0s:%0d) [%0s] %0s", $time, `__FILE__, `__LINE__, ID_, MSG_);
+`endif
+
+`ifndef dv_error
+  // verilog_lint: waive macro-name-style
+  `define dv_error(MSG_, ID_ = $sformatf("%m")) \
+    $error("%0t: (%0s:%0d) [%0s] %0s", $time, `__FILE__, `__LINE__, ID_, MSG_);
+`endif
+
+`ifndef dv_fatal
+  // verilog_lint: waive macro-name-style
+  `define dv_fatal(MSG_, ID_ = $sformatf("%m")) \
+    $fatal("%0t: (%0s:%0d) [%0s] %0s", $time, `__FILE__, `__LINE__, ID_, MSG_);
+`endif
+
+`endif // UVM
+
+// Macros for constrain clk with common frequencies
+// constrain clock to run at 24Mhz - 100Mhz and use higher weights on 24, 25, 48, 50, 100
+`ifndef DV_COMMON_CLK_CONSTRAINT
+`define DV_COMMON_CLK_CONSTRAINT(FREQ_) \
+  FREQ_ dist { \
+    [24:25] :/ 2, \
+    [26:47] :/ 1, \
+    [48:50] :/ 2, \
+    [51:95] :/ 1, \
+    96      :/ 1, \
+    [97:99] :/ 1, \
+    100     :/ 1  \
+  };
+`endif
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv
new file mode 100644
index 00000000..91e3337e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_catcher.sv
@@ -0,0 +1,46 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+// Report catcher/demoter
+class dv_report_catcher extends uvm_report_catcher;
+
+  // Stores a new severity indexed by the ID and
+  // the regular expression to match the message
+  protected uvm_severity m_changed_sev[string][string];
+
+  `uvm_object_utils(dv_report_catcher)
+  `uvm_object_new
+
+  // Called for all report messages - defined in uvm_report_catcher
+  virtual function action_e catch();
+    string id = get_id();
+    if (m_changed_sev.exists(id)) begin
+      string report_msg = get_message();
+      foreach (m_changed_sev[id][msg]) begin
+        if (uvm_re_match(msg, report_msg)) begin
+          set_severity(m_changed_sev[id][msg]);
+        end
+      end
+    end
+    return THROW;
+  endfunction
+
+  // Change severity of a message with ID == id and message text
+  // matching msg which is treated as a regular expression
+  virtual function void add_change_sev(string id, string msg, uvm_severity sev);
+    m_changed_sev[id][msg] = sev;
+  endfunction
+
+  // Remove a change entry
+  // If msg == "" then remove all changes for a given id
+  virtual function void remove_change_sev(string id, string msg = "");
+    if (m_changed_sev.exists(id))
+      if (msg == "") begin
+        // Delete all with id if message is blank
+        m_changed_sev.delete(id);
+      end else if (m_changed_sev[id].exists(msg)) begin
+        m_changed_sev[id].delete(msg);
+      end
+  endfunction
+
+endclass
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv
new file mode 100644
index 00000000..a5d7440e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_report_server.sv
@@ -0,0 +1,65 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Standardize look & feel of report phase and uvm logging messages.
+class dv_report_server extends uvm_default_report_server;
+
+  bit show_file_line = 1'b1;
+  // if enabled, show the relative path of the file. By default only show file name
+  bit show_file_path = 1'b0;
+  bit use_default_uvm_report_message_format = 1'b0;
+
+  function new (string name = "");
+    super.new(name);
+    // provide ability to override these knobs over cli
+    void'($value$plusargs("show_file_line=%0b", show_file_line));
+    void'($value$plusargs("show_file_path=%0b", show_file_path));
+    void'($value$plusargs("use_default_uvm_report_message_format=%0b",
+                           use_default_uvm_report_message_format));
+  endfunction
+
+  function void report_summarize(UVM_FILE file = 0);
+    int num_uvm_warning;
+    int num_uvm_error;
+    int num_uvm_fatal;
+
+    num_uvm_warning = get_severity_count(UVM_WARNING);
+    num_uvm_error   = get_severity_count(UVM_ERROR);
+    num_uvm_fatal   = get_severity_count(UVM_FATAL);
+
+    // Print default summary report
+    super.report_summarize(file);
+
+    // Print final test pass-fail - external tool can use this signature for test status
+    // Treat UVM_WARNINGs as a sign of test failure since it could silently result in false pass
+    dv_test_status_pkg::dv_test_status((num_uvm_warning + num_uvm_error + num_uvm_fatal) == 0);
+  endfunction
+
+  // Override default messaging format to standard "pretty" format for all testbenches
+  virtual function string compose_report_message(uvm_report_message report_message,
+                                                 string report_object_name = "");
+
+    if (use_default_uvm_report_message_format) begin
+      return (super.compose_report_message(report_message, report_object_name));
+    end else begin
+      uvm_severity  severity  = report_message.get_severity();
+      string        filename  = report_message.get_filename();
+      int           line      = report_message.get_line();
+      string        obj_name  = report_message.get_report_object().get_full_name();
+      string        id        = report_message.get_id();
+      string        message   = report_message.get_message();
+      string        file_line;
+
+      if (show_file_line && filename != "") begin
+        if (!show_file_path) filename = str_utils_pkg::str_path_basename(filename);
+        file_line = $sformatf("(%0s:%0d) ", filename, line);
+      end
+      obj_name = {obj_name, ((obj_name != "") ? " " : "")};
+      compose_report_message = $sformatf({"%0s @ %t: ", file_line, obj_name, "[%0s] %0s"},
+                                          severity.name(), $realtime, id, message);
+      return compose_report_message;
+    end
+  endfunction
+
+endclass
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core
new file mode 100644
index 00000000..bbec1b05
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status.core
@@ -0,0 +1,17 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dv_test_status"
+description: "DV test status reporting utilities"
+
+filesets:
+  files_dv:
+    files:
+      - dv_test_status_pkg.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_dv
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv
new file mode 100644
index 00000000..3a81ddfc
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_test_status_pkg.sv
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package dv_test_status_pkg;
+
+  // Prints the test status signature & banner.
+  //
+  // This function takes a boolean arg indicating whether the test passed or failed and prints the
+  // signature along with a banner. The signature can be used by external scripts to determine if
+  // the test passed or failed.
+  function automatic void dv_test_status(bit passed);
+    if (passed) begin
+      $display("\nTEST PASSED CHECKS");
+      $display(" _____         _                                  _ _ ");
+      $display("|_   _|__  ___| |_   _ __   __ _ ___ ___  ___  __| | |");
+      $display("  | |/ _ \\/ __| __| | '_ \\ / _` / __/ __|/ _ \\/ _` | |");
+      $display("  | |  __/\\__ \\ |_  | |_) | (_| \\__ \\__ \\  __/ (_| |_|");
+      $display("  |_|\\___||___/\\__| | .__/ \\__,_|___/___/\\___|\\__,_(_)");
+      $display("                    |_|                               \n");
+    end else begin
+      $display("\nTEST FAILED CHECKS");
+      $display(" _____         _      __       _ _          _ _ ");
+      $display("|_   _|__  ___| |_   / _| __ _(_) | ___  __| | |");
+      $display("  | |/ _ \\/ __| __| | |_ / _` | | |/ _ \\/ _` | |");
+      $display("  | |  __/\\__ \\ |_  |  _| (_| | | |  __/ (_| |_|");
+      $display("  |_|\\___||___/\\__| |_|  \\__,_|_|_|\\___|\\__,_(_)\n");
+    end
+  endfunction
+
+endpackage
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core
new file mode 100644
index 00000000..1e405236
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core
@@ -0,0 +1,28 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dv_utils"
+description: "DV utilities"
+
+filesets:
+  files_dv:
+    depend:
+      - lowrisc:dv:dv_macros
+      - lowrisc:dv:dv_fcov_macros
+      - lowrisc:dv:common_ifs
+      - lowrisc:prim:assert:0.1
+      - lowrisc:cve2:bus_params_pkg
+      - lowrisc:dv:str_utils
+      - lowrisc:dv:dv_test_status
+    files:
+      - dv_utils_pkg.sv
+      - dv_report_catcher.sv: {is_include_file: true}
+      - dv_report_server.sv: {is_include_file: true}
+      - dv_vif_wrap.sv: {is_include_file: true}
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_dv
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
new file mode 100644
index 00000000..62f3b765
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv
@@ -0,0 +1,223 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package dv_utils_pkg;
+  // dep packages
+  import uvm_pkg::*;
+  import bus_params_pkg::*;
+
+  // macro includes
+  `include "dv_macros.svh"
+`ifdef UVM
+  `include "uvm_macros.svh"
+`endif
+
+  // common parameters used across all benches
+  parameter int NUM_MAX_INTERRUPTS = 32;
+  typedef logic [NUM_MAX_INTERRUPTS-1:0] interrupt_t;
+
+  parameter int NUM_MAX_ALERTS = 32;
+  typedef logic [NUM_MAX_ALERTS-1:0] alert_t;
+
+  // types & variables
+  typedef bit [31:0] uint;
+  typedef bit [7:0]  uint8;
+  typedef bit [15:0] uint16;
+  typedef bit [31:0] uint32;
+  typedef bit [63:0] uint64;
+
+  // TODO: The above typedefs violate the name rule, which is fixed below. Cleanup the codebase to
+  // use the typedefs below and remove the ones above.
+  typedef bit [7:0]  uint8_t;
+  typedef bit [15:0] uint16_t;
+  typedef bit [31:0] uint32_t;
+  typedef bit [63:0] uint64_t;
+
+  // typedef parameterized pins_if for ease of implementation for interrupts and alerts
+  typedef virtual pins_if #(NUM_MAX_INTERRUPTS) intr_vif;
+  typedef virtual pins_if #(1)                  devmode_vif;
+
+  // interface direction / mode - Host or Device
+  typedef enum bit {
+    Host,
+    Device
+  } if_mode_e;
+
+  // compare operator types
+  typedef enum {
+    CompareOpEq,
+    CompareOpCaseEq,
+    CompareOpNe,
+    CompareOpCaseNe,
+    CompareOpGt,
+    CompareOpGe,
+    CompareOpLt,
+    CompareOpLe
+  } compare_op_e;
+
+  // mem address struct
+  typedef struct {
+    uvm_reg_addr_t start_addr;
+    uvm_reg_addr_t end_addr;
+  } addr_range_t;
+
+  // Enum representing a bus operation type - read or write.
+  typedef enum bit {
+    BusOpWrite = 1'b0,
+    BusOpRead  = 1'b1
+  } bus_op_e;
+
+  // Enum representing a type of host requests - read only, write only or random read & write
+  typedef enum int {
+    HostReqNone      = 0,
+    HostReqReadOnly  = 1,
+    HostReqWriteOnly = 2,
+    HostReqReadWrite = 3
+  } host_req_type_e;
+
+  // Enum representing clock frequency difference on 2 clocks
+  typedef enum bit [1:0] {
+    ClkFreqDiffNone,
+    ClkFreqDiffSmall,
+    ClkFreqDiffBig,
+    ClkFreqDiffAny
+  } clk_freq_diff_e;
+
+  string msg_id = "dv_utils_pkg";
+
+  // return the smaller value of 2 inputs
+  function automatic int min2(int a, int b);
+      return (a < b) ? a : b;
+  endfunction
+
+  // return the bigger value of 2 inputs
+  function automatic int max2(int a, int b);
+    return (a > b) ? a : b;
+  endfunction
+
+  // return the biggest value within the given queue of integers.
+  function automatic int max(const ref int int_q[$]);
+    `DV_CHECK_GT_FATAL(int_q.size(), 0, "max function cannot accept an empty queue of integers!",
+                       msg_id)
+    // Assign the first value from the queue in case of negative integers.
+    max = int_q[0];
+    foreach (int_q[i]) max = max2(max, int_q[i]);
+    return max;
+  endfunction
+
+  // get absolute value of the input. Usage: absolute(val) or absolute(a - b)
+  function automatic uint absolute(int val);
+    return val >= 0 ? val : -val;
+  endfunction
+
+  // endian swaps a 32-bit data word
+  function automatic logic [31:0] endian_swap(logic [31:0] data);
+    return {<<8{data}};
+  endfunction
+
+  // endian swaps bytes at a word granularity, while preserving overall word ordering.
+  //
+  // e.g. if `arr[] = '{'h0, 'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7}`, this function will produce:
+  //      `'{'h3, 'h2, 'h1, 'h0, 'h7, 'h6, 'h5, 'h4}`
+  function automatic void endian_swap_byte_arr(ref bit [7:0] arr[]);
+    arr = {<< byte {arr}};
+    arr = {<< 32 {arr}};
+  endfunction
+
+`ifdef UVM
+  // Simple function to set max errors before quitting sim
+  function automatic void set_max_quit_count(int n);
+    uvm_report_server report_server = uvm_report_server::get_server();
+    report_server.set_max_quit_count(n);
+  endfunction
+
+  // return if uvm_fatal occurred
+  function automatic bit has_uvm_fatal_occurred();
+    uvm_report_server report_server = uvm_report_server::get_server();
+    return report_server.get_severity_count(UVM_FATAL) > 0;
+  endfunction
+
+  // task that waits for the specfied timeout
+  task automatic wait_timeout(input uint    timeout_ns,
+                              input string  error_msg_id  = msg_id,
+                              input string  error_msg     = "timeout occurred!",
+                              input bit     report_fatal  = 1);
+    #(timeout_ns * 1ns);
+    if (report_fatal) `uvm_fatal(error_msg_id, error_msg)
+    else              `uvm_error(error_msg_id, error_msg)
+  endtask : wait_timeout
+
+  // get masked data based on provided byte mask; if csr reg handle is provided (optional) then
+  // masked bytes from csr's mirrored value are returned, else masked bytes are 0's
+  function automatic bit [bus_params_pkg::BUS_DW-1:0]
+      get_masked_data(bit [bus_params_pkg::BUS_DW-1:0] data,
+                      bit [bus_params_pkg::BUS_DBW-1:0] mask,
+                      uvm_reg csr = null);
+    bit [bus_params_pkg::BUS_DW-1:0] csr_data;
+    csr_data = (csr != null) ? csr.get_mirrored_value() : '0;
+    get_masked_data = data;
+    foreach (mask[i]) begin
+      if (~mask[i]) get_masked_data[i * 8 +: 8] = csr_data[i * 8 +: 8];
+    end
+  endfunction
+
+  // create a sequence by name and return the handle of uvm_sequence
+  function automatic uvm_sequence create_seq_by_name(string seq_name);
+    uvm_object      obj;
+    uvm_factory     factory;
+    uvm_sequence    seq;
+
+    factory = uvm_factory::get();
+    obj = factory.create_object_by_name(seq_name, "", seq_name);
+    if (obj == null) begin
+      // print factory overrides to help debug
+      factory.print(1);
+      `uvm_fatal(msg_id, $sformatf("could not create %0s seq", seq_name))
+    end
+    if (!$cast(seq, obj)) begin
+      `uvm_fatal(msg_id, $sformatf("cast failed - %0s is not a uvm_sequence", seq_name))
+    end
+    return seq;
+  endfunction
+`endif
+
+  // Returns the hierarchical path to the interface / module N levels up.
+  //
+  // Meant to be invoked inside a module or interface.
+  // hier:        String input of the interface / module, typically $sformatf("%m").
+  // n_levels_up: Integer number of levels up the hierarchy to omit.
+  //              Example: if (hier = tb.dut.foo.bar, n_levels_up = 2), then return tb.dut
+  function automatic string get_parent_hier(string hier, int n_levels_up = 1);
+    int idx;
+    int level;
+    if (n_levels_up <= 0) return hier;
+    for (idx = hier.len() - 1; idx >= 0; idx--) begin
+      if (hier[idx] == ".") level++;
+      if (level == n_levels_up) break;
+    end
+    return (hier.substr(0, idx - 1));
+  endfunction
+
+  // Periodically check for the existence of a magic file (dv.stop). Exit if it exists. This
+  // provides a mechanism to gracefully kill a simulation without direct access to the process.
+  task automatic poll_for_stop(uint interval_ns = 10_000, string filename = "dv.stop");
+    fork
+      while (1) begin
+        #(interval_ns * 1ns);
+        if (!$system($sformatf("test -f %0s", filename))) begin
+          $system($sformatf("rm %0s", filename));
+          `dv_fatal($sformatf("Found %0s file. Exiting!", filename), "poll_for_stop")
+        end
+      end
+    join_none
+  endtask : poll_for_stop
+
+  // sources
+`ifdef UVM
+  `include "dv_report_catcher.sv"
+  `include "dv_report_server.sv"
+  `include "dv_vif_wrap.sv"
+`endif
+
+endpackage
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv
new file mode 100644
index 00000000..61d99479
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/vendor/lowrisc_ip/dv/sv/dv_utils/dv_vif_wrap.sv
@@ -0,0 +1,96 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Abstract class meant to hold arbitrary virtual interface handles.
+//
+// Written primarily for an interface which implements functional coverage, this could be used
+// for other purposes as well. This abstract class provides utilities & macros to retrieve
+// virtual interface handles that are bound to a DUT's sub-modules. These sub-module interfaces must
+// self-register using the `DV_VIF_WRAP_SET_VIF()` macro (see details below). The extended class
+// then implements the `get_vifs()` method using the `DV_VIF_WRAP_GET_VIF*` macros below to retrieve
+// the sub-module interface handles it maintains.
+virtual class dv_vif_wrap;
+  string hier;  // Represents the hierarchy of the parent module or interface.
+  string name;  // Name of the class instance.
+
+  function new(string hier, string name = "");
+    this.hier = hier;
+    this.name = name;
+  endfunction
+
+  // Abstract method implemented by the extended class. It is recommended to invoke the helper
+  // macros below rather than manually define it.
+  pure virtual task get_vifs();
+
+endclass
+
+// Helper macros.
+//
+// These are defined in the file itself since they are tightly coupled to the class definition
+// above. These are scoped globally so that extended classes can invoke them.
+
+// Enable an interface to register itself (set its handle into the config db).
+//
+// Meant to be invoked from an interface. The macros invocation causes the interface to register
+// itself into the uvm_resource_db pool. The derived class of dv_vif_wrap retrieves the handle to
+// that interface handle from the uvm_resource db pool.
+//
+// SV LRM does not yet allow referencing the instance of an interface within itself as one
+// would in case of a class using the ~this~ keyword. However, most major simulators actually
+// support this in their own custom way. On VCS, a reference to self within the interface can be set
+// using `interface::self()` construct. On Xcelium, this is achieved by simply referencing the
+// interface name.
+//
+// _IF:    The SV interface
+// _VIF:   The corresponding virtual interface handle name
+// _LEVEL: # of hierarchical levels the module to which the SV interface is bound, starting at the
+//         top level DUT instance.
+`define DV_VIF_WRAP_SET_VIF(_IF, _VIF, _LEVEL = 0) \
+  import uvm_pkg::*; \
+  function automatic void self_register(); \
+    string path; \
+    virtual _IF vif; \
+    /* Initial block adds another level in the path hierarchy which needs to be split out. */ \
+    /* Add one more to go one level up the interface instance. */ \
+    /* Example: tb.dut.core.u_foo_if.self_register -> tb.dut.core. */ \
+    path = dv_utils_pkg::get_parent_hier(.hier($sformatf("%m")), .n_levels_up(2 + _LEVEL)); \
+`ifdef VCS \
+  vif = interface::self(); \
+`elsif XCELIUM \
+  vif = _IF; \
+`else \
+  vif = _IF; \
+`endif \
+    uvm_pkg::uvm_resource_db#(virtual _IF)::set(path, `"_VIF`", vif); \
+  endfunction \
+  initial self_register();
+
+// Enables the retrieval of individual vifs.
+//
+// The three macros below go together to define the _get_vifs() task in the extended class.
+`define DV_VIF_WRAP_GET_VIFS_BEGIN \
+  task get_vifs(); \
+    fork \
+
+// To avoid race condition between the instant when an interface handle is set into the config db
+// and the instant when it is retrieved (in the same time step, at t = 0), the macro below invokes
+// uvm_config_db#(..)::wait_modified() to ensure that the retrieval is done only after the set.
+`define DV_VIF_WRAP_GET_VIF(_IF, _VIF) \
+    begin \
+      bit vif_found; \
+      /* At most 2 retries. */ \
+      repeat (2) begin \
+        /* Force the evaluation at the end of the time step. */ \
+        #0; \
+        if (uvm_pkg::uvm_resource_db#(virtual _IF)::read_by_name(hier, `"_VIF`", _VIF)) begin \
+          vif_found = 1'b1; \
+          break; \
+        end \
+      end \
+      `DV_CHECK_FATAL(vif_found, {`"_VIF`", " not found in the resource db"}, hier) \
+    end
+
+`define DV_VIF_WRAP_GET_VIFS_END \
+    join \
+  endtask
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.core
index f11d35c1..1d8a39f7 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.core
@@ -64,3 +64,4 @@ targets:
     - files_rtl
     - ff_regfile
     - target_sim? (files_clk_gate)
+    - target_sim_sc? (files_clk_gate)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson
index 00ea518e..b122083e 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/openhwgroup/cv32e40p.git
-    rev: c8d65849ec060c6f7bc62325b46ba0ab7eae8805
+    rev: 370cf19b3b60cbdc847ff102551392dd501029a2
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson
index 462a2848..5b2ce889 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/openhwgroup/cv32e40p.git",
-    rev: "c8d65849ec060c6f7bc62325b46ba0ab7eae8805",
+    rev: "370cf19b3b60cbdc847ff102551392dd501029a2",
   },
 
   patch_dir: "patches/openhwgroup_cv32e40p",
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore
index ef351b19..66eb251a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore
@@ -18,3 +18,9 @@ TAGS
 /build
 /Bender.lock
 /Bender.local
+golden_reference_design
+golden.src
+revised.src
+cadence_conformal
+synopsys_formality
+questa_autocheck
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh
index 8c4ae99f..a89ed4e4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh
@@ -679,22 +679,22 @@ class instr_trace_t;
       // decode and print instruction
       case (instr[11:8])
         // cv.starti, cv.endi
-        4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, rd[0], imm_iz_type);
+        4'b0000, 4'b0010: str = $sformatf("%-16s %d, 0x%0x", mnemonic, instr[7], imm_iz_type);
         // cv.counti
-        4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, rd[0], imm_iz_type);
+        4'b0100: str = $sformatf("%-16s %d, %d", mnemonic, instr[7], imm_iz_type);
         // cv.start, cv.end, cv.count
         4'b0001, 4'b0011, 4'b0101: begin
           regs_read.push_back('{rs1, rs1_value, 0});
-          str = $sformatf("%-16s %d, %s", mnemonic, rd[0], regAddrToStr(rs1));
+          str = $sformatf("%-16s %d, %s", mnemonic, instr[7], regAddrToStr(rs1));
         end
         // cv.setupi
         4'b0110: begin
-          str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, rd[0], imm_iz_type, rs1);
+          str = $sformatf("%-16s %d, %d, 0x%0x", mnemonic, instr[7], imm_iz_type, rs1);
         end
         // cv.setup
         4'b0111: begin
           regs_read.push_back('{rs1, rs1_value, 0});
-          str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, rd[0], regAddrToStr(rs1), imm_iz_type);
+          str = $sformatf("%-16s %d, %s, 0x%0x", mnemonic, instr[7], regAddrToStr(rs1), imm_iz_type);
         end
       endcase
     end
@@ -861,7 +861,7 @@ class instr_trace_t;
           endcase
           str_sci  = "";
         end
-  
+
         // shuffle/pack
         6'b110000: begin
           if (instr[14:12] == 3'b111) begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv
index ca158f96..13a5beb0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv
@@ -73,6 +73,10 @@ module cv32e40p_rvfi
     input logic        is_compressed_id_i,
 
     input logic ebrk_insn_dec_i,
+    input logic ecall_insn_dec_i,
+
+    input logic mret_insn_dec_i,
+    input logic mret_dec_i,
 
     input logic [5:0] csr_cause_i,
 
@@ -126,6 +130,9 @@ module cv32e40p_rvfi
     input logic [31:0] data_wdata_ex_i,
     input logic        lsu_split_q_ex_i,
 
+    input logic mult_ready_i,
+    input logic alu_ready_i,
+
     //// WB probes ////
     input logic [31:0] pc_wb_i,
     input logic        wb_ready_i,
@@ -202,6 +209,7 @@ module cv32e40p_rvfi
     input logic            csr_we_i,
     input logic     [31:0] csr_wdata_int_i,
 
+    input logic    csr_fregs_we_i,
     input logic    csr_jvt_we_i,
     input Status_t csr_mstatus_n_i,
     input Status_t csr_mstatus_q_i,
@@ -617,6 +625,8 @@ module cv32e40p_rvfi
   logic pc_mux_interrupt;
   logic pc_mux_nmi;
 
+  localparam logic [31:0] MSTATUS_WRITE_MASK = 32'h0000_6088;
+
   `include "pipe_freeze_trace.sv"
 
   `include "insn_trace.sv"
@@ -633,6 +643,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
   logic   [2:0] saved_debug_cause;
   integer       next_send;
 
+  event         e_empty_queue;
   function void empty_fifo();
     integer i, trace_q_size;
     trace_q_size = wb_bypass_trace_q.size();
@@ -648,6 +659,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           new_rvfi_trace.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
           rvfi_trace_q.push_back(new_rvfi_trace);
           next_send = next_send + 1;
+          ->e_empty_queue;
         end else begin
           wb_bypass_trace_q.push_back(new_rvfi_trace);
         end
@@ -658,6 +670,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
   /*
    * Function used to alocate a new insn and send it to the rvfi driver
    */
+  event e_add_to_bypass;
   function void send_rvfi(insn_trace_t m_wb_insn);
     insn_trace_t new_rvfi_trace;
     new_rvfi_trace = new();
@@ -667,6 +680,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       next_send = next_send + 1;
     end else begin
       wb_bypass_trace_q.push_back(new_rvfi_trace);
+      ->e_add_to_bypass;
     end
     empty_fifo();
   endfunction
@@ -837,7 +851,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
     //CSR
     rvfi_csr_mstatus_rmask = new_rvfi_trace.m_csr.mstatus_rmask | new_rvfi_trace.m_csr.mstatus_fs_rmask;
-    rvfi_csr_mstatus_wmask = new_rvfi_trace.m_csr.mstatus_wmask;
+    rvfi_csr_mstatus_wmask = new_rvfi_trace.m_csr.mstatus_wmask & MSTATUS_WRITE_MASK;
     rvfi_csr_mstatus_wmask[31] = new_rvfi_trace.m_csr.mstatus_fs_wmask[31];
     rvfi_csr_mstatus_wmask[14:13] = new_rvfi_trace.m_csr.mstatus_fs_wmask[14:13];
 
@@ -870,7 +884,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     end
     rvfi_csr_mstatus_wdata[30:18] = '0;
     // MPRV is not implemented in the target configuration, writes to it are ignored
-    rvfi_csr_mstatus_wdata[17] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.mprv;
+    rvfi_csr_mstatus_wdata[17] = 1'b0;  //new_rvfi_trace.m_csr.mstatus_wdata.mprv;
     rvfi_csr_mstatus_wdata[16:15] = '0;
     if (FPU == 1 && ZFINX == 0) begin
       rvfi_csr_mstatus_wdata[14:13] = new_rvfi_trace.m_csr.mstatus_fs_wdata;
@@ -882,11 +896,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     rvfi_csr_mstatus_wdata[7] = new_rvfi_trace.m_csr.mstatus_wdata.mpie;
     rvfi_csr_mstatus_wdata[6:5] = '0;
     // UPIE is not implemented in the target configuration, writes to it are ignored
-    rvfi_csr_mstatus_wdata[4] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.upie;
+    rvfi_csr_mstatus_wdata[4] = 1'b0;  //new_rvfi_trace.m_csr.mstatus_wdata.upie;
     rvfi_csr_mstatus_wdata[3] = new_rvfi_trace.m_csr.mstatus_wdata.mie;
     rvfi_csr_mstatus_wdata[2:1] = '0;
     // UIE is not implemented in the target configuration, writes to it are ignored
-    rvfi_csr_mstatus_wdata[0] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.uie;
+    rvfi_csr_mstatus_wdata[0] = 1'b0;  //new_rvfi_trace.m_csr.mstatus_wdata.uie;
 
     `SET_RVFI_CSR_FROM_INSN(misa)
     `SET_RVFI_CSR_FROM_INSN(mie)
@@ -1111,6 +1125,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
    * The third updates the rvfi interface
    */
   `define CSR_FROM_PIPE(TRACE_NAME, CSR_NAME) \
+    if(!trace_``TRACE_NAME``.m_csr.``CSR_NAME``_we) begin \
+      trace_``TRACE_NAME``.m_csr.``CSR_NAME``_wdata   = r_pipe_freeze_trace.csr.``CSR_NAME``_n; \
+    end\
     if (r_pipe_freeze_trace.csr.``CSR_NAME``_we) begin \
       trace_``TRACE_NAME``.m_csr.``CSR_NAME``_we      = r_pipe_freeze_trace.csr.``CSR_NAME``_we; \
       trace_``TRACE_NAME``.m_csr.``CSR_NAME``_wdata   = r_pipe_freeze_trace.csr.``CSR_NAME``_n; \
@@ -1120,9 +1137,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     trace_``TRACE_NAME``.m_csr.``CSR_NAME``_rmask   = '1;
 
   event e_mstatus_to_id;
+  event e_fregs_dirty_1, e_fregs_dirty_2, e_fregs_dirty_3;
   function void mstatus_to_id();
     `CSR_FROM_PIPE(id, mstatus)
     `CSR_FROM_PIPE(id, mstatus_fs)
+    if(r_pipe_freeze_trace.csr.fregs_we && !r_pipe_freeze_trace.csr.mstatus_fs_we && !(r_pipe_freeze_trace.csr.we && r_pipe_freeze_trace.csr.mstatus_fs_we)) begin //writes happening in ex that needs to be reported to id
+      trace_id.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
+      ->e_fregs_dirty_2;
+    end
     ->e_mstatus_to_id;
   endfunction
   //those event are for debug purpose
@@ -1133,10 +1155,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       e_dev_commit_rf_to_ex_3,
       e_dev_commit_rf_to_ex_4,
       e_dev_commit_rf_to_ex_5;
-  event e_if_2_id_1, e_if_2_id_2;
+  event e_if_2_id_1, e_if_2_id_2, e_if_2_id_3, e_if_2_id_4;
   event e_ex_to_wb_1, e_ex_to_wb_2;
   event e_id_to_ex_1, e_id_to_ex_2;
   event e_commit_dpc;
+  event e_csr_in_ex, e_csr_irq;
 
   event e_send_rvfi_trace_apu_resp;
   event
@@ -1160,12 +1183,17 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     `CSR_FROM_PIPE(apu_resp, fcsr)
     `CSR_FROM_PIPE(apu_resp, fflags)
 
-    // `CSR_FROM_PIPE(apu_resp, mstatus)
     `CSR_FROM_PIPE(apu_resp, mstatus_fs)
 
-    if (r_pipe_freeze_trace.csr.mstatus_we) begin
+    if (r_pipe_freeze_trace.csr.mstatus_fs_we && (trace_id.m_order > trace_apu_resp.m_order)) begin
+      trace_id.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
+    end
+    if (r_pipe_freeze_trace.csr.mstatus_fs_we && (trace_ex.m_order > trace_apu_resp.m_order)) begin
       trace_ex.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
     end
+    if (r_pipe_freeze_trace.csr.mstatus_fs_we && (trace_wb.m_order > trace_apu_resp.m_order)) begin
+      trace_wb.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
+    end
   endfunction
 
   function void csr_to_apu_req();
@@ -1243,14 +1271,22 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
   bit s_is_irq_start;
   bit s_id_done;
   function void if_to_id();
+    if (trace_id.m_valid) begin
+      `CSR_FROM_PIPE(id, misa)
+      `CSR_FROM_PIPE(id, tdata1)
+      `CSR_FROM_PIPE(id, tdata2)
+      tinfo_to_id();
+      `CSR_FROM_PIPE(id, mip)
+      send_rvfi(trace_id);
+    end
     trace_id.init(trace_if);
     trace_id.m_trap       = ~r_pipe_freeze_trace.minstret;
-    trace_id.m_is_illegal = r_pipe_freeze_trace.is_illegal;
+    trace_id.m_is_illegal = trace_id.m_is_illegal | r_pipe_freeze_trace.is_illegal;
+    `CSR_FROM_PIPE(id, dpc)
     s_is_pc_set           = 1'b0;
     s_is_irq_start        = 1'b0;
     trace_if.m_valid      = 1'b0;
     s_id_done             = 1'b0;
-    `CSR_FROM_PIPE(id, dpc)
   endfunction
 
   function logic [31:0] be_to_mask(logic [3:0] be);
@@ -1280,34 +1316,44 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
     bit s_core_is_decoding;  // For readability, ctrl_fsm is DECODE or DECODE_HWLOOP
 
-    trace_if            = new();
-    trace_id            = new();
-    trace_ex            = new();
-    trace_wb            = new();
-    s_new_valid_insn    = 1'b0;
-    s_ex_valid_adjusted = 1'b0;
+    bit s_ex_reg_we_adjusted;  //ex_reg_we
+    bit s_rf_we_wb_adjusted;  //
+
+    bit s_dont_override_mstatus_fs_id;
+
+    trace_if             = new();
+    trace_id             = new();
+    trace_ex             = new();
+    trace_wb             = new();
+    s_new_valid_insn     = 1'b0;
+    s_ex_valid_adjusted  = 1'b0;
+
+    s_id_done            = 1'b0;
+    s_apu_wb_ok          = 1'b0;
+    s_apu_0_cycle_reps   = 1'b0;
+
+    next_send            = 1;
+    cnt_data_req         = 0;
+    cnt_data_resp        = 0;
+    cnt_apu_req          = 0;
+    cnt_apu_resp         = 0;
+    csr_is_irq           = '0;
+    is_dbg_taken         = '0;
+    s_was_flush          = 1'b0;
 
-    s_id_done           = 1'b0;
-    s_apu_wb_ok         = 1'b0;
-    s_apu_0_cycle_reps  = 1'b0;
+    s_is_pc_set          = 1'b0;
+    s_is_irq_start       = 1'b0;
 
-    next_send           = 1;
-    cnt_data_req        = 0;
-    cnt_data_resp       = 0;
-    cnt_apu_req         = 0;
-    cnt_apu_resp        = 0;
-    csr_is_irq          = '0;
-    is_dbg_taken        = '0;
-    s_was_flush         = 1'b0;
+    s_is_pc_set          = 1'b0;
+    s_is_irq_start       = 1'b0;
+    s_skip_wb            = 1'b0;
 
-    s_is_pc_set         = 1'b0;
-    s_is_irq_start      = 1'b0;
+    s_core_is_decoding   = 1'b0;
 
-    s_is_pc_set         = 1'b0;
-    s_is_irq_start      = 1'b0;
-    s_skip_wb           = 1'b0;
+    s_ex_reg_we_adjusted = 1'b0;
+    s_rf_we_wb_adjusted  = 1'b0;
 
-    s_core_is_decoding  = 1'b0;
+    s_dont_override_mstatus_fs_id = 1'b0;
 
     forever begin
       wait(e_pipe_monitor_ok.triggered);  // event triggered
@@ -1325,19 +1371,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       end
 
       if (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID && r_pipe_freeze_trace.ebrk_insn_dec) begin
-        if (trace_wb.m_valid) begin
-          send_rvfi(trace_wb);
-          trace_wb.m_valid = 1'b0;
-          ->e_send_rvfi_trace_wb_1;
-        end
-        if (trace_ex.m_valid) begin
-          send_rvfi(trace_ex);
-          trace_ex.m_valid = 1'b0;
-          ->e_send_rvfi_trace_ex_1;
-        end
         if (trace_id.m_valid) begin
-
-          minstret_to_id();
           `CSR_FROM_PIPE(id, misa)
           `CSR_FROM_PIPE(id, tdata1)
           `CSR_FROM_PIPE(id, tdata2)
@@ -1387,7 +1421,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       s_new_valid_insn = r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.is_decoding;// && !r_pipe_freeze_trace.apu_rvalid;
 
-      s_wb_valid_adjusted = r_pipe_freeze_trace.wb_valid && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX));// && !r_pipe_freeze_trace.apu_rvalid;;
+      s_wb_valid_adjusted = r_pipe_freeze_trace.wb_valid && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) || (r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_WB) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF));// && !r_pipe_freeze_trace.apu_rvalid;;
+      s_ex_reg_we_adjusted = r_pipe_freeze_trace.ex_reg_we && r_pipe_freeze_trace.mult_ready && r_pipe_freeze_trace.alu_ready && r_pipe_freeze_trace.lsu_ready_ex && !s_apu_to_alu_port;
+      s_rf_we_wb_adjusted = r_pipe_freeze_trace.rf_we_wb && (~r_pipe_freeze_trace.data_misaligned_ex && r_pipe_freeze_trace.wb_ready) && (!s_apu_to_lsu_port || r_pipe_freeze_trace.wb_contention_lsu);
 
       s_fflags_we_non_apu = 1'b0;
       if (r_pipe_freeze_trace.csr.fflags_we) begin
@@ -1418,60 +1454,55 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           s_skip_wb = 1'b1;
         end
       end
-      if (trace_wb.m_valid && !s_skip_wb) begin
-        if (r_pipe_freeze_trace.rf_we_wb) begin
-          if((trace_wb.m_rd_addr[0] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[0]) && trace_wb.m_mem_req_id_valid[0]) begin
-            trace_wb.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_wb.m_mem_req_id_valid[0] = 1'b0;
-          end else if (trace_wb.m_2_rd_insn && (trace_wb.m_rd_addr[1] == r_pipe_freeze_trace.rf_addr_wb) && (cnt_data_resp == trace_wb.m_mem_req_id[1]) && trace_wb.m_mem_req_id_valid[1]) begin
-            trace_wb.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_wb.m_mem_req_id_valid[1] = 1'b0;
-          end
-        end
 
-        if (!trace_wb.m_data_missaligned) begin
-          send_rvfi(trace_wb);
-          ->e_dev_send_wb_1; ->e_send_rvfi_trace_wb_2;
-          trace_wb.m_valid = 1'b0;
+      if (trace_wb.m_valid && !s_skip_wb && s_rf_we_wb_adjusted) begin
+        if (trace_wb.m_2_rd_insn) begin
+          trace_wb.m_rd_addr[1]  = r_pipe_freeze_trace.rf_addr_wb;
+          trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
+        end else if (trace_wb.m_ex_fw) begin
+          trace_wb.m_rd_addr[1]  = r_pipe_freeze_trace.rf_addr_wb;
+          trace_wb.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
+          trace_wb.m_2_rd_insn   = 1'b1;
         end else begin
-          if (s_wb_valid_adjusted) begin
-            if (r_pipe_freeze_trace.rf_we_wb) begin
-              if (!trace_wb.m_ex_fw) begin
-                trace_wb.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
-                trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-              end
-              if (trace_wb.m_data_missaligned && !trace_wb.m_got_first_data) begin
-                trace_wb.m_got_first_data = 1'b1;
-              end else begin
-                send_rvfi(trace_wb);
-                ->e_dev_send_wb_2; ->e_send_rvfi_trace_wb_3;
-                trace_wb.m_valid = 1'b0;
-              end
-            end  // rf_we_wb
+          trace_wb.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
+          trace_wb.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
+        end
+
+        if (r_pipe_freeze_trace.csr.fregs_we) begin
+          `CSR_FROM_PIPE(wb, mstatus_fs)
+          trace_wb.m_csr.mstatus_fs_we = 1'b1;
+          trace_wb.m_csr.mstatus_fs_wmask = '1;
+          if(r_pipe_freeze_trace.csr.we && r_pipe_freeze_trace.csr.mstatus_fs_we) begin //In this specific case, two writes to mstatus_fs happen at the same time. We need to recreate the writes caused by fregs_we
+            trace_wb.m_csr.mstatus_fs_wdata = FS_DIRTY;
           end
+          ->e_fregs_dirty_1;
         end
+
+        send_rvfi(trace_wb);
+        ->e_dev_send_wb_1; ->e_send_rvfi_trace_wb_2;
+        trace_wb.m_valid = 1'b0;
+
       end
 
       if (trace_ex.m_valid) begin
-
-        if (!trace_ex.m_csr.got_minstret) begin
+        if(trace_ex.m_instret_smaple_trigger == 1) begin //time to sample instret
           minstret_to_ex();
         end
+        trace_ex.m_instret_smaple_trigger = trace_ex.m_instret_smaple_trigger + 1;
+
         `CSR_FROM_PIPE(ex, misa)
         `CSR_FROM_PIPE(ex, tdata1)
         `CSR_FROM_PIPE(ex, tdata2)
         tinfo_to_ex();
 
-        if (r_pipe_freeze_trace.regfile_we_lsu) begin
+        if (s_rf_we_wb_adjusted) begin
           ->e_dev_commit_rf_to_ex_4;
-          if ((cnt_data_resp == trace_ex.m_mem_req_id[0]) && !(trace_ex.m_got_ex_reg) && trace_ex.m_mem_req_id_valid[0]) begin
+          if (!(trace_ex.m_got_ex_reg) && trace_ex.m_mem_req_id_valid[0]) begin
             trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
             trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
             trace_ex.m_got_first_data = 1'b1;
             trace_ex.m_mem_req_id_valid[0] = 1'b0;
-          end else if ((cnt_data_resp == trace_ex.m_mem_req_id[1])  && trace_ex.m_mem_req_id_valid[1]) begin
+          end else if (trace_ex.m_mem_req_id_valid[1]) begin
             trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
             trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
             trace_ex.m_got_first_data = 1'b1;
@@ -1485,7 +1516,8 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_ex.m_valid = 1'b0;
             ->e_send_rvfi_trace_ex_2;
           end else begin
-            if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port) begin
+
+            if (s_rf_we_wb_adjusted) begin
               ->e_dev_commit_rf_to_ex_1;
               if (trace_ex.m_got_ex_reg) begin
                 trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
@@ -1497,24 +1529,35 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
                 trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
                 trace_ex.m_got_first_data = 1'b1;
               end
-            end
 
-            if (!s_ex_valid_adjusted & !trace_ex.m_csr.got_minstret) begin
-              minstret_to_ex();
-            end
-            if (trace_ex.m_is_load) begin  // only move relevant instr in wb stage
-              ->e_ex_to_wb_1;
-              trace_wb.move_down_pipe(trace_ex);
-            end else begin
-              if (!trace_ex.m_csr.got_minstret) begin
-                minstret_to_ex();
+              if (r_pipe_freeze_trace.csr.fregs_we && !r_pipe_freeze_trace.apu_rvalid) begin //Catching mstatus_fs updates caused by flw
+                `CSR_FROM_PIPE(ex, mstatus_fs)
+                trace_ex.m_csr.mstatus_fs_we = 1'b1;
+                trace_ex.m_csr.mstatus_fs_wmask = '1;
+                if(r_pipe_freeze_trace.csr.we && r_pipe_freeze_trace.csr.mstatus_fs_we) begin //In this specific case, two writes to mstatus_fs happen at the same time. We need to recreate the writes caused by fregs_we
+                  trace_ex.m_csr.mstatus_fs_wdata = FS_DIRTY;
+                end else begin
+                  trace_id.m_csr.mstatus_fs_rdata = trace_ex.m_csr.mstatus_fs_wdata;
+                  s_dont_override_mstatus_fs_id = 1'b1;
+                end
+                ->e_fregs_dirty_3;
               end
+
               send_rvfi(trace_ex);
-              ->e_send_rvfi_trace_ex_6;
+              trace_ex.m_valid = 1'b0;
+
+            end else begin
+              if (trace_ex.m_is_load) begin  // only move relevant instr in wb stage
+                ->e_ex_to_wb_1;
+                trace_wb.move_down_pipe(trace_ex);
+              end else begin
+                send_rvfi(trace_ex);
+                ->e_send_rvfi_trace_ex_6;
+              end
+              trace_ex.m_valid = 1'b0;
             end
-            trace_ex.m_valid = 1'b0;
           end
-        end else if (r_pipe_freeze_trace.rf_we_wb && !s_apu_to_lsu_port && !s_was_flush) begin
+        end else if (s_rf_we_wb_adjusted && !s_was_flush) begin
           ->e_dev_commit_rf_to_ex_2;
           if (trace_ex.m_got_ex_reg) begin
             trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
@@ -1529,21 +1572,38 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         end
       end
 
-      s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex);
+      // If mret, we need to keep the instruction in Id during flush_ex because mstatus update happens at that time
+      s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || ((r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) && !r_pipe_freeze_trace.mret_insn_dec));
       //EX_STAGE
-      if (trace_id.m_valid) begin
-        mtvec_to_id();
 
-        `CSR_FROM_PIPE(id, mip)
-        `CSR_FROM_PIPE(id, misa)
+      if (trace_id.m_valid) begin
+        if(trace_id.m_instret_smaple_trigger == 1) begin //time to sample instret
+          minstret_to_id();
+        end
+        trace_id.m_instret_smaple_trigger = trace_id.m_instret_smaple_trigger + 1;
 
-        if (!csr_is_irq && !s_is_irq_start) begin
-          mstatus_to_id();
+        if(trace_id.m_sample_csr_write_in_ex && !csr_is_irq && !s_is_irq_start) begin //First cycle after id_ready, csr write is asserted in this cycle
+          `CSR_FROM_PIPE(id, mstatus)
+          if(!s_dont_override_mstatus_fs_id) begin
+              `CSR_FROM_PIPE(id, mstatus_fs)
+          end
           `CSR_FROM_PIPE(id, mepc)
-          if (trace_id.m_csr.mcause_we == '0) begin  //for debug purpose
-            `CSR_FROM_PIPE(id, mcause)
+          `CSR_FROM_PIPE(id, mcause)
+          `CSR_FROM_PIPE(id, dscratch0)
+          `CSR_FROM_PIPE(id, dscratch1)
+          if(r_pipe_freeze_trace.csr.we && (r_pipe_freeze_trace.csr.addr == CSR_DPC)) begin
+            `CSR_FROM_PIPE(id, dpc)
           end
+          ->e_csr_in_ex;
+        end
+
+        if(r_pipe_freeze_trace.is_decoding) begin
+            trace_id.m_sample_csr_write_in_ex = 1'b0;
         end
+        mtvec_to_id();
+
+        `CSR_FROM_PIPE(id, mip)
+        `CSR_FROM_PIPE(id, misa)
 
         `CSR_FROM_PIPE(id, mcountinhibit)
         `CSR_FROM_PIPE(id, mscratch)
@@ -1553,10 +1613,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         `CSR_FROM_PIPE(id, frm)
         `CSR_FROM_PIPE(id, fcsr)
 
-        if (r_pipe_freeze_trace.csr.we) begin
-          `CSR_FROM_PIPE(id, dpc)
-        end
-
         if (r_pipe_freeze_trace.csr.dcsr_we) begin
           dcsr_to_id();
         end
@@ -1577,6 +1633,15 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         trace_ex.m_csr.frm_wmask    = '0;
         trace_ex.m_csr.fcsr_wmask   = '0;
 
+        if(r_pipe_freeze_trace.ctrl_fsm_cs == XRET_JUMP) begin //xret exit pipeline
+            tinfo_to_id();
+            `CSR_FROM_PIPE(id, tdata1)
+            `CSR_FROM_PIPE(id, tdata2)
+            send_rvfi(trace_id);
+            trace_id.m_valid = 1'b0;
+            s_dont_override_mstatus_fs_id = 1'b0;
+        end
+
         if (r_pipe_freeze_trace.apu_req && r_pipe_freeze_trace.apu_gnt) begin
           trace_id.m_is_apu = 1'b1;
           trace_id.m_apu_req_id = cnt_apu_req;
@@ -1586,6 +1651,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           trace_apu_req.set_to_apu();
           apu_trace_q.push_back(trace_apu_req);
           trace_id.m_valid = 1'b0;
+          s_dont_override_mstatus_fs_id = 1'b0;
 
           if(r_pipe_freeze_trace.apu_rvalid && (cnt_apu_req == cnt_apu_resp)) begin//APU return in the same cycle
             apu_resp();
@@ -1603,10 +1669,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_id.m_rd_addr[0]  = r_pipe_freeze_trace.ex_reg_addr;
             trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.ex_reg_wdata;
             trace_id.m_got_ex_reg = 1'b1;
-          end else if (!trace_ex.m_valid & r_pipe_freeze_trace.rf_we_wb & !trace_id.m_ex_fw) begin
+          end else if (!trace_ex.m_valid & s_rf_we_wb_adjusted & !trace_id.m_ex_fw) begin
             trace_id.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
             trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-          end else if (r_pipe_freeze_trace.rf_we_wb) begin
+          end else if (s_rf_we_wb_adjusted) begin
             trace_id.m_rd_addr[1]  = r_pipe_freeze_trace.rf_addr_wb;
             trace_id.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
             trace_id.m_2_rd_insn   = 1'b1;
@@ -1621,19 +1687,16 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp;
             if (r_pipe_freeze_trace.data_misaligned) begin
               cnt_data_req = cnt_data_req + 1;
+              trace_id.m_mem_req_id[0] = cnt_data_req;
             end
+
             if (!r_pipe_freeze_trace.data_we_ex) begin
               trace_id.m_is_load   = 1'b1;
               trace_id.m_mem.wmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be);  //'1;
-              if (r_pipe_freeze_trace.data_misaligned) begin
-                trace_id.m_data_missaligned = 1'b1;
-                trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
-                trace_id.m_mem_req_id[0] = cnt_data_req;
-                trace_id.m_mem_req_id_valid[1] = 1'b1;
-              end
             end else begin
               trace_id.m_mem.rmask = be_to_mask(r_pipe_freeze_trace.lsu_data_be);  //'1;
             end
+
             if (trace_id.m_got_ex_reg) begin  // Shift index 0 to 1
               trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
               trace_id.m_mem_req_id[0] = 0;
@@ -1644,6 +1707,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           hwloop_to_id();
           trace_ex.move_down_pipe(trace_id);  // The instruction moves forward from ID to EX
           trace_id.m_valid = 1'b0;
+          s_dont_override_mstatus_fs_id = 1'b0;
           ->e_id_to_ex_1;
 
         end else if (r_pipe_freeze_trace.ex_reg_we && r_pipe_freeze_trace.rf_alu_we_ex) begin
@@ -1667,9 +1731,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       if (s_new_valid_insn) begin  // There is a new valid instruction
         if (trace_id.m_valid) begin
           if (trace_ex.m_valid) begin
-            if (!trace_ex.m_csr.got_minstret) begin
-              minstret_to_ex();
-            end
             if (trace_wb.m_valid) begin
               send_rvfi(trace_ex);
               ->e_send_rvfi_trace_ex_4;
@@ -1692,15 +1753,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_id.m_mem.addr = r_pipe_freeze_trace.data_addr_pmp;
             if (r_pipe_freeze_trace.data_misaligned) begin
               cnt_data_req = cnt_data_req + 1;
+              trace_id.m_mem_req_id[0] = cnt_data_req;
             end
             if (!r_pipe_freeze_trace.data_we_ex) begin
               trace_id.m_is_load = 1'b1;
-              if (r_pipe_freeze_trace.data_misaligned) begin
-                trace_id.m_data_missaligned = 1'b1;
-                trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
-                trace_id.m_mem_req_id[0] = cnt_data_req;
-                trace_id.m_mem_req_id_valid[1] = 1'b1;
-              end
             end
             if (trace_id.m_got_ex_reg) begin  // Shift index 0 to 1
               trace_id.m_mem_req_id[1] = trace_id.m_mem_req_id[0];
@@ -1708,7 +1764,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
               trace_id.m_mem_req_id_valid[0] = 1'b0;
               trace_id.m_mem_req_id_valid[1] = 1'b1;
             end
-          end else if (r_pipe_freeze_trace.rf_we_wb && !r_pipe_freeze_trace.ex_reg_we) begin
+          end else if (s_rf_we_wb_adjusted && !r_pipe_freeze_trace.ex_reg_we) begin
             trace_id.m_rd_addr[0]  = r_pipe_freeze_trace.rf_addr_wb;
             trace_id.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
           end
@@ -1716,6 +1772,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           hwloop_to_id();
           trace_ex.move_down_pipe(trace_id);
           trace_id.m_valid = 1'b0;
+          s_dont_override_mstatus_fs_id = 1'b0;
           ->e_id_to_ex_2;
         end
         if_to_id();
@@ -1733,12 +1790,27 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       end
 
       //IF_STAGE
-      if (r_pipe_freeze_trace.if_valid && r_pipe_freeze_trace.if_ready) begin
-        if(trace_if.m_valid && r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.id_ready && !trace_id.m_valid && r_pipe_freeze_trace.ebrk_insn_dec) begin
-          if_to_id();
-          trace_id.m_is_ebreak = '1;  //trace_if.m_is_ebreak;
-          ->e_if_2_id_2;
+      if(trace_if.m_valid) begin
+        if(r_pipe_freeze_trace.is_illegal && r_pipe_freeze_trace.is_decoding) begin
+          trace_if.m_is_illegal = 1'b1;
         end
+      end
+
+      if (r_pipe_freeze_trace.if_valid && r_pipe_freeze_trace.if_ready && r_pipe_freeze_trace.instr_valid_if) begin
+        if (trace_if.m_valid) begin
+          if (r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.id_ready && !trace_id.m_valid && r_pipe_freeze_trace.ebrk_insn_dec) begin
+            if_to_id();
+            trace_id.m_is_ebreak = '1;  //trace_if.m_is_ebreak;
+            ->e_if_2_id_2;
+          end else if (trace_if.m_is_illegal) begin
+            if_to_id();
+            ->e_if_2_id_3;
+          end else if (r_pipe_freeze_trace.ecall_insn_dec) begin
+            if_to_id();
+            ->e_if_2_id_4;
+          end
+        end
+
 
         trace_if.m_insn = r_pipe_freeze_trace.instr_if;  //Instr comes from if, buffer for one cycle
         trace_if.m_pc_rdata = r_pipe_freeze_trace.pc_if;
@@ -1754,6 +1826,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         mstatus_to_id();
         `CSR_FROM_PIPE(id, mepc)
         `CSR_FROM_PIPE(id, mcause)
+        ->e_csr_irq;
       end
 
       if (!s_id_done && r_pipe_freeze_trace.is_decoding) begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv
index 725ed4f0..ca703682 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv
@@ -279,8 +279,12 @@ module cv32e40p_tb_wrapper
       // .instr         (cv32e40p_top_i.core_i.id_stage_i.instr     ),
       .is_compressed_id_i(cv32e40p_top_i.core_i.id_stage_i.is_compressed_i),
       .ebrk_insn_dec_i   (cv32e40p_top_i.core_i.id_stage_i.ebrk_insn_dec),
-      .csr_cause_i       (cv32e40p_top_i.core_i.csr_cause),
-      .debug_csr_save_i  (cv32e40p_top_i.core_i.debug_csr_save),
+      .ecall_insn_dec_i  (cv32e40p_top_i.core_i.id_stage_i.ecall_insn_dec),
+      .mret_insn_dec_i   (cv32e40p_top_i.core_i.id_stage_i.mret_insn_dec),
+      .mret_dec_i        (cv32e40p_top_i.core_i.id_stage_i.mret_dec),
+
+      .csr_cause_i     (cv32e40p_top_i.core_i.csr_cause),
+      .debug_csr_save_i(cv32e40p_top_i.core_i.debug_csr_save),
 
       // HWLOOP regs
       .hwlp_start_q_i  (hwlp_start_q),
@@ -305,9 +309,11 @@ module cv32e40p_tb_wrapper
       // .rf_addr_alu_i  (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_waddr_fw_i),
       // .rf_wdata_alu_i (cv32e40p_top_i.core_i.id_stage_i.regfile_alu_wdata_fw_i),
 
+      .mult_ready_i        (cv32e40p_top_i.core_i.ex_stage_i.mult_ready),
+      .alu_ready_i         (cv32e40p_top_i.core_i.ex_stage_i.alu_ready),
       //// WB probes ////
-      .wb_valid_i(cv32e40p_top_i.core_i.wb_valid),
-
+      .wb_valid_i          (cv32e40p_top_i.core_i.wb_valid),
+      .wb_ready_i          (cv32e40p_top_i.core_i.lsu_ready_wb),
       //// LSU probes ////
       .data_we_ex_i        (cv32e40p_top_i.core_i.data_we_ex),
       .data_atop_ex_i      (cv32e40p_top_i.core_i.data_atop_ex),
@@ -360,6 +366,8 @@ module cv32e40p_tb_wrapper
       .csr_we_i       (cv32e40p_top_i.core_i.cs_registers_i.csr_we_int),
       .csr_wdata_int_i(cv32e40p_top_i.core_i.cs_registers_i.csr_wdata_int),
 
+      .csr_fregs_we_i(cv32e40p_top_i.core_i.cs_registers_i.fregs_we_i),
+
       .csr_mstatus_n_i   (cv32e40p_top_i.core_i.cs_registers_i.mstatus_n),
       .csr_mstatus_q_i   (cv32e40p_top_i.core_i.cs_registers_i.mstatus_q),
       .csr_mstatus_fs_n_i(cv32e40p_top_i.core_i.cs_registers_i.mstatus_fs_n),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv
index c099ff4f..d026c4aa 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv
@@ -196,8 +196,8 @@ package cv32e40p_tracer_pkg;
   parameter INSTR_CVEND0 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b0, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNTI0 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b0, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNT0 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b0, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUPI0 = {12'b?, 5'b00000, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUP0 = {12'b?, 5'b00000, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUPI0 = {17'b?, 3'b100, 4'b0110, 1'b0, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUP0 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b0, OPCODE_CUSTOM_1};
 
   parameter INSTR_CVSTARTI1 = {12'b?, 5'b00000, 3'b100, 4'b0000, 1'b1, OPCODE_CUSTOM_1};
   parameter INSTR_CVSTART1 = {12'b000000000000, 5'b?, 3'b100, 4'b0001, 1'b1, OPCODE_CUSTOM_1};
@@ -205,8 +205,8 @@ package cv32e40p_tracer_pkg;
   parameter INSTR_CVEND1 = {12'b000000000000, 5'b?, 3'b100, 4'b0011, 1'b1, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNTI1 = {12'b?, 5'b00000, 3'b100, 4'b0100, 1'b1, OPCODE_CUSTOM_1};
   parameter INSTR_CVCOUNT1 = {12'b000000000000, 5'b?, 3'b100, 4'b0101, 1'b1, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUPI1 = {12'b?, 5'b00000, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1};
-  parameter INSTR_CVSETUP1 = {12'b?, 5'b00000, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUPI1 = {17'b?, 3'b100, 4'b0110, 1'b1, OPCODE_CUSTOM_1};
+  parameter INSTR_CVSETUP1 = {12'b?, 5'b?, 3'b100, 4'b0111, 1'b1, OPCODE_CUSTOM_1};
 
 
   parameter INSTR_FF1 = {7'b0100001, 5'b0, 5'b?, 3'b011, 5'b?, OPCODE_CUSTOM_1};
@@ -449,8 +449,8 @@ package cv32e40p_tracer_pkg;
   parameter INSTR_CVSHUFFLE2H = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
   parameter INSTR_CVSHUFFLE2B = {5'b11100, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
 
-  parameter INSTR_CVPACK = {5'b11101, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
-  parameter INSTR_CVPACKH = {5'b11101, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
+  parameter INSTR_CVPACK = {5'b11110, 1'b0, 1'b0, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
+  parameter INSTR_CVPACKH = {5'b11110, 1'b0, 1'b1, 5'b?, 5'b?, 3'b000, 5'b?, OPCODE_CUSTOM_3};
 
   parameter INSTR_CVPACKHIB = {5'b11111, 1'b0, 1'b1, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
   parameter INSTR_CVPACKLOB = {5'b11111, 1'b0, 1'b0, 5'b?, 5'b?, 3'b001, 5'b?, OPCODE_CUSTOM_3};
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv
index 3db2a7ee..71cbaaff 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv
@@ -65,6 +65,9 @@
     bit m_move_down_pipe;
 
     int m_instret_cnt;
+    int m_instret_smaple_trigger; //We need to sample minstret from csr 2 cycle after id is doen
+
+    bit m_sample_csr_write_in_ex;
 
     struct {
       logic [31:0] addr ;
@@ -145,32 +148,34 @@
 
 
     function new();
-      this.m_order             = 0;
-      this.m_skip_order        = 1'b0;
-      this.m_valid             = 1'b0;
-      this.m_move_down_pipe    = 1'b0;
-      this.m_data_missaligned  = 1'b0;
-      this.m_got_first_data    = 1'b0;
-      this.m_got_ex_reg        = 1'b0;
-      this.m_intr              = '0;
-      this.m_dbg_taken         = 1'b0;
-      this.m_dbg_cause         = '0;
-      this.m_is_ebreak         = '0;
-      this.m_is_illegal        = '0;
-      this.m_is_irq            = '0;
-      this.m_is_memory         = 1'b0;
-      this.m_is_load           = 1'b0;
-      this.m_is_apu            = 1'b0;
-      this.m_is_apu_ok         = 1'b0;
-      this.m_apu_req_id        = 0;
-      this.m_mem_req_id[0]     = 0;
-      this.m_mem_req_id[1]     = 0;
-      this.m_mem_req_id_valid  = '0;
-      this.m_trap              = 1'b0;
-      this.m_fflags_we_non_apu = 1'b0;
-      this.m_frm_we_non_apu    = 1'b0;
-      this.m_fcsr_we_non_apu   = 1'b0;
-      this.m_instret_cnt       = 0;
+      this.m_order                  = 0;
+      this.m_skip_order             = 1'b0;
+      this.m_valid                  = 1'b0;
+      this.m_move_down_pipe         = 1'b0;
+      this.m_data_missaligned       = 1'b0;
+      this.m_got_first_data         = 1'b0;
+      this.m_got_ex_reg             = 1'b0;
+      this.m_intr                   = '0;
+      this.m_dbg_taken              = 1'b0;
+      this.m_dbg_cause              = '0;
+      this.m_is_ebreak              = '0;
+      this.m_is_illegal             = '0;
+      this.m_is_irq                 = '0;
+      this.m_is_memory              = 1'b0;
+      this.m_is_load                = 1'b0;
+      this.m_is_apu                 = 1'b0;
+      this.m_is_apu_ok              = 1'b0;
+      this.m_apu_req_id             = 0;
+      this.m_mem_req_id[0]          = 0;
+      this.m_mem_req_id[1]          = 0;
+      this.m_mem_req_id_valid       = '0;
+      this.m_trap                   = 1'b0;
+      this.m_fflags_we_non_apu      = 1'b0;
+      this.m_frm_we_non_apu         = 1'b0;
+      this.m_fcsr_we_non_apu        = 1'b0;
+      this.m_instret_cnt            = 0;
+      this.m_instret_smaple_trigger = 0;
+      this.m_sample_csr_write_in_ex = 1'b1;
     endfunction
 
     function void get_mnemonic();
@@ -875,37 +880,39 @@
       if(this.m_skip_order) begin
         this.m_order            = this.m_order + 64'h1;
       end
-      this.m_skip_order        = 1'b0;
-      this.m_pc_rdata          = r_pipe_freeze_trace.pc_id;
-      this.m_is_illegal        = 1'b0;
-      this.m_is_irq            = 1'b0;
-      this.m_is_memory         = 1'b0;
-      this.m_is_load           = 1'b0;
-      this.m_is_apu            = 1'b0;
-      this.m_is_apu_ok         = 1'b0;
-      this.m_apu_req_id        = 0;
-      this.m_mem_req_id[0]     = 0;
-      this.m_mem_req_id[1]     = 0;
-      this.m_mem_req_id_valid  = '0;
-      this.m_data_missaligned  = 1'b0;
-      this.m_got_first_data    = 1'b0;
-      this.m_got_ex_reg        = 1'b0;
-      this.m_got_regs_write    = 1'b0;
-      this.m_move_down_pipe    = 1'b0;
-      this.m_instret_cnt       = 0;
-      this.m_rd_addr[0]        = '0;
-      this.m_rd_addr[1]        = '0;
-      this.m_2_rd_insn         = 1'b0;
-      this.m_rs1_addr          = '0;
-      this.m_rs2_addr          = '0;
-      this.m_rs3_addr          = '0;
-      this.m_ex_fw             = '0;
-      this.m_csr.got_minstret  = '0;
-      this.m_dbg_taken         = '0;
-      this.m_trap              = 1'b0;
-      this.m_fflags_we_non_apu = 1'b0;
-      this.m_frm_we_non_apu    = 1'b0;
-      this.m_fcsr_we_non_apu   = 1'b0;
+      this.m_skip_order             = 1'b0;
+      this.m_pc_rdata               = r_pipe_freeze_trace.pc_id;
+      this.m_is_illegal             = 1'b0;
+      this.m_is_irq                 = 1'b0;
+      this.m_is_memory              = 1'b0;
+      this.m_is_load                = 1'b0;
+      this.m_is_apu                 = 1'b0;
+      this.m_is_apu_ok              = 1'b0;
+      this.m_apu_req_id             = 0;
+      this.m_mem_req_id[0]          = 0;
+      this.m_mem_req_id[1]          = 0;
+      this.m_mem_req_id_valid       = '0;
+      this.m_data_missaligned       = 1'b0;
+      this.m_got_first_data         = 1'b0;
+      this.m_got_ex_reg             = 1'b0;
+      this.m_got_regs_write         = 1'b0;
+      this.m_move_down_pipe         = 1'b0;
+      this.m_instret_cnt            = 0;
+      this.m_instret_smaple_trigger = 0;
+      this.m_sample_csr_write_in_ex = 1'b1;
+      this.m_rd_addr[0]             = '0;
+      this.m_rd_addr[1]             = '0;
+      this.m_2_rd_insn              = 1'b0;
+      this.m_rs1_addr               = '0;
+      this.m_rs2_addr               = '0;
+      this.m_rs3_addr               = '0;
+      this.m_ex_fw                  = '0;
+      this.m_csr.got_minstret       = '0;
+      this.m_dbg_taken              = '0;
+      this.m_trap                   = 1'b0;
+      this.m_fflags_we_non_apu      = 1'b0;
+      this.m_frm_we_non_apu         = 1'b0;
+      this.m_fcsr_we_non_apu        = 1'b0;
       this.m_csr.mcause_we = '0;
       if (is_compressed_id_i) begin
         this.m_insn[31:16] = '0;
@@ -944,47 +951,49 @@
     endfunction
 
     function void copy_full(insn_trace_t m_source);
-      this.m_valid              = m_source.m_valid;
-      this.m_stage              = m_source.m_stage;
-      this.m_order              = m_source.m_order;
-      this.m_pc_rdata           = m_source.m_pc_rdata;
-      this.m_insn               = m_source.m_insn;
-      this.m_mnemonic           = m_source.m_mnemonic;
-      this.m_is_memory          = m_source.m_is_memory;
-      this.m_is_load            = m_source.m_is_load;
-      this.m_is_apu             = m_source.m_is_apu;
-      this.m_is_apu_ok          = m_source.m_is_apu_ok;
-      this.m_apu_req_id         = m_source.m_apu_req_id;
-      this.m_mem_req_id         = m_source.m_mem_req_id;
-      this.m_mem_req_id_valid   = m_source.m_mem_req_id_valid;
-      this.m_data_missaligned   = m_source.m_data_missaligned;
-      this.m_got_first_data     = m_source.m_got_first_data;
-      this.m_got_ex_reg         = m_source.m_got_ex_reg;
-      this.m_dbg_taken          = m_source.m_dbg_taken;
-      this.m_dbg_cause          = m_source.m_dbg_cause;
-      this.m_is_ebreak          = m_source.m_is_ebreak;
-      this.m_is_illegal         = m_source.m_is_illegal;
-      this.m_is_irq             = m_source.m_is_irq;
-      this.m_instret_cnt        = m_source.m_instret_cnt;
-      this.m_rs1_addr           = m_source.m_rs1_addr;
-      this.m_rs2_addr           = m_source.m_rs2_addr;
-      this.m_rs3_addr           = m_source.m_rs3_addr;
-      this.m_rs1_rdata          = m_source.m_rs1_rdata;
-      this.m_rs2_rdata          = m_source.m_rs2_rdata;
-      this.m_rs3_rdata          = m_source.m_rs3_rdata;
-
-      this.m_ex_fw              = m_source.m_ex_fw;
-      this.m_rd_addr            = m_source.m_rd_addr;
-      this.m_2_rd_insn          = m_source.m_2_rd_insn;
-      this.m_rd_wdata           = m_source.m_rd_wdata;
-
-      this.m_intr               = m_source.m_intr;
-      this.m_trap               = m_source.m_trap;
-      this.m_fflags_we_non_apu  = m_source.m_fflags_we_non_apu;
-      this.m_frm_we_non_apu     = m_source.m_frm_we_non_apu   ;
-      this.m_fcsr_we_non_apu    = m_source.m_fcsr_we_non_apu;
-
-      this.m_mem                = m_source.m_mem;
+      this.m_valid                  = m_source.m_valid;
+      this.m_stage                  = m_source.m_stage;
+      this.m_order                  = m_source.m_order;
+      this.m_pc_rdata               = m_source.m_pc_rdata;
+      this.m_insn                   = m_source.m_insn;
+      this.m_mnemonic               = m_source.m_mnemonic;
+      this.m_is_memory              = m_source.m_is_memory;
+      this.m_is_load                = m_source.m_is_load;
+      this.m_is_apu                 = m_source.m_is_apu;
+      this.m_is_apu_ok              = m_source.m_is_apu_ok;
+      this.m_apu_req_id             = m_source.m_apu_req_id;
+      this.m_mem_req_id             = m_source.m_mem_req_id;
+      this.m_mem_req_id_valid       = m_source.m_mem_req_id_valid;
+      this.m_data_missaligned       = m_source.m_data_missaligned;
+      this.m_got_first_data         = m_source.m_got_first_data;
+      this.m_got_ex_reg             = m_source.m_got_ex_reg;
+      this.m_dbg_taken              = m_source.m_dbg_taken;
+      this.m_dbg_cause              = m_source.m_dbg_cause;
+      this.m_is_ebreak              = m_source.m_is_ebreak;
+      this.m_is_illegal             = m_source.m_is_illegal;
+      this.m_is_irq                 = m_source.m_is_irq;
+      this.m_instret_cnt            = m_source.m_instret_cnt;
+      this.m_instret_smaple_trigger = m_source.m_instret_smaple_trigger;
+      this.m_sample_csr_write_in_ex = m_source.m_sample_csr_write_in_ex;
+      this.m_rs1_addr               = m_source.m_rs1_addr;
+      this.m_rs2_addr               = m_source.m_rs2_addr;
+      this.m_rs3_addr               = m_source.m_rs3_addr;
+      this.m_rs1_rdata              = m_source.m_rs1_rdata;
+      this.m_rs2_rdata              = m_source.m_rs2_rdata;
+      this.m_rs3_rdata              = m_source.m_rs3_rdata;
+
+      this.m_ex_fw                  = m_source.m_ex_fw;
+      this.m_rd_addr                = m_source.m_rd_addr;
+      this.m_2_rd_insn              = m_source.m_2_rd_insn;
+      this.m_rd_wdata               = m_source.m_rd_wdata;
+
+      this.m_intr                   = m_source.m_intr;
+      this.m_trap                   = m_source.m_trap;
+      this.m_fflags_we_non_apu      = m_source.m_fflags_we_non_apu;
+      this.m_frm_we_non_apu         = m_source.m_frm_we_non_apu   ;
+      this.m_fcsr_we_non_apu        = m_source.m_fcsr_we_non_apu;
+
+      this.m_mem                    = m_source.m_mem;
       //CRS
       `ASSIGN_CSR(mstatus)
       `ASSIGN_CSR(mstatus_fs)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv
index 58051ab8..88d65d0b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv
@@ -64,6 +64,9 @@ typedef struct {
   logic is_compressed_id;
 
   logic ebrk_insn_dec;
+  logic ecall_insn_dec;
+  logic mret_insn_dec;
+  logic mret_dec;
 
   logic [5:0] csr_cause;
 
@@ -112,6 +115,9 @@ typedef struct {
   logic [31:0] data_wdata_ex;
   logic lsu_split_q_ex;
 
+  logic mult_ready;
+  logic alu_ready;
+
   //// WB probes ////
   logic [31:0] pc_wb;
   logic wb_ready;
@@ -198,6 +204,8 @@ typedef struct {
     logic mcause_we;
     logic dcsr_we;
 
+    logic fregs_we;
+
     logic jvt_we;
     Status_t mstatus_n;
     Status_t mstatus_q;
@@ -348,16 +356,24 @@ function compute_csr_we();
         r_pipe_freeze_trace.csr.mstatus_we    = 1'b1;
         r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
       end
-      CSR_MISA:     r_pipe_freeze_trace.csr.misa_we = 1'b1;
-      CSR_MTVEC:    r_pipe_freeze_trace.csr.mtvec_we = 1'b1;
-      CSR_MSCRATCH: r_pipe_freeze_trace.csr.mscratch_we = 1'b1;
-      CSR_MEPC:     r_pipe_freeze_trace.csr.mepc_we = 1'b1;
-      CSR_MCAUSE:   r_pipe_freeze_trace.csr.mcause_we = 1'b1;
-      CSR_DCSR:     r_pipe_freeze_trace.csr.dcsr_we = 1'b1;
-      CSR_FFLAGS:   r_pipe_freeze_trace.csr.fflags_we = 1'b1;
-      CSR_FRM:      r_pipe_freeze_trace.csr.frm_we = 1'b1;
-      CSR_FCSR:     r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
-      CSR_DPC:      r_pipe_freeze_trace.csr.dpc_we = 1'b1;
+      CSR_MISA:      r_pipe_freeze_trace.csr.misa_we = 1'b1;
+      CSR_MTVEC:     r_pipe_freeze_trace.csr.mtvec_we = 1'b1;
+      CSR_MSCRATCH:  r_pipe_freeze_trace.csr.mscratch_we = 1'b1;
+      CSR_MEPC:      r_pipe_freeze_trace.csr.mepc_we = 1'b1;
+      CSR_MCAUSE:    r_pipe_freeze_trace.csr.mcause_we = 1'b1;
+      CSR_DCSR:      r_pipe_freeze_trace.csr.dcsr_we = 1'b1;
+      CSR_FFLAGS: begin
+        r_pipe_freeze_trace.csr.fflags_we = 1'b1;
+        r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
+      end
+      CSR_FRM:       r_pipe_freeze_trace.csr.frm_we = 1'b1;
+      CSR_FCSR: begin
+        r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
+        r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
+      end
+      CSR_DPC:       r_pipe_freeze_trace.csr.dpc_we = 1'b1;
+      CSR_DSCRATCH0: r_pipe_freeze_trace.csr.dscratch0_we = 1'b1;
+      CSR_DSCRATCH1: r_pipe_freeze_trace.csr.dscratch1_we = 1'b1;
     endcase
   end
   // CSR_MCAUSE:   r_pipe_freeze_trace.csr.mcause_we = r_pipe_freeze_trace.csr.mcause_n != r_pipe_freeze_trace.csr.mcause_q; //for debug purpose
@@ -416,6 +432,9 @@ task monitor_pipeline();
     r_pipe_freeze_trace.jump_target_id = jump_target_id_i;
     r_pipe_freeze_trace.is_compressed_id = is_compressed_id_i;
     r_pipe_freeze_trace.ebrk_insn_dec = ebrk_insn_dec_i;
+    r_pipe_freeze_trace.ecall_insn_dec = ecall_insn_dec_i;
+    r_pipe_freeze_trace.mret_insn_dec = mret_insn_dec_i;
+    r_pipe_freeze_trace.mret_dec = mret_dec_i;
     r_pipe_freeze_trace.csr_cause = csr_cause_i;
     r_pipe_freeze_trace.debug_csr_save = debug_csr_save_i;
     r_pipe_freeze_trace.minstret = minstret_i;
@@ -462,6 +481,8 @@ task monitor_pipeline();
     r_pipe_freeze_trace.data_wdata_ex = data_wdata_ex_i;
     r_pipe_freeze_trace.lsu_split_q_ex = lsu_split_q_ex_i;
 
+    r_pipe_freeze_trace.mult_ready = mult_ready_i;
+    r_pipe_freeze_trace.alu_ready = alu_ready_i;
     //// WB probes ////
     r_pipe_freeze_trace.pc_wb = pc_wb_i;
     r_pipe_freeze_trace.wb_ready = wb_ready_i;
@@ -526,6 +547,8 @@ task monitor_pipeline();
     r_pipe_freeze_trace.csr.we = csr_we_i;
     r_pipe_freeze_trace.csr.wdata_int = csr_wdata_int_i;
 
+    r_pipe_freeze_trace.csr.fregs_we = csr_fregs_we_i;
+
     r_pipe_freeze_trace.csr.jvt_we = csr_jvt_we_i;
     r_pipe_freeze_trace.csr.mstatus_n = csr_mstatus_n_i;
     r_pipe_freeze_trace.csr.mstatus_q = csr_mstatus_q_i;
@@ -650,10 +673,6 @@ task monitor_pipeline();
     if (r_pipe_freeze_trace.csr.fcsr_we) begin
       r_pipe_freeze_trace.csr.fflags_we = 1'b1;
       r_pipe_freeze_trace.csr.frm_we    = 1'b1;
-    end else begin
-      if (r_pipe_freeze_trace.csr.fflags_we || r_pipe_freeze_trace.csr.frm_we) begin
-        r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
-      end
     end
 
     if (csr_fcsr_fflags_we_i) begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv
index 54980269..a41e345d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv
@@ -491,6 +491,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
             if ( (debug_req_pending || trigger_match_i) & ~debug_mode_q )
               begin
                 //Serving the debug
+                is_decoding_o     = COREV_PULP ? 1'b0 : 1'b1;
                 halt_if_o         = 1'b1;
                 halt_id_o         = 1'b1;
                 ctrl_fsm_ns       = DBG_FLUSH;
@@ -712,6 +713,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
             if ( (debug_req_pending || trigger_match_i) & ~debug_mode_q )
               begin
                 //Serving the debug
+                is_decoding_o     = COREV_PULP ? 1'b0 : 1'b1;
                 halt_if_o         = 1'b1;
                 halt_id_o         = 1'b1;
                 ctrl_fsm_ns       = DBG_FLUSH;
@@ -764,7 +766,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
 
                     ebrk_insn_i: begin
                       halt_if_o     = 1'b1;
-                      halt_id_o     = 1'b1;
+                      halt_id_o     = 1'b0;
 
                       if (debug_mode_q)
                         // we got back to the park loop in the debug rom
@@ -776,15 +778,15 @@ module cv32e40p_controller import cv32e40p_pkg::*;
 
                       else begin
                         // otherwise just a normal ebreak exception
-                        ctrl_fsm_ns = FLUSH_EX;
+                        ctrl_fsm_ns = id_ready_i ? FLUSH_EX : DECODE_HWLOOP;
                       end
 
                     end
 
                     ecall_insn_i: begin
                       halt_if_o     = 1'b1;
-                      halt_id_o     = 1'b1;
-                      ctrl_fsm_ns   = FLUSH_EX;
+                      halt_id_o     = 1'b0;
+                      ctrl_fsm_ns   = id_ready_i ? FLUSH_EX : DECODE_HWLOOP;
                     end
 
                     csr_status_i: begin
@@ -1559,7 +1561,7 @@ endgenerate
 
     // HWLoop 0 and 1 having target address constraints
     property p_hwlp_same_target_address;
-       @(posedge clk) (hwlp_counter_i[1] > 1 && hwlp_counter_i[0] > 1) |-> ( hwlp_end_addr_i[1] - 4 >= hwlp_end_addr_i[0] - 4 + 8 );
+       @(posedge clk) (hwlp_counter_i[1] > 1 && hwlp_counter_i[0] > 1 && pc_id_i >= hwlp_start_addr_i[0] && pc_id_i <= hwlp_end_addr_i[0] - 4) |-> ( hwlp_end_addr_i[1] - 4 >= hwlp_end_addr_i[0] - 4 + 8 );
     endproperty
 
     a_hwlp_same_target_address : assert property(p_hwlp_same_target_address) else $warning("%t, HWLoops target address do not respect constraints", $time);
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv
index e6f9f709..d72fae9e 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv
@@ -158,6 +158,7 @@ module cv32e40p_core
   logic [31:0] jump_target_id, jump_target_ex;
   logic               branch_in_ex;
   logic               branch_decision;
+  logic        [ 1:0] ctrl_transfer_insn_in_dec;
 
   logic               ctrl_busy;
   logic               if_busy;
@@ -201,6 +202,7 @@ module cv32e40p_core
   logic        [            C_RM-1:0]       frm_csr;
   logic        [         C_FFLAG-1:0]       fflags_csr;
   logic                                     fflags_we;
+  logic                                     fregs_we;
 
   // APU
   logic                                     apu_en_ex;
@@ -228,6 +230,7 @@ module cv32e40p_core
   logic                                     regfile_we_ex;
   logic        [                 5:0]       regfile_waddr_fw_wb_o;  // From WB to ID
   logic                                     regfile_we_wb;
+  logic                                     regfile_we_wb_power;
   logic        [                31:0]       regfile_wdata;
 
   logic        [                 5:0]       regfile_alu_waddr_ex;
@@ -235,6 +238,7 @@ module cv32e40p_core
 
   logic        [                 5:0]       regfile_alu_waddr_fw;
   logic                                     regfile_alu_we_fw;
+  logic                                     regfile_alu_we_fw_power;
   logic        [                31:0]       regfile_alu_wdata_fw;
 
   // CSR control
@@ -540,9 +544,10 @@ module cv32e40p_core
       .instr_req_o  (instr_req_int),
 
       // Jumps and branches
-      .branch_in_ex_o   (branch_in_ex),
-      .branch_decision_i(branch_decision),
-      .jump_target_o    (jump_target_id),
+      .branch_in_ex_o             (branch_in_ex),
+      .branch_decision_i          (branch_decision),
+      .jump_target_o              (jump_target_id),
+      .ctrl_transfer_insn_in_dec_o(ctrl_transfer_insn_in_dec),
 
       // IF and ID control signals
       .clear_instr_valid_o(clear_instr_valid),
@@ -699,13 +704,15 @@ module cv32e40p_core
       .wake_from_sleep_o(wake_from_sleep),
 
       // Forward Signals
-      .regfile_waddr_wb_i(regfile_waddr_fw_wb_o),  // Write address ex-wb pipeline
-      .regfile_we_wb_i   (regfile_we_wb),  // write enable for the register file
-      .regfile_wdata_wb_i(regfile_wdata),  // write data to commit in the register file
+      .regfile_waddr_wb_i   (regfile_waddr_fw_wb_o),  // Write address ex-wb pipeline
+      .regfile_we_wb_i      (regfile_we_wb),  // write enable for the register file
+      .regfile_we_wb_power_i(regfile_we_wb_power),
+      .regfile_wdata_wb_i   (regfile_wdata),  // write data to commit in the register file
 
-      .regfile_alu_waddr_fw_i(regfile_alu_waddr_fw),
-      .regfile_alu_we_fw_i   (regfile_alu_we_fw),
-      .regfile_alu_wdata_fw_i(regfile_alu_wdata_fw),
+      .regfile_alu_waddr_fw_i   (regfile_alu_waddr_fw),
+      .regfile_alu_we_fw_i      (regfile_alu_we_fw),
+      .regfile_alu_we_fw_power_i(regfile_alu_we_fw_power),
+      .regfile_alu_wdata_fw_i   (regfile_alu_wdata_fw),
 
       // from ALU
       .mult_multicycle_i(mult_multicycle),
@@ -737,6 +744,7 @@ module cv32e40p_core
   //                                                 //
   /////////////////////////////////////////////////////
   cv32e40p_ex_stage #(
+      .COREV_PULP      (COREV_PULP),
       .FPU             (FPU),
       .APU_NARGS_CPU   (APU_NARGS_CPU),
       .APU_WOP_CPU     (APU_WOP_CPU),
@@ -785,6 +793,8 @@ module cv32e40p_core
       .data_misaligned_ex_i(data_misaligned_ex),  // from ID/EX pipeline
       .data_misaligned_i   (data_misaligned),
 
+      .ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec),
+
       // FPU
       .fpu_fflags_we_o(fflags_we),
       .fpu_fflags_o   (fflags_csr),
@@ -838,18 +848,20 @@ module cv32e40p_core
       .regfile_we_i   (regfile_we_ex),
 
       // Output of ex stage pipeline
-      .regfile_waddr_wb_o(regfile_waddr_fw_wb_o),
-      .regfile_we_wb_o   (regfile_we_wb),
-      .regfile_wdata_wb_o(regfile_wdata),
+      .regfile_waddr_wb_o   (regfile_waddr_fw_wb_o),
+      .regfile_we_wb_o      (regfile_we_wb),
+      .regfile_we_wb_power_o(regfile_we_wb_power),
+      .regfile_wdata_wb_o   (regfile_wdata),
 
       // To IF: Jump and branch target and decision
       .jump_target_o    (jump_target_ex),
       .branch_decision_o(branch_decision),
 
       // To ID stage: Forwarding signals
-      .regfile_alu_waddr_fw_o(regfile_alu_waddr_fw),
-      .regfile_alu_we_fw_o   (regfile_alu_we_fw),
-      .regfile_alu_wdata_fw_o(regfile_alu_wdata_fw),
+      .regfile_alu_waddr_fw_o   (regfile_alu_waddr_fw),
+      .regfile_alu_we_fw_o      (regfile_alu_we_fw),
+      .regfile_alu_we_fw_power_o(regfile_alu_we_fw_power),
+      .regfile_alu_wdata_fw_o   (regfile_alu_wdata_fw),
 
       // stall control
       .is_decoding_i (is_decoding),
@@ -969,6 +981,7 @@ module cv32e40p_core
       .frm_o      (frm_csr),
       .fflags_i   (fflags_csr),
       .fflags_we_i(fflags_we),
+      .fregs_we_i (fregs_we),
 
       // Interrupt related control signals
       .mie_bypass_o  (mie_bypass),
@@ -1037,13 +1050,16 @@ module cv32e40p_core
   );
 
   //  CSR access
-  assign csr_addr     = csr_addr_int;
-  assign csr_wdata    = alu_operand_a_ex;
-  assign csr_op       = csr_op_ex;
+  assign csr_addr = csr_addr_int;
+  assign csr_wdata = alu_operand_a_ex;
+  assign csr_op = csr_op_ex;
 
   assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0);
 
-
+  //  Floating-Point registers write
+  assign fregs_we     = (FPU == 1 & ZFINX == 0) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
+                                                   (regfile_we_wb     && regfile_waddr_fw_wb_o[5]))
+                                                : 1'b0;
 
   ///////////////////////////
   //   ____  __  __ ____   //
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_cs_registers.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_cs_registers.sv
index 25c777e2..920305c8 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_cs_registers.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_cs_registers.sv
@@ -68,6 +68,7 @@ module cv32e40p_cs_registers
     output logic [        2:0] frm_o,
     input  logic [C_FFLAG-1:0] fflags_i,
     input  logic               fflags_we_i,
+    input  logic               fregs_we_i,
 
     // Interrupts
     output logic [31:0] mie_bypass_o,
@@ -212,6 +213,7 @@ module cv32e40p_cs_registers
 
   logic [31:0] exception_pc;
   Status_t mstatus_q, mstatus_n;
+  logic mstatus_we_int;
   FS_t mstatus_fs_q, mstatus_fs_n;
   logic [5:0] mcause_q, mcause_n;
   logic [5:0] ucause_q, ucause_n;
@@ -507,7 +509,7 @@ module cv32e40p_cs_registers
 
         // mimpid, Machine Implementation ID
         CSR_MIMPID: begin
-          csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER) ? 32'h1 : 'b0;
+          csr_rdata_int = (FPU == 1 || COREV_PULP == 1 || COREV_CLUSTER == 1) ? 32'h1 : 'b0;
         end
 
         // unimplemented, read 0 CSRs
@@ -897,6 +899,7 @@ module cv32e40p_cs_registers
       dscratch0_n = dscratch0_q;
       dscratch1_n = dscratch1_q;
 
+      mstatus_we_int = 1'b0;
       mstatus_n = mstatus_q;
       mcause_n = mcause_q;
       ucause_n = '0;  // Not used if PULP_SECURE == 0
@@ -957,7 +960,8 @@ module cv32e40p_cs_registers
               mprv: csr_wdata_int[MSTATUS_MPRV_BIT]
           };
           if (FPU == 1 && ZFINX == 0) begin
-            mstatus_fs_n = FS_t'(csr_wdata_int[MSTATUS_FS_BIT_HIGH:MSTATUS_FS_BIT_LOW]);
+            mstatus_we_int = 1'b1;
+            mstatus_fs_n   = FS_t'(csr_wdata_int[MSTATUS_FS_BIT_HIGH:MSTATUS_FS_BIT_LOW]);
           end
         end
         // mie: machine interrupt enable
@@ -1027,7 +1031,7 @@ module cv32e40p_cs_registers
 
         if (ZFINX == 0) begin
           // FPU Register File/Flags implicit update or modified by CSR instructions
-          if (fflags_we_i || fcsr_update) begin
+          if ((fregs_we_i && !(mstatus_we_int && mstatus_fs_n != FS_DIRTY)) || fflags_we_i || fcsr_update) begin
             mstatus_fs_n = FS_DIRTY;
           end
         end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_ex_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_ex_stage.sv
index c51ef7f8..488a83dc 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_ex_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_ex_stage.sv
@@ -33,6 +33,7 @@ module cv32e40p_ex_stage
   import cv32e40p_pkg::*;
   import cv32e40p_apu_core_pkg::*;
 #(
+    parameter COREV_PULP       = 0,
     parameter FPU              = 0,
     parameter APU_NARGS_CPU    = 3,
     parameter APU_WOP_CPU      = 6,
@@ -81,6 +82,8 @@ module cv32e40p_ex_stage
     input logic data_misaligned_ex_i,
     input logic data_misaligned_i,
 
+    input logic [1:0] ctrl_transfer_insn_in_dec_i,
+
     // FPU signals
     output logic fpu_fflags_we_o,
     output logic [APU_NUSFLAGS_CPU-1:0] fpu_fflags_o,
@@ -138,11 +141,13 @@ module cv32e40p_ex_stage
     // Output of EX stage pipeline
     output logic [ 5:0] regfile_waddr_wb_o,
     output logic        regfile_we_wb_o,
+    output logic        regfile_we_wb_power_o,
     output logic [31:0] regfile_wdata_wb_o,
 
     // Forwarding ports : to ID stage
     output logic [ 5:0] regfile_alu_waddr_fw_o,
     output logic        regfile_alu_we_fw_o,
+    output logic        regfile_alu_we_fw_power_o,
     output logic [31:0] regfile_alu_wdata_fw_o,  // forward to RF and ID/EX pipe, ALU & MUL
 
     // To IF: Jump and branch target and decision
@@ -190,22 +195,27 @@ module cv32e40p_ex_stage
 
   // ALU write port mux
   always_comb begin
-    regfile_alu_wdata_fw_o = '0;
-    regfile_alu_waddr_fw_o = '0;
-    regfile_alu_we_fw_o    = '0;
-    wb_contention          = 1'b0;
+    regfile_alu_wdata_fw_o    = '0;
+    regfile_alu_waddr_fw_o    = '0;
+    regfile_alu_we_fw_o       = 1'b0;
+    regfile_alu_we_fw_power_o = 1'b0;
+    wb_contention             = 1'b0;
 
-    // APU single cycle operations, and multicycle operations (>2cycles) are written back on ALU port
+    // APU single cycle operations, and multicycle operations (> 2cycles) are written back on ALU port
     if (apu_valid & (apu_singlecycle | apu_multicycle)) begin
-      regfile_alu_we_fw_o    = 1'b1;
-      regfile_alu_waddr_fw_o = apu_waddr;
-      regfile_alu_wdata_fw_o = apu_result;
+      regfile_alu_we_fw_o       = 1'b1;
+      regfile_alu_we_fw_power_o = 1'b1;
+      regfile_alu_waddr_fw_o    = apu_waddr;
+      regfile_alu_wdata_fw_o    = apu_result;
 
       if (regfile_alu_we_i & ~apu_en_i) begin
         wb_contention = 1'b1;
       end
     end else begin
-      regfile_alu_we_fw_o    = regfile_alu_we_i & ~apu_en_i;  // private fpu incomplete?
+      regfile_alu_we_fw_o = regfile_alu_we_i & ~apu_en_i;
+      regfile_alu_we_fw_power_o = (COREV_PULP == 0) ? regfile_alu_we_i & ~apu_en_i : 
+                                                     regfile_alu_we_i & ~apu_en_i &
+                                                     mult_ready & alu_ready & lsu_ready_ex_i;
       regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
       if (alu_en_i) regfile_alu_wdata_fw_o = alu_result;
       if (mult_en_i) regfile_alu_wdata_fw_o = mult_result;
@@ -215,21 +225,24 @@ module cv32e40p_ex_stage
 
   // LSU write port mux
   always_comb begin
-    regfile_we_wb_o    = 1'b0;
-    regfile_waddr_wb_o = regfile_waddr_lsu;
-    regfile_wdata_wb_o = lsu_rdata_i;
-    wb_contention_lsu  = 1'b0;
+    regfile_we_wb_o       = 1'b0;
+    regfile_we_wb_power_o = 1'b0;
+    regfile_waddr_wb_o    = regfile_waddr_lsu;
+    regfile_wdata_wb_o    = lsu_rdata_i;
+    wb_contention_lsu     = 1'b0;
 
     if (regfile_we_lsu) begin
-      regfile_we_wb_o = 1'b1;
+      regfile_we_wb_o       = 1'b1;
+      regfile_we_wb_power_o = (COREV_PULP == 0) ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
       if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin
         wb_contention_lsu = 1'b1;
       end
       // APU two-cycle operations are written back on LSU port
     end else if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin
-      regfile_we_wb_o    = 1'b1;
-      regfile_waddr_wb_o = apu_waddr;
-      regfile_wdata_wb_o = apu_result;
+      regfile_we_wb_o       = 1'b1;
+      regfile_we_wb_power_o = 1'b1;
+      regfile_waddr_wb_o    = apu_waddr;
+      regfile_wdata_wb_o    = apu_result;
     end
   end
 
@@ -371,11 +384,20 @@ module cv32e40p_ex_stage
           apu_result_q <= 'b0;
           apu_flags_q  <= 'b0;
         end else begin
-          if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || (data_req_i && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
+          if (apu_rvalid_i && apu_multicycle &&
+              (data_misaligned_i || data_misaligned_ex_i ||
+               ((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
+               (mulh_active && (mult_operator_i == MUL_H)) ||
+               ((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
+                regfile_alu_we_i && ~apu_read_dep_for_jalr_o))) begin
             apu_rvalid_q <= 1'b1;
             apu_result_q <= apu_result_i;
             apu_flags_q  <= apu_flags_i;
-          end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
+          end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i ||
+                                         ((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
+                                         (mulh_active && (mult_operator_i == MUL_H)) ||
+                                         ((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
+                                          regfile_alu_we_i && ~apu_read_dep_for_jalr_o))) begin
             apu_rvalid_q <= 1'b0;
           end
         end
@@ -383,7 +405,12 @@ module cv32e40p_ex_stage
 
       assign apu_req_o = apu_req;
       assign apu_gnt = apu_gnt_i;
-      assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
+      assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i ||
+                                             ((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
+                                             (mulh_active && (mult_operator_i == MUL_H)) ||
+                                             ((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
+                                              regfile_alu_we_i && ~apu_read_dep_for_jalr_o)))
+                         ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
       assign apu_operands_o = apu_operands_i;
       assign apu_op_o = apu_op_i;
       assign apu_result = apu_rvalid_q ? apu_result_q : apu_result_i;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv
index 042fa0f2..62ec46c2 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv
@@ -111,7 +111,7 @@ module cv32e40p_fp_wrapper
       .int_fmt_i     (fpnew_pkg::int_format_e'(fpu_int_fmt)),
       .vectorial_op_i(fpu_vec_op),
       .tag_i         (1'b0),
-      .simd_mask_i   ('b0),
+      .simd_mask_i   (1'b0),
       .in_valid_i    (apu_req_i),
       .in_ready_o    (apu_gnt_o),
       .flush_i       (1'b0),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv
index 7811eabf..93bb1380 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv
@@ -70,6 +70,7 @@ module cv32e40p_id_stage
     output logic        branch_in_ex_o,
     input  logic        branch_decision_i,
     output logic [31:0] jump_target_o,
+    output logic [ 1:0] ctrl_transfer_insn_in_dec_o,
 
     // IF and ID stage signals
     output logic       clear_instr_valid_o,
@@ -225,10 +226,12 @@ module cv32e40p_id_stage
     // Forward Signals
     input logic [5:0] regfile_waddr_wb_i,
     input logic regfile_we_wb_i,
+    input logic regfile_we_wb_power_i,
     input  logic [31:0] regfile_wdata_wb_i, // From wb_stage: selects data from data memory, ex_stage result and sp rdata
 
     input logic [ 5:0] regfile_alu_waddr_fw_i,
     input logic        regfile_alu_we_fw_i,
+    input logic        regfile_alu_we_fw_power_i,
     input logic [31:0] regfile_alu_wdata_fw_i,
 
     // from ALU
@@ -809,6 +812,9 @@ module cv32e40p_id_stage
             if (ctrl_transfer_target_mux_sel == JT_JALR) begin
               apu_read_regs[0]       = regfile_addr_ra_id;
               apu_read_regs_valid[0] = 1'b1;
+            end else begin
+              apu_read_regs[0]       = regfile_addr_ra_id;
+              apu_read_regs_valid[0] = 1'b0;
             end
           end  // OP_A_CURRPC:
           OP_A_REGA_OR_FWD: begin
@@ -948,12 +954,12 @@ module cv32e40p_id_stage
       // Write port a
       .waddr_a_i(regfile_waddr_wb_i),
       .wdata_a_i(regfile_wdata_wb_i),
-      .we_a_i   (regfile_we_wb_i),
+      .we_a_i   (regfile_we_wb_power_i),
 
       // Write port b
       .waddr_b_i(regfile_alu_waddr_fw_i),
       .wdata_b_i(regfile_alu_wdata_fw_i),
-      .we_b_i   (regfile_alu_we_fw_i)
+      .we_b_i   (regfile_alu_we_fw_power_i)
   );
 
 
@@ -1087,7 +1093,7 @@ module cv32e40p_id_stage
       .debug_wfi_no_sleep_i(debug_wfi_no_sleep),
 
       // jump/branches
-      .ctrl_transfer_insn_in_dec_o   (ctrl_transfer_insn_in_dec),
+      .ctrl_transfer_insn_in_dec_o   (ctrl_transfer_insn_in_dec_o),
       .ctrl_transfer_insn_in_id_o    (ctrl_transfer_insn_in_id),
       .ctrl_transfer_target_mux_sel_o(ctrl_transfer_target_mux_sel),
 
@@ -1187,7 +1193,7 @@ module cv32e40p_id_stage
       // jump/branch control
       .branch_taken_ex_i          (branch_taken_ex),
       .ctrl_transfer_insn_in_id_i (ctrl_transfer_insn_in_id),
-      .ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec),
+      .ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec_o),
 
       // Interrupt signals
       .irq_wu_ctrl_i     (irq_wu_ctrl),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40x.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40x.core
index 70a248de..7a12b181 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40x.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40x.core
@@ -67,3 +67,4 @@ targets:
     filesets:
       - files_rtl
       - target_sim? (files_clk_gate)
+      - target_sim_sc? (files_clk_gate)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson
index d1cc1ce7..a9251111 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson
@@ -8,7 +8,7 @@
 {
   upstream:
   {
-    url: https://github.com/davideschiavone/cve2.git
-    rev: 5039e60cdea6a76282576ca7e93a35ee9a3ff2e9
+    url: https://github.com/openhwgroup/cve2.git
+    rev: f5b21e71c9b511477b04ef81d1292858c51ac20c
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson
index 8c860069..d398c1eb 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson
@@ -6,22 +6,43 @@
   target_dir: "openhwgroup_cv32e20",
 
   upstream: {
-    url: "https://github.com/davideschiavone/cve2.git",
-    rev: "5039e60cdea6a76282576ca7e93a35ee9a3ff2e9",
+    url: "https://github.com/openhwgroup/cve2.git",
+    rev: "f5b21e71c9b511477b04ef81d1292858c51ac20c",
   },
 
+  patch_dir: "patches/openhwgroup_cv32e20",
+
   exclude_from_upstream: [
     "ci",
     "dv",
     "examples",
     "formal",
     ".dir-locals.el",
-    "cv32e40p_manifest.flist",
     "doc",
     "shared",
     "syn",
     "util",
-    "vendor",
+    "scripts",
+    "vendor/eembc_coremark",
+    "vendor/eembc_coremark.lock.hjson",
+    "vendor/google_riscv-dv",
+    "vendor/google_riscv-dv.lock.hjson",
+    "vendor/google_riscv-dv.vendor.hjson",
+    "vendor/lowrisc_ip.lock.hjson",
+    "vendor/lowrisc_ip.vendor.hjson",
+    "vendor/patches",
+    "vendor/lowrisc_ip/ip"
+    "vendor/lowrisc_ip/lint"
+    "vendor/lowrisc_ip/util"
+    "vendor/lowrisc_ip/dv/tools",
+    "vendor/lowrisc_ip/dv/verilator",
+    "vendor/lowrisc_ip/dv/sv/common_ifs",
+    "vendor/lowrisc_ip/dv/sv/csr_utils",
+    "vendor/lowrisc_ip/dv/sv/dv_base_reg",
+    "vendor/lowrisc_ip/dv/sv/dv_lib",
+    "vendor/lowrisc_ip/dv/sv/mem_bkdr_util",
+    "vendor/lowrisc_ip/dv/sv/mem_model",
+    "vendor/lowrisc_ip/dv/sv/str_utils",
     ".github",
     "azure-pipelines.yml",
     "check_tool_requirements.core",
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/esl_epfl_cv32e40px/0001-vendor-cv32e40px-Re-vendor.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/esl_epfl_cv32e40px/0001-vendor-cv32e40px-Re-vendor.patch
deleted file mode 100644
index 28ab47b1..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/esl_epfl_cv32e40px/0001-vendor-cv32e40px-Re-vendor.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-diff --git a/rtl/cv32e40px_cs_registers.sv b/rtl/cv32e40px_cs_registers.sv
-index 1f1d56b..cdc6433 100644
---- a/rtl/cv32e40px_cs_registers.sv
-+++ b/rtl/cv32e40px_cs_registers.sv
-@@ -1450,7 +1450,7 @@ module cv32e40px_cs_registers
-       // minstret is located at index 2
-       // Programable HPM counters start at index 3
-       if ((cnt_gidx == 1) || (cnt_gidx >= (NUM_MHPMCOUNTERS + 3))) begin : gen_non_implemented
--        assign mhpmcounter_q[cnt_gidx] = 'b0;
-+        always_ff @(posedge clk) mhpmcounter_q[cnt_gidx] <= 'b0;
-       end else begin : gen_implemented
-         always_ff @(posedge clk, negedge rst_n)
-           if (!rst_n) begin
-@@ -1478,10 +1478,10 @@ module cv32e40px_cs_registers
-     for (evt_gidx = 0; evt_gidx < 32; evt_gidx++) begin : gen_mhpmevent
-       // programable HPM events start at index3
-       if ((evt_gidx < 3) || (evt_gidx >= (NUM_MHPMCOUNTERS + 3))) begin : gen_non_implemented
--        assign mhpmevent_q[evt_gidx] = 'b0;
-+        always_ff @(posedge clk) mhpmevent_q[evt_gidx] <= 'b0;
-       end else begin : gen_implemented
-         if (NUM_HPM_EVENTS < 32) begin : gen_tie_off
--          assign mhpmevent_q[evt_gidx][31:NUM_HPM_EVENTS] = 'b0;
-+          always_ff @(posedge clk) mhpmevent_q[evt_gidx][31:NUM_HPM_EVENTS] <= 'b0;
-         end
-         always_ff @(posedge clk, negedge rst_n)
-           if (!rst_n) mhpmevent_q[evt_gidx][NUM_HPM_EVENTS-1:0] <= 'b0;
-@@ -1499,7 +1499,7 @@ module cv32e40px_cs_registers
-           (en_gidx == 1) ||
-           (en_gidx >= (NUM_MHPMCOUNTERS+3) ) )
-         begin : gen_non_implemented
--        assign mcounteren_q[en_gidx] = 'b0;
-+        always_ff @(posedge clk) mcounteren_q[en_gidx] <= 'b0;
-       end else begin : gen_implemented
-         always_ff @(posedge clk, negedge rst_n)
-           if (!rst_n) mcounteren_q[en_gidx] <= 'b0;  // default disable
-@@ -1514,7 +1514,7 @@ module cv32e40px_cs_registers
-   generate
-     for (inh_gidx = 0; inh_gidx < 32; inh_gidx++) begin : gen_mcountinhibit
-       if ((inh_gidx == 1) || (inh_gidx >= (NUM_MHPMCOUNTERS + 3))) begin : gen_non_implemented
--        assign mcountinhibit_q[inh_gidx] = 'b0;
-+        always_ff @(posedge clk) mcountinhibit_q[inh_gidx] <= 'b0;
-       end else begin : gen_implemented
-         always_ff @(posedge clk, negedge rst_n)
-           if (!rst_n) mcountinhibit_q[inh_gidx] <= 'b1;  // default disable
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/lowrisc_opentitan/uartdpi.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/lowrisc_opentitan/uartdpi.patch
index 94b7d2b8..54c13229 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/lowrisc_opentitan/uartdpi.patch
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/lowrisc_opentitan/uartdpi.patch
@@ -1,5 +1,5 @@
 diff --git a/hw/dv/dpi/uartdpi/uartdpi.h b/hw/dv/dpi/uartdpi/uartdpi.h
-index 29d50a5a2..2149fb115 100644
+index 29d50a5a28..2149fb1155 100644
 --- a/hw/dv/dpi/uartdpi/uartdpi.h
 +++ b/hw/dv/dpi/uartdpi/uartdpi.h
 @@ -5,7 +5,9 @@
@@ -21,21 +21,23 @@ index 29d50a5a2..2149fb115 100644
 +#endif
  #endif  // OPENTITAN_HW_DV_DPI_UARTDPI_UARTDPI_H_
 diff --git a/hw/dv/dpi/uartdpi/uartdpi.sv b/hw/dv/dpi/uartdpi/uartdpi.sv
-index 97fae4767..07c75cf8e 100644
+index 97fae47674..2be4df54ff 100644
 --- a/hw/dv/dpi/uartdpi/uartdpi.sv
 +++ b/hw/dv/dpi/uartdpi/uartdpi.sv
-@@ -82,11 +82,14 @@ module uartdpi #(
+@@ -82,11 +82,16 @@ module uartdpi #(
      end
    end
  
 -
 +`ifndef VCS
 +`ifndef MODELSIM
++`ifndef XCELIUM
    initial begin
      // Prevent falling edges of rx_i before reset causing spurious characters
      seen_reset = 0;
    end
 +`endif
++`endif
 +`endif
  
    // RX
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_assert.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_assert.patch
new file mode 100644
index 00000000..4ac84c15
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_assert.patch
@@ -0,0 +1,12 @@
+diff --git a/rtl/cve2_top.sv b/rtl/cve2_top.sv
+index 34af60b7..00c38a4a 100644
+--- a/rtl/cve2_top.sv
++++ b/rtl/cve2_top.sv
+@@ -265,7 +265,6 @@ module cve2_top import cve2_pkg::*; #(
+ 
+   `ASSERT_KNOWN(IbexDataGntX, data_gnt_i)
+   `ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i)
+-  `ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_err_i}, data_rvalid_i)
+ 
+   `ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i})
+ 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_core.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_core.patch
new file mode 100644
index 00000000..9727dec1
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/openhwgroup_cv32e20/cv32e20_core.patch
@@ -0,0 +1,12 @@
+diff --git a/cve2_top.core b/cve2_top.core
+index cb4e23b4..0d9d2c5c 100644
+--- a/cve2_top.core
++++ b/cve2_top.core
+@@ -75,6 +75,7 @@ targets:
+       - tool_veriblelint ? (files_lint_verible)
+       - files_rtl
+       - target_sim ? (files_clk_gate)
++      - target_sim_sc ? (files_clk_gate)
+     toplevel: cve2_top
+     parameters:
+       - tool_vivado ? (FPGA_XILINX=true)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_common_cells/clk_mux_glitch_free.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_common_cells/clk_mux_glitch_free.patch
new file mode 100644
index 00000000..3e5ccb84
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_common_cells/clk_mux_glitch_free.patch
@@ -0,0 +1,13 @@
+diff --git a/src/clk_mux_glitch_free.sv b/src/clk_mux_glitch_free.sv
+index e0eb5cd..5193742 100644
+--- a/src/clk_mux_glitch_free.sv
++++ b/src/clk_mux_glitch_free.sv
+@@ -191,7 +191,7 @@ endmodule
+ 
+ // Helper Module to generate an N-input clock OR-gate from a tree of tc_clk_or2 cells.
+ module clk_or_tree #(
+-  parameter int unsigned NUM_INPUTS
++  parameter int unsigned NUM_INPUTS = 1
+ ) (
+   input logic [NUM_INPUTS-1:0] clks_i,
+   output logic clk_o
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/0002-spiflash_valueargs.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/0002-spiflash_valueargs.patch
deleted file mode 100644
index 5b525705..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/0002-spiflash_valueargs.patch
+++ /dev/null
@@ -1,20 +0,0 @@
-diff --git a/picosoc/spiflash.v b/picosoc/spiflash.v
-index 22b337b..e0eef9f 100644
---- a/picosoc/spiflash.v
-+++ b/picosoc/spiflash.v
-@@ -102,8 +102,14 @@ module spiflash (
- 	reg [7:0] memory [0:16*1024*1024-1];
- 
- 	reg [1023:0] firmware_file;
-+	reg result;
-+	integer i;
-+
- 	initial begin
--		if (!$value$plusargs("firmware=%s", firmware_file))
-+		for (i=0;i<=16*1024*1024;i=i+1)
-+			memory[i] = '0;
-+		result = $value$plusargs("firmware=%s", firmware_file);
-+		if (!result)
- 			firmware_file = "firmware.hex";
- 		$readmemh(firmware_file, memory);
- 	end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/spiflash.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/spiflash.patch
new file mode 100644
index 00000000..3583151d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/spiflash.patch
@@ -0,0 +1,113 @@
+diff --git a/picosoc/spiflash.v b/picosoc/spiflash.v
+index 22b337b..55342b5 100644
+--- a/picosoc/spiflash.v
++++ b/picosoc/spiflash.v
+@@ -26,7 +26,7 @@
+ // updates output signals 1ns after the SPI clock edge.
+ //
+ // Supported commands:
+-//    AB, B9, FF, 03, BB, EB, ED
++//    AB, B9, FF, 03, BB, EB, ED, 06, 02, 32
+ //
+ // Well written SPI flash data sheets:
+ //    Cypress S25FL064L http://www.cypress.com/file/316661/download
+@@ -61,6 +61,8 @@ module spiflash (
+ 	reg spi_io_vld;
+ 
+ 	reg powered_up = 0;
++	reg write_enable = 0;
++	reg write_enable_reset = 0;
+ 
+ 	localparam [3:0] mode_spi         = 1;
+ 	localparam [3:0] mode_dspi_rd     = 2;
+@@ -102,8 +104,14 @@ module spiflash (
+ 	reg [7:0] memory [0:16*1024*1024-1];
+ 
+ 	reg [1023:0] firmware_file;
++	reg result;
++	integer i;
++
+ 	initial begin
+-		if (!$value$plusargs("firmware=%s", firmware_file))
++		for (i=0;i<=16*1024*1024;i=i+1)
++			memory[i] = 8'h00;
++		result = $value$plusargs("firmware=%s", firmware_file);
++		if (!result)
+ 			firmware_file = "firmware.hex";
+ 		$readmemh(firmware_file, memory);
+ 	end
+@@ -123,6 +131,9 @@ module spiflash (
+ 
+ 				if (spi_cmd == 8'h ff)
+ 					xip_cmd = 0;
++
++				if (spi_cmd == 8'h 06)
++					write_enable = 1;
+ 			end
+ 
+ 			if (powered_up && spi_cmd == 'h 03) begin
+@@ -141,6 +152,25 @@ module spiflash (
+ 				end
+ 			end
+ 
++			if (powered_up && write_enable && spi_cmd == 'h 02) begin
++				if (bytecount == 1)
++					write_enable_reset = 1;
++
++				if (bytecount == 2)
++					spi_addr[23:16] = buffer;
++
++				if (bytecount == 3)
++					spi_addr[15:8] = buffer;
++
++				if (bytecount == 4)
++					spi_addr[7:0] = buffer;
++
++				if (bytecount >= 5 && bytecount <= 260) begin
++					memory[spi_addr] = buffer;
++					spi_addr = spi_addr + 1;
++				end
++			end
++
+ 			if (powered_up && spi_cmd == 'h bb) begin
+ 				if (bytecount == 1)
+ 					mode = mode_dspi_rd;
+@@ -191,6 +221,27 @@ module spiflash (
+ 				end
+ 			end
+ 
++			if (powered_up && write_enable && spi_cmd == 'h 32) begin
++				if (bytecount == 1)
++					write_enable_reset = 1;
++
++				if (bytecount == 2)
++					spi_addr[23:16] = buffer;
++
++				if (bytecount == 3)
++					spi_addr[15:8] = buffer;
++
++				if (bytecount == 4) begin
++					spi_addr[7:0] = buffer;
++					mode = mode_qspi_rd;
++				end
++
++				if (bytecount >= 5 && bytecount <= 260) begin
++					memory[spi_addr] = buffer;
++					spi_addr = spi_addr + 1;
++				end
++			end
++
+ 			if (powered_up && spi_cmd == 'h ed) begin
+ 				if (bytecount == 1)
+ 					next_mode = mode_qspi_ddr_rd;
+@@ -268,6 +319,10 @@ module spiflash (
+ 				$display("");
+ 				$fflush;
+ 			end
++			if (write_enable_reset) begin
++				write_enable = 0;
++				write_enable_reset = 0;
++			end
+ 			buffer = 0;
+ 			bitcount = 0;
+ 			bytecount = 0;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/0001-async.-lowactive-reset.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/spimemio.patch
similarity index 100%
rename from hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/0001-async.-lowactive-reset.patch
rename to hw/vendor/esl_epfl_x_heep/hw/vendor/patches/yosyshq_picorv32/spimemio.patch
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_common_cells/src/clk_mux_glitch_free.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_common_cells/src/clk_mux_glitch_free.sv
index e0eb5cdc..51937424 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_common_cells/src/clk_mux_glitch_free.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_common_cells/src/clk_mux_glitch_free.sv
@@ -191,7 +191,7 @@ endmodule
 
 // Helper Module to generate an N-input clock OR-gate from a tree of tc_clk_or2 cells.
 module clk_or_tree #(
-  parameter int unsigned NUM_INPUTS
+  parameter int unsigned NUM_INPUTS = 1
 ) (
   input logic [NUM_INPUTS-1:0] clks_i,
   output logic clk_o
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.lock.hjson
index bc1ec555..de40549d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/pulp-platform/fpnew.git
-    rev: d6e581628f3517a1fb1257507d3214e599f7859d
+    rev: 79e453139072df42c9ec8f697132ba485d74e23d
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.vendor.hjson
index 7ae0d55c..1fe09cca 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_fpnew.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/pulp-platform/fpnew.git",
-    rev: "d6e581628f3517a1fb1257507d3214e599f7859d",
+    rev: "79e453139072df42c9ec8f697132ba485d74e23d",
   },
 
   exclude_from_upstream: [
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_gpio.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_gpio.core
index 630f318a..2d79c611 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_gpio.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_gpio.core
@@ -39,8 +39,10 @@ targets:
     - rtl
     - "gpio-test? (testbench)"
     - target_sim? (clock-gate)
+    - target_sim_sc? (clock-gate)
     - target_asic_synthesis? (clock-gate)
     - target_asic_yosys_synthesis? (clock-gate)
     - target_nexys-a7-100t? (no-clock-gate)
     - target_pynq-z2? (no-clock-gate)
     - target_pynq-z2-arm-emulation? (no-clock-gate)
+    - target_zcu104? (no-clock-gate)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.lock.hjson
index 3f13125e..f74356a1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/pulp-platform/riscv-dbg.git
-    rev: 69be5ddc03ea1688c0eab47d6ed9d0e8725beda1
+    rev: 358f90110220adf7a083f8b65d157e836d706236
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson
index 2ec8e7e9..1c13cb43 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/pulp-platform/riscv-dbg.git",
-    rev: "69be5ddc03ea1688c0eab47d6ed9d0e8725beda1",
+    rev: "358f90110220adf7a083f8b65d157e836d706236",
   },
 
   exclude_from_upstream: [
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/CHANGELOG.md b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/CHANGELOG.md
index 35db8983..99dab605 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/CHANGELOG.md
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/CHANGELOG.md
@@ -4,7 +4,40 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
-## [Unreleased]
+## Unreleased
+
+## [0.8.1] - 2023-10-01
+### Changed
+- debug_rom: Add rst
+
+## [0.8.0] - 2023-04-05
+### Fixed
+- dm_csrs: Fix W1C behavior of `sberror` (#155) [@andreaskurth](https://github.com/andreaskurth)
+- gen_rom.py: Port to python3 (#152) [@andreaskurth](https://github.com/andreaskurth)
+
+### Added
+- `xprop_off` to Xprop-incompatible processes (#151) [@andreaskurth](https://github.com/andreaskurth)
+
+## [0.7.0] - 2022-11-02
+### Fixed
+- 64-bit unaligned accesses (#145) [@creinwar](https://github.com/creinwar)
+- Various minor testbench fixes (#146)
+
+### Changed
+- Halted, Resume and Exception addresses are now aligned to 8 bytes
+
+## [0.6.0] - 2022-10-11
+### Fixed
+- Testbench build (#141, #142)
+- remote_bitbang tb build for newer GCC versions (#133) [@epsilon537](https://github.com/noytzach)
+- 32-bit access to abstract data (#27) [@Silabs-ArjanB](https://github.com/Silabs-ArjanB)
+- `dm_mem`: Clear state of hart upon ndmreset (#140) [@andreaskurth](https://github.com/andreaskurth)
+- `dmi_jtag_tap`: Bring all state to initial value in test-logic-reset (#139) [@andreaskurth](https://github.com/andreaskurth)
+- Fix DMI response when command or SBA are busy (#138) [@andreaskurth](https://github.com/andreaskurth)
+
+### Changed
+- Add expontential backoff to read_dmi in tb (#134) [@colluca](https://github.com/colluca)
+
 ## [0.5.1] - 2022-04-12
 ### Fixed
 - Fixed dmi_bscane_tap top-level signals
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/Makefile b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/Makefile
index b23370aa..931e2532 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/Makefile
@@ -5,7 +5,7 @@ debug_rom = debug_rom.sv debug_rom_one_scratch.sv
 GCC?=riscv64-unknown-elf-gcc
 OBJCOPY?=riscv64-unknown-elf-objcopy
 OBJDUMP?=riscv64-unknown-elf-objdump
-PYTHON?=python
+PYTHON?=python3
 
 all: $(debug_rom)
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.S b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.S
index 2989c7e8..7126ae46 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.S
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.S
@@ -6,9 +6,9 @@
 // # define SND_SCRATCH 1
 // These are implementation-specific addresses in the Debug Module
 #define HALTED    0x100
-#define GOING     0x104
-#define RESUMING  0x108
-#define EXCEPTION 0x10C
+#define GOING     0x108
+#define RESUMING  0x110
+#define EXCEPTION 0x118
 
 // Region of memory where each hart has 1
 // byte to read.
@@ -26,10 +26,13 @@
 
 entry:
        jal zero, _entry
+       nop
 resume:
        jal zero, _resume
+       nop
 exception:
        jal zero, _exception
+       nop
 
 
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.h b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.h
index b4f2d35a..9e1d73d2 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.h
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.h
@@ -1,11 +1,14 @@
 // Auto-generated code
 
-const int reset_vec_size = 38;
+const int reset_vec_size = 40;
 
 uint32_t reset_vec[reset_vec_size] = {
-    0x00c0006f,
-    0x07c0006f,
-    0x04c0006f,
+    0x0180006f,
+    0x00000013,
+    0x0840006f,
+    0x00000013,
+    0x0500006f,
+    0x00000013,
     0x0ff0000f,
     0x7b241073,
     0x7b351073,
@@ -22,23 +25,22 @@ uint32_t reset_vec[reset_vec_size] = {
     0x00a40433,
     0x40044403,
     0x00247413,
-    0xfa041ce3,
+    0xfa0418e3,
     0xfd5ff06f,
     0x00000517,
     0x00c55513,
     0x00c51513,
-    0x10052623,
+    0x10052c23,
     0x7b302573,
     0x7b202473,
     0x00100073,
-    0x10052223,
+    0x10052423,
     0x7b302573,
     0x7b202473,
-    0xa85ff06f,
+    0xa79ff06f,
     0xf1402473,
-    0x10852423,
+    0x10852823,
     0x7b302573,
     0x7b202473,
-    0x7b200073,
-    0x00000000
+    0x7b200073
 };
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.sv
index 0299db6b..ac10eeea 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom.sv
@@ -16,41 +16,47 @@
 // Auto-generated code
 module debug_rom (
   input  logic         clk_i,
+  input  logic         rst_ni,
   input  logic         req_i,
   input  logic [63:0]  addr_i,
   output logic [63:0]  rdata_o
 );
 
-  localparam int unsigned RomSize = 19;
+  localparam int unsigned RomSize = 20;
 
   logic [RomSize-1:0][63:0] mem;
   assign mem = {
-    64'h00000000_7b200073,
+    64'h7b200073_7b202473,
+    64'h7b302573_10852823,
+    64'hf1402473_a79ff06f,
     64'h7b202473_7b302573,
-    64'h10852423_f1402473,
-    64'ha85ff06f_7b202473,
-    64'h7b302573_10052223,
-    64'h00100073_7b202473,
-    64'h7b302573_10052623,
-    64'h00c51513_00c55513,
-    64'h00000517_fd5ff06f,
-    64'hfa041ce3_00247413,
-    64'h40044403_00a40433,
-    64'hf1402473_02041c63,
-    64'h00147413_40044403,
-    64'h00a40433_10852023,
-    64'hf1402473_00c51513,
+    64'h10052423_00100073,
+    64'h7b202473_7b302573,
+    64'h10052c23_00c51513,
     64'h00c55513_00000517,
-    64'h7b351073_7b241073,
-    64'h0ff0000f_04c0006f,
-    64'h07c0006f_00c0006f
+    64'hfd5ff06f_fa0418e3,
+    64'h00247413_40044403,
+    64'h00a40433_f1402473,
+    64'h02041c63_00147413,
+    64'h40044403_00a40433,
+    64'h10852023_f1402473,
+    64'h00c51513_00c55513,
+    64'h00000517_7b351073,
+    64'h7b241073_0ff0000f,
+    64'h00000013_0500006f,
+    64'h00000013_0840006f,
+    64'h00000013_0180006f
   };
 
-  logic [$clog2(RomSize)-1:0] addr_q;
+  logic [$clog2(RomSize)-1:0] addr_d, addr_q;
+
+  assign addr_d = req_i ? addr_i[$clog2(RomSize)-1+3:3] : addr_q;
 
-  always_ff @(posedge clk_i) begin
-    if (req_i) begin
-      addr_q <= addr_i[$clog2(RomSize)-1+3:3];
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      addr_q <= '0;
+    end else begin
+      addr_q <= addr_d;
     end
   end
 
@@ -59,7 +65,7 @@ module debug_rom (
   always_comb begin : p_outmux
     rdata_o = '0;
     if (addr_q < $clog2(RomSize)'(RomSize)) begin
-        rdata_o = mem[addr_q];
+      rdata_o = mem[addr_q];
     end
   end
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.h b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.h
index 625d66a0..d4539714 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.h
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.h
@@ -1,11 +1,14 @@
 // Auto-generated code
 
-const int reset_vec_size = 26;
+const int reset_vec_size = 28;
 
 uint32_t reset_vec[reset_vec_size] = {
-    0x00c0006f,
-    0x0500006f,
-    0x0340006f,
+    0x0180006f,
+    0x00000013,
+    0x0580006f,
+    0x00000013,
+    0x0380006f,
+    0x00000013,
     0x0ff0000f,
     0x7b241073,
     0xf1402473,
@@ -16,17 +19,16 @@ uint32_t reset_vec[reset_vec_size] = {
     0xf1402473,
     0x40044403,
     0x00247413,
-    0xfc0418e3,
+    0xfc0414e3,
     0xfddff06f,
-    0x10002623,
+    0x10002c23,
     0x7b202473,
     0x00100073,
-    0x10002223,
+    0x10002423,
     0x7b202473,
-    0xab1ff06f,
+    0xaa5ff06f,
     0xf1402473,
-    0x10802423,
+    0x10802823,
     0x7b202473,
-    0x7b200073,
-    0x00000000
+    0x7b200073
 };
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.sv
index af7e67c7..3cd2d9e2 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/debug_rom_one_scratch.sv
@@ -16,35 +16,41 @@
 // Auto-generated code
 module debug_rom_one_scratch (
   input  logic         clk_i,
+  input  logic         rst_ni,
   input  logic         req_i,
   input  logic [63:0]  addr_i,
   output logic [63:0]  rdata_o
 );
 
-  localparam int unsigned RomSize = 13;
+  localparam int unsigned RomSize = 14;
 
   logic [RomSize-1:0][63:0] mem;
   assign mem = {
-    64'h00000000_7b200073,
-    64'h7b202473_10802423,
-    64'hf1402473_ab1ff06f,
-    64'h7b202473_10002223,
-    64'h00100073_7b202473,
-    64'h10002623_fddff06f,
-    64'hfc0418e3_00247413,
-    64'h40044403_f1402473,
-    64'h02041263_00147413,
-    64'h40044403_10802023,
-    64'hf1402473_7b241073,
-    64'h0ff0000f_0340006f,
-    64'h0500006f_00c0006f
+    64'h7b200073_7b202473,
+    64'h10802823_f1402473,
+    64'haa5ff06f_7b202473,
+    64'h10002423_00100073,
+    64'h7b202473_10002c23,
+    64'hfddff06f_fc0414e3,
+    64'h00247413_40044403,
+    64'hf1402473_02041263,
+    64'h00147413_40044403,
+    64'h10802023_f1402473,
+    64'h7b241073_0ff0000f,
+    64'h00000013_0380006f,
+    64'h00000013_0580006f,
+    64'h00000013_0180006f
   };
 
-  logic [$clog2(RomSize)-1:0] addr_q;
+  logic [$clog2(RomSize)-1:0] addr_d, addr_q;
 
-  always_ff @(posedge clk_i) begin
-    if (req_i) begin
-      addr_q <= addr_i[$clog2(RomSize)-1+3:3];
+  assign addr_d = req_i ? addr_i[$clog2(RomSize)-1+3:3] : addr_q;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      addr_q <= '0;
+    end else begin
+      addr_q <= addr_d;
     end
   end
 
@@ -53,7 +59,7 @@ module debug_rom_one_scratch (
   always_comb begin : p_outmux
     rdata_o = '0;
     if (addr_q < $clog2(RomSize)'(RomSize)) begin
-        rdata_o = mem[addr_q];
+      rdata_o = mem[addr_q];
     end
   end
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/gen_rom.py b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/gen_rom.py
index b8cb60bc..a34efc5d 100755
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/gen_rom.py
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/debug_rom/gen_rom.py
@@ -43,6 +43,7 @@
 module = """\
 module $filename (
   input  logic         clk_i,
+  input  logic         rst_ni,
   input  logic         req_i,
   input  logic [63:0]  addr_i,
   output logic [63:0]  rdata_o
@@ -55,11 +56,15 @@
 $content
   };
 
-  logic [$$clog2(RomSize)-1:0] addr_q;
+  logic [$$clog2(RomSize)-1:0] addr_d, addr_q;
 
-  always_ff @(posedge clk_i) begin
-    if (req_i) begin
-      addr_q <= addr_i[$$clog2(RomSize)-1+3:3];
+  assign addr_d = req_i ? addr_i[$$clog2(RomSize)-1+3:3] : addr_q;
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      addr_q <= '0;
+    end else begin
+      addr_q <= addr_d;
     end
   end
 
@@ -68,7 +73,7 @@
   always_comb begin : p_outmux
     rdata_o = '0;
     if (addr_q < $$clog2(RomSize)'(RomSize)) begin
-        rdata_o = mem[addr_q];
+      rdata_o = mem[addr_q];
     end
   end
 
@@ -88,9 +93,8 @@
 def read_bin():
 
     with open(filename + ".img", 'rb') as f:
-        rom = binascii.hexlify(f.read())
-        rom = map(''.join, zip(rom[::2], rom[1::2]))
-
+        rom = bytes.hex(f.read())
+        rom = list(map(''.join, zip(rom[::2], rom[1::2])))
 
     # align to 64 bit
     align = (int((len(rom) + 7) / 8 )) * 8;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/doc/debug-system.md b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/doc/debug-system.md
index 1beca7df..5fbfbe18 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/doc/debug-system.md
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/doc/debug-system.md
@@ -439,9 +439,9 @@ Address         | Description
 --------------- | ------------------------------------------------------------------------------------------------------------------------------------------
 0x0 to 0x0ff    | _unused_
 0x100           | Halted. Write to this address to acknowledge that the core is halted.
-0x104           | Going. Write to this address to acknowledge that the core is executing.
-0x108           | Resuming. Write to this address to acknowledge that the core is resuming non-debug operation.
-0x10c           | Exception. An exception was triggered while the core was in debug mode.
+0x108           | Going. Write to this address to acknowledge that the core is executing.
+0x110           | Resuming. Write to this address to acknowledge that the core is resuming non-debug operation.
+0x118           | Exception. An exception was triggered while the core was in debug mode.
 0x300           | WhereTo
 0x338 to 0x35f  | AbstractCmd
 0x360 to 0x37f  | Program Buffer (8 words)
@@ -449,8 +449,8 @@ Address         | Description
 0x400 to 0x7ff  | Flags
 0x800 to 0x1000 | Debug ROM
 0x800           | HaltAddress. Entry point into the Debug Module. The core must jump to this address when it was requested to halt.
-0x804           | ResumeAddress. Entry point into the Debug Module. Jumping to this address instructs the debug module to bring the core out of debug mode and back into normal operation mode.
-0x808           | ExceptionAddress. Entry point into the Debug Module. The core must jump to this address when it receives an exception while being in debug mode.
+0x808           | ResumeAddress. Entry point into the Debug Module. Jumping to this address instructs the debug module to bring the core out of debug mode and back into normal operation mode.
+0x810           | ExceptionAddress. Entry point into the Debug Module. The core must jump to this address when it receives an exception while being in debug mode.
 
 (Note: The debug memory addressing scheme is adopted from the Rocket Chip Generator.)
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv
index 350c6c5f..59d1c90a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv
@@ -90,7 +90,6 @@ module dm_csrs #(
   logic        resp_queue_empty;
   logic        resp_queue_push;
   logic        resp_queue_pop;
-  logic [31:0] resp_queue_data;
 
   localparam dm::dm_csr_e DataEnd = dm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1);
   localparam dm::dm_csr_e ProgBufEnd = dm::dm_csr_e'(dm::ProgBuf0 + {4'h0, dm::ProgBufSize} - 8'h1);
@@ -179,8 +178,8 @@ module dm_csrs #(
 
   logic [HartSelLen-1:0] selected_hart;
 
-  // a successful response returns zero
-  assign dmi_resp_o.resp = dm::DTM_SUCCESS;
+  dm::dmi_resp_t resp_queue_inp;
+
   assign dmi_resp_valid_o     = ~resp_queue_empty;
   assign dmi_req_ready_o      = ~resp_queue_full;
   assign resp_queue_push      = dmi_req_valid_i & dmi_req_ready_o;
@@ -223,7 +222,7 @@ module dm_csrs #(
   // types instead.
   assign autoexecdata_idx = 4'({dm_csr_addr} - {dm::Data0});
 
-  always_comb begin : csr_read_write
+  always_comb (*xprop_off *) begin : csr_read_write
     // --------------------
     // Static Values (R/O)
     // --------------------
@@ -279,7 +278,8 @@ module dm_csrs #(
     sbaddr_d            = 64'(sbaddress_i);
     sbdata_d            = sbdata_q;
 
-    resp_queue_data         = 32'h0;
+    resp_queue_inp.data     = 32'h0;
+    resp_queue_inp.resp     = dm::DTM_SUCCESS;
     cmd_valid_d             = 1'b0;
     sbaddress_write_valid_o = 1'b0;
     sbdata_read_valid_o     = 1'b0;
@@ -294,62 +294,70 @@ module dm_csrs #(
     if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) begin
       unique case (dm_csr_addr) inside
         [(dm::Data0):DataEnd]: begin
-          resp_queue_data = data_q[$clog2(dm::DataCount)'(autoexecdata_idx)];
+          resp_queue_inp.data = data_q[$clog2(dm::DataCount)'(autoexecdata_idx)];
           if (!cmdbusy_i) begin
             // check whether we need to re-execute the command (just give a cmd_valid)
             cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
           // An abstract command was executing while one of the data registers was read
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
-        dm::DMControl:    resp_queue_data = dmcontrol_q;
-        dm::DMStatus:     resp_queue_data = dmstatus;
-        dm::Hartinfo:     resp_queue_data = hartinfo_aligned[selected_hart];
-        dm::AbstractCS:   resp_queue_data = abstractcs;
-        dm::AbstractAuto: resp_queue_data = abstractauto_q;
+        dm::DMControl:    resp_queue_inp.data = dmcontrol_q;
+        dm::DMStatus:     resp_queue_inp.data = dmstatus;
+        dm::Hartinfo:     resp_queue_inp.data = hartinfo_aligned[selected_hart];
+        dm::AbstractCS:   resp_queue_inp.data = abstractcs;
+        dm::AbstractAuto: resp_queue_inp.data = abstractauto_q;
         // command is read-only
-        dm::Command:    resp_queue_data = '0;
+        dm::Command:    resp_queue_inp.data = '0;
         [(dm::ProgBuf0):ProgBufEnd]: begin
-          resp_queue_data = progbuf_q[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]];
+          resp_queue_inp.data = progbuf_q[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]];
           if (!cmdbusy_i) begin
             // check whether we need to re-execute the command (just give a cmd_valid)
             // range of autoexecprogbuf is 31:16
             cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
 
           // An abstract command was executing while one of the progbuf registers was read
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
-        dm::HaltSum0: resp_queue_data = haltsum0;
-        dm::HaltSum1: resp_queue_data = haltsum1;
-        dm::HaltSum2: resp_queue_data = haltsum2;
-        dm::HaltSum3: resp_queue_data = haltsum3;
+        dm::HaltSum0: resp_queue_inp.data = haltsum0;
+        dm::HaltSum1: resp_queue_inp.data = haltsum1;
+        dm::HaltSum2: resp_queue_inp.data = haltsum2;
+        dm::HaltSum3: resp_queue_inp.data = haltsum3;
         dm::SBCS: begin
-          resp_queue_data = sbcs_q;
+          resp_queue_inp.data = sbcs_q;
         end
         dm::SBAddress0: begin
-          resp_queue_data = sbaddr_q[31:0];
+          resp_queue_inp.data = sbaddr_q[31:0];
         end
         dm::SBAddress1: begin
-          resp_queue_data = sbaddr_q[63:32];
+          resp_queue_inp.data = sbaddr_q[63:32];
         end
         dm::SBData0: begin
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbdata_read_valid_o = (sbcs_q.sberror == '0);
-            resp_queue_data = sbdata_q[31:0];
+            resp_queue_inp.data = sbdata_q[31:0];
           end
         end
         dm::SBData1: begin
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
-            resp_queue_data = sbdata_q[63:32];
+            resp_queue_inp.data = sbdata_q[63:32];
           end
         end
         default:;
@@ -367,8 +375,11 @@ module dm_csrs #(
               // check whether we need to re-execute the command (just give a cmd_valid)
               cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
             //An abstract command was executing while one of the data registers was written
-            end else if (cmderr_q == dm::CmdErrNone) begin
-              cmderr_d = dm::CmdErrBusy;
+            end else begin
+              resp_queue_inp.resp = dm::DTM_BUSY;
+              if (cmderr_q == dm::CmdErrNone) begin
+                cmderr_d = dm::CmdErrBusy;
+              end
             end
           end
         end
@@ -391,8 +402,11 @@ module dm_csrs #(
           // reads during abstract command execution are not allowed
           if (!cmdbusy_i) begin
             cmderr_d = dm::cmderr_e'(~a_abstractcs.cmderr & cmderr_q);
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         dm::Command: begin
@@ -402,8 +416,11 @@ module dm_csrs #(
             command_d = dm::command_t'(dmi_req_i.data);
           // if there was an attempted to write during a busy execution
           // and the cmderror field is zero set the busy error
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         dm::AbstractAuto: begin
@@ -412,8 +429,11 @@ module dm_csrs #(
             abstractauto_d                 = 32'h0;
             abstractauto_d.autoexecdata    = 12'(dmi_req_i.data[dm::DataCount-1:0]);
             abstractauto_d.autoexecprogbuf = 16'(dmi_req_i.data[dm::ProgBufSize-1+16:16]);
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         [(dm::ProgBuf0):ProgBufEnd]: begin
@@ -426,26 +446,31 @@ module dm_csrs #(
             // range of autoexecprogbuf is 31:16
             cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
           //An abstract command was executing while one of the progbuf registers was written
-          end else if (cmderr_q == dm::CmdErrNone) begin
-            cmderr_d = dm::CmdErrBusy;
+          end else begin
+            resp_queue_inp.resp = dm::DTM_BUSY;
+            if (cmderr_q == dm::CmdErrNone) begin
+              cmderr_d = dm::CmdErrBusy;
+            end
           end
         end
         dm::SBCS: begin
           // access while the SBA was busy
           if (sbbusy_i) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbcs = dm::sbcs_t'(dmi_req_i.data);
             sbcs_d = sbcs;
             // R/W1C
             sbcs_d.sbbusyerror = sbcs_q.sbbusyerror & (~sbcs.sbbusyerror);
-            sbcs_d.sberror     = sbcs_q.sberror     & {3{~(sbcs.sberror == 3'd1)}};
+            sbcs_d.sberror     = (|sbcs.sberror) ? 3'b0 : sbcs_q.sberror;
           end
         end
         dm::SBAddress0: begin
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbaddr_d[31:0] = dmi_req_i.data;
             sbaddress_write_valid_o = (sbcs_q.sberror == '0);
@@ -455,6 +480,7 @@ module dm_csrs #(
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
             sbcs_d.sbbusyerror = 1'b1;
+            resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbaddr_d[63:32] = dmi_req_i.data;
           end
@@ -463,6 +489,7 @@ module dm_csrs #(
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
            sbcs_d.sbbusyerror = 1'b1;
+           resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbdata_d[31:0] = dmi_req_i.data;
             sbdata_write_valid_o = (sbcs_q.sberror == '0);
@@ -472,6 +499,7 @@ module dm_csrs #(
           // access while the SBA was busy
           if (sbbusy_i || sbcs_q.sbbusyerror) begin
            sbcs_d.sbbusyerror = 1'b1;
+           resp_queue_inp.resp = dm::DTM_BUSY;
           end else begin
             sbdata_d[63:32] = dmi_req_i.data;
           end
@@ -557,8 +585,8 @@ module dm_csrs #(
 
   // response FIFO
   fifo_v2 #(
-    .dtype            ( logic [31:0]         ),
-    .DEPTH            ( 2                    )
+    .dtype            ( logic [$bits(dmi_resp_o)-1:0] ),
+    .DEPTH            ( 2                             )
   ) i_fifo (
     .clk_i,
     .rst_ni,
@@ -569,9 +597,9 @@ module dm_csrs #(
     .empty_o          ( resp_queue_empty     ),
     .alm_full_o       (                      ),
     .alm_empty_o      (                      ),
-    .data_i           ( resp_queue_data      ),
+    .data_i           ( resp_queue_inp       ),
     .push_i           ( resp_queue_push      ),
-    .data_o           ( dmi_resp_o.data      ),
+    .data_o           ( dmi_resp_o           ),
     .pop_i            ( resp_queue_pop       )
   );
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv
index 178259f6..9ff3c86a 100755
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv
@@ -26,6 +26,7 @@ module dm_mem #(
   input  logic                             rst_ni,      // debug module reset
 
   output logic [NrHarts-1:0]               debug_req_o,
+  input  logic                             ndmreset_i,
   input  logic [19:0]                      hartsel_i,
   // from Ctrl and Status register
   input  logic [NrHarts-1:0]               haltreq_i,
@@ -77,9 +78,9 @@ module dm_mem #(
   localparam logic [DbgAddressBits-1:0] FlagsEndAddr  = 'h7FF;
 
   localparam logic [DbgAddressBits-1:0] HaltedAddr    = 'h100;
-  localparam logic [DbgAddressBits-1:0] GoingAddr     = 'h104;
-  localparam logic [DbgAddressBits-1:0] ResumingAddr  = 'h108;
-  localparam logic [DbgAddressBits-1:0] ExceptionAddr = 'h10C;
+  localparam logic [DbgAddressBits-1:0] GoingAddr     = 'h108;
+  localparam logic [DbgAddressBits-1:0] ResumingAddr  = 'h110;
+  localparam logic [DbgAddressBits-1:0] ExceptionAddr = 'h118;
 
   logic [dm::ProgBufSize/2-1:0][63:0]   progbuf;
   logic [7:0][63:0]   abstract_cmd;
@@ -201,6 +202,13 @@ module dm_mem #(
       cmderror_valid_o = 1'b1;
       cmderror_o = dm::CmdErrorException;
     end
+
+    if (ndmreset_i) begin
+      // Clear state of hart and its control signals when it is being reset.
+      state_d = Idle;
+      go      = 1'b0;
+      resume  = 1'b0;
+    end
   end
 
   // word mux for 32bit and 64bit buses
@@ -214,14 +222,13 @@ module dm_mem #(
   end
 
   // read/write logic
-  logic [63:0] data_bits;
+  logic [dm::DataCount-1:0][31:0] data_bits;
   logic [7:0][7:0] rdata;
-  always_comb begin : p_rw_logic
+  always_comb (* xprop_off *) begin : p_rw_logic
 
     halted_d_aligned   = NrHartsAligned'(halted_q);
     resuming_d_aligned = NrHartsAligned'(resuming_q);
     rdata_d        = rdata_q;
-    // convert the data in bits representation
     data_bits      = data_i;
     rdata          = '0;
 
@@ -258,9 +265,19 @@ module dm_mem #(
           // core can write data registers
           [DataBaseAddr:DataEndAddr]: begin
             data_valid_o = 1'b1;
-            for (int i = 0; i < $bits(be_i); i++) begin
-              if (be_i[i]) begin
-                data_bits[i*8+:8] = wdata_i[i*8+:8];
+            for (int dc = 0; dc < dm::DataCount; dc++) begin
+              if ((addr_i[DbgAddressBits-1:2] - DataBaseAddr[DbgAddressBits-1:2]) == dc) begin
+                for (int i = 0; i < $bits(be_i); i++) begin
+                  if (be_i[i]) begin
+                    if (i>3) begin // for upper 32bit data write (only used for BusWidth ==  64)
+                      if ((dc+1) < dm::DataCount) begin // ensure we write to an implemented data register
+                        data_bits[dc+1][(i-4)*8+:8] = wdata_i[i*8+:8];
+                      end
+                    end else begin // for lower 32bit data write
+                      data_bits[dc][i*8+:8] = wdata_i[i*8+:8];
+                    end
+                  end
+                end
               end
             end
           end
@@ -293,10 +310,8 @@ module dm_mem #(
 
           [DataBaseAddr:DataEndAddr]: begin
             rdata_d = {
-                      data_i[$clog2(dm::ProgBufSize)'(addr_i[DbgAddressBits-1:3] -
-                          DataBaseAddr[DbgAddressBits-1:3] + 1'b1)],
-                      data_i[$clog2(dm::ProgBufSize)'(addr_i[DbgAddressBits-1:3] -
-                          DataBaseAddr[DbgAddressBits-1:3])]
+                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1) + 1'b1)],
+                      data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
                       };
           end
 
@@ -325,6 +340,12 @@ module dm_mem #(
       end
     end
 
+    if (ndmreset_i) begin
+      // When harts are reset, they are neither halted nor resuming.
+      halted_d_aligned   = '0;
+      resuming_d_aligned = '0;
+    end
+
     data_o = data_bits;
   end
 
@@ -476,6 +497,7 @@ module dm_mem #(
   if (HasSndScratch) begin : gen_rom_snd_scratch
     debug_rom i_debug_rom (
       .clk_i,
+      .rst_ni,
       .req_i,
       .addr_i  ( rom_addr  ),
       .rdata_o ( rom_rdata )
@@ -486,6 +508,7 @@ module dm_mem #(
     // be saved.
     debug_rom_one_scratch i_debug_rom (
       .clk_i,
+      .rst_ni,
       .req_i,
       .addr_i  ( rom_addr  ),
       .rdata_o ( rom_rdata )
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_pkg.sv
index 1c2b6195..cc2e1ebc 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_pkg.sv
@@ -26,8 +26,8 @@ package dm;
 
   // address to which a hart should jump when it was requested to halt
   localparam logic [63:0] HaltAddress = 64'h800;
-  localparam logic [63:0] ResumeAddress = HaltAddress + 4;
-  localparam logic [63:0] ExceptionAddress = HaltAddress + 8;
+  localparam logic [63:0] ResumeAddress = HaltAddress + 8;
+  localparam logic [63:0] ExceptionAddress = HaltAddress + 16;
 
   // address where data0-15 is shadowed or if shadowed in a CSR
   // address of the first CSR used for shadowing the data
@@ -197,6 +197,12 @@ package dm;
     DTM_WRITE = 2'h2
   } dtm_op_e;
 
+  typedef enum logic [1:0] {
+    DTM_SUCCESS = 2'h0,
+    DTM_ERR     = 2'h2,
+    DTM_BUSY    = 2'h3
+  } dtm_op_status_e;
+
   typedef struct packed {
     logic [31:29] sbversion;
     logic [28:23] zero0;
@@ -215,8 +221,6 @@ package dm;
     logic         sbaccess8;
   } sbcs_t;
 
-  localparam logic [1:0] DTM_SUCCESS = 2'h0;
-
   typedef struct packed {
     logic [6:0]  addr;
     dtm_op_e     op;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_top.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_top.sv
index 3c9c4451..c21e58d9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_top.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_top.sv
@@ -86,6 +86,7 @@ module dm_top #(
   logic [dm::DataCount-1:0][31:0]   data_csrs_mem;
   logic [dm::DataCount-1:0][31:0]   data_mem_csrs;
   logic                             data_valid;
+  logic                             ndmreset;
   logic [19:0]                      hartsel;
   // System Bus Access Module
   logic [BusWidth-1:0]              sbaddress_csrs_sba;
@@ -104,6 +105,7 @@ module dm_top #(
   logic                             sberror_valid;
   logic [2:0]                       sberror;
 
+  assign ndmreset_o = ndmreset;
 
   dm_csrs #(
     .NrHarts(NrHarts),
@@ -120,7 +122,7 @@ module dm_top #(
     .dmi_resp_valid_o,
     .dmi_resp_ready_i,
     .dmi_resp_o,
-    .ndmreset_o,
+    .ndmreset_o              ( ndmreset              ),
     .dmactive_o,
     .hartsel_o               ( hartsel               ),
     .hartinfo_i,
@@ -201,6 +203,7 @@ module dm_top #(
     .clk_i,
     .rst_ni,
     .debug_req_o,
+    .ndmreset_i              ( ndmreset              ),
     .hartsel_i               ( hartsel               ),
     .haltreq_i               ( haltreq               ),
     .resumereq_i             ( resumereq             ),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag.sv
index 0712f8c6..577c3fd0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag.sv
@@ -17,7 +17,7 @@
 */
 
 module dmi_jtag #(
-  parameter logic [31:0] IdcodeValue = 32'h00000001
+  parameter logic [31:0] IdcodeValue = 32'h00000DB3
 ) (
   input  logic         clk_i,      // DMI Clock
   input  logic         rst_ni,     // Asynchronous reset active low
@@ -134,9 +134,11 @@ module dmi_jtag #(
   assign dmi_resp_ready = 1'b1;
 
   logic error_dmi_busy;
+  logic error_dmi_op_failed;
 
   always_comb begin : p_fsm
     error_dmi_busy = 1'b0;
+    error_dmi_op_failed = 1'b0;
     // default assignments
     state_d   = state_q;
     address_d = address_q;
@@ -177,7 +179,22 @@ module dmi_jtag #(
         WaitReadValid: begin
           // load data into register and shift out
           if (dmi_resp_valid) begin
-            data_d = dmi_resp.data;
+            unique case (dmi_resp.resp)
+              dm::DTM_SUCCESS: begin
+                data_d = dmi_resp.data;
+              end
+              dm::DTM_ERR: begin
+                data_d = 32'hDEAD_BEEF;
+                error_dmi_op_failed = 1'b1;
+              end
+              dm::DTM_BUSY: begin
+                data_d = 32'hB051_B051;
+                error_dmi_busy = 1'b1;
+              end
+              default: begin
+                data_d = 32'hBAAD_C0DE;
+              end
+            endcase
             state_d = Idle;
           end
         end
@@ -193,6 +210,11 @@ module dmi_jtag #(
         WaitWriteValid: begin
           // got a valid answer go back to idle
           if (dmi_resp_valid) begin
+            unique case (dmi_resp.resp)
+              dm::DTM_ERR: error_dmi_op_failed = 1'b1;
+              dm::DTM_BUSY: error_dmi_busy = 1'b1;
+              default: ;
+            endcase
             state_d = Idle;
           end
         end
@@ -218,9 +240,14 @@ module dmi_jtag #(
         error_dmi_busy = 1'b1;
       end
 
-      if (error_dmi_busy) begin
+      if (error_dmi_busy && error_q == DMINoError) begin
         error_d = DMIBusy;
       end
+
+      if (error_dmi_op_failed && error_q == DMINoError) begin
+        error_d = DMIOPFailed;
+      end
+
       // clear sticky error flag
       if (update && dtmcs_q.dmireset && dtmcs_select) begin
         error_d = DMINoError;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag_tap.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag_tap.sv
index 0c188c05..53f0fa9d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag_tap.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dmi_jtag_tap.sv
@@ -94,8 +94,9 @@ module dmi_jtag_tap #(
       jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
     end
 
-    // According to JTAG spec we have to reset the IR to IDCODE in test_logic_reset
     if (test_logic_reset) begin
+      // Bring all TAP state to the initial value.
+      jtag_ir_shift_d = '0;
       jtag_ir_d = IDCODE;
     end
   end
@@ -135,6 +136,12 @@ module dmi_jtag_tap #(
       if (idcode_select)  idcode_d = {td_i, 31'(idcode_q >> 1)};
       if (bypass_select)  bypass_d = td_i;
     end
+
+    if (test_logic_reset) begin
+      // Bring all TAP state to the initial value.
+      idcode_d = IdcodeValue;
+      bypass_d = 1'b0;
+    end
   end
 
   // ----------------
@@ -180,12 +187,12 @@ module dmi_jtag_tap #(
   // ----------------
   logic tck_n, tck_ni;
 
-  cluster_clock_inverter i_tck_inv (
+  tc_clk_inverter i_tck_inv (
     .clk_i ( tck_i  ),
     .clk_o ( tck_ni )
   );
 
-  pulp_clock_mux2 i_dft_tck_mux (
+  tc_clk_mux2 i_dft_tck_mux (
     .clk0_i    ( tck_ni     ),
     .clk1_i    ( tck_i      ), // bypass the inverted clock for testing
     .clk_sel_i ( testmode_i ),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_tech_cells_generic.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_tech_cells_generic.core
index 6a70b8e2..02d8b12c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_tech_cells_generic.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_tech_cells_generic.core
@@ -20,3 +20,4 @@ targets:
   default:
     filesets:
     - target_sim? (rtl_sim)
+    - target_sim_sc? (rtl_sim)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40p.vlt b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40p.vlt
index 65542b42..4be49e61 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40p.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40p.vlt
@@ -114,3 +114,4 @@ lint_off -rule WIDTH -file "*/rtl/cv32e40p_decoder.sv" -match "Logical operator
 lint_off -rule WIDTH -file "*/rtl/cv32e40p_controller.sv" -match "Logical operator LOGAND expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*"
 lint_off -rule WIDTH -file "*/rtl/cv32e40p_cs_registers.sv" -match "Logical operator LOGOR expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*"
 lint_off -rule LATCH -file "*/rtl/cv32e40p_id_stage.sv" -match "Latch inferred for signal*apu_read_regs*"
+lint_off -rule WIDTH -file "*/rtl/cv32e40p_cs_registers.sv" -match "Logical operator LOGOR expects 1 bit on the RHS, but RHS's VARREF 'COREV_PULP' generates 32 bits.*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cve2.vlt b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cve2.vlt
index ac5b0076..7b3fc6bb 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cve2.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cve2.vlt
@@ -6,3 +6,6 @@
 
 lint_off -rule DECLFILENAME -file "*bhv/cve2_sim_clock_gate.sv" -match "*Filename 'cve2_sim_clock_gate' does not match MODULE name: 'cve2_clock_gate'*"
 lint_off -rule UNOPTFLAT -file "*rtl/*.sv" -match "*"
+lint_off -rule UNUSED -file "*rtl/cve2_core.sv" -match "Signal is not used: 'rf_ren_a'*"
+lint_off -rule UNUSED -file "*rtl/cve2_core.sv" -match "Signal is not used: 'rf_ren_b'*"
+lint_off -rule UNUSED -file "*rtl/cve2_wb.sv" -match "Signal is not used:*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt
index 460f3c6b..6a33f058 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt
@@ -11,3 +11,4 @@ lint_off -rule DECLFILENAME -file "*/src/cdc_reset_ctrlr.sv" -match "Filename 'c
 lint_off -rule DECLFILENAME -file "*/src/cdc_fifo_gray_clearable.sv" -match "Filename 'cdc_fifo_gray_clearable' does not match MODULE name: 'cdc_fifo_gray_src_clearable'*"
 lint_off -rule WIDTH -file "*/src/cdc_2phase_clearable.sv" -match "Logical operator GENIF expects 1 bit on the If, but If's VARREF 'CLEAR_ON_ASYNC_RESET' generates 32 bits.*"
 lint_off -rule UNOPTFLAT -file "*/src/cdc_4phase.sv" -match "Signal unoptimizable*"
+lint_off -rule WIDTH -file "*/src/dm_mem.sv" -match "*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/yosyshq_picorv32/picosoc/spiflash.v b/hw/vendor/esl_epfl_x_heep/hw/vendor/yosyshq_picorv32/picosoc/spiflash.v
index e0eef9f7..55342b5f 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/yosyshq_picorv32/picosoc/spiflash.v
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/yosyshq_picorv32/picosoc/spiflash.v
@@ -26,7 +26,7 @@
 // updates output signals 1ns after the SPI clock edge.
 //
 // Supported commands:
-//    AB, B9, FF, 03, BB, EB, ED
+//    AB, B9, FF, 03, BB, EB, ED, 06, 02, 32
 //
 // Well written SPI flash data sheets:
 //    Cypress S25FL064L http://www.cypress.com/file/316661/download
@@ -61,6 +61,8 @@ module spiflash (
 	reg spi_io_vld;
 
 	reg powered_up = 0;
+	reg write_enable = 0;
+	reg write_enable_reset = 0;
 
 	localparam [3:0] mode_spi         = 1;
 	localparam [3:0] mode_dspi_rd     = 2;
@@ -107,7 +109,7 @@ module spiflash (
 
 	initial begin
 		for (i=0;i<=16*1024*1024;i=i+1)
-			memory[i] = '0;
+			memory[i] = 8'h00;
 		result = $value$plusargs("firmware=%s", firmware_file);
 		if (!result)
 			firmware_file = "firmware.hex";
@@ -129,6 +131,9 @@ module spiflash (
 
 				if (spi_cmd == 8'h ff)
 					xip_cmd = 0;
+
+				if (spi_cmd == 8'h 06)
+					write_enable = 1;
 			end
 
 			if (powered_up && spi_cmd == 'h 03) begin
@@ -147,6 +152,25 @@ module spiflash (
 				end
 			end
 
+			if (powered_up && write_enable && spi_cmd == 'h 02) begin
+				if (bytecount == 1)
+					write_enable_reset = 1;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4)
+					spi_addr[7:0] = buffer;
+
+				if (bytecount >= 5 && bytecount <= 260) begin
+					memory[spi_addr] = buffer;
+					spi_addr = spi_addr + 1;
+				end
+			end
+
 			if (powered_up && spi_cmd == 'h bb) begin
 				if (bytecount == 1)
 					mode = mode_dspi_rd;
@@ -197,6 +221,27 @@ module spiflash (
 				end
 			end
 
+			if (powered_up && write_enable && spi_cmd == 'h 32) begin
+				if (bytecount == 1)
+					write_enable_reset = 1;
+
+				if (bytecount == 2)
+					spi_addr[23:16] = buffer;
+
+				if (bytecount == 3)
+					spi_addr[15:8] = buffer;
+
+				if (bytecount == 4) begin
+					spi_addr[7:0] = buffer;
+					mode = mode_qspi_rd;
+				end
+
+				if (bytecount >= 5 && bytecount <= 260) begin
+					memory[spi_addr] = buffer;
+					spi_addr = spi_addr + 1;
+				end
+			end
+
 			if (powered_up && spi_cmd == 'h ed) begin
 				if (bytecount == 1)
 					next_mode = mode_qspi_ddr_rd;
@@ -274,6 +319,10 @@ module spiflash (
 				$display("");
 				$fflush;
 			end
+			if (write_enable_reset) begin
+				write_enable = 0;
+				write_enable_reset = 0;
+			end
 			buffer = 0;
 			bitcount = 0;
 			bytecount = 0;
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/README.md b/hw/vendor/esl_epfl_x_heep/linux_femu/README.md
deleted file mode 100644
index 45764e74..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/README.md
+++ /dev/null
@@ -1,171 +0,0 @@
-# Linux-FEMU
-
-In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the Zynq 7020 chip and Linux is run on the ARM-based processing system (PS) side of the same chip. The X-HEEP JTAG signals are driven by the PS GPIO peripheral and are used to program and debug the architecture, while the X-HEEP UART is connected to the PS UART peripheral and is used to get the stdout of the program running on the architecture. Moreover, the X-HEEP flash SPI is connected to the ARM AXI bus passing through an SPI to AXI bridge: this allows virtualising the flash memory into the on-board DDR RAM memory. In this way, the program running on the architecture can read the external virtualised flash as it was a real flash memory, i.e., this virtualisation is totally transparent to the X-HEEP code.
-
-Go through the following steps to build and use our Linux-FEMU version.
-
-## Build the platform
-
-Start in the x-heep main folder.
-
-## Generate the files
-
-1. Activate the conda environment with:
-
-```
-conda activate core-v-mini-mcu
-```
-
-2. Generate the hdl files by calling:
-
-```
-make linux-femu-gen PAD_CFG=linux_femu/pad_cfg.hjson
-```
-
-__NOTE__: you can customize the mcu-gen process by providing the MEMORY_BANKS - CPU - BUS parameters to the above command.
-
-## Flash the SD card with a Linux image
-
-1. Download the Linux image (version v3.0.1) using the following link:
-
-`http://www.pynq.io/board.html`
-
-2. Follow the procedure explained in the following linked page to flash the downloaded image to the SD card:
-
-`https://pynq.readthedocs.io/en/v2.2.1/appendix.html#writing-the-sd-card`
-
-3. Insert the SD into the Pynq-Z2 board and make sure the booting bridge is on the SD position.
-
-4. Power-on the board and wait for Linux to boot (a row of 4 leds should turn on).
-
-## Create the Vivado project and generate the bitstream
-
-1. Starting in the x-heep main folder, run the following command to create the Vivado project and generate the bitstream:
-
-```
-make vivado-fpga FPGA_BOARD=pynq-z2-arm-emulation
-```
-
-2. Open the project x-heep/build/openhwgroup.org_systems_core-v-mini-mcu_0/pynq-z2-arm-emulation-vivado/openhwgroup.org_systems_core-v-mini-mcu_0.xpr with Vivado and use the Hardware Manager to program the bitstream to the Zynq 7020 of the Pynq-Z2 board.
-
-## Connect to Linux running on the Pynq-Z2 board
-
-Connect your Linux-based PC to the Pynq-Z2 board through Ethernet and run the following command:
-
-```
-ssh -X xilinx@board_ip
-```
-
-The default password is: xilinx
-
-If you need additional documentation on how to connect your PC to the Pynq-Z2 board, use the following link:
-
-`https://pynq.readthedocs.io/en/v2.6.1/getting_started/pynq_z2_setup.html`
-
-## Install OpenOCD on the Pynq-Z2 board
-
-1. Clone the OpenOCD repository usign the following link:
-
-`https://github.com/openocd-org/openocd`
-
-2. Run the following commands from the OpneOCD main folder to install it:
-
-```
-sudo ./bootstrap
-sudo ./configure --enable-sysfsgpio
-sudo make
-sudo make install
-```
-
-## Copy the x-heep folder to the Pynq-Z2 baord
-
-Copy the x-heep/linux_femu/arm/ folder from your PC to the home directory of the Pynq-Z2 board with the following command:
-
-```
-sudo scp -r x-heep/linux_femu/arm/ xilinx@board_ip:~
-```
-
-## Enable UART1 on Linux on the Pynq-Z2 baord
-
-Enter the arm/uart_enable/ folder and run the following commands:
-
-```
-sudo su
-mkdir -p /configfs
-./uart_enable.sh
-exit
-```
-
-These commands enable the UART1 on the ARM system side of the Zynq 7020 on the Pynq-Z2 board. UART1 is used to receive the stdout of the code running on the HEEP architecture implemented on the PL side of the chip.
-
-## Prepare the needed shells
-
-You need to use 5 shells (the first, second and third shells will run on the Pynq-Z2 board, while the fourth and fifth shells will run on your PC):
-
-1. First shell - run virtual flash app on the Pynq-Z2 board - browse to the arm/virtual_flash/ folder and execute the following commands to compile and run the required application:
-
-```
-sudo make clean
-sudo make
-sudo ./virtual_flash
-```
-
-This app allocates a buffer into the off-chip DDR memory of the Pynq-Z2 board and stores its physical base address to the hijacker PL peripheral.
-
-2. Second shell - run the following commands on the Pynq-Z2 board to get the stdout from the app running on x-heep:
-
-```
-sudo apt-get install screen
-sudo screen /dev/ttyPS1 115200
-```
-
-3. Third shell - run openocd on the Pynq-Z2 board - browse to the arm/openocd_cfg/ folder and run the following command:
-
-```
-sudo openocd -f ./gpio_bitbang.cfg
-```
-
-4. Fourth shell - compile HEEP app on your PC - browse to the x-heep/sw/ folder and run the following command:
-
-```
-make clean applications/example_virtual_flash/example_virtual_flash.hex TARGET=pynq-z2
-```
-
-With this command you compile a sample RISC-V based application that uses the allocated DDR-based virtual memory. You may want to change this command with the name of your own application.
-
-5. Fifth shell - run GDB on your PC - browse to the x-heep/sw/applications/example_virtual_flash/ folder and run the following command to connect GDB:
-
-```
-sudo /path_to_your_riscv_toolchain/bin/riscv32-unknown-elf-gdb
-```
-
-Use the following GDB commands to connect to OpenOCD running on the Pynq-Z2 board and run your application:
-
-```
-(gdb) target remote board_ip:3333
-(gdb) load example_virtual_flash.elf
-(gdb) cont
-```
-
-Go back to the first shell and press ENTER to end the application and dump the content of the virtual flash to a file. Then, run the following commands:
-
-```
-xxd dump.txt dump
-nano dump
-```
-
-Check if your result corresponds to the following lines:
-
-```
-00000000: 0000 0000 0000 0001 0000 0002 0000 0003  ................
-00000010: 0000 0004 0000 0005 0000 0006 0000 0007  ................
-00000020: 0000 0008 0000 0009 0000 000a 0000 000b  ................
-00000030: 0000 000c 0000 000d 0000 000e 0000 000f  ................
-00000040: 0000 0010 0000 0011 0000 0012 0000 0013  ................
-00000050: 0000 0014 0000 0015 0000 0016 0000 0017  ................
-00000060: 0000 0018 0000 0019 0000 001a 0000 001b  ................
-00000070: 0000 001c 0000 001d 0000 001e 0000 001f  ................
-00000080: 0000 0000 0000 0000 0000 0000 0000 0000  ................
-```
-
-__NOTE__: to run other applications, press the hard reset button on the Pynq-Z2 board (BTN3) and re-connect OpneOCD and GDB.
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/README.md b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/README.md
deleted file mode 100644
index 38dfdbce..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/README.md
+++ /dev/null
@@ -1,80 +0,0 @@
-### Hardware Configurations
-
-On the hardware side, we must configure the ZYNQ processing system to use the EMIO and export them externally so that they can be attached to x-heep. They are then routed outwards from the wrapper to x-heep JTAG signals.
-
-### Software Configurations
-
-## Target adapter configuration __gpio_bitbang.cfg__:
-
-```
-# SPDX-License-Identifier: GPL-2.0-or-later
-
-#
-# Config for using RaspberryPi's expansion header
-#
-# This is best used with a fast enough buffer but also
-# is suitable for direct connection if the target voltage
-# matches RPi's 3.3V
-#
-# Do not forget the GND connection, pin 6 of the expansion header.
-#
-
-adapter driver sysfsgpio
-transport select jtag
-
-bindto 0.0.0.0
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10001c05
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x000
-echo "Target created"
-
-riscv set_reset_timeout_sec 2000
-riscv set_command_timeout_sec 2000
-# riscv set_prefer_sba off
-
-echo "Setting preferences"
-
-# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
-# Header pin numbers: 23 22 19 21
-sysfsgpio jtag_nums 964 961 963 962
-
-# Each of the SWD lines need a gpio number set: swclk swdio
-# Header pin numbers: 23 22
-# sysfsgpio swd_nums 11 25
-
-# If you define trst or srst, use appropriate reset_config
-# Header pin numbers: TRST - 26, SRST - 18
-
-sysfsgpio trst_num 960
-reset_config trst_only
-
-# sysfsgpio srst_num 24
-# reset_config srst_only srst_push_pull
-
-# or if you have both connected,
-# reset_config trst_and_srst srst_push_pull
-
-scan_chain
-
-init
-
-echo "Init routine started"
-
-halt
-echo "Ready for connections"
-```
-
-This instructs openocd to use the riscv HART and jtag module but instead of transmitting the commands over the usual FTDI usb adapter, it bitbangs the GPIOs by using the SYSFS framework.
-
-In order to understand the pin numbering used in the script we have to know how the JTAG has been ported to the PYNQ without using external adapters. The ZYNQ 7000 offers several banks of GPIO lines used for different purposes. The first 54 are MIO (multiplexed I/O) and are configured for different purposes but are PS-side only. After those, we have 64 EMIO (extended MIO) which are lines that can be routed to the PL). The idea is therefore to expose 5 EMIO GPIOS (5 jtag signals) and route them to the PL and to x-heep directly. Those can be controlled as normal GPIO lines and allow interfacing directly from ARM.
-
-Therefore, the pin numbers used in the configuration file are derived as follows:
-
-1. Find the GPIO starting numbers that linux uses by running ``` sudo cat /sys/kernel/debug/gpio ``` -> in this case it was __906__
-
-2. Add 54 (the first 54 GPIOS are the MIOs).
-
-3. Add the gpio_n assigned to the specific signal (depends on the HDL connections).
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/gpio_bitbang.cfg b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/gpio_bitbang.cfg
deleted file mode 100755
index 11c5519d..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/openocd_cfg/gpio_bitbang.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-
-#
-# Config for using RaspberryPi's expansion header
-#
-# This is best used with a fast enough buffer but also
-# is suitable for direct connection if the target voltage
-# matches RPi's 3.3V
-#
-# Do not forget the GND connection, pin 6 of the expansion header.
-#
-
-adapter driver sysfsgpio
-transport select jtag
-
-bindto 0.0.0.0
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10001c05
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x000
-echo "Target created"
-
-riscv set_reset_timeout_sec 2000
-riscv set_command_timeout_sec 2000
-# riscv set_prefer_sba off
-
-echo "Setting preferences"
-
-# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
-# Header pin numbers: 23 22 19 21
-sysfsgpio jtag_nums 964 961 963 962
-
-# Each of the SWD lines need a gpio number set: swclk swdio
-# Header pin numbers: 23 22
-# sysfsgpio swd_nums 11 25
-
-# If you define trst or srst, use appropriate reset_config
-# Header pin numbers: TRST - 26, SRST - 18
-
-sysfsgpio trst_num 960
-reset_config trst_only
-
-# sysfsgpio srst_num 24
-# reset_config srst_only srst_push_pull
-
-# or if you have both connected,
-# reset_config trst_and_srst srst_push_pull
-
-scan_chain
-
-init
-
-echo "Init routine started"
-
-halt
-echo "Ready for connections"
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/README.md b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/README.md
deleted file mode 100644
index 15f4fac9..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/README.md
+++ /dev/null
@@ -1,57 +0,0 @@
-### Hardware Configurations
-
-On the hardware side, we must configure the ZYNQ processing system to enable UART1 and route tx and rx to the EMIO pins so that they can be attached to x-heep. They are then routed outwards from the wrapper to x-heep UART signals.
-
-__NOTE__: remembed to connect tx to rx and viceversa.
-
-### Software Configurations
-
-## Enable UART1
-
-In order to ask Linux to use that as a normal serial port, we need to modify the DEVICE TREE to expose this new hardware piece. In theory, the UART1 peripheral is already defined in the tree but is disabled. Instead of rebuilding the device tree, we can add an overlay at runtime to add and change configuration properties of the tree. In particular, we need to extend the device tree with the following:
-
-```
-/dts-v1/;
-/plugin/;
-
-/{
-    fragment@0{
-        target-path = "/aliases";
-        __overlay__ {
-            serial1 = "/axi/serial@e0001000";
-        };
-    };
-
-    fragment@1{
-        target = <&uart1>;
-        __overlay__ {
-            status = "okay";
-        };
-    };
-};
-
-```
-
-This first makes an alias to make sure that the uart1 (/axi/serial@e0001000) is called serial1, and then enables it by setting the status as "okay". Aliasing is important to avoid a problem that could arise if the kernel decides to swap the ttyPS1 and ttyPS0 (uart0 and the one used to connect to ARM through serial), because we'd have no access to the board over serial.
-
-1. DTSI file must be compiled into binary format as follows:
-
-```
-dtc -O dtb -o uart_enable.dtbo -b 0 -@ uart_enable.dtsi
-```
-2. We mount the configfs, which is a RAM-based configuration file-system exposed to add overlays.
-
-```
-sudo mount configfs configfs /configfs
-sudo mkdir configfs/device-tree/overlays/uart_enable
-```
-
-3. Concatenate the dtbo binary file to insert into the kernel device tree.
-
-```
-sudo su
-cat uart_enable.dtbo >/configfs/device-tree/overlays/uart_enable/dtbo
-exit
-```
-
-4. Make sure with dmesg that no errors were thrown and that /dev/ttySP1 has appeared -> that is x-heep's serial.
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.dtbo b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.dtbo
deleted file mode 100755
index 896a0f34f64bdb7390b4dc181001e74076428956..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 344
zcmZusJqyAx5WV;@2nq^1xjDH=n@u|PXSjtM(ps#xB&oFj(m&$vq~0~9qWIwD-97G-
zm)q=l2M`AU*pr5&TjGK^Co;HywAJ?^x>h6x)3d&~n709j#0eJx<{4UTxh4puimNs`
zHcD~Nb1ULBz&Z=8HW}uz4#Q9qd4MqJ_<2LNKJSi*%NK$4-`!*K*To4NQbvE5Qb|@<
orS&oT9Gjs3h>RSXRJ-Um$He=)65SDeWC`8_>(EseDl|^Q8(n`scK`qY

diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.dtsi b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.dtsi
deleted file mode 100755
index 21804e30..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-/dts-v1/;
-/plugin/;
-
-/{
-	fragment@0{
-		target-path = "/aliases";
-		__overlay__ {
-			serial1 = "/axi/serial@e0001000";	
-		};
-	};
-
-	fragment@1{
-		target = <&uart1>;
-		__overlay__ {
-			status = "okay";
-		};
-	};
-};
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.sh b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.sh
deleted file mode 100755
index ec02611c..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/uart_enable/uart_enable.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-#!/bin/bash
-
-mount -t configfs configfs /configfs
-mkdir /configfs/device-tree/overlays/uart_enable
-cat ./uart_enable.dtbo >/configfs/device-tree/overlays/uart_enable/dtbo
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/Makefile b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/Makefile
deleted file mode 100755
index e9c11b69..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-all: virtual_flash
-
-virtual_flash: virtual_flash.cpp OverlayControl.c OverlayControl.h
-	g++ -O0 -g -Wall virtual_flash.cpp OverlayControl.c -o virtual_flash -lpthread -lm -lcma
-
-clean:
-	rm -f virtual_flash
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.c b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.c
deleted file mode 100755
index 68f2a857..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.c
+++ /dev/null
@@ -1,103 +0,0 @@
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <sys/mman.h>
-
-// 1 --> Basic logging, 2 --> Debugging
-#define LOGGING 2
-
-#include "OverlayControl.h"
-extern "C" {
-#include <libxlnk_cma.h>
-}
-
-static volatile uint32_t * memMapAddr = NULL;
-static int memMapFileDesc = -1;
-static uint32_t memMapSize = 0;
-
-volatile uint32_t * MapMemIO(uint32_t baseAddr, uint32_t mapSize)
-{
-  bool res = true;
-
-    res = ( (memMapFileDesc = open("/dev/mem", O_RDWR | O_SYNC )) != -1);
-
-    if (!res) {
-    #ifdef LOGGING
-        printf("Error opening file.\n");
-    #endif
-    }
-    else {
-    #if LOGGING == 2
-        printf("File opened.\n");
-    #endif
-        memMapAddr = (volatile unsigned int *)mmap(NULL, mapSize, PROT_READ | PROT_WRITE, MAP_SHARED, memMapFileDesc, baseAddr);
-        res = (memMapAddr != MAP_FAILED);
-        if (!res) {
-      #ifdef LOGGING
-            printf("Memory mapping failed.\n");
-      #endif
-            close(memMapFileDesc);
-            memMapFileDesc = -1;
-      memMapAddr = NULL;
-        }
-    }
-
-    if (res) {
-    #ifdef LOGGING
-        printf("Memory mapped.\n");
-    #endif
-    memMapSize = mapSize;
-  }
-
-    return memMapAddr;
-}
-
-bool UnmapMemIO()
-{
-    bool res = true;
-
-    if ((memMapAddr != NULL) && (memMapAddr != MAP_FAILED)) {
-        if ( munmap((void*)memMapAddr, memMapSize) ) {
-      #ifdef LOGGING
-            printf("Memory unmapping failed.\n");
-      #endif
-            res = false;
-        }
-        else {
-      #ifdef LOGGING
-            printf("Memory unmapped.\n");
-      #endif
-        }
-    }
-
-    if (memMapFileDesc != -1) {
-        close(memMapFileDesc);
-        memMapFileDesc = -1;
-    }
-
-    return res;
-}
-
-// Reference of functions to (de)allocate DMA memory.
-// extern "C" {
-// #include <libxlnk_cma.h>
-// }
-/* * Allocate a physically contiguos chunk of CMA memory and map it into
- * virtual memory space. Return this Virtual pointer. Returns -1 on failure.
-void *cma_alloc(uint32_t len, uint32_t cacheable);
- * Return a physical memory address corresponding to a given Virtual address
- * pointer. Returns NULL on failure.
-unsigned long cma_get_phy_addr(void *buf);
- * Free a previously allocated CMA memory chunk.
-void cma_free(void *buf);
- * Returns the number of available CMA memiry pages which can be allocated.
-uint32_t cma_pages_available();
- * Extra functions in case user needs to flush or invalidate Cache.
-void cma_flush_cache(void *buf, unsigned int phys_addr, int size);
-void cma_invalidate_cache(void *buf, unsigned int phys_addr, int size);
-*/
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.h b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.h
deleted file mode 100755
index 92807321..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/OverlayControl.h
+++ /dev/null
@@ -1,27 +0,0 @@
-
-#ifndef	OVERLAYCONTROL_H
-#define	OVERLAYCONTROL_H
-
-volatile uint32_t * MapMemIO(uint32_t baseAddr, uint32_t mapSize);
-bool UnmapMemIO();
-
-// Reference of functions to (de)allocate DMA memory.
-// extern "C" {
-// #include <libxlnk_cma.h>
-// }
-/* * Allocate a physically contiguos chunk of CMA memory and map it into
- * virtual memory space. Return this Virtual pointer. Returns -1 on failure.
-void *cma_alloc(uint32_t len, uint32_t cacheable);
- * Return a physical memory address corresponding to a given Virtual address
- * pointer. Returns NULL on failure.
-unsigned long cma_get_phy_addr(void *buf);
- * Free a previously allocated CMA memory chunk.
-void cma_free(void *buf);
- * Returns the number of available CMA memiry pages which can be allocated.
-uint32_t cma_pages_available();
- * Extra functions in case user needs to flush or invalidate Cache.
-void cma_flush_cache(void *buf, unsigned int phys_addr, int size);
-void cma_invalidate_cache(void *buf, unsigned int phys_addr, int size);
-*/
-
-#endif // OVERLAYCONTROL_H
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/virtual_flash.cpp b/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/virtual_flash.cpp
deleted file mode 100755
index 8de7bc7c..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/arm/virtual_flash/virtual_flash.cpp
+++ /dev/null
@@ -1,100 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <time.h>
-#include <unistd.h>
-#include <signal.h>
-#include "OverlayControl.h"
-
-extern "C" {
-#include <libxlnk_cma.h>
-}
-
-const uint32_t MEM_IS_CACHEABLE = 0;
-const uint32_t MAP_SIZE = 64*1024;
-const uint32_t BASE_ADDR = 0x43C00000;
-const uint32_t ALLOC_SIZE_BYTE = 64*1024*128;
-const uint32_t FIXED_VALUE = 0x1c;
-
-uint32_t *virtual_flash_buffer, *virtual_flash_buffer_phy;
-
-static void stop(int)
-{
-    signal(SIGTERM, SIG_DFL);
-    signal(SIGINT, SIG_DFL);
-
-    if(virtual_flash_buffer != NULL){
-        FILE* dump = fopen("./dump.txt", "wb");
-        fwrite(virtual_flash_buffer, ALLOC_SIZE_BYTE, 1, dump);
-        fclose(dump);
-    }
-}
-
-int main(int argc, char **argv)
-{
-    signal(SIGTERM, stop);
-    signal(SIGINT, stop);
-    volatile uint8_t *pl_peripherals = NULL;
-    volatile uint32_t* hijacker = NULL;
-
-    printf("Press ENTER to confirm that the bitstream is loaded (proceeding without it can crash the board).\n");
-    getchar();
-
-    // Get the virtual address corresponding to the physical base address of the PL peripherals
-    if ((pl_peripherals = (uint8_t *) MapMemIO(BASE_ADDR, MAP_SIZE)) == NULL) {
-        printf("Error getting address!\n");
-        return -1;
-    }
-    printf("PL peripherals mapped at 0x%08X.\n", (uint32_t)pl_peripherals);
-    fflush(stdout);
-
-    // Map hijacker PL peripheral
-    hijacker = (uint32_t *)pl_peripherals;
-    printf("hijacker mapped at 0x%08X.\n", (uint32_t)hijacker);
-
-    // Allocate DDR memory buffer to virtualize a Flash memory and get its physical address
-    fflush(stdout);
-    virtual_flash_buffer = (uint32_t *)cma_alloc(ALLOC_SIZE_BYTE, MEM_IS_CACHEABLE);
-    virtual_flash_buffer_phy = (uint32_t *)((uint32_t)cma_get_phy_addr(virtual_flash_buffer));
-    printf("DDR memory buffer allocated.\n");
-    fflush(stdout);
-    printf("Virtual address: 0x%.8X.\n", (uint32_t)virtual_flash_buffer);
-    fflush(stdout);
-    printf("Physical address: Phys: 0x%.8X.\n\n", (uint32_t)virtual_flash_buffer_phy);
-    fflush(stdout);
-    if (virtual_flash_buffer == NULL) {
-        printf("Error allocating DDR memory for %u bytes!\n", ALLOC_SIZE_BYTE);
-        return -1;
-    }
-
-    // Initialize DDR memory buffer
-    for (uint32_t i = 0; i < ALLOC_SIZE_BYTE / sizeof(uint32_t); i++)
-        virtual_flash_buffer[0] = i;
-
-    // Copy the physical address of the DDR memory buffer to hijacker PL peripheral
-    *hijacker = (uint32_t)virtual_flash_buffer_phy;
-
-    // Press ENTER to end the application
-    printf("Press ENTER to end the application.\n");
-    getchar();
-
-    printf("Virtual flash read and content stored in file dump.txt.\n\n");
-
-    // Read content of the DDR memory buffer and store it to a file
-    FILE *dump = fopen("./dump.txt", "wb");
-    fwrite(virtual_flash_buffer, ALLOC_SIZE_BYTE, 1, dump);
-    fclose(dump);
-
-    ///////////////////////////////////////////////////////////////////////////////////////
-    // DDR memory is a global variable. In this Linux version, it is allocated
-    // by a pl_peripherals driver provided by Xilinx. This means that it is not freed
-    // automatically when our process exits. We MUST free it or the board will
-    // run out of DMA memory!!!
-    ///////////////////////////////////////////////////////////////////////////////////////
-    if (virtual_flash_buffer != NULL)
-        cma_free(virtual_flash_buffer);
-    UnmapMemIO();
-
-    return 0;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/constraints/constraints.xdc b/hw/vendor/esl_epfl_x_heep/linux_femu/constraints/constraints.xdc
deleted file mode 100644
index ca9babe2..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/constraints/constraints.xdc
+++ /dev/null
@@ -1 +0,0 @@
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets linux_femu/pad_ring_i/pad_clk_i/xilinx_iobuf_i/O]
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/constraints/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/linux_femu/constraints/pin_assign.xdc
deleted file mode 100644
index d6be7e83..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/constraints/pin_assign.xdc
+++ /dev/null
@@ -1,73 +0,0 @@
-# Copyright 2022 EPFL
-# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk_in]
-set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports rst_i]
-set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports rst_led]
-set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports clk_led]
-set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports clk_out]
-set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
-set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
-set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports execute_from_flash_i]
-set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports boot_select_i]
-
-## Pmoda
-## RPi GPIO 7-0 are shared with pmoda_rpi_gpio_tri_io[7:0]
-
-# QSPI
-
-set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_csb_io]
-set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_sck_io]
-set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports {spi_sd_0_io}]
-set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {spi_sd_1_io}]
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {spi_sd_2_io}]
-set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {spi_sd_3_io}]
-
-## Pmodb
-
-set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[0]}]
-set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[1]}]
-set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[2]}]
-set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[3]}]
-set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[4]}]
-set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {gpio_io[5]}]
-set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[6]}]
-set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[7]}]
-set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[8]}]
-set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[9]}]
-set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[10]}]
-set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[11]}]
-set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[12]}]
-set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[13]}]
-set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[14]}]
-set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {gpio_io[15]}]
-set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {gpio_io[16]}]
-set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {gpio_io[17]}]
-set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {gpio_io[18]}]
-set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {gpio_io[19]}]
-set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS33} [get_ports {gpio_io[20]}]
-set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports {gpio_io[21]}]
-set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {gpio_io[22]}]
-set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_io[0]}]
-set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_io[1]}]
-set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports {spi2_sck_io}]
-set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_0_io}]
-set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_1_io}]
-set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_2_io}]
-set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_3_io}]
-#set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[24]}]
-#set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports {gpio_io[25]}]
-#set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[26]}]
-#set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {gpio_io[27]}]
-#set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {gpio_io[28]}]
-#set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[29]}]
-#set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {gpio_io[30]}]
-#set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {gpio_io[31]}]
-
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]
-
-set_property PACKAGE_PIN W13 [get_ports i2c_scl_io]
-set_property PACKAGE_PIN T10 [get_ports i2c_sda_io]
-set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl_io]
-set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda_io]
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/pad_cfg.hjson b/hw/vendor/esl_epfl_x_heep/linux_femu/pad_cfg.hjson
deleted file mode 100644
index 235ee13f..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/pad_cfg.hjson
+++ /dev/null
@@ -1,208 +0,0 @@
-// Copyright 2020 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-// Derived from Occamy: https://github.com/pulp-platform/snitch/blob/master/hw/system/occamy/src/occamy_cfg.hjson
-// Peripherals configuration for core-v-mini-mcu.
-{
-    pads: {
-
-        clk: {
-            num: 1,
-            type: input
-        },
-        rst: {
-            num: 1,
-            active: low,
-            driven_manually: True
-            type: input
-        },
-        boot_select: {
-            num: 1,
-            type: input
-        },
-        execute_from_flash: {
-            num: 1,
-            type: input
-        },
-        jtag_tck: {
-            num: 1,
-            keep_internal: True
-            type: input
-        },
-        jtag_tms: {
-            num: 1,
-            keep_internal: True
-            type: input
-        },
-        jtag_trst: {
-            num: 1,
-            keep_internal: True
-            active: low,
-            type: input
-        },
-        jtag_tdi: {
-            num: 1,
-            keep_internal: True
-            type: input
-        },
-        jtag_tdo: {
-            num: 1,
-            keep_internal: True
-            type: output
-        },
-        uart_rx: {
-            num: 1,
-            keep_internal: True
-            type: input
-        },
-        uart_tx: {
-            num: 1,
-            keep_internal: True
-            type: output
-        },
-        exit_valid: {
-            num: 1,
-            type: output
-        },
-        gpio: {
-            num: 23,
-            num_offset: 0, #first gpio is gpio0
-            type: inout
-        },
-        spi_flash_sck: {
-            num: 1,
-            keep_internal: True
-            type: inout
-        },
-        spi_flash_cs: {
-            num: 2, #carefull, the x-heep uses the CS from the spi pkg, change it
-            keep_internal: True
-            type: inout
-        },
-        spi_flash_sd: {
-            num: 4,
-            keep_internal: True
-            type: inout
-        },
-        spi_sck: {
-            num: 1,
-            type: inout
-        },
-        spi_cs: {
-            num: 2,
-            type: inout
-        },
-        spi_sd: {
-            num: 4,
-            type: inout
-        },
-        spi2_cs_0: {
-            num: 1,
-            type: inout
-            mux: {
-                spi2_cs_0: {
-                    type: inout
-                },
-                gpio_23: {
-                    type: inout
-                },
-            }
-        },
-        spi2_cs_1: {
-            num: 1,
-            type: inout
-            mux: {
-                spi2_cs_1: {
-                    type: inout
-                },
-                gpio_24: {
-                    type: inout
-                },
-            },
-        },
-        spi2_sck: {
-            num: 1,
-            type: inout
-            mux: {
-                spi2_sck: {
-                    type: inout
-                },
-                gpio_25: {
-                    type: inout
-                },
-            }
-        },
-        spi2_sd_0: {
-            num: 1,
-            type: inout
-            mux: {
-                spi2_sd_0: {
-                    type: inout
-                },
-                gpio_26: {
-                    type: inout
-                },
-            }
-        },
-        spi2_sd_1: {
-            num: 1,
-            type: inout
-            mux: {
-                spi2_sd_1: {
-                    type: inout
-                },
-                gpio_27: {
-                    type: inout
-                },
-            }
-        },
-        spi2_sd_2: {
-            num: 1,
-            type: inout
-            mux: {
-                spi2_sd_2: {
-                    type: inout
-                },
-                gpio_28: {
-                    type: inout
-                },
-            }
-        },
-        spi2_sd_3: {
-            num: 1,
-            type: inout
-            mux: {
-                spi2_sd_3: {
-                    type: inout
-                },
-                gpio_29: {
-                    type: inout
-                },
-            }
-        },
-        i2c_scl: {
-            num: 1,
-            type: inout
-            mux: {
-                i2c_scl: {
-                    type: inout
-                },
-                gpio_31: {
-                    type: inout
-                },
-            }
-        },
-        i2c_sda: {
-            num: 1,
-            type: inout
-            mux: {
-                i2c_sda: {
-                    type: inout
-                },
-                gpio_30: {
-                    type: inout
-                },
-            }
-        }
-    }
-}
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/rtl/axi_address_hijacker.v b/hw/vendor/esl_epfl_x_heep/linux_femu/rtl/axi_address_hijacker.v
deleted file mode 100644
index e99c60e8..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/rtl/axi_address_hijacker.v
+++ /dev/null
@@ -1,331 +0,0 @@
-// Copyright 2022 EPFL
-// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-module axi_address_hijacker #
-(
-  parameter integer AXI_ADDR_WIDTH = 32,
-  parameter integer C_S_AXI_DATA_WIDTH = 32,
-  parameter integer C_S_AXI_ADDR_WIDTH = 4
-)(
-  input wire [AXI_ADDR_WIDTH-1:0] axi_master_awaddr_in,
-  input wire [AXI_ADDR_WIDTH-1:0] axi_master_araddr_in,
-
-  output wire [AXI_ADDR_WIDTH-1:0] axi_master_araddr_out,
-  output wire [AXI_ADDR_WIDTH-1:0] axi_master_awaddr_out,
-
-  /////////////////////////////////////////
-  // AXI-Lite slave interface
-  /////////////////////////////////////////
-
-  // clock and reset
-  input wire S_AXI_ACLK,
-  input wire S_AXI_ARESETN,
-
-  // write address
-  input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
-  input wire [2 : 0] S_AXI_AWPROT,
-  input wire S_AXI_AWVALID,
-  output wire S_AXI_AWREADY,
-
-  // write data
-  input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
-  input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
-  input wire S_AXI_WVALID,
-  output wire S_AXI_WREADY,
-
-  // write response
-  output wire [1 : 0] S_AXI_BRESP,
-  output wire S_AXI_BVALID,
-  input wire S_AXI_BREADY,
-
-  // read address
-  input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
-  input wire [2 : 0] S_AXI_ARPROT,
-  input wire S_AXI_ARVALID,
-  output wire S_AXI_ARREADY,
-
-  // read data
-  output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
-  output wire [1 : 0] S_AXI_RRESP,
-  output wire S_AXI_RVALID,
-  input wire S_AXI_RREADY
-);
-
-  reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
-  reg axi_awready;
-  reg axi_wready;
-  reg [1 : 0] axi_bresp;
-  reg axi_bvalid;
-  reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
-  reg axi_arready;
-  reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
-  reg [1 : 0] axi_rresp;
-  reg axi_rvalid;
-
-  localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
-  localparam integer OPT_MEM_ADDR_BITS = 1;
-
-  reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
-  reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
-  reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
-  reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
-  wire slv_reg_rden;
-  wire slv_reg_wren;
-  reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
-  integer byte_index;
-  reg aw_en;
-
-  assign S_AXI_AWREADY = axi_awready;
-  assign S_AXI_WREADY = axi_wready;
-  assign S_AXI_BRESP  = axi_bresp;
-  assign S_AXI_BVALID = axi_bvalid;
-  assign S_AXI_ARREADY = axi_arready;
-  assign S_AXI_RDATA  = axi_rdata;
-  assign S_AXI_RRESP  = axi_rresp;
-  assign S_AXI_RVALID = axi_rvalid;
-
-  // Implement axi_awready generation
-  // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-  // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-  // de-asserted when reset is low.
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        axi_awready <= 1'b0;
-        aw_en <= 1'b1;
-      end
-    else
-      begin
-        if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
-          begin
-            axi_awready <= 1'b1;
-            aw_en <= 1'b0;
-          end
-          else if (S_AXI_BREADY && axi_bvalid)
-              begin
-                aw_en <= 1'b1;
-                axi_awready <= 1'b0;
-              end
-        else
-          begin
-            axi_awready <= 1'b0;
-          end
-      end
-  end
-
-  // Implement axi_awaddr latching
-  // This process is used to latch the address when both
-  // S_AXI_AWVALID and S_AXI_WVALID are valid.
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        axi_awaddr <= 0;
-      end
-    else
-      begin
-        if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
-          begin
-            axi_awaddr <= S_AXI_AWADDR;
-          end
-      end
-  end
-
-  // Implement axi_wready generation
-  // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-  // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-  // de-asserted when reset is low.
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        axi_wready <= 1'b0;
-      end
-    else
-      begin
-        if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
-          begin
-            axi_wready <= 1'b1;
-          end
-        else
-          begin
-            axi_wready <= 1'b0;
-          end
-      end
-  end
-
-  // Implement memory mapped register select and write logic generation
-  // The write data is accepted and written to memory mapped registers when
-  // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-  // select byte enables of slave registers while writing.
-  // These registers are cleared when reset (active low) is applied.
-  // Slave register write enable is asserted when valid address and data are available
-  // and the slave is ready to accept the write address and write data.
-  assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
-
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        slv_reg0 <= 0;
-        slv_reg1 <= 0;
-        slv_reg2 <= 0;
-        slv_reg3 <= 0;
-      end
-    else begin
-      if (slv_reg_wren)
-        begin
-          case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
-            2'h0:
-              for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
-                if ( S_AXI_WSTRB[byte_index] == 1 ) begin
-                  slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
-                end
-            2'h1:
-              for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
-                if ( S_AXI_WSTRB[byte_index] == 1 ) begin
-                  slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
-                end
-            2'h2:
-              for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
-                if ( S_AXI_WSTRB[byte_index] == 1 ) begin
-                  slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
-                end
-            2'h3:
-              for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
-                if ( S_AXI_WSTRB[byte_index] == 1 ) begin
-                  slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
-                end
-            default : begin
-              slv_reg0 <= slv_reg0;
-              slv_reg1 <= slv_reg1;
-              slv_reg2 <= slv_reg2;
-              slv_reg3 <= slv_reg3;
-            end
-          endcase
-        end
-    end
-  end
-
-  // Implement write response logic generation
-  // The write response and response valid signals are asserted by the slave
-  // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-  // This marks the acceptance of address and indicates the status of
-  // write transaction.
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        axi_bvalid  <= 0;
-        axi_bresp   <= 2'b0;
-      end
-    else
-      begin
-        if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
-          begin
-            axi_bvalid <= 1'b1;
-            axi_bresp  <= 2'b0;
-          end
-        else
-          begin
-            if (S_AXI_BREADY && axi_bvalid)
-              begin
-                axi_bvalid <= 1'b0;
-              end
-          end
-      end
-  end
-
-  // Implement axi_arready generation
-  // axi_arready is asserted for one S_AXI_ACLK clock cycle when
-  // S_AXI_ARVALID is asserted. axi_awready is
-  // de-asserted when reset (active low) is asserted.
-  // The read address is also latched when S_AXI_ARVALID is
-  // asserted. axi_araddr is reset to zero on reset assertion.
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        axi_arready <= 1'b0;
-        axi_araddr  <= 32'b0;
-      end
-    else
-      begin
-        if (~axi_arready && S_AXI_ARVALID)
-          begin
-            axi_arready <= 1'b1;
-            axi_araddr  <= S_AXI_ARADDR;
-          end
-        else
-          begin
-            axi_arready <= 1'b0;
-          end
-      end
-  end
-
-  // Implement axi_arvalid generation
-  // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-  // S_AXI_ARVALID and axi_arready are asserted. The slave registers
-  // data are available on the axi_rdata bus at this instance. The
-  // assertion of axi_rvalid marks the validity of read data on the
-  // bus and axi_rresp indicates the status of read transaction.axi_rvalid
-  // is deasserted on reset (active low). axi_rresp and axi_rdata are
-  // cleared to zero on reset (active low).
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        axi_rvalid <= 0;
-        axi_rresp  <= 0;
-      end
-    else
-      begin
-        if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
-          begin
-            axi_rvalid <= 1'b1;
-            axi_rresp  <= 2'b0;
-          end
-        else if (axi_rvalid && S_AXI_RREADY)
-          begin
-            axi_rvalid <= 1'b0;
-          end
-      end
-  end
-
-  // Implement memory mapped register select and read logic generation
-  // Slave register read enable is asserted when valid address is available
-  // and the slave is ready to accept the read address.
-  assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
-  always @(*)
-  begin
-    case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
-      2'h0 : reg_data_out <= slv_reg0;
-      2'h1 : reg_data_out <= slv_reg1;
-      2'h2 : reg_data_out <= slv_reg2;
-      2'h3 : reg_data_out <= slv_reg3;
-      default : reg_data_out <= 0;
-    endcase
-  end
-
-  // Output register or memory read data
-  always @( posedge S_AXI_ACLK )
-  begin
-    if ( S_AXI_ARESETN == 1'b0 )
-      begin
-        axi_rdata <= 0;
-      end
-    else
-      begin
-        if (slv_reg_rden)
-          begin
-            axi_rdata <= reg_data_out;
-          end
-      end
-  end
-
-  assign axi_master_araddr_out = axi_master_araddr_in + slv_reg0;
-  assign axi_master_awaddr_out = axi_master_awaddr_in + slv_reg0;
-
-  endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/rtl/linux_femu.sv.tpl b/hw/vendor/esl_epfl_x_heep/linux_femu/rtl/linux_femu.sv.tpl
deleted file mode 100644
index ef5dad9b..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/rtl/linux_femu.sv.tpl
+++ /dev/null
@@ -1,533 +0,0 @@
-// Copyright 2022 EPFL
-// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-module linux_femu
-  import obi_pkg::*;
-  import reg_pkg::*;
-#(
-  parameter COREV_PULP           = 0,
-  parameter FPU                  = 0,
-  parameter ZFINX                = 0,
-  parameter EXT_XBAR_NMASTER     = 0,
-  parameter CLK_LED_COUNT_LENGTH = 27
-) (
-  inout logic clk_in,
-  inout logic rst_i,
-
-  output logic rst_led,
-  output logic clk_led,
-  output logic clk_out,
-
-  inout logic boot_select_i,
-  inout logic execute_from_flash_i,
-
-  inout logic [29:0] gpio_io,
-
-  output logic exit_value_o,
-  inout  logic exit_valid_o,
-
-  inout logic spi_sd_0_io,
-  inout logic spi_sd_1_io,
-  inout logic spi_sd_2_io,
-  inout logic spi_sd_3_io,
-  inout logic spi_csb_io,
-  inout logic spi_sck_io,
-
-  inout logic spi2_sd_0_io,
-  inout logic spi2_sd_1_io,
-  inout logic spi2_sd_2_io,
-  inout logic spi2_sd_3_io,
-  inout logic [1:0] spi2_csb_io,
-  inout logic spi2_sck_io,
-
-  inout logic i2c_scl_io,
-  inout logic i2c_sda_io,
-
-  inout wire [14:0] DDR_addr,
-  inout wire [2:0] DDR_ba,
-  inout wire DDR_cas_n,
-  inout wire DDR_ck_n,
-  inout wire DDR_ck_p,
-  inout wire DDR_cke,
-  inout wire DDR_cs_n,
-  inout wire [3:0] DDR_dm,
-  inout wire [31:0] DDR_dq,
-  inout wire [3:0] DDR_dqs_n,
-  inout wire [3:0] DDR_dqs_p,
-  inout wire DDR_odt,
-  inout wire DDR_ras_n,
-  inout wire DDR_reset_n,
-  inout wire DDR_we_n,
-  inout wire FIXED_IO_ddr_vrn,
-  inout wire FIXED_IO_ddr_vrp,
-  inout wire [53:0] FIXED_IO_mio,
-  inout wire FIXED_IO_ps_clk,
-  inout wire FIXED_IO_ps_porb,
-  inout wire FIXED_IO_ps_srstb
-);
-
-  import core_v_mini_mcu_pkg::*;
-
-  parameter AXI_ADDR_WIDTH = 32;
-  parameter AXI_ADDR_WIDTH_SLAVE = 4;
-  parameter AXI_DATA_WIDTH = 32;
-
-  // PM signals
-  logic cpu_subsystem_powergate_switch;
-  logic cpu_subsystem_powergate_switch_ack;
-  logic cpu_subsystem_powergate_iso;
-  logic cpu_subsystem_rst_n;
-  logic peripheral_subsystem_powergate_switch;
-  logic peripheral_subsystem_powergate_switch_ack;
-  logic peripheral_subsystem_powergate_iso;
-  logic peripheral_subsystem_rst_n;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_set_retentive;
-
-  // PS SIDE PORTS
-  logic AXI_HP_ACLK;
-  logic AXI_HP_ARESETN;
-  logic [AXI_ADDR_WIDTH - 1:0] AXI_HP_araddr_sig;
-  logic [1:0] AXI_HP_arburst_sig;
-  logic [3:0] AXI_HP_arcache_sig;
-  logic [5:0] AXI_HP_arid_sig;
-  logic [3:0] AXI_HP_arlen_sig;
-  logic [1:0] AXI_HP_arlock_sig;
-  logic [2:0] AXI_HP_arprot_sig;
-  logic [3:0] AXI_HP_arqos_sig;
-  logic AXI_HP_arready_sig;
-  logic [2:0] AXI_HP_arsize_sig;
-  logic AXI_HP_arvalid_sig;
-  logic [AXI_ADDR_WIDTH - 1:0] AXI_HP_awaddr_sig;
-  logic [1:0] AXI_HP_awburst_sig;
-  logic [3:0] AXI_HP_awcache_sig;
-  logic [5:0] AXI_HP_awid_sig;
-  logic [3:0] AXI_HP_awlen_sig;
-  logic [1:0] AXI_HP_awlock_sig;
-  logic [2:0] AXI_HP_awprot_sig;
-  logic [3:0] AXI_HP_awqos_sig;
-  logic AXI_HP_awready_sig;
-  logic [2:0] AXI_HP_awsize_sig;
-  logic AXI_HP_awvalid_sig;
-  logic [5:0] AXI_HP_bid_sig;
-  logic AXI_HP_bready_sig;
-  logic [1:0] AXI_HP_bresp_sig;
-  logic AXI_HP_bvalid_sig;
-  logic [AXI_DATA_WIDTH - 1:0] AXI_HP_rdata_sig;
-  logic [5:0] AXI_HP_rid_sig;
-  logic AXI_HP_rlast_sig;
-  logic AXI_HP_rready_sig;
-  logic [1:0] AXI_HP_rresp_sig;
-  logic AXI_HP_rvalid_sig;
-  logic [AXI_DATA_WIDTH - 1:0] AXI_HP_wdata_sig;
-  logic [5:0] AXI_HP_wid_sig;
-  logic AXI_HP_wlast_sig;
-  logic AXI_HP_wready_sig;
-  logic [3:0] AXI_HP_wstrb_sig;
-  logic AXI_HP_wvalid_sig;
-
-  logic spi_test_clk_sig;
-  logic spi_test_cs_sig;
-  logic [3:0] spi_test_data_sig;
-
-  // ADDRESS HIJACKER PORTS
-  logic [AXI_ADDR_WIDTH-1:0] axi_master_awaddr_in_sig;
-  logic [AXI_ADDR_WIDTH-1:0] axi_master_araddr_in_sig;
-
-  logic [AXI_ADDR_WIDTH_SLAVE - 1 : 0] s00_axi_awaddr_sig;
-  logic s00_axi_awvalid_sig;
-  logic s00_axi_awready_sig;
-  logic [AXI_DATA_WIDTH - 1 : 0] s00_axi_wdata_sig;
-  logic s00_axi_wvalid_sig;
-  logic s00_axi_wready_sig;
-  logic s00_axi_bvalid_sig;
-  logic s00_axi_bready_sig;
-  logic [(AXI_DATA_WIDTH / 8)-1 : 0] s00_axi_wstrb_sig;
-  logic [2 : 0] s00_axi_arprot_sig;
-  logic [2 : 0] s00_axi_awprot_sig;
-  logic [AXI_ADDR_WIDTH_SLAVE - 1 : 0] s00_axi_araddr_sig;
-  logic s00_axi_arvalid_sig;
-  logic s00_axi_arready_sig;
-  logic [AXI_DATA_WIDTH - 1 : 0] s00_axi_rdata_sig;
-  logic s00_axi_rvalid_sig;
-  logic s00_axi_rready_sig;
-  logic [1:0] s00_axi_rresp_sig;
-  logic [1:0] s00_axi_bresp_sig;
-
-  // PAD controller
-  reg_req_t pad_req;
-  reg_rsp_t pad_resp;
-  logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][7:0] pad_attributes;
-  logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][3:0] pad_muxes;
-
-  logic rst_ngen;
-
-  // input, output pins from core_v_mini_mcu
-% for pad in total_pad_list:
-${pad.internal_signals}
-% endfor
-
-  wire                               clk_gen;
-  logic [                      31:0] exit_value;
-  wire                               rst_n;
-  logic [CLK_LED_COUNT_LENGTH - 1:0] clk_count;
-
-  // low active reset
-  assign rst_n   = !rst_i;
-
-  // reset LED for debugging
-  assign rst_led = rst_n;
-
-  // counter to blink an LED
-  assign clk_led = clk_count[CLK_LED_COUNT_LENGTH-1];
-
-  always_ff @(posedge clk_gen or negedge rst_n) begin : clk_count_process
-    if (!rst_n) begin
-      clk_count <= '0;
-    end else begin
-      clk_count <= clk_count + 1;
-    end
-  end
-
-  // clock output for debugging
-  assign clk_out = clk_gen;
-
-  xilinx_clk_wizard_wrapper xilinx_clk_wizard_wrapper_i (
-    .clk_125MHz(clk_in),
-    .clk_out1_0(clk_gen)
-  );
-
-  // eXtension Interface
-  if_xif #() ext_if ();
-
-  logic clk_i;
-  assign clk_i = clk_gen;
-
-  core_v_mini_mcu #(
-    .COREV_PULP(COREV_PULP),
-    .FPU(FPU),
-    .ZFINX(ZFINX),
-    .EXT_XBAR_NMASTER(EXT_XBAR_NMASTER)
-  ) core_v_mini_mcu_i (
-
-    .rst_ni(rst_ngen),
-% for pad in pad_list:
-${pad.core_v_mini_mcu_bonding}
-% endfor
-    .intr_vector_ext_i('0),
-    .xif_compressed_if(ext_if),
-    .xif_issue_if(ext_if),
-    .xif_commit_if(ext_if),
-    .xif_mem_if(ext_if),
-    .xif_mem_result_if(ext_if),
-    .xif_result_if(ext_if),
-    .ext_xbar_master_req_i('0),
-    .ext_xbar_master_resp_o(),
-    .ext_core_instr_req_o(),
-    .ext_core_instr_resp_i('0),
-    .ext_core_data_req_o(),
-    .ext_core_data_resp_i('0),
-    .ext_debug_master_req_o(),
-    .ext_debug_master_resp_i('0),
-    .ext_dma_read_ch0_req_o(),
-    .ext_dma_read_ch0_resp_i('0),
-    .ext_dma_write_ch0_req_o(),
-    .ext_dma_write_ch0_resp_i('0),
-    .ext_dma_addr_ch0_req_o(),
-    .ext_dma_addr_ch0_resp_i('0),
-    .ext_peripheral_slave_req_o(),
-    .ext_peripheral_slave_resp_i('0),
-    .external_subsystem_powergate_switch_o(),
-    .external_subsystem_powergate_switch_ack_i(),
-    .external_subsystem_powergate_iso_o(),
-    .external_subsystem_rst_no(),
-    .external_ram_banks_set_retentive_o(),
-    .exit_value_o(exit_value),
-    .pad_req_o(pad_req),
-    .pad_resp_i(pad_resp),
-    .cpu_subsystem_powergate_switch_o(cpu_subsystem_powergate_switch),
-    .cpu_subsystem_powergate_switch_ack_i(cpu_subsystem_powergate_switch_ack),
-    .peripheral_subsystem_powergate_switch_o(peripheral_subsystem_powergate_switch),
-    .peripheral_subsystem_powergate_switch_ack_i(peripheral_subsystem_powergate_switch_ack),
-    .memory_subsystem_banks_powergate_switch_o(memory_subsystem_banks_powergate_switch),
-    .memory_subsystem_banks_powergate_switch_ack_i(memory_subsystem_banks_powergate_switch_ack)
-  );
-
-  logic gpio_0_io;
-  logic gpio_1_io;
-  logic gpio_2_io;
-  logic gpio_3_io;
-  logic gpio_4_io;
-  logic gpio_5_io;
-  logic gpio_6_io;
-  logic gpio_7_io;
-  logic gpio_8_io;
-  logic gpio_9_io;
-  logic gpio_10_io;
-  logic gpio_11_io;
-  logic gpio_12_io;
-  logic gpio_13_io;
-  logic gpio_14_io;
-  logic gpio_15_io;
-  logic gpio_16_io;
-  logic gpio_17_io;
-  logic gpio_18_io;
-  logic gpio_19_io;
-  logic gpio_20_io;
-  logic gpio_21_io;
-  logic gpio_22_io;
-
-  assign spi_flash_sck_o_sig = spi_flash_sck_out_x;
-  assign spi_flash_csb_o_sig = spi_flash_cs_0_out_x;
-  assign spi_sdi1_sig = spi_flash_sd_1_in_x;
-  assign spi_sdo0_sig = spi_flash_sd_0_out_x;
-  assign spi_sdo2_sig = spi_sd_2_out_x;
-  assign spi_sdo3_sig = spi_sd_3_out_x;
-
-  assign spi2_csb_io[0] = spi2_cs_0_io;
-  assign spi2_csb_io[1] = spi2_cs_1_io;
-
-  assign gpio_io[0] = gpio_0_io;
-  assign gpio_io[1] = gpio_1_io;
-  assign gpio_io[2] = gpio_2_io;
-  assign gpio_io[3] = gpio_3_io;
-  assign gpio_io[4] = gpio_4_io;
-  assign gpio_io[5] = gpio_5_io;
-  assign gpio_io[6] = gpio_6_io;
-  assign gpio_io[7] = gpio_7_io;
-  assign gpio_io[8] = gpio_8_io;
-  assign gpio_io[9] = gpio_9_io;
-  assign gpio_io[10] = gpio_10_io;
-  assign gpio_io[11] = gpio_11_io;
-  assign gpio_io[12] = gpio_12_io;
-  assign gpio_io[13] = gpio_13_io;
-  assign gpio_io[14] = gpio_14_io;
-  assign gpio_io[15] = gpio_15_io;
-  assign gpio_io[16] = gpio_16_io;
-  assign gpio_io[17] = gpio_17_io;
-  assign gpio_io[18] = gpio_18_io;
-  assign gpio_io[19] = gpio_19_io;
-  assign gpio_io[20] = gpio_20_io;
-  assign gpio_io[21] = gpio_21_io;
-  assign gpio_io[22] = gpio_22_io;
-
-  processing_system_wrapper processing_system_wrapper_i (
-    .DDR_addr(DDR_addr),
-    .DDR_ba(DDR_ba),
-    .DDR_cas_n(DDR_cas_n),
-    .DDR_ck_n(DDR_ck_n),
-    .DDR_ck_p(DDR_ck_p),
-    .DDR_cke(DDR_cke),
-    .DDR_cs_n(DDR_cs_n),
-    .DDR_dm(DDR_dm),
-    .DDR_dq(DDR_dq),
-    .DDR_dqs_n(DDR_dqs_n),
-    .DDR_dqs_p(DDR_dqs_p),
-    .DDR_odt(DDR_odt),
-    .DDR_ras_n(DDR_ras_n),
-    .DDR_reset_n(DDR_reset_n),
-    .DDR_we_n(DDR_we_n),
-    .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
-    .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
-    .FIXED_IO_mio(FIXED_IO_mio),
-    .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
-    .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
-    .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
-    .UART_rxd(uart_tx_out_x),
-    .UART_txd(uart_rx_in_x),
-    .gpio_jtag_tck_i(jtag_tck_in_x),
-    .gpio_jtag_tms_i(jtag_tms_in_x),
-    .gpio_jtag_trst_ni(jtag_trst_nin_x),
-    .gpio_jtag_tdi_i(jtag_tdi_in_x),
-    .gpio_jtag_tdo_o(jtag_tdo_out_x),
-    .AXI_HP_ACLK(AXI_HP_ACLK),
-    .AXI_HP_ARESETN(AXI_HP_ARESETN),
-    .AXI_HP_araddr(AXI_HP_araddr_sig),
-    .AXI_HP_arburst(AXI_HP_arburst_sig),
-    .AXI_HP_arcache(AXI_HP_arcache_sig),
-    .AXI_HP_arlen(AXI_HP_arlen_sig),
-    .AXI_HP_arlock(AXI_HP_arlock_sig),
-    .AXI_HP_arprot(AXI_HP_arprot_sig),
-    .AXI_HP_arqos(AXI_HP_arqos_sig),
-    .AXI_HP_arready(AXI_HP_arready_sig),
-    .AXI_HP_arsize(AXI_HP_arsize_sig),
-    .AXI_HP_arvalid(AXI_HP_arvalid_sig),
-    .AXI_HP_awaddr(AXI_HP_awaddr_sig),
-    .AXI_HP_awburst(AXI_HP_awburst_sig),
-    .AXI_HP_awcache(AXI_HP_awcache_sig),
-    .AXI_HP_awlen(AXI_HP_awlen_sig),
-    .AXI_HP_awlock(AXI_HP_awlock_sig),
-    .AXI_HP_awprot(AXI_HP_awprot_sig),
-    .AXI_HP_awqos(AXI_HP_awqos_sig),
-    .AXI_HP_awready(AXI_HP_awready_sig),
-    .AXI_HP_awsize(AXI_HP_awsize_sig),
-    .AXI_HP_awvalid(AXI_HP_awvalid_sig),
-    .AXI_HP_bready(AXI_HP_bready_sig),
-    .AXI_HP_bresp(AXI_HP_bresp_sig),
-    .AXI_HP_bvalid(AXI_HP_bvalid_sig),
-    .AXI_HP_rdata(AXI_HP_rdata_sig),
-    .AXI_HP_rlast(AXI_HP_rlast_sig),
-    .AXI_HP_rready(AXI_HP_rready_sig),
-    .AXI_HP_rresp(AXI_HP_rresp_sig),
-    .AXI_HP_rvalid(AXI_HP_rvalid_sig),
-    .AXI_HP_wdata(AXI_HP_wdata_sig),
-    .AXI_HP_wlast(AXI_HP_wlast_sig),
-    .AXI_HP_wready(AXI_HP_wready_sig),
-    .AXI_HP_wstrb(AXI_HP_wstrb_sig),
-    .AXI_HP_wvalid(AXI_HP_wvalid_sig),
-    .M_AXI_araddr(s00_axi_araddr_sig),
-    .M_AXI_arready(s00_axi_arready_sig),
-    .M_AXI_arvalid(s00_axi_arvalid_sig),
-    .M_AXI_awaddr(s00_axi_awaddr_sig),
-    .M_AXI_awready(s00_axi_awready_sig),
-    .M_AXI_awvalid(s00_axi_awvalid_sig),
-    .M_AXI_bready(s00_axi_bready_sig),
-    .M_AXI_bresp(s00_axi_bresp_sig),
-    .M_AXI_bvalid(s00_axi_bvalid_sig),
-    .M_AXI_rdata(s00_axi_rdata_sig),
-    .M_AXI_rready(s00_axi_rready_sig),
-    .M_AXI_rresp(s00_axi_rresp_sig),
-    .M_AXI_rvalid(s00_axi_rvalid_sig),
-    .M_AXI_wdata(s00_axi_wdata_sig),
-    .M_AXI_wready(s00_axi_wready_sig),
-    .M_AXI_wvalid(s00_axi_wvalid_sig),
-    .M_AXI_awprot(s00_axi_awprot_sig),
-    .M_AXI_arprot(s00_axi_arprot_sig),
-    .M_AXI_wstrb(s00_axi_wstrb_sig)
-  );
-
-  axi_address_hijacker #(
-    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
-    .C_S_AXI_DATA_WIDTH(AXI_DATA_WIDTH)
-  ) add_hij (
-    .axi_master_awaddr_in(axi_master_awaddr_in_sig),
-    .axi_master_araddr_in(axi_master_araddr_in_sig),
-
-    // output write and read address by adding fixed offset
-    .axi_master_araddr_out(AXI_HP_araddr_sig),
-    .axi_master_awaddr_out(AXI_HP_awaddr_sig),
-
-    .S_AXI_ACLK(AXI_HP_ACLK),
-    .S_AXI_ARESETN(AXI_HP_ARESETN),
-
-    .S_AXI_AWADDR (s00_axi_awaddr_sig),
-    .S_AXI_AWPROT (s00_axi_awprot_sig),
-    .S_AXI_AWVALID(s00_axi_awvalid_sig),
-    .S_AXI_AWREADY(s00_axi_awready_sig),
-    .S_AXI_WDATA  (s00_axi_wdata_sig),
-    .S_AXI_WSTRB  (s00_axi_wstrb_sig),
-    .S_AXI_WVALID (s00_axi_wvalid_sig),
-    .S_AXI_WREADY (s00_axi_wready_sig),
-    .S_AXI_BRESP  (s00_axi_bresp_sig),
-    .S_AXI_BVALID (s00_axi_bvalid_sig),
-    .S_AXI_BREADY (s00_axi_bready_sig),
-    .S_AXI_ARADDR (s00_axi_araddr_sig),
-    .S_AXI_ARPROT (s00_axi_arprot_sig),
-    .S_AXI_ARVALID(s00_axi_arvalid_sig),
-    .S_AXI_ARREADY(s00_axi_arready_sig),
-    .S_AXI_RDATA  (s00_axi_rdata_sig),
-    .S_AXI_RRESP  (s00_axi_rresp_sig),
-    .S_AXI_RVALID (s00_axi_rvalid_sig),
-    .S_AXI_RREADY (s00_axi_rready_sig)
-  );
-
-  axi_spi_slave #(
-    .AXI_DATA_WIDTH(AXI_DATA_WIDTH)
-  ) fake_flash (
-    .axi_aclk(AXI_HP_ACLK),
-    .axi_aresetn(AXI_HP_ARESETN),
-
-    .test_mode('0),
-
-    .axi_master_aw_valid(AXI_HP_awvalid_sig),
-    .axi_master_aw_id(AXI_HP_awid_sig),
-    .axi_master_aw_prot(AXI_HP_awprot_sig),
-    .axi_master_aw_qos(AXI_HP_awqos_sig),
-    .axi_master_aw_cache(AXI_HP_awcache_sig),
-    .axi_master_aw_lock(AXI_HP_awlock_sig),
-    .axi_master_aw_burst(AXI_HP_awburst_sig),
-    .axi_master_aw_size(AXI_HP_awsize_sig),
-    .axi_master_aw_len(AXI_HP_awlen_sig),
-    .axi_master_aw_addr(axi_master_awaddr_in_sig),
-    .axi_master_aw_ready(AXI_HP_awready_sig),
-
-    .axi_master_w_valid(AXI_HP_wvalid_sig),
-    .axi_master_w_data (AXI_HP_wdata_sig),
-    .axi_master_w_strb (AXI_HP_wstrb_sig),
-    .axi_master_w_last (AXI_HP_wlast_sig),
-    .axi_master_w_ready(AXI_HP_wready_sig),
-
-    .axi_master_b_valid(AXI_HP_bvalid_sig),
-    .axi_master_b_id(AXI_HP_bid_sig),
-    .axi_master_b_resp(AXI_HP_bresp_sig),
-    .axi_master_b_ready(AXI_HP_bready_sig),
-
-    .axi_master_ar_valid(AXI_HP_arvalid_sig),
-    .axi_master_ar_id(AXI_HP_arid_sig),
-    .axi_master_ar_prot(AXI_HP_arprot_sig),
-    .axi_master_ar_qos(AXI_HP_arqos_sig),
-    .axi_master_ar_cache(AXI_HP_arcache_sig),
-    .axi_master_ar_lock(AXI_HP_arlock_sig),
-    .axi_master_ar_burst(AXI_HP_arburst_sig),
-    .axi_master_ar_size(AXI_HP_arsize_sig),
-    .axi_master_ar_len(AXI_HP_arlen_sig),
-    .axi_master_ar_addr(axi_master_araddr_in_sig),
-    .axi_master_ar_ready(AXI_HP_arready_sig),
-
-    .axi_master_r_valid(AXI_HP_rvalid_sig),
-    .axi_master_r_id(AXI_HP_rid_sig),
-    .axi_master_r_data(AXI_HP_rdata_sig),
-    .axi_master_r_resp(AXI_HP_rresp_sig),
-    .axi_master_r_last(AXI_HP_rlast_sig),
-    .axi_master_r_ready(AXI_HP_rready_sig),
-
-    .spi_sclk(spi_flash_sck_o_sig),
-    .spi_cs  (spi_flash_csb_o_sig),
-    .spi_sdo1(spi_sdi1_sig),
-    .spi_sdi0(spi_sdo0_sig),
-    .spi_sdi2(spi_sdo2_sig),
-    .spi_sdi3(spi_sdo3_sig)
-  );
-
-  // TESTING PURPOSES -> THEY WILL BE INPUT TO PS AND READ BY SYSTEM ILA
-  assign spi_test_clk_sig  = spi_flash_sck_o_sig;
-  assign spi_test_cs_sig   = spi_flash_csb_o_sig;
-  assign spi_test_data_sig = {spi_sdo0_sig, spi_sdi1_sig, spi_sdo2_sig, spi_sdo3_sig};
-
-  pad_ring pad_ring_i (
-% for pad in total_pad_list:
-${pad.pad_ring_bonding_bonding}
-% endfor
-    .pad_attributes_i(pad_attributes)
-  );
-
-${pad_constant_driver_assign}
-
-${pad_mux_process}
-
-  pad_control #(
-    .reg_req_t(reg_pkg::reg_req_t),
-    .reg_rsp_t(reg_pkg::reg_rsp_t),
-    .NUM_PAD  (core_v_mini_mcu_pkg::NUM_PAD)
-  ) pad_control_i (
-    .clk_i(clk_in_x),
-    .rst_ni(rst_ngen),
-    .reg_req_i(pad_req),
-    .reg_rsp_o(pad_resp),
-    .pad_attributes_o(pad_attributes),
-    .pad_muxes_o(pad_muxes)
-  );
-
-  rstgen rstgen_i (
-    .clk_i(clk_in_x),
-    .rst_ni(rst_n),
-    .test_mode_i(1'b0),
-    .rst_no(rst_ngen),
-    .init_no()
-  );
-
-  assign exit_value_o = exit_value[0];
-endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/linux_femu/scripts/xilinx_generate_processing_system.tcl b/hw/vendor/esl_epfl_x_heep/linux_femu/scripts/xilinx_generate_processing_system.tcl
deleted file mode 100644
index a4628c5b..00000000
--- a/hw/vendor/esl_epfl_x_heep/linux_femu/scripts/xilinx_generate_processing_system.tcl
+++ /dev/null
@@ -1,118 +0,0 @@
-# Copyright 2022 EPFL
-# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-# Define design macros
-
-# Select board
-set_property board_part tul.com.tw:pynq-z2:part0:1.0 [current_project]
-
-# Create block design
-create_bd_design "processing_system"
-
-# Add Zynq Processing System
-create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" }  [get_bd_cells processing_system7_0]
-set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_UART1_IO {EMIO} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} CONFIG.PCW_GPIO_EMIO_GPIO_IO {5}] [get_bd_cells processing_system7_0]
-
-# Add AXI Interconnect
-create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0
-set_property -dict [list CONFIG.NUM_SI {2} CONFIG.NUM_MI {2}] [get_bd_cells axi_interconnect_0]
-
-# Add Constant
-create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0
-set_property -dict [list CONFIG.CONST_WIDTH {2} CONFIG.CONST_VAL {0b11}] [get_bd_cells xlconstant_0]
-
-# Add Concatenation
-create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0
-set_property -dict [list CONFIG.IN0_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN2_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_0]
-set_property -dict [list CONFIG.NUM_PORTS {3} CONFIG.IN0_WIDTH {2} CONFIG.IN2_WIDTH {2}] [get_bd_cells xlconcat_0]
-
-# Add Slices
-create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0
-create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1
-create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2
-create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3
-set_property -dict [list CONFIG.DIN_TO {3} CONFIG.DIN_FROM {3} CONFIG.DIN_WIDTH {5} CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_0]
-set_property -dict [list CONFIG.DIN_TO {4} CONFIG.DIN_FROM {4} CONFIG.DIN_WIDTH {5} CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_1]
-set_property -dict [list CONFIG.DIN_TO {1} CONFIG.DIN_FROM {1} CONFIG.DIN_WIDTH {5} CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_2]
-set_property -dict [list CONFIG.DIN_TO {0} CONFIG.DIN_FROM {0} CONFIG.DIN_WIDTH {5} CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_3]
-
-# Create port AXI_HP
-make_bd_intf_pins_external [get_bd_intf_pins axi_interconnect_0/S00_AXI]
-set_property name AXI_HP [get_bd_intf_ports S00_AXI_0]
-set_property -dict [list CONFIG.FREQ_HZ {20000000}] [get_bd_intf_ports AXI_HP]
-
-# Create port M_AXI
-make_bd_intf_pins_external  [get_bd_intf_pins axi_interconnect_0/M01_AXI]
-set_property name M_AXI [get_bd_intf_ports M01_AXI_0]
-set_property -dict [list CONFIG.FREQ_HZ {20000000}] [get_bd_intf_ports M_AXI]
-
-# Connect AXI Interconnect and Zynq Processing System
-connect_bd_intf_net -boundary_type upper [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
-connect_bd_intf_net [get_bd_intf_pins processing_system7_0/M_AXI_GP0] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S01_AXI]
-apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/processing_system7_0/FCLK_CLK0 (20 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/ACLK]
-apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/processing_system7_0/FCLK_CLK0 (20 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/M00_ACLK]
-apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/processing_system7_0/FCLK_CLK0 (20 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/M01_ACLK]
-apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/processing_system7_0/FCLK_CLK0 (20 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/S00_ACLK]
-apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/processing_system7_0/FCLK_CLK0 (20 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} [get_bd_pins axi_interconnect_0/S01_ACLK]
-
-# Create port AXI_HP_ACLK
-create_bd_port -dir O -type clk AXI_HP_ACLK
-
-# Create port AXI_HP_ARESETN
-create_bd_port -dir O -type rst AXI_HP_ARESETN
-
-# Connect AXI_HP_ACLK and AXI_HP_ARESETN
-connect_bd_net [get_bd_ports AXI_HP_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0]
-connect_bd_net [get_bd_ports AXI_HP_ARESETN] [get_bd_pins rst_ps7_0_20M/peripheral_aresetn]
-
-# Create port gpio_jtag_tdo_o
-make_bd_pins_external [get_bd_pins xlconcat_0/In1]
-set_property name gpio_jtag_tdo_o [get_bd_ports In1_0]
-
-# Connect Constant and Concatenation
-connect_bd_net [get_bd_pins xlconstant_0/dout] [get_bd_pins xlconcat_0/In0]
-connect_bd_net [get_bd_pins xlconcat_0/In2] [get_bd_pins xlconstant_0/dout]
-connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins processing_system7_0/GPIO_I]
-
-# Create port gpio_jtag_tdi_i
-make_bd_pins_external [get_bd_pins xlslice_0/Dout]
-set_property name gpio_jtag_tdi_i [get_bd_ports Dout_0]
-
-# Create port gpio_jtag_tck_i
-make_bd_pins_external [get_bd_pins xlslice_1/Dout]
-set_property name gpio_jtag_tck_i [get_bd_ports Dout_0]
-
-# Create port gpio_jtag_tms_i
-make_bd_pins_external [get_bd_pins xlslice_2/Dout]
-set_property name gpio_jtag_tms_i [get_bd_ports Dout_0]
-
-# Create port gpio_jtag_trst_ni
-make_bd_pins_external [get_bd_pins xlslice_3/Dout]
-set_property name gpio_jtag_trst_ni [get_bd_ports Dout_0]
-
-# Connect Slices
-connect_bd_net [get_bd_pins xlslice_0/Din] [get_bd_pins processing_system7_0/GPIO_O]
-connect_bd_net [get_bd_pins xlslice_1/Din] [get_bd_pins processing_system7_0/GPIO_O]
-connect_bd_net [get_bd_pins xlslice_2/Din] [get_bd_pins processing_system7_0/GPIO_O]
-connect_bd_net [get_bd_pins xlslice_3/Din] [get_bd_pins processing_system7_0/GPIO_O]
-
-# Create port UART
-make_bd_intf_pins_external [get_bd_intf_pins processing_system7_0/UART_1]
-set_property name UART [get_bd_intf_ports UART_1_0]
-
-# Assign addresses
-assign_bd_address
-
-# Validate design
-validate_bd_design
-
-# Save design
-save_bd_design
-
-# Close design
-close_bd_design [get_bd_designs processing_system]
-
-# Make wrapper
-set wrapper_path [ make_wrapper -fileset sources_1 -files [ get_files -norecurse processing_system.bd ] -top ]
-add_files -norecurse -fileset sources_1 $wrapper_path
diff --git a/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson b/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
index 4bc1e1df..f1d435df 100644
--- a/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
+++ b/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
@@ -27,6 +27,8 @@
                 lenght: whatisleft, #keyword used to calculate the size as: ram.length - code.lenght
             }
         },
+        stack_size: 0x800,
+        heap_size: 0x800,
     }
 
     debug: {
diff --git a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
index 98440522..ed74849a 100644
--- a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
+++ b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
@@ -27,6 +27,8 @@
                 lenght: whatisleft, #keyword used to calculate the size as: ram.length - code.lenght
             }
         },
+        stack_size: 0x800,
+        heap_size: 0x800,
     }
 
     debug: {
diff --git a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
index d857d792..9639d6cf 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
+++ b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
@@ -63,9 +63,9 @@ FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS ${SOURCE_PATH}*.h)
 SET(dir_list_str "")
 FOREACH(file_path ${new_list})
   SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-  if(${file_path} MATCHES "/device/")
-    if(${file_path} MATCHES "/target/") # Add it if its not in target, or if its in target/${TARGET}
-      if(${file_path} MATCHES ${TARGET})
+  if(${file_path} MATCHES "${ROOT_PROJECT}device/")
+    if(${file_path} MATCHES "${ROOT_PROJECT}device/target/") # Add it if its not in target, or if its in target/${TARGET}
+      if(${file_path} MATCHES "${ROOT_PROJECT}device/target/${TARGET}")
         SET(add 1)
       endif()
     else()
@@ -73,9 +73,9 @@ FOREACH(file_path ${new_list})
     endif()
   elseif(${file_path} MATCHES ${PROJECT})
     SET(add 1)
-  elseif( ( ${file_path} MATCHES "/freertos/" ) AND ( ${PROJECT} MATCHES "freertos" ) )
+  elseif( ( ${file_path} MATCHES "${ROOT_PROJECT}freertos/" ) AND ( ${PROJECT} MATCHES "freertos" ) )
     SET(add 1)
-  elseif( ${file_path} MATCHES "/external/" )
+  elseif( ${file_path} MATCHES "${ROOT_PROJECT}external/" )
     SET(add 1)
   endif()
 
@@ -124,9 +124,9 @@ SET( c_dir_list "" )
 SET( app_found 0 )
 FOREACH(file_path IN LISTS new_list)
   SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-  if(${file_path} MATCHES "/device/")
+  if(${file_path} MATCHES "${ROOT_PROJECT}device/")
     SET(add 1)
-  elseif( ${file_path} MATCHES "/external/" )
+  elseif( ${file_path} MATCHES "${ROOT_PROJECT}external/" )
     SET(add 1)
   elseif( ( ${file_path} MATCHES "/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES ${MAINFILE} ) )
     SET(add 1)
@@ -153,7 +153,7 @@ if( app_found EQUAL 0 )
   SET(c_dir_list "")
   FOREACH(file_path IN LISTS new_list)
     SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-    if(${file_path} MATCHES "/device/")
+    if(${file_path} MATCHES "${ROOT_PROJECT}device/")
       SET(add 1)
     elseif( ( ${file_path} MATCHES "/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES ${MAINFILE} ) )
       SET(add 1)
@@ -303,14 +303,27 @@ endif()
 # Set CMAKE flags
 
 # specify the C standard
-set(COMPILER_LINKER_FLAGS "\
-  -march=${CMAKE_SYSTEM_PROCESSOR} \
-  -w -Os -g  -nostdlib  \
-  -DHOST_BUILD \
-  -D${CRT_TYPE} \
-  -D${CRTO} \
-  -DportasmHANDLE_INTERRUPT=vSystemIrqHandler\
-")
+if(NOT ${PROJECT} MATCHES "coremark")
+  set(COMPILER_LINKER_FLAGS "\
+    -march=${CMAKE_SYSTEM_PROCESSOR} \
+    -w -O2 -g  -nostdlib  \
+    -ffunction-sections \
+    -DHOST_BUILD \
+    -D${CRT_TYPE} \
+    -D${CRTO} \
+    -DportasmHANDLE_INTERRUPT=vSystemIrqHandler\
+  ")
+else()
+  set(COMPILER_LINKER_FLAGS "\
+    -march=${CMAKE_SYSTEM_PROCESSOR} \
+    -w -O3 -g  -nostdlib -falign-functions=16 -funroll-all-loops -falign-jumps=4 -finline-functions -Wall -static -pedantic -DPERFORMANCE_RUN=1 -DITERATIONS=1 -DHAS_STDIO=1 -DHAS_PRINTF=1 \
+    -ffunction-sections \
+    -DHOST_BUILD \
+    -D${CRT_TYPE} \
+    -D${CRTO} \
+    -DportasmHANDLE_INTERRUPT=vSystemIrqHandler\
+  ")
+endif()
 set(CMAKE_C_FLAGS ${COMPILER_LINKER_FLAGS})
 
 if (${COMPILER} MATCHES "clang")
@@ -401,7 +414,7 @@ endif()
 
 # Post processing command to create a disassembly file
 add_custom_command(TARGET ${MAINFILE}.elf POST_BUILD
-        COMMAND ${CMAKE_OBJDUMP} -S  ${MAINFILE}.elf > ${MAINFILE}.disasm
+        COMMAND ${CMAKE_OBJDUMP} -S  ${MAINFILE}.elf > ${MAINFILE}.S
         COMMENT "Invoking: Disassemble")
 
 # Post processing command to create a hex file
@@ -434,4 +447,4 @@ endforeach()
 
 SET(DCMAKE_EXPORT_COMPILE_COMMANDS ON)
 
-#message( FATAL_ERROR "You can not do this at all, CMake will exit." )
\ No newline at end of file
+#message( FATAL_ERROR "You can not do this at all, CMake will exit." )
diff --git a/hw/vendor/esl_epfl_x_heep/sw/Makefile b/hw/vendor/esl_epfl_x_heep/sw/Makefile
index 3582fb25..a36f5ead 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/sw/Makefile
@@ -25,7 +25,7 @@ PROJECT  ?= hello_world
 # Linker options are 'on_chip' (default),'flash_load','flash_exec'
 LINKER   ?= on_chip
 
-# Target options are 'sim' (default) and 'pynq-z2'
+# Target options are 'sim' (default), 'pynq-z2', and 'nexys-a7-100t'
 TARGET   ?= sim
 
 # Compiler options are 'gcc' (default) and 'clang'
@@ -38,7 +38,7 @@ COMPILER_PREFIX ?= riscv32-unknown-
 ARCH     ?= rv32imc
 
 # Path relative from the location of sw/Makefile from which to fetch source files. The directory of that file is the default value.
-SOURCE 	 ?= "."
+SOURCE 	 ?= $(".")
 
 # riscv toolchain install path
 RISCV                      ?= ~/.riscv
@@ -56,7 +56,7 @@ source_path := $(realpath $(mkfile_path)/$(SOURCE))
 $(info $$You are fetching sources from $(source_path) )
 
 
-SOURCE_PATH   		   = $(source_path)/
+SOURCE_PATH   		       = $(source_path)/
 ROOT_PROJECT               = $(mkfile_path)/
 INC_FOLDERS                = $(mkfile_path)/device/target/$(TARGET)/
 LINK_FOLDER                = $(mkfile_path)/linker
@@ -70,6 +70,9 @@ else
 CMAKE=cmake3
 endif
 
+# Export variables to sub-makefiles
+export
+
 # Let's CMake!
 include cmake/targets.mak
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_list_join.c b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_list_join.c
new file mode 100644
index 00000000..64527aa5
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_list_join.c
@@ -0,0 +1,612 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+#include "coremark.h"
+/*
+Topic: Description
+        Benchmark using a linked list.
+
+        Linked list is a common data structure used in many applications.
+
+        For our purposes, this will excercise the memory units of the processor.
+        In particular, usage of the list pointers to find and alter data.
+
+        We are not using Malloc since some platforms do not support this
+library.
+
+        Instead, the memory block being passed in is used to create a list,
+        and the benchmark takes care not to add more items then can be
+        accomodated by the memory block. The porting layer will make sure
+        that we have a valid memory block.
+
+        All operations are done in place, without using any extra memory.
+
+        The list itself contains list pointers and pointers to data items.
+        Data items contain the following:
+
+        idx - An index that captures the initial order of the list.
+        data - Variable data initialized based on the input parameters. The 16b
+are divided as follows: o Upper 8b are backup of original data. o Bit 7
+indicates if the lower 7 bits are to be used as is or calculated. o Bits 0-2
+indicate type of operation to perform to get a 7b value. o Bits 3-6 provide
+input for the operation.
+
+*/
+
+/* local functions */
+
+list_head *core_list_find(list_head *list, list_data *info);
+list_head *core_list_reverse(list_head *list);
+list_head *core_list_remove(list_head *item);
+list_head *core_list_undo_remove(list_head *item_removed,
+                                 list_head *item_modified);
+list_head *core_list_insert_new(list_head * insert_point,
+                                list_data * info,
+                                list_head **memblock,
+                                list_data **datablock,
+                                list_head * memblock_end,
+                                list_data * datablock_end);
+typedef ee_s32 (*list_cmp)(list_data *a, list_data *b, core_results *res);
+list_head *core_list_mergesort(list_head *   list,
+                               list_cmp      cmp,
+                               core_results *res);
+
+ee_s16
+calc_func(ee_s16 *pdata, core_results *res)
+{
+    ee_s16 data = *pdata;
+    ee_s16 retval;
+    ee_u8  optype
+        = (data >> 7)
+          & 1;  /* bit 7 indicates if the function result has been cached */
+    if (optype) /* if cached, use cache */
+        return (data & 0x007f);
+    else
+    {                             /* otherwise calculate and cache the result */
+        ee_s16 flag = data & 0x7; /* bits 0-2 is type of function to perform */
+        ee_s16 dtype
+            = ((data >> 3)
+               & 0xf);       /* bits 3-6 is specific data for the operation */
+        dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */
+        switch (flag)
+        {
+            case 0:
+                if (dtype < 0x22) /* set min period for bit corruption */
+                    dtype = 0x22;
+                retval = core_bench_state(res->size,
+                                          res->memblock[3],
+                                          res->seed1,
+                                          res->seed2,
+                                          dtype,
+                                          res->crc);
+                if (res->crcstate == 0)
+                    res->crcstate = retval;
+                break;
+            case 1:
+                retval = core_bench_matrix(&(res->mat), dtype, res->crc);
+                if (res->crcmatrix == 0)
+                    res->crcmatrix = retval;
+                break;
+            default:
+                retval = data;
+                break;
+        }
+        res->crc = crcu16(retval, res->crc);
+        retval &= 0x007f;
+        *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */
+        return retval;
+    }
+}
+/* Function: cmp_complex
+        Compare the data item in a list cell.
+
+        Can be used by mergesort.
+*/
+ee_s32
+cmp_complex(list_data *a, list_data *b, core_results *res)
+{
+    ee_s16 val1 = calc_func(&(a->data16), res);
+    ee_s16 val2 = calc_func(&(b->data16), res);
+    return val1 - val2;
+}
+
+/* Function: cmp_idx
+        Compare the idx item in a list cell, and regen the data.
+
+        Can be used by mergesort.
+*/
+ee_s32
+cmp_idx(list_data *a, list_data *b, core_results *res)
+{
+    if (res == NULL)
+    {
+        a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16 >> 8));
+        b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16 >> 8));
+    }
+    return a->idx - b->idx;
+}
+
+void
+copy_info(list_data *to, list_data *from)
+{
+    to->data16 = from->data16;
+    to->idx    = from->idx;
+}
+
+/* Benchmark for linked list:
+        - Try to find multiple data items.
+        - List sort
+        - Operate on data from list (crc)
+        - Single remove/reinsert
+        * At the end of this function, the list is back to original state
+*/
+ee_u16
+core_bench_list(core_results *res, ee_s16 finder_idx)
+{
+    ee_u16     retval = 0;
+    ee_u16     found = 0, missed = 0;
+    list_head *list     = res->list;
+    ee_s16     find_num = res->seed3;
+    list_head *this_find;
+    list_head *finder, *remover;
+    list_data  info;
+    ee_s16     i;
+
+    info.idx = finder_idx;
+    /* find <find_num> values in the list, and change the list each time
+     * (reverse and cache if value found) */
+    for (i = 0; i < find_num; i++)
+    {
+        info.data16 = (i & 0xff);
+        this_find   = core_list_find(list, &info);
+        list        = core_list_reverse(list);
+        if (this_find == NULL)
+        {
+            missed++;
+            retval += (list->next->info->data16 >> 8) & 1;
+        }
+        else
+        {
+            found++;
+            if (this_find->info->data16 & 0x1) /* use found value */
+                retval += (this_find->info->data16 >> 9) & 1;
+            /* and cache next item at the head of the list (if any) */
+            if (this_find->next != NULL)
+            {
+                finder          = this_find->next;
+                this_find->next = finder->next;
+                finder->next    = list->next;
+                list->next      = finder;
+            }
+        }
+        if (info.idx >= 0)
+            info.idx++;
+#if CORE_DEBUG
+        ee_printf("List find %d: [%d,%d,%d]\n", i, retval, missed, found);
+#endif
+    }
+    retval += found * 4 - missed;
+    /* sort the list by data content and remove one item*/
+    if (finder_idx > 0)
+        list = core_list_mergesort(list, cmp_complex, res);
+    remover = core_list_remove(list->next);
+    /* CRC data content of list from location of index N forward, and then undo
+     * remove */
+    finder = core_list_find(list, &info);
+    if (!finder)
+        finder = list->next;
+    while (finder)
+    {
+        retval = crc16(list->info->data16, retval);
+        finder = finder->next;
+    }
+#if CORE_DEBUG
+    ee_printf("List sort 1: %04x\n", retval);
+#endif
+    remover = core_list_undo_remove(remover, list->next);
+    /* sort the list by index, in effect returning the list to original state */
+    list = core_list_mergesort(list, cmp_idx, NULL);
+    /* CRC data content of list */
+    finder = list->next;
+    while (finder)
+    {
+        retval = crc16(list->info->data16, retval);
+        finder = finder->next;
+    }
+#if CORE_DEBUG
+    ee_printf("List sort 2: %04x\n", retval);
+#endif
+    return retval;
+}
+/* Function: core_list_init
+        Initialize list with data.
+
+        Parameters:
+        blksize - Size of memory to be initialized.
+        memblock - Pointer to memory block.
+        seed - 	Actual values chosen depend on the seed parameter.
+                The seed parameter MUST be supplied from a source that cannot be
+   determined at compile time
+
+        Returns:
+        Pointer to the head of the list.
+
+*/
+list_head *
+core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed)
+{
+    /* calculated pointers for the list */
+    ee_u32 per_item = 16 + sizeof(struct list_data_s);
+    ee_u32 size     = (blksize / per_item)
+                  - 2; /* to accomodate systems with 64b pointers, and make sure
+                          same code is executed, set max list elements */
+    list_head *memblock_end  = memblock + size;
+    list_data *datablock     = (list_data *)(memblock_end);
+    list_data *datablock_end = datablock + size;
+    /* some useful variables */
+    ee_u32     i;
+    list_head *finder, *list = memblock;
+    list_data  info;
+
+    /* create a fake items for the list head and tail */
+    list->next         = NULL;
+    list->info         = datablock;
+    list->info->idx    = 0x0000;
+    list->info->data16 = (ee_s16)0x8080;
+    memblock++;
+    datablock++;
+    info.idx    = 0x7fff;
+    info.data16 = (ee_s16)0xffff;
+    core_list_insert_new(
+        list, &info, &memblock, &datablock, memblock_end, datablock_end);
+
+    /* then insert size items */
+    for (i = 0; i < size; i++)
+    {
+        ee_u16 datpat = ((ee_u16)(seed ^ i) & 0xf);
+        ee_u16 dat
+            = (datpat << 3) | (i & 0x7); /* alternate between algorithms */
+        info.data16 = (dat << 8) | dat;  /* fill the data with actual data and
+                                            upper bits with rebuild value */
+        core_list_insert_new(
+            list, &info, &memblock, &datablock, memblock_end, datablock_end);
+    }
+    /* and now index the list so we know initial seed order of the list */
+    finder = list->next;
+    i      = 1;
+    while (finder->next != NULL)
+    {
+        if (i < size / 5) /* first 20% of the list in order */
+            finder->info->idx = i++;
+        else
+        {
+            ee_u16 pat = (ee_u16)(i++ ^ seed); /* get a pseudo random number */
+            finder->info->idx = 0x3fff
+                                & (((i & 0x07) << 8)
+                                   | pat); /* make sure the mixed items end up
+                                              after the ones in sequence */
+        }
+        finder = finder->next;
+    }
+    list = core_list_mergesort(list, cmp_idx, NULL);
+#if CORE_DEBUG
+    ee_printf("Initialized list:\n");
+    finder = list;
+    while (finder)
+    {
+        ee_printf(
+            "[%04x,%04x]", finder->info->idx, (ee_u16)finder->info->data16);
+        finder = finder->next;
+    }
+    ee_printf("\n");
+#endif
+    return list;
+}
+
+/* Function: core_list_insert
+        Insert an item to the list
+
+        Parameters:
+        insert_point - where to insert the item.
+        info - data for the cell.
+        memblock - pointer for the list header
+        datablock - pointer for the list data
+        memblock_end - end of region for list headers
+        datablock_end - end of region for list data
+
+        Returns:
+        Pointer to new item.
+*/
+list_head *
+core_list_insert_new(list_head * insert_point,
+                     list_data * info,
+                     list_head **memblock,
+                     list_data **datablock,
+                     list_head * memblock_end,
+                     list_data * datablock_end)
+{
+    list_head *newitem;
+
+    if ((*memblock + 1) >= memblock_end)
+        return NULL;
+    if ((*datablock + 1) >= datablock_end)
+        return NULL;
+
+    newitem = *memblock;
+    (*memblock)++;
+    newitem->next      = insert_point->next;
+    insert_point->next = newitem;
+
+    newitem->info = *datablock;
+    (*datablock)++;
+    copy_info(newitem->info, info);
+
+    return newitem;
+}
+
+/* Function: core_list_remove
+        Remove an item from the list.
+
+        Operation:
+        For a singly linked list, remove by copying the data from the next item
+        over to the current cell, and unlinking the next item.
+
+        Note:
+        since there is always a fake item at the end of the list, no need to
+   check for NULL.
+
+        Returns:
+        Removed item.
+*/
+list_head *
+core_list_remove(list_head *item)
+{
+    list_data *tmp;
+    list_head *ret = item->next;
+    /* swap data pointers */
+    tmp        = item->info;
+    item->info = ret->info;
+    ret->info  = tmp;
+    /* and eliminate item */
+    item->next = item->next->next;
+    ret->next  = NULL;
+    return ret;
+}
+
+/* Function: core_list_undo_remove
+        Undo a remove operation.
+
+        Operation:
+        Since we want each iteration of the benchmark to be exactly the same,
+        we need to be able to undo a remove.
+        Link the removed item back into the list, and switch the info items.
+
+        Parameters:
+        item_removed - Return value from the <core_list_remove>
+        item_modified - List item that was modified during <core_list_remove>
+
+        Returns:
+        The item that was linked back to the list.
+
+*/
+list_head *
+core_list_undo_remove(list_head *item_removed, list_head *item_modified)
+{
+    list_data *tmp;
+    /* swap data pointers */
+    tmp                 = item_removed->info;
+    item_removed->info  = item_modified->info;
+    item_modified->info = tmp;
+    /* and insert item */
+    item_removed->next  = item_modified->next;
+    item_modified->next = item_removed;
+    return item_removed;
+}
+
+/* Function: core_list_find
+        Find an item in the list
+
+        Operation:
+        Find an item by idx (if not 0) or specific data value
+
+        Parameters:
+        list - list head
+        info - idx or data to find
+
+        Returns:
+        Found item, or NULL if not found.
+*/
+list_head *
+core_list_find(list_head *list, list_data *info)
+{
+    if (info->idx >= 0)
+    {
+        while (list && (list->info->idx != info->idx))
+            list = list->next;
+        return list;
+    }
+    else
+    {
+        while (list && ((list->info->data16 & 0xff) != info->data16))
+            list = list->next;
+        return list;
+    }
+}
+/* Function: core_list_reverse
+        Reverse a list
+
+        Operation:
+        Rearrange the pointers so the list is reversed.
+
+        Parameters:
+        list - list head
+        info - idx or data to find
+
+        Returns:
+        Found item, or NULL if not found.
+*/
+
+list_head *
+core_list_reverse(list_head *list)
+{
+    list_head *next = NULL, *tmp;
+    while (list)
+    {
+        tmp        = list->next;
+        list->next = next;
+        next       = list;
+        list       = tmp;
+    }
+    return next;
+}
+/* Function: core_list_mergesort
+        Sort the list in place without recursion.
+
+        Description:
+        Use mergesort, as for linked list this is a realistic solution.
+        Also, since this is aimed at embedded, care was taken to use iterative
+   rather then recursive algorithm. The sort can either return the list to
+   original order (by idx) , or use the data item to invoke other other
+   algorithms and change the order of the list.
+
+        Parameters:
+        list - list to be sorted.
+        cmp - cmp function to use
+
+        Returns:
+        New head of the list.
+
+        Note:
+        We have a special header for the list that will always be first,
+        but the algorithm could theoretically modify where the list starts.
+
+ */
+list_head *
+core_list_mergesort(list_head *list, list_cmp cmp, core_results *res)
+{
+    list_head *p, *q, *e, *tail;
+    ee_s32     insize, nmerges, psize, qsize, i;
+
+    insize = 1;
+
+    while (1)
+    {
+        p    = list;
+        list = NULL;
+        tail = NULL;
+
+        nmerges = 0; /* count number of merges we do in this pass */
+
+        while (p)
+        {
+            nmerges++; /* there exists a merge to be done */
+            /* step `insize' places along from p */
+            q     = p;
+            psize = 0;
+            for (i = 0; i < insize; i++)
+            {
+                psize++;
+                q = q->next;
+                if (!q)
+                    break;
+            }
+
+            /* if q hasn't fallen off end, we have two lists to merge */
+            qsize = insize;
+
+            /* now we have two lists; merge them */
+            while (psize > 0 || (qsize > 0 && q))
+            {
+
+                /* decide whether next element of merge comes from p or q */
+                if (psize == 0)
+                {
+                    /* p is empty; e must come from q. */
+                    e = q;
+                    q = q->next;
+                    qsize--;
+                }
+                else if (qsize == 0 || !q)
+                {
+                    /* q is empty; e must come from p. */
+                    e = p;
+                    p = p->next;
+                    psize--;
+                }
+                else if (cmp(p->info, q->info, res) <= 0)
+                {
+                    /* First element of p is lower (or same); e must come from
+                     * p. */
+                    e = p;
+                    p = p->next;
+                    psize--;
+                }
+                else
+                {
+                    /* First element of q is lower; e must come from q. */
+                    e = q;
+                    q = q->next;
+                    qsize--;
+                }
+
+                /* add the next element to the merged list */
+                if (tail)
+                {
+                    tail->next = e;
+                }
+                else
+                {
+                    list = e;
+                }
+                tail = e;
+            }
+
+            /* now p has stepped `insize' places along, and q has too */
+            p = q;
+        }
+
+        tail->next = NULL;
+
+        /* If we have done only one merge, we're finished. */
+        if (nmerges <= 1) /* allow for nmerges==0, the empty list case */
+            return list;
+
+        /* Otherwise repeat, merging lists twice the size */
+        insize *= 2;
+    }
+#if COMPILER_REQUIRES_SORT_RETURN
+    return list;
+#endif
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_matrix.c b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_matrix.c
new file mode 100644
index 00000000..9c7901c3
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_matrix.c
@@ -0,0 +1,376 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+#include "coremark.h"
+/*
+Topic: Description
+        Matrix manipulation benchmark
+
+        This very simple algorithm forms the basis of many more complex
+algorithms.
+
+        The tight inner loop is the focus of many optimizations (compiler as
+well as hardware based) and is thus relevant for embedded processing.
+
+        The total available data space will be divided to 3 parts:
+        NxN Matrix A - initialized with small values (upper 3/4 of the bits all
+zero). NxN Matrix B - initialized with medium values (upper half of the bits all
+zero). NxN Matrix C - used for the result.
+
+        The actual values for A and B must be derived based on input that is not
+available at compile time.
+*/
+ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val);
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval);
+void   matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val);
+void   matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void   matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void   matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void   matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val);
+
+#define matrix_test_next(x)      (x + 1)
+#define matrix_clip(x, y)        ((y) ? (x)&0x0ff : (x)&0x0ffff)
+#define matrix_big(x)            (0xf000 | (x))
+#define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff << (to))))
+
+#if CORE_DEBUG
+void
+printmat(MATDAT *A, ee_u32 N, char *name)
+{
+    ee_u32 i, j;
+    ee_printf("Matrix %s [%dx%d]:\n", name, N, N);
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            if (j != 0)
+                ee_printf(",");
+            ee_printf("%d", A[i * N + j]);
+        }
+        ee_printf("\n");
+    }
+}
+void
+printmatC(MATRES *C, ee_u32 N, char *name)
+{
+    ee_u32 i, j;
+    ee_printf("Matrix %s [%dx%d]:\n", name, N, N);
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            if (j != 0)
+                ee_printf(",");
+            ee_printf("%d", C[i * N + j]);
+        }
+        ee_printf("\n");
+    }
+}
+#endif
+/* Function: core_bench_matrix
+        Benchmark function
+
+        Iterate <matrix_test> N times,
+        changing the matrix values slightly by a constant amount each time.
+*/
+ee_u16
+core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc)
+{
+    ee_u32  N   = p->N;
+    MATRES *C   = p->C;
+    MATDAT *A   = p->A;
+    MATDAT *B   = p->B;
+    MATDAT  val = (MATDAT)seed;
+
+    crc = crc16(matrix_test(N, C, A, B, val), crc);
+
+    return crc;
+}
+
+/* Function: matrix_test
+        Perform matrix manipulation.
+
+        Parameters:
+        N - Dimensions of the matrix.
+        C - memory for result matrix.
+        A - input matrix
+        B - operator matrix (not changed during operations)
+
+        Returns:
+        A CRC value that captures all results calculated in the function.
+        In particular, crc of the value calculated on the result matrix
+        after each step by <matrix_sum>.
+
+        Operation:
+
+        1 - Add a constant value to all elements of a matrix.
+        2 - Multiply a matrix by a constant.
+        3 - Multiply a matrix by a vector.
+        4 - Multiply a matrix by a matrix.
+        5 - Add a constant value to all elements of a matrix.
+
+        After the last step, matrix A is back to original contents.
+*/
+ee_s16
+matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val)
+{
+    ee_u16 crc     = 0;
+    MATDAT clipval = matrix_big(val);
+
+    matrix_add_const(N, A, val); /* make sure data changes  */
+#if CORE_DEBUG
+    printmat(A, N, "matrix_add_const");
+#endif
+    matrix_mul_const(N, C, A, val);
+    crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+    printmatC(C, N, "matrix_mul_const");
+#endif
+    matrix_mul_vect(N, C, A, B);
+    crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+    printmatC(C, N, "matrix_mul_vect");
+#endif
+    matrix_mul_matrix(N, C, A, B);
+    crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+    printmatC(C, N, "matrix_mul_matrix");
+#endif
+    matrix_mul_matrix_bitextract(N, C, A, B);
+    crc = crc16(matrix_sum(N, C, clipval), crc);
+#if CORE_DEBUG
+    printmatC(C, N, "matrix_mul_matrix_bitextract");
+#endif
+
+    matrix_add_const(N, A, -val); /* return matrix to initial value */
+    return crc;
+}
+
+/* Function : matrix_init
+        Initialize the memory block for matrix benchmarking.
+
+        Parameters:
+        blksize - Size of memory to be initialized.
+        memblk - Pointer to memory block.
+        seed - Actual values chosen depend on the seed parameter.
+        p - pointers to <mat_params> containing initialized matrixes.
+
+        Returns:
+        Matrix dimensions.
+
+        Note:
+        The seed parameter MUST be supplied from a source that cannot be
+   determined at compile time
+*/
+ee_u32
+core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p)
+{
+    ee_u32  N = 0;
+    MATDAT *A;
+    MATDAT *B;
+    ee_s32  order = 1;
+    MATDAT  val;
+    ee_u32  i = 0, j = 0;
+    if (seed == 0)
+        seed = 1;
+    while (j < blksize)
+    {
+        i++;
+        j = i * i * 2 * 4;
+    }
+    N = i - 1;
+    A = (MATDAT *)align_mem(memblk);
+    B = A + N * N;
+
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            seed         = ((order * seed) % 65536);
+            val          = (seed + order);
+            val          = matrix_clip(val, 0);
+            B[i * N + j] = val;
+            val          = (val + order);
+            val          = matrix_clip(val, 1);
+            A[i * N + j] = val;
+            order++;
+        }
+    }
+
+    p->A = A;
+    p->B = B;
+    p->C = (MATRES *)align_mem(B + N * N);
+    p->N = N;
+#if CORE_DEBUG
+    printmat(A, N, "A");
+    printmat(B, N, "B");
+#endif
+    return N;
+}
+
+/* Function: matrix_sum
+        Calculate a function that depends on the values of elements in the
+   matrix.
+
+        For each element, accumulate into a temporary variable.
+
+        As long as this value is under the parameter clipval,
+        add 1 to the result if the element is bigger then the previous.
+
+        Otherwise, reset the accumulator and add 10 to the result.
+*/
+ee_s16
+matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval)
+{
+    MATRES tmp = 0, prev = 0, cur = 0;
+    ee_s16 ret = 0;
+    ee_u32 i, j;
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            cur = C[i * N + j];
+            tmp += cur;
+            if (tmp > clipval)
+            {
+                ret += 10;
+                tmp = 0;
+            }
+            else
+            {
+                ret += (cur > prev) ? 1 : 0;
+            }
+            prev = cur;
+        }
+    }
+    return ret;
+}
+
+/* Function: matrix_mul_const
+        Multiply a matrix by a constant.
+        This could be used as a scaler for instance.
+*/
+void
+matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val)
+{
+    ee_u32 i, j;
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            C[i * N + j] = (MATRES)A[i * N + j] * (MATRES)val;
+        }
+    }
+}
+
+/* Function: matrix_add_const
+        Add a constant value to all elements of a matrix.
+*/
+void
+matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val)
+{
+    ee_u32 i, j;
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            A[i * N + j] += val;
+        }
+    }
+}
+
+/* Function: matrix_mul_vect
+        Multiply a matrix by a vector.
+        This is common in many simple filters (e.g. fir where a vector of
+   coefficients is applied to the matrix.)
+*/
+void
+matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B)
+{
+    ee_u32 i, j;
+    for (i = 0; i < N; i++)
+    {
+        C[i] = 0;
+        for (j = 0; j < N; j++)
+        {
+            C[i] += (MATRES)A[i * N + j] * (MATRES)B[j];
+        }
+    }
+}
+
+/* Function: matrix_mul_matrix
+        Multiply a matrix by a matrix.
+        Basic code is used in many algorithms, mostly with minor changes such as
+   scaling.
+*/
+void
+matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B)
+{
+    ee_u32 i, j, k;
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            C[i * N + j] = 0;
+            for (k = 0; k < N; k++)
+            {
+                C[i * N + j] += (MATRES)A[i * N + k] * (MATRES)B[k * N + j];
+            }
+        }
+    }
+}
+
+/* Function: matrix_mul_matrix_bitextract
+        Multiply a matrix by a matrix, and extract some bits from the result.
+        Basic code is used in many algorithms, mostly with minor changes such as
+   scaling.
+*/
+void
+matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B)
+{
+    ee_u32 i, j, k;
+    for (i = 0; i < N; i++)
+    {
+        for (j = 0; j < N; j++)
+        {
+            C[i * N + j] = 0;
+            for (k = 0; k < N; k++)
+            {
+                MATRES tmp = (MATRES)A[i * N + k] * (MATRES)B[k * N + j];
+                C[i * N + j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5, 7);
+            }
+        }
+    }
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.c b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.c
new file mode 100644
index 00000000..3b40763c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.c
@@ -0,0 +1,104 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+#include "csr.h"
+#include "x-heep.h"
+
+#include "coremark.h"
+
+ee_u32 default_num_contexts = 1;
+
+static CORETIMETYPE start_time_val, stop_time_val;
+
+#if VALIDATION_RUN
+volatile ee_s32 seed1_volatile = 0x3415;
+volatile ee_s32 seed2_volatile = 0x3415;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PERFORMANCE_RUN
+volatile ee_s32 seed1_volatile = 0x0;
+volatile ee_s32 seed2_volatile = 0x0;
+volatile ee_s32 seed3_volatile = 0x66;
+#endif
+#if PROFILE_RUN
+volatile ee_s32 seed1_volatile = 0x8;
+volatile ee_s32 seed2_volatile = 0x8;
+volatile ee_s32 seed3_volatile = 0x8;
+#endif
+volatile ee_s32 seed4_volatile = ITERATIONS;
+volatile ee_s32 seed5_volatile = 0;
+
+void
+portable_init(core_portable *p, int *argc, char *argv[])
+{
+    // Don't need to do anything here atm.
+    (void)p;
+    (void)argc;
+    (void)argv;
+}
+
+void
+portable_fini(core_portable *p)
+{
+    // Don't need to do anything here atm.
+    (void)p;
+}
+
+void
+start_time(void)
+{
+    // Enable mcycle counter and read value
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+
+    CSR_READ(CSR_REG_MCYCLE, &start_time_val);
+}
+
+void
+stop_time(void)
+{
+    CSR_READ(CSR_REG_MCYCLE, &stop_time_val);
+}
+
+CORE_TICKS
+get_time(void)
+{
+    return (stop_time_val - start_time_val);
+}
+
+secs_ret
+time_in_secs(CORE_TICKS ticks)
+{
+    return ticks*1E-6;  // Normalized to 1 MHz clock period
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.h b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.h
new file mode 100644
index 00000000..5a15066a
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_portme.h
@@ -0,0 +1,93 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+#include <stddef.h>
+#include <stdio.h>
+
+typedef signed short   ee_s16;
+typedef unsigned short ee_u16;
+typedef signed int     ee_s32;
+typedef double         ee_f32;
+typedef unsigned char  ee_u8;
+typedef unsigned int   ee_u32;
+typedef ee_u32         ee_ptr_int;
+typedef size_t         ee_size_t;
+
+typedef ee_u32 CORE_TICKS;
+
+typedef struct CORE_PORTABLE_S
+{
+    ee_u8 portable_id;
+} core_portable;
+
+#ifndef MULTITHREAD
+#define MULTITHREAD 1  // 1 means single-core
+#define USE_PTHREAD 0
+#define USE_FORK    0
+#define USE_SOCKET  0
+#endif
+
+#ifndef COMPILER_VERSION
+#ifdef __GNUC__
+#define COMPILER_VERSION "GCC"__VERSION__
+#else
+#define COMPILER_VERSION "Undefined non-gcc compiler used"
+#endif
+#endif
+
+#ifndef COMPILER_FLAGS
+#define COMPILER_FLAGS FLAGS_STR
+#endif
+
+#ifndef MEM_LOCATION
+#define MEM_LOCATION ""
+#endif
+
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 1
+#endif
+
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3))
+
+#define CORETIMETYPE ee_u32
+
+extern ee_u32 default_num_contexts;
+
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_state.c b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_state.c
new file mode 100644
index 00000000..b5c3d461
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_state.c
@@ -0,0 +1,347 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+#include "coremark.h"
+/* local functions */
+enum CORE_STATE core_state_transition(ee_u8 **instr, ee_u32 *transition_count);
+
+/*
+Topic: Description
+        Simple state machines like this one are used in many embedded products.
+
+        For more complex state machines, sometimes a state transition table
+implementation is used instead, trading speed of direct coding for ease of
+maintenance.
+
+        Since the main goal of using a state machine in CoreMark is to excercise
+the switch/if behaviour, we are using a small moore machine.
+
+        In particular, this machine tests type of string input,
+        trying to determine whether the input is a number or something else.
+        (see core_state.png).
+*/
+
+/* Function: core_bench_state
+        Benchmark function
+
+        Go over the input twice, once direct, and once after introducing some
+   corruption.
+*/
+ee_u16
+core_bench_state(ee_u32 blksize,
+                 ee_u8 *memblock,
+                 ee_s16 seed1,
+                 ee_s16 seed2,
+                 ee_s16 step,
+                 ee_u16 crc)
+{
+    ee_u32 final_counts[NUM_CORE_STATES];
+    ee_u32 track_counts[NUM_CORE_STATES];
+    ee_u8 *p = memblock;
+    ee_u32 i;
+
+#if CORE_DEBUG
+    ee_printf("State Bench: %d,%d,%d,%04x\n", seed1, seed2, step, crc);
+#endif
+    for (i = 0; i < NUM_CORE_STATES; i++)
+    {
+        final_counts[i] = track_counts[i] = 0;
+    }
+    /* run the state machine over the input */
+    while (*p != 0)
+    {
+        enum CORE_STATE fstate = core_state_transition(&p, track_counts);
+        final_counts[fstate]++;
+#if CORE_DEBUG
+        ee_printf("%d,", fstate);
+    }
+    ee_printf("\n");
+#else
+    }
+#endif
+    p = memblock;
+    while (p < (memblock + blksize))
+    { /* insert some corruption */
+        if (*p != ',')
+            *p ^= (ee_u8)seed1;
+        p += step;
+    }
+    p = memblock;
+    /* run the state machine over the input again */
+    while (*p != 0)
+    {
+        enum CORE_STATE fstate = core_state_transition(&p, track_counts);
+        final_counts[fstate]++;
+#if CORE_DEBUG
+        ee_printf("%d,", fstate);
+    }
+    ee_printf("\n");
+#else
+    }
+#endif
+    p = memblock;
+    while (p < (memblock + blksize))
+    { /* undo corruption is seed1 and seed2 are equal */
+        if (*p != ',')
+            *p ^= (ee_u8)seed2;
+        p += step;
+    }
+    /* end timing */
+    for (i = 0; i < NUM_CORE_STATES; i++)
+    {
+        crc = crcu32(final_counts[i], crc);
+        crc = crcu32(track_counts[i], crc);
+    }
+    return crc;
+}
+
+/* Default initialization patterns */
+static ee_u8 *intpat[4]
+    = { (ee_u8 *)"5012", (ee_u8 *)"1234", (ee_u8 *)"-874", (ee_u8 *)"+122" };
+static ee_u8 *floatpat[4] = { (ee_u8 *)"35.54400",
+                              (ee_u8 *)".1234500",
+                              (ee_u8 *)"-110.700",
+                              (ee_u8 *)"+0.64400" };
+static ee_u8 *scipat[4]   = { (ee_u8 *)"5.500e+3",
+                            (ee_u8 *)"-.123e-2",
+                            (ee_u8 *)"-87e+832",
+                            (ee_u8 *)"+0.6e-12" };
+static ee_u8 *errpat[4]   = { (ee_u8 *)"T0.3e-1F",
+                            (ee_u8 *)"-T.T++Tq",
+                            (ee_u8 *)"1T3.4e4z",
+                            (ee_u8 *)"34.0e-T^" };
+
+/* Function: core_init_state
+        Initialize the input data for the state machine.
+
+        Populate the input with several predetermined strings, interspersed.
+        Actual patterns chosen depend on the seed parameter.
+
+        Note:
+        The seed parameter MUST be supplied from a source that cannot be
+   determined at compile time
+*/
+void
+core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p)
+{
+    ee_u32 total = 0, next = 0, i;
+    ee_u8 *buf = 0;
+#if CORE_DEBUG
+    ee_u8 *start = p;
+    ee_printf("State: %d,%d\n", size, seed);
+#endif
+    size--;
+    next = 0;
+    while ((total + next + 1) < size)
+    {
+        if (next > 0)
+        {
+            for (i = 0; i < next; i++)
+                *(p + total + i) = buf[i];
+            *(p + total + i) = ',';
+            total += next + 1;
+        }
+        seed++;
+        switch (seed & 0x7)
+        {
+            case 0: /* int */
+            case 1: /* int */
+            case 2: /* int */
+                buf  = intpat[(seed >> 3) & 0x3];
+                next = 4;
+                break;
+            case 3: /* float */
+            case 4: /* float */
+                buf  = floatpat[(seed >> 3) & 0x3];
+                next = 8;
+                break;
+            case 5: /* scientific */
+            case 6: /* scientific */
+                buf  = scipat[(seed >> 3) & 0x3];
+                next = 8;
+                break;
+            case 7: /* invalid */
+                buf  = errpat[(seed >> 3) & 0x3];
+                next = 8;
+                break;
+            default: /* Never happen, just to make some compilers happy */
+                break;
+        }
+    }
+    size++;
+    while (total < size)
+    { /* fill the rest with 0 */
+        *(p + total) = 0;
+        total++;
+    }
+#if CORE_DEBUG
+    ee_printf("State Input: %s\n", start);
+#endif
+}
+
+static ee_u8
+ee_isdigit(ee_u8 c)
+{
+    ee_u8 retval;
+    retval = ((c >= '0') & (c <= '9')) ? 1 : 0;
+    return retval;
+}
+
+/* Function: core_state_transition
+        Actual state machine.
+
+        The state machine will continue scanning until either:
+        1 - an invalid input is detcted.
+        2 - a valid number has been detected.
+
+        The input pointer is updated to point to the end of the token, and the
+   end state is returned (either specific format determined or invalid).
+*/
+
+enum CORE_STATE
+core_state_transition(ee_u8 **instr, ee_u32 *transition_count)
+{
+    ee_u8 *         str = *instr;
+    ee_u8           NEXT_SYMBOL;
+    enum CORE_STATE state = CORE_START;
+    for (; *str && state != CORE_INVALID; str++)
+    {
+        NEXT_SYMBOL = *str;
+        if (NEXT_SYMBOL == ',') /* end of this input */
+        {
+            str++;
+            break;
+        }
+        switch (state)
+        {
+            case CORE_START:
+                if (ee_isdigit(NEXT_SYMBOL))
+                {
+                    state = CORE_INT;
+                }
+                else if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-')
+                {
+                    state = CORE_S1;
+                }
+                else if (NEXT_SYMBOL == '.')
+                {
+                    state = CORE_FLOAT;
+                }
+                else
+                {
+                    state = CORE_INVALID;
+                    transition_count[CORE_INVALID]++;
+                }
+                transition_count[CORE_START]++;
+                break;
+            case CORE_S1:
+                if (ee_isdigit(NEXT_SYMBOL))
+                {
+                    state = CORE_INT;
+                    transition_count[CORE_S1]++;
+                }
+                else if (NEXT_SYMBOL == '.')
+                {
+                    state = CORE_FLOAT;
+                    transition_count[CORE_S1]++;
+                }
+                else
+                {
+                    state = CORE_INVALID;
+                    transition_count[CORE_S1]++;
+                }
+                break;
+            case CORE_INT:
+                if (NEXT_SYMBOL == '.')
+                {
+                    state = CORE_FLOAT;
+                    transition_count[CORE_INT]++;
+                }
+                else if (!ee_isdigit(NEXT_SYMBOL))
+                {
+                    state = CORE_INVALID;
+                    transition_count[CORE_INT]++;
+                }
+                break;
+            case CORE_FLOAT:
+                if (NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e')
+                {
+                    state = CORE_S2;
+                    transition_count[CORE_FLOAT]++;
+                }
+                else if (!ee_isdigit(NEXT_SYMBOL))
+                {
+                    state = CORE_INVALID;
+                    transition_count[CORE_FLOAT]++;
+                }
+                break;
+            case CORE_S2:
+                if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-')
+                {
+                    state = CORE_EXPONENT;
+                    transition_count[CORE_S2]++;
+                }
+                else
+                {
+                    state = CORE_INVALID;
+                    transition_count[CORE_S2]++;
+                }
+                break;
+            case CORE_EXPONENT:
+                if (ee_isdigit(NEXT_SYMBOL))
+                {
+                    state = CORE_SCIENTIFIC;
+                    transition_count[CORE_EXPONENT]++;
+                }
+                else
+                {
+                    state = CORE_INVALID;
+                    transition_count[CORE_EXPONENT]++;
+                }
+                break;
+            case CORE_SCIENTIFIC:
+                if (!ee_isdigit(NEXT_SYMBOL))
+                {
+                    state = CORE_INVALID;
+                    transition_count[CORE_INVALID]++;
+                }
+                break;
+            default:
+                break;
+        }
+    }
+    *instr = str;
+    return state;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_util.c b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_util.c
new file mode 100644
index 00000000..0544e621
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/core_util.c
@@ -0,0 +1,266 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+#include "coremark.h"
+/* Function: get_seed
+        Get a values that cannot be determined at compile time.
+
+        Since different embedded systems and compilers are used, 3 different
+   methods are provided: 1 - Using a volatile variable. This method is only
+   valid if the compiler is forced to generate code that reads the value of a
+   volatile variable from memory at run time. Please note, if using this method,
+   you would need to modify core_portme.c to generate training profile. 2 -
+   Command line arguments. This is the preferred method if command line
+   arguments are supported. 3 - System function. If none of the first 2 methods
+   is available on the platform, a system function which is not a stub can be
+   used.
+
+        e.g. read the value on GPIO pins connected to switches, or invoke
+   special simulator functions.
+*/
+#if (SEED_METHOD == SEED_VOLATILE)
+extern volatile ee_s32 seed1_volatile;
+extern volatile ee_s32 seed2_volatile;
+extern volatile ee_s32 seed3_volatile;
+extern volatile ee_s32 seed4_volatile;
+extern volatile ee_s32 seed5_volatile;
+ee_s32
+get_seed_32(int i)
+{
+    ee_s32 retval;
+    switch (i)
+    {
+        case 1:
+            retval = seed1_volatile;
+            break;
+        case 2:
+            retval = seed2_volatile;
+            break;
+        case 3:
+            retval = seed3_volatile;
+            break;
+        case 4:
+            retval = seed4_volatile;
+            break;
+        case 5:
+            retval = seed5_volatile;
+            break;
+        default:
+            retval = 0;
+            break;
+    }
+    return retval;
+}
+#elif (SEED_METHOD == SEED_ARG)
+ee_s32
+parseval(char *valstring)
+{
+    ee_s32 retval  = 0;
+    ee_s32 neg     = 1;
+    int    hexmode = 0;
+    if (*valstring == '-')
+    {
+        neg = -1;
+        valstring++;
+    }
+    if ((valstring[0] == '0') && (valstring[1] == 'x'))
+    {
+        hexmode = 1;
+        valstring += 2;
+    }
+    /* first look for digits */
+    if (hexmode)
+    {
+        while (((*valstring >= '0') && (*valstring <= '9'))
+               || ((*valstring >= 'a') && (*valstring <= 'f')))
+        {
+            ee_s32 digit = *valstring - '0';
+            if (digit > 9)
+                digit = 10 + *valstring - 'a';
+            retval *= 16;
+            retval += digit;
+            valstring++;
+        }
+    }
+    else
+    {
+        while ((*valstring >= '0') && (*valstring <= '9'))
+        {
+            ee_s32 digit = *valstring - '0';
+            retval *= 10;
+            retval += digit;
+            valstring++;
+        }
+    }
+    /* now add qualifiers */
+    if (*valstring == 'K')
+        retval *= 1024;
+    if (*valstring == 'M')
+        retval *= 1024 * 1024;
+
+    retval *= neg;
+    return retval;
+}
+
+ee_s32
+get_seed_args(int i, int argc, char *argv[])
+{
+    if (argc > i)
+        return parseval(argv[i]);
+    return 0;
+}
+
+#elif (SEED_METHOD == SEED_FUNC)
+/* If using OS based function, you must define and implement the functions below
+ * in core_portme.h and core_portme.c ! */
+ee_s32
+get_seed_32(int i)
+{
+    ee_s32 retval;
+    switch (i)
+    {
+        case 1:
+            retval = portme_sys1();
+            break;
+        case 2:
+            retval = portme_sys2();
+            break;
+        case 3:
+            retval = portme_sys3();
+            break;
+        case 4:
+            retval = portme_sys4();
+            break;
+        case 5:
+            retval = portme_sys5();
+            break;
+        default:
+            retval = 0;
+            break;
+    }
+    return retval;
+}
+#endif
+
+/* Function: crc*
+        Service functions to calculate 16b CRC code.
+
+*/
+ee_u16
+crcu8(ee_u8 data, ee_u16 crc)
+{
+    ee_u8 i = 0, x16 = 0, carry = 0;
+
+    for (i = 0; i < 8; i++)
+    {
+        x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1));
+        data >>= 1;
+
+        if (x16 == 1)
+        {
+            crc ^= 0x4002;
+            carry = 1;
+        }
+        else
+            carry = 0;
+        crc >>= 1;
+        if (carry)
+            crc |= 0x8000;
+        else
+            crc &= 0x7fff;
+    }
+    return crc;
+}
+ee_u16
+crcu16(ee_u16 newval, ee_u16 crc)
+{
+    crc = crcu8((ee_u8)(newval), crc);
+    crc = crcu8((ee_u8)((newval) >> 8), crc);
+    return crc;
+}
+ee_u16
+crcu32(ee_u32 newval, ee_u16 crc)
+{
+    crc = crc16((ee_s16)newval, crc);
+    crc = crc16((ee_s16)(newval >> 16), crc);
+    return crc;
+}
+ee_u16
+crc16(ee_s16 newval, ee_u16 crc)
+{
+    return crcu16((ee_u16)newval, crc);
+}
+
+ee_u8
+check_data_types()
+{
+    ee_u8 retval = 0;
+    if (sizeof(ee_u8) != 1)
+    {
+        ee_printf("ERROR: ee_u8 is not an 8b datatype!\n");
+        retval++;
+    }
+    if (sizeof(ee_u16) != 2)
+    {
+        ee_printf("ERROR: ee_u16 is not a 16b datatype!\n");
+        retval++;
+    }
+    if (sizeof(ee_s16) != 2)
+    {
+        ee_printf("ERROR: ee_s16 is not a 16b datatype!\n");
+        retval++;
+    }
+    if (sizeof(ee_s32) != 4)
+    {
+        ee_printf("ERROR: ee_s32 is not a 32b datatype!\n");
+        retval++;
+    }
+    if (sizeof(ee_u32) != 4)
+    {
+        ee_printf("ERROR: ee_u32 is not a 32b datatype!\n");
+        retval++;
+    }
+    if (sizeof(ee_ptr_int) != sizeof(int *))
+    {
+        ee_printf(
+            "ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n");
+        retval++;
+    }
+    if (retval > 0)
+    {
+        ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n");
+    }
+    return retval;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h
new file mode 100644
index 00000000..1501da49
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h
@@ -0,0 +1,211 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+/* Topic: Description
+        This file contains  declarations of the various benchmark functions.
+*/
+
+/* Configuration: TOTAL_DATA_SIZE
+        Define total size for data algorithms will operate on
+*/
+#ifndef TOTAL_DATA_SIZE
+#define TOTAL_DATA_SIZE 2 * 1000
+#endif
+
+#define SEED_ARG      0
+#define SEED_FUNC     1
+#define SEED_VOLATILE 2
+
+#define MEM_STATIC 0
+#define MEM_MALLOC 1
+#define MEM_STACK  2
+
+#include "core_portme.h"
+
+#if HAS_STDIO
+#include <stdio.h>
+#endif
+#if HAS_PRINTF
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define ee_printf(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+    #define ee_printf(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define ee_printf printf
+#endif
+
+#endif
+
+/* Actual benchmark execution in iterate */
+void *iterate(void *pres);
+
+/* Typedef: secs_ret
+        For machines that have floating point support, get number of seconds as
+   a double. Otherwise an unsigned int.
+*/
+#if HAS_FLOAT
+typedef double secs_ret;
+#else
+typedef ee_u32 secs_ret;
+#endif
+
+#if MAIN_HAS_NORETURN
+#define MAIN_RETURN_VAL
+#define MAIN_RETURN_TYPE void
+#else
+#define MAIN_RETURN_VAL  0
+#define MAIN_RETURN_TYPE int
+#endif
+
+void       start_time(void);
+void       stop_time(void);
+CORE_TICKS get_time(void);
+secs_ret   time_in_secs(CORE_TICKS ticks);
+
+/* Misc useful functions */
+ee_u16 crcu8(ee_u8 data, ee_u16 crc);
+ee_u16 crc16(ee_s16 newval, ee_u16 crc);
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc);
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc);
+ee_u8  check_data_types(void);
+void * portable_malloc(ee_size_t size);
+void   portable_free(void *p);
+ee_s32 parseval(char *valstring);
+
+/* Algorithm IDS */
+#define ID_LIST             (1 << 0)
+#define ID_MATRIX           (1 << 1)
+#define ID_STATE            (1 << 2)
+#define ALL_ALGORITHMS_MASK (ID_LIST | ID_MATRIX | ID_STATE)
+#define NUM_ALGORITHMS      3
+
+/* list data structures */
+typedef struct list_data_s
+{
+    ee_s16 data16;
+    ee_s16 idx;
+} list_data;
+
+typedef struct list_head_s
+{
+    struct list_head_s *next;
+    struct list_data_s *info;
+} list_head;
+
+/*matrix benchmark related stuff */
+#define MATDAT_INT 1
+#if MATDAT_INT
+typedef ee_s16 MATDAT;
+typedef ee_s32 MATRES;
+#else
+typedef ee_f16 MATDAT;
+typedef ee_f32 MATRES;
+#endif
+
+typedef struct MAT_PARAMS_S
+{
+    int     N;
+    MATDAT *A;
+    MATDAT *B;
+    MATRES *C;
+} mat_params;
+
+/* state machine related stuff */
+/* List of all the possible states for the FSM */
+typedef enum CORE_STATE
+{
+    CORE_START = 0,
+    CORE_INVALID,
+    CORE_S1,
+    CORE_S2,
+    CORE_INT,
+    CORE_FLOAT,
+    CORE_EXPONENT,
+    CORE_SCIENTIFIC,
+    NUM_CORE_STATES
+} core_state_e;
+
+/* Helper structure to hold results */
+typedef struct RESULTS_S
+{
+    /* inputs */
+    ee_s16              seed1;       /* Initializing seed */
+    ee_s16              seed2;       /* Initializing seed */
+    ee_s16              seed3;       /* Initializing seed */
+    void *              memblock[4]; /* Pointer to safe memory location */
+    ee_u32              size;        /* Size of the data */
+    ee_u32              iterations;  /* Number of iterations to execute */
+    ee_u32              execs;       /* Bitmask of operations to execute */
+    struct list_head_s *list;
+    mat_params          mat;
+    /* outputs */
+    ee_u16 crc;
+    ee_u16 crclist;
+    ee_u16 crcmatrix;
+    ee_u16 crcstate;
+    ee_s16 err;
+    /* ultithread specific */
+    core_portable port;
+} core_results;
+
+/* Multicore execution handling */
+#if (MULTITHREAD > 1)
+ee_u8 core_start_parallel(core_results *res);
+ee_u8 core_stop_parallel(core_results *res);
+#endif
+
+/* list benchmark functions */
+list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed);
+ee_u16     core_bench_list(core_results *res, ee_s16 finder_idx);
+
+/* state benchmark functions */
+void   core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p);
+ee_u16 core_bench_state(ee_u32 blksize,
+                        ee_u8 *memblock,
+                        ee_s16 seed1,
+                        ee_s16 seed2,
+                        ee_s16 step,
+                        ee_u16 crc);
+
+/* matrix benchmark functions */
+ee_u32 core_init_matrix(ee_u32      blksize,
+                        void *      memblk,
+                        ee_s32      seed,
+                        mat_params *p);
+ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc);
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/main.c
new file mode 100644
index 00000000..12136ada
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/main.c
@@ -0,0 +1,459 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+// Copyright 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
+//
+// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     https://solderpad.org/licenses/
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier:Apache-2.0 WITH SHL-2.0
+
+/* File: core_main.c
+        This file contains the framework to acquire a block of memory, seed
+   initial parameters, tun t he benchmark and report the results.
+*/
+#include "coremark.h"
+
+/* Function: iterate
+        Run the benchmark for a specified number of iterations.
+
+        Operation:
+        For each type of benchmarked algorithm:
+                a - Initialize the data block for the algorithm.
+                b - Execute the algorithm N times.
+
+        Returns:
+        NULL.
+*/
+static ee_u16 list_known_crc[]   = { (ee_u16)0xd4b0,
+                                   (ee_u16)0x3340,
+                                   (ee_u16)0x6a79,
+                                   (ee_u16)0xe714,
+                                   (ee_u16)0xe3c1 };
+static ee_u16 matrix_known_crc[] = { (ee_u16)0xbe52,
+                                     (ee_u16)0x1199,
+                                     (ee_u16)0x5608,
+                                     (ee_u16)0x1fd7,
+                                     (ee_u16)0x0747 };
+static ee_u16 state_known_crc[]  = { (ee_u16)0x5e47,
+                                    (ee_u16)0x39bf,
+                                    (ee_u16)0xe5a4,
+                                    (ee_u16)0x8e3a,
+                                    (ee_u16)0x8d84 };
+void *
+iterate(void *pres)
+{
+    ee_u32        i;
+    ee_u16        crc;
+    core_results *res        = (core_results *)pres;
+    ee_u32        iterations = res->iterations;
+    res->crc                 = 0;
+    res->crclist             = 0;
+    res->crcmatrix           = 0;
+    res->crcstate            = 0;
+
+    for (i = 0; i < iterations; i++)
+    {
+        crc      = core_bench_list(res, 1);
+        res->crc = crcu16(crc, res->crc);
+        crc      = core_bench_list(res, -1);
+        res->crc = crcu16(crc, res->crc);
+        if (i == 0)
+            res->crclist = res->crc;
+    }
+    return NULL;
+}
+
+#if (SEED_METHOD == SEED_ARG)
+ee_s32 get_seed_args(int i, int argc, char *argv[]);
+#define get_seed(x)    (ee_s16) get_seed_args(x, argc, argv)
+#define get_seed_32(x) get_seed_args(x, argc, argv)
+#else /* via function or volatile */
+ee_s32 get_seed_32(int i);
+#define get_seed(x) (ee_s16) get_seed_32(x)
+#endif
+
+#if (MEM_METHOD == MEM_STATIC)
+ee_u8 static_memblk[TOTAL_DATA_SIZE];
+#endif
+char *mem_name[3] = { "Static", "Heap", "Stack" };
+/* Function: main
+        Main entry routine for the benchmark.
+        This function is responsible for the following steps:
+
+        1 - Initialize input seeds from a source that cannot be determined at
+   compile time. 2 - Initialize memory block for use. 3 - Run and time the
+   benchmark. 4 - Report results, testing the validity of the output if the
+   seeds are known.
+
+        Arguments:
+        1 - first seed  : Any value
+        2 - second seed : Must be identical to first for iterations to be
+   identical 3 - third seed  : Any value, should be at least an order of
+   magnitude less then the input size, but bigger then 32. 4 - Iterations  :
+   Special, if set to 0, iterations will be automatically determined such that
+   the benchmark will run between 10 to 100 secs
+
+*/
+
+#if MAIN_HAS_NOARGC
+MAIN_RETURN_TYPE
+main(void)
+{
+    int   argc = 0;
+    char *argv[1];
+#else
+MAIN_RETURN_TYPE
+main(int argc, char *argv[])
+{
+#endif
+    ee_u16       i, j = 0, num_algorithms = 0;
+    ee_s16       known_id = -1, total_errors = 0;
+    ee_u16       seedcrc = 0;
+    CORE_TICKS   total_time;
+    core_results results[MULTITHREAD];
+#if (MEM_METHOD == MEM_STACK)
+    ee_u8 stack_memblock[TOTAL_DATA_SIZE * MULTITHREAD];
+#endif
+    /* first call any initializations needed */
+    portable_init(&(results[0].port), &argc, argv);
+    /* First some checks to make sure benchmark will run ok */
+    if (sizeof(struct list_head_s) > 128)
+    {
+        ee_printf("list_head structure too big for comparable data!\n");
+        return MAIN_RETURN_VAL;
+    }
+    results[0].seed1      = get_seed(1);
+    results[0].seed2      = get_seed(2);
+    results[0].seed3      = get_seed(3);
+    results[0].iterations = get_seed_32(4);
+#if CORE_DEBUG
+    results[0].iterations = 1;
+#endif
+    results[0].execs = get_seed_32(5);
+    if (results[0].execs == 0)
+    { /* if not supplied, execute all algorithms */
+        results[0].execs = ALL_ALGORITHMS_MASK;
+    }
+    /* put in some default values based on one seed only for easy testing */
+    if ((results[0].seed1 == 0) && (results[0].seed2 == 0)
+        && (results[0].seed3 == 0))
+    { /* perfromance run */
+        results[0].seed1 = 0;
+        results[0].seed2 = 0;
+        results[0].seed3 = 0x66;
+    }
+    if ((results[0].seed1 == 1) && (results[0].seed2 == 0)
+        && (results[0].seed3 == 0))
+    { /* validation run */
+        results[0].seed1 = 0x3415;
+        results[0].seed2 = 0x3415;
+        results[0].seed3 = 0x66;
+    }
+#if (MEM_METHOD == MEM_STATIC)
+    results[0].memblock[0] = (void *)static_memblk;
+    results[0].size        = TOTAL_DATA_SIZE;
+    results[0].err         = 0;
+#if (MULTITHREAD > 1)
+#error "Cannot use a static data area with multiple contexts!"
+#endif
+#elif (MEM_METHOD == MEM_MALLOC)
+    for (i = 0; i < MULTITHREAD; i++)
+    {
+        ee_s32 malloc_override = get_seed(7);
+        if (malloc_override != 0)
+            results[i].size = malloc_override;
+        else
+            results[i].size = TOTAL_DATA_SIZE;
+        results[i].memblock[0] = portable_malloc(results[i].size);
+        results[i].seed1       = results[0].seed1;
+        results[i].seed2       = results[0].seed2;
+        results[i].seed3       = results[0].seed3;
+        results[i].err         = 0;
+        results[i].execs       = results[0].execs;
+    }
+#elif (MEM_METHOD == MEM_STACK)
+for (i = 0; i < MULTITHREAD; i++)
+{
+    results[i].memblock[0] = stack_memblock + i * TOTAL_DATA_SIZE;
+    results[i].size        = TOTAL_DATA_SIZE;
+    results[i].seed1       = results[0].seed1;
+    results[i].seed2       = results[0].seed2;
+    results[i].seed3       = results[0].seed3;
+    results[i].err         = 0;
+    results[i].execs       = results[0].execs;
+}
+#else
+#error "Please define a way to initialize a memory block."
+#endif
+    /* Data init */
+    /* Find out how space much we have based on number of algorithms */
+    for (i = 0; i < NUM_ALGORITHMS; i++)
+    {
+        if ((1 << (ee_u32)i) & results[0].execs)
+            num_algorithms++;
+    }
+    for (i = 0; i < MULTITHREAD; i++)
+        results[i].size = results[i].size / num_algorithms;
+    /* Assign pointers */
+    for (i = 0; i < NUM_ALGORITHMS; i++)
+    {
+        ee_u32 ctx;
+        if ((1 << (ee_u32)i) & results[0].execs)
+        {
+            for (ctx = 0; ctx < MULTITHREAD; ctx++)
+                results[ctx].memblock[i + 1]
+                    = (char *)(results[ctx].memblock[0]) + results[0].size * j;
+            j++;
+        }
+    }
+    /* call inits */
+    for (i = 0; i < MULTITHREAD; i++)
+    {
+        if (results[i].execs & ID_LIST)
+        {
+            results[i].list = core_list_init(
+                results[0].size, results[i].memblock[1], results[i].seed1);
+        }
+        if (results[i].execs & ID_MATRIX)
+        {
+            core_init_matrix(results[0].size,
+                             results[i].memblock[2],
+                             (ee_s32)results[i].seed1
+                                 | (((ee_s32)results[i].seed2) << 16),
+                             &(results[i].mat));
+        }
+        if (results[i].execs & ID_STATE)
+        {
+            core_init_state(
+                results[0].size, results[i].seed1, results[i].memblock[3]);
+        }
+    }
+
+    /* automatically determine number of iterations if not set */
+    if (results[0].iterations == 0)
+    {
+        secs_ret secs_passed = 0;
+        ee_u32   divisor;
+        results[0].iterations = 1;
+        while (secs_passed < (secs_ret)1)
+        {
+            results[0].iterations *= 10;
+            start_time();
+            iterate(&results[0]);
+            stop_time();
+            secs_passed = time_in_secs(get_time());
+        }
+        /* now we know it executes for at least 1 sec, set actual run time at
+         * about 10 secs */
+        divisor = (ee_u32)secs_passed;
+        if (divisor == 0) /* some machines cast float to int as 0 since this
+                             conversion is not defined by ANSI, but we know at
+                             least one second passed */
+            divisor = 1;
+        results[0].iterations *= 1 + 10 / divisor;
+    }
+    /* perform actual benchmark */
+    start_time();
+#if (MULTITHREAD > 1)
+    if (default_num_contexts > MULTITHREAD)
+    {
+        default_num_contexts = MULTITHREAD;
+    }
+    for (i = 0; i < default_num_contexts; i++)
+    {
+        results[i].iterations = results[0].iterations;
+        results[i].execs      = results[0].execs;
+        core_start_parallel(&results[i]);
+    }
+    for (i = 0; i < default_num_contexts; i++)
+    {
+        core_stop_parallel(&results[i]);
+    }
+#else
+    iterate(&results[0]);
+#endif
+    stop_time();
+    total_time = get_time();
+    /* get a function of the input to report */
+    seedcrc = crc16(results[0].seed1, seedcrc);
+    seedcrc = crc16(results[0].seed2, seedcrc);
+    seedcrc = crc16(results[0].seed3, seedcrc);
+    seedcrc = crc16(results[0].size, seedcrc);
+
+    switch (seedcrc)
+    {                /* test known output for common seeds */
+        case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */
+            known_id = 0;
+            ee_printf("6k performance run parameters for coremark.\n");
+            break;
+        case 0x7b05: /*  seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per
+                        algorithm */
+            known_id = 1;
+            ee_printf("6k validation run parameters for coremark.\n");
+            break;
+        case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm
+                      */
+            known_id = 2;
+            ee_printf("Profile generation run parameters for coremark.\n");
+            break;
+        case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */
+            known_id = 3;
+            ee_printf("2K performance run parameters for coremark.\n");
+            break;
+        case 0x18f2: /*  seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per
+                        algorithm */
+            known_id = 4;
+            ee_printf("2K validation run parameters for coremark.\n");
+            break;
+        default:
+            total_errors = -1;
+            break;
+    }
+    if (known_id >= 0)
+    {
+        for (i = 0; i < default_num_contexts; i++)
+        {
+            results[i].err = 0;
+            if ((results[i].execs & ID_LIST)
+                && (results[i].crclist != list_known_crc[known_id]))
+            {
+                ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n",
+                          i,
+                          results[i].crclist,
+                          list_known_crc[known_id]);
+                results[i].err++;
+            }
+            if ((results[i].execs & ID_MATRIX)
+                && (results[i].crcmatrix != matrix_known_crc[known_id]))
+            {
+                ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n",
+                          i,
+                          results[i].crcmatrix,
+                          matrix_known_crc[known_id]);
+                results[i].err++;
+            }
+            if ((results[i].execs & ID_STATE)
+                && (results[i].crcstate != state_known_crc[known_id]))
+            {
+                ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n",
+                          i,
+                          results[i].crcstate,
+                          state_known_crc[known_id]);
+                results[i].err++;
+            }
+            total_errors += results[i].err;
+        }
+    }
+    total_errors += check_data_types();
+    /* and report results */
+    ee_printf("CoreMark Size    : %lu\n", (long unsigned)results[0].size);
+    ee_printf("Total ticks      : %lu\n", (long unsigned)total_time);
+#if HAS_FLOAT
+    ee_printf("Total time (secs): %f\n", time_in_secs(total_time));
+    if (time_in_secs(total_time) > 0)
+        ee_printf("Iterations/Sec   : %f\n",
+                  default_num_contexts * results[0].iterations
+                      / time_in_secs(total_time));
+#else
+    ee_printf("Total time (secs): %d\n", time_in_secs(total_time));
+    if (time_in_secs(total_time) > 0)
+        ee_printf("Iterations/Sec   : %d\n",
+                  default_num_contexts * results[0].iterations
+                      / time_in_secs(total_time));
+#endif
+/*  if (time_in_secs(total_time) < 10)
+    {
+        ee_printf(
+            "ERROR! Must execute for at least 10 secs for a valid result!\n");
+        total_errors++;
+    }
+*/
+
+    ee_printf("Iterations       : %lu\n",
+              (long unsigned)default_num_contexts * results[0].iterations);
+#if (MULTITHREAD > 1)
+    ee_printf("Parallel %s : %d\n", PARALLEL_METHOD, default_num_contexts);
+#endif
+    ee_printf("Memory location  : %s\n", MEM_LOCATION);
+    /* output for verification */
+    ee_printf("seedcrc          : 0x%04x\n", seedcrc);
+    if (results[0].execs & ID_LIST)
+        for (i = 0; i < default_num_contexts; i++)
+            ee_printf("[%d]crclist       : 0x%04x\n", i, results[i].crclist);
+    if (results[0].execs & ID_MATRIX)
+        for (i = 0; i < default_num_contexts; i++)
+            ee_printf("[%d]crcmatrix     : 0x%04x\n", i, results[i].crcmatrix);
+    if (results[0].execs & ID_STATE)
+        for (i = 0; i < default_num_contexts; i++)
+            ee_printf("[%d]crcstate      : 0x%04x\n", i, results[i].crcstate);
+    for (i = 0; i < default_num_contexts; i++)
+        ee_printf("[%d]crcfinal      : 0x%04x\n", i, results[i].crc);
+    if (total_errors == 0)
+    {
+        ee_printf(
+            "Correct operation validated. See README.md for run and reporting "
+            "rules.\n");
+#if HAS_FLOAT
+        if (known_id == 3)
+        {
+            ee_printf("CoreMark 1.0 : %f / %s",
+                      default_num_contexts * results[0].iterations
+                          / time_in_secs(total_time),
+                      COMPILER_VERSION);
+//                    COMPILER_VERSION,
+//                    COMPILER_FLAGS);
+#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
+            ee_printf(" / %s", MEM_LOCATION);
+#else
+            ee_printf(" / %s", mem_name[MEM_METHOD]);
+#endif
+
+#if (MULTITHREAD > 1)
+            ee_printf(" / %d:%s", default_num_contexts, PARALLEL_METHOD);
+#endif
+            ee_printf("\n");
+        }
+#endif
+    }
+    if (total_errors > 0)
+        ee_printf("Errors detected\n");
+    if (total_errors < 0)
+        ee_printf(
+            "Cannot validate operation for these seed values, please compare "
+            "with results on a known platform.\n");
+
+#if (MEM_METHOD == MEM_MALLOC)
+    for (i = 0; i < MULTITHREAD; i++)
+        portable_free(results[i].memblock[0]);
+#endif
+    /* And last call any target specific code for finalizing */
+    portable_fini(&(results[0].port));
+
+    return MAIN_RETURN_VAL;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
index bbab3698..ea842d8a 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
@@ -208,7 +208,7 @@ int main(int argc, char *argv[])
 
 #endif // TEST_ADDRESS_MODE
 
-#ifndef TARGET_PYNQ_Z2
+#if defined(TARGET_SIM) || defined(TARGET_SYSTEMC)
 
 #ifdef TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
@@ -275,7 +275,7 @@ int main(int argc, char *argv[])
 #endif //TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
 #else
-    #pragma message( "TEST_ADDRESS_MODE_EXTERNAL_DEVICE is not executed on PYNQ Z2" )
+    #pragma message( "TEST_ADDRESS_MODE_EXTERNAL_DEVICE is not executed on target different than TARGET_SIM" )
 #endif
 
 #ifdef TEST_PENDING_TRANSACTION
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_ext_memory/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_ext_memory/main.c
new file mode 100644
index 00000000..8af03ad4
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_ext_memory/main.c
@@ -0,0 +1,128 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+
+#define BUFF_LEN 100
+
+uint32_t  buffer_rnd_index[BUFF_LEN];
+
+#ifdef TARGET_SYSTEMC
+//make app PROJECT=example_ext_memory TARGET=systemc
+#define CACHE_FLUSH   1
+#define CACHE_BYPASS  2
+#define CACHE_SIZE    4*1024
+#endif
+
+#define MEMORY_SIZE           32*1024
+#define MEMORY_ADDR_MASK       0x7FFF
+#define MEMORY_MAX_WORD_INDEX  (MEMORY_SIZE/4)
+
+int is_in_array(uint32_t number, uint32_t* array, int N ) {
+
+    for (int i=0;i<N;i++) {
+        if (number == array[i])
+            return 1;
+    }
+    return 0;
+}
+
+int main(int argc, char *argv[])
+{
+
+
+#if defined(TARGET_SIM) || defined(TARGET_SYSTEMC)
+
+    uint32_t* ext_memory = (uint32_t*)EXT_SLAVE_START_ADDRESS;
+
+    #ifdef TARGET_SYSTEMC
+    //last address of systemC memory used as a configuration register to flush or bypass
+    volatile uint32_t* cache_cfg = (uint32_t*)(EXT_SLAVE_START_ADDRESS + MEMORY_SIZE - 4);
+    #endif
+
+    uint32_t random_number = 0;
+    uint32_t errors = 0;
+
+    heep_init_lfsr();
+
+    //test 1
+    for(int i=0;i<BUFF_LEN;i++) {
+        ext_memory[i] = i;
+    }
+
+    for(int i=0;i<BUFF_LEN;i++){
+        if (ext_memory[i] != i) {
+            printf("%d) T1: exp. %x, got %x (@%x)\n",i, i,ext_memory[i],&ext_memory[i]);
+            errors++;
+        }
+    }
+
+    //test 2
+    for(int i=0;i<BUFF_LEN;i++) {
+
+        do {
+            random_number = (uint32_t)(heep_rand_lfsr()) % MEMORY_MAX_WORD_INDEX;
+        } while ( is_in_array(random_number, buffer_rnd_index, i) );
+
+        buffer_rnd_index[i] = random_number;
+        ext_memory[buffer_rnd_index[i]] = i*16;
+    }
+
+    for(int i=0;i<BUFF_LEN;i++){
+        if (ext_memory[buffer_rnd_index[i]] != i*16) {
+            printf("%d) T2: exp. %x, got %x (@%x)\n",i, i*16,ext_memory[buffer_rnd_index[i]],&ext_memory[buffer_rnd_index[i]]);
+            errors++;
+        }
+    }
+
+
+    //test 3
+
+    //as the memory is 32kB, and the cache has 256 blocks
+    //replace some cache line
+    //writing at EXT_SLAVE_START_ADDRESS + 0x1000 (4kB)
+    //the cache is 256*16B = 4KB, so every 4KB it will replace the index
+    uint32_t* myptr1 = (uint32_t*)(EXT_SLAVE_START_ADDRESS + 0x1000);
+
+    for(int i=0;i<BUFF_LEN;i++){
+        myptr1[i] = i*32;
+    }
+
+    for(int i=0;i<BUFF_LEN;i++){
+        if (myptr1[i] != i*32) {
+            printf("%d) T3: exp. %x, got %x (@%x)\n",i, i*32,myptr1[i],&myptr1[i]);
+            errors++;
+        }
+    }
+
+    //test 4, flush and bypass
+    #ifdef TARGET_SYSTEMC
+    //make sure you store everything back to main memory and bypass the flash
+    *cache_cfg = CACHE_FLUSH;
+    *cache_cfg = CACHE_BYPASS;
+    #endif
+
+    for(int i=0;i<BUFF_LEN;i++){
+        if (myptr1[i] != i*32) {
+            printf("%d) T4: exp. %x, got %x (@%x)\n",i, i*32,myptr1[i],&myptr1[i]);
+            errors++;
+        }
+    }
+
+
+
+
+    return errors;
+
+#else
+   #pragma message ( "this application must be ran only in the testbench" )
+    return EXIT_SUCCESS;
+#endif
+
+}
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
new file mode 100644
index 00000000..b62fab6a
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright EPFL contributors.
+ * Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Author: Pierre Guillod <pierre.guillod@epfl.ch>
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "core_v_mini_mcu.h"
+
+#include "x-heep.h"
+#include "iffifo_regs.h"
+
+#include "mmio.h"
+#include "handler.h"
+#include "csr.h"
+#include "hart.h"
+
+#include "rv_plic.h"
+
+#include "dma.h"
+#include "dma_regs.h"
+#include "fast_intr_ctrl.h"
+
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+unsigned int IFFIFO_START_ADDRESS = EXT_PERIPHERAL_START_ADDRESS + 0x2000;
+
+int32_t to_fifo  [6]   __attribute__ ((aligned (4)))  = { 1, 2, 3, 4, 5, 6 };
+int32_t from_fifo[4]   __attribute__ ((aligned (4)))  = { 0, 0, 0, 0 };
+
+int8_t dma_intr_flag = 0;
+void dma_intr_handler_trans_done()
+{
+  dma_intr_flag = 1;
+}
+
+void protected_wait_for_dma_interrupt(void)
+{
+  while(!dma_is_ready()) {
+    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+    if (!dma_is_ready()) {
+        wait_for_interrupt();
+    }
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+  }
+}
+
+iffifo_intr_flag = 0;
+static void handler_irq_iffifo( uint32_t int_id )
+{
+  mmio_region_t iffifo_base_addr = mmio_region_from_addr((uintptr_t)IFFIFO_START_ADDRESS);
+  mmio_region_write32(iffifo_base_addr, IFFIFO_INTERRUPTS_REG_OFFSET, 0b0);
+  iffifo_intr_flag = 1;
+  PRINTF(" ** REACH intr. fired.\n");
+}
+
+static dma_target_t tgt_src;
+static dma_target_t tgt_dst;
+static dma_trans_t trans;
+
+int compare_print_fifo_array(void) {
+  int errors = 0;
+  PRINTF("from_fifo = {");
+  for (int i = 0; i < 4; i+=1) {
+    PRINTF("%d",from_fifo[i]);
+    if(i != 4-1) {PRINTF(", ");};
+    if (to_fifo[i]+1 != from_fifo[i]) {++errors;}
+  }
+  PRINTF("}\n");
+  return errors;
+}
+
+void print_status_register(void)
+{
+  mmio_region_t iffifo_base_addr = mmio_region_from_addr((uintptr_t)IFFIFO_START_ADDRESS);
+  int32_t status = mmio_region_read32(iffifo_base_addr, IFFIFO_STATUS_REG_OFFSET);
+  PRINTF("STATUS = ");
+  PRINTF(status & (1 << IFFIFO_STATUS_EMPTY_BIT)     ? "E" : "-"); // FIFO empty
+  PRINTF(status & (1 << IFFIFO_STATUS_AVAILABLE_BIT) ? "A" : "-"); // Data available in FIFO
+  PRINTF(status & (1 << IFFIFO_STATUS_REACHED_BIT)   ? "R" : "-"); // Watermark reached
+  PRINTF(status & (1 << IFFIFO_STATUS_FULL_BIT)      ? "F" : "-"); // FIFO full
+  PRINTF("\n");
+}
+
+int is_iffifo_full(void)
+{
+  mmio_region_t iffifo_base_addr = mmio_region_from_addr((uintptr_t)IFFIFO_START_ADDRESS);
+  int32_t status = mmio_region_read32(iffifo_base_addr, IFFIFO_STATUS_REG_OFFSET);
+  return status & (1 << IFFIFO_STATUS_FULL_BIT);
+}
+
+int main(int argc, char *argv[]) {
+
+    mmio_region_t iffifo_base_addr = mmio_region_from_addr((uintptr_t)IFFIFO_START_ADDRESS);
+    
+    // Enable interrupt on processor side
+    // Enable global interrupt for machine-level interrupts
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+    // Set mie.MEIE bit to one to enable machine-level external interrupts
+    const uint32_t mask = 1 << 11;
+    CSR_SET_BITS(CSR_REG_MIE, mask);
+    
+    if(plic_Init()) {return EXIT_FAILURE;};
+    if(plic_irq_set_priority(EXT_INTR_1, 1)) {return EXIT_FAILURE;};
+    if(plic_irq_set_enabled(EXT_INTR_1, kPlicToggleEnabled)) {return EXIT_FAILURE;};
+    
+    plic_assign_external_irq_handler(EXT_INTR_1, &handler_irq_iffifo);
+    
+    mmio_region_write32(iffifo_base_addr, IFFIFO_WATERMARK_REG_OFFSET, 2);
+    mmio_region_write32(iffifo_base_addr, IFFIFO_INTERRUPTS_REG_OFFSET, 0b1);
+    
+    dma_config_flags_t ret;
+
+     // -- DMA CONFIGURATION --
+
+    dma_init(NULL);
+    tgt_src.ptr        = to_fifo;
+    tgt_src.inc_du     = 1;
+    tgt_src.trig       = DMA_TRIG_MEMORY;
+    tgt_src.type       = DMA_DATA_TYPE_WORD;
+    tgt_src.size_du    = 6;
+
+    tgt_dst.ptr        = IFFIFO_START_ADDRESS + IFFIFO_FIFO_IN_REG_OFFSET;
+    tgt_dst.inc_du     = 0;
+    tgt_dst.trig       = DMA_TRIG_SLOT_EXT_TX;
+    tgt_dst.type       = DMA_DATA_TYPE_WORD;
+    
+    trans.src        = &tgt_src;
+    trans.dst        = &tgt_dst;
+    trans.end        = DMA_TRANS_END_INTR;
+
+    ret = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    if (ret != 0) {return EXIT_FAILURE;}
+    ret = dma_load_transaction(&trans);
+    if (ret != 0) {return EXIT_FAILURE;}
+    
+    if (compare_print_fifo_array() != 4) {return EXIT_FAILURE;}
+    
+    print_status_register();
+    
+    PRINTF("Launch MM -> Stream DMA\n");
+    // Launch a 6-word TX DMA transaction to a 4-word FIFO. The FIFO will be full.
+    dma_launch( &trans );
+    
+    // To terminate the DMA transaction, 2 words must be manually popped from the FIFO.
+    while(!is_iffifo_full());
+    int32_t read0 = mmio_region_read32(iffifo_base_addr, IFFIFO_FIFO_OUT_REG_OFFSET);
+    while(!is_iffifo_full());
+    int32_t read1 = mmio_region_read32(iffifo_base_addr, IFFIFO_FIFO_OUT_REG_OFFSET);
+    
+    print_status_register();
+    
+    PRINTF("Manual readings: {%d, %d}\n", read0, read1);
+
+    protected_wait_for_dma_interrupt();
+    
+    dma_init(NULL);
+    tgt_src.ptr        = IFFIFO_START_ADDRESS + IFFIFO_FIFO_OUT_REG_OFFSET;
+    tgt_src.inc_du     = 0;
+    tgt_src.trig       = DMA_TRIG_SLOT_EXT_RX;
+    tgt_src.type       = DMA_DATA_TYPE_WORD;
+    tgt_src.size_du    = 4;
+
+    tgt_dst.ptr        = from_fifo;
+    tgt_dst.inc_du     = 1;
+    tgt_dst.trig       = DMA_TRIG_MEMORY;
+    tgt_dst.type       = DMA_DATA_TYPE_WORD;
+
+    trans.src        = &tgt_src;
+    trans.dst        = &tgt_dst;
+    trans.end        = DMA_TRANS_END_INTR;
+    
+    ret = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    if (ret != 0) {return EXIT_FAILURE;}
+    ret = dma_load_transaction(&trans);
+    if (ret != 0) {return EXIT_FAILURE;}
+    PRINTF("Launch Stream -> MM DMA\n");
+    dma_launch( &trans );
+    
+    protected_wait_for_dma_interrupt();
+    
+    print_status_register();
+
+    if (compare_print_fifo_array() == 0) {return EXIT_FAILURE;};
+    
+    if (!iffifo_intr_flag) {return EXIT_FAILURE;};
+    
+    return EXIT_SUCCESS;
+    
+}
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c
new file mode 100644
index 00000000..86f69972
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c
@@ -0,0 +1,84 @@
+// Copyright 2022 OpenHW Group
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "csr.h"
+#include "matrixAdd32.h"
+#include "x-heep.h"
+#include "core_v_mini_mcu.h"
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+void __attribute__ ((noinline)) matrixAdd(int32_t * A, int32_t * B, int32_t * C, int N, int M);
+uint32_t check_results(int32_t *  C, int N, int M);
+
+int32_t __attribute__((section(".xheep_data_interleaved"))) m_c[16*16];
+
+
+int main()
+{
+
+#ifndef HAS_MEMORY_BANKS_IL
+    PRINTF("This application is only meant to be tested when there are interleaved memory banks\n");
+    return EXIT_SUCCESS;
+#endif
+
+
+    int N = WIDTH;
+    int M = HEIGHT;
+    uint32_t errors = 0;
+    unsigned int instr, cycles, ldstall, jrstall, imstall;
+
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+
+    //execute the kernel
+    matrixAdd(m_a, m_b, m_c, N, M);
+
+    CSR_READ(CSR_REG_MCYCLE, &cycles) ;
+
+    //stop the HW counter used for monitoring
+
+    errors = check_results(m_c, N, M);
+
+    PRINTF("program finished with %d errors and %d cycles\n\r", errors, cycles);
+    return errors;
+}
+
+void __attribute__ ((noinline)) matrixAdd(int32_t *  A, int32_t *  B, int32_t *  C, int N, int M)
+{
+    for(int i = 0; i < N; i++) {
+        for(int j = 0; j < M; j++) {
+            C[i*N+j] = A[i*WIDTH+j] + B[i*WIDTH+j];
+        }
+    }
+}
+
+uint32_t check_results(int32_t * C, int N, int M)
+{
+    // check
+    int i, j;
+    uint32_t err = 0;
+
+    for(i = 0; i < N; i++) {
+        for(j = 0; j < M; j++) {
+            if(C[i*N+j] != m_exp[i*WIDTH+j]) {
+                err++;
+                PRINTF("Error at index %d, %d, expected %d, got %d\n\r", i, j, m_exp[i*WIDTH+j], C[i*N+j]);
+            }
+        }
+    }
+
+    return err;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/matrixAdd32.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/matrixAdd32.h
new file mode 100644
index 00000000..8b9bace3
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/matrixAdd32.h
@@ -0,0 +1,64 @@
+#ifndef MatrixAdd32_H_
+#define MatrixAdd32_H_
+
+int32_t __attribute__((section(".xheep_data_interleaved"))) m_a[16*16] = {
+-267220638, -815694637, -357240193, 52586566, 471263969, -752743258, -54811671, -330483534, -895389047, 476606065, -261687046, -301494394, 101299356, 1064594637, 876939884, 673598893,
+510087407, 21095419, -66273695, 200819447, 230905645, -522677817, 466985617, -42864608, 925345137, -985253526, 963426323, 34126990, -894741205, -944572242, -62503253, -88084923,
+-40863508, 775424478, -977993934, -563294903, 240810335, -950840151, 841082377, 814816122, 1010825869, 626595210, -30466653, 32965586, -1009681585, -398274647, 209852250, -680997577,
+831825297, 371554642, 209565266, -173321792, 130553499, -846489230, -837855833, -291296547, -656131005, -1008649794, -644660179, -559832327, -957317256, 414035806, 238077607, -417354312,
+691270381, 167236288, -370338394, 264811381, -740211299, -502137446, -216028919, -576761164, -1005576983, -300300576, -51567714, 742968985, -713639053, 81381137, -254911471, -456085969,
+-657637814, 212880558, 164912940, 975706502, -558175870, -522438623, 219649600, -149341108, -761491992, -324770181, -905679666, -1066241764, 852450941, -105770862, -706293797, 965826475,
+605386582, 397282251, -510180840, 322039481, 906789344, 577829424, -244909961, -6565162, -10463653, -275962613, 1045813592, 287658995, 202626085, -913131320, -953473425, 7501200,
+44568419, 631042458, -962343731, 389765403, 510986448, 615528098, 854389577, 873031590, 291656555, 717742724, 139337062, 1014134612, 37179482, 156110030, 549532436, -211305424,
+146967397, -910154681, 306466943, 809719463, 990862734, -321035009, -503247368, -434011427, -184327001, -460285290, -695885128, 745541667, 549735829, 972687164, 81845219, 626415449,
+-869892524, 7650305, -668932203, 612640394, -533618868, -767284692, 263874653, -505082478, -333082894, -170998598, 351985173, 539903843, 161284779, -223326011, -386924128, -894616525,
+-205913216, 983230715, 184759813, 3745004, -421392253, 311771810, 809133901, 541639735, 1029270115, 390582486, 1059667793, -308077038, -345200733, 661937983, -69729012, -313649214,
+-457079064, 660862401, -419895058, -352985806, 748622990, 789128492, 57857836, 123409871, 367565501, 714681971, 90478156, 401194382, -25590123, 808922190, 231668089, 365978441,
+-168791957, 500701111, 966566283, -619646012, 410934777, -567381204, 405170082, -954683259, -176892010, 205925886, 1035377376, 91289957, 478111519, 220727997, -859802080, -155168848,
+723982461, -833318195, -445511314, -903460885, 167471780, 423323222, -640855013, 480396600, -268314639, -850542572, 257027787, -315635254, 560711756, -717798753, -372060287, -544448897,
+-103077323, -640041517, 577573751, 1039664378, -546538923, 739571966, 680289428, 412799378, 987282320, -378880850, 588647906, -965191092, -829907433, 739600408, -33720223, 56361300,
+-1068334620, -399957948, -960664907, -540542510, 280786542, -752129362, -10289650, 1029788294, -636639267, 1029706817, -892387611, 191199904, -965464658, -1048403025, -734580512, 872029387,
+};
+
+int32_t __attribute__((section(".xheep_data_interleaved"))) m_b[16*16] = {
+-451882475, -777460700, 909169980, -96074001, -300818508, 814405880, -568048006, -83472456, 402440048, 810240641, -180564453, 216877888, -140613462, 620727378, -909318526, 765805622,
+-231722067, -336894715, -1073684733, -121460761, -23888211, 438175722, -904262018, 145258576, -356787314, 372900212, -358591099, 140421444, -928238022, -99914115, 968352616, -71902672,
+-7354035, -831973999, 233305822, -392287490, -729923194, -828467700, -323283176, -788941348, -111739211, -199056442, -476803416, 465916744, 443852965, -376815395, 148885406, 124331090,
+-998134941, -490161461, 607731285, 887008149, 683830004, -186741406, -241303958, 456378716, 536730595, 967225269, 1037796891, -802215107, 382626188, 791688228, 538691527, -19673298,
+251682349, 598278365, 984763713, 698038628, 821027888, -495782484, -798473539, -424505599, 310436971, 361824506, -130460722, -847926918, 926418138, 637997507, 565305015, 901041052,
+236841072, 748341019, 851219634, 437917539, 979456559, 834327011, -191800443, 415161968, -687346999, -41616108, 226338567, 671381489, -248505365, -991524242, 465050274, 673573191,
+-432551530, 1057245412, 714468280, -650829182, -850172935, 408331778, 846612827, 884618062, -1025138869, 389044228, 241552082, 1038961376, -425996140, -770151901, -59811946, 433319347,
+420324744, -41895865, -626338369, -617719112, -398763632, 40560785, 608712418, 270292226, 276772130, 713936878, -39616963, 852564869, 651061789, -1069752389, 942487510, -212496210,
+-884568730, -614540093, 940597970, 963278316, 500604546, -89930534, -362276438, 800923761, 799305363, 67728257, -935053727, -507421158, 453168328, -270267180, 767962559, 540805,
+-178905319, 755067965, -132287841, -8637376, 608185815, 427835026, 103464976, -203264205, 80225884, 539643001, -362743073, -487778248, 792077066, 697184933, 827496823, 790812604,
+249285726, 359686773, 419021969, 454726313, 124358246, 47824230, -619837186, -913155286, -381944316, 783327309, 572077053, -225060553, 787746239, 671339856, 730167112, 870184696,
+319311551, 932192632, -376845525, -288051918, 713264893, -102198441, -315559203, -635483087, -76253988, -427900440, -508626018, -847322511, -717023663, 649773356, -751674700, -363502823,
+896873064, -967112426, -607994984, 346538028, -403535863, -456242519, -865446025, -238823125, 568667781, -1008745310, -517236588, -90482335, -769550983, -553756781, -473911347, -317302102,
+308779302, 610106502, -99323447, -610238668, 176302035, 320291710, 22124485, 927846370, -961507070, 1046393978, 623269088, -385024596, -636139940, -661255126, -1024580190, -710776275,
+874358552, -978379641, 484825057, -177908522, -643611415, -197553591, 406358020, 460342548, 408235584, -809119385, 1047128507, -592130753, -50891763, 786819419, 314046385, 461621105,
+-328939806, 375494681, 558517164, 640788713, -419567316, -499867631, 629778826, 201608525, 1006046604, 259505742, 994398852, 338082134, -444011788, 128878595, -672831452, 18560178,
+};
+
+int32_t m_exp[16*16] = {
+-719103113, -1593155337, 551929787, -43487435, 170445461, 61662622, -622859677, -413955990, -492948999, 1286846706, -442251499, -84616506, -39314106, 1685322015, -32378642, 1439404515,
+278365340, -315799296, -1139958428, 79358686, 207017434, -84502095, -437276401, 102393968, 568557823, -612353314, 604835224, 174548434, -1822979227, -1044486357, 905849363, -159987595,
+-48217543, -56549521, -744688112, -955582393, -489112859, -1779307851, 517799201, 25874774, 899086658, 427538768, -507270069, 498882330, -565828620, -775090042, 358737656, -556666487,
+-166309644, -118606819, 817296551, 713686357, 814383503, -1033230636, -1079159791, 165082169, -119400410, -41424525, 393136712, -1362047434, -574691068, 1205724034, 776769134, -437027610,
+942952730, 765514653, 614425319, 962850009, 80816589, -997919930, -1014502458, -1001266763, -695140012, 61523930, -182028436, -104957933, 212779085, 719378644, 310393544, 444955083,
+-420796742, 961221577, 1016132574, 1413624041, 421280689, 311888388, 27849157, 265820860, -1448838991, -366386289, -679341099, -394860275, 603945576, -1097295104, -241243523, 1639399666,
+172835052, 1454527663, 204287440, -328789701, 56616409, 986161202, 601702866, 878052900, -1035602522, 113081615, 1287365674, 1326620371, -223370055, -1683283221, -1013285371, 440820547,
+464893163, 589146593, -1588682100, -227953709, 112222816, 656088883, 1463101995, 1143323816, 568428685, 1431679602, 99720099, 1866699481, 688241271, -913642359, 1492019946, -423801634,
+-737601333, -1524694774, 1247064913, 1772997779, 1491467280, -410965543, -865523806, 366912334, 614978362, -392557033, -1630938855, 238120509, 1002904157, 702419984, 849807778, 626956254,
+-1048797843, 762718270, -801220044, 604003018, 74566947, -339449666, 367339629, -708346683, -252857010, 368644403, -10757900, 52125595, 953361845, 473858922, 440572695, -103803921,
+43372510, 1342917488, 603781782, 458471317, -297034007, 359596040, 189296715, -371515551, 647325799, 1173909795, 1631744846, -533137591, 442545506, 1333277839, 660438100, 556535482,
+-137767513, 1593055033, -796740583, -641037724, 1461887883, 686930051, -257701367, -512073216, 291311513, 286781531, -418147862, -446128129, -742613786, 1458695546, -520006611, 2475618,
+728081107, -466411315, 358571299, -273107984, 7398914, -1023623723, -460275943, -1193506384, 391775771, -802819424, 518140788, 807622, -291439464, -333028784, -1333713427, -472470950,
+1032761763, -223211693, -544834761, -1513699553, 343773815, 743614932, -618730528, 1408242970, -1229821709, 195851406, 880296875, -700659850, -75428184, -1379053879, -1396640477, -1255225172,
+771281229, -1618421158, 1062398808, 861755856, -1190150338, 542018375, 1086647448, 873141926, 1395517904, -1188000235, 1635776413, -1557321845, -880799196, 1526419827, 280326162, 517982405,
+-1397274426, -24463267, -402147743, 100246203, -138780774, -1251996993, 619489176, 1231396819, 369407337, 1289212559, 102011241, 529282038, -1409476446, -919524430, -1407411964, 890589565,
+};
+
+#define WIDTH 16
+#define HEIGHT 16
+
+#endif  // MatrixAdd32_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/gen_stimuly.py b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/gen_stimuly.py
new file mode 100644
index 00000000..cdf55503
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/gen_stimuly.py
@@ -0,0 +1,52 @@
+#!/usr/bin/env python
+
+## Copyright 2024 EPFL
+## Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+import sys
+import random
+import numpy as np
+
+def write_arr(f, name, arr, ctype, size):
+    f.write("const " + ctype + " " + name + "[] = {\n")
+
+    for row in arr:
+        for elem in row[:-1]:
+            f.write('%d,' % (elem))
+        f.write('%d,\n' % (row[-1]))
+
+    f.write('};\n\n')
+    return
+
+
+################################################################################
+f = open('matrixMul8.h', 'w')
+f.write('#ifndef _MATMUL8_\n')
+f.write('#define _MATMUL8_\n')
+f.write('// This file is automatically generated\n')
+
+
+SIZE  = 16
+RANGE = 4
+
+m_a   = []
+m_b   = []
+m_exp = []
+
+# Generate random 8 bit integers from -RANGE to RANGE for A and B
+m_a = np.random.randint(-RANGE, RANGE, size=(SIZE, SIZE), dtype=np.int32)
+m_b = np.random.randint(-RANGE, RANGE, size=(SIZE, SIZE), dtype=np.int32)
+m_exp = np.zeros((SIZE, SIZE), dtype=np.int32)
+
+# Test the function with A and B
+m_exp = np.matmul(m_a,m_b)
+
+write_arr(f, 'm_a',   m_a, 'int8_t', SIZE)
+write_arr(f, 'm_b',   m_b, 'int8_t', SIZE)
+write_arr(f, 'm_exp', m_exp, 'int32_t', SIZE)
+
+f.write('#define SIZE %d\n' % SIZE)
+
+
+f.write('#endif')
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c
new file mode 100644
index 00000000..aec6ca4e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c
@@ -0,0 +1,126 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "csr.h"
+#include "matrixMul8.h"
+#include "x-heep.h"
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+void __attribute__ ((noinline)) matrixMul8_blocksize(int8_t *  A, int8_t *  B, int32_t *  C, int N);
+
+void __attribute__ ((noinline)) matrixMul8_tiled(int8_t *  A, int8_t *  B, int32_t *  C, int N);
+
+uint32_t check_results(int32_t * C, int N);
+
+int32_t m_c[SIZE*SIZE];
+
+#define BLOCK_SIZE 4
+
+// Define a macro for accessing matrix elements
+#define A(i,j) &A[i*SIZE+j]
+#define B(i,j) &B[i*SIZE+j]
+#define C(i,j) &C[i*SIZE+j]
+
+#define HIGHEST_PERF
+
+int main()
+{
+
+    uint32_t errors = 0;
+    unsigned int instr, cycles;
+
+    for(int i =0;i<SIZE;i++) {
+        for(int j =0;j<SIZE;j++) {
+            m_c[i*SIZE+j] = 0;
+        }
+    }
+
+    //enable mcycle csr
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+
+#ifdef HIGHEST_PERF
+    matrixMul8_blocksize(m_a, m_b, m_c, SIZE);
+#else
+    //execute the kernel
+    matrixMul8_tiled(m_a, m_b, m_c, SIZE);
+#endif
+
+    CSR_READ(CSR_REG_MCYCLE, &cycles);
+
+    errors = check_results(m_c, SIZE);
+
+    PRINTF("program finished with %d errors and %d cycles\n\r", errors, cycles);
+    return errors;
+}
+
+void __attribute__ ((noinline)) matrixMul8_blocksize(int8_t *  A, int8_t *  B, int32_t *  C, int N)
+{
+
+    for(int i = 0; i < N; i++) {
+        for(int j = 0; j < N; j++) {
+            int32_t acc = 0;
+            for(int k = 0; k < N; k++) {
+                acc+= A[i*SIZE+k] * B[k*SIZE+j];
+            }
+            C[i*SIZE+j] += acc;
+        }
+    }
+
+}
+
+
+// Define a recursive function that multiplies two matrices using the tiled algorithm
+void __attribute__ ((noinline)) matrixMul8_tiled(int8_t* A, int8_t* B, int32_t* C, int N) {
+    // use the elementary function
+    if (N == BLOCK_SIZE) {
+        matrixMul8_blocksize(A, B, C, N);
+    }
+    //split the matrices into four blocks each
+    else {
+        N = N >> 1; // Half the size
+        // Multiply the blocks and add them to the corresponding blocks of C
+        matrixMul8_tiled(A(0, 0), B(0, 0), C(0, 0), N); // C_00 += A_00 * B_00
+        matrixMul8_tiled(A(0, N), B(N, 0), C(0, 0), N); // C_00 += A_01 * B_10
+        matrixMul8_tiled(A(0, 0), B(0, N), C(0, N), N); // C_01 += A_00 * B_01
+        matrixMul8_tiled(A(0, N), B(N, N), C(0, N), N); // C_01 += A_01 * B_11
+        matrixMul8_tiled(A(N, 0), B(0, 0), C(N, 0), N); // C_10 += A_10 * B_00
+        matrixMul8_tiled(A(N, N), B(N, 0), C(N, 0), N); // C_10 += A_11 * B_10
+        matrixMul8_tiled(A(N, 0), B(0, N), C(N, N), N); // C_11 += A_10 * B_01
+        matrixMul8_tiled(A(N, N), B(N, N), C(N, N), N); // C_11 += A_11 * B_11
+    }
+}
+
+
+uint32_t check_results(int32_t * C, int N)
+{
+    // check
+    int i, j;
+    uint32_t err = 0;
+
+    for(i = 0; i < N; i++) {
+        for(j = 0; j < N; j++) {
+            if(C[i*N+j] != m_exp[i*N+j]) {
+                err++;
+                PRINTF("Error at index %d, %d, expected %d, got %d\n\r", i, j, m_exp[i*N+j], C[i*N+j]);
+            }
+        }
+    }
+
+    return err;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/matrixMul8.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/matrixMul8.h
new file mode 100644
index 00000000..bc2be3e0
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/matrixMul8.h
@@ -0,0 +1,62 @@
+#ifndef _MATMUL8_
+#define _MATMUL8_
+// This file is automatically generated
+const int8_t m_a[] = {
+-4,-2,-3,3,3,-1,-4,-3,1,-2,-2,2,-2,-4,-2,-1,
+0,2,0,-2,-3,3,-2,3,-1,3,0,2,3,1,-3,-2,
+0,2,2,3,-2,-2,-3,-2,0,-3,0,-4,2,-3,-3,1,
+3,-4,1,1,-1,0,-3,0,1,3,-1,-2,2,3,-4,0,
+3,-1,2,-4,-1,-2,0,-3,-3,0,-2,-4,-2,1,0,-2,
+-3,0,-2,2,-1,2,2,2,3,1,0,-2,-1,-4,3,-3,
+1,3,2,-3,-4,-3,-2,-1,-2,3,1,-3,2,-4,0,0,
+-2,0,3,-1,3,-4,0,-2,2,3,-2,-2,-1,-4,-3,1,
+-4,-2,-4,-1,-2,-4,-4,-2,-4,-4,-3,0,-2,-4,2,-4,
+1,-1,-3,-2,-1,-2,-4,0,2,3,1,-3,-3,1,3,1,
+-3,0,1,3,-3,1,3,2,0,-2,1,-4,-3,0,1,-4,
+3,0,-1,-3,2,-1,-1,1,-1,3,2,-4,2,2,0,-2,
+-4,2,2,-2,2,-4,-3,-3,-3,-3,-2,-3,3,0,3,0,
+2,3,-2,0,3,1,1,-3,3,0,1,-4,-4,-1,0,1,
+0,0,1,3,-3,3,3,1,-3,1,1,2,1,-2,-2,2,
+-1,2,-2,1,0,-2,-3,-1,0,0,2,0,3,3,-4,-4,
+};
+
+const int8_t m_b[] = {
+2,1,2,1,0,3,-1,-1,3,3,3,-2,0,-3,-1,3,
+-3,0,-3,0,2,-2,3,0,-2,-1,2,-3,2,-2,0,-2,
+-4,0,1,3,-3,-3,-2,2,3,0,-1,2,3,2,-2,-4,
+3,3,-2,3,2,2,-2,-1,-3,-3,-1,-3,3,-2,2,-2,
+0,1,0,-3,-1,-3,-1,0,-1,3,3,1,-1,-1,2,2,
+-2,-4,-1,-1,1,1,2,-1,2,3,0,3,2,0,-4,3,
+-1,-1,-3,2,-4,3,3,-1,3,1,-3,-2,1,1,2,3,
+0,2,0,1,1,-3,-4,-4,2,-2,1,0,3,2,0,-1,
+0,1,1,-1,2,-1,0,2,-1,-3,3,0,-2,-4,2,3,
+1,-4,2,-4,0,1,3,-4,-2,-3,-2,-2,-1,3,-2,-3,
+1,0,2,3,0,1,1,-1,-3,-1,3,-3,-3,-2,1,-4,
+-3,2,-4,1,3,2,3,-2,1,1,3,0,-2,-2,-1,-1,
+1,-3,-1,1,-2,2,-1,-4,3,0,-3,-4,-3,1,-1,2,
+-1,-2,3,-4,0,1,1,1,-2,1,-4,3,0,1,2,1,
+1,3,-1,-4,2,0,-1,-1,-4,-3,-2,-4,-1,-4,3,2,
+0,1,0,1,3,-4,-1,2,1,-1,3,-2,-2,-2,-1,-1,
+};
+
+const int32_t m_exp[] = {
+15,30,-21,1,25,-11,-8,24,-29,-1,32,23,-10,-15,9,-4,
+-20,-44,1,-1,3,12,19,-41,25,4,-10,11,7,36,-44,-17,
+13,10,3,50,-5,-17,-31,28,5,-12,9,-14,14,-3,-8,-28,
+23,-31,50,-6,-12,14,-20,-5,19,6,-17,24,-4,29,-22,-1,
+0,-17,35,-16,-40,5,-2,28,15,29,-28,27,10,27,-7,8,
+15,8,-21,-5,6,6,0,-18,-23,-38,-11,-19,16,-8,16,14,
+3,-18,14,16,-15,-9,1,-8,6,-23,-5,-36,-6,20,-27,-43,
+-4,-1,9,3,-23,-39,-5,24,5,-13,15,6,-4,21,-3,-26,
+20,35,-18,-6,6,3,-17,18,-28,-4,-14,16,-2,8,15,-4,
+31,7,45,-49,28,-14,-8,10,-49,-31,11,-6,-24,-17,14,-3,
+3,8,-5,21,-19,8,-10,8,-17,-23,-39,10,49,16,22,-9,
+21,-30,44,-32,-25,5,-5,-22,-5,10,-12,-8,-15,19,1,8,
+-7,8,-2,-18,-18,-38,-23,28,-20,-3,-29,-4,-9,9,17,-11,
+10,4,11,-18,8,-13,16,34,-29,6,36,-5,0,-37,18,22,
+-7,-13,-29,48,-2,22,13,-26,31,1,-8,-18,20,16,-30,-23,
+8,-20,13,0,-5,20,10,-10,-22,2,-9,4,-12,14,6,-18,
+};
+
+#define SIZE 16
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c
new file mode 100644
index 00000000..71de642f
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c
@@ -0,0 +1,85 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+
+#define TEST_DATA_SIZE      16
+
+#define PRINTF_IN_SIM   1
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+
+int32_t errors = 0;
+
+//defined in the testharness_pkg.sv
+#define SIMPLE_ACC_START_ADDRESS EXT_PERIPHERAL_START_ADDRESS + 0x3000;
+
+// Simple accelerator Decoder (address for bytes)
+//0 READ ADDRESS
+#define SIMPLE_ACC_READ_OFFSET 0
+//4 WRITE ADDRESS
+#define SIMPLE_ACC_WRITE_OFFSET 1
+//8 THRESHOLD
+#define SIMPLE_ACC_THRESHOLD_OFFSET 2
+//C READY
+#define SIMPLE_ACC_READY_OFFSET 3
+//10 SIZE
+#define SIMPLE_ACC_SIZE_OFFSET 4
+//14 START
+#define SIMPLE_ACC_START_OFFSET 5
+
+
+
+int main(int argc, char *argv[])
+{
+
+    static uint32_t source_data[TEST_DATA_SIZE] __attribute__ ((aligned (4)));
+    static uint32_t copied_data[TEST_DATA_SIZE] __attribute__ ((aligned (4)));
+    uint32_t threshold_value = 20;
+    volatile static uint32_t *simple_acc =  SIMPLE_ACC_START_ADDRESS;
+
+
+    for(int i=0;i<TEST_DATA_SIZE;i++)
+        source_data[i] = i & 0x1 ? i*3 : i*2;
+
+
+    simple_acc[SIMPLE_ACC_READ_OFFSET] = &source_data[0];
+    simple_acc[SIMPLE_ACC_WRITE_OFFSET] = &copied_data[0];
+    simple_acc[SIMPLE_ACC_THRESHOLD_OFFSET] = threshold_value;
+    simple_acc[SIMPLE_ACC_SIZE_OFFSET] = TEST_DATA_SIZE;
+
+    //START
+    simple_acc[SIMPLE_ACC_START_OFFSET] = 1;
+
+    //UNTIL IT IS NOT READY.. WAIT SIMPLE ACCELERATOR
+    while(simple_acc[SIMPLE_ACC_READY_OFFSET] != 1);
+
+    errors = 0;
+    for(int i=0;i<TEST_DATA_SIZE;i++) {
+        uint32_t expected_data = source_data[i] > threshold_value ? source_data[i] : threshold_value;
+        if(copied_data[i] != expected_data){
+            errors++;
+            PRINTF("copied_data[%d] is %d, expected %d\n\r",i,copied_data[i], expected_data);
+        }
+    }
+
+    if (errors == 0) {
+        PRINTF("Simple Accelerator Successful\n\r");
+        return EXIT_SUCCESS;
+    } else {
+        PRINTF("Simple Accelerator failure: %d errors out of %d data checked\n\r", errors, TEST_DATA_SIZE );
+        return EXIT_FAILURE;
+    }
+
+    return EXIT_SUCCESS;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_flash_write/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_flash_write/main.c
deleted file mode 100644
index a3d273e7..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_flash_write/main.c
+++ /dev/null
@@ -1,490 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "core_v_mini_mcu.h"
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "rv_plic.h"
-#include "rv_plic_regs.h"
-#include "soc_ctrl.h"
-#include "spi_host.h"
-#include "dma.h"
-#include "fast_intr_ctrl.h"
-#include "fast_intr_ctrl_regs.h"
-#include "x-heep.h"
-
-
-#ifdef TARGET_PYNQ_Z2
-    #define USE_SPI_FLASH
-#endif
-/* Test Configurations */
-#define TEST_CIRCULAR
-#define TEST_MEM_2_SPI
-#define TEST_SPI_2_MEM
-
-// These defines are used only to easily change the data types.
-// If not needed, the proper way is using the dma_data_type_t enum.
-#define TEST_DATA_TYPE  DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD
-
-#if TEST_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD
-#define DATA_TYPE    uint8_t
-#elif TEST_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD
-#define DATA_TYPE    uint16_t
-#else
-#define DATA_TYPE    uint32_t
-#endif
-
-
-#ifdef TEST_CIRCULAR
-// WARNING: When using circular mode the amount of WORDS of each cycle needs to be 32 <= x <= 128
-    #define CIRCULAR_CYCLES 4
-    #define COPY_DATA_UNITS 256
-    #define COPY_DATA_PER_CYCLE ( COPY_DATA_UNITS / CIRCULAR_CYCLES )// Flash page size = 256 Bytes
-#else
-    #define COPY_DATA_UNITS 64
-    #define COPY_DATA_PER_CYCLE COPY_DATA_UNITS
-#endif //TEST_CIRCULAR
-
-#define REVERT_24b_ADDR(addr) ((((uint32_t)addr & 0xff0000) >> 16) | ((uint32_t)addr & 0xff00) | (((uint32_t)addr & 0xff) << 16))
-
-#define FLASH_ADDR 0x00008500 // 256B data alignment
-
-#define FLASH_CLK_MAX_HZ (133*1000*1000) // In Hz (133 MHz for the flash w25q128jvsim used in the EPFL Programmer)
-
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-int8_t spi_intr_flag;
-spi_host_t spi_host;
-int8_t cycles;
-
-// Reserve memory array
-DATA_TYPE flash_data[COPY_DATA_UNITS] __attribute__ ((aligned (DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE)))) = { 0 };
-DATA_TYPE copy_data [COPY_DATA_UNITS] __attribute__ ((aligned (DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE)))) = { 0 };
-
-DATA_TYPE *fifo_ptr_tx;
-DATA_TYPE *fifo_ptr_rx;
-
-#ifndef USE_SPI_FLASH
-void fic_irq_spi(void)
-{
-    // Disable SPI interrupts
-    spi_enable_evt_intr(&spi_host, false);
-    spi_enable_rxwm_intr(&spi_host, false);
-    spi_intr_flag = 1;
-}
-#else
-void fic_irq_spi_flash(void)
-{
-    // Disable SPI interrupts
-    // PRINTF("&");
-    spi_enable_evt_intr(&spi_host, false);
-    spi_enable_rxwm_intr(&spi_host, false);
-    spi_intr_flag = 1;
-}
-#endif //USE_SPI_FLASH
-
-#ifdef TEST_CIRCULAR
-void dma_intr_handler_trans_done(void)
-{
-    PRINTF("#");
-    cycles++;
-    if( cycles >= CIRCULAR_CYCLES -1 ) dma_stop_circular();
-}
-#else
-void dma_intr_handler_trans_done(void)
-{
-    PRINTF("#");
-}
-#endif
-
-static inline __attribute__((always_inline)) void spi_config()
-{
-
-/*
-* SPI CONFIGURATIONS
-*/
-#ifndef USE_SPI_FLASH
-    spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
-#else
-    spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
-#endif //USE_SPI_FLASH
-
-    soc_ctrl_t soc_ctrl;
-    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
-    uint32_t core_clk = soc_ctrl_get_frequency(&soc_ctrl);
-
-    // Enable interrupt on processor side
-    // Enable global interrupt for machine-level interrupts
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    // Set mie.MEIE bit to one to enable machine-level fast spi interrupt
-
-
-#ifndef USE_SPI_FLASH
-        const uint32_t mask = 1 << 20;
-#else
-        const uint32_t mask = 1 << 21;
-#endif
-    CSR_SET_BITS(CSR_REG_MIE, mask);
-    spi_intr_flag = 0;
-
-#ifdef USE_SPI_FLASH
-        // Select SPI host as SPI output
-        soc_ctrl_select_spi_host(&soc_ctrl);
-#endif // USE_SPI_FLASH
-
-
-    CSR_SET_BITS(CSR_REG_MIE, mask);
-
-    // Enable SPI host device
-    spi_set_enable(&spi_host, true);
-    // Enable SPI output
-    spi_output_enable(&spi_host, true);
-
-    // SPI and SPI_FLASH are the same IP so same register map
-    fifo_ptr_tx = spi_host.base_addr.base + SPI_HOST_TXDATA_REG_OFFSET;
-    fifo_ptr_rx = spi_host.base_addr.base + SPI_HOST_RXDATA_REG_OFFSET;
-
-    // Configure SPI clock
-    // SPI clk freq = 1/2 core clk freq when clk_div = 0
-    // SPI_CLK = CORE_CLK/(2 + 2 * CLK_DIV) <= CLK_MAX => CLK_DIV > (CORE_CLK/CLK_MAX - 2)/2
-    uint16_t clk_div = 0;
-    if(FLASH_CLK_MAX_HZ < core_clk/2){
-        clk_div = (core_clk/(FLASH_CLK_MAX_HZ) - 2)/2; // The value is truncated
-        if (core_clk/(2 + 2 * clk_div) > FLASH_CLK_MAX_HZ) clk_div += 1; // Adjust if the truncation was not 0
-    }
-    // SPI Configuration
-    // Configure chip 0 (flash memory)
-    const uint32_t chip_cfg = spi_create_configopts((spi_configopts_t){
-        .clkdiv     = clk_div,
-        .csnidle    = 0xF,
-        .csntrail   = 0xF,
-        .csnlead    = 0xF,
-        .fullcyc    = false,
-        .cpha       = 0,
-        .cpol       = 0
-    });
-    spi_set_configopts(&spi_host, 0, chip_cfg);
-    spi_set_csid(&spi_host, 0);
-
-    // Reset
-    const uint32_t reset_cmd = 0xFFFFFFFF;
-    spi_write_word(&spi_host, reset_cmd);
-    const uint32_t cmd_reset = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_reset);
-    spi_wait_for_ready(&spi_host);
-    spi_set_rx_watermark(&spi_host,1);
-
-    // Power up flash
-    const uint32_t powerup_byte_cmd = 0xab;
-    spi_write_word(&spi_host, powerup_byte_cmd);
-    const uint32_t cmd_powerup = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_powerup);
-    spi_wait_for_ready(&spi_host);
-
-    // Write enable
-    const uint32_t write_enable_cmd = 0x06;
-    spi_write_word(&spi_host, write_enable_cmd);
-    const uint32_t cmd_write_en = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_write_en);
-    spi_wait_for_ready(&spi_host);
-
-    // Write command
-    const uint32_t write_byte_cmd = ((FLASH_ADDR << 8) | 0x02); // Program Page + addr
-    spi_write_word(&spi_host, write_byte_cmd);
-    const uint32_t cmd_write = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = true,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_write);
-    spi_wait_for_ready(&spi_host);
-
-}
-
-
-static inline __attribute__((always_inline)) void spi_wait_4_resp()
-{
-    // Check status register status waiting for ready
-    bool flash_busy = true;
-    uint8_t flash_resp[4] = {0xff,0xff,0xff,0xff};
-    while(flash_busy){
-        uint32_t flash_cmd = 0x00000005; // [CMD] Read status register
-        spi_write_word(&spi_host, flash_cmd); // Push TX buffer
-        uint32_t spi_status_cmd = spi_create_command((spi_command_t){
-            .len        = 0,
-            .csaat      = true,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirTxOnly
-        });
-        uint32_t spi_status_read_cmd = spi_create_command((spi_command_t){
-            .len        = 0,
-            .csaat      = false,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirRxOnly
-        });
-        spi_set_command(&spi_host, spi_status_cmd);
-        spi_wait_for_ready(&spi_host);
-        spi_set_command(&spi_host, spi_status_read_cmd);
-        spi_wait_for_ready(&spi_host);
-        spi_wait_for_rx_watermark(&spi_host);
-        spi_read_word(&spi_host, &flash_resp[0]);
-        if ((flash_resp[0] & 0x01) == 0) flash_busy = false;
-    }
-}
-
-int main(int argc, char *argv[])
-{
-
-#ifdef TARGET_SIM
-  #pragma message("This app does not allow Flash write operations in simulation!")
-    PRINTF("Flash writes are not permitted during Simulation, only on FPGA\n");
-    return EXIT_SUCCESS;
-#endif
-
-    soc_ctrl_t soc_ctrl;
-    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
-
-#ifdef USE_SPI_FLASH
-   if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO )
-    {
-        PRINTF("This application cannot work with the memory mapped SPI FLASH module - do not use the FLASH_EXEC linker script for this application\n");
-        return EXIT_SUCCESS;
-    }
-#endif
-    spi_config();
-    dma_init(NULL);
-
-    dma_config_flags_t res;
-
-    for( DATA_TYPE i = 0; i < COPY_DATA_PER_CYCLE; i ++ )
-    {
-        ((DATA_TYPE*)flash_data)[i] = (DATA_TYPE) i;
-    }
-
-#ifdef TEST_MEM_2_SPI
-
-    PRINTF("\n\n\r======================================\n\n\r");
-    PRINTF(" MEM -> -> DMA -> -> SPI -> -> FLASH ");
-    PRINTF("\n\n\r======================================\n\n\r");
-
-#ifndef USE_SPI_FLASH
-    const uint8_t slot = DMA_TRIG_SLOT_SPI_TX; // The DMA will wait for the SPI TX FIFO ready signal
-#else
-    const uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_TX; // The DMA will wait for the SPI FLASH TX FIFO ready signal
-#endif //USE_SPI_FLASH
-
-    static dma_target_t tgt1= {
-        .ptr = flash_data,
-        .inc_du = 1,
-        .size_du = COPY_DATA_PER_CYCLE,
-        .trig = DMA_TRIG_MEMORY,
-        .type = TEST_DATA_TYPE,
-    };
-
-    static dma_target_t tgt2= {
-        .inc_du = 0,
-        .size_du = COPY_DATA_PER_CYCLE,
-        .trig = slot,
-        .type = TEST_DATA_TYPE,
-    };
-
-    tgt2.ptr = fifo_ptr_tx; // This is necessary because fifo_ptr_tx is not a constant, and therefore cannot be used as initializer element.
-
-    static dma_trans_t trans = {
-                            .src = &tgt1,
-                            .dst = &tgt2,
-                            .mode = DMA_TRANS_MODE_SINGLE,
-                            .win_du = 0,
-                            .end = DMA_TRANS_END_INTR,
-                            };
-
-#ifdef TEST_CIRCULAR
-    trans.mode = DMA_TRANS_MODE_CIRCULAR;
-    cycles = 0;
-#endif // TEST_CIRCULAR
-
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("tran: %u \n\r", res);
-
-    res = dma_load_transaction(&trans);
-    PRINTF("load: %u \n\r", res);
-
-    res = dma_launch(&trans);
-
-    spi_intr_flag = 0;
-    // Wait for the first data to arrive to the TX FIFO before enabling interrupt
-    spi_wait_for_tx_not_empty(&spi_host);
-    // Enable event interrupt
-    spi_enable_evt_intr(&spi_host, true);
-    // Enable TX empty interrupt
-    spi_enable_txempty_intr(&spi_host, true);
-
-    const uint32_t cmd_write_tx = spi_create_command((spi_command_t){
-        .len        = COPY_DATA_UNITS*DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE) - 1,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_write_tx);
-    spi_wait_for_ready(&spi_host);
-
-    // Wait for SPI interrupt
-    while(spi_intr_flag == 0) {
-        wait_for_interrupt();
-    }
-    PRINTF("triggered\n\r");
-
-    spi_wait_4_resp();
-
-    PRINTF("%d Bytes written in Flash at @ 0x%08x \n\r", COPY_DATA_UNITS*DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE), FLASH_ADDR);
-
-
-#endif //TEST_SPI_2_MEM
-
-#ifdef TEST_SPI_2_MEM
-
-    PRINTF("\n\n\r======================================\n\n\r");
-    PRINTF(" MEM <- <- DMA <- <- SPI <- <- FLASH ");
-    PRINTF("\n\n\r======================================\n\n\r");
-
-#ifndef USE_SPI_FLASH
-    const uint8_t slot2 = DMA_TRIG_SLOT_SPI_RX; // The DMA will wait for the SPI TX FIFO ready signal
-#else
-    const uint8_t slot2 = DMA_TRIG_SLOT_SPI_FLASH_RX; // The DMA will wait for the SPI FLASH TX FIFO ready signal
-    #endif
-
-    static dma_target_t tgt3= {
-    .ptr = copy_data,
-    .inc_du = 1,
-    // Because the data type needs to be WORD the size needs to be normalized.
-    .size_du = COPY_DATA_PER_CYCLE*DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE)/DMA_DATA_TYPE_2_SIZE(DMA_DATA_TYPE_WORD),
-    .trig = DMA_TRIG_MEMORY,
-    .type = DMA_DATA_TYPE_WORD, // Only possible to read word-wise from SPI
-    };
-
-    static dma_target_t tgt4= {
-        .inc_du = 0,
-        // Because the data type needs to be WORD the size needs to be normalized.
-        .size_du = COPY_DATA_PER_CYCLE*DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE)/DMA_DATA_TYPE_2_SIZE(DMA_DATA_TYPE_WORD),
-        .trig = slot2,
-        .type = DMA_DATA_TYPE_WORD,
-    };
-    tgt4.ptr = fifo_ptr_rx;
-
-    static dma_trans_t trans2 = {
-                            .src = &tgt4,
-                            .dst = &tgt3,
-                            .end = DMA_TRANS_END_INTR,
-                            };
-
-    res = dma_validate_transaction( &trans2, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("tran: %u \n\r", res);
-
-    res = dma_load_transaction(&trans2);
-    PRINTF("load: %u \n\r", res);
-
-    // The address bytes sent through the SPI to the Flash are in reverse order
-    const int32_t read_byte_cmd = ((REVERT_24b_ADDR(FLASH_ADDR) << 8) | 0x03);
-
-    // Fill TX FIFO with TX data (read command + 3B address)
-    spi_write_word(&spi_host, read_byte_cmd);
-    // Wait for readiness to process commands
-    spi_wait_for_ready(&spi_host);
-
-    // Load command FIFO with read command (1 Byte at single speed)
-    const uint32_t cmd_read = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = true,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_read);
-    spi_wait_for_ready(&spi_host);
-
-    const uint32_t cmd_read_rx = spi_create_command((spi_command_t){
-        .len        = COPY_DATA_UNITS*DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE) - 1,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirRxOnly
-    });
-    spi_set_command(&spi_host, cmd_read_rx);
-    spi_wait_for_ready(&spi_host);
-
-    res = dma_launch(&trans2);
-
-    while( ! dma_is_ready() ){
-        /* wait_for_interrupt(); For small buffer sizes the interrupt arrives before going to wfi(); */
-    };
-
-    PRINTF("triggered!\n\r");
-
-    // Power down flash
-    const uint32_t powerdown_byte_cmd = 0xb9;
-    spi_write_word(&spi_host, powerdown_byte_cmd);
-    const uint32_t cmd_powerdown = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_powerdown);
-    spi_wait_for_ready(&spi_host);
-
-    // The data is already in memory -- Check results
-    PRINTF("ram vs flash...\n\r");
-
-    int i;
-    uint32_t errors = 0;
-    uint32_t count = 0;
-    for (i = 0; i<COPY_DATA_UNITS*DMA_DATA_TYPE_2_SIZE(TEST_DATA_TYPE); i++) {
-        if(((uint8_t*)flash_data)[i] != ((uint8_t*)copy_data)[i]) {
-            PRINTF("@%08x-@%08x : %02d\t!=\t%02d\n\r" , &((uint8_t*)flash_data)[i] , &((uint8_t*)copy_data)[i], ((uint8_t*)flash_data)[i], ((uint8_t*)copy_data)[i]);
-            errors++;
-        }
-        count++;
-    }
-
-    if (errors == 0) {
-        PRINTF("success! (Data units checked: %d)\n\r", count);
-    } else {
-        PRINTF("Failure, %d errors! (Out of %d)\n\r", errors, count);
-        return EXIT_FAILURE;
-    }
-
-#endif //TEST_MEM_2_SPI
-
-    return EXIT_SUCCESS;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host/main.c
deleted file mode 100644
index c2436489..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host/main.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "core_v_mini_mcu.h"
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "soc_ctrl.h"
-#include "spi_host.h"
-#include "fast_intr_ctrl.h"
-#include "fast_intr_ctrl_regs.h"
-#include "x-heep.h"
-
-#ifdef TARGET_PYNQ_Z2
-    #define USE_SPI_FLASH
-#endif
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-// Simple example to check the SPI host peripheral is working. It checks the ram and flash have the same content
-#define REVERT_24b_ADDR(addr) ((((uint32_t)(addr) & 0xff0000) >> 16) | ((uint32_t)(addr) & 0xff00) | (((uint32_t)(addr) & 0xff) << 16))
-
-#define FLASH_CLK_MAX_HZ (133*1000*1000) // In Hz (133 MHz for the flash w25q128jvsim used in the EPFL Programmer)
-
-volatile int8_t spi_intr_flag;
-spi_host_t spi_host;
-uint32_t flash_data[8];
-uint32_t flash_original[8] = {1};
-
-#ifndef USE_SPI_FLASH
-void fic_irq_spi(void)
-{
-    // Disable SPI interrupts
-    spi_enable_evt_intr(&spi_host, false);
-    spi_enable_rxwm_intr(&spi_host, false);
-    spi_intr_flag = 1;
-}
-#else
-void fic_irq_spi_flash(void)
-{
-    // Disable SPI interrupts
-    spi_enable_evt_intr(&spi_host, false);
-    spi_enable_rxwm_intr(&spi_host, false);
-    spi_intr_flag = 1;
-}
-#endif
-
-int main(int argc, char *argv[])
-{
-
-    soc_ctrl_t soc_ctrl;
-    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
-    uint32_t read_byte_cmd = ((REVERT_24b_ADDR(flash_original) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-
-   if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO )
-    {
-#ifdef USE_SPI_FLASH
-        PRINTF("This application cannot work with the memory mapped SPI FLASH module - do not use the FLASH_EXEC linker script for this application\n");
-        return EXIT_SUCCESS;
-#else
-        /*
-            if we are using in SIMULATION the SPIMMIO from Yosys, then the flash_original data is different
-            as the compilation is done differently, so we will store there the first WORDs of code mapped at the beginning of the FLASH
-        */
-        uint32_t* ptr_flash = (uint32_t*)FLASH_MEM_START_ADDRESS;
-        for(int i =0; i < 8 ; i++){
-            flash_original[i] = ptr_flash[i];
-        }
-        // we read the data from the FLASH address 0x0, which corresponds to FLASH_MEM_START_ADDRESS
-        read_byte_cmd = ((REVERT_24b_ADDR(0x0) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-
-#endif
-
-    }
-
-
-    // spi_host_t spi_host;
-    #ifndef USE_SPI_FLASH
-        spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
-    #else
-        spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
-    #endif
-
-    uint32_t core_clk = soc_ctrl_get_frequency(&soc_ctrl);
-
-    // Enable interrupt on processor side
-    // Enable global interrupt for machine-level interrupts
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    // Set mie.MEIE bit to one to enable machine-level fast spi interrupt
-    #ifndef USE_SPI_FLASH
-        const uint32_t mask = 1 << 20;
-    #else
-        const uint32_t mask = 1 << 21;
-    #endif
-    CSR_SET_BITS(CSR_REG_MIE, mask);
-    spi_intr_flag = 0;
-
-    #ifdef USE_SPI_FLASH
-        // Select SPI host as SPI output
-        soc_ctrl_select_spi_host(&soc_ctrl);
-    #endif
-
-    // Enable SPI host device
-    spi_set_enable(&spi_host, true);
-
-    // Enable event interrupt
-    spi_enable_evt_intr(&spi_host, true);
-    // Enable RX watermark interrupt
-    spi_enable_rxwm_intr(&spi_host, true);
-    // Enable SPI output
-    spi_output_enable(&spi_host, true);
-
-    // Configure SPI clock
-    // SPI clk freq = 1/2 core clk freq when clk_div = 0
-    // SPI_CLK = CORE_CLK/(2 + 2 * CLK_DIV) <= CLK_MAX => CLK_DIV > (CORE_CLK/CLK_MAX - 2)/2
-    uint16_t clk_div = 0;
-    if(FLASH_CLK_MAX_HZ < core_clk/2){
-        clk_div = (core_clk/(FLASH_CLK_MAX_HZ) - 2)/2; // The value is truncated
-        if (core_clk/(2 + 2 * clk_div) > FLASH_CLK_MAX_HZ) clk_div += 1; // Adjust if the truncation was not 0
-    }
-    // SPI Configuration
-    // Configure chip 0 (flash memory)
-    const uint32_t chip_cfg = spi_create_configopts((spi_configopts_t){
-        .clkdiv     = clk_div,
-        .csnidle    = 0xF,
-        .csntrail   = 0xF,
-        .csnlead    = 0xF,
-        .fullcyc    = false,
-        .cpha       = 0,
-        .cpol       = 0
-    });
-    spi_set_configopts(&spi_host, 0, chip_cfg);
-    spi_set_csid(&spi_host, 0);
-
-    // Set RX watermark to 8 word
-    spi_set_rx_watermark(&spi_host, 8);
-
-    uint32_t *flash_data_ptr = flash_data[0];
-
-    // Power up flash
-    const uint32_t powerup_byte_cmd = 0xab;
-    spi_write_word(&spi_host, powerup_byte_cmd);
-    // Load command FIFO with command (1 Byte at single speed)
-    const uint32_t cmd_powerup = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_powerup);
-    spi_wait_for_ready(&spi_host);
-
-    volatile uint32_t data_addr = flash_original;
-
-
-    // Fill TX FIFO with TX data (read command + 3B address)
-    spi_write_word(&spi_host, read_byte_cmd);
-    // Wait for readiness to process commands
-    spi_wait_for_ready(&spi_host);
-
-    ////////////////////////////////////////////////////////////////
-
-    // // Load command FIFO with read command (1 Byte at single speed)
-    // const uint32_t cmd_read = spi_create_command((spi_command_t){
-    //     .len        = 0,
-    //     .csaat      = true,
-    //     .speed      = kSpiSpeedStandard,
-    //     .direction  = kSpiDirTxOnly
-    // });
-    // spi_set_command(&spi_host, cmd_read);
-    // spi_wait_for_ready(&spi_host);
-    // // Load command FIFO with read address (3 Byte at single speed)
-    // const uint32_t cmd_addr = spi_create_command((spi_command_t){
-    //     .len        = 2,
-    //     .csaat      = true,
-    //     .speed      = kSpiSpeedStandard,
-    //     .direction  = kSpiDirTxOnly
-    // });
-    // spi_set_command(&spi_host, cmd_addr);
-    // spi_wait_for_ready(&spi_host);
-
-    // OR
-
-    // Load command FIFO with read command (1 Byte at single speed)
-    const uint32_t cmd_read = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = true,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_read);
-    spi_wait_for_ready(&spi_host);
-
-    ////////////////////////////////////////////////////////////////
-
-    const uint32_t cmd_read_rx = spi_create_command((spi_command_t){
-        .len        = 31,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirRxOnly
-    });
-    spi_set_command(&spi_host, cmd_read_rx);
-    spi_wait_for_ready(&spi_host);
-
-    // Wait transaction is finished (polling register)
-    // spi_wait_for_rx_watermark(&spi_host);
-    // or wait for SPI interrupt
-    PRINTF("Waiting for SPI...\n\r");
-
-    while( spi_intr_flag == 0 ) {
-        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-
-        if( spi_intr_flag == 0 )
-            wait_for_interrupt();
-
-        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    }
-
-    // Enable event interrupt
-    spi_enable_evt_intr(&spi_host, true);
-    // Enable RX watermark interrupt
-    spi_enable_rxwm_intr(&spi_host, true);
-
-    // Read data from SPI RX FIFO
-    for (int i=0; i<8; i++) {
-        spi_read_word(&spi_host, &flash_data[i]);
-    }
-
-    PRINTF("flash vs ram...\n\r");
-
-    uint32_t errors = 0;
-    uint32_t* ram_ptr = flash_original;
-    for (int i=0; i<8; i++) {
-        if(flash_data[i] != *ram_ptr) {
-            PRINTF("@%x : %x != %x\n\r", ram_ptr, flash_data[i], *ram_ptr);
-            errors++;
-        }
-        ram_ptr++;
-    }
-
-    if (errors == 0) {
-        PRINTF("success!\n\r");
-    } else {
-        PRINTF("failure, %d errors!\n\r", errors);
-        return EXIT_FAILURE;
-    }
-
-    return EXIT_SUCCESS;
-
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma/main.c
deleted file mode 100644
index de6ab165..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma/main.c
+++ /dev/null
@@ -1,312 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "core_v_mini_mcu.h"
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "soc_ctrl.h"
-#include "spi_host.h"
-#include "dma.h"
-#include "fast_intr_ctrl.h"
-#include "fast_intr_ctrl_regs.h"
-#include "x-heep.h"
-
-#ifdef TARGET_PYNQ_Z2
-    #define USE_SPI_FLASH
-#endif
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-// Type of data frome the SPI. For types different than words the SPI data is requested in separate transactions
-// word(0), half-word(1), byte(2,3)
-#define SPI_DATA_TYPE DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD
-
-// Number of elements to copy
-#define COPY_DATA_NUM 16
-
-#define FLASH_CLK_MAX_HZ (133*1000*1000) // In Hz (133 MHz for the flash w25q128jvsim used in the EPFL Programmer)
-
-#define REVERT_24b_ADDR(addr) ((((uint32_t)(addr) & 0xff0000) >> 16) | ((uint32_t)(addr) & 0xff00) | (((uint32_t)(addr) & 0xff) << 16))
-
-volatile int8_t dma_intr_flag;
-spi_host_t spi_host;
-
-void dma_intr_handler_trans_done(void)
-{
-    PRINTF("Non-weak implementation of a DMA interrupt\n\r");
-    dma_intr_flag = 1;
-}
-
-// Reserve memory array
-uint32_t flash_data[COPY_DATA_NUM] __attribute__ ((aligned (4))) = {0x76543210,0xfedcba98,0x579a6f90,0x657d5bee,0x758ee41f,0x01234567,0xfedbca98,0x89abcdef,0x679852fe,0xff8252bb,0x763b4521,0x6875adaa,0x09ac65bb,0x666ba334,0x44556677,0x0000ba98};
-uint32_t copy_data[COPY_DATA_NUM] __attribute__ ((aligned (4)))  = { 0 };
-
-#if SPI_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD
-    #define DATA_TYPE uint32_t
-#elif SPI_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD
-    #define DATA_TYPE uint16_t
-#else
-    #define DATA_TYPE uint8_t
-#endif
-
-#define COPY_DATA_TYPE (COPY_DATA_NUM/(sizeof(uint32_t)/sizeof(DATA_TYPE)))
-
-
-int main(int argc, char *argv[])
-{
-
-    soc_ctrl_t soc_ctrl;
-    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
-    uint32_t read_byte_cmd;
-
-    if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO )
-    {
-#ifdef USE_SPI_FLASH
-        PRINTF("This application cannot work with the memory mapped SPI FLASH module - do not use the FLASH_EXEC linker script for this application\n");
-        return EXIT_SUCCESS;
-#else
-        /*
-            if we are using in SIMULATION the SPIMMIO from Yosys, then the flash_original data is different
-            as the compilation is done differently, so we will store there the first WORDs of code mapped at the beginning of the FLASH
-        */
-        uint32_t* ptr_flash = (uint32_t*)FLASH_MEM_START_ADDRESS;
-        for(int i =0; i < COPY_DATA_NUM ; i++){
-            flash_data[i] = ptr_flash[i];
-        }
-#endif
-
-    }
-
-
-    #ifndef USE_SPI_FLASH
-        spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
-    #else
-        spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
-    #endif
-
-    uint32_t core_clk = soc_ctrl_get_frequency(&soc_ctrl);
-
-    // Enable interrupt on processor side
-    // Enable global interrupt for machine-level interrupts
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-
-    #ifdef USE_SPI_FLASH
-        // Select SPI host as SPI output
-        soc_ctrl_select_spi_host(&soc_ctrl);
-    #endif
-
-    // Enable SPI host device
-    spi_set_enable(&spi_host, true);
-    // Enable SPI output
-    spi_output_enable(&spi_host, true);
-
-    // SPI and SPI_FLASH are the same IP so same register map
-    uint32_t *fifo_ptr_rx = spi_host.base_addr.base + SPI_HOST_RXDATA_REG_OFFSET;
-
-
-    // DMA CONFIGURATION
-    PRINTF("---- TEST ---- \n\r");
-    dma_init(NULL);
-
-
-    #ifndef USE_SPI_FLASH
-        uint8_t slot = DMA_TRIG_SLOT_SPI_RX;  // The DMA will wait for the SPI RX FIFO valid signal
-    #else
-        uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_RX; // The DMA will wait for the SPI FLASH RX FIFO valid signal
-    #endif
-
-    static dma_target_t tgt_src = {
-        .inc_du = 0,
-        .size_du = COPY_DATA_NUM,
-        .type = SPI_DATA_TYPE,
-    };
-    tgt_src.ptr = fifo_ptr_rx; // Necessary outside 'cause its not a const.
-    tgt_src.trig = slot;// Necessary outside 'cause its not a const.
-
-    static dma_target_t tgt_dst = {
-        .ptr = copy_data,
-        .inc_du = 1,
-        .type = SPI_DATA_TYPE,
-        .trig = DMA_TRIG_MEMORY,
-    };
-    static dma_trans_t trans = {
-        .src = &tgt_src,
-        .dst = &tgt_dst,
-        .end = DMA_TRANS_END_INTR,
-    };
-
-    dma_config_flags_t res;
-
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("Result - tgt trans: %u\n\r", res );
-    res = dma_load_transaction(&trans);
-    PRINTF("Result - tgt load: %u\n\r", res );
-
-    // Configure SPI clock
-    // SPI clk freq = 1/2 core clk freq when clk_div = 0
-    // SPI_CLK = CORE_CLK/(2 + 2 * CLK_DIV) <= CLK_MAX => CLK_DIV > (CORE_CLK/CLK_MAX - 2)/2
-    uint16_t clk_div = 0;
-    if(FLASH_CLK_MAX_HZ < core_clk/2){
-        clk_div = (core_clk/(FLASH_CLK_MAX_HZ) - 2)/2; // The value is truncated
-        if (core_clk/(2 + 2 * clk_div) > FLASH_CLK_MAX_HZ) clk_div += 1; // Adjust if the truncation was not 0
-    }
-    // SPI Configuration
-    // Configure chip 0 (flash memory)
-    const uint32_t chip_cfg = spi_create_configopts((spi_configopts_t){
-        .clkdiv     = clk_div,
-        .csnidle    = 0xF,
-        .csntrail   = 0xF,
-        .csnlead    = 0xF,
-        .fullcyc    = false,
-        .cpha       = 0,
-        .cpol       = 0
-    });
-    spi_set_configopts(&spi_host, 0, chip_cfg);
-    spi_set_csid(&spi_host, 0);
-
-    // Reset
-    const uint32_t reset_cmd = 0xFFFFFFFF;
-    spi_write_word(&spi_host, reset_cmd);
-    const uint32_t cmd_reset = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_reset);
-    spi_wait_for_ready(&spi_host);
-
-    // Power up flash
-    const uint32_t powerup_byte_cmd = 0xab;
-    spi_write_word(&spi_host, powerup_byte_cmd);
-    const uint32_t cmd_powerup = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_powerup);
-    spi_wait_for_ready(&spi_host);
-
-    // Load command FIFO with read command (1 Byte at single speed)
-    const uint32_t cmd_read = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = true,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-
-    dma_intr_flag = 0;
-    res = dma_launch(&trans);
-    PRINTF("launched!\n\r");
-
-    #if SPI_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD
-
-        if(get_spi_flash_mode(&soc_ctrl) != SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO)
-            read_byte_cmd = ((REVERT_24b_ADDR(flash_data) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-        else
-            // we read the data from the FLASH address 0x0, which corresponds to FLASH_MEM_START_ADDRESS
-            read_byte_cmd = ((REVERT_24b_ADDR(0x0) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-
-        const uint32_t cmd_read_rx = spi_create_command((spi_command_t){ // Single transaction
-            .len        = COPY_DATA_NUM*sizeof(DATA_TYPE) - 1, // In bytes - 1
-            .csaat      = false,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirRxOnly
-        });
-        spi_write_word(&spi_host, read_byte_cmd); // Fill TX FIFO with TX data (read command + 3B address)
-        spi_wait_for_ready(&spi_host); // Wait for readiness to process commands
-        spi_set_command(&spi_host, cmd_read); // Send read command to the external device through SPI
-        spi_wait_for_ready(&spi_host);
-        spi_set_command(&spi_host, cmd_read_rx); // Receive data in RX
-        spi_wait_for_ready(&spi_host);
-    #else
-        const uint32_t cmd_read_rx = spi_create_command((spi_command_t){ // Multiple transactions of the data type
-            .len        = (sizeof(DATA_TYPE) - 1),
-            .csaat      = false,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirRxOnly
-        });
-        DATA_TYPE* flash_ptr = (DATA_TYPE *)flash_data;
-        for (int i = 0; i<COPY_DATA_NUM; i++) { // Multiple 8 or 16-bit transactions, just to try a new mode, we could treat it as int32
-            // Request the same data multiple times
-            if(get_spi_flash_mode(&soc_ctrl) != SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO)
-                read_byte_cmd = ((REVERT_24b_ADDR(&flash_ptr[i]) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-            else
-                read_byte_cmd = ((REVERT_24b_ADDR(i) << 8) | 0x03);
-            spi_write_word(&spi_host, read_byte_cmd); // Fill TX FIFO with TX data (read command + 3B address)
-            spi_wait_for_ready(&spi_host); // Wait for readiness to process commands
-            spi_set_command(&spi_host, cmd_read); // Send read command to the external device through SPI
-            spi_wait_for_ready(&spi_host);
-            spi_set_command(&spi_host, cmd_read_rx); // Receive data in RX
-            spi_wait_for_ready(&spi_host);
-        }
-    #endif
-
-    // Wait for DMA interrupt
-    if( trans.end == DMA_TRANS_END_POLLING ){
-        while( ! dma_is_ready() ){};
-    } else{
-        PRINTF("Waiting for the DMA interrupt...\n\r");
-        while( dma_intr_flag == 0 ) {
-            CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-
-            if( dma_intr_flag == 0 )
-                wait_for_interrupt();
-
-            CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-        }
-        PRINTF("triggered!\n\r");
-    }
-
-
-    // Power down flash
-    const uint32_t powerdown_byte_cmd = 0xb9;
-    spi_write_word(&spi_host, powerdown_byte_cmd);
-    const uint32_t cmd_powerdown = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_powerdown);
-    spi_wait_for_ready(&spi_host);
-
-    // The data is already in memory -- Check results
-    PRINTF("flash vs ram...\n\r");
-
-    uint32_t errors = 0;
-    uint32_t count = 0;
-    for (int i = 0; i<COPY_DATA_TYPE; i++) {
-        if(flash_data[i] != copy_data[i]) {
-            PRINTF("@%08x-@%08x : %02x != %02x\n\r" , &flash_data[i] , &copy_data[i], flash_data[i], copy_data[i]);
-            errors++;
-        }
-        count++;
-    }
-
-    if (errors == 0) {
-        PRINTF("success! (bytes checked: %d)\n\r", count*sizeof(DATA_TYPE));
-    } else {
-        PRINTF("failure, %d errors! (Out of %d)\n\r", errors, count);
-        return EXIT_FAILURE;
-    }
-    return EXIT_SUCCESS;
-}
-
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c
index 6f80e5b4..0f1a444a 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c
@@ -70,13 +70,16 @@ uint32_t copy_data[COPY_DATA_NUM] __attribute__ ((aligned (4)))  = { 0 };
 
 #define COPY_DATA_TYPE (COPY_DATA_NUM/(sizeof(uint32_t)/sizeof(DATA_TYPE)))
 
-
 int main(int argc, char *argv[])
 {
 
     soc_ctrl_t soc_ctrl;
     soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
     uint32_t read_byte_cmd;
+    uint32_t* flash_data_lma = flash_data;
+    //set MS 8 bits to 0 as the flash only uses 24b
+    flash_data_lma = (uint32_t*) ((uint32_t)(flash_data_lma) & 0x00FFFFFF);
+
 
    if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO )
     {
@@ -237,7 +240,7 @@ int main(int argc, char *argv[])
 
     #if SPI_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD
         if(get_spi_flash_mode(&soc_ctrl) != SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO)
-            read_byte_cmd = ((REVERT_24b_ADDR(flash_data) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
+            read_byte_cmd = ((REVERT_24b_ADDR(flash_data_lma) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
         else
             // we read the data from the FLASH address 0x0, which corresponds to FLASH_MEM_START_ADDRESS
             read_byte_cmd = ((REVERT_24b_ADDR(0x0) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
@@ -260,7 +263,7 @@ int main(int argc, char *argv[])
             .speed      = kSpiSpeedStandard,
             .direction  = kSpiDirRxOnly
         });
-        DATA_TYPE* flash_ptr = (DATA_TYPE *)flash_data;
+        DATA_TYPE* flash_ptr = (DATA_TYPE *)flash_data_lma;
         for (int i = 0; i<COPY_DATA_NUM; i++) { // Multiple 8 or 16-bit transactions, just to try a new mode, we could treat it as int32
             // Request the same data multiple times
             if(get_spi_flash_mode(&soc_ctrl) != SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/buffer.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/buffer.h
new file mode 100644
index 00000000..f02f556b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/buffer.h
@@ -0,0 +1,35 @@
+uint32_t flash_original_1024B[256] = {
+    0x76543211, 0xfedcba99, 0x579a6f91, 0x657d5bef, 0x758ee420, 0x01234568, 0xfedbca97, 0x89abde00,
+    0x76543212, 0xfedcba9a, 0x579a6f92, 0x657d5bf0, 0x758ee421, 0x01234569, 0xfedbca98, 0x89abde01,
+    0x76543213, 0xfedcba9b, 0x579a6f93, 0x657d5bf1, 0x758ee422, 0x0123456a, 0xfedbca99, 0x89abde02,
+    0x76543214, 0xfedcba9c, 0x579a6f94, 0x657d5bf2, 0x758ee423, 0x0123456b, 0xfedbca9a, 0x89abde03,
+    0x76543215, 0xfedcba9d, 0x579a6f95, 0x657d5bf3, 0x758ee424, 0x0123456c, 0xfedbca9b, 0x89abde04,
+    0x76543216, 0xfedcba9e, 0x579a6f96, 0x657d5bf4, 0x758ee425, 0x0123456d, 0xfedbca9c, 0x89abde05,
+    0x76543217, 0xfedcba9f, 0x579a6f97, 0x657d5bf5, 0x758ee426, 0x0123456e, 0xfedbca9d, 0x89abde06,
+    0x76543218, 0xfedcbaa0, 0x579a6f98, 0x657d5bf6, 0x758ee427, 0x0123456f, 0xfedbca9e, 0x89abde07,
+    0x76543219, 0xfedcbaa1, 0x579a6f99, 0x657d5bf7, 0x758ee428, 0x01234570, 0xfedbca9f, 0x89abde08,
+    0x7654321a, 0xfedcbaa2, 0x579a6f9a, 0x657d5bf8, 0x758ee429, 0x01234571, 0xfedbcaa0, 0x89abde09,
+    0x7654321b, 0xfedcbaa3, 0x579a6f9b, 0x657d5bf9, 0x758ee42a, 0x01234572, 0xfedbcaa1, 0x89abde0a,
+    0x7654321c, 0xfedcbaa4, 0x579a6f9c, 0x657d5bfa, 0x758ee42b, 0x01234573, 0xfedbcaa2, 0x89abde0b,
+    0x7654321d, 0xfedcbaa5, 0x579a6f9d, 0x657d5bfb, 0x758ee42c, 0x01234574, 0xfedbcaa3, 0x89abde0c,
+    0x7654321e, 0xfedcbaa6, 0x579a6f9e, 0x657d5bfc, 0x758ee42d, 0x01234575, 0xfedbcaa4, 0x89abde0d,
+    0x7654321f, 0xfedcbaa7, 0x579a6f9f, 0x657d5bfd, 0x758ee42e, 0x01234576, 0xfedbcaa5, 0x89abde0e,
+    0x76543220, 0xfedcbaa8, 0x579a6fa0, 0x657d5bfe, 0x758ee42f, 0x01234577, 0xfedbcaa6, 0x89abde0f,
+    0x76543221, 0xfedcbaa9, 0x579a6fa1, 0x657d5bff, 0x758ee430, 0x01234578, 0xfadbcaa7, 0x89abde10,
+    0x76543222, 0xfedcbaaa, 0x579a6fa2, 0x657d5c00, 0x758ee431, 0x01234579, 0xfadbcaa8, 0x89abde11,
+    0x76543223, 0xfedcbaab, 0x579a6fa3, 0x657d5c01, 0x758ee432, 0x0123457a, 0xfadbcaa9, 0x89abde12,
+    0x76543224, 0xfedcbaac, 0x579a6fa4, 0x657d5c02, 0x758ee433, 0x0123457b, 0xfadbcaaa, 0x89abde13,
+    0x76543225, 0xfedcbaad, 0x579a6fa5, 0x657d5c03, 0x758ee434, 0x0123457c, 0xfadbcaab, 0x89abde14,
+    0x76543226, 0xfedcbaae, 0x579a6fa6, 0x657d5c04, 0x758ee435, 0x0123457d, 0xfadbcaac, 0x89abde15,
+    0x76543227, 0xfedcbaaf, 0x579a6fa7, 0x657d5c05, 0x758ee436, 0x0123457e, 0xfadbcaad, 0x89abde16,
+    0x76543228, 0xfedcbab0, 0x579a6fa8, 0x657d5c06, 0x758ee437, 0x0123457f, 0xfadbcaae, 0x89abde17,
+    0x76543220, 0xfedcbaa8, 0x579a6fa0, 0x657d5bfe, 0x758ee42f, 0x01234577, 0xfedbcaa6, 0x89abde0f,
+    0x76543221, 0xfedcbaa9, 0x579a6fa1, 0x657d5bff, 0x758ee430, 0x01234578, 0xfadbcaa7, 0x89abde10,
+    0x76543222, 0xfedcbaaa, 0x579a6fa2, 0x657d5c00, 0x758ee431, 0x01234579, 0xfadbcaa8, 0x89abde11,
+    0x76543223, 0xfedcbaab, 0x579a6fa3, 0x657d5c01, 0x758ee432, 0x0123457a, 0xfadbcaa9, 0x89abde12,
+    0x76543224, 0xfedcbaac, 0x579a6fa4, 0x657d5c02, 0x758ee433, 0x0123457b, 0xfadbcaaa, 0x89abde13,
+    0x76543225, 0xfedcbaad, 0x579a6fa5, 0x657d5c03, 0x758ee434, 0x0123457c, 0xfadbcaab, 0x89abde14,
+    0x76543226, 0xfedcbaae, 0x579a6fa6, 0x657d5c04, 0x758ee435, 0x0123457d, 0xfadbcaac, 0x89abde15,
+    0x76543227, 0xfedcbaaf, 0x579a6fa7, 0x657d5c05, 0x758ee436, 0x0123457e, 0xfadbcaad, 0x89abde16,
+    0x76543228, 0xfedcbab0, 0x579a6fa8, 0x657d5c06, 0x758ee437, 0x0123457f, 0xfadbcaae, 0x89abde17
+};
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c
new file mode 100644
index 00000000..2e952816
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c
@@ -0,0 +1,300 @@
+/**
+ * @file main.c
+ * @brief Simple spi write example using BSP
+ *
+ * Simple example that writes a 1kB buffer to flash memory at a specific address
+ * and then read it back to check if the data was written correctly.
+ *
+*/
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "x-heep.h"
+#include "w25q128jw.h"
+
+/* By default, PRINTFs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+#ifdef TARGET_PYNQ_Z2
+    #define USE_SPI_FLASH
+#endif
+
+
+// Start buffers (the original data)
+#include "buffer.h"
+// End buffer (where what is read is stored)
+uint32_t flash_data[256];
+
+/*
+ * Assign the test buffer to the buffer to write to flash.
+ * The buffer is defined in the file buffer.h. As multiple buffers can
+ * be defined, this is userful to pick the right one.
+ * Also the length is specified, to test different length cases. In any case
+ * length <= test_buffer length.
+*/
+#define TEST_BUFFER flash_original_1024B
+#define LENGTH 1024
+
+#ifndef ON_CHIP
+#define FLASH_ONLY_WORDS 32
+#define FLASH_ONLY_BYTES (FLASH_ONLY_WORDS*4)
+
+int32_t __attribute__((section(".xheep_data_flash_only"))) __attribute__ ((aligned (16))) flash_only_buffer[FLASH_ONLY_WORDS] = {
+    0xABCDEF00,
+    0xABCDEF01,
+    0xABCDEF02,
+    0xABCDEF03,
+    0xABCDEF04,
+    0xABCDEF05,
+    0xABCDEF06,
+    0xABCDEF07,
+    0xABCDEF08,
+    0xABCDEF09,
+    0xABCDEF0A,
+    0xABCDEF0B,
+    0xABCDEF0C,
+    0xABCDEF0D,
+    0xABCDEF0E,
+    0xABCDEF0F,
+    0xABCDEF10,
+    0xABCDEF11,
+    0xABCDEF12,
+    0xABCDEF13,
+    0xABCDEF14,
+    0xABCDEF15,
+    0xABCDEF16,
+    0xABCDEF17,
+    0xABCDEF18,
+    0xABCDEF19,
+    0xABCDEF1A,
+    0xABCDEF1B,
+    0xABCDEF1C,
+    0xABCDEF1D,
+    0xABCDEF1E,
+    0xABCDEF1F,
+};
+
+int32_t __attribute__ ((aligned (16))) flash_only_buffer_golden_value[FLASH_ONLY_WORDS] = {
+    0xABCDEF00,
+    0xABCDEF01,
+    0xABCDEF02,
+    0xABCDEF03,
+    0xABCDEF04,
+    0xABCDEF05,
+    0xABCDEF06,
+    0xABCDEF07,
+    0xABCDEF08,
+    0xABCDEF09,
+    0xABCDEF0A,
+    0xABCDEF0B,
+    0xABCDEF0C,
+    0xABCDEF0D,
+    0xABCDEF0E,
+    0xABCDEF0F,
+    0xABCDEF10,
+    0xABCDEF11,
+    0xABCDEF12,
+    0xABCDEF13,
+    0xABCDEF14,
+    0xABCDEF15,
+    0xABCDEF16,
+    0xABCDEF17,
+    0xABCDEF18,
+    0xABCDEF19,
+    0xABCDEF1A,
+    0xABCDEF1B,
+    0xABCDEF1C,
+    0xABCDEF1D,
+    0xABCDEF1E,
+    0xABCDEF1F,
+};
+#endif
+
+// Test functions
+uint32_t test_read(uint32_t *test_buffer, uint32_t len);
+uint32_t test_read_flash_only(uint32_t *test_buffer, uint32_t len);
+uint32_t test_read_dma(uint32_t *test_buffer, uint32_t len);
+uint32_t test_read_quad(uint32_t *test_buffer, uint32_t len);
+uint32_t test_read_quad_dma(uint32_t *test_buffer, uint32_t len);
+
+// Check function
+uint32_t check_result(uint8_t *test_buffer, uint32_t len);
+
+// Define global status variable
+w25q_error_codes_t global_status;
+
+int main(int argc, char *argv[]) {
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+
+    if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO ) {
+        PRINTF("This application cannot work with the memory mapped SPI FLASH"
+            "module - do not use the FLASH_EXEC linker script for this application\n");
+        return EXIT_SUCCESS;
+    }
+
+    PRINTF("BSP read test\n", LENGTH);
+
+    // Pick the correct spi device based on simulation type
+    spi_host_t spi;
+    #ifndef USE_SPI_FLASH
+    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
+    #else
+    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
+    #endif
+
+    // Define status variable
+    int32_t errors = 0;
+
+    // Init SPI host and SPI<->Flash bridge parameters
+    if (w25q128jw_init(spi) != FLASH_OK) return EXIT_FAILURE;
+
+    // Test simple read
+    PRINTF("Testing simple read...\n");
+    errors += test_read(TEST_BUFFER, LENGTH);
+
+#ifndef ON_CHIP
+    PRINTF("Testing simple read on flash only data...\n");
+    errors += test_read_flash_only(flash_only_buffer, FLASH_ONLY_BYTES);
+#endif
+
+    // Test simple read with DMA
+    PRINTF("Testing simple read with DMA...\n");
+    errors += test_read_dma(TEST_BUFFER, LENGTH);
+
+    // Test quad read
+    PRINTF("Testing quad read...\n");
+    errors += test_read_quad(TEST_BUFFER, LENGTH);
+
+    // Test quad read with DMA
+    PRINTF("Testing quad read with DMA...\n");
+    errors += test_read_quad_dma(TEST_BUFFER, LENGTH);
+
+    PRINTF("\n--------TEST FINISHED--------\n");
+    if (errors == 0) {
+        PRINTF("All tests passed!\n");
+        return EXIT_SUCCESS;
+    } else {
+        PRINTF("Some tests failed!\n");
+        return EXIT_FAILURE;
+    }
+
+}
+
+uint32_t test_read(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = test_buffer;
+
+    // Read from flash memory at the same address
+    w25q_error_codes_t status = w25q128jw_read_standard(test_buffer_flash, flash_data, len);
+    if (status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_data == test_buffer)
+    uint32_t res =  check_result(test_buffer, len);
+
+    // Reset the flash data buffer
+    memset(flash_data, 0, len * sizeof(uint8_t));
+
+    return res;
+}
+#ifndef ON_CHIP
+uint32_t test_read_flash_only(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = heep_get_flash_address_offset(test_buffer);
+
+    // Read from flash memory at the same address
+    w25q_error_codes_t status = w25q128jw_read_standard(test_buffer_flash, flash_data, len);
+    if (status != FLASH_OK) exit(EXIT_FAILURE);
+
+    printf("Checking Results \n");
+
+    // Check if what we read is correct (i.e. flash_data == test_buffer)
+    uint32_t res =  check_result(flash_only_buffer_golden_value, len);
+
+    // Reset the flash data buffer
+    memset(flash_data, 0, len * sizeof(uint8_t));
+
+    return res;
+}
+#endif
+uint32_t test_read_dma(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = test_buffer;
+
+    // Read from flash memory at the same address
+    w25q_error_codes_t status = w25q128jw_read_standard_dma(test_buffer_flash, flash_data, len);
+    if (status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_data == test_buffer)
+    uint32_t res = check_result(test_buffer, len);
+
+    // Reset the flash data buffer
+    memset(flash_data, 0, len * sizeof(uint8_t));
+
+    return res;
+}
+
+uint32_t test_read_quad(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = test_buffer;
+
+    // Read from flash memory at the same address
+    w25q_error_codes_t status = w25q128jw_read_quad(test_buffer_flash, flash_data, len);
+    if (status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_data == test_buffer)
+    uint32_t res = check_result(test_buffer, len);
+
+    // Reset the flash data buffer
+    memset(flash_data, 0, len * sizeof(uint8_t));
+
+    return res;
+}
+
+uint32_t test_read_quad_dma(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = test_buffer;
+
+    // Read from flash memory at the same address
+    w25q_error_codes_t status = w25q128jw_read_quad_dma(test_buffer_flash, flash_data, len);
+    if (status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_data == test_buffer)
+    uint32_t res = check_result(test_buffer, len);
+
+    // Reset the flash data buffer
+    memset(flash_data, 0, len * sizeof(uint8_t));
+
+    return res;
+}
+
+uint32_t check_result(uint8_t *test_buffer, uint32_t len) {
+    uint32_t errors = 0;
+    uint8_t *flash_data_char = (uint8_t *)flash_data;
+
+    for (uint32_t i = 0; i < len; i++) {
+        if (test_buffer[i] != flash_data_char[i]) {
+            PRINTF("Error at position %d: expected %x, got %x\n", i, test_buffer[i], flash_data_char[i]);
+            errors++;
+        }
+    }
+
+    if (errors == 0) {
+        PRINTF("success!\n");
+    } else {
+        PRINTF("failure, %d errors!\n", errors);
+    }
+
+    return errors;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c
new file mode 100644
index 00000000..2b1a362b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c
@@ -0,0 +1,351 @@
+/**
+ * @file main.c
+ * @brief Simple spi write example using BSP
+ *
+ * Simple example that writes a 1kB buffer to flash memory at a specific address
+ * and then read it back to check if the data was written correctly.
+ * For buffers bigger than 4kB (or even smaller buffers that are not aligned to 4kB),
+ * the erase operation must be tweeked to erase all the sectors that contain the
+ * buffer.
+ *
+ * @note The application assume the correct functioning of the read operation.
+ *
+*/
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "x-heep.h"
+#include "w25q128jw.h"
+
+/* By default, PRINTFs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+#ifdef TARGET_PYNQ_Z2
+    #define USE_SPI_FLASH
+#endif
+
+
+// what to write in flash
+uint32_t flash_original_1024B[256] = {
+    0x76543211, 0xfedcba99, 0x579a6f91, 0x657d5bef, 0x758ee420, 0x01234568, 0xfedbca97, 0x89abde00,
+    0x76543212, 0xfedcba9a, 0x579a6f92, 0x657d5bf0, 0x758ee421, 0x01234569, 0xfedbca98, 0x89abde01,
+    0x76543213, 0xfedcba9b, 0x579a6f93, 0x657d5bf1, 0x758ee422, 0x0123456a, 0xfedbca99, 0x89abde02,
+    0x76543214, 0xfedcba9c, 0x579a6f94, 0x657d5bf2, 0x758ee423, 0x0123456b, 0xfedbca9a, 0x89abde03,
+    0x76543215, 0xfedcba9d, 0x579a6f95, 0x657d5bf3, 0x758ee424, 0x0123456c, 0xfedbca9b, 0x89abde04,
+    0x76543216, 0xfedcba9e, 0x579a6f96, 0x657d5bf4, 0x758ee425, 0x0123456d, 0xfedbca9c, 0x89abde05,
+    0x76543217, 0xfedcba9f, 0x579a6f97, 0x657d5bf5, 0x758ee426, 0x0123456e, 0xfedbca9d, 0x89abde06,
+    0x76543218, 0xfedcbaa0, 0x579a6f98, 0x657d5bf6, 0x758ee427, 0x0123456f, 0xfedbca9e, 0x89abde07,
+    0x76543219, 0xfedcbaa1, 0x579a6f99, 0x657d5bf7, 0x758ee428, 0x01234570, 0xfedbca9f, 0x89abde08,
+    0x7654321a, 0xfedcbaa2, 0x579a6f9a, 0x657d5bf8, 0x758ee429, 0x01234571, 0xfedbcaa0, 0x89abde09,
+    0x7654321b, 0xfedcbaa3, 0x579a6f9b, 0x657d5bf9, 0x758ee42a, 0x01234572, 0xfedbcaa1, 0x89abde0a,
+    0x7654321c, 0xfedcbaa4, 0x579a6f9c, 0x657d5bfa, 0x758ee42b, 0x01234573, 0xfedbcaa2, 0x89abde0b,
+    0x7654321d, 0xfedcbaa5, 0x579a6f9d, 0x657d5bfb, 0x758ee42c, 0x01234574, 0xfedbcaa3, 0x89abde0c,
+    0x7654321e, 0xfedcbaa6, 0x579a6f9e, 0x657d5bfc, 0x758ee42d, 0x01234575, 0xfedbcaa4, 0x89abde0d,
+    0x7654321f, 0xfedcbaa7, 0x579a6f9f, 0x657d5bfd, 0x758ee42e, 0x01234576, 0xfedbcaa5, 0x89abde0e,
+    0x76543220, 0xfedcbaa8, 0x579a6fa0, 0x657d5bfe, 0x758ee42f, 0x01234577, 0xfedbcaa6, 0x89abde0f,
+    0x76543221, 0xfedcbaa9, 0x579a6fa1, 0x657d5bff, 0x758ee430, 0x01234578, 0xfadbcaa7, 0x89abde10,
+    0x76543222, 0xfedcbaaa, 0x579a6fa2, 0x657d5c00, 0x758ee431, 0x01234579, 0xfadbcaa8, 0x89abde11,
+    0x76543223, 0xfedcbaab, 0x579a6fa3, 0x657d5c01, 0x758ee432, 0x0123457a, 0xfadbcaa9, 0x89abde12,
+    0x76543224, 0xfedcbaac, 0x579a6fa4, 0x657d5c02, 0x758ee433, 0x0123457b, 0xfadbcaaa, 0x89abde13,
+    0x76543225, 0xfedcbaad, 0x579a6fa5, 0x657d5c03, 0x758ee434, 0x0123457c, 0xfadbcaab, 0x89abde14,
+    0x76543226, 0xfedcbaae, 0x579a6fa6, 0x657d5c04, 0x758ee435, 0x0123457d, 0xfadbcaac, 0x89abde15,
+    0x76543227, 0xfedcbaaf, 0x579a6fa7, 0x657d5c05, 0x758ee436, 0x0123457e, 0xfadbcaad, 0x89abde16,
+    0x76543228, 0xfedcbab0, 0x579a6fa8, 0x657d5c06, 0x758ee437, 0x0123457f, 0xfadbcaae, 0x89abde17,
+    0x76543220, 0xfedcbaa8, 0x579a6fa0, 0x657d5bfe, 0x758ee42f, 0x01234577, 0xfedbcaa6, 0x89abde0f,
+    0x76543221, 0xfedcbaa9, 0x579a6fa1, 0x657d5bff, 0x758ee430, 0x01234578, 0xfadbcaa7, 0x89abde10,
+    0x76543222, 0xfedcbaaa, 0x579a6fa2, 0x657d5c00, 0x758ee431, 0x01234579, 0xfadbcaa8, 0x89abde11,
+    0x76543223, 0xfedcbaab, 0x579a6fa3, 0x657d5c01, 0x758ee432, 0x0123457a, 0xfadbcaa9, 0x89abde12,
+    0x76543224, 0xfedcbaac, 0x579a6fa4, 0x657d5c02, 0x758ee433, 0x0123457b, 0xfadbcaaa, 0x89abde13,
+    0x76543225, 0xfedcbaad, 0x579a6fa5, 0x657d5c03, 0x758ee434, 0x0123457c, 0xfadbcaab, 0x89abde14,
+    0x76543226, 0xfedcbaae, 0x579a6fa6, 0x657d5c04, 0x758ee435, 0x0123457d, 0xfadbcaac, 0x89abde15,
+    0x76543227, 0xfedcbaaf, 0x579a6fa7, 0x657d5c05, 0x758ee436, 0x0123457e, 0xfadbcaad, 0x89abde16,
+    0x76543228, 0xfedcbab0, 0x579a6fa8, 0x657d5c06, 0x758ee437, 0x0123457f, 0xfadbcaae, 0x89abde17
+};
+
+// End buffer (where what is read is stored)
+uint32_t flash_read_data[256];
+
+#define BYTES_TO_WRITE 533 //in bytes, must be less than 256*4=1024
+
+// address to which we write in FLASH, we do not initiliaze it to 0 as we do not want into the BSS
+// otherwise the compilers/linker won't allocate this to the .data section, thus not written in flash
+// If not written in flash, after erasing the block this array would be all '0xFF', and this would loose
+// generality of the testing as without erasing, the write operation in flash can bring 1->0 but not viceversa
+// by initializing to another number, we are sure it goes to .data section and written in flash
+uint32_t __attribute__ ((aligned (16))) flash_write_buffer[256] = {
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA,
+    0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA
+};
+
+#ifndef ON_CHIP
+int32_t __attribute__((section(".xheep_data_flash_only"))) __attribute__ ((aligned (16))) flash_only_write_buffer[256];
+#endif
+
+// Test functions
+uint32_t test_write(uint32_t *test_buffer, uint32_t len);
+uint32_t test_write_dma(uint32_t *test_buffer, uint32_t len);
+uint32_t test_write_quad(uint32_t *test_buffer, uint32_t len);
+uint32_t test_write_quad_dma(uint32_t *test_buffer, uint32_t len);
+uint32_t test_write_flash_only(uint32_t *test_buffer, uint32_t len);
+
+// Check function
+uint32_t check_result(uint8_t *test_buffer, uint32_t len);
+
+// Erase memory function
+void erase_memory(uint32_t addr);
+
+// Define global status variable
+w25q_error_codes_t global_status;
+
+int main(int argc, char *argv[]) {
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+
+    if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO ) {
+        PRINTF("This application cannot work with the memory mapped SPI FLASH"
+            "module - do not use the FLASH_EXEC linker script for this application\n");
+        return EXIT_SUCCESS;
+    }
+
+    PRINTF("BSP write test\n");
+
+    // Pick the correct spi device
+    spi_host_t spi;
+    #ifndef USE_SPI_FLASH
+    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
+    #else
+    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
+    #endif
+
+    // Define status variable
+    int32_t errors = 0;
+
+    // Init SPI host and SPI<->Flash bridge parameters
+    if (w25q128jw_init(spi) != FLASH_OK) return EXIT_FAILURE;
+
+    // Test simple write
+    PRINTF("Testing simple write...\n");
+    errors += test_write(flash_original_1024B, BYTES_TO_WRITE);
+
+#ifndef ON_CHIP
+    // Test simple write on flash_only data
+    PRINTF("Testing simple write. on flash only data..\n");
+    errors += test_write_flash_only(flash_original_1024B, BYTES_TO_WRITE);
+#endif
+
+
+    // Test simple write with DMA
+    PRINTF("Testing simple write with DMA...\n");
+    errors += test_write_dma(flash_original_1024B, BYTES_TO_WRITE);
+
+    // Test quad write
+    PRINTF("Testing quad write...\n");
+    errors += test_write_quad(flash_original_1024B, BYTES_TO_WRITE);
+
+    // Test quad write with DMA
+    PRINTF("Testing quad write with DMA...\n");
+    errors += test_write_quad_dma(flash_original_1024B, BYTES_TO_WRITE);
+
+    PRINTF("\n--------TEST FINISHED--------\n");
+    if (errors == 0) {
+        PRINTF("All tests passed!\n");
+        return EXIT_SUCCESS;
+    } else {
+        PRINTF("Some tests failed!\n");
+        return EXIT_FAILURE;
+    }
+}
+
+
+uint32_t test_write(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = flash_write_buffer;
+
+    // Write to flash memory at specific address
+    global_status = w25q128jw_erase_and_write_standard(test_buffer_flash, test_buffer, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Read from flash memory at the same address
+    global_status = w25q128jw_read(test_buffer_flash, flash_read_data, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_original == flash_read_data)
+    int32_t result = check_result(test_buffer, len);
+
+    // Clean memory for next test
+    erase_memory(test_buffer_flash);
+
+    // Reset the flash data buffer
+    memset(flash_read_data, 0, len * sizeof(uint8_t));
+
+    return result;
+}
+
+uint32_t test_write_dma(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = flash_write_buffer;
+
+    // Write to flash memory at specific address
+    global_status = w25q128jw_erase_and_write_standard_dma(test_buffer_flash, test_buffer, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Read from flash memory at the same address
+    global_status = w25q128jw_read(test_buffer_flash, flash_read_data, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_original == flash_read_data)
+    int32_t result = check_result(test_buffer, len);
+
+    // Clean memory for next test
+    erase_memory(test_buffer_flash);
+
+    // Reset the flash data buffer
+    memset(flash_read_data, 0, len * sizeof(uint8_t));
+
+    return result;
+}
+
+uint32_t test_write_quad(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = flash_write_buffer;
+
+    // Write to flash memory at specific address
+    global_status = w25q128jw_erase_and_write_quad(test_buffer_flash, test_buffer, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Read from flash memory at the same address
+    global_status = w25q128jw_read(test_buffer_flash, flash_read_data, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_original == flash_read_data)
+    int32_t result = check_result(test_buffer, len);
+
+    // Clean memory for next test
+    erase_memory(test_buffer_flash);
+
+    // Reset the flash data buffer
+    memset(flash_read_data, 0, len * sizeof(uint8_t));
+
+    return result;
+}
+
+uint32_t test_write_quad_dma(uint32_t *test_buffer, uint32_t len) {
+
+    uint32_t *test_buffer_flash = flash_write_buffer;
+
+    // Write to flash memory at specific address
+    global_status = w25q128jw_erase_and_write_quad_dma(test_buffer_flash, test_buffer, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Read from flash memory at the same address
+    global_status = w25q128jw_read(test_buffer_flash, flash_read_data, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_original == flash_read_data)
+    int32_t result = check_result(test_buffer, len);
+
+    // Clean memory for next test
+    erase_memory(test_buffer_flash);
+
+    // Reset the flash data buffer
+    memset(flash_read_data, 0, len * sizeof(uint8_t));
+
+    return result;
+}
+#ifndef ON_CHIP
+uint32_t test_write_flash_only(uint32_t *test_buffer, uint32_t len) {
+
+    //remove FLASH offset as required by the BSP, flash_only_write_buffer is only mapped to the LMA
+    uint32_t *test_buffer_flash = heep_get_flash_address_offset(flash_only_write_buffer);
+
+    // Clean memory
+    erase_memory(test_buffer_flash);
+
+    // Write to flash memory at specific address
+    global_status = w25q128jw_erase_and_write_standard(test_buffer_flash, test_buffer, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Read from flash memory at the same address
+    global_status = w25q128jw_read(test_buffer_flash, flash_read_data, len);
+    if (global_status != FLASH_OK) exit(EXIT_FAILURE);
+
+    // Check if what we read is correct (i.e. flash_original == flash_read_data)
+    int32_t result = check_result(test_buffer, len);
+
+    // Clean memory for next test
+    erase_memory(test_buffer_flash);
+
+    // Reset the flash data buffer
+    memset(flash_read_data, 0, len * sizeof(uint8_t));
+
+    return result;
+}
+#endif
+uint32_t check_result(uint8_t *test_buffer, uint32_t len) {
+    uint32_t errors = 0;
+    uint8_t *flash_read_data_char = (uint8_t *)flash_read_data;
+
+    for (uint32_t i = 0; i < len; i++) {
+        if (test_buffer[i] != flash_read_data_char[i]) {
+            PRINTF("Error at position %d: expected %x, got %x\n", i, test_buffer[i], flash_read_data_char[i]);
+            errors++;
+        }
+    }
+
+    if (errors == 0) {
+        PRINTF("success!\n");
+    } else {
+        PRINTF("failure, %d errors!\n", errors);
+    }
+
+    return errors;
+}
+
+// Erase the memory only if FPGA is used
+void erase_memory(uint32_t addr) {
+    #ifdef USE_SPI_FLASH
+    w25q128jw_4k_erase(addr);
+    #endif
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_virtual_flash/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_virtual_flash/main.c
deleted file mode 100644
index e1e16f56..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_virtual_flash/main.c
+++ /dev/null
@@ -1,222 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "rv_timer.h"
-#include "rv_timer_regs.h"
-#include "soc_ctrl.h"
-#include "rv_plic.h"
-#include "rv_plic_regs.h"
-#include "spi_host.h"
-#include "spi_host_regs.h"
-#include "dma.h"
-#include "fast_intr_ctrl.h"
-#include "gpio.h"
-#include "fast_intr_ctrl_regs.h"
-#include "x-heep.h"
-
-#define REVERT_24b_ADDR(addr) ((((uint32_t)addr & 0xff0000) >> 16) | ((uint32_t)addr & 0xff00) | (((uint32_t)addr & 0xff) << 16))
-#define FLASH_ADDR 0x00000000
-#define FLASH_SIZE 64 * 1024 * 1024
-#define FLASH_CLK_MAX_HZ (133 * 1000 * 1000)
-
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-// Interrupt controller variables
-plic_result_t plic_res;
-uint32_t intr_num;
-
-//volatile int8_t timer_flag;
-volatile int8_t spi_intr_flag;
-
-spi_host_t spi_host_flash;
-
-void dma_intr_handler_trans_done(){
-    PRINTF("#\n\r");
-}
-
-void fic_irq_spi_flash(){
-    // Disable SPI interrupts
-    spi_enable_evt_intr(&spi_host_flash, false);
-    spi_enable_rxwm_intr(&spi_host_flash, false);
-    spi_intr_flag = 1;
-    PRINTF("@\n\r");
-}
-
-
-void write_to_flash(spi_host_t *SPI, uint16_t *data, uint32_t byte_count, uint32_t addr)
-{
-    uint32_t write_to_mem = 0x02;
-    spi_write_word(SPI, write_to_mem);
-    uint32_t cmd_write_to_mem = spi_create_command((spi_command_t){
-        .len       = 0,
-        .csaat     = true,
-        .speed     = kSpiSpeedStandard,
-        .direction = kSpiDirTxOnly
-    });
-    spi_set_command(SPI, cmd_write_to_mem);
-    spi_wait_for_ready(SPI);
-
-    uint32_t addr_cmd = __builtin_bswap32(addr);
-    spi_write_word(SPI, addr_cmd);
-    uint32_t cmd_address = spi_create_command((spi_command_t){
-        .len       = 3,
-        .csaat     = true,
-        .speed     = kSpiSpeedStandard,
-        .direction = kSpiDirTxOnly
-    });
-    spi_set_command(SPI, cmd_address);
-    spi_wait_for_ready(SPI);
-
-    uint32_t *fifo_ptr_tx = SPI->base_addr.base + SPI_HOST_TXDATA_REG_OFFSET;
-
-    // -- DMA CONFIGURATION --
-    dma_init(NULL);
-
-    dma_target_t tgt_src = {
-        .ptr = data,
-        .inc_du = 1,
-        .size_du = 64,
-        .type = DMA_DATA_TYPE_HALF_WORD,
-        .trig = DMA_TRIG_MEMORY,
-    };
-    dma_target_t tgt_dst = {
-        .ptr = fifo_ptr_tx,
-        .inc_du = 0,
-        .size_du = 0,
-        .type = DMA_DATA_TYPE_HALF_WORD,
-        .trig = DMA_TRIG_SLOT_SPI_FLASH_TX,
-    };
-    dma_trans_t trans = {
-        .src = &tgt_src,
-        .dst = &tgt_dst,
-        .end = DMA_TRANS_END_INTR,
-    };
-
-    dma_config_flags_t res;
-
-    spi_intr_flag = 0;
-
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("trans: %u\n\r", res );
-    res = dma_load_transaction(&trans);
-    PRINTF("load: %u\n\r", res );
-    res = dma_launch(&trans);
-
-    // Wait for the first data to arrive to the TX FIFO before enabling interrupt
-    spi_wait_for_tx_not_empty(SPI);
-    // Enable event interrupt
-    spi_enable_evt_intr(SPI, true);
-    // Enable TX empty interrupt
-    spi_enable_txempty_intr(SPI, true);
-
-    const uint32_t cmd_write_tx = spi_create_command((spi_command_t){
-        .len       = byte_count - 1,
-        .csaat     = false,
-        .speed     = kSpiSpeedStandard,
-        .direction = kSpiDirTxOnly
-    });
-    spi_set_command(SPI, cmd_write_tx);
-    spi_wait_for_ready(SPI);
-
-   // Wait for SPI interrupt
-   while(spi_intr_flag == 0) {
-        wait_for_interrupt();
-   }
-
-    PRINTF("%d words written to flash.\n\n\r", byte_count/4);
-}
-
-int main(int argc, char *argv[])
-{
-    // Get current Frequency
-    soc_ctrl_t soc_ctrl;
-    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
-    soc_ctrl_select_spi_host(&soc_ctrl);
-
-    uint32_t core_clk = soc_ctrl_get_frequency(&soc_ctrl);
-
-    // Enable interrupt on processor side
-    // Enable global interrupt for machine-level interrupts
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    uint32_t mask = 1 << 21;
-    CSR_SET_BITS(CSR_REG_MIE, mask);
-    spi_intr_flag = 0;
-    // Set mie.MEIE bit to one to enable timer interrupt
-    mask = 1 << 7;
-    CSR_SET_BITS(CSR_REG_MIE, mask);
-
-    spi_host_flash.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
-    spi_set_enable(&spi_host_flash, true);
-    spi_output_enable(&spi_host_flash, true);
-
-    uint16_t clk_div = 0;
-    if (FLASH_CLK_MAX_HZ < core_clk / 2)
-    {
-        clk_div = (core_clk / (FLASH_CLK_MAX_HZ)-2) / 2; // The value is truncated
-        if (core_clk / (2 + 2 * clk_div) > FLASH_CLK_MAX_HZ)
-            clk_div += 1; // Adjust if the truncation was not 0
-    }
-
-    // SPI Configuration
-    // Configure chip 0 (flash memory)
-    const uint32_t chip_cfg_flash = spi_create_configopts((spi_configopts_t){
-        .clkdiv = clk_div,
-        .csnidle = 0xF,
-        .csntrail = 0xF,
-        .csnlead = 0xF,
-        .fullcyc = false,
-        .cpha = 0,
-        .cpol = 0});
-    spi_set_configopts(&spi_host_flash, 0, chip_cfg_flash);
-    spi_set_csid(&spi_host_flash, 0);
-
-    // To set the number of dummy cycles we have to send command 0x11 and then a 1B value
-    const uint32_t reset_cmd = 0x11;
-    spi_write_word(&spi_host_flash, reset_cmd);
-    const uint32_t cmd_reset = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = true,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host_flash, cmd_reset);
-    spi_wait_for_ready(&spi_host_flash);
-
-    const uint32_t set_dummy_cycle = 0x07;
-    spi_write_word(&spi_host_flash, set_dummy_cycle);
-    const uint32_t cmd_set_dummy = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-
-    spi_set_command(&spi_host_flash, cmd_set_dummy);
-    spi_wait_for_ready(&spi_host_flash);
-
-    uint32_t results[32];
-    for(uint32_t i = 0; i < 32; i++){
-        results[i] = i;
-    }
-
-    write_to_flash(&spi_host_flash, results, sizeof(*results) * 32, FLASH_ADDR);
-
-    PRINTF("Success.\n\r");
-
-    return EXIT_SUCCESS;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/arch.cfg b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/arch.cfg
new file mode 100644
index 00000000..0583bdfe
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/arch.cfg
@@ -0,0 +1,67 @@
+###############################################################################
+#
+# Copyright 2020 OpenHW Group
+# 
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+# 
+#     https://solderpad.org/licenses/
+# 
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# 
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+#
+###############################################################################
+
+# This is a python setting of parameters for the architecture.  The following
+# parameters may be set (other keys are silently ignored).  Defaults are shown
+# in brackets
+# - cc ('cc')
+# - ld (same value as for cc)
+# - cflags ([])
+# - ldflags ([])
+# - cc_define_pattern ('-D{0}')
+# - cc_incdir_pattern ('-I{0}')
+# - cc_input_pattern ('{0}')
+# - cc_output_pattern ('-o {0}')
+# - ld_input_pattern ('{0}')
+# - ld_output_pattern ('-o {0}')
+# - user_libs ([])
+# - dummy_libs ([])
+# - cpu_mhz (1)
+# - warmup_heat (1)
+
+# The "flags" and "libs" parameters (cflags, ldflags, user_libs, dummy_libs)
+# should be lists of arguments to be passed to the compile or link line as
+# appropriate.  Patterns are Python format patterns used to create arguments.
+# Thus for GCC or Clang/LLVM defined constants can be passed using the prefix
+# '-D', and the pattern '-D{0}' would be appropriate (which happens to be the
+# default).
+
+# "user_libs" may be absolute file names or arguments to the linker. In the
+# latter case corresponding arguments in ldflags may be needed.  For example
+# with GCC or Clang/LLVM is "-l" flags are used in "user_libs", the "-L" flags
+# may be needed in "ldflags".
+
+# Dummy libs have their source in the "support" subdirectory. Thus if 'crt0'
+# is specified, there should be a source file 'dummy-crt0.c' in the support
+# directory.
+
+# There is no need to set an unused parameter, and this file may be empty to
+# set no flags.
+
+# Parameter values which are duplicated in architecture, board, chip or
+# command line are used in the following order of priority
+# - default value
+# - architecture specific value
+# - chip specific value
+# - board specific value
+# - command line value
+
+# For flags, this priority is applied to individual flags, not the complete
+# list of flags.
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.c
new file mode 100644
index 00000000..5e55329f
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.c
@@ -0,0 +1,177 @@
+/* BEEBS local library variants
+
+   Copyright (C) 2019 Embecosm Limited.
+
+   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+
+   This file is part of Embench and was formerly part of the Bristol/Embecosm
+   Embedded Benchmark Suite.
+
+   SPDX-License-Identifier: GPL-3.0-or-later */
+
+/* These are very simple local versions of library routines, to ensure the
+   code is compiled with the flags used for the benchmark.  Not all library
+   routines are here, just ones that cause a lot of unecessary load, or where
+   there is variation between platforms and architectures. */
+
+#include <stddef.h>
+#include <string.h>
+#include "beebsc.h"
+
+/* Seed for the random number generator */
+
+static long int seed = 0;
+
+/* Heap records and sane initial values */
+
+static void *heap_ptr = NULL;
+static void *heap_end = NULL;
+static size_t heap_requested = 0;
+
+
+/* Yield a sequence of random numbers in the range [0, 2^15-1].
+
+   long int is guaranteed to be at least 32 bits. The seed only ever uses 31
+   bits (so is positive).
+
+   For BEEBS this gets round different operating systems using different
+   multipliers and offsets and RAND_MAX variations. */
+
+int
+rand_beebs (void)
+{
+  seed = (seed * 1103515245L + 12345) & ((1UL << 31) - 1);
+  return (int) (seed >> 16);
+}
+
+
+/* Initialize the random number generator */
+
+void
+srand_beebs (unsigned int new_seed)
+{
+  seed = (long int) new_seed;
+}
+
+
+/* Initialize the BEEBS heap pointers. Note that the actual memory block is
+   in the caller code. */
+
+void
+init_heap_beebs (void *heap, size_t heap_size)
+{
+  heap_ptr = (void *) heap;
+  heap_end = (void *) ((char *) heap_ptr + heap_size);
+  heap_requested = 0;
+}
+
+
+/* Report if malloc ever failed.
+
+   Return non-zero (TRUE) if malloc did not reqest more than was available
+   since the last call to init_heap_beebs, zero (FALSE) otherwise. */
+
+int
+check_heap_beebs (void *heap)
+{
+  return ((void *) ((char *) heap + heap_requested) <= heap_end);
+}
+
+
+/* BEEBS version of malloc.
+
+   This is primarily to reduce library and OS dependencies. Malloc is
+   generally not used in embedded code, or if it is, only in well defined
+   contexts to pre-allocate a fixed amount of memory. So this simplistic
+   implementation is just fine.
+
+   Note in particular the assumption that memory will never be freed! */
+
+void *
+malloc_beebs (size_t size)
+{
+  void *new_ptr = heap_ptr;
+
+  heap_requested += size;
+
+  if (((void *) ((char *) heap_ptr + size) > heap_end) || (0 == size))
+    return NULL;
+  else
+    {
+      heap_ptr = (void *) ((char *) heap_ptr + size);
+      return new_ptr;
+    }
+}
+
+
+/* BEEBS version of calloc.
+
+   Implement as wrapper for malloc */
+
+void *
+calloc_beebs (size_t nmemb, size_t size)
+{
+  void *new_ptr = malloc_beebs (nmemb * size);
+
+  /* Calloc is defined to zero the memory. OK to use a function here, because
+     it will be handled specially by the compiler anyway. */
+
+  if (NULL != new_ptr)
+    memset (new_ptr, 0, nmemb * size);
+
+  return new_ptr;
+}
+
+
+/* BEEBS version of realloc.
+
+   This is primarily to reduce library and OS dependencies. We just have to
+   allocate new memory and copy stuff across. */
+
+void *
+realloc_beebs (void *ptr, size_t size)
+{
+  void *new_ptr = heap_ptr;
+
+  heap_requested += size;
+
+  if (((void *) ((char *) heap_ptr + size) > heap_end) || (0 == size))
+    return NULL;
+  else
+    {
+      heap_ptr = (void *) ((char *) heap_ptr + size);
+
+      /* This is clunky, since we don't know the size of the original
+         pointer. However it is a read only action and we know it must
+         be big enough if we right off the end, or we couldn't have
+         allocated here. If the size is smaller, it doesn't matter. */
+
+      if (NULL != ptr)
+	{
+	  size_t i;
+
+	  for (i = 0; i < size; i++)
+	    ((char *) new_ptr)[i] = ((char *) ptr)[i];
+	}
+
+      return new_ptr;
+    }
+}
+
+
+/* BEEBS version of free.
+
+   For our simplified version of memory handling, free can just do nothing. */
+
+void
+free_beebs (void *ptr __attribute__ ((unused)))
+{
+}
+
+
+/*
+   Local Variables:
+   mode: C
+   c-file-style: "gnu"
+   End:
+*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.h b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.h
new file mode 100644
index 00000000..4a108959
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/beebsc.h
@@ -0,0 +1,65 @@
+/* BEEBS local library variants header
+
+   Copyright (C) 2019 Embecosm Limited.
+
+   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+
+   This file is part of Embench and was formerly part of the Bristol/Embecosm
+   Embedded Benchmark Suite.
+
+   SPDX-License-Identifier: GPL-3.0-or-later */
+
+#ifndef BEEBSC_H
+#define BEEBSC_H
+
+#include <stddef.h>
+
+/* BEEBS fixes RAND_MAX to its lowest permitted value, 2^15-1 */
+
+#ifdef RAND_MAX
+#undef RAND_MAX
+#endif
+#define RAND_MAX ((1U << 15) - 1)
+
+/* Common understanding of a "small value" (epsilon) for floating point
+   comparisons. */
+
+#define VERIFY_DOUBLE_EPS 1.0e-13
+#define VERIFY_FLOAT_EPS 1.0e-5
+
+/* Simplified assert.
+
+   The full complexity of assert is not needed for a benchmark. See the
+   discussion at:
+
+   https://lists.librecores.org/pipermail/embench/2019-August/000007.html 
+
+   This function just*/
+
+#define assert_beebs(expr) { if (!(expr)) exit (1); }
+
+#define float_eq_beebs(exp, actual) (fabsf(exp - actual) < VERIFY_FLOAT_EPS)
+#define float_neq_beebs(exp, actual) !float_eq_beebs(exp, actual)
+#define double_eq_beebs(exp, actual) (fabs(exp - actual) < VERIFY_DOUBLE_EPS)
+#define double_neq_beebs(exp, actual) !double_eq_beebs(exp, actual)
+
+/* Local simplified versions of library functions */
+
+int rand_beebs (void);
+void srand_beebs (unsigned int new_seed);
+
+void init_heap_beebs (void *heap, const size_t heap_size);
+int check_heap_beebs (void *heap);
+void *malloc_beebs (size_t size);
+void *calloc_beebs (size_t nmemb, size_t size);
+void *realloc_beebs (void *ptr, size_t size);
+void free_beebs (void *ptr);
+#endif /* BEEBSC_H */
+
+
+/*
+   Local Variables:
+   mode: C
+   c-file-style: "gnu"
+   End:
+*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/board.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/board.c
new file mode 100644
index 00000000..db8fafa8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/board.c
@@ -0,0 +1,22 @@
+/* Common board.c for the benchmarks
+
+   Copyright (C) 2018-2019 Embecosm Limited
+
+   Contributor: Jeremy Bennett <jeremy.bennett@embecosm.com>
+
+   This file is part of Embench and was formerly part of the Bristol/Embecosm
+   Embedded Benchmark Suite.
+
+   SPDX-License-Identifier: GPL-3.0-or-later */
+
+/* This is just a wrapper for the board specific support file. */
+
+#include "boardsupport.c"
+
+
+/*
+   Local Variables:
+   mode: C
+   c-file-style: "gnu"
+   End:
+*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.c
new file mode 100644
index 00000000..f2e674de
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.c
@@ -0,0 +1,21 @@
+/*
+**
+** Copyright 2020 OpenHW Group
+** 
+** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+** you may not use this file except in compliance with the License.
+** You may obtain a copy of the License at
+** 
+**     https://solderpad.org/licenses/
+** 
+** Unless required by applicable law or agreed to in writing, software
+** distributed under the License is distributed on an "AS IS" BASIS,
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+** See the License for the specific language governing permissions and
+** limitations under the License.
+** 
+*******************************************************************************
+*/
+
+#include "boardsupport.h"
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.h b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.h
new file mode 100644
index 00000000..6223cd68
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/boardsupport.h
@@ -0,0 +1,21 @@
+/*
+**
+** Copyright 2020 OpenHW Group
+** 
+** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+** you may not use this file except in compliance with the License.
+** You may obtain a copy of the License at
+** 
+**     https://solderpad.org/licenses/
+** 
+** Unless required by applicable law or agreed to in writing, software
+** distributed under the License is distributed on an "AS IS" BASIS,
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+** See the License for the specific language governing permissions and
+** limitations under the License.
+** 
+*******************************************************************************
+*/
+
+
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chip.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chip.c
new file mode 100644
index 00000000..37ac28fe
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chip.c
@@ -0,0 +1,32 @@
+/* Common board.c for the benchmarks
+
+   Copyright (C) 2018-2019 Embecosm Limited
+
+   Contributor: Jeremy Bennett <jeremy.bennett@embecosm.com>
+
+   This file is part of Embench and was formerly part of the Bristol/Embecosm
+   Embedded Benchmark Suite.
+
+   SPDX-License-Identifier: GPL-3.0-or-later */
+
+/* This is just a wrapper for the chip specific support file if there is one. */
+
+/*#include "config.h"*/
+
+#ifdef HAVE_CHIPSUPPORT_H
+#include "chipsupport.c"
+#endif
+
+/* Standard C does not permit empty translation units, so provide one. */
+
+static void
+empty_func ()
+{
+}
+
+/*
+   Local Variables:
+   mode: C
+   c-file-style: "gnu"
+   End:
+*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c
new file mode 100644
index 00000000..3228651d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c
@@ -0,0 +1,73 @@
+/*
+**
+** Copyright 2020 OpenHW Group
+** 
+** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+** you may not use this file except in compliance with the License.
+** You may obtain a copy of the License at
+** 
+**     https://solderpad.org/licenses/
+** 
+** Unless required by applicable law or agreed to in writing, software
+** distributed under the License is distributed on an "AS IS" BASIS,
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+** See the License for the specific language governing permissions and
+** limitations under the License.
+** 
+*******************************************************************************
+*/
+
+#include <support.h>
+#include <stdint.h>
+#include <stdio.h>
+#include "chipsupport.h"
+
+#include "csr.h"
+#include "x-heep.h"
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+#define FS_INITIAL 0x01
+
+void
+initialise_board ()
+{
+  PRINTF("Initialize board corev32 \n");
+
+  //enable FP operations
+  CSR_SET_BITS(CSR_REG_MSTATUS, (FS_INITIAL << 13));
+
+}
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+start_trigger ()
+{
+  PRINTF("start of test \n");
+
+  // Enable mcycle counter and read value
+  CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+  CSR_WRITE(CSR_REG_MCYCLE, 0);
+
+}
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+stop_trigger ()
+{
+  uint32_t cycle_cnt;
+  CSR_READ(CSR_REG_MCYCLE, &cycle_cnt);
+  PRINTF("end of test \n");
+  PRINTF("Result is given in CPU cycles \n");
+  PRINTF("RES: %d \n", cycle_cnt);
+
+}
+ 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.h b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.h
new file mode 100644
index 00000000..bd174c31
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.h
@@ -0,0 +1,25 @@
+/*
+**
+** Copyright 2020 OpenHW Group
+** 
+** Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+** you may not use this file except in compliance with the License.
+** You may obtain a copy of the License at
+** 
+**     https://solderpad.org/licenses/
+** 
+** Unless required by applicable law or agreed to in writing, software
+** distributed under the License is distributed on an "AS IS" BASIS,
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+** See the License for the specific language governing permissions and
+** limitations under the License.
+** 
+*******************************************************************************
+*/
+
+#ifndef CHIPSUPPORT_H
+#define CHIPSUPPORT_H
+
+#define CPU_MHZ 1
+
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/libminver.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/libminver.c
new file mode 100644
index 00000000..0cabd55b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/libminver.c
@@ -0,0 +1,292 @@
+/* BEEBS minver benchmark
+
+   This version, copyright (C) 2014-2019 Embecosm Limited and University of
+   Bristol
+
+   Contributor Pierre Langlois <pierre.langlois@embecosm.com>
+   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+
+   This file is part of Embench and was formerly part of the Bristol/Embecosm
+   Embedded Benchmark Suite.
+
+   SPDX-License-Identifier: GPL-3.0-or-later
+
+   *************************************************************************
+   *                                                                       *
+   *   SNU-RT Benchmark Suite for Worst Case Timing Analysis               *
+   *   =====================================================               *
+   *                              Collected and Modified by S.-S. Lim      *
+   *                                           sslim@archi.snu.ac.kr       *
+   *                                         Real-Time Research Group      *
+   *                                        Seoul National University      *
+   *                                                                       *
+   *                                                                       *
+   *        < Features > - restrictions for our experimental environment   *
+   *                                                                       *
+   *          1. Completely structured.                                    *
+   *               - There are no unconditional jumps.                     *
+   *               - There are no exit from loop bodies.                   *
+   *                 (There are no 'break' or 'return' in loop bodies)     *
+   *          2. No 'switch' statements.                                   *
+   *          3. No 'do..while' statements.                                *
+   *          4. Expressions are restricted.                               *
+   *               - There are no multiple expressions joined by 'or',     *
+   *                'and' operations.                                      *
+   *          5. No library calls.                                         *
+   *               - All the functions needed are implemented in the       *
+   *                 source file.                                          *
+   *                                                                       *
+   *                                                                       *
+   *************************************************************************
+   *                                                                       *
+   *  FILE: minver.c                                                       *
+   *  SOURCE : Turbo C Programming for Engineering by Hyun Soo Ahn         *
+   *                                                                       *
+   *  DESCRIPTION :                                                        *
+   *                                                                       *
+   *     Matrix inversion for 3x3 floating point matrix.                   *
+   *                                                                       *
+   *  REMARK :                                                             *
+   *                                                                       *
+   *  EXECUTION TIME :                                                     *
+   *                                                                       *
+   *                                                                       *
+   *************************************************************************
+
+*/
+
+#include <math.h>
+#include <string.h>
+#include "support.h"
+
+/* This scale factor will be changed to equalise the runtime of the
+   benchmarks. */
+#define LOCAL_SCALE_FACTOR 555
+
+int minver (int row, int col, float eps);
+int mmul (int row_a, int col_a, int row_b, int col_b);
+
+static float a_ref[3][3] = {
+  {3.0, -6.0, 7.0},
+  {9.0, 0.0, -5.0},
+  {5.0, -8.0, 6.0},
+};
+
+static float b[3][3] = {
+  {-3.0, 0.0, 2.0},
+  {3.0, -2.0, 0.0},
+  {0.0, 2.0, -3.0},
+};
+
+static float a[3][3], c[3][3], d[3][3], det;
+
+static float
+minver_fabs (float n)
+{
+  float f;
+
+  if (n >= 0)
+    f = n;
+  else
+    f = -n;
+  return f;
+}
+
+int
+mmul (int row_a, int col_a, int row_b, int col_b)
+{
+  int i, j, k, row_c, col_c;
+  float w;
+
+  row_c = row_a;
+  col_c = col_b;
+
+  if (row_c < 1 || row_b < 1 || col_c < 1 || col_a != row_b)
+    return (999);
+  for (i = 0; i < row_c; i++)
+    {
+      for (j = 0; j < col_c; j++)
+	{
+	  w = 0.0;
+	  for (k = 0; k < row_b; k++)
+	    w += a[i][k] * b[k][j];
+	  c[i][j] = w;
+	}
+    }
+
+  return (0);
+}
+
+
+int
+minver (int row, int col, float eps)
+{
+  int work[500], i, j, k, r, iw, u, v;
+  float w, wmax, pivot, api, w1;
+
+  r = w = 0;
+  if (row < 2 || row > 500 || eps <= 0.0)
+    return (999);
+  w1 = 1.0;
+  for (i = 0; i < row; i++)
+    work[i] = i;
+  for (k = 0; k < row; k++)
+    {
+      wmax = 0.0;
+      for (i = k; i < row; i++)
+	{
+	  w = minver_fabs (a[i][k]);
+	  if (w > wmax)
+	    {
+	      wmax = w;
+	      r = i;
+	    }
+	}
+      pivot = a[r][k];
+      api = minver_fabs (pivot);
+      if (api <= eps)
+	{
+	  det = w1;
+	  return (1);
+	}
+      w1 *= pivot;
+      u = k * col;
+      v = r * col;
+      if (r != k)
+	{
+	  w1 = -w;
+	  iw = work[k];
+	  work[k] = work[r];
+	  work[r] = iw;
+	  for (j = 0; j < row; j++)
+	    {
+	      w = a[k][j];
+	      a[k][j] = a[r][j];
+	      a[r][j] = w;
+	    }
+	}
+      for (i = 0; i < row; i++)
+	a[k][i] /= pivot;
+      for (i = 0; i < row; i++)
+	{
+	  if (i != k)
+	    {
+	      v = i * col;
+	      w = a[i][k];
+	      if (w != 0.0)
+		{
+		  for (j = 0; j < row; j++)
+		    if (j != k)
+		      a[i][j] -= w * a[k][j];
+		  a[i][k] = -w / pivot;
+		}
+	    }
+	}
+      a[k][k] = 1.0 / pivot;
+    }
+
+  for (i = 0; i < row; i++)
+    {
+      while (1)
+	{
+	  k = work[i];
+	  if (k == i)
+	    break;
+	  iw = work[k];
+	  work[k] = work[i];
+	  work[i] = iw;
+	  for (j = 0; j < row; j++)
+	    {
+	      u = j * col;
+	      w = a[k][i];
+	      a[k][i] = a[k][k];
+	      a[k][k] = w;
+	    }
+	}
+    }
+
+  det = w1;
+
+  return (0);
+}
+
+
+int
+verify_benchmark (int res __attribute ((unused)))
+{
+  int i, j;
+  float eps = 1.0e-6;
+
+  static float c_exp[3][3] = {
+    {-27.0, 26.0, -15.0},
+    {-27.0, -10.0, 33.0},
+    {-39.0, 28.0, -8.0}
+  };
+
+  static float d_exp[3][3] = {
+    {0.133333325, -0.199999958, 0.2666665910},
+    {-0.519999862, 0.113333330, 0.5266665220},
+    {0.479999840, -0.359999895, 0.0399999917}
+  };
+
+  /* Allow small errors in floating point */
+
+  for (i = 0; i < 3; i++)
+    for (j = 0; j < 3; j++)
+      if (float_neq_beebs(c[i][j], c_exp[i][j]) || float_neq_beebs(d[i][j], d_exp[i][j]))
+	return 0;
+
+  return float_eq_beebs(det, -16.6666718);
+}
+
+
+void
+initialise_benchmark (void)
+{
+}
+
+
+static int benchmark_body (int  rpt);
+
+void
+warm_caches (int  heat)
+{
+  int  res = benchmark_body (heat);
+
+  return;
+}
+
+
+int
+benchmark (void)
+{
+  return benchmark_body (LOCAL_SCALE_FACTOR * 1);
+}
+
+
+static int __attribute__ ((noinline))
+benchmark_body (int rpt)
+{
+  int i;
+
+  for (i = 0; i < rpt; i++)
+    {
+      float eps = 1.0e-6;
+
+      memcpy (a, a_ref, 3 * 3 * sizeof (a[0][0]));
+      minver (3, 3, eps);
+      memcpy (d, a, 3 * 3 * sizeof (a[0][0]));
+      memcpy (a, a_ref, 3 * 3 * sizeof (a[0][0]));
+      mmul (3, 3, 3, 3);
+    }
+
+  return 0;
+}
+
+
+/*
+   Local Variables:
+   mode: C
+   c-file-style: "gnu"
+   End:
+*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/main.c
new file mode 100644
index 00000000..64566101
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/main.c
@@ -0,0 +1,50 @@
+/* Common main.c for the benchmarks
+
+   Copyright (C) 2014 Embecosm Limited and University of Bristol
+   Copyright (C) 2018-2019 Embecosm Limited
+
+   Contributor: James Pallister <james.pallister@bristol.ac.uk>
+   Contributor: Jeremy Bennett <jeremy.bennett@embecosm.com>
+
+   This file is part of Embench and was formerly part of the Bristol/Embecosm
+   Embedded Benchmark Suite.
+
+   SPDX-License-Identifier: GPL-3.0-or-later */
+
+#include "csr.h"
+#include "x-heep.h"
+
+#include "support.h"
+
+
+int __attribute__ ((used))
+main (int argc __attribute__ ((unused)),
+      char *argv[] __attribute__ ((unused)))
+{
+  int i;
+  volatile int result;
+  int correct;
+
+  initialise_board ();
+  initialise_benchmark ();
+  warm_caches (1);
+
+  start_trigger ();
+  result = benchmark ();
+  stop_trigger ();
+
+  /* bmarks that use arrays will check a global array rather than int result */
+
+  correct = verify_benchmark (result);
+
+  return (!correct);
+
+}				/* main () */
+
+
+/*
+   Local Variables:
+   mode: C
+   c-file-style: "gnu"
+   End:
+*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/support.h b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/support.h
new file mode 100644
index 00000000..b68b81e6
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/support.h
@@ -0,0 +1,72 @@
+/* Support header for BEEBS.
+
+   Copyright (C) 2014 Embecosm Limited and the University of Bristol
+   Copyright (C) 2019 Embecosm Limited
+
+   Contributor James Pallister <james.pallister@bristol.ac.uk>
+
+   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+
+   This file is part of Embench and was formerly part of the Bristol/Embecosm
+   Embedded Benchmark Suite.
+
+   SPDX-License-Identifier: GPL-3.0-or-later */
+
+#ifndef SUPPORT_H
+#define SUPPORT_H
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+/* Include board support header if we have one */
+
+#ifdef HAVE_BOARDSUPPORT_H
+#include "boardsupport.h"
+#endif
+
+/* Benchmarks must implement verify_benchmark, which must return -1 if no
+   verification is done. */
+
+int verify_benchmark (int result);
+
+/* Standard functions implemented for each board */
+
+void initialise_board (void);
+void start_trigger (void);
+void stop_trigger (void);
+
+/* Every benchmark implements this for one-off data initialization.  This is
+   only used for initialization that is independent of how often benchmark ()
+   is called. */
+
+void initialise_benchmark (void);
+
+/* Every benchmark implements this for cache warm up, typically calling
+   benchmark several times. The argument controls how much warming up is
+   done, with 0 meaning no warming. */
+
+void warm_caches (int temperature);
+
+/* Every benchmark implements this as its entry point. Don't allow it to be
+   inlined! */
+
+int benchmark (void) __attribute__ ((noinline));
+
+/* Every benchmark must implement this to validate the result of the
+   benchmark. */
+
+int verify_benchmark (int res);
+
+/* Local simplified versions of library functions */
+
+#include "beebsc.h"
+
+#endif /* SUPPORT_H */
+
+/*
+   Local Variables:
+   mode: C
+   c-file-style: "gnu"
+   End:
+*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
new file mode 100644
index 00000000..5c7763f5
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
@@ -0,0 +1,1449 @@
+/*
+                              *******************
+******************************* C SOURCE FILE *****************************
+**                            *******************
+**
+** project  : X-HEEP
+** filename : w25q.c
+** version  : 1
+** date     : 1/11/2023
+**
+***************************************************************************
+**
+** Copyright (c) EPFL contributors.
+** All rights reserved.
+**
+***************************************************************************
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+/**
+* @file   w25q.c
+* @date   1/11/2023
+* @brief  Source file of the W25Q-family flash memory driver.
+*/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                             MODULES USED                                 */
+/**                                                                        **/
+/****************************************************************************/
+#include "string.h"
+
+#include "w25q128jw.h"
+
+/* To manage addresses. */
+#include "mmio.h"
+
+/* To manage interrupts. */
+#include "fast_intr_ctrl.h"
+#include "csr.h"
+#include "stdasm.h"
+
+/* To manage DMA. */
+#include "dma.h"
+
+/* To get TX and RX FIFO depth */
+#include "spi_host_regs.h"
+
+/* To get the target of the compilation (sim or pynq) */
+#include "x-heep.h"
+
+/* To get the soc_ctrl base address */
+#include "soc_ctrl_structs.h"
+
+/* For word swap operations*/
+#include "bitfield.h"
+
+/****************************************************************************/
+/**                                                                        **/
+/*                        DEFINITIONS AND MACROS                            */
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * The flash is expecting the address in Big endian format, so a swap is needed
+ * in order to provide the MSB first.
+ * Shift is needed as the byteswap is performed on 32-bit words.
+*/
+#define REVERT_24b_ADDR(addr) (bitfield_byteswap32(addr) >> 8)
+
+/**
+ * @bref If the target is the FPGA, use the SPI FLASH.
+*/
+#ifdef TARGET_PYNQ_Z2
+#define USE_SPI_FLASH
+#endif
+
+/****************************************************************************/
+/**                                                                        **/
+/*                      PROTOTYPES OF LOCAL FUNCTIONS                       */
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Power up the flash.
+*/
+static void flash_power_up(void);
+
+/**
+ * @brief Set the QE bit in the flash status register.
+ *
+ * @return FLASH_OK if the QE bit is set, @ref error_codes otherwise.
+*/
+static w25q_error_codes_t set_QE_bit(void);
+
+/**
+ * @brief Configure the SPI<->Flash connection paramethers.
+*/
+static void configure_spi(void);
+
+/**
+ * @brief Wait for the flash to be ready.
+ *
+ * It pools the BUSY bit in the flash status register.
+ * It is not checking the SUS bit status.
+*/
+static void flash_wait(void);
+
+/**
+ * @brief Reset the flash.
+*/
+static void flash_reset(void);
+
+/**
+ * @brief Erase the flash and write the data.
+ *
+ * It read 4k (a sector) at a time, erase it and write the data back.
+ * Befor writing the data back, it modifies the buffer in order to
+ * add the new data without modifing the other bytes. All the bytes
+ * that are not going to be modified will be copied back as is.
+ *
+ * @param addr 24-bit address to write to.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+static w25q_error_codes_t erase_and_write(uint32_t addr, uint8_t *data ,uint32_t length);
+
+/**
+ * @brief Wrapper for page write.
+ *
+ * It performs the sanity checks and calls the page_write function with
+ * the correct speed paramether. A wrapper is necessary as it is not possible
+ * to program more than a page (256 bytes) at a time. So multiple calls
+ * to page_write can be needed.
+ *
+ * @param addr 24-bit address to write to.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @param quad if 1, the write is performed at quad speed.
+ * @param dma if 1, the write is performed using DMA.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+static w25q_error_codes_t page_write_wrapper(uint32_t addr, uint8_t *data, uint32_t length, uint8_t quad, uint8_t dma);
+
+/**
+ * @brief Write (up to) a page to the flash.
+ *
+ * @param addr 24-bit address to write to.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @param quad if 1, the write is performed at quad speed.
+ * @param dma if 1, the write is performed using DMA.
+*/
+static w25q_error_codes_t page_write(uint32_t addr, uint8_t *data, uint32_t length, uint8_t quad, uint8_t dma);
+
+/**
+ * @brief Copy length bytes from data to the SPI TX FIFO, using DMA.
+ *
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to copy.
+
+ * @return FLASH_OK if the operation is successful, @ref error_codes otherwise.
+*/
+static w25q_error_codes_t dma_send_toflash(uint8_t *data, uint32_t length);
+
+/**
+ * @brief Enable flash write.
+ *
+ * It sets the WEL bit in the flash status register.
+ * Every action that require the WEL to be set is goig to automatically
+ * clear it.
+*/
+static void flash_write_enable(void);
+
+/**
+ * @brief Performs sanity checks on the input parameters.
+ *
+ * Checks if the address is valid, the data pointer is not NULL
+ * and the length is not 0.
+ *
+ * @param addr 24-bit address.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to read/write.
+ * @return FLASH_OK if the sanity checks are passed, @ref error_codes otherwise.
+*/
+static w25q_error_codes_t w25q128jw_sanity_checks(uint32_t addr, uint8_t *data, uint32_t length);
+
+/**
+ * @brief Return the minimum between two numbers.
+ *
+ * The function uses signed integers in order to handle also negative numbers.
+ *
+ * @param a first number.
+ * @param b second number.
+ * @return the minimum between a and b.
+*/
+static int32_t MIN(int32_t a, int32_t b) {
+    return (a < b) ? a : b;
+}
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            GLOBAL VARIABLES                              */
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief SPI structure.
+*/
+spi_host_t __attribute__((section(".xheep_init_data_crt0"))) spi; //this variable is also used by the crt0, thus keep it in this section
+
+/**
+ * @brief Static vector used in the erase_and_write function.
+ *
+ * It is used to store the data of a sector (4k) of the flash. Given the dimensions
+ * of the vector, is not possible to allocate it dinamically as it would cause a stack
+ * or heap overflow.
+*/
+uint8_t sector_data[FLASH_SECTOR_SIZE];
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                           EXPORTED FUNCTIONS                             */
+/**                                                                        **/
+/****************************************************************************/
+
+
+void w25q128jw_init_crt0() {
+    //make sure spi variable is into the xheep_init_data_crt0 section
+    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
+    return;
+}
+
+w25q_error_codes_t w25q128jw_init(spi_host_t spi_host) {
+    /*
+     * Check if memory mapped SPI is enabled. Current version of the bsp
+     * does not support memory mapped SPI.
+    */
+    if (soc_ctrl_peri->USE_SPIMEMIO == 1) {
+        return FLASH_ERROR; // Error
+    }
+
+    // Set the global spi variable to the one passed as argument.
+    spi = spi_host;
+
+    #ifdef USE_SPI_FLASH
+    // Select SPI host as SPI output
+    soc_ctrl_select_spi_host((soc_ctrl_t*)soc_ctrl_peri);
+    #endif // USE_SPI_FLASH
+
+    // Enable SPI host device
+    spi_set_enable(&spi, true);
+
+    // Enable SPI output
+    spi_output_enable(&spi, true);
+
+    // Configure SPI<->Flash connection on CSID 0
+    configure_spi();
+
+    // Set CSID
+    spi_set_csid(&spi, 0);
+
+    // Power up flash
+    flash_power_up();
+
+    // Set QE bit (only FPGA, simulation do not support status registers at all)
+    #ifdef TARGET_PYNQ_Z2
+    if (set_QE_bit() == FLASH_ERROR) return FLASH_ERROR; // Error occurred while setting QE bit
+    #endif // TARGET_PYNQ_Z2
+
+    return FLASH_OK; // Success
+}
+
+w25q_error_codes_t w25q128jw_read(uint32_t addr, void *data, uint32_t length) {
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    // Define the status variable
+    w25q_error_codes_t status;
+
+    if (length < RX_DMA_THRESHOLD) {
+        status = w25q128jw_read_quad(addr, data, length);
+        if (status != FLASH_OK) return status;
+    } else {
+        // Wait DMA to be free
+        while(!dma_is_ready());
+        status = w25q128jw_read_quad_dma(addr, data, length);
+        if (status != FLASH_OK) return status;
+    }
+
+    return FLASH_OK;
+}
+
+w25q_error_codes_t w25q128jw_write(uint32_t addr, void *data, uint32_t length, uint8_t erase_before_write) {
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    // Define the status variable
+    w25q_error_codes_t status = FLASH_OK;
+
+    if (erase_before_write == 1) {
+        status = erase_and_write(addr, data, length);
+    } else {
+        // Wait DMA to be free
+        while(!dma_is_ready());
+        status = w25q128jw_write_quad_dma(addr, data, length);
+    }
+
+    return status;
+}
+
+w25q_error_codes_t w25q128jw_read_standard(uint32_t addr, void* data, uint32_t length) {
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    // Address + Read command
+    uint32_t read_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_RD);
+    // Load command to TX FIFO
+    spi_write_word(&spi, read_byte_cmd);
+    spi_wait_for_ready(&spi);
+
+    // Set up segment parameters -> send command and address
+    const uint32_t cmd_read_1 = spi_create_command((spi_command_t){
+        .len        = 3,                 // 4 Bytes
+        .csaat      = true,              // Command not finished
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    // Load segment parameters to COMMAND register
+    spi_set_command(&spi, cmd_read_1);
+    spi_wait_for_ready(&spi);
+
+    // Set up segment parameters -> read length bytes
+    const uint32_t cmd_read_2 = spi_create_command((spi_command_t){
+        .len        = length-1,          // len bytes
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirRxOnly      // Read only
+    });
+    spi_set_command(&spi, cmd_read_2);
+    spi_wait_for_ready(&spi);
+
+    /*
+     * Set RX watermark to length. The watermark is in words.
+     * If the length is not a multiple of 4, the RX watermark is set to length/4+1
+     * to take into account the extra bytes.
+     * If the length is higher then the RX FIFO depth, the RX watermark is set to
+     * RX FIFO depth. In this case the flag is not set to 0, so the loop will
+     * continue until all the data is read.
+    */
+    int flag = 1;
+    int to_read = 0;
+    int i_start = 0;
+    int length_original = length;
+    uint32_t *data_32bit = (uint32_t *)data;
+    while (flag) {
+        if (length >= SPI_HOST_PARAM_RX_DEPTH) {
+            spi_set_rx_watermark(&spi, SPI_HOST_PARAM_RX_DEPTH>>2);
+            length -= SPI_HOST_PARAM_RX_DEPTH;
+            to_read += SPI_HOST_PARAM_RX_DEPTH;
+        }
+        else {
+            spi_set_rx_watermark(&spi, (length%4==0 ? length>>2 : (length>>2)+1));
+            to_read += length;
+            flag = 0;
+        }
+        // Wait till SPI RX FIFO is full (or I read all the data)
+        spi_wait_for_rx_watermark(&spi);
+        // Read data from SPI RX FIFO
+        for (int i = i_start; i < to_read>>2; i++) {
+            spi_read_word(&spi, &data_32bit[i]); // Writes a full word
+        }
+        // Update the starting index
+        i_start += SPI_HOST_PARAM_RX_DEPTH>>2;
+    }
+    // Take into account the extra bytes (if any)
+    if (length_original % 4 != 0) {
+        uint32_t last_word = 0;
+        spi_read_word(&spi, &last_word);
+        memcpy(&data_32bit[length_original>>2], &last_word, length%4);
+    }
+
+    return FLASH_OK; // Success
+}
+
+w25q_error_codes_t w25q128jw_write_standard(uint32_t addr, void* data, uint32_t length) {
+    // Call the wrapper with quad = 0, dma = 0
+    return page_write_wrapper(addr, data, length, 0, 0);
+}
+
+
+w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data, uint32_t length){
+
+    uint32_t remaining_length = length;
+    uint32_t current_addr = addr;
+    uint8_t *current_data = data;
+
+    w25q_error_codes_t status;
+
+    while (remaining_length > 0) {
+        // Start address of the sector to erase, 4kB aligned
+        uint32_t sector_start_addr = current_addr & 0xfffff000;
+
+        // Read the full sector and save it into RAM
+        status = w25q128jw_read_standard(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Erase the sector (no need to do so in simulation)
+        #ifdef TARGET_PYNQ_Z2
+        w25q128jw_4k_erase(sector_start_addr);
+        #endif // TARGET_PYNQ_Z2
+
+        // Calculate the length of data to write in this sector
+        uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
+
+        // Modify the data in RAM to include the new data
+        memcpy(&sector_data[current_addr - sector_start_addr], current_data, write_length);
+
+        // Write the modified data back to the flash
+        status = w25q128jw_write_standard(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Update the remaining length, address and data pointer
+        remaining_length -= write_length;
+        current_addr += write_length;
+        current_data += write_length;
+    }
+
+    return FLASH_OK;
+
+}
+
+
+
+w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length) {
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    /*
+     * SET UP DMA
+    */
+    // SPI and SPI_FLASH are the same IP so same register map
+    uint32_t *fifo_ptr_rx = spi.base_addr.base + SPI_HOST_RXDATA_REG_OFFSET;
+
+    // Init DMA, the integrated DMA is used (peri == NULL)
+    dma_init(NULL);
+
+    // The DMA will wait for the SPI HOST/FLASH RX FIFO valid signal
+    #ifndef USE_SPI_FLASH
+        uint8_t slot = DMA_TRIG_SLOT_SPI_RX;
+    #else
+        uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_RX;
+    #endif
+
+    // Set up DMA source target
+    static dma_target_t tgt_src = {
+        .inc_du = 0, // Target is peripheral, no increment
+        .type = DMA_DATA_TYPE_WORD, // Data type is word
+    };
+    // Size is in data units (words in this case)
+    tgt_src.size_du = length>>2;
+    // Target is SPI RX FIFO
+    tgt_src.ptr = (uint8_t*)fifo_ptr_rx;
+    // Trigger to control the data flow
+    tgt_src.trig = slot;
+
+    // Set up DMA destination target
+    static dma_target_t tgt_dst = {
+        .inc_du = 1, // Increment by 1 data unit (word)
+        .type = DMA_DATA_TYPE_WORD, // Data type is byte
+        .trig = DMA_TRIG_MEMORY, // Read-write operation to memory
+    };
+    tgt_dst.ptr = (uint8_t*)data; // Target is the data buffer
+
+    // Set up DMA transaction
+    static dma_trans_t trans = {
+        .src = &tgt_src,
+        .dst = &tgt_dst,
+        .end = DMA_TRANS_END_POLLING,
+    };
+
+    // Validate, load and launch DMA transaction
+    dma_config_flags_t res;
+    res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    res = dma_load_transaction(&trans);
+    res = dma_launch(&trans);
+
+    // Address + Read command
+    uint32_t read_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_RD);
+    // Load command to TX FIFO
+    spi_write_word(&spi, read_byte_cmd);
+    spi_wait_for_ready(&spi);
+
+    // Set up segment parameters -> send command and address
+    const uint32_t cmd_read_1 = spi_create_command((spi_command_t){
+        .len        = 3,                 // 4 Bytes
+        .csaat      = true,              // Command not finished
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    // Load segment parameters to COMMAND register
+    spi_set_command(&spi, cmd_read_1);
+    spi_wait_for_ready(&spi);
+
+    // Set up segment parameters -> read length bytes
+    const uint32_t cmd_read_2 = spi_create_command((spi_command_t){
+        .len        = length-1,          // len bytes
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirRxOnly      // Read only
+    });
+    spi_set_command(&spi, cmd_read_2);
+    spi_wait_for_ready(&spi);
+
+    // Wait for DMA to finish transaction
+    while(!dma_is_ready());
+
+    // Take into account the extra bytes (if any)
+    if (length % 4 != 0) {
+        uint32_t last_word = 0;
+        spi_read_word(&spi, &last_word);
+        memcpy(&data[length - length%4], &last_word, length%4);
+    }
+
+    return FLASH_OK;
+}
+
+w25q_error_codes_t w25q128jw_write_standard_dma(uint32_t addr, void *data, uint32_t length) {
+    // Call the wrapper with quad = 0, dma = 1
+    return page_write_wrapper(addr, data, length, 0, 1);
+}
+
+w25q_error_codes_t w25q128jw_erase_and_write_standard_dma(uint32_t addr, void* data, uint32_t length){
+
+    uint32_t remaining_length = length;
+    uint32_t current_addr = addr;
+    uint8_t *current_data = data;
+
+    w25q_error_codes_t status;
+
+    while (remaining_length > 0) {
+        // Start address of the sector to erase, 4kB aligned
+        uint32_t sector_start_addr = current_addr & 0xfffff000;
+
+        // Read the full sector and save it into RAM
+        status = w25q128jw_read_standard_dma(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Erase the sector (no need to do so in simulation)
+        #ifdef TARGET_PYNQ_Z2
+        w25q128jw_4k_erase(sector_start_addr);
+        #endif // TARGET_PYNQ_Z2
+
+        // Calculate the length of data to write in this sector
+        uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
+
+        // Modify the data in RAM to include the new data
+        memcpy(&sector_data[current_addr - sector_start_addr], current_data, write_length);
+
+        // Write the modified data back to the flash
+        status = w25q128jw_write_standard_dma(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Update the remaining length, address and data pointer
+        remaining_length -= write_length;
+        current_addr += write_length;
+        current_data += write_length;
+    }
+
+    return FLASH_OK;
+
+}
+
+
+w25q_error_codes_t w25q128jw_read_quad(uint32_t addr, void *data, uint32_t length) {
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    // Send quad read command at standard speed
+    uint32_t cmd_read_quadIO = FC_RDQIO;
+    spi_write_word(&spi, cmd_read_quadIO);
+    const uint32_t cmd_read = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = true,              // Command not finished
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_read);
+    spi_wait_for_ready(&spi);
+
+    /*
+     * Send address at quad speed.
+     * Last byte is Fxh (here FFh) required by W25Q128JW
+    */
+    uint32_t read_byte_cmd = (REVERT_24b_ADDR(addr) | (0xFF << 24));
+    spi_write_word(&spi, read_byte_cmd);
+    const uint32_t cmd_address = spi_create_command((spi_command_t){
+        .len        = 3,                // 3 Byte
+        .csaat      = true,             // Command not finished
+        .speed      = kSpiSpeedQuad,    // Quad speed
+        .direction  = kSpiDirTxOnly     // Write only
+    });
+    spi_set_command(&spi, cmd_address);
+    spi_wait_for_ready(&spi);
+
+    // Quad read requires dummy clocks
+    const uint32_t dummy_clocks_cmd = spi_create_command((spi_command_t){
+        #ifdef TARGET_PYNQ_Z2
+        .len        = DUMMY_CLOCKS_FAST_READ_QUAD_IO-1,
+        #else
+        .len        = DUMMY_CLOCKS_SIM-1,
+        #endif
+        .csaat      = true,            // Command not finished
+        .speed      = kSpiSpeedQuad,   // Quad speed
+        .direction  = kSpiDirDummy     // Dummy
+    });
+    spi_set_command(&spi, dummy_clocks_cmd);
+    spi_wait_for_ready(&spi);
+
+    // Read back the requested data at quad speed
+    const uint32_t cmd_read_rx = spi_create_command((spi_command_t){
+        .len        = length-1,        // 32 Byte
+        .csaat      = false,           // End command
+        .speed      = kSpiSpeedQuad,   // Quad speed
+        .direction  = kSpiDirRxOnly    // Read only
+    });
+    spi_set_command(&spi, cmd_read_rx);
+    spi_wait_for_ready(&spi);
+
+    /* COMMAND FINISHED */
+
+    /*
+     * Set RX watermark to length. The watermark is in words.
+     * If the length is not a multiple of 4, the RX watermark is set to length/4+1
+     * to take into account the extra bytes.
+     * If the length is higher then the RX FIFO depth, the RX watermark is set to
+     * RX FIFO depth. In this case the flag is not set to 0, so the loop will
+     * continue until all the data is read.
+    */
+    int flag = 1;
+    int to_read = 0;
+    int i_start = 0;
+    int length_original = length;
+    uint32_t *data_32bit = (uint32_t *)data;
+    while (flag) {
+        if (length >= SPI_HOST_PARAM_RX_DEPTH) {
+            spi_set_rx_watermark(&spi, SPI_HOST_PARAM_RX_DEPTH>>2);
+            length -= SPI_HOST_PARAM_RX_DEPTH;
+            to_read += SPI_HOST_PARAM_RX_DEPTH;
+        }
+        else {
+            spi_set_rx_watermark(&spi, (length%4==0 ? length>>2 : (length>>2)+1));
+            to_read += length;
+            flag = 0;
+        }
+        // Wait till SPI RX FIFO is full (or I read all the data)
+        spi_wait_for_rx_watermark(&spi);
+        // Read data from SPI RX FIFO
+        for (int i = i_start; i < to_read>>2; i++) {
+            spi_read_word(&spi, &data_32bit[i]); // Writes a full word
+        }
+        // Update the starting index
+        i_start += SPI_HOST_PARAM_RX_DEPTH>>2;
+    }
+    // Take into account the extra bytes (if any)
+    if (length_original%4 != 0) {
+        uint32_t last_word = 0;
+        spi_read_word(&spi, &last_word);
+        memcpy(&data_32bit[length_original>>2], &last_word, length%4);
+    }
+
+    return FLASH_OK; // Success
+}
+
+w25q_error_codes_t w25q128jw_write_quad(uint32_t addr, void *data, uint32_t length) {
+    // Call the wrapper with quad = 1, dma = 0
+    return page_write_wrapper(addr, data, length, 1, 0);
+}
+
+
+w25q_error_codes_t w25q128jw_erase_and_write_quad(uint32_t addr, void *data, uint32_t length) {
+
+    uint32_t remaining_length = length;
+    uint32_t current_addr = addr;
+    uint8_t *current_data = data;
+
+    w25q_error_codes_t status;
+
+    while (remaining_length > 0) {
+        // Start address of the sector to erase, 4kB aligned
+        uint32_t sector_start_addr = current_addr & 0xfffff000;
+
+        // Read the full sector and save it into RAM
+        status = w25q128jw_read_quad(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Erase the sector (no need to do so in simulation)
+        #ifdef TARGET_PYNQ_Z2
+        w25q128jw_4k_erase(sector_start_addr);
+        #endif // TARGET_PYNQ_Z2
+
+        // Calculate the length of data to write in this sector
+        uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
+
+        // Modify the data in RAM to include the new data
+        memcpy(&sector_data[current_addr - sector_start_addr], current_data, write_length);
+
+        // Write the modified data back to the flash
+        status = w25q128jw_write_quad(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Update the remaining length, address and data pointer
+        remaining_length -= write_length;
+        current_addr += write_length;
+        current_data += write_length;
+    }
+
+    return FLASH_OK;
+
+}
+
+
+w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t length) {
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    // Send quad read command at standard speed
+    uint32_t cmd_read_quadIO = FC_RDQIO;
+    spi_write_word(&spi, cmd_read_quadIO);
+    const uint32_t cmd_read = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = true,              // Command not finished
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_read);
+    spi_wait_for_ready(&spi);
+
+    /*
+     * Send address at quad speed.
+     * Last byte is Fxh (here FFh) required by W25Q128JW
+    */
+    uint32_t read_byte_cmd = (REVERT_24b_ADDR(addr) | (0xFF << 24));
+    spi_write_word(&spi, read_byte_cmd);
+    const uint32_t cmd_address = spi_create_command((spi_command_t){
+        .len        = 3,                // 3 Byte
+        .csaat      = true,             // Command not finished
+        .speed      = kSpiSpeedQuad,    // Quad speed
+        .direction  = kSpiDirTxOnly     // Write only
+    });
+    spi_set_command(&spi, cmd_address);
+    spi_wait_for_ready(&spi);
+
+    // Quad read requires dummy clocks
+    const uint32_t dummy_clocks_cmd = spi_create_command((spi_command_t){
+        #ifdef TARGET_PYNQ_Z2
+        .len        = DUMMY_CLOCKS_FAST_READ_QUAD_IO-1, // W25Q128JW flash needs 4 dummy cycles
+        #else
+        .len        = DUMMY_CLOCKS_SIM-1, // SPI flash simulation model needs 8 dummy cycles
+        #endif
+        .csaat      = true,              // Command not finished
+        .speed      = kSpiSpeedQuad,     // Quad speed
+        .direction  = kSpiDirDummy       // Dummy
+    });
+    spi_set_command(&spi, dummy_clocks_cmd);
+    spi_wait_for_ready(&spi);
+
+    // Read back the requested data at quad speed
+    const uint32_t cmd_read_rx = spi_create_command((spi_command_t){
+        .len        = length-1,        // length bytes
+        .csaat      = false,           // End command
+        .speed      = kSpiSpeedQuad,   // Quad speed
+        .direction  = kSpiDirRxOnly    // Read only
+    });
+    spi_set_command(&spi, cmd_read_rx);
+    spi_wait_for_ready(&spi);
+
+    /* COMMAND FINISHED */
+
+    /*
+     * SET UP DMA
+    */
+    // SPI and SPI_FLASH are the same IP so same register map
+    uint32_t *fifo_ptr_rx = spi.base_addr.base + SPI_HOST_RXDATA_REG_OFFSET;
+
+    // Init DMA, the integrated DMA is used (peri == NULL)
+    dma_init(NULL);
+
+    // The DMA will wait for the SPI HOST/FLASH RX FIFO valid signal
+    #ifndef USE_SPI_FLASH
+        uint8_t slot = DMA_TRIG_SLOT_SPI_RX;
+    #else
+        uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_RX;
+    #endif
+
+    // Set up DMA source target
+    static dma_target_t tgt_src = {
+        .inc_du = 0, // Target is peripheral, no increment
+        .type = DMA_DATA_TYPE_WORD, // Data type is byte
+    };
+    // Size is in data units (words in this case)
+    tgt_src.size_du = length>>2;
+    // Target is SPI RX FIFO
+    tgt_src.ptr = (uint8_t*)fifo_ptr_rx;
+    // Trigger to control the data flow
+    tgt_src.trig = slot;
+
+    // Set up DMA destination target
+    static dma_target_t tgt_dst = {
+        .inc_du = 1, // Increment by 1 data unit (word)
+        .type = DMA_DATA_TYPE_WORD, // Data type is byte
+        .trig = DMA_TRIG_MEMORY, // Read-write operation to memory
+    };
+    tgt_dst.ptr = (uint8_t*)data; // Target is the data buffer
+
+    // Set up DMA transaction
+    static dma_trans_t trans = {
+        .src = &tgt_src,
+        .dst = &tgt_dst,
+        .end = DMA_TRANS_END_POLLING,
+    };
+
+    // Validate, load and launch DMA transaction
+    dma_config_flags_t res;
+    res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    res = dma_load_transaction(&trans);
+    res = dma_launch(&trans);
+
+    // Wait for DMA to finish transaction
+    while(!dma_is_ready());
+
+    // Take into account the extra bytes (if any)
+    if (length % 4 != 0) {
+        uint32_t last_word = 0;
+        spi_read_word(&spi, &last_word);
+        memcpy(&data[length - length%4], &last_word, length%4);
+    }
+
+    return FLASH_OK;
+}
+
+w25q_error_codes_t w25q128jw_write_quad_dma(uint32_t addr, void *data, uint32_t length) {
+    // Call the wrapper with quad = 1, dma = 1
+    return page_write_wrapper(addr, data, length, 1, 1);
+}
+
+w25q_error_codes_t w25q128jw_erase_and_write_quad_dma(uint32_t addr, void *data, uint32_t length) {
+
+    uint32_t remaining_length = length;
+    uint32_t current_addr = addr;
+    uint8_t *current_data = data;
+
+    w25q_error_codes_t status;
+
+    while (remaining_length > 0) {
+        // Start address of the sector to erase, 4kB aligned
+        uint32_t sector_start_addr = current_addr & 0xfffff000;
+
+        // Read the full sector and save it into RAM
+        status = w25q128jw_read_quad_dma(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Erase the sector (no need to do so in simulation)
+        #ifdef TARGET_PYNQ_Z2
+        w25q128jw_4k_erase(sector_start_addr);
+        #endif // TARGET_PYNQ_Z2
+
+        // Calculate the length of data to write in this sector
+        uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
+
+        // Modify the data in RAM to include the new data
+        memcpy(&sector_data[current_addr - sector_start_addr], current_data, write_length);
+
+        // Write the modified data back to the flash
+        status = w25q128jw_write_quad_dma(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Update the remaining length, address and data pointer
+        remaining_length -= write_length;
+        current_addr += write_length;
+        current_data += write_length;
+    }
+
+    return FLASH_OK;
+
+}
+
+w25q_error_codes_t w25q128jw_4k_erase(uint32_t addr) {
+    // Sanity checks
+    if (addr > MAX_FLASH_ADDR || addr < 0) return FLASH_ERROR;
+
+    // Wait any other operation to finish
+    flash_wait();
+
+    // Enable flash write in order to erase
+    flash_write_enable();
+
+    // Build and send erase command
+    uint32_t erase_4k_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_SE);
+    spi_write_word(&spi, erase_4k_cmd);
+    spi_wait_for_ready(&spi);
+    const uint32_t cmd_erase = spi_create_command((spi_command_t){
+        .len        = 3,                 // 4 Bytes
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_erase);
+    spi_wait_for_ready(&spi);
+
+    // Wait for the erase operation to be finished
+    flash_wait();
+}
+
+w25q_error_codes_t w25q128jw_32k_erase(uint32_t addr) {
+    // Sanity checks
+    if (addr > 0x00ffffff || addr < 0) return FLASH_ERROR;
+
+    // Wait any other operation to finish
+    flash_wait();
+
+    // Enable flash write in order to erase
+    flash_write_enable();
+
+    // Build and send erase command
+    uint32_t erase_32k_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_BE32);
+    spi_write_word(&spi, erase_32k_cmd);
+    spi_wait_for_ready(&spi);
+    const uint32_t cmd_erase = spi_create_command((spi_command_t){
+        .len        = 3,                 // 4 Bytes
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_erase);
+    spi_wait_for_ready(&spi);
+
+    // Wait for the erase operation to be finished
+    flash_wait();
+}
+
+w25q_error_codes_t w25q128jw_64k_erase(uint32_t addr) {
+    // Sanity checks
+    if (addr > 0x00ffffff || addr < 0) return FLASH_ERROR;
+
+    // Wait any other operation to finish
+    flash_wait();
+
+    // Enable flash write in order to erase
+    flash_write_enable();
+
+    // Build and send erase command
+    uint32_t erase_64k_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_BE64);
+    spi_write_word(&spi, erase_64k_cmd);
+    spi_wait_for_ready(&spi);
+    const uint32_t cmd_erase = spi_create_command((spi_command_t){
+        .len        = 3,                 // 4 Bytes
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_erase);
+    spi_wait_for_ready(&spi);
+
+    // Wait for the erase operation to be finished
+    flash_wait();
+}
+
+void w25q128jw_chip_erase(void) {
+    // Wait any other operation to finish
+    flash_wait();
+
+    // Enable flash write in order to erase
+    flash_write_enable();
+
+    // Build and send erase command
+    spi_write_word(&spi, FC_CE);
+    spi_wait_for_ready(&spi);
+    const uint32_t cmd_erase = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Bytes
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_erase);
+    spi_wait_for_ready(&spi);
+
+    // Wait for the erase operation to be finished
+    flash_wait();
+}
+
+void w25q128jw_reset(void) {
+    // Wait for ongoing operation to finish (if any)
+    flash_wait();
+
+    // Build and send reset command
+    flash_reset();
+
+    // Wait for the reset operation to be finished
+    flash_wait();
+}
+
+void w25q128jw_reset_force(void) {
+    // Build and send reset command without waiting for ongoing operation
+    flash_reset();
+
+    // Wait for the reset operation to be finished
+    flash_wait();
+}
+
+void w25q128jw_power_down(void) {
+    // Build and send power down command
+    spi_write_word(&spi, FC_PD);
+    const uint32_t cmd_power_down = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_power_down);
+    spi_wait_for_ready(&spi);
+}
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            LOCAL FUNCTIONS                               */
+/**                                                                        **/
+/****************************************************************************/
+
+static void flash_power_up(void) {
+    spi_write_word(&spi, FC_RPD);
+    spi_wait_for_ready(&spi);
+    const uint32_t cmd_powerup = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_powerup);
+    spi_wait_for_ready(&spi);
+}
+
+static w25q_error_codes_t set_QE_bit(void) {
+    spi_set_rx_watermark(&spi,1);
+
+    // Read Status Register 2
+    const uint32_t reg2_read_cmd = FC_RSR2;
+    spi_write_word(&spi, reg2_read_cmd);
+
+    const uint32_t reg2_read_1 = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = true,              // Command not finished
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, reg2_read_1);
+    spi_wait_for_ready(&spi);
+
+    const uint32_t reg2_read_2 = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Standard speed
+        .direction  = kSpiDirRxOnly      // Read only
+    });
+    spi_set_command(&spi, reg2_read_2);
+    spi_wait_for_ready(&spi);
+    spi_wait_for_rx_watermark(&spi);
+
+    /*
+     * the partial word will be zero-padded and inserted into the RX FIFO once the segment is completed
+     * The actual register is 8 bit, but the SPI host gives a full word
+    */
+    uint32_t reg2_data;
+    spi_read_word(&spi, &reg2_data);
+
+    // Set bit in position 1 (QE bit), leaving the others unchanged
+    reg2_data |= 0x2;
+
+    // Enable write operation
+    flash_write_enable();
+
+    // Write Status Register 2 (set QE bit)
+    const uint32_t reg2_write_cmd = FC_WSR2;
+    spi_write_word(&spi, reg2_write_cmd);
+
+    const uint32_t reg2_write_1 = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = true,              // Command not finished
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, reg2_write_1);
+    spi_wait_for_ready(&spi);
+
+    // Load data to TX FIFO
+    spi_write_word(&spi, reg2_data);
+
+    // Create command segment
+    const uint32_t reg2_write_2 = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Standard speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, reg2_write_2);
+    spi_wait_for_ready(&spi);
+
+    // Wait flash to complete write routine
+    flash_wait();
+
+    // Read back Status Register 2
+    spi_write_word(&spi, reg2_read_cmd);
+    spi_set_command(&spi, reg2_read_1);
+    spi_wait_for_ready(&spi);
+    spi_set_command(&spi, reg2_read_2);
+    spi_wait_for_ready(&spi);
+    spi_wait_for_rx_watermark(&spi);
+    uint32_t reg2_data_check = 0x00;
+    spi_read_word(&spi, &reg2_data_check);
+
+    // Check if the QE bit is set
+    if ((reg2_data_check & 0x2) == 0) return FLASH_ERROR;
+    else return FLASH_OK;
+}
+
+static void configure_spi(void) {
+    // Configure SPI clock
+    uint32_t core_clk = soc_ctrl_peri->SYSTEM_FREQUENCY_HZ;
+    uint16_t clk_div = 0;
+    if(FLASH_CLK_MAX_HZ < core_clk/2){
+        clk_div = (core_clk/(FLASH_CLK_MAX_HZ) - 2)/2; // The value is truncated
+        if (core_clk/(2 + 2 * clk_div) > FLASH_CLK_MAX_HZ) clk_div += 1; // Adjust if the truncation was not 0
+    }
+    // SPI Configuration
+    // Configure chip 0 (flash memory)
+    const uint32_t chip_cfg = spi_create_configopts((spi_configopts_t){
+        .clkdiv     = clk_div,
+        .csnidle    = 0xF,
+        .csntrail   = 0xF,
+        .csnlead    = 0xF,
+        .fullcyc    = false,
+        .cpha       = 0,
+        .cpol       = 0
+    });
+    spi_set_configopts(&spi, 0, chip_cfg);
+}
+
+static void flash_wait(void) {
+    spi_set_rx_watermark(&spi,1);
+    bool flash_busy = true;
+    uint8_t flash_resp[4] = {0xff,0xff,0xff,0xff};
+
+    while(flash_busy){
+        uint32_t flash_cmd = FC_RSR1; // [CMD] Read status register 1
+        spi_write_word(&spi, flash_cmd); // Push TX buffer
+        uint32_t spi_status_cmd = spi_create_command((spi_command_t){
+            .len        = 0,
+            .csaat      = true,
+            .speed      = kSpiSpeedStandard,
+            .direction  = kSpiDirTxOnly
+        });
+        uint32_t spi_status_read_cmd = spi_create_command((spi_command_t){
+            .len        = 0,
+            .csaat      = false,
+            .speed      = kSpiSpeedStandard,
+            .direction  = kSpiDirRxOnly
+        });
+        spi_set_command(&spi, spi_status_cmd);
+        spi_wait_for_ready(&spi);
+        spi_set_command(&spi, spi_status_read_cmd);
+        spi_wait_for_ready(&spi);
+        spi_wait_for_rx_watermark(&spi);
+        spi_read_word(&spi, (uint32_t *)flash_resp);
+        if ((flash_resp[0] & 0x01) == 0) flash_busy = false;
+    }
+}
+
+static void flash_reset(void) {
+    spi_write_word(&spi, FC_ERESET);
+    spi_write_word(&spi, FC_RESET);
+    spi_wait_for_ready(&spi);
+
+    const uint32_t cmd_reset_enable = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_reset_enable);
+    spi_wait_for_ready(&spi);
+    const uint32_t cmd_reset = spi_create_command((spi_command_t){
+        .len        = 0,                 // 1 Byte
+        .csaat      = false,             // End command
+        .speed      = kSpiSpeedStandard, // Single speed
+        .direction  = kSpiDirTxOnly      // Write only
+    });
+    spi_set_command(&spi, cmd_reset);
+    spi_wait_for_ready(&spi);
+}
+
+w25q_error_codes_t erase_and_write(uint32_t addr, uint8_t *data, uint32_t length) {
+
+    uint32_t remaining_length = length;
+    uint32_t current_addr = addr;
+    uint8_t *current_data = data;
+
+    w25q_error_codes_t status;
+
+    while (remaining_length > 0) {
+        // Start address of the sector to erase, 4kB aligned
+        uint32_t sector_start_addr = current_addr & 0xfffff000;
+
+        // Read the full sector and save it into RAM
+        status = w25q128jw_read(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Erase the sector (no need to do so in simulation)
+        #ifdef TARGET_PYNQ_Z2
+        w25q128jw_4k_erase(sector_start_addr);
+        #endif // TARGET_PYNQ_Z2
+
+        // Calculate the length of data to write in this sector
+        uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
+
+        // Modify the data in RAM to include the new data
+        memcpy(&sector_data[current_addr - sector_start_addr], current_data, write_length);
+
+        // Write the modified data back to the flash (without erasing this time)
+        status = w25q128jw_write(sector_start_addr, sector_data, FLASH_SECTOR_SIZE, 0);
+        if (status != FLASH_OK) return FLASH_ERROR;
+
+        // Update the remaining length, address and data pointer
+        remaining_length -= write_length;
+        current_addr += write_length;
+        current_data += write_length;
+    }
+
+    return FLASH_OK;
+}
+
+static w25q_error_codes_t page_write_wrapper(uint32_t addr, uint8_t *data, uint32_t length, uint8_t quad, uint8_t dma) {
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    // Pointer arithmetics is not allowed on void pointers
+    uint8_t *data_8bit = (uint8_t *)data;
+
+    /*
+     * Set speed and DMA flags.
+     * Robust implementation: no need to perform safety checks on the flags.
+    */
+    uint8_t speed = quad==1 ? 1 : 0;
+    uint8_t dma_flag = dma==1 ? 1 : 0;
+
+    /*
+     * Taking care of misalligned start address.
+     * If the start address is not aligned to a 256 bytes boundary,
+     * the first page is written with the first 256 - (addr % 256) bytes.
+    */
+    if (addr % FLASH_PAGE_SIZE != 0) {
+        uint8_t tmp_len = FLASH_PAGE_SIZE - (addr % FLASH_PAGE_SIZE);
+        tmp_len = MIN(tmp_len, length);
+        page_write(addr, data_8bit, tmp_len, speed, dma_flag);
+        addr += tmp_len;
+        data_8bit += tmp_len;
+        length -= tmp_len;
+    }
+
+    // Check if we already finished
+    if (length == 0) return FLASH_OK;
+
+    // I cannot program more than a page (256 Bytes) at a time.
+    int flag = 1;
+    while (flag) {
+        if (length > FLASH_PAGE_SIZE) {
+            page_write(addr, data_8bit, FLASH_PAGE_SIZE, speed, dma_flag);
+            addr += FLASH_PAGE_SIZE;
+            data_8bit += FLASH_PAGE_SIZE;
+            length -= FLASH_PAGE_SIZE;
+        } else {
+            page_write(addr, data_8bit, length, speed, dma_flag);
+            flag = 0;
+        }
+    }
+    return FLASH_OK;
+}
+
+static w25q_error_codes_t page_write(uint32_t addr, uint8_t *data, uint32_t length, uint8_t quad, uint8_t dma) {
+    // Required every time before issuing a write command
+    flash_write_enable();
+
+    /*
+     * Build and send write command (24bit address + command).
+     * The command is picked based on the quad flag.
+    */
+    const uint32_t write_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | (quad ? FC_PPQ : FC_PP));
+    spi_write_word(&spi, write_byte_cmd);
+    const uint32_t cmd_write = spi_create_command((spi_command_t){
+        .len        = 3,
+        .csaat      = true,
+        .speed      = kSpiSpeedStandard,
+        .direction  = kSpiDirTxOnly
+    });
+    spi_set_command(&spi, cmd_write);
+    spi_wait_for_ready(&spi);
+
+    /*
+     * Place data in TX FIFO
+     * In simulation it do not wait for the flash to be ready, so we must check
+     * if the FIFO is full before writing.
+    */
+    if (dma) {
+        dma_send_toflash(data, length);
+    } else {
+        uint32_t *data_32bit = (uint32_t *)data;
+        for (int i = 0; i < length>>2; i++) {
+            spi_wait_for_tx_not_full(&spi);
+            spi_write_word(&spi, data_32bit[i]);
+        }
+        if (length % 4 != 0) {
+            uint32_t last_word = 0;
+            memcpy(&last_word, &data[length - length % 4], length % 4);
+            spi_wait_for_tx_not_full(&spi);
+            spi_write_word(&spi, last_word);
+        }
+    }
+
+    /*
+     * Set up segment parameters -> send data.
+     * Speed is quad if quad flag is set, standard otherwise.
+    */
+    const uint32_t cmd_write_2 = spi_create_command((spi_command_t){
+        .len        = length-1,
+        .csaat      = false,
+        .speed      = quad ? kSpiSpeedQuad : kSpiSpeedStandard,
+        .direction  = kSpiDirTxOnly
+    });
+    spi_set_command(&spi, cmd_write_2);
+    spi_wait_for_ready(&spi);
+
+    // Wait for flash to be ready again (FPGA only)
+    #ifdef TARGET_PYNQ_Z2
+    flash_wait();
+    #endif // TARGET_PYNQ_Z2
+}
+
+static w25q_error_codes_t dma_send_toflash(uint8_t *data, uint32_t length) {
+    // SPI and SPI_FLASH are the same IP so same register map
+    uint32_t *fifo_ptr_tx = spi.base_addr.base + SPI_HOST_TXDATA_REG_OFFSET;
+
+    // Init DMA, the integrated DMA is used (peri == NULL)
+    dma_init(NULL);
+
+    // The DMA will wait for the SPI HOST/FLASH TX FIFO valid signal
+    #ifndef USE_SPI_FLASH
+        uint8_t slot = DMA_TRIG_SLOT_SPI_TX;
+    #else
+        uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_TX;
+    #endif
+
+    // Set up DMA source target
+    static dma_target_t tgt_src = {
+        .inc_du = 1, // Increment by 1 data unit (word)
+        .type = DMA_DATA_TYPE_WORD, // Data type is word
+    };
+    // Size is in data units (words in this case)
+    tgt_src.size_du = length>>2;
+    // Target is data buffer
+    tgt_src.ptr = data;
+    // Reads from memory
+    tgt_src.trig = DMA_TRIG_MEMORY;
+
+    // Set up DMA destination target
+    static dma_target_t tgt_dst = {
+        .inc_du = 0, // It's a peripheral, no increment
+        .type = DMA_DATA_TYPE_WORD, // Data type is word
+    };
+    tgt_dst.trig = slot;
+    tgt_dst.ptr = (uint8_t*)fifo_ptr_tx; // Target is SPI TX FIFO
+
+    // Set up DMA transaction
+    static dma_trans_t trans = {
+        .src = &tgt_src,
+        .dst = &tgt_dst,
+        .mode = DMA_TRANS_MODE_SINGLE,
+        .win_du = 0,
+        .end = DMA_TRANS_END_POLLING,
+    };
+
+    // Validate, load and launch DMA transaction
+    dma_config_flags_t res;
+    res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    if (res != DMA_CONFIG_OK) return FLASH_ERROR_DMA;
+    res = dma_load_transaction(&trans);
+    if (res != DMA_CONFIG_OK) return FLASH_ERROR_DMA;
+    res = dma_launch(&trans);
+    if (res != DMA_CONFIG_OK) return FLASH_ERROR_DMA;
+
+    // Wait for DMA to finish transaction
+    while(!dma_is_ready());
+
+    // Take into account the extra bytes (if any)
+    if (length % 4 != 0) {
+        uint32_t last_word = 0;
+        memcpy(&last_word, &data[length - length % 4], length % 4);
+        spi_wait_for_tx_not_full(&spi);
+        spi_write_word(&spi, last_word);
+    }
+    return FLASH_OK;
+}
+
+static void flash_write_enable(void) {
+    spi_write_word(&spi, FC_WE);
+    const uint32_t cmd_write_en = spi_create_command((spi_command_t){
+        .len        = 0,
+        .csaat      = false,
+        .speed      = kSpiSpeedStandard,
+        .direction  = kSpiDirTxOnly
+    });
+    spi_set_command(&spi, cmd_write_en);
+    spi_wait_for_ready(&spi);
+}
+
+static w25q_error_codes_t w25q128jw_sanity_checks(uint32_t addr, uint8_t *data, uint32_t length) {
+    // Check if address is out of range
+    if (addr > MAX_FLASH_ADDR || addr < 0) return FLASH_ERROR;
+
+    // Check if data pointer is NULL
+    if (data == NULL) return FLASH_ERROR;
+
+    // Check if length is 0
+    if (length <= 0) return FLASH_ERROR;
+
+    // Check if current address + length is out of range
+    if (addr + length > MAX_FLASH_ADDR) return FLASH_ERROR;
+
+    return FLASH_OK; // Success
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/*                                 EOF                                      */
+/**                                                                        **/
+/****************************************************************************/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
new file mode 100644
index 00000000..c6f29e9c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
@@ -0,0 +1,433 @@
+/*
+                              *******************
+******************************* H HEADER FILE *****************************
+**                            *******************
+**
+** project  : X-HEEP
+** filename : w25q128jw.h
+** version  : 1
+** date     : 1/11/2023
+**
+***************************************************************************
+**
+** Copyright (c) EPFL contributors.
+** All rights reserved.
+**
+***************************************************************************
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+
+/**
+* @file   w25q128jw.h
+* @date   13/02/23
+* @brief  Header file for the W25Q128JW flash memory.
+*/
+
+#ifndef W25Q128JW_H
+#define W25Q128JW_H
+
+/****************************************************************************/
+/**                                                                        **/
+/**                            MODULES USED                                **/
+/**                                                                        **/
+/****************************************************************************/
+
+#include "spi_host.h"
+#include "soc_ctrl.h"
+#include "core_v_mini_mcu.h"
+
+/****************************************************************************/
+/**                                                                        **/
+/**                       DEFINITIONS AND MACROS                           **/
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * In Hz (133 MHz for the flash w25q128jvsim used in the EPFL Programmer)
+*/
+#define FLASH_CLK_MAX_HZ (133*1000*1000)
+
+/**
+ * @defgroup flash_commands Flash commands
+ * @{
+ */
+#define FC_WE      0x06 /** Write Enable */
+#define FC_SRWE    0x50 /** Volatile SR Write Enable */
+#define FC_WD      0x04 /** Write Disable */
+#define FC_RPD     0xAB /** Release Power-Down, returns Device ID */
+#define FC_MFGID   0x90 /** Read Manufacturer/Device ID */
+#define FC_JEDECID 0x9F /** Read JEDEC ID */
+#define FC_UID     0x4B /** Read Unique ID */
+#define FC_RD      0x03 /** Read Data */
+#define FC_FR      0x0B /** Fast Read */
+#define FC_RDQIO   0xEB /** Fast Read Quad I/O */
+#define FC_PP      0x02 /** Page Program */
+#define FC_PPQ     0x32 /** Quad Input Page Program */
+#define FC_SE      0x20 /** Sector Erase 4kb */
+#define FC_BE32    0x52 /** Block Erase 32kb */
+#define FC_BE64    0xD8 /** Block Erase 64kb */
+#define FC_CE      0xC7 /** Chip Erase */
+#define FC_RSR1    0x05 /** Read Status Register 1 */
+#define FC_WSR1    0x01 /** Write Status Register 1 */
+#define FC_RSR2    0x35 /** Read Status Register 2 */
+#define FC_WSR2    0x31 /** Write Status Register 2 */
+#define FC_RSR3    0x15 /** Read Status Register 3 */
+#define FC_WSR3    0x11 /** Write Status Register 3 */
+#define FC_RSFDP   0x5A /** Read SFDP Register */
+#define FC_ESR     0x44 /** Erase Security Register */
+#define FC_PSR     0x42 /** Program Security Register */
+#define FC_RSR     0x48 /** Read Security Register */
+#define FC_GBL     0x7E /** Global Block Lock */
+#define FC_GBU     0x98 /** Global Block Unlock */
+#define FC_RBL     0x3D /** Read Block Lock */
+#define FC_RPR     0x3C /** Read Sector Protection Registers (adesto) */
+#define FC_IBL     0x36 /** Individual Block Lock */
+#define FC_IBU     0x39 /** Individual Block Unlock */
+#define FC_EPS     0x75 /** Erase / Program Suspend */
+#define FC_EPR     0x7A /** Erase / Program Resume */
+#define FC_PD      0xB9 /** Power-down */
+#define FC_QPI     0x38 /** Enter QPI mode */
+#define FC_ERESET  0x66 /** Enable Reset */
+#define FC_RESET   0x99 /** Reset Device */
+/** @} */
+
+/**
+ * @defgroup error_codes Error codes
+ * @{
+*/
+#define FLASH_OK    0      /** No error @hideinitializer*/
+#define FLASH_ERROR 1      /** Generic error @hideinitializer*/
+#define FLASH_ERROR_DMA 2  /** DMA error @hideinitializer*/
+/** @} */
+
+/**
+/**
+ * @brief Threshold value for switching to DMA in read mode.
+ *        If the number of bytes to be read exceeds this threshold,
+ *        DMA is the more efficient data transfer.
+ */
+#define RX_DMA_THRESHOLD 75
+
+/**
+ * @brief Threshold value for switching to DMA in write mode.
+ *        If the number of bytes to be wrote exceeds this threshold,
+ *        DMA is the more efficient data transfer.
+ */
+#define TX_DMA_THRESHOLD 0
+
+/**
+ * @brief Dimension of a flash page, in bytes.
+*/
+#define FLASH_PAGE_SIZE 256
+
+/**
+ * @brief Dimension of a flash sector, in bytes.
+*/
+#define FLASH_SECTOR_SIZE 4096
+
+/**
+ * @brief Number of dummy clocks cycles required by the simulation model.
+*/
+#define DUMMY_CLOCKS_SIM 8
+
+/**
+ * @brief Number of dummy clocks cycles required by the flash during
+ * fast read quad I/O operations (command code: EBh).
+*/
+#define DUMMY_CLOCKS_FAST_READ_QUAD_IO 4
+
+/**
+ * @brief Upper bound for the flash address.
+*/
+#define MAX_FLASH_ADDR 0x00ffffff
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/**                                                                        **/
+/**                       TYPEDEFS AND STRUCTURES                          **/
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Return status type.
+*/
+typedef uint8_t w25q_error_codes_t;
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED VARIABLES                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED FUNCTIONS                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Initialize data structure used by crt0 flash_load.
+ *
+*/
+void w25q128jw_init_crt0();
+
+/**
+ * @brief Power up and itialize the flash.
+ *
+ * Enable the SPI interface.
+ * Power up the flash and set the SPI configuration specific to the flash.
+ * It also set the QE bit in order to accept Quad I/O commands.
+ * By default both error and event interrupts are disabled.
+ *
+ * @param spi_host SPI host to use.
+ *
+ * @note The flash uses CSID 0. If the CSID register value is changed, it must be
+ * restored back to 0 before using the flash again.
+ *
+ * @return FLASH_OK if the flash is correctly initialized, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_init(spi_host_t spi_host);
+
+/**
+ * @brief Read from flash.
+ *
+ * The function automatically uses the best parameters based on
+ * the current state of the system and the length of the data to read.
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer to be filled.
+ * @param length number of bytes to read.
+ * @return FLASH_OK if the read is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_read(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Write to flash.
+ *
+ * The function automatically uses the best parameters based on
+ * the current state of the system and the length of the data to write.
+ * If erase_before_write is set, the function will take care of erasing
+ * the correct sectors before writing. All the bytes not written will be
+ * copied back in their current state before the write operation.
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @param erase_before_write if set to 1, the function will take care of erasing
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_write(uint32_t addr, void* data, uint32_t length, uint8_t erase_before_write);
+
+/**
+ * @brief Read from flash at standard speed.
+ *
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer to be filled.
+ * @param length number of bytes to read.
+ * @retval FLASH_OK if the read is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_read_standard(uint32_t addr, void* data, uint32_t length);
+
+
+/**
+ * @brief Write to flash at standard speed. Use this function only to write to unitialized data
+ *
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_write_standard(uint32_t addr, void* data, uint32_t length);
+
+
+/**
+ * @brief Erase and Write to flash at standard speed.
+ *
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Read from flash at standard speed using DMA
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to read.
+ * @return FLASH_OK if the read is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void* data, uint32_t length);
+
+
+/**
+ * @brief Write to flash at standard speed using DMA. Use this function only to write to unitialized data
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_write_standard_dma(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Erase and Write to flash at standard speed using DMA
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_erase_and_write_standard_dma(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Read from flash at quad speed.
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_read_quad(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Write to flash at quad speed. Use this function only to write to unitialized data
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_write_quad(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Erase and Write to flash at quad speed.
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_erase_and_write_quad(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Read from flash at quad speed using DMA.
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Write to flash at quad speed using DMA. Use this function only to write to unitialized data
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_write_quad_dma(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Erase and Write to flash at quad speed using DMA. Use this function only to write to unitialized data
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to write.
+ * @return FLASH_OK if the write is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_erase_and_write_quad_dma(uint32_t addr, void* data, uint32_t length);
+
+/**
+ * @brief Erase a 4kb sector.
+ *
+ * Sets all memory within a 4kb sector to the erased state of all 1s (FFh).
+ * After the erase is issued, waits for the flash to be ready.
+ *
+ * @param addr 24-bit address of the sector to erase.
+*/
+w25q_error_codes_t w25q128jw_4k_erase(uint32_t addr);
+
+/**
+ * @brief Erase a 32kb block.
+ *
+ * Sets all memory within a 32kb block to the erased state of all 1s (FFh).
+ * After the erase is issued, waits for the flash to be ready.
+ *
+ * @param addr 24-bit address of the block to erase.
+*/
+w25q_error_codes_t w25q128jw_32k_erase(uint32_t addr);
+
+/**
+ * @brief Erase a 64kb block.
+ *
+ * Sets all memory within a 64kb block to the erased state of all 1s (FFh).
+ * After the erase is issued, waits for the flash to be ready.
+ *
+ * @param addr 24-bit address of the block to erase.
+*/
+w25q_error_codes_t w25q128jw_64k_erase(uint32_t addr);
+
+/**
+ * @brief Erase the entire chip.
+ *
+ * Sets all memory within the chip to the erased state of all 1s (FFh).
+ * After the erase is issued, waits for the flash to be ready.
+*/
+void w25q128jw_chip_erase(void);
+
+
+/**
+ * @brief Reset the flash.
+ *
+ * Before issuing the reset command, the function checks (and eventually wait)
+ * any ongoing read/write operation in order to preserve data integrity.
+ * After the reset is issued, wait for the flash to be ready.
+*/
+void w25q128jw_reset(void);
+
+/**
+ * @brief Reset the flash without checking for ongoing operations.
+ *
+ * This function is used to reset the flash when it is not possible to check
+ * for ongoing operations (e.g. when the flash is not responding).
+ * Upon receiving the reset command, the flash will abort any ongoing operation.
+ * After the reset is issued, waits for the flash to be ready.
+*/
+void w25q128jw_reset_force(void);
+
+/**
+ * @brief Power down the flash.
+ *
+ * During power down state, the only command that can be issued is the
+ * release power down command. All other commands are going to be ignored
+ * by the flash.
+*/
+void w25q128jw_power_down(void);
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          INLINE FUNCTIONS                              **/
+/**                                                                        **/
+/****************************************************************************/
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif /* W25Q128JW_H */
+/****************************************************************************/
+/**                                                                        **/
+/**                                EOF                                     **/
+/**                                                                        **/
+/****************************************************************************/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S
index b5f843ab..82776471 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S
@@ -14,11 +14,7 @@
 #include "core_v_mini_mcu.h"
 #include "soc_ctrl_regs.h"
 
-/* In case the operation is to load from FLASH
-*/
-#ifdef FLASH_LOAD
-#include "spi_host_regs.h"
-#endif
+#define RAMSIZE_COPIEDBY_BOOTROM 2048
 
 /* Entry point for bare metal programs */
 .section .text.start
@@ -46,139 +42,69 @@ _start:
 #endif
 
 #ifdef FLASH_LOAD
-/* copy the remaining (if any) text and data sections */
+
+    call w25q128jw_init_crt0
+
+    // This assumes ram base address is 0x00000000 and the section .text stars from ram0 (in the first RAMSIZE_COPIEDBY_BOOTROM Byte)
+    li     s1, RAMSIZE_COPIEDBY_BOOTROM
+    li     s2, FLASH_MEM_START_ADDRESS
+
+    // copy the remaining (if any) text and data sections //
     // Setup the in/out pointers and copy size knowing 1KiB as already been copied
-    li     a2, FLASH_MEM_START_ADDRESS # src ptr (flash)
-    addi   a2, a2, 1024
-    // This assumes ram base address is 0x00000000
-    li     s1, 1024 # dst ptr (ram)
-    la     a0, _edata
-    addi   a0, a0, -4 # _edata point to next address, so decrease it by one word
-    // Skip if everything has already been copied
-    blt    a0, s1, _init_bss
-    addi   a3, a0, -1024 # copy size in bytes (_edata is word aligned, so -1020 to make sure last word is copied)
-
-    li     a1, SPI_FLASH_START_ADDRESS
-    // Spi should already be enabled, powered-up and TXWM to 8
-    // Address in byte reversed order (might be useless for the 1KiB address value)
-    // Highest byte is discarded(address on 3 bytes)
-    // ((x << 24) | (((x>>16)<<24)>>16) |  (((x<<16)>>24)<<16))
-    slli   a4, a2, 24
-    srli   s0, a2, 16
-    slli   s0, s0, 24
-    srli   s0, s0, 16
-    slli   a5, a2, 16
-    srli   a5, a5, 24
-    slli   a5, a5, 16
-    or     a4, a4, s0
-    or     a2, a4, a5
-    or     a2, a2, 0x03
-    sw     a2, SPI_HOST_TXDATA_REG_OFFSET(a1)
-    nop    # otherwise ready bit check is too fast
-
-_wait_spi_ready_read_prog:
-    lw     a5, SPI_HOST_STATUS_REG_OFFSET(a1)
-    bgez   a5, _wait_spi_ready_read_prog
-    // Read command: 0x11000003
-    lui    a4, 0x11000
-    addi   a4, a4, 3 # spi cmd: txonly + stdspeed + csaat + 4B
-    sw     a4, SPI_HOST_COMMAND_REG_OFFSET(a1)
-    nop    # otherwise ready bit check is too fast
-
-_wait_spi_ready_copy_cmd:
-    lw     a4, SPI_HOST_STATUS_REG_OFFSET(a1)
-    bgez   a4, _wait_spi_ready_copy_cmd
-
-    // For loop until the copy from flash to ram is done
-    // Try first to do as much as 256-bytes copies as possible
-    // mv     s0, a3
-    li     s6, 256
-    // Read command: 0x90000FF
-   lui    s5, 0x9000
-    addi   s5, s5, 255 # spi cmd: rxonly + stdspeed + csaat + 255 bytes
-
-_32B_chunk_loop:
-    blt    s6, a3, _read_32B_chunk
-    // Read remaining bytes
-    lui    a5, 0x8000
-    addi   a4, a3, -1
-    or     a5, a5, a4 # spi cmd: rxonly + stdspeed + remaining bytes (a3-1)
-    sw     a5, SPI_HOST_COMMAND_REG_OFFSET(a1)
-    nop    # otherwise ready bit check is too fast
-
-_wait_spi_ready_remaining_bytes:
-    lw     a5, SPI_HOST_STATUS_REG_OFFSET(a1)
-    bgez   a5, _wait_spi_ready_remaining_bytes
-    li     s4, 32
-    j      _last_bytes_read_start
-
-_read_32B_chunk:
-    sw     s5, SPI_HOST_COMMAND_REG_OFFSET(a1)
-    nop    # otherwise ready bit check is too fast
-
-_wait_spi_ready_read_32B_chunk:
-    lw     a5, SPI_HOST_STATUS_REG_OFFSET(a1)
-    bgez   a5, _wait_spi_ready_read_32B_chunk
-    addi   s7, s1, 256 # add 32*8 (256 bytes) to dst ptr
-
-_wait_spi_rxwm_8_words:
-    lw     a5, SPI_HOST_STATUS_REG_OFFSET(a1)
-    srli   a5, a5, 0x14
-    andi   a5, a5, 1 # SPI_HOST_STATUS_RXWM_BIT
-    beqz   a5, _wait_spi_rxwm_8_words
-    addi   a2, s1, 32 # add 32 bytes (4 words) to dst ptr
-
-_spi_fifo_read_8_words:
-    // Read 32B (8 words) from RX FIFO
-    lw     a7, SPI_HOST_RXDATA_REG_OFFSET(a1)
-    sw     a7, 0(s1)
-    addi   s1, s1, 4
-    bne    s1, a2, _spi_fifo_read_8_words
-    bne    s1, s7, _wait_spi_rxwm_8_words
-    addi   a3, a3, -256
-    j      _32B_chunk_loop
-
-_wait_spi_rxwm_8_words_1:
-    lw     a5, SPI_HOST_STATUS_REG_OFFSET(a1)
-    srli   a5, a5, 0x14
-    andi   a5, a5, 1 # SPI_HOST_STATUS_RXWM_BIT
-    beqz   a5, _wait_spi_rxwm_8_words_1
-    addi   a2, s1, 32 # add 32 bytes (4 words) to dst ptr
-
-_spi_fifo_read_8_words_1:
-    // Read 32B (8 words) from RX FIFO
-    lw     a7, SPI_HOST_RXDATA_REG_OFFSET(a1)
-    sw     a7, 0(s1)
-    addi   s1, s1, 4
-    bne    s1, a2, _spi_fifo_read_8_words_1
-    addi   a3, a3, -32
-
-_last_bytes_read_start:
-    bltu   s4, a3, _wait_spi_rxwm_8_words_1
-    // Update RX watermark with remaining words (<=8)
-    lw     a4, SPI_HOST_CONTROL_REG_OFFSET(a1)
-    andi   a4, a4, -256 # ~SPI_HOST_CONTROL_RX_WATERMARK_MASK
-    srli   a5, a3, 0x2 # 4 bytes = 1 word
-    or     a5, a5, a4
-    sw     a5, SPI_HOST_CONTROL_REG_OFFSET(a1)
-
-_wait_spi_rxwm_n_words:
-    lw     a5, SPI_HOST_STATUS_REG_OFFSET(a1)
-    srli   a5, a5, 0x14
-    andi   a5, a5, 1 # SPI_HOST_STATUS_RXWM_BIT
-    beqz   a5, _wait_spi_rxwm_n_words
-
-_remaining_bytes_loop:
-    bnez   a3, _spi_read_word
-    j      _init_bss
-
-_spi_read_word:
-    lw     a7, SPI_HOST_RXDATA_REG_OFFSET(a1)
-    sw     a7, 0(s1)
-    addi   a3, a3, -4
-    addi   s1, s1, 4
-    j      _remaining_bytes_loop
-	
+    mv     a0, s2 // src ptr (flash)
+    add   a0, a0, s1
+
+    la     a1, _etext
+    // Skip if everything has already been copied, and copy the data section
+    blt    a1, s1, _load_data_section
+
+    // copy size in bytes, i.e. _etext - RAMSIZE_COPIEDBY_BOOTROM
+    sub   a2, a1, s1
+
+    // dst ptr (ram)
+    mv     a1, s1
+
+    // copy the remaining data --> w25q128jw_read_standard(a0 is src addr, a1 is dest ptr data, a2 is length)
+
+    // this sub is redundat as we could have simply set a0 to RAMSIZE_COPIEDBY_BOOTROM+0x0,
+    // but like this is more readable as we set the FLASH address as memory mapped to FLASH_MEM_START_ADDRESS, and then remove the offset
+    // as required bz the w25q128jw_read_standard function
+    sub    a0,a0,s2
+    call w25q128jw_read_standard
+
+_load_data_section:
+    // src ptr
+    la     a0, _lma_data_start
+    // dst ptr
+    la     a1, __data_start
+    // copy size in bytes
+    la     a2, _lma_data_end
+    sub    a2, a2, a0
+
+    bltz   a2, _load_data_interleaved_section // dont do anything if you do not have data
+
+    sub    a0,a0,s2
+    call w25q128jw_read_standard
+
+
+_load_data_interleaved_section:
+    #ifdef HAS_MEMORY_BANKS_IL
+    // src ptr
+    la     a0, _lma_data_interleaved_start
+    // dst ptr
+    la     a1, __data_interleaved_start
+    // copy size in bytes
+    la     a2, _lma_data_interleaved_end
+    sub    a2, a2, a0
+
+    bltz   a2, _init_bss // dont do anything if you do not have interleaved data
+
+    sub    a0,a0,s2
+    call w25q128jw_read_standard
+    #endif
+
+#endif
+
 /* clear the bss segment */
 _init_bss:
     la     a0, __bss_start
@@ -186,14 +112,6 @@ _init_bss:
     sub    a2, a2, a0
     li     a1, 0
     call   memset
-#else
-/* clear the bss segment */
-   la a0, __bss_start
-   la a2, __bss_end
-   sub a2, a2, a0
-   li a1, 0
-   call memset
-#endif
 
 #ifdef FLASH_EXEC
 /* copy initialized data sections from flash to ram (to be verified, copied from picosoc)*/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
index c30b6105..d0b977d2 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
@@ -562,7 +562,7 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
          * No further operations are done to prevent corrupting information
          * that could be useful for debugging purposes.
          */
-        uint8_t isEnv = p_trans->dst->env;
+        uint8_t isEnv = (p_trans->dst->env != NULL);
         uint8_t isOutb = is_region_outbound(
                                     p_trans->dst->ptr,
                                     p_trans->dst->env->end,
@@ -689,35 +689,21 @@ dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans )
     /*
      * SET THE POINTERS
      */
-    dma_cb.peri->SRC_PTR = dma_cb.trans->src->ptr;
+    dma_cb.peri->SRC_PTR = (uint32_t)dma_cb.trans->src->ptr;
 
     if(dma_cb.trans->mode != DMA_TRANS_MODE_ADDRESS)
     {
         /*
-            Write to the destination pointers only if we are not in address mode,
-            otherwise the destination address is read in a separate port in parallel with the data
-            from the address port
+        Write to the destination pointers only if we are not in address mode,
+        otherwise the destination address is read in a separate port in parallel with the data
+        from the address port
         */
-        dma_cb.peri->DST_PTR = dma_cb.trans->dst->ptr;
-     }
-     else
-     {
-        dma_cb.peri->ADDR_PTR = dma_cb.trans->src_addr->ptr;
-     }
-
-    if(dma_cb.trans->mode != DMA_TRANS_MODE_ADDRESS)
+        dma_cb.peri->DST_PTR = (uint32_t)dma_cb.trans->dst->ptr;
+    }
+    else
     {
-        /*
-            Write to the destination pointers only if we are not in address mode,
-            otherwise the destination address is read in a separate port in parallel with the data
-            from the address port
-        */
-        dma_cb.peri->DST_PTR = dma_cb.trans->dst->ptr;
-     }
-     else
-     {
-        dma_cb.peri->ADDR_PTR = dma_cb.trans->src_addr->ptr;
-     }
+        dma_cb.peri->ADDR_PTR = (uint32_t)dma_cb.trans->src_addr->ptr;
+    }
 
     /*
      * SET THE INCREMENTS
@@ -1107,7 +1093,7 @@ static inline uint8_t is_region_outbound(   uint8_t  *p_start,
    */
     uint32_t affectedUnits      = ( p_size_du - 1 ) * p_inc_du + 1;
     uint32_t rangeSize          = DMA_DATA_TYPE_2_SIZE(p_type) * affectedUnits;
-    uint32_t lasByteInsideRange = p_start + rangeSize -1;
+    uint32_t lasByteInsideRange = (uint32_t)p_start + rangeSize -1;
     return ( p_end < lasByteInsideRange );
     // Size is be guaranteed to be non-zero before calling this function.
 }
@@ -1166,4 +1152,4 @@ static inline uint32_t get_increment_b( dma_target_t * p_tgt )
 /**                                                                        **/
 /*                                 EOF                                      */
 /**                                                                        **/
-/****************************************************************************/
\ No newline at end of file
+/****************************************************************************/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
index 1956f9e8..85ee6475 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
@@ -104,6 +104,8 @@ typedef enum
     DMA_TRIG_SLOT_SPI_FLASH_RX  = 4, /*!< Slot 3 (MEM < SPI FLASH). */
     DMA_TRIG_SLOT_SPI_FLASH_TX  = 8, /*!< Slot 4 (MEM > SPI FLASH). */
     DMA_TRIG_SLOT_I2S           = 16,/*!< Slot 5 (I2S). */
+    DMA_TRIG_SLOT_EXT_TX        = 32,/*!< Slot 6 (External peripherals TX). */
+    DMA_TRIG_SLOT_EXT_RX        = 64,/*!< Slot 7 (External peripherals RX). */
     DMA_TRIG__size,      /*!< Not used, only for sanity checks. */
     DMA_TRIG__undef,     /*!< DMA will not be used. */
 } dma_trigger_slot_mask_t;
@@ -463,4 +465,4 @@ uint8_t dma_window_ratio_warning_threshold(void);
 /**                                                                        **/
 /**                                EOF                                     **/
 /**                                                                        **/
-/****************************************************************************/
\ No newline at end of file
+/****************************************************************************/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c
index 3e733ecd..f5cb004f 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c
@@ -150,7 +150,7 @@ gpio_result_t gpio_assign_irq_handler( uint32_t intr_id,
 {
   if( intr_id >= GPIO_INTR_START && intr_id <= GPIO_INTR_END )
   {
-    gpio_handlers[ intr_id - GPIO_INTR_START ] = handler;
+    gpio_handlers[ intr_id - GPIO_INTR_START ] = (void (*)(void))handler;
     return GpioOk;
   }
   return GpioError;
@@ -160,7 +160,7 @@ void gpio_reset_handlers_list( )
 {
     for( uint8_t i = 0; i < GPIO_INTR_QTY; i++ )
     {
-        gpio_handlers[ i ] = &gpio_handler_irq_dummy;
+        gpio_handlers[ i ] = (void (*)(void))&gpio_handler_irq_dummy;
     }
 }
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo.h
new file mode 100644
index 00000000..03ec588a
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo.h
@@ -0,0 +1,56 @@
+/*
+                              *******************
+******************************* C SOURCE FILE *******************************
+**                            *******************                          **
+**                                                                         **
+** project  : x-heep                                                       **
+** filename : i2s.h                                                        **
+** date     : 28/10/2023                                                   **
+**                                                                         **
+*****************************************************************************
+**                                                                         **
+** Copyright (c) EPFL contributors.                                        **
+** All rights reserved.                                                    **
+**                                                                         **
+*****************************************************************************
+
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+
+/**
+* @file   iffifo.h
+* @date   28/10/2023
+* @author Pierre Guillod
+* @brief  HAL of the IFFIFO peripheral
+*
+*/
+
+#ifndef _DRIVERS_IFFIFO_H_
+#define _DRIVERS_IFFIFO_H_
+
+/****************************************************************************/
+/**                                                                        **/
+/*                             MODULES USED                                 */
+/**                                                                        **/
+/****************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((weak)) void handler_irq_iffifo(uint32_t id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _DRIVERS_IFFIFO_H_
+
+/****************************************************************************/
+/**                                                                        **/
+/*                                 EOF                                      */
+/**                                                                        **/
+/****************************************************************************/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo_regs.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo_regs.h
new file mode 100644
index 00000000..6acd3aa8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/iffifo/iffifo_regs.h
@@ -0,0 +1,47 @@
+// Generated register defines for iffifo
+
+// Copyright information found in source file:
+// Copyright EPFL contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _IFFIFO_REG_DEFS_
+#define _IFFIFO_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Register width
+#define IFFIFO_PARAM_REG_WIDTH 32
+
+// Data coming from the FIFO (Fifo Output/Software RX)
+#define IFFIFO_FIFO_OUT_REG_OFFSET 0x0
+
+// Data sent to the FIFO (Fifo Input/Software TX)
+#define IFFIFO_FIFO_IN_REG_OFFSET 0x4
+
+// General purpose status register
+#define IFFIFO_STATUS_REG_OFFSET 0x8
+#define IFFIFO_STATUS_EMPTY_BIT 0
+#define IFFIFO_STATUS_AVAILABLE_BIT 1
+#define IFFIFO_STATUS_REACHED_BIT 2
+#define IFFIFO_STATUS_FULL_BIT 3
+
+// Current number of occupied FIFO slots
+#define IFFIFO_OCCUPANCY_REG_OFFSET 0xc
+
+// FIFO occupancy at which the STATUS:REACHED bit is asserted
+#define IFFIFO_WATERMARK_REG_OFFSET 0x10
+
+// Write any value to assert an interrupt. Write 0 or 1 to disable or enable
+// an interrupt.
+#define IFFIFO_INTERRUPTS_REG_OFFSET 0x14
+#define IFFIFO_INTERRUPTS_REACHED_BIT 0
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // _IFFIFO_REG_DEFS_
+// End generated register defines for iffifo
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c
index 7b6ba5f4..ffbb822d 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c
@@ -371,7 +371,7 @@ plic_result_t plic_assign_external_irq_handler( uint32_t id,
 {
   if( id >= EXT_IRQ_START && id <= QTY_INTR )
   {
-    handlers[ id ] = (handler_funct_t*) handler;
+    handlers[ id ] = (handler_funct_t) handler;
     return kPlicOk;
   }
   return kPlicBadArg;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h
index b5db646d..af81fe21 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h
@@ -302,6 +302,15 @@ static inline __attribute__((always_inline)) void spi_wait_for_tx_not_empty(cons
     while (mmio_region_get_bit32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET, SPI_HOST_STATUS_TXEMPTY_BIT));
 }
 
+/**
+ * Wait TX FIFO not full.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ */
+static inline __attribute__((always_inline)) void spi_wait_for_tx_not_full(const spi_host_t *spi) {
+    while (mmio_region_get_bit32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET, SPI_HOST_STATUS_TXFULL_BIT));
+}
+
 /**
  * Wait RX FIFO reach watermark.
  *
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.c
new file mode 100644
index 00000000..326fd963
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.c
@@ -0,0 +1,37 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include "core_v_mini_mcu.h"
+#include <stdint.h>
+
+//heep functions prototypes
+uint32_t * heep_get_flash_address_offset(uint32_t* data_address_lma);
+void heep_init_lfsr();
+uint32_t heep_rand_lfsr();
+
+// this translates the logical address of the FLASH relative to 0 instead of FLASH_MEM_START_ADDRESS, as used by the BSP
+uint32_t * heep_get_flash_address_offset(uint32_t* data_address_lma){
+
+#ifdef ON_CHIP
+    // no need to translate as FLASH is not memory mapped
+    return data_address_lma;
+#else
+    uint32_t* data_address_adjusted = (uint32_t*) ((uint32_t)(data_address_lma) - FLASH_MEM_START_ADDRESS);
+    return data_address_adjusted;
+#endif
+
+}
+
+//get random values
+uint32_t lfsr;
+
+void heep_init_lfsr() {
+    lfsr = (uint32_t)0xAABBCCDD;
+}
+
+uint32_t heep_rand_lfsr() {
+    uint32_t bit = (lfsr ^ (lfsr >> 10) ^ (lfsr >> 11) ^ (lfsr >> 12)) & 1;
+    lfsr = (lfsr >> 1) | (bit << 31);
+    return lfsr;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
index 1491a6ed..2bfec7d9 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
@@ -10,6 +10,9 @@ extern "C" {
 #endif  // __cplusplus
 
 #define MEMORY_BANKS ${ram_numbanks}
+% if ram_numbanks_il > 0:
+#define HAS_MEMORY_BANKS_IL
+% endif
 
 #define EXTERNAL_DOMAINS ${external_domains}
 
@@ -67,6 +70,7 @@ extern "C" {
 
 #define GPIO_AO_DOMAIN_LIMIT 8
 
+
 #ifdef __cplusplus
 }  // extern "C"
 #endif  // __cplusplus
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c
index 8ee1a0d8..c9cd02d3 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c
@@ -3,9 +3,9 @@
 // SPDX-License-Identifier: Apache-2.0
 
 #include "handler.h"
-
 #include "csr.h"
 #include "stdasm.h"
+#include <stdio.h>'
 
 /**
  * Return value of mtval
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c
index 05dd28f9..a9a7fcc2 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c
@@ -18,33 +18,41 @@
  */
 
 #include <sys/stat.h>
+#include <string.h>
 #include <newlib.h>
 #include <unistd.h>
+#include <reent.h>
 #include <errno.h>
 #include "uart.h"
 #include "soc_ctrl.h"
 #include "core_v_mini_mcu.h"
 #include "error.h"
 #include "x-heep.h"
+#include <stdio.h>
 
 #undef errno
 extern int errno;
 
 #define STDOUT_FILENO 1
 
-/* It turns out that older newlib versions use different symbol names which goes
- * against newlib recommendations. Anyway this is fixed in later version.
- */
-#if __NEWLIB__ <= 2 && __NEWLIB_MINOR__ <= 5
-#    define _sbrk sbrk
-#    define _write write
-#    define _close close
-#    define _lseek lseek
-#    define _read read
-#    define _fstat fstat
-#    define _isatty isatty
+#ifndef _LIBC
+/* Provide prototypes for most of the _<systemcall> names that are
+   provided in newlib for some compilers.  */
+int     _close (int __fildes);
+pid_t   _fork (void);
+pid_t   _getpid (void);
+int     _isatty (int __fildes);
+int     _link (const char *__path1, const char *__path2);
+_off_t  _lseek (int __fildes, _off_t __offset, int __whence);
+ssize_t _read (int __fd, void *__buf, size_t __nbyte);
+void *  _sbrk (ptrdiff_t __incr);
+int     _unlink (const char *__path);
+ssize_t _write (int __fd, const void *__buf, size_t __nbyte);
+int     _execve (const char *__path, char * const __argv[], char * const __envp[]);
+int     _kill (pid_t pid, int sig);
 #endif
 
+
 void unimplemented_syscall()
 {
     const char *p = "Unimplemented system call called!\n";
@@ -108,7 +116,7 @@ int _faccessat(int dirfd, const char *file, int mode, int flags)
     return -1;
 }
 
-int _fork(void)
+pid_t _fork(void)
 {
     errno = EAGAIN;
     return -1;
@@ -140,7 +148,7 @@ char *_getcwd(char *buf, size_t size)
     return NULL;
 }
 
-int _getpid()
+pid_t _getpid()
 {
     return 1;
 }
@@ -156,7 +164,7 @@ int _isatty(int file)
     return (file == STDOUT_FILENO);
 }
 
-int _kill(int pid, int sig)
+int _kill(pid_t pid, int sig)
 {
     errno = EINVAL;
     return -1;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h b/hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h
new file mode 100644
index 00000000..c1ef5c5c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h
@@ -0,0 +1,30 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef X_HEEP
+#define X_HEEP
+
+#pragma message ( "the x-heep.h for NEXYS-A7-100T is used" )
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+
+#define REFERENCE_CLOCK_Hz 15*1000*1000
+#define UART_BAUDRATE 9600
+#define TARGET_NEXYS_A7_100T 1
+
+/**
+ * As the hw is configurable, we can have setups with different number of
+ * Gpio pins
+ */
+#define MAX_PIN     32
+
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif  // __cplusplus
+
+#endif  // X_HEEP
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/target/systemc/x-heep.h b/hw/vendor/esl_epfl_x_heep/sw/device/target/systemc/x-heep.h
new file mode 100644
index 00000000..1c1390cb
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/target/systemc/x-heep.h
@@ -0,0 +1,30 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef X_HEEP
+#define X_HEEP
+
+#pragma message ( "the x-heep.h for SIMULATION in SYSTEMC is used" )
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+
+#define REFERENCE_CLOCK_Hz 100*1000*1000
+#define UART_BAUDRATE 256000
+#define TARGET_SYSTEMC 1
+
+/**
+ * As the hw is configurable, we can have setups with different number of
+ * Gpio pins
+ */
+#define MAX_PIN     32
+
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif  // __cplusplus
+
+#endif  // X_HEEP
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h b/hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h
new file mode 100644
index 00000000..af1b4cd5
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h
@@ -0,0 +1,28 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef X_HEEP
+#define X_HEEP
+
+#pragma message ( "the x-heep.h for ZCU104 is used" )
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+#define REFERENCE_CLOCK_Hz 15*1000*1000
+#define UART_BAUDRATE 9600
+#define TARGET_ZCU104 1
+
+/**
+ * As the hw is configurable, we can have setups with different number of
+ * Gpio pins
+ */
+#define MAX_PIN 32
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif  // __cplusplus
+
+#endif  // X_HEEP
diff --git a/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl b/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
index 98f491ce..7403248d 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
@@ -24,7 +24,7 @@ MEMORY
   ram1 (rwxai) : ORIGIN = 0x${linker_onchip_data_start_address}, LENGTH = 0x${linker_onchip_data_size_address}
 % if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
   ram_il (rwxai) : ORIGIN = 0x${linker_onchip_il_start_address}, LENGTH = 0x${linker_onchip_il_size_address}
-% endif  
+% endif
 }
 
 /*
@@ -38,51 +38,13 @@ SECTIONS
   PROVIDE(__boot_address = 0x180);
 
   /* stack and heap related settings */
-  __stack_size = DEFINED(__stack_size) ? __stack_size : 0x800;
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 0x${stack_size};
   PROVIDE(__stack_size = __stack_size);
-  __heap_size = DEFINED(__heap_size) ? __heap_size : 0x800;
+  __heap_size = DEFINED(__heap_size) ? __heap_size : 0x${heap_size};
 
   /* Read-only sections, merged into text segment: */
   PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x10000)); . = SEGMENT_START("text-segment", 0x10000) + SIZEOF_HEADERS;
 
-  /* We don't do any dynamic linking so we remove everything related to it */
-/*
-  .interp         : { *(.interp) }
-  .note.gnu.build-id : { *(.note.gnu.build-id) }
-  .hash           : { *(.hash) }
-  .gnu.hash       : { *(.gnu.hash) }
-  .dynsym         : { *(.dynsym) }
-  .dynstr         : { *(.dynstr) }
-  .gnu.version    : { *(.gnu.version) }
-  .gnu.version_d  : { *(.gnu.version_d) }
-  .gnu.version_r  : { *(.gnu.version_r) }
-  .rela.dyn       :
-    {
-      *(.rela.init)
-      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
-      *(.rela.fini)
-      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
-      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
-      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
-      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
-      *(.rela.ctors)
-      *(.rela.dtors)
-      *(.rela.got)
-      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
-      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
-      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
-      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
-      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
-      PROVIDE_HIDDEN (__rela_iplt_start = .);
-      *(.rela.iplt)
-      PROVIDE_HIDDEN (__rela_iplt_end = .);
-    }
-  .rela.plt       :
-    {
-      *(.rela.plt)
-    }
-*/
-
   /* interrupt vectors */
   .vectors (ORIGIN(ram0)):
   {
@@ -97,11 +59,6 @@ SECTIONS
     KEEP (*(.text.start))
   } >ram0
 
-  /* More dynamic linking sections */
-/*
-  .plt            : { *(.plt) }
-  .iplt           : { *(.iplt) }
-*/
 
   /* the bulk of the program: main, libc, functions etc. */
   .text           :
@@ -268,6 +225,8 @@ SECTIONS
     *(.data1)
   } >ram1
 
+  _lma_vma_data_offset = 0x0;
+
   /* no dynamic linking, no object tables required */
   /* .got            : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) } */
 
@@ -335,12 +294,14 @@ SECTIONS
    PROVIDE(__freertos_irq_stack_top = .);
   } >ram1
 
-.data_interleaved :
+% if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
+  .data_interleaved :
   {
     . = ALIGN(4);
     *(.xheep_data_interleaved)
     . = ALIGN(4);
   } >ram_il
+% endif
 
   /* Stabs debugging sections.  */
   .stab          0 : { *(.stab) }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl
index f8e0f83f..8bd9e64e 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl
@@ -17,9 +17,9 @@ SECTIONS {
     PROVIDE(__boot_address = 0x40000180);
 
     /* stack and heap related settings */
-    __stack_size = DEFINED(__stack_size) ? __stack_size : 0x1000;
+    __stack_size = DEFINED(__stack_size) ? __stack_size : 0x${stack_size};
     PROVIDE(__stack_size = __stack_size);
-    __heap_size = DEFINED(__heap_size) ? __heap_size : 0x1000;
+    __heap_size = DEFINED(__heap_size) ? __heap_size : 0x${heap_size};
 
     /* interrupt vectors */
     .vectors (ORIGIN(FLASH)):
@@ -70,6 +70,8 @@ SECTIONS {
         _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
     } >RAM AT >FLASH
 
+    _lma_vma_data_offset = 0x0;
+
     .power_manager : ALIGN(4096)
     {
        PROVIDE(__power_manager_start = .);
diff --git a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl
index a33ca3dd..541b2233 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl
@@ -7,47 +7,70 @@ ENTRY(_start)
 
 MEMORY
 {
-    FLASH (rx)      : ORIGIN = 0x${flash_mem_start_address}, LENGTH = 0x${flash_mem_size_address}
-    RAM (xrw)       : ORIGIN = 0x${'{:08X}'.format(int(ram_start_address,16))}, LENGTH = 0x${'{:08X}'.format(int(ram_size_address,16) - 4)}
+    ram0 (rwxai) : ORIGIN = 0x${linker_onchip_code_start_address}, LENGTH = 0x${linker_onchip_code_size_address}
+    ram1 (rwxai) : ORIGIN = 0x${linker_onchip_data_start_address}, LENGTH = 0x${linker_onchip_data_size_address}
+    FLASH0 (rx)   : ORIGIN = 0x${linker_flash_code_start_address}, LENGTH = 0x${linker_onchip_code_size_address}
+    FLASH1 (rx)   : ORIGIN = 0x${linker_flash_data_start_address}, LENGTH = 0x${linker_onchip_data_size_address}
+  % if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
+    ram_il (rwxai) : ORIGIN = 0x${linker_onchip_il_start_address}, LENGTH = 0x${linker_onchip_il_size_address}
+    FLASH_il (rx)   : ORIGIN = 0x${linker_flash_il_start_address}, LENGTH = 0x${linker_onchip_il_size_address}
+  % endif
+    FLASH_left (rx)   : ORIGIN = 0x${linker_flash_left_start_address}, LENGTH = 0x${linker_flash_left_size_address}
 }
 
+
+
 SECTIONS {
 
     /* we want a fixed entry point */
     PROVIDE(__boot_address = 0x180);
 
     /* stack and heap related settings */
-    __stack_size = DEFINED(__stack_size) ? __stack_size : 0x1000;
+    __stack_size = DEFINED(__stack_size) ? __stack_size : 0x${stack_size};
     PROVIDE(__stack_size = __stack_size);
-    __heap_size = DEFINED(__heap_size) ? __heap_size : 0x1000;
+    __heap_size = DEFINED(__heap_size) ? __heap_size : 0x${heap_size};
 
     /* interrupt vectors */
-    .vectors (ORIGIN(RAM)):
+    .vectors (ORIGIN(ram0)):
     {
         PROVIDE(__vector_start = .);
+        _lma_text_start = LOADADDR(.vectors);
         KEEP(*(.vectors));
         __VECTORS_AT = .;
-    } >RAM AT >FLASH
+    } >ram0 AT >FLASH0
 
     /* Fill memory up to __boot_address */
     .fill :
     {
         FILL(0xDEADBEEF);
-        . = ORIGIN(RAM) + (__boot_address) - 1;
+        . = ORIGIN(ram0) + (__boot_address) - 1;
         BYTE(0xEE)
-    } >RAM AT >FLASH
+    } >ram0 AT >FLASH0
 
     /* crt0 init code */
     .init (__boot_address):
     {
         KEEP (*(SORT_NONE(.init)))
         KEEP (*(.text.start))
-    } >RAM AT >FLASH
+        KEEP (*(.text.w25q128jw_init_crt0))
+        KEEP (*(.text.w25q128jw_sanity_checks))
+        KEEP (*(.text.spi_write_word*))
+        KEEP (*(.text.spi_wait_for_ready*))
+        KEEP (*(.text.spi_create_command*))
+        KEEP (*(.text.spi_set_command*))
+        KEEP (*(.text.spi_set_rx_watermark*))
+        KEEP (*(.text.spi_wait_for_rx_watermark*))
+        KEEP (*(.text.spi_read_word*))
+        KEEP (*(.text.memcpy))
+        KEEP (*(.text.w25q128jw_read_standard)) /* as this function is used in the crt0, link it in the top, should be before 1024 Bytes loaded by the bootrom */
+        *(.xheep_init_data_crt0) /* this global variables are used in the crt0 */
+    } >ram0 AT >FLASH0
 
     /* The program code and other data goes into FLASH */
     .text : ALIGN_WITH_INPUT
     {
         . = ALIGN(4);
+        __text_start = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
         *(.text)           /* .text sections (code) */
         *(.text*)          /* .text* sections (code) */
         *(.rodata)         /* .rodata sections (constants, strings, etc.) */
@@ -56,16 +79,17 @@ SECTIONS {
         *(.srodata*)       /* .rodata* sections (constants, strings, etc.) */
         . = ALIGN(4);
         _etext = .;        /* define a global symbol at end of code */
-    } >RAM AT >FLASH
+    } >ram0 AT >FLASH0
 
     /* This is the initialized data section
     The program executes knowing that the data is in the RAM
     but the loader puts the initial values in the FLASH (inidata).
     It is one task of the startup to copy the initial values from FLASH to RAM. */
-    .data : ALIGN_WITH_INPUT
+    .data : ALIGN(256)
     {
-        . = ALIGN(4);
+        __data_start = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
         _sidata = LOADADDR(.data);
+        _lma_data_start = LOADADDR(.data);
         _sdata = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
         _ram_start = .;    /* create a global symbol at ram start for garbage collector */
         . = ALIGN(4);
@@ -75,18 +99,20 @@ SECTIONS {
         __SDATA_BEGIN__ = .;
         *(.sdata)           /* .sdata sections */
         *(.sdata*)          /* .sdata* sections */
-        . = ALIGN(4);
-        _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
-    } >RAM AT >FLASH
+    } >ram1 AT >FLASH1
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
 
-    .power_manager : ALIGN(4096)
+    .power_manager : ALIGN_WITH_INPUT
     {
+        . = ALIGN(4);
        PROVIDE(__power_manager_start = .);
        . += 256;
-    } >RAM
+    } >ram1 AT >FLASH1
 
     /* Uninitialized data section */
-    .bss :
+    .bss : ALIGN_WITH_INPUT
     {
         . = ALIGN(4);
         __bss_start = .;         /* define a global symbol at bss start; used by startup code */
@@ -99,7 +125,14 @@ SECTIONS {
         . = ALIGN(4);
         __bss_end = .;         /* define a global symbol at bss end; used by startup code */
         __BSS_END__ = .;
-    } >RAM
+    } >ram1 AT >FLASH1
+
+    _lma_data_end = _lma_data_start + SIZEOF(.data) + SIZEOF(.power_manager) + SIZEOF(.bss);
+    _lma_vma_data_offset = _lma_data_start - __data_start;
+
+    _lma_text_end = _lma_text_start + SIZEOF(.vectors) + SIZEOF(.init) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.power_manager) + SIZEOF(.bss);
+    _lma_text_vma_offset = _lma_text_start - __vector_start;
+
 
     /* The compiler uses this to access data in the .sdata, .data, .sbss and .bss
      sections with fewer instructions (relaxation). This reduces code size. */
@@ -112,7 +145,7 @@ SECTIONS {
         PROVIDE(__heap_start = .);
         . = __heap_size;
         PROVIDE(__heap_end = .);
-    } >RAM
+    } >ram1
 
     /* stack: we should consider putting this further to the top of the address
     space */
@@ -123,5 +156,29 @@ SECTIONS {
        PROVIDE(_sp = .);
        PROVIDE(__stack_end = .);
        PROVIDE(__freertos_irq_stack_top = .);
-    } >RAM
+    } >ram1
+
+  % if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
+    .data_interleaved : ALIGN_WITH_INPUT
+    {
+        PROVIDE(__data_interleaved_start = .);
+        _lma_data_interleaved_start = LOADADDR(.data_interleaved);
+        . = ALIGN(4);
+        *(.xheep_data_interleaved)
+        . = ALIGN(4);
+    } >ram_il AT >FLASH_il
+
+   . = ALIGN(4);
+  _eddata_interleaved = .;
+  _lma_data_interleaved_end = _lma_data_interleaved_start + SIZEOF(.data_interleaved);
+
+  % endif
+
+    .data_flash_only : ALIGN(256)
+    {
+        . = ALIGN(4);
+        *(.xheep_data_flash_only)
+        . = ALIGN(4);
+    } >FLASH_left
+
 }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/vendor/patches/yosyshq_icestorm/0001-Add-flash-prgraner-iceprog-custom-for-heep-with-gpio.patch b/hw/vendor/esl_epfl_x_heep/sw/vendor/patches/yosyshq_icestorm/0001-Add-flash-prgraner-iceprog-custom-for-heep-with-gpio.patch
index b325b7bc..1af9cacb 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/vendor/patches/yosyshq_icestorm/0001-Add-flash-prgraner-iceprog-custom-for-heep-with-gpio.patch
+++ b/hw/vendor/esl_epfl_x_heep/sw/vendor/patches/yosyshq_icestorm/0001-Add-flash-prgraner-iceprog-custom-for-heep-with-gpio.patch
@@ -1,8 +1,43 @@
 diff --git a/iceprog/iceprog.c b/iceprog/iceprog.c
-index 8ee6443..38e308f 100644
+index 8ee6443..0413697 100644
 --- a/iceprog/iceprog.c
 +++ b/iceprog/iceprog.c
-@@ -506,6 +506,7 @@ static void help(const char *progname)
+@@ -480,6 +480,34 @@ static void flash_enable_quad()
+ 	fprintf(stderr, "SR2: %08x\n", data[1]);
+ }
+ 
++static void flash_disable_quad()
++{
++	fprintf(stderr, "Disabling Quad operation...\n");
++
++	// Allow write
++	flash_write_enable();
++
++	// Write Status Register 2 <- 0x00
++	uint8_t data[2] = { FC_WSR2, 0x00 };
++	flash_chip_select();
++	mpsse_xfer_spi(data, 2);
++	flash_chip_deselect();
++
++	flash_wait();
++
++	// Read Status Register 1
++	data[0] = FC_RSR2;
++
++	flash_chip_select();
++	mpsse_xfer_spi(data, 2);
++	flash_chip_deselect();
++
++	if ((data[1] & 0x02) != 0x00)
++		fprintf(stderr, "failed to set QE=0, SR2 now equal to 0x%02x (expected 0x%02x)\n", data[1], data[1] | 0x00);
++
++	fprintf(stderr, "SR2: %08x\n", data[1]);
++}
++
+ // ---------------------------------------------------------
+ // iceprog implementation
+ // ---------------------------------------------------------
+@@ -506,11 +534,13 @@ static void help(const char *progname)
  	fprintf(stderr, "  -s                    slow SPI (50 kHz instead of 6 MHz)\n");
  	fprintf(stderr, "  -k                    keep flash in powered up state (i.e. skip power down command)\n");
  	fprintf(stderr, "  -v                    verbose output\n");
@@ -10,25 +45,61 @@ index 8ee6443..38e308f 100644
  	fprintf(stderr, "  -i [4,32,64]          select erase block size [default: 64k]\n");
  	fprintf(stderr, "\n");
  	fprintf(stderr, "Mode of operation:\n");
-@@ -587,6 +588,8 @@ int main(int argc, char **argv)
+ 	fprintf(stderr, "  [default]             write file contents to flash, then verify\n");
+ 	fprintf(stderr, "  -X                    write file contents to flash only\n");	
++	fprintf(stderr, "  -a <size in bytes>    provides file size of the file to program\n");
+ 	fprintf(stderr, "  -r                    read first 256 kB from flash and write to file\n");
+ 	fprintf(stderr, "  -R <size in bytes>    read the specified number of bytes from flash\n");
+ 	fprintf(stderr, "                          (append 'k' to the argument for size in kilobytes,\n");
+@@ -578,6 +608,7 @@ int main(int argc, char **argv)
+ 	bool bulk_erase = false;
+ 	bool dont_erase = false;
+ 	bool prog_sram = false;
++	bool filesize_mode = false;
+ 	int  test_mode = 0;
+ 	bool slow_clock = false;
+ 	bool disable_protect = false;
+@@ -587,6 +618,9 @@ int main(int argc, char **argv)
  	const char *devstr = NULL;
  	int ifnum = 0;
  
 +	bool stop_spi = false;
++	long file_size = -1;
 +
  #ifdef _WIN32
  	_setmode(_fileno(stdin), _O_BINARY);
  	_setmode(_fileno(stdout), _O_BINARY);
-@@ -600,7 +603,7 @@ int main(int argc, char **argv)
+@@ -600,7 +634,7 @@ int main(int argc, char **argv)
  	/* Decode command line parameters */
  	int opt;
  	char *endptr;
 -	while ((opt = getopt_long(argc, argv, "d:i:I:rR:e:o:cbnStQvspXk", long_options, NULL)) != -1) {
-+	while ((opt = getopt_long(argc, argv, "d:i:I:rR:e:o:cbnStQvTspXk", long_options, NULL)) != -1) {
++	while ((opt = getopt_long(argc, argv, "d:i:I:rR:e:o:a:cbnStQvTspXk", long_options, NULL)) != -1) {
  		switch (opt) {
  		case 'd': /* device string */
  			devstr = optarg;
-@@ -696,6 +699,9 @@ int main(int argc, char **argv)
+@@ -648,6 +682,20 @@ int main(int argc, char **argv)
+ 				return EXIT_FAILURE;
+ 			}
+ 			break;
++		case 'a': /* filesize used to program flash */
++			filesize_mode = true;
++			file_size = strtol(optarg, &endptr, 0);
++			if (*endptr == '\0')
++				/* ok */;
++			else if (!strcmp(endptr, "k"))
++				file_size *= 1024;
++			else if (!strcmp(endptr, "M"))
++				file_size *= 1024 * 1024;
++			else {
++				fprintf(stderr, "%s: `%s' is not a valid size\n", my_name, optarg);
++				return EXIT_FAILURE;
++			}
++			break;
+ 		case 'e': /* Erase blocks as if we were writing n bytes */
+ 			erase_mode = true;
+ 			erase_size = strtol(optarg, &endptr, 0);
+@@ -696,6 +744,9 @@ int main(int argc, char **argv)
  		case 'v': /* provide verbose output */
  			verbose = true;
  			break;
@@ -38,7 +109,46 @@ index 8ee6443..38e308f 100644
  		case 's': /* use slow SPI clock */
  			slow_clock = true;
  			break;
-@@ -997,22 +1003,59 @@ int main(int argc, char **argv)
+@@ -778,7 +829,7 @@ int main(int argc, char **argv)
+ 	   so we can fail before initializing the hardware */
+ 
+ 	FILE *f = NULL;
+-	long file_size = -1;
++
+ 
+ 	if (test_mode) {
+ 		/* nop */;
+@@ -809,7 +860,7 @@ int main(int argc, char **argv)
+ 		   named pipe, or contrarily, the standard input may be an
+ 		   ordinary file. */
+ 
+-		if (!prog_sram && !check_mode) {
++		if (!prog_sram && !check_mode && !filesize_mode) {
+ 			if (fseek(f, 0L, SEEK_END) != -1) {
+ 				file_size = ftell(f);
+ 				if (file_size == -1) {
+@@ -943,6 +994,8 @@ int main(int argc, char **argv)
+ 		flash_reset();
+ 		flash_power_up();
+ 
++		flash_disable_quad();
++
+ 		flash_read_id();
+ 
+ 
+@@ -968,7 +1021,10 @@ int main(int argc, char **argv)
+ 				}
+ 				else
+ 				{
+-					fprintf(stderr, "file size: %ld\n", file_size);
++					if(filesize_mode)
++						fprintf(stderr, "provided file size: %ld\n", file_size);
++					else
++						fprintf(stderr, "file size: %ld\n", file_size);
+ 
+ 					int block_size = erase_block_size << 10;
+ 					int block_mask = block_size - 1;
+@@ -997,22 +1053,59 @@ int main(int argc, char **argv)
  				}
  			}
  
@@ -62,7 +172,7 @@ index 8ee6443..38e308f 100644
 +				size_t len = 0;
 +				uint8_t buffer[256];
 +				int count = 0;
-+				while (true) {					
++				while (true) {
 +					rc = getline(&line_buffer, &len, f);
 +					if (rc <= 0){
 +						if(count > 0){
@@ -107,20 +217,22 @@ index 8ee6443..38e308f 100644
  				fprintf(stderr, "                      \r");
  				fprintf(stderr, "done.\n");
  
-@@ -1026,6 +1069,12 @@ int main(int argc, char **argv)
+@@ -1026,7 +1119,13 @@ int main(int argc, char **argv)
  		// ---------------------------------------------------------
  
  		if (read_mode) {
+-			fprintf(stderr, "reading..\n");
 +			if(stop_spi){
 +				/* Just to debug reading of values with the logic analyzer*/
 +				printf("Stoped before writting. Press ENTER to continue\n");
 +				getchar();
 +			}
 +
- 			fprintf(stderr, "reading..\n");
++			fprintf(stderr, "reading..");
  			for (int addr = 0; addr < read_size; addr += 256) {
  				uint8_t buffer[256];
-@@ -1037,23 +1086,40 @@ int main(int argc, char **argv)
+ 				fprintf(stderr, "                      \r");
+@@ -1037,23 +1136,40 @@ int main(int argc, char **argv)
  			fprintf(stderr, "                      \r");
  			fprintf(stderr, "done.\n");
  		} else if (!erase_mode && !disable_verify) {
@@ -134,7 +246,7 @@ index 8ee6443..38e308f 100644
 +			int rc, addr = 0;
 +			size_t len = 0;
 +			uint8_t buffer_flash[256], buffer_file[256];
-+			while (true) {					
++			while (true) {
 +				rc = getline(&line_buffer, &len, f);
  				if (rc <= 0)
  					break;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/vendor/yosyshq_icestorm/iceprog/iceprog.c b/hw/vendor/esl_epfl_x_heep/sw/vendor/yosyshq_icestorm/iceprog/iceprog.c
index 38e308f8..0413697d 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/vendor/yosyshq_icestorm/iceprog/iceprog.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/vendor/yosyshq_icestorm/iceprog/iceprog.c
@@ -480,6 +480,34 @@ static void flash_enable_quad()
 	fprintf(stderr, "SR2: %08x\n", data[1]);
 }
 
+static void flash_disable_quad()
+{
+	fprintf(stderr, "Disabling Quad operation...\n");
+
+	// Allow write
+	flash_write_enable();
+
+	// Write Status Register 2 <- 0x00
+	uint8_t data[2] = { FC_WSR2, 0x00 };
+	flash_chip_select();
+	mpsse_xfer_spi(data, 2);
+	flash_chip_deselect();
+
+	flash_wait();
+
+	// Read Status Register 1
+	data[0] = FC_RSR2;
+
+	flash_chip_select();
+	mpsse_xfer_spi(data, 2);
+	flash_chip_deselect();
+
+	if ((data[1] & 0x02) != 0x00)
+		fprintf(stderr, "failed to set QE=0, SR2 now equal to 0x%02x (expected 0x%02x)\n", data[1], data[1] | 0x00);
+
+	fprintf(stderr, "SR2: %08x\n", data[1]);
+}
+
 // ---------------------------------------------------------
 // iceprog implementation
 // ---------------------------------------------------------
@@ -512,6 +540,7 @@ static void help(const char *progname)
 	fprintf(stderr, "Mode of operation:\n");
 	fprintf(stderr, "  [default]             write file contents to flash, then verify\n");
 	fprintf(stderr, "  -X                    write file contents to flash only\n");	
+	fprintf(stderr, "  -a <size in bytes>    provides file size of the file to program\n");
 	fprintf(stderr, "  -r                    read first 256 kB from flash and write to file\n");
 	fprintf(stderr, "  -R <size in bytes>    read the specified number of bytes from flash\n");
 	fprintf(stderr, "                          (append 'k' to the argument for size in kilobytes,\n");
@@ -579,6 +608,7 @@ int main(int argc, char **argv)
 	bool bulk_erase = false;
 	bool dont_erase = false;
 	bool prog_sram = false;
+	bool filesize_mode = false;
 	int  test_mode = 0;
 	bool slow_clock = false;
 	bool disable_protect = false;
@@ -589,6 +619,7 @@ int main(int argc, char **argv)
 	int ifnum = 0;
 
 	bool stop_spi = false;
+	long file_size = -1;
 
 #ifdef _WIN32
 	_setmode(_fileno(stdin), _O_BINARY);
@@ -603,7 +634,7 @@ int main(int argc, char **argv)
 	/* Decode command line parameters */
 	int opt;
 	char *endptr;
-	while ((opt = getopt_long(argc, argv, "d:i:I:rR:e:o:cbnStQvTspXk", long_options, NULL)) != -1) {
+	while ((opt = getopt_long(argc, argv, "d:i:I:rR:e:o:a:cbnStQvTspXk", long_options, NULL)) != -1) {
 		switch (opt) {
 		case 'd': /* device string */
 			devstr = optarg;
@@ -651,6 +682,20 @@ int main(int argc, char **argv)
 				return EXIT_FAILURE;
 			}
 			break;
+		case 'a': /* filesize used to program flash */
+			filesize_mode = true;
+			file_size = strtol(optarg, &endptr, 0);
+			if (*endptr == '\0')
+				/* ok */;
+			else if (!strcmp(endptr, "k"))
+				file_size *= 1024;
+			else if (!strcmp(endptr, "M"))
+				file_size *= 1024 * 1024;
+			else {
+				fprintf(stderr, "%s: `%s' is not a valid size\n", my_name, optarg);
+				return EXIT_FAILURE;
+			}
+			break;
 		case 'e': /* Erase blocks as if we were writing n bytes */
 			erase_mode = true;
 			erase_size = strtol(optarg, &endptr, 0);
@@ -784,7 +829,7 @@ int main(int argc, char **argv)
 	   so we can fail before initializing the hardware */
 
 	FILE *f = NULL;
-	long file_size = -1;
+
 
 	if (test_mode) {
 		/* nop */;
@@ -815,7 +860,7 @@ int main(int argc, char **argv)
 		   named pipe, or contrarily, the standard input may be an
 		   ordinary file. */
 
-		if (!prog_sram && !check_mode) {
+		if (!prog_sram && !check_mode && !filesize_mode) {
 			if (fseek(f, 0L, SEEK_END) != -1) {
 				file_size = ftell(f);
 				if (file_size == -1) {
@@ -949,6 +994,8 @@ int main(int argc, char **argv)
 		flash_reset();
 		flash_power_up();
 
+		flash_disable_quad();
+
 		flash_read_id();
 
 
@@ -974,7 +1021,10 @@ int main(int argc, char **argv)
 				}
 				else
 				{
-					fprintf(stderr, "file size: %ld\n", file_size);
+					if(filesize_mode)
+						fprintf(stderr, "provided file size: %ld\n", file_size);
+					else
+						fprintf(stderr, "file size: %ld\n", file_size);
 
 					int block_size = erase_block_size << 10;
 					int block_mask = block_size - 1;
@@ -1018,7 +1068,7 @@ int main(int argc, char **argv)
 				size_t len = 0;
 				uint8_t buffer[256];
 				int count = 0;
-				while (true) {					
+				while (true) {
 					rc = getline(&line_buffer, &len, f);
 					if (rc <= 0){
 						if(count > 0){
@@ -1075,7 +1125,7 @@ int main(int argc, char **argv)
 				getchar();
 			}
 
-			fprintf(stderr, "reading..\n");
+			fprintf(stderr, "reading..");
 			for (int addr = 0; addr < read_size; addr += 256) {
 				uint8_t buffer[256];
 				fprintf(stderr, "                      \r");
@@ -1093,7 +1143,7 @@ int main(int argc, char **argv)
 			int rc, addr = 0;
 			size_t len = 0;
 			uint8_t buffer_flash[256], buffer_file[256];
-			while (true) {					
+			while (true) {
 				rc = getline(&line_buffer, &len, f);
 				if (rc <= 0)
 					break;
diff --git a/hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.cpp b/hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.cpp
new file mode 100644
index 00000000..947d31ef
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.cpp
@@ -0,0 +1,100 @@
+#include "XHEEP_CmdLineOptions.hh"
+#include <iostream>
+#include <string>
+
+XHEEP_CmdLineOptions::XHEEP_CmdLineOptions(int argc, char* argv[]) // define default constructor
+{
+    this->argc = argc;
+    this->argv = argv;
+}
+
+std::string XHEEP_CmdLineOptions::getCmdOption(int argc, char* argv[], const std::string& option)
+{
+    std::string cmd;
+     for( int i = 0; i < argc; ++i)
+     {
+          std::string arg = argv[i];
+          size_t arg_size = arg.length();
+          size_t option_size = option.length();
+
+          if(arg.find(option)==0){
+            cmd = arg.substr(option_size,arg_size-option_size);
+          }
+     }
+     return cmd;
+}
+
+bool XHEEP_CmdLineOptions::get_use_openocd()
+{
+
+  std::string arg_openocd = this->getCmdOption(this->argc, this->argv, "+openOCD=");;
+
+  bool use_openocd = false;
+
+  if(arg_openocd.empty()){
+    std::cout<<"[TESTBENCH]: No OpenOCD is used"<<std::endl;
+  } else {
+    std::cout<<"[TESTBENCH]: OpenOCD is used"<<std::endl;
+    use_openocd = true;
+  }
+
+  return use_openocd;
+}
+
+
+std::string XHEEP_CmdLineOptions::get_firmware()
+{
+
+  std::string firmware = this->getCmdOption(this->argc, this->argv, "+firmware=");
+
+  if(firmware.empty()){
+    std::cout<<"[TESTBENCH]: No firmware  specified"<<std::endl;
+  } else {
+    std::cout<<"[TESTBENCH]: loading firmware  "<<firmware<<std::endl;
+  }
+
+  return firmware;
+}
+
+
+unsigned int XHEEP_CmdLineOptions::get_max_sim_time(bool& run_all)
+{
+
+  std::string arg_max_sim_time = this->getCmdOption(this->argc, this->argv, "+max_sim_time=");
+  unsigned int max_sim_time;
+
+  max_sim_time     = 0;
+  if(arg_max_sim_time.empty()){
+    std::cout<<"[TESTBENCH]: No Max time specified"<<std::endl;
+    run_all = true;
+  } else {
+    max_sim_time = stoi(arg_max_sim_time);
+    std::cout<<"[TESTBENCH]: Max Times is  "<<max_sim_time<<std::endl;
+  }
+
+  return max_sim_time;
+}
+
+unsigned int XHEEP_CmdLineOptions::get_boot_sel()
+{
+  std::string arg_boot_sel = this->getCmdOption(this->argc, this->argv, "+boot_sel=");
+  unsigned int boot_sel     = 0;
+
+  if(arg_boot_sel.empty()){
+    std::cout<<"[TESTBENCH]: No Boot Option specified, using jtag (boot_sel=0)"<<std::endl;
+    boot_sel = 0;
+  } else {
+    if(arg_boot_sel.compare("1") == 0) {
+      boot_sel = 1;
+      std::cout<<"[TESTBENCH]: Booting from flash"<<std::endl;
+    } else if(arg_boot_sel.compare("0") == 0) {
+      boot_sel = 0;
+      std::cout<<"[TESTBENCH]: Booting from jtag"<<std::endl;
+    } else {
+      std::cout<<"[TESTBENCH]: Wrong Boot Option specified (jtag, flash) - using jtag (boot_sel=0)"<<std::endl;
+      boot_sel = 0;
+    }
+  }
+
+  return boot_sel;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.hh b/hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.hh
new file mode 100644
index 00000000..fc053afc
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/tb/XHEEP_CmdLineOptions.hh
@@ -0,0 +1,24 @@
+#ifndef XHEEP_TB_UTIL_H
+#define XHEEP_TB_UTIL_H
+
+#include <iostream>
+
+class XHEEP_CmdLineOptions // declare Calculator class
+{
+
+  public: // public members
+    XHEEP_CmdLineOptions(int argc, char* argv[]); // default constructor
+
+    std::string getCmdOption(int argc, char* argv[], const std::string& option); // get options from cmd lines
+    bool get_use_openocd();
+    std::string get_firmware();
+    unsigned int get_max_sim_time(bool& run_all);
+    unsigned int get_boot_sel();
+    int argc;
+    char** argv;
+
+};
+
+
+
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/tb/core-v-mini-mcu-pynq-z2-bscan.cfg b/hw/vendor/esl_epfl_x_heep/tb/core-v-mini-mcu-pynq-z2-bscan.cfg
new file mode 100644
index 00000000..f0134765
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/tb/core-v-mini-mcu-pynq-z2-bscan.cfg
@@ -0,0 +1,44 @@
+adapter driver ftdi 	
+adapter speed 1000
+transport select jtag
+
+
+# FT2232HQ Adapter Pynq Z2
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_channel 0
+ftdi_layout_init 0x0088 0x008b
+
+reset_config none
+
+echo "ftdi setting..."
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x23727093
+jtag newtap arm_dap_0 tap -irlen 4 -expected-id 0x4ba00477
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x000
+
+echo "target created..."
+
+#log_output openocd_fpga.log
+
+riscv set_ir idcode 0x09
+riscv set_ir dtmcs 0x22
+riscv set_ir dmi 0x23
+
+riscv set_reset_timeout_sec 2000
+riscv set_command_timeout_sec 2000
+
+echo "setting preferences..."
+
+scan_chain
+
+init
+
+echo "init routine started"
+
+halt
+
+echo "Ready for Remote Connections"
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/Cache.h b/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/Cache.h
new file mode 100644
index 00000000..d9c94b5d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/Cache.h
@@ -0,0 +1,221 @@
+#ifndef CACHE_H
+#define CACHE_H
+
+#include <fstream>
+#include <iostream>
+#include <sstream>
+#include <iomanip>
+
+
+// Target module representing a simple direct mapped cache
+class CacheMemory
+{
+
+public:
+  uint32_t cache_size_byte    = 4*1024;
+  uint32_t number_of_blocks   = 256;
+
+  uint32_t nbits_blocks       = 0;
+  uint32_t nbits_tags         = 0;
+  uint32_t nbits_index        = 0;
+  uint32_t block_size_byte    = 0;
+
+  enum { ARCHITECTURE_bits = 32 };
+
+  std::ofstream cacheFile;
+
+  typedef struct cache_line {
+    uint32_t tag;
+    bool    valid;
+    uint8_t* data;
+  } cache_line_t;
+
+  cache_line_t* cache_array;
+
+
+  CacheMemory(): cacheFile("cache_status.log")
+  {
+    cache_array = NULL;
+  }
+
+  void create_cache() {
+      cache_array = new cache_line_t[number_of_blocks];
+      this->block_size_byte = get_block_size();
+      this->nbits_blocks    = log2(block_size_byte);
+      this->nbits_index     = log2(number_of_blocks);
+      this->nbits_tags      = ARCHITECTURE_bits - nbits_index - nbits_blocks;
+      printf("bits block %d, index %d, tags %d\n",nbits_blocks, nbits_index, nbits_tags );
+  }
+
+  void create_cache(uint32_t cache_size_byte, uint32_t number_of_blocks) {
+      this->cache_size_byte = cache_size_byte;
+      this->number_of_blocks = number_of_blocks;
+      cache_array = new cache_line_t[number_of_blocks];
+      this->block_size_byte = get_block_size();
+      this->nbits_blocks    = log2(block_size_byte);
+      this->nbits_index     = log2(number_of_blocks);
+      this->nbits_tags      = ARCHITECTURE_bits - nbits_index - nbits_blocks;
+  }
+
+  uint32_t initialize_cache() {
+      if(cache_array == NULL) {
+        return -1;
+      }
+      // Initialize memory with random data
+      for (int i = 0; i < number_of_blocks; i++) {
+        cache_array[i].valid = false;
+        cache_array[i].tag   = 0;
+        cache_array[i].data = new uint8_t[block_size_byte];
+        for(int j = 0; j<block_size_byte;j++) {
+          cache_array[i].data[j] = (uint8_t)(i*j);
+        }
+      }
+      return 0;
+  }
+
+  uint32_t get_block_size() {
+    return (uint32_t)(cache_size_byte / number_of_blocks);
+  }
+
+  uint32_t get_index(uint32_t address) {
+    uint32_t mask_index = (1 << nbits_index) - 1;
+    return (uint32_t)((address >> nbits_blocks) & mask_index );
+  }
+
+  uint32_t get_block_offset(uint32_t address) {
+    uint32_t mask_block = (1 << nbits_blocks) - 1;
+    return (uint32_t)(address & mask_block);
+  }
+
+  uint32_t get_base_address(uint32_t address) {
+    return (uint32_t)((address >> nbits_blocks) << nbits_blocks);
+  }
+
+  uint32_t get_tag(uint32_t address) {
+    return (uint32_t)(address >> (nbits_index+nbits_blocks));
+  }
+
+  uint32_t get_tag_from_index(uint32_t index) {
+    return cache_array[index].tag;
+  }
+
+
+  bool cache_hit(uint32_t address) {
+    uint32_t index = get_index(address);
+    uint32_t tag   = get_tag(address);
+    return ( cache_array[index].valid && tag == cache_array[index].tag);
+
+  }
+
+  void add_entry(uint32_t address, uint8_t* new_data) {
+    uint32_t index = get_index(address);
+    uint32_t tag   = get_tag(address);
+    cache_array[index].valid = true;
+    cache_array[index].tag   = tag;
+    memcpy(cache_array[index].data, new_data, block_size_byte);
+  }
+
+  void get_data(uint32_t address, uint8_t* new_data) {
+    uint32_t index = get_index(address);
+    memcpy(new_data, cache_array[index].data, block_size_byte);
+  }
+
+  void get_data_at_index(uint32_t index, uint8_t* new_data) {
+    memcpy(new_data, cache_array[index].data, block_size_byte);
+  }
+
+  uint32_t get_address(uint32_t address){
+    uint32_t index = get_index(address);
+    uint32_t tag   = cache_array[index].tag;
+    uint32_t new_address = (tag << (nbits_index+nbits_blocks)) | (index<<nbits_blocks); //<<2 as words
+    return new_address;
+  }
+
+  uint32_t get_address_at_index(uint32_t index){
+    uint32_t tag   = cache_array[index].tag;
+    uint32_t new_address = tag << (nbits_index+nbits_blocks) | (index<<nbits_blocks); //<<2 as words
+    return new_address;
+  }
+
+  int32_t get_word(uint32_t address) {
+    int32_t data_word = 0;
+    uint32_t block_offset = this->get_block_offset(address);
+    uint8_t* new_data = new uint8_t[block_size_byte];
+    this->get_data(address, new_data);
+    data_word = *((int32_t *)&new_data[block_offset]);
+    delete new_data;
+    return data_word;
+  }
+
+  void set_word(uint32_t address, int32_t data_word) {
+    uint32_t block_offset = this->get_block_offset(address);
+    uint8_t* new_data = new uint8_t[block_size_byte];
+    this->get_data(address, new_data);
+    *((int32_t *)&new_data[block_offset]) = data_word;
+    for(int i=0;i<block_size_byte;i++)
+    this->add_entry(address, new_data);
+    delete new_data;
+  }
+
+  bool is_entry_valid(uint32_t address) {
+    uint32_t index = get_index(address);
+    return cache_array[index].valid;
+  }
+
+  bool is_entry_valid_at_index(uint32_t index) {
+    return cache_array[index].valid;
+  }
+
+  void print_cache_status(uint32_t operation_id, std::string time_str) {
+    if (cacheFile.is_open()) {
+      std::string log_cache = "";
+      std::ostringstream ss;
+
+      log_cache+= std::to_string(operation_id) + "):  " + time_str + "\n";
+      log_cache+= "INDEX | TAG | DATA BLOCK | VALID\n";
+
+      for(int i=0;i<number_of_blocks;i++) {
+        ss << "0x" << std::setw(this->nbits_index/4) << std::setfill('0') << std::hex << static_cast<uint32_t>(i);
+        log_cache+= ss.str() + " | ";
+        ss.str("");
+        ss.clear();
+        ss << "0x" << std::setw(this->nbits_tags/4) << std::setfill('0') << std::hex << cache_array[i].tag;
+        log_cache+= ss.str() + " | 0x";
+        ss.str("");
+        ss.clear();
+        for(int j = 0; j<block_size_byte; j++)
+          ss << ":" << std::setw(2) << std::setfill('0') << std::hex << static_cast<uint16_t>(cache_array[i].data[j]);
+        log_cache+= ss.str() + " | ";
+        log_cache+= std::string( cache_array[i].valid ? "1" : "0" ) + "\n";
+
+        cacheFile << log_cache;
+        ss.str("");
+        ss.clear();
+        log_cache = std::string("");
+      }
+    } else {
+      std::cout << "Failed to create the Cache file." << std::endl;
+    }
+  }
+
+  /* main memory address
+    0x7052 = 'b111_0000_0101_0010'
+
+    cache size = 4KB,
+    number_of_blocks = 256, thus index is on 8bit
+    block_size_in_byte = 4KB/256 = 16bytes, i.e. 4 words
+
+    111:       tag
+    0000_0101: used as index
+    0010:      used for block offset , 4bits as 16 bytes
+
+
+      get_tag(0x7052) --> 0x7
+      get_index(0x7052) --> 0x5
+      get_block_offset(0x7052) --> 0x2
+
+
+  */
+};
+
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MainMemory.h b/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MainMemory.h
new file mode 100644
index 00000000..984f81cf
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MainMemory.h
@@ -0,0 +1,68 @@
+#ifndef MEMORY_H
+#define MEMORY_H
+
+// Needed for the simple_target_socket
+#define SC_INCLUDE_DYNAMIC_PROCESSES
+
+#include "systemc"
+using namespace sc_core;
+using namespace sc_dt;
+using namespace std;
+
+#include "tlm.h"
+#include "tlm_utils/simple_target_socket.h"
+
+
+// Target module representing a simple direct mapped cache
+SC_MODULE(MainMemory)
+{
+  // TLM-2 socket, defaults to 32-bits wide, base protocol
+  tlm_utils::simple_target_socket<MainMemory> socket;
+
+  enum { SIZE = 32*1024/4 }; //32KB word addressable
+
+  int32_t mem[SIZE];
+
+
+  SC_CTOR(MainMemory)
+  : socket("socket")
+  {
+    // Register callback for incoming b_transport interface method call
+    socket.register_b_transport(this, &MainMemory::b_transport);
+
+    // Initialize memory with random data
+    for (int i = 0; i < SIZE; i++)
+      mem[i] = 0xAA000000 | (rand() % 256);
+  }
+
+  // TLM-2 blocking transport method
+  virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay )
+  {
+    tlm::tlm_command cmd = trans.get_command();
+    sc_dt::uint64    adr = trans.get_address() / 4;
+    unsigned char*   ptr = trans.get_data_ptr();
+    unsigned int     len = trans.get_data_length();
+    unsigned char*   byt = trans.get_byte_enable_ptr();
+    unsigned int     wid = trans.get_streaming_width();
+
+    // Obliged to check address range and check for unsupported features,
+    //   i.e. byte enables, streaming, and bursts
+    // Can ignore DMI hint and extensions
+    // Using the SystemC report handler is an acceptable way of signalling an error
+
+    if (adr >= sc_dt::uint64(SIZE) || byt != 0 || len > 4 || wid < len)
+      SC_REPORT_ERROR("TLM-2", "Target does not support given generic payload transaction");
+
+    // Obliged to implement read and write commands
+    if ( cmd == tlm::TLM_READ_COMMAND )
+      memcpy(ptr, &mem[adr], len);
+    else if ( cmd == tlm::TLM_WRITE_COMMAND )
+      memcpy(&mem[adr], ptr, len);
+
+    // Obliged to set response status to indicate successful completion
+    trans.set_response_status( tlm::TLM_OK_RESPONSE );
+  }
+
+};
+
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MemoryRequest.h b/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MemoryRequest.h
new file mode 100644
index 00000000..c0a7d1c7
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/tb/systemc_tb/MemoryRequest.h
@@ -0,0 +1,241 @@
+#ifndef MEMORYREQUEST_H
+#define MEMORYREQUEST_H
+
+#include "systemc"
+using namespace sc_core;
+using namespace sc_dt;
+using namespace std;
+
+#include "tlm.h"
+#include "tlm_utils/simple_initiator_socket.h"
+
+#include "Cache.h"
+
+#include <fstream>
+#include <iostream>
+#include <sstream>
+#include <iomanip>
+
+// MemoryRequest module generating generic payload transactions
+
+SC_MODULE(MemoryRequest)
+{
+  // TLM-2 socket, defaults to 32-bits wide, base protocol
+  tlm_utils::simple_initiator_socket<MemoryRequest> socket;
+  bool                                          we_i;
+  uint32_t                                      be_i;
+  uint32_t                                      addr_i;
+  uint32_t                                      rwdata_io;
+  CacheMemory*                                  cache;
+  std::ofstream                                 heep_mem_transactions;
+  bool                                          bypass_state = false;
+
+  typedef struct cache_statistics
+  {
+    uint32_t number_of_transactions;
+    uint32_t number_of_hit;
+    uint32_t number_of_miss;
+  } cache_statistics_t;
+
+  cache_statistics_t cache_stat;
+
+  SC_CTOR(MemoryRequest)
+  : socket("socket"),  // Construct and name socket
+    heep_mem_transactions("heep_mem_transactions.log")
+  {
+
+    cache = new CacheMemory;
+    cache->create_cache();
+    cache->initialize_cache();
+    cache_stat.number_of_transactions = 0;
+    cache_stat.number_of_hit = 0;
+    cache_stat.number_of_miss = 0;
+    cache->print_cache_status(cache_stat.number_of_transactions++, sc_time_stamp().to_string());
+
+    SC_THREAD(thread_process);
+  }
+
+
+  uint32_t memory_copy(uint32_t addr, int32_t* buffer_data, int N, bool write_enable, tlm::tlm_generic_payload* trans, sc_time delay) {
+
+    tlm::tlm_command cmd = write_enable ? tlm::TLM_WRITE_COMMAND : tlm::TLM_READ_COMMAND;
+
+    //first read block_size bytes from memory to place them in cache regardless of the cmd
+    for(int i=0; i < N; i++){
+      trans->set_command( cmd );
+      trans->set_address( (addr + i*4) & 0x00007FFF ); //15bits
+      trans->set_data_ptr( reinterpret_cast<unsigned char*>(&buffer_data[i]) );
+      trans->set_data_length( 4 );
+      trans->set_streaming_width( 4 ); // = data_length to indicate no streaming
+      trans->set_byte_enable_ptr( 0 ); // 0 indicates unused
+      trans->set_dmi_allowed( false ); // Mandatory initial value
+      trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE ); // Mandatory initial value
+      socket->b_transport( *trans, delay );  // Blocking transport call
+
+      if(bypass_state){
+        if(write_enable)
+          heep_mem_transactions << "Writing to Mem[" << hex << ((addr + i*4) & 0x00007FFF) << "]: " << buffer_data[i] << " at time " << sc_time_stamp() <<std::endl;
+        else
+          heep_mem_transactions << "Reading from Mem[" << hex << ((addr + i*4) & 0x00007FFF) << "]: " << buffer_data[i] << " at time " << sc_time_stamp() <<std::endl;
+      } else {
+        if(write_enable)
+          heep_mem_transactions << "Cache Writing to Mem[" << hex << ((addr + i*4) & 0x00007FFF) << "]: " << buffer_data[i] << " at time " << sc_time_stamp() <<std::endl;
+        else
+          heep_mem_transactions << "Cache Reading from Mem[" << hex << ((addr + i*4) & 0x00007FFF) << "]: " << buffer_data[i] << " at time " << sc_time_stamp() <<std::endl;
+      }
+      // Initiator obliged to check response status and delay
+      if ( trans->is_response_error() )
+        SC_REPORT_ERROR("TLM-2", "Response error from b_transport");
+    }
+    return N;
+  }
+
+
+  void thread_process()
+  {
+    // TLM-2 generic payload transaction, reused across calls to b_transport
+    tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
+
+    sc_time delay_gnt_miss = sc_time(100, SC_NS);
+    sc_time delay_rvalid_miss = sc_time(100, SC_NS);
+
+    sc_time delay_rvalid_hit = sc_time(20, SC_NS); //as of today, it must be >=20
+
+    sc_time delay = sc_time(1, SC_NS);
+
+    uint32_t cache_block_size_byte = cache->get_block_size();
+    uint32_t cache_block_size_word = cache->get_block_size()/4;
+    uint8_t* cache_data = new uint8_t[cache_block_size_byte];
+    int32_t* main_mem_data = new int32_t[cache_block_size_word];
+    uint32_t address_to_replace;
+    uint32_t cache_flushed;
+
+    while(true) {
+
+      wait(obi_new_req);
+
+      heep_mem_transactions << "X-HEEP tlm_generic_payload REQ: { " << (we_i ? 'W' : 'R') << ", @0x" << hex << addr_i
+                << " , DATA = 0x" << hex << rwdata_io << " BE = " << hex << be_i <<", at time " << sc_time_stamp() << " }" << std::endl;
+
+      if(be_i!=0xF) {
+        SC_REPORT_ERROR("OBI External Memory SystemC", "ByteEnable different than 0xF is not supported");
+      }
+
+      //if we are writing 1 or 2 to last address, flush cache or bypass
+      if(we_i && ((addr_i & 0x00007FFF) == 0x7FFC)){
+
+        if(rwdata_io == 1){
+          //FLUSH Cache
+          heep_mem_transactions << "X-HEEP Flush Cache, at time " << sc_time_stamp() << " }" << std::endl;
+          uint32_t cache_number_of_blocks = cache->number_of_blocks;
+          heep_mem_transactions<<"Cache Flushing at time "<<sc_time_stamp()<<std::endl;
+          cache_flushed=0;
+          for(int i=0;i<cache_number_of_blocks;i++){
+              if (cache->is_entry_valid_at_index(i)) {
+                cache_flushed++;
+                //if we are going to replace a valid entry
+                cache->get_data_at_index(i, cache_data);
+                address_to_replace = cache->get_address_at_index(i);
+                //write back
+                memory_copy(address_to_replace, (uint32_t *)cache_data, cache_block_size_word, true, trans, delay);
+            }
+          }
+          heep_mem_transactions<<"Cache Flushed "<< dec << cache_flushed << " entries"<<std::endl;
+        } else if (rwdata_io == 2){
+          //ByPass Flash from next transaction
+          bypass_state = true;
+          heep_mem_transactions<<"Cache ByPass set at time "<<sc_time_stamp()<<std::endl;
+          heep_mem_transactions << "X-HEEP Bypass Cache, at time " << sc_time_stamp() << " }" << std::endl;
+        }
+        obi_new_gnt.notify();
+        wait(delay_rvalid_miss);
+      }
+
+      else{
+
+        if (bypass_state) {
+          heep_mem_transactions << "Cache in bypass state at time " << sc_time_stamp() <<std::endl;
+          wait(delay_gnt_miss);
+          obi_new_gnt.notify();
+          memory_copy(addr_i, &rwdata_io, 1, we_i == true, trans, delay);
+          wait(delay_rvalid_miss);
+        } else {
+          // we use the cache only to read
+          if(cache->cache_hit(addr_i)){
+
+            heep_mem_transactions << "Cache HIT on address " << hex << addr_i << " at time " << sc_time_stamp() <<std::endl;
+
+            cache_stat.number_of_hit++;
+
+            obi_new_gnt.notify();
+            main_mem_data[0] = cache->get_word(addr_i);
+            //if Write, writes to cache
+            if(we_i)
+              cache->set_word(addr_i, rwdata_io);
+            else
+              rwdata_io = main_mem_data[0];
+            wait(delay_rvalid_hit);
+          }
+
+          else { //miss case
+
+            cache_stat.number_of_miss++;
+
+            heep_mem_transactions << "Cache MISS on address " << hex << addr_i << " at time " << sc_time_stamp() <<std::endl;
+
+            //wait some time before giving the gnt as we have a miss
+            wait(delay_gnt_miss);
+            obi_new_gnt.notify();
+
+            uint32_t addr_to_read = cache->get_base_address(addr_i);
+            uint32_t addr_offset  = cache->get_block_offset(addr_i);
+
+            //first read block_size bytes from memory to place them in cache regardless of the cmd
+            memory_copy(addr_to_read, main_mem_data, cache_block_size_word, false, trans, delay);
+            uint32_t index_to_add = cache->get_index(addr_i);
+            uint32_t tag_to_add       = cache->get_tag(addr_i);
+
+            heep_mem_transactions << "Adding to Cache TAG " << hex << tag_to_add << " and index " << hex << index_to_add <<std::endl;
+
+            //always write back what will be replace if valid as we do not have dirty bits for simplicity
+            if (cache->is_entry_valid(addr_i)) {
+              //if we are going to replace a valid entry
+              cache->get_data(addr_i, cache_data);
+              address_to_replace = cache->get_address(addr_i);
+              uint32_t index_to_replace = cache->get_index(addr_i);
+              uint32_t tag_to_replace = cache->get_tag_from_index(index_to_replace);
+
+              heep_mem_transactions << "Cache Replace address " << hex << addr_i << " with address " << hex << address_to_replace << " due to the MISS at time " << sc_time_stamp() <<std::endl;
+              heep_mem_transactions << "Index to replace " << hex << index_to_replace << " Tag to replace " << tag_to_replace <<std::endl;
+
+              //write back
+              memory_copy(address_to_replace, (uint32_t *)cache_data, cache_block_size_word, true, trans, delay);
+            }
+
+            //now replace the entry in cache
+            cache->add_entry(addr_i, (uint8_t*)main_mem_data);
+
+            //if Write, writes to cache
+            if(we_i)
+              cache->set_word(addr_i, rwdata_io);
+
+            //now give back the rdata
+            rwdata_io = main_mem_data[addr_offset>>2]; //>>2 as addr_offset is for byte address, not words
+
+            //wait some time before giving the rvalid
+            wait(delay_rvalid_miss);
+
+          }
+        }
+      }
+
+      heep_mem_transactions << "X-HEEP tlm_generic_payload RESP: { DATA = 0x" << hex << rwdata_io <<", at time " << sc_time_stamp() << " }" << std::endl;
+      cache->print_cache_status(cache_stat.number_of_transactions++, sc_time_stamp().to_string());
+
+      obi_new_rvalid.notify();
+
+    }
+  }
+};
+
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/tb/tb_sc_top.cpp b/hw/vendor/esl_epfl_x_heep/tb/tb_sc_top.cpp
new file mode 100644
index 00000000..b619d950
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/tb/tb_sc_top.cpp
@@ -0,0 +1,342 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include "verilated.h"
+#include <verilated_vcd_sc.h>
+#include "Vtestharness.h"
+#include "Vtestharness__Syms.h"
+#include "systemc.h"
+#include <stdlib.h>
+#include <iostream>
+#include "XHEEP_CmdLineOptions.hh"
+
+sc_event reset_done_event;
+sc_event obi_new_gnt;
+sc_event obi_new_rvalid;
+sc_event obi_new_req;
+
+
+#include "systemc_tb/MemoryRequest.h"
+#include "systemc_tb/MainMemory.h"
+
+
+#define CLK_PERIOD 10
+
+SC_MODULE(external_memory)
+{
+  MemoryRequest *memory_request;
+  MainMemory    *memory;
+
+  sc_in<bool>          clk_i;
+  sc_in<bool>          ext_systemc_req_req_i;
+  sc_in<bool>          ext_systemc_req_we_i;
+  sc_in<uint32_t>      ext_systemc_req_be_i;
+  sc_in<uint32_t>      ext_systemc_req_addr_i;
+  sc_in<uint32_t>      ext_systemc_req_wdata_i;
+  sc_out<bool>         ext_systemc_resp_gnt_o;
+  sc_out<bool>         ext_systemc_resp_rvalid_o;
+  sc_out<uint32_t>     ext_systemc_resp_rdata_o;
+
+  void notify_obi_transaction () {
+    if(ext_systemc_req_req_i) {
+      obi_new_req.notify();
+      memory_request->we_i    = ext_systemc_req_we_i;
+      memory_request->be_i    = ext_systemc_req_be_i;
+      memory_request->addr_i  = ext_systemc_req_addr_i;
+      memory_request->rwdata_io = ext_systemc_req_wdata_i;
+    }
+  }
+
+  void give_gnt_back () {
+    while (true) {
+      ext_systemc_resp_gnt_o.write(false);
+      wait(obi_new_gnt);
+      ext_systemc_resp_gnt_o.write(true);
+      wait();
+    }
+  }
+
+  void give_rvalid_rdata_back () {
+    while (true) {
+      ext_systemc_resp_rvalid_o.write(false);
+      wait(obi_new_rvalid);
+      ext_systemc_resp_rvalid_o.write(true);
+      ext_systemc_resp_rdata_o.write(memory_request->rwdata_io);
+      wait();
+    }
+  }
+
+  SC_CTOR(external_memory)
+  {
+    // Instantiate components
+    memory_request = new MemoryRequest("memory_request");
+    memory         = new MainMemory   ("main_memory");
+
+    SC_METHOD(notify_obi_transaction);
+    sensitive << ext_systemc_req_req_i;
+
+    SC_CTHREAD(give_gnt_back, clk_i.pos());
+    SC_CTHREAD(give_rvalid_rdata_back, clk_i.pos());
+
+    // Bind memory_request socket to target socket
+    memory_request->socket.bind( memory->socket );
+  }
+};
+
+
+SC_MODULE(testbench)
+{
+
+  sc_in<bool> clk_i;
+  sc_out<bool> clk_o;
+  sc_out<bool> rst_no;
+  sc_out<bool> boot_select_o;
+  sc_out<bool> execute_from_flash_o;
+  sc_out<bool> jtag_tck_o;
+  sc_out<bool> jtag_tms_o;
+  sc_out<bool> jtag_trst_n_o;
+  sc_out<bool> jtag_tdi_o;
+
+  Vtestharness* dut;
+  std::string* firmware;
+
+  bool boot_select_option;
+  unsigned int reset_cycles = 30;
+
+  void make_clock () {
+    while(1) {
+      clk_o.write(false);
+      wait();
+      clk_o.write(true);
+      wait();
+    }
+  }
+
+  void do_reset_cycle () {
+    //active low
+    //-----
+    rst_no.write(false);
+
+    for(int i=0;i<reset_cycles;i++) wait();
+
+    //-----|||||||
+    rst_no.write(true);
+    for(int i=0;i<reset_cycles;i++) wait();
+
+    //-----|||||||------
+    rst_no.write(false);
+    for(int i=0;i<reset_cycles;i++) wait();
+
+    //-----|||||||------||||||
+    rst_no.write(true);
+    for(int i=0;i<reset_cycles;i++) wait();
+  }
+
+
+  void load_firmware () {
+    wait();
+    dut->tb_loadHEX(firmware->c_str());
+  }
+
+  void set_exit_loop () {
+    wait();
+    dut->tb_set_exit_loop();
+  }
+
+  void make_stimuli () {
+
+    boot_select_o.write(boot_select_option);
+    execute_from_flash_o.write(true);
+    jtag_tck_o.write(false);
+    jtag_tms_o.write(false);
+    jtag_trst_n_o.write(false);
+    jtag_tdi_o.write(false);
+
+    std::cout<<"Start Reset Cycle: "<<sc_time_stamp()<< std::endl;
+    do_reset_cycle();
+    std::cout<<"Reset Released: "<<sc_time_stamp()<< std::endl;
+
+    std::cout<<"Loading firmware "<<firmware->c_str()<<std::endl;
+    load_firmware ();
+
+    std::cout<<"Set Exit Loop"<< std::endl;
+    set_exit_loop ();
+
+    reset_done_event.notify();
+
+    //sc_stop();
+  }
+
+  SC_CTOR(testbench)
+  {
+
+    SC_CTHREAD(make_clock, clk_i.pos());
+    SC_CTHREAD(make_stimuli, clk_i.pos());
+
+  }
+
+
+
+};
+
+int sc_main (int argc, char * argv[])
+{
+
+  std::string firmware;
+  unsigned int max_sim_time, boot_sel, exit_val;
+  bool use_openocd;
+  bool run_all = false;
+  Verilated::commandArgs(argc, argv);
+  Verilated::traceEverOn(true);
+
+  XHEEP_CmdLineOptions* cmd_lines_options = new XHEEP_CmdLineOptions(argc,argv);
+
+  use_openocd = cmd_lines_options->get_use_openocd();
+  firmware = cmd_lines_options->get_firmware();
+
+  if(firmware.empty() && use_openocd==false) {
+    std::cout<<"You must specify the firmware if you are not using OpenOCD"<<std::endl;
+    exit(EXIT_FAILURE);
+  }
+
+  max_sim_time = cmd_lines_options->get_max_sim_time(run_all);
+
+  boot_sel     = cmd_lines_options->get_boot_sel();
+
+  if(use_openocd) {
+    std::cout<<"[TESTBENCH]: ERROR: Executing from OpenOCD in SystemC is not supported (yet) in X-HEEP"<<std::endl;
+    std::cout<<"exit simulation..."<<std::endl;
+    exit(EXIT_FAILURE);
+  }
+
+  if(boot_sel == 1) {
+    std::cout<<"[TESTBENCH]: ERROR: Executing from SPI is not supported (yet) in Verilator"<<std::endl;
+    std::cout<<"exit simulation..."<<std::endl;
+    exit(EXIT_FAILURE);
+  }
+
+  // generate clock, twice the speed as we generate it by dividing it by 2
+  sc_clock clock_sig("clock", CLK_PERIOD>>1, SC_NS, 0.5);
+
+  Vtestharness dut("TOP");
+  testbench tb("testbench");
+  external_memory ext_mem("external_memory");
+
+  svSetScope(svGetScopeFromName("TOP.testharness"));
+  svScope scope = svGetScope();
+  if (!scope) {
+    std::cout<<"Warning: svGetScope failed"<< std::endl;
+    exit(EXIT_FAILURE);
+  }
+
+
+  // static values
+  tb.boot_select_option = boot_sel == 1;
+
+
+  // Vtestharness interface
+  sc_signal<bool, SC_MANY_WRITERS>     clk;
+  sc_signal<bool, SC_MANY_WRITERS>     rst_n;
+  sc_signal<bool, SC_MANY_WRITERS>     boot_select;
+  sc_signal<bool, SC_MANY_WRITERS>     execute_from_flash;
+  sc_signal<bool>     jtag_tck;
+  sc_signal<bool>     jtag_tms;
+  sc_signal<bool>     jtag_trst_n;
+  sc_signal<bool>     jtag_tdi;
+  sc_signal<bool>     jtag_tdo;
+  sc_signal<uint32_t> exit_value;
+  sc_signal<bool, SC_MANY_WRITERS>     exit_valid;
+  sc_signal<bool>      ext_systemc_req_req;
+  sc_signal<bool>      ext_systemc_req_we;
+  sc_signal<uint32_t>  ext_systemc_req_be;
+  sc_signal<uint32_t>  ext_systemc_req_addr;
+  sc_signal<uint32_t>  ext_systemc_req_wdata;
+  sc_signal<bool>      ext_systemc_resp_gnt;
+  sc_signal<bool>      ext_systemc_resp_rvalid;
+  sc_signal<uint32_t>  ext_systemc_resp_rdata;
+
+
+
+  tb.clk_i(clock_sig);
+  tb.clk_o(clk);
+  tb.rst_no(rst_n);
+  tb.boot_select_o(boot_select);
+  tb.execute_from_flash_o(execute_from_flash);
+  tb.jtag_tck_o(jtag_tck);
+  tb.jtag_tms_o(jtag_tms);
+  tb.jtag_trst_n_o(jtag_trst_n);
+  tb.jtag_tdi_o(jtag_tdi);
+
+  tb.dut = &dut;
+  tb.firmware = &firmware;
+
+  dut.clk_i(clk);
+  dut.rst_ni(rst_n);
+  dut.boot_select_i(boot_select);
+  dut.execute_from_flash_i(execute_from_flash);
+  dut.jtag_tck_i(jtag_tck);
+  dut.jtag_tms_i(jtag_tms);
+  dut.jtag_trst_ni(jtag_trst_n);
+  dut.jtag_tdi_i(jtag_tdi);
+  dut.jtag_tdo_o(jtag_tdo);
+  dut.exit_value_o(exit_value);
+  dut.exit_valid_o(exit_valid);
+  dut.ext_systemc_req_req_o(ext_systemc_req_req);
+  dut.ext_systemc_req_we_o(ext_systemc_req_we);
+  dut.ext_systemc_req_be_o(ext_systemc_req_be);
+  dut.ext_systemc_req_addr_o(ext_systemc_req_addr);
+  dut.ext_systemc_req_wdata_o(ext_systemc_req_wdata);
+  dut.ext_systemc_resp_gnt_i(ext_systemc_resp_gnt);
+  dut.ext_systemc_resp_rvalid_i(ext_systemc_resp_rvalid);
+  dut.ext_systemc_resp_rdata_i(ext_systemc_resp_rdata);
+
+  ext_mem.clk_i(clk);
+  ext_mem.ext_systemc_req_req_i(ext_systemc_req_req);
+  ext_mem.ext_systemc_req_we_i(ext_systemc_req_we);
+  ext_mem.ext_systemc_req_be_i(ext_systemc_req_be);
+  ext_mem.ext_systemc_req_addr_i(ext_systemc_req_addr);
+  ext_mem.ext_systemc_req_wdata_i(ext_systemc_req_wdata);
+  ext_mem.ext_systemc_resp_gnt_o(ext_systemc_resp_gnt);
+  ext_mem.ext_systemc_resp_rdata_o(ext_systemc_resp_rdata);
+  ext_mem.ext_systemc_resp_rvalid_o(ext_systemc_resp_rvalid);
+
+
+
+  // You must do one evaluation before enabling waves, in order to allow
+  // SystemC to interconnect everything for testing.
+  sc_start(1, SC_NS);
+
+
+  VerilatedVcdSc* tfp = nullptr;
+  tfp = new VerilatedVcdSc;
+  dut.trace(tfp, 99);  // Trace 99 levels of hierarchy
+  tfp->open("waveform.vcd");
+
+  // Simulate until $finish
+  while (!Verilated::gotFinish() && exit_valid !=1 ) {
+      // Flush the wave files each cycle so we can immediately see the output
+      // Don't do this in "real" programs, do it in an abort() handler instead
+      if (tfp) tfp->flush();
+      // Simulate 1ns
+      sc_start(1, SC_NS);
+  }
+
+  if(exit_valid == 1) {
+    std::cout<<"Program Finished with value "<< exit_value <<std::endl;
+    exit_val = EXIT_SUCCESS;
+  } else exit_val = EXIT_FAILURE;
+
+  // Final model cleanup
+  dut.final();
+
+  // Close trace if opened
+  if (tfp) {
+      tfp->close();
+      tfp = nullptr;
+  }
+
+
+  exit(exit_val);
+
+}
diff --git a/hw/vendor/esl_epfl_x_heep/tb/tb_top.cpp b/hw/vendor/esl_epfl_x_heep/tb/tb_top.cpp
index 956b77d6..7dd4757e 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/tb_top.cpp
+++ b/hw/vendor/esl_epfl_x_heep/tb/tb_top.cpp
@@ -10,26 +10,10 @@
 #include <stdlib.h>
 #include <iostream>
 
+#include "XHEEP_CmdLineOptions.hh"
 
 vluint64_t sim_time = 0;
 
-
-std::string getCmdOption(int argc, char* argv[], const std::string& option)
-{
-    std::string cmd;
-     for( int i = 0; i < argc; ++i)
-     {
-          std::string arg = argv[i];
-          size_t arg_size = arg.length();
-          size_t option_size = option.length();
-
-          if(arg.find(option)==0){
-            cmd = arg.substr(option_size,arg_size-option_size);
-          }
-     }
-     return cmd;
-}
-
 void runCycles(unsigned int ncycles, Vtestharness *dut, VerilatedFstC *m_trace){
   for(unsigned int i = 0; i < ncycles; i++) {
     dut->clk_i ^= 1;
@@ -42,12 +26,11 @@ void runCycles(unsigned int ncycles, Vtestharness *dut, VerilatedFstC *m_trace){
 int main (int argc, char * argv[])
 {
 
-  unsigned int SRAM_SIZE;
-  std::string firmware, arg_max_sim_time, arg_openocd, arg_boot_sel, arg_execute_from_flash;
-  unsigned int max_sim_time;
+  std::string firmware;
+  unsigned int max_sim_time, boot_sel, exit_val;
   bool use_openocd;
   bool run_all = false;
-  int i,j, exit_val, boot_sel, execute_from_flash;
+
   Verilated::commandArgs(argc, argv);
 
   // Instantiate the model
@@ -59,59 +42,24 @@ int main (int argc, char * argv[])
   dut->trace (m_trace, 99);
   m_trace->open ("waveform.vcd");
 
-  arg_openocd = getCmdOption(argc, argv, "+openOCD=");
-  use_openocd = false;
-  if(arg_openocd.empty()){
-    std::cout<<"[TESTBENCH]: No OpenOCD is used"<<std::endl;
-  } else {
-    std::cout<<"[TESTBENCH]: OpenOCD is used"<<std::endl;
-    use_openocd = true;
-  }
+  XHEEP_CmdLineOptions* cmd_lines_options = new XHEEP_CmdLineOptions(argc,argv);
 
-  firmware = getCmdOption(argc, argv, "+firmware=");
-  if(firmware.empty()){
-    std::cout<<"[TESTBENCH]: No firmware  specified"<<std::endl;
-    if(use_openocd==false)
-      exit(EXIT_FAILURE);
-  } else {
-    std::cout<<"[TESTBENCH]: loading firmware  "<<firmware<<std::endl;
-  }
+  use_openocd = cmd_lines_options->get_use_openocd();
+  firmware = cmd_lines_options->get_firmware();
 
-  arg_max_sim_time = getCmdOption(argc, argv, "+max_sim_time=");
-  max_sim_time     = 0;
-  if(arg_max_sim_time.empty()){
-    std::cout<<"[TESTBENCH]: No Max time specified"<<std::endl;
-    run_all = true;
-  } else {
-    max_sim_time = stoi(arg_max_sim_time);
-    std::cout<<"[TESTBENCH]: Max Times is  "<<max_sim_time<<std::endl;
+  if(firmware.empty() && use_openocd==false){
+      std::cout<<"You must specify the firmware if you are not using OpenOCD"<<std::endl;
+      exit(EXIT_FAILURE);
   }
 
-  arg_boot_sel = getCmdOption(argc, argv, "+boot_sel=");
-  boot_sel     = 0;
-  if(arg_boot_sel.empty()){
-    std::cout<<"[TESTBENCH]: No Boot Option specified, using jtag (boot_sel=0)"<<std::endl;
-    boot_sel = 0;
-  } else {
-    if(arg_boot_sel.compare("1") == 0) {
-      boot_sel = 1;
-      std::cout<<"[TESTBENCH]: Booting from flash"<<std::endl;
-    } else if(arg_boot_sel.compare("0") == 0) {
-      boot_sel = 0;
-      std::cout<<"[TESTBENCH]: Booting from jtag"<<std::endl;
-    } else {
-      std::cout<<"[TESTBENCH]: Wrong Boot Option specified (jtag, flash) - using jtag (boot_sel=0)"<<std::endl;
-      boot_sel = 0;
-    }
-  }
+  max_sim_time = cmd_lines_options->get_max_sim_time(run_all);
 
-  arg_boot_sel = getCmdOption(argc, argv, "+execute_from_flash=");
-  execute_from_flash = 1;
+  boot_sel     = cmd_lines_options->get_boot_sel();
 
   if(boot_sel == 1) {
     std::cout<<"[TESTBENCH]: ERROR: Executing from SPI is not supported (yet) in Verilator"<<std::endl;
     std::cout<<"exit simulation..."<<std::endl;
-    return -1;
+    exit(EXIT_FAILURE);
   }
 
   svSetScope(svGetScopeFromName("TOP.testharness"));
@@ -127,7 +75,7 @@ int main (int argc, char * argv[])
   dut->jtag_tms_i           = 0;
   dut->jtag_trst_ni         = 0;
   dut->jtag_tdi_i           = 0;
-  dut->execute_from_flash_i = execute_from_flash;
+  dut->execute_from_flash_i = 1; //this cause boot_sel cannot be 1 anyway
   dut->boot_select_i        = boot_sel;
 
   dut->eval();
@@ -172,6 +120,7 @@ int main (int argc, char * argv[])
 
   m_trace->close();
   delete dut;
+  delete cmd_lines_options;
 
   exit(exit_val);
 
diff --git a/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl b/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl
index ece91031..a0f295a4 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl
+++ b/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl
@@ -96,7 +96,7 @@ endtask
 
 % for bank in range(ram_numbanks):
 task tb_writetoSram${bank};
-  input integer addr;
+  input int addr;
   input [7:0] val3;
   input [7:0] val2;
   input [7:0] val1;
diff --git a/hw/vendor/esl_epfl_x_heep/tb/testharness.sv b/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
index fc216e7b..2a4c7040 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
@@ -21,6 +21,17 @@ module testharness #(
     inout wire boot_select_i,
     inout wire execute_from_flash_i,
 
+`ifdef SIM_SYSTEMC
+    output logic        ext_systemc_req_req_o,
+    output logic        ext_systemc_req_we_o,
+    output logic [ 3:0] ext_systemc_req_be_o,
+    output logic [31:0] ext_systemc_req_addr_o,
+    output logic [31:0] ext_systemc_req_wdata_o,
+
+    input  logic        ext_systemc_resp_gnt_i,
+    input  logic        ext_systemc_resp_rvalid_i,
+    input  logic [31:0] ext_systemc_resp_rdata_i,
+`endif
     input  wire         jtag_tck_i,
     input  wire         jtag_tms_i,
     input  wire         jtag_trst_ni,
@@ -74,6 +85,9 @@ module testharness #(
 
   logic [EXT_PERIPHERALS_PORT_SEL_WIDTH-1:0] ext_periph_select;
 
+  logic iffifo_in_ready, iffifo_out_valid;
+  logic iffifo_int_o;
+
   // External xbar master/slave and peripheral ports
   obi_req_t [EXT_XBAR_NMASTER_RND-1:0] ext_master_req;
   obi_req_t [EXT_XBAR_NMASTER_RND-1:0] heep_slave_req;
@@ -99,10 +113,6 @@ module testharness #(
   reg_pkg::reg_req_t [testharness_pkg::EXT_NPERIPHERALS-1:0] ext_periph_slv_req;
   reg_pkg::reg_rsp_t [testharness_pkg::EXT_NPERIPHERALS-1:0] ext_periph_slv_rsp;
 
-  // External xbar slave example port
-  obi_req_t slow_ram_slave_req;
-  obi_resp_t slow_ram_slave_resp;
-
   // External interrupts
   logic [NEXT_INT_RND-1:0] intr_vector_ext;
   logic memcopy_intr;
@@ -132,6 +142,7 @@ module testharness #(
     end
     // Re-assign the interrupt lines used here
     intr_vector_ext[0] = memcopy_intr;
+    intr_vector_ext[1] = iffifo_int_o;
   end
 
   //log parameters
@@ -249,7 +260,9 @@ module testharness #(
       .external_subsystem_powergate_iso_no(external_subsystem_powergate_iso_n),
       .external_subsystem_rst_no(external_subsystem_rst_n),
       .external_ram_banks_set_retentive_no(external_ram_banks_set_retentive_n),
-      .external_subsystem_clkgate_en_no(external_subsystem_clkgate_en_n)
+      .external_subsystem_clkgate_en_no(external_subsystem_clkgate_en_n),
+      .ext_dma_slot_tx_i(iffifo_in_ready),
+      .ext_dma_slot_rx_i(iffifo_out_valid)
   );
 
   // Testbench external bus
@@ -360,20 +373,45 @@ module testharness #(
       .exit()
   );
 
-  assign mux_jtag_tck                    = JTAG_DPI ? sim_jtag_tck : jtag_tck_i;
-  assign mux_jtag_tms                    = JTAG_DPI ? sim_jtag_tms : jtag_tms_i;
-  assign mux_jtag_tdi                    = JTAG_DPI ? sim_jtag_tdi : jtag_tdi_i;
-  assign mux_jtag_trstn                  = JTAG_DPI ? sim_jtag_trstn : jtag_trst_ni;
+  assign mux_jtag_tck   = JTAG_DPI ? sim_jtag_tck : jtag_tck_i;
+  assign mux_jtag_tms   = JTAG_DPI ? sim_jtag_tms : jtag_tms_i;
+  assign mux_jtag_tdi   = JTAG_DPI ? sim_jtag_tdi : jtag_tdi_i;
+  assign mux_jtag_trstn = JTAG_DPI ? sim_jtag_trstn : jtag_trst_ni;
+
+  assign sim_jtag_tdo   = JTAG_DPI ? mux_jtag_tdo : '0;
+  assign jtag_tdo_o     = !JTAG_DPI ? mux_jtag_tdo : '0;
 
-  assign sim_jtag_tdo                    = JTAG_DPI ? mux_jtag_tdo : '0;
-  assign jtag_tdo_o                      = !JTAG_DPI ? mux_jtag_tdo : '0;
+  // External xbar slave example port
+  obi_req_t  slow_ram_slave_req;
+  obi_resp_t slow_ram_slave_resp;
+
+`ifndef SIM_SYSTEMC
 
   assign slow_ram_slave_req              = ext_slave_req[SLOW_MEMORY_IDX];
   assign ext_slave_resp[SLOW_MEMORY_IDX] = slow_ram_slave_resp;
+`else
+
+  obi_req_t  ext_systemc_req;
+  obi_resp_t ext_systemc_resp;
+
+  assign ext_systemc_req_req_o           = ext_systemc_req.req;
+  assign ext_systemc_req_we_o            = ext_systemc_req.we;
+  assign ext_systemc_req_be_o            = ext_systemc_req.be;
+  assign ext_systemc_req_addr_o          = ext_systemc_req.addr;
+  assign ext_systemc_req_wdata_o         = ext_systemc_req.wdata;
+
+  assign ext_systemc_resp.gnt            = ext_systemc_resp_gnt_i;
+  assign ext_systemc_resp.rvalid         = ext_systemc_resp_rvalid_i;
+  assign ext_systemc_resp.rdata          = ext_systemc_resp_rdata_i;
+
+  assign ext_systemc_req                 = ext_slave_req[SLOW_MEMORY_IDX];
+  assign ext_slave_resp[SLOW_MEMORY_IDX] = ext_systemc_resp;
+`endif
 
   generate
     if (USE_EXTERNAL_DEVICE_EXAMPLE) begin : gen_USE_EXTERNAL_DEVICE_EXAMPLE
 
+`ifndef SIM_SYSTEMC
       obi_pkg::obi_req_t  slave_fifoout_req;
       obi_pkg::obi_resp_t slave_fifoout_resp;
 
@@ -389,14 +427,14 @@ module testharness #(
 
       // External xbar slave memory example
       slow_memory #(
-          .NumWords (128),
+          .NumWords (8192),
           .DataWidth(32'd32)
       ) slow_ram_i (
           .clk_i,
           .rst_ni,
           .req_i(slave_fifoout_req.req),
           .we_i(slave_fifoout_req.we),
-          .addr_i(slave_fifoout_req.addr[8:2]),
+          .addr_i(slave_fifoout_req.addr[15:2]),
           .wdata_i(slave_fifoout_req.wdata),
           .be_i(slave_fifoout_req.be),
           // output ports
@@ -404,6 +442,7 @@ module testharness #(
           .rdata_o(slave_fifoout_resp.rdata),
           .rvalid_o(slave_fifoout_resp.rvalid)
       );
+`endif
 
       parameter DMA_TRIGGER_SLOT_NUM = 4;
 
@@ -430,6 +469,22 @@ module testharness #(
           .dma_window_intr_o()
       );
 
+      simple_accelerator #(
+          .reg_req_t (reg_pkg::reg_req_t),
+          .reg_rsp_t (reg_pkg::reg_rsp_t),
+          .obi_req_t (obi_pkg::obi_req_t),
+          .obi_resp_t(obi_pkg::obi_resp_t)
+      ) simple_accelerator_i (
+          .clk_i,
+          .rst_ni,
+          .reg_req_i(ext_periph_slv_req[testharness_pkg::SIMPLE_ACC_IDX]),
+          .reg_rsp_o(ext_periph_slv_rsp[testharness_pkg::SIMPLE_ACC_IDX]),
+          .acc_read_ch0_req_o(ext_master_req[testharness_pkg::EXT_MASTER2_IDX]),
+          .acc_read_ch0_resp_i(ext_master_resp[testharness_pkg::EXT_MASTER2_IDX]),
+          .acc_write_ch0_req_o(ext_master_req[testharness_pkg::EXT_MASTER3_IDX]),
+          .acc_write_ch0_resp_i(ext_master_resp[testharness_pkg::EXT_MASTER3_IDX])
+      );
+
       // AMS external peripheral
       ams #(
           .reg_req_t(reg_pkg::reg_req_t),
@@ -441,6 +496,22 @@ module testharness #(
           .reg_rsp_o(ext_periph_slv_rsp[testharness_pkg::AMS_IDX])
       );
 
+      // InterFaced FIFO (IFFIFO) external peripheral
+      iffifo #(
+          .reg_req_t(reg_pkg::reg_req_t),
+          .reg_rsp_t(reg_pkg::reg_rsp_t)
+      ) iffifo_i (
+          .clk_i,
+          .rst_ni,
+          .reg_req_i(ext_periph_slv_req[testharness_pkg::IFFIFO_IDX]),
+          .reg_rsp_o(ext_periph_slv_rsp[testharness_pkg::IFFIFO_IDX]),
+          // DMA slots
+          .iffifo_in_ready_o(iffifo_in_ready),
+          .iffifo_out_valid_o(iffifo_out_valid),
+          // Interrupt lines
+          .iffifo_int_o(iffifo_int_o)
+      );
+
       addr_decode #(
           .NoIndices(testharness_pkg::EXT_NPERIPHERALS),
           .NoRules(testharness_pkg::EXT_NPERIPHERALS),
@@ -557,6 +628,7 @@ module testharness #(
       assign ext_master_req[testharness_pkg::EXT_MASTER0_IDX].wdata = '0;
 
       assign memcopy_intr = '0;
+      assign iffifo_int_o = '0;
       assign periph_slave_rsp = '0;
 
     end
diff --git a/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv b/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv
index 58e202ce..d74011f4 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv
@@ -7,12 +7,14 @@ package testharness_pkg;
   import addr_map_rule_pkg::*;
   import core_v_mini_mcu_pkg::*;
 
-  localparam EXT_XBAR_NMASTER = 2;
+  localparam EXT_XBAR_NMASTER = 4;
   localparam EXT_XBAR_NSLAVE = 1;
 
   //master idx
   localparam logic [31:0] EXT_MASTER0_IDX = 0;
   localparam logic [31:0] EXT_MASTER1_IDX = 1;
+  localparam logic [31:0] EXT_MASTER2_IDX = 2;
+  localparam logic [31:0] EXT_MASTER3_IDX = 3;
 
   //slave mmap and idx
   localparam logic [31:0] SLOW_MEMORY_START_ADDRESS = core_v_mini_mcu_pkg::EXT_SLAVE_START_ADDRESS;
@@ -29,7 +31,7 @@ package testharness_pkg;
   };
 
   //slave encoder
-  localparam EXT_NPERIPHERALS = 2;
+  localparam EXT_NPERIPHERALS = 4;
 
   // Memcopy controller (external peripheral example)
   localparam logic [31:0] MEMCOPY_CTRL_START_ADDRESS = core_v_mini_mcu_pkg::EXT_PERIPHERAL_START_ADDRESS + 32'h0;
@@ -38,11 +40,22 @@ package testharness_pkg;
   localparam logic [31:0] MEMCOPY_CTRL_IDX = 32'd0;
 
   // External AMS Peripheral
-  localparam logic [31:0] AMS_START_ADDRESS = core_v_mini_mcu_pkg::EXT_PERIPHERAL_START_ADDRESS + 32'h001000;
+  localparam logic [31:0] AMS_START_ADDRESS = core_v_mini_mcu_pkg::EXT_PERIPHERAL_START_ADDRESS + 32'h01000;
   localparam logic [31:0] AMS_SIZE = 32'h100;
   localparam logic [31:0] AMS_END_ADDRESS = AMS_START_ADDRESS + AMS_SIZE;
   localparam logic [31:0] AMS_IDX = 32'd1;
 
+  // External InterFaced FIFO (IFFIFO) Peripheral
+  localparam logic [31:0] IFFIFO_START_ADDRESS = core_v_mini_mcu_pkg::EXT_PERIPHERAL_START_ADDRESS + 32'h02000;
+  localparam logic [31:0] IFFIFO_SIZE = 32'h100;
+  localparam logic [31:0] IFFIFO_END_ADDRESS = IFFIFO_START_ADDRESS + IFFIFO_SIZE;
+  localparam logic [31:0] IFFIFO_IDX = 32'd2;
+
+  // External Simple Accelerator Peripheral
+  localparam logic [31:0] SIMPLE_ACC_START_ADDRESS = core_v_mini_mcu_pkg::EXT_PERIPHERAL_START_ADDRESS + 32'h03000;
+  localparam logic [31:0] SIMPLE_ACC_SIZE = 32'h100;
+  localparam logic [31:0] SIMPLE_ACC_END_ADDRESS = SIMPLE_ACC_START_ADDRESS + SIMPLE_ACC_SIZE;
+  localparam logic [31:0] SIMPLE_ACC_IDX = 32'd3;
 
   localparam addr_map_rule_t [EXT_NPERIPHERALS-1:0] EXT_PERIPHERALS_ADDR_RULES = '{
       '{
@@ -50,7 +63,13 @@ package testharness_pkg;
           start_addr: MEMCOPY_CTRL_START_ADDRESS,
           end_addr: MEMCOPY_CTRL_END_ADDRESS
       },
-      '{idx: AMS_IDX, start_addr: AMS_START_ADDRESS, end_addr: AMS_END_ADDRESS}
+      '{idx: AMS_IDX, start_addr: AMS_START_ADDRESS, end_addr: AMS_END_ADDRESS},
+      '{idx: IFFIFO_IDX, start_addr: IFFIFO_START_ADDRESS, end_addr: IFFIFO_END_ADDRESS},
+      '{
+          idx: SIMPLE_ACC_IDX,
+          start_addr: SIMPLE_ACC_START_ADDRESS,
+          end_addr: SIMPLE_ACC_END_ADDRESS
+      }
   };
 
   localparam int unsigned EXT_PERIPHERALS_PORT_SEL_WIDTH = EXT_NPERIPHERALS > 1 ? $clog2(
diff --git a/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py b/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
index e8c012f8..5c86308f 100755
--- a/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
+++ b/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
@@ -540,8 +540,28 @@ def len_extracted_peripherals(peripherals):
     linker_onchip_il_start_address = str('{:08X}'.format(int(linker_onchip_data_start_address,16) + int(linker_onchip_data_size_address,16)))
     linker_onchip_il_size_address = str('{:08X}'.format(ram_numbanks_il*32*1024))
 
+    stack_size  = string2int(obj['linker_script']['stack_size'])
+    heap_size  = string2int(obj['linker_script']['heap_size'])
+
+
+    linker_flash_code_start_address  = str('{:08X}'.format(int(linker_onchip_code_start_address,16) + int(flash_mem_start_address,16)))
+    linker_flash_data_start_address  = str('{:08X}'.format(int(linker_onchip_data_start_address,16) + int(flash_mem_start_address,16)))
+    linker_flash_il_start_address    = str('{:08X}'.format(int(linker_onchip_il_start_address,16)   + int(flash_mem_start_address,16)))
+
+    if ram_numbanks_il == 0 or (ram_numbanks_cont == 1 and ram_numbanks_il > 0):
+        linker_flash_left_start_address   = str('{:08X}'.format(int(linker_flash_data_start_address,16) + int(linker_onchip_data_size_address,16)))
+        linker_flash_left_size_address    = str('{:08X}'.format(int(flash_mem_size_address,16) - int(linker_onchip_code_size_address,16) - int(linker_onchip_data_size_address,16)))
+    else:
+        linker_flash_left_start_address   = str('{:08X}'.format(int(linker_flash_il_start_address,16) + int(linker_onchip_il_size_address,16)))
+        linker_flash_left_size_address    = str('{:08X}'.format(int(flash_mem_size_address,16) - int(linker_onchip_code_size_address,16) - int(linker_onchip_data_size_address,16) - int(linker_onchip_il_size_address,16)))
+
+
     if ((int(linker_onchip_data_size_address,16) + int(linker_onchip_code_size_address,16)) > int(ram_size_address,16)):
         exit("The code and data section must fit in the RAM size, instead they takes " + str(linker_onchip_data_size_address + linker_onchip_code_size_address))
+    
+    if ((int(stack_size,16) + int(heap_size,16)) > int(ram_size_address,16)):
+        exit("The stack and heap section must fit in the RAM size, instead they takes " + str(stack_size + heap_size))
+
 
     plic_used_n_interrupts = len(obj['interrupts']['list'])
     plit_n_interrupts = obj['interrupts']['number']
@@ -841,12 +861,19 @@ def len_extracted_peripherals(peripherals):
         "ext_slave_size_address"           : ext_slave_size_address,
         "flash_mem_start_address"          : flash_mem_start_address,
         "flash_mem_size_address"           : flash_mem_size_address,
+        "linker_flash_code_start_address"  : linker_flash_code_start_address,
+        "linker_flash_data_start_address"  : linker_flash_data_start_address,
+        "linker_flash_il_start_address"    : linker_flash_il_start_address,
+        "linker_flash_left_start_address"  : linker_flash_left_start_address,
+        "linker_flash_left_size_address"   : linker_flash_left_size_address,
         "linker_onchip_code_start_address" : linker_onchip_code_start_address,
         "linker_onchip_code_size_address"  : linker_onchip_code_size_address,
         "linker_onchip_data_start_address" : linker_onchip_data_start_address,
         "linker_onchip_data_size_address"  : linker_onchip_data_size_address,
         "linker_onchip_il_start_address"   : linker_onchip_il_start_address,
         "linker_onchip_il_size_address"    : linker_onchip_il_size_address,
+        "stack_size"                       : stack_size,
+        "heap_size"                        : heap_size,
         "plic_used_n_interrupts"           : plic_used_n_interrupts,
         "plit_n_interrupts"                : plit_n_interrupts,
         "interrupts"                       : interrupts,
diff --git a/hw/vendor/esl_epfl_x_heep/util/structs_gen.py b/hw/vendor/esl_epfl_x_heep/util/structs_gen.py
index f815de76..3c776b42 100644
--- a/hw/vendor/esl_epfl_x_heep/util/structs_gen.py
+++ b/hw/vendor/esl_epfl_x_heep/util/structs_gen.py
@@ -1,4 +1,5 @@
 import hjson
+from  math import ceil
 import string
 import argparse
 import sys
@@ -297,7 +298,7 @@ def add_registers(peripheral_json):
                 n_bits += count_bits(f["bits"])
 
             # computes the number of registers needed to pack all the bit fields needed
-            n_multireg = int((count * n_bits) /  int(peripheral_json["regwidth"]))
+            n_multireg = ceil((count * n_bits) /  int(peripheral_json["regwidth"]))
             
             # generate the multiregisters
             for r in range(n_multireg):
diff --git a/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core b/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core
index 05b75ba5..98252573 100644
--- a/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core
+++ b/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core
@@ -14,7 +14,9 @@ filesets:
     - example:ip:gpio_cnt
     - example:ip:pdm2pcm_dummy
     - example:ip:ams
+    - example:ip:iffifo
     - example:ip:i2s_microphone
+    - example:ip:simple_accelerator
     files:
     file_type: systemVerilogSource
 
@@ -22,6 +24,8 @@ filesets:
     files:
     - hw/ip_examples/slow_memory/slow_memory.vlt
     - hw/ip_examples/ams/ams.vlt
+    - hw/ip_examples/iffifo/iffifo.vlt
+    - hw/ip_examples/simple_accelerator/simple_accelerator.vlt
     - tb/tb.vlt
     file_type: vlt
 
@@ -67,6 +71,11 @@ filesets:
     - tb/tb_top.cpp
     file_type: cppSource
 
+  tb-sc-verilator:
+    files:
+    - tb/tb_sc_top.cpp
+    file_type: cppSource
+
 targets:
   default: &default_target
     filesets:
@@ -75,13 +84,17 @@ targets:
     - tool_verilator? (uartdpi)
     - tool_modelsim? (systemverilog_only_uart)
     - tool_vcs? (systemverilog_only_uart)
+    - tool_xcelium? (systemverilog_only_uart)
     - tool_verilator? (files_verilator_waiver)
     - tool_verilator? (remote_bitbang_dpi)
     - tool_modelsim? (systemverilog_only_simjtag)
     - tool_vcs? (systemverilog_only_simjtag)
+    - tool_xcelium? (systemverilog_only_simjtag)
     - tool_modelsim? (cypress_flash)
     - tool_vcs? (cypress_flash)
+    - tool_xcelium? (cypress_flash)
     toplevel:
     - tool_modelsim? (tb_top)
     - tool_vcs? (tb_top)
+    - tool_xcelium? (tb_top)
     - tool_verilator? (testharness)
diff --git a/hw/vendor/eslepfl_x_heep.lock.hjson b/hw/vendor/eslepfl_x_heep.lock.hjson
index 04dcb944..0ae40dc6 100644
--- a/hw/vendor/eslepfl_x_heep.lock.hjson
+++ b/hw/vendor/eslepfl_x_heep.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/x-heep.git
-    rev: df569a88fc7eaa447645262f0d3a76dd22c519f7
+    rev: 76d58efe7b9dec0723c1cb9aaf8ad76ad6c85373
   }
 }

From 812bd681ee782770e943f69642ab78f816dc6b4a Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Mon, 18 Mar 2024 16:53:38 +0100
Subject: [PATCH 04/27] revendor x-heep Luigi fix

---
 hw/vendor/eslepfl_x_heep.vendor.hjson             | 4 ++--
 sw/applications/transformer/SYLT-FFT              | 1 +
 sw/applications/transformer_il/SYLT-FFT           | 1 +
 sw/applications/transformer_without_cgra/SYLT-FFT | 1 +
 4 files changed, 5 insertions(+), 2 deletions(-)
 create mode 160000 sw/applications/transformer/SYLT-FFT
 create mode 160000 sw/applications/transformer_il/SYLT-FFT
 create mode 160000 sw/applications/transformer_without_cgra/SYLT-FFT

diff --git a/hw/vendor/eslepfl_x_heep.vendor.hjson b/hw/vendor/eslepfl_x_heep.vendor.hjson
index 2571c6da..e60b27ec 100644
--- a/hw/vendor/eslepfl_x_heep.vendor.hjson
+++ b/hw/vendor/eslepfl_x_heep.vendor.hjson
@@ -7,8 +7,8 @@
   target_dir: "esl_epfl_x_heep",
 
   upstream: {
-    url: "https://github.com/esl-epfl/x-heep.git",
-    rev: "76d58efe7b9dec0723c1cb9aaf8ad76ad6c85373",
+    url: "https://github.com/Luigi2898/x-heep.git",
+    rev: "849539ddf996926f9b679837f3bc84c0799287bb",
   },
 
   patch_dir: "patches/esl_epfl_x_heep",
diff --git a/sw/applications/transformer/SYLT-FFT b/sw/applications/transformer/SYLT-FFT
new file mode 160000
index 00000000..c6f58caa
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT
@@ -0,0 +1 @@
+Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b
diff --git a/sw/applications/transformer_il/SYLT-FFT b/sw/applications/transformer_il/SYLT-FFT
new file mode 160000
index 00000000..c6f58caa
--- /dev/null
+++ b/sw/applications/transformer_il/SYLT-FFT
@@ -0,0 +1 @@
+Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b
diff --git a/sw/applications/transformer_without_cgra/SYLT-FFT b/sw/applications/transformer_without_cgra/SYLT-FFT
new file mode 160000
index 00000000..c6f58caa
--- /dev/null
+++ b/sw/applications/transformer_without_cgra/SYLT-FFT
@@ -0,0 +1 @@
+Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b

From ac9f32d584b234c108f25ca05a8829b18823f3b6 Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Mon, 18 Mar 2024 16:55:02 +0100
Subject: [PATCH 05/27] Update esl_epfl_x_heep to Luigi2898/x-heep@849539d

Update code from upstream repository
https://github.com/Luigi2898/x-heep.git to revision
849539ddf996926f9b679837f3bc84c0799287bb

Signed-off-by: mbelda <11842513+mbelda@users.noreply.github.com>
---
 hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt | 24 ++++++++++-----------
 hw/vendor/eslepfl_x_heep.lock.hjson         |  4 ++--
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
index 9639d6cf..ef5743c6 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
+++ b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
@@ -63,19 +63,19 @@ FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS ${SOURCE_PATH}*.h)
 SET(dir_list_str "")
 FOREACH(file_path ${new_list})
   SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-  if(${file_path} MATCHES "${ROOT_PROJECT}device/")
-    if(${file_path} MATCHES "${ROOT_PROJECT}device/target/") # Add it if its not in target, or if its in target/${TARGET}
-      if(${file_path} MATCHES "${ROOT_PROJECT}device/target/${TARGET}")
+  if(${file_path} MATCHES "${SOURCE_PATH}device/")
+    if(${file_path} MATCHES "${SOURCE_PATH}device/target/") # Add it if its not in target, or if its in target/${TARGET}
+      if(${file_path} MATCHES "${SOURCE_PATH}device/target/${TARGET}")
         SET(add 1)
       endif()
     else()
       SET(add 1)
     endif()
-  elseif(${file_path} MATCHES ${PROJECT})
+  elseif(${file_path} MATCHES ${SOURCE_PATH}applications/${PROJECT}/)
     SET(add 1)
-  elseif( ( ${file_path} MATCHES "${ROOT_PROJECT}freertos/" ) AND ( ${PROJECT} MATCHES "freertos" ) )
+  elseif( ( ${file_path} MATCHES "${SOURCE_PATH}freertos/" ) AND ( ${PROJECT} MATCHES "freertos" ) )
     SET(add 1)
-  elseif( ${file_path} MATCHES "${ROOT_PROJECT}external/" )
+  elseif( ${file_path} MATCHES "${SOURCE_PATH}external/" )
     SET(add 1)
   endif()
 
@@ -124,14 +124,14 @@ SET( c_dir_list "" )
 SET( app_found 0 )
 FOREACH(file_path IN LISTS new_list)
   SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
-  if(${file_path} MATCHES "${ROOT_PROJECT}device/")
+  if(${file_path} MATCHES "${SOURCE_PATH}device/")
     SET(add 1)
-  elseif( ${file_path} MATCHES "${ROOT_PROJECT}external/" )
+  elseif( ${file_path} MATCHES "${SOURCE_PATH}external/" )
     SET(add 1)
-  elseif( ( ${file_path} MATCHES "/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES ${MAINFILE} ) )
-    SET(add 1)
-    elseif( ( ${file_path} MATCHES "/${PROJECT}/" ) AND ( ${file_path} MATCHES ${MAINFILE} ) )
+  elseif( ${file_path} MATCHES "${SOURCE_PATH}applications/${PROJECT}/.*${MAINFILE}\." ) # look for main.*
     SET(app_found 1)
+  elseif( ${file_path} MATCHES "${SOURCE_PATH}applications/${PROJECT}/" ) # other sources
+    SET(add 1)
   endif()
 
   if( add EQUAL 1 ) # If the file path mathced one of the criterion, add it to the list
@@ -155,7 +155,7 @@ if( app_found EQUAL 0 )
     SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
     if(${file_path} MATCHES "${ROOT_PROJECT}device/")
       SET(add 1)
-    elseif( ( ${file_path} MATCHES "/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES ${MAINFILE} ) )
+    elseif( ( ${file_path} MATCHES "${ROOT_PROJECT}/applications/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES "${ROOT_PROJECT}applications/${PROJECT}/.*${MAINFILE}\." ) )
       SET(add 1)
     endif()
 
diff --git a/hw/vendor/eslepfl_x_heep.lock.hjson b/hw/vendor/eslepfl_x_heep.lock.hjson
index 0ae40dc6..e6880390 100644
--- a/hw/vendor/eslepfl_x_heep.lock.hjson
+++ b/hw/vendor/eslepfl_x_heep.lock.hjson
@@ -8,7 +8,7 @@
 {
   upstream:
   {
-    url: https://github.com/esl-epfl/x-heep.git
-    rev: 76d58efe7b9dec0723c1cb9aaf8ad76ad6c85373
+    url: https://github.com/Luigi2898/x-heep.git
+    rev: 849539ddf996926f9b679837f3bc84c0799287bb
   }
 }

From 9c5dd988382b89c09538a16ca6127cef909d660c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miranda=20Calero=20Jos=C3=A9=20Angel?=
 <jamirand@eslsrv11.intranet.epfl.ch>
Date: Fri, 7 Jun 2024 17:17:10 +0200
Subject: [PATCH 06/27] 1. Port ZCU / 2. fix xdc file for the ZCU / 3. Fix top
 to include dif clk for ZCU

---
 cgra_x_heep.core                              | 43 ++++++++++++++++++-
 hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv    | 17 +++++++-
 .../hw/fpga/constraints/zcu104/pin_assign.xdc | 34 +++++++++------
 3 files changed, 76 insertions(+), 18 deletions(-)

diff --git a/cgra_x_heep.core b/cgra_x_heep.core
index d828a37c..a548bd1c 100644
--- a/cgra_x_heep.core
+++ b/cgra_x_heep.core
@@ -107,7 +107,6 @@ filesets:
 
   ip-fpga:
     files:
-    - hw/fpga/scripts/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
     - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
     - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource } # Here there are the following modules
     - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
@@ -117,6 +116,16 @@ filesets:
     - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
     - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }
 
+  ip-fpga-pynq-z2:
+    files:
+    - hw/fpga/scripts/pynq-z2/set_board.tcl: { file_type: tclSource }
+    - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+
+  ip-fpga-zcu104:
+    files:
+    - hw/fpga/scripts/zcu104/set_board.tcl: { file_type: tclSource }
+    - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+
   fpga-arm-emulation:
     depend:
     - pulp-platform.org::axi_spi_slave
@@ -129,7 +138,13 @@ filesets:
 
   xdc-fpga-pynq-z2:
     files:
-    - hw/fpga_cgra/constraints/pin_assign.xdc
+    - hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
+    - hw/fpga/constraints/pynq-z2/constraints.xdc
+    file_type: xdc
+
+  xdc-fpga-zcu104:
+    files:
+    - hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
     file_type: xdc
 
   netlist-fpga:
@@ -154,6 +169,10 @@ parameters:
     datatype: bool
     paramtype: vlogdefine
     default: false
+  FPGA_ZCU104:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
   # Make the parameter known to FuseSoC to enable overrides from the
   # command line. If not overwritten, use the generic technology library.
   PRIM_DEFAULT_IMPL:
@@ -277,4 +296,24 @@ targets:
     tools:
       vivado:
         part: xc7z020clg400-1
+    toplevel: [xilinx_cgra_x_heep_wrapper]
+
+  zcu104:
+    <<: *default_target
+    default_tool: vivado
+    description: ZCU104 Evaluation Board
+    filesets_append:
+    - x_heep_system
+    - rtl-fpga
+    - ip-fpga-zcu104
+    - ip-fpga
+    - xdc-fpga-zcu104
+    - ext_bus
+    parameters:
+    - COREV_PULP=0
+    - SYNTHESIS=true
+    - FPGA_ZCU104=true
+    tools:
+      vivado:
+        part: xczu7ev-ffvc1156-2-e
     toplevel: [xilinx_cgra_x_heep_wrapper]
\ No newline at end of file
diff --git a/hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv b/hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv
index ca4f6ab4..ddba0861 100644
--- a/hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv
+++ b/hw/fpga_cgra/xilinx_cgra_x_heep_wrapper.sv
@@ -11,8 +11,13 @@ module xilinx_cgra_x_heep_wrapper
     parameter ZFINX    = 0,
     parameter CLK_LED_COUNT_LENGTH = 27
 ) (
-    inout logic         clk_i,
-    inout logic         rst_i,
+`ifdef FPGA_ZCU104
+    inout logic clk_300mhz_n,
+    inout logic clk_300mhz_p,
+`else
+    inout logic clk_i,
+`endif
+    inout logic rst_i,
 
     //visibility signals
     output logic        rst_led,
@@ -84,10 +89,18 @@ module xilinx_cgra_x_heep_wrapper
   // clock output for debugging
   assign clk_out = clk_gen;
 
+`ifdef FPGA_ZCU104
+  xilinx_clk_wizard_wrapper xilinx_clk_wizard_wrapper_i (
+      .CLK_IN1_D_0_clk_n(clk_300mhz_n),
+      .CLK_IN1_D_0_clk_p(clk_300mhz_p),
+      .clk_out1_0(clk_gen)
+  );
+`else  // FPGA PYNQ-Z2
   xilinx_clk_wizard_wrapper xilinx_clk_wizard_wrapper_i (
       .clk_125MHz(clk_i),
       .clk_out1_0(clk_gen)
   );
+`endif
 
   cgra_x_heep_top #(
         .COREV_PULP (0),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
index 4b523cdf..2a431086 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
@@ -12,8 +12,9 @@ set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports rst_i]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_i]
 
 # LEDS
-set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports rst_led_o]
-set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports clk_led_o]
+set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports rst_led]
+set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports clk_led]
+set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports clk_out]
 set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
 set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
 
@@ -81,19 +82,24 @@ set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports {gpio_io[16]}
 set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[17]}]
 
 # PDM2PCM
-set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_clk_io]
-set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_pdm_io]
+# set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_clk_io]
+# set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_pdm_io]
+set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports {gpio_io[19]}]
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[18]}]
 
 # I2S
-set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports i2s_sck_io]
-set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports i2s_ws_io]
-set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports i2s_sd_io]
+# set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports i2s_sck_io]
+# set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports i2s_ws_io]
+# set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports i2s_sd_io]
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[20]}]
+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[21]}]
+set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[22]}]
 
 # SPI2
-set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_o[0]}]
-set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_o[1]}]
-set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports spi2_sck_o]
-set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[0]}]
-set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[1]}]
-set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[2]}]
-set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[3]}]
+set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_io[0]}]
+set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_io[1]}]
+set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports {spi2_sck_o}]
+set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_0_io}]
+set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_1_io}]
+set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_2_io}]
+set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_3_io}]

From 17aecfd28a26ef961f7d817c6e2e1332ce067d6c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miranda=20Calero=20Jos=C3=A9=20Angel?=
 <jamirand@eslsrv11.intranet.epfl.ch>
Date: Fri, 7 Jun 2024 17:18:19 +0200
Subject: [PATCH 07/27] added new pin and constraint files

---
 .../constraints/pynq-z2/constraints.xdc       |   1 +
 .../constraints/pynq-z2/pin_assign.xdc        |  93 ++++++++++++++++
 .../constraints/zcu104/pin_assign.xdc         | 105 ++++++++++++++++++
 .../pynq-z2/xilinx_generate_clk_wizard.tcl    |  44 ++++++++
 .../zcu104/xilinx_generate_clk_wizard.tcl     |  40 +++++++
 5 files changed, 283 insertions(+)
 create mode 100644 hw/fpga_cgra/constraints/pynq-z2/constraints.xdc
 create mode 100644 hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
 create mode 100644 hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
 create mode 100644 hw/fpga_cgra/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl
 create mode 100644 hw/fpga_cgra/scripts/zcu104/xilinx_generate_clk_wizard.tcl

diff --git a/hw/fpga_cgra/constraints/pynq-z2/constraints.xdc b/hw/fpga_cgra/constraints/pynq-z2/constraints.xdc
new file mode 100644
index 00000000..38e2f6b3
--- /dev/null
+++ b/hw/fpga_cgra/constraints/pynq-z2/constraints.xdc
@@ -0,0 +1 @@
+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 5} [get_ports {clk_i}];
diff --git a/hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc b/hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
new file mode 100644
index 00000000..deb10d68
--- /dev/null
+++ b/hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
@@ -0,0 +1,93 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk_i]
+set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports rst_i]
+
+set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports rst_led]
+set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports clk_led]
+set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports clk_out]
+
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports boot_select_i]
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports execute_from_flash_i]
+
+## Pmoda
+## RPi GPIO 7-0 are shared with pmoda_rpi_gpio_tri_io[7:0]
+
+# QSPI
+# Q0 / MOSI
+# Q1 / MISO
+# Q2 / nWP
+# Q3 / nHLD
+
+
+## Pmodb
+#set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {crst}]
+set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i]
+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i]
+set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni]
+set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i]
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o]
+
+set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports uart_tx_o]
+set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports uart_rx_i]
+
+set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[0]}]
+set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[1]}]
+set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[2]}]
+set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[3]}]
+set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[4]}]
+set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {gpio_io[5]}]
+set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[6]}]
+set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {gpio_io[7]}]
+set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[8]}]
+set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS33} [get_ports {gpio_io[9]}]
+set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[10]}]
+set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {gpio_io[11]}]
+set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports {gpio_io[12]}]
+set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[13]}]
+set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {gpio_io[14]}]
+set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports {gpio_io[15]}]
+set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports {gpio_io[16]}]
+set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports {gpio_io[17]}]
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports {gpio_io[18]}]
+set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {gpio_io[19]}]
+## Tri-color LD5 for TARGET_PYNQ_Z2
+set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS33} [get_ports {gpio_io[20]}]
+set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[21]}]
+set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports {gpio_io[22]}]
+
+set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
+set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
+
+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]
+set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]
+set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]
+set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]
+set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o]
+set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o]
+
+set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[0]}]
+set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[1]}]
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[2]}]
+set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {spi_sd_io[3]}]
+set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports spi_csb_o]
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports spi_sck_o]
+
+set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_0_io}]
+set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_1_io}]
+set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_2_io}]
+set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {spi2_sd_3_io}]
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_io[0]}]
+set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {spi2_csb_io[1]}]
+set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports {spi2_sck_o}]
+
+set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {i2c_scl_io}]
+set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {i2c_sda_io}]
+
+# Removing this line (but leaving the one in constraints.xdc gives an error and recommends adding exactly this to turn it into a warning)
+# Having this line along with the one in constrains.xdc gives an critical warning
+# Not having the line in constraints.xdc synthezises SUPER slow (>1h), or at least thats a candidate for that. 
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]
+
diff --git a/hw/fpga_cgra/constraints/zcu104/pin_assign.xdc b/hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
new file mode 100644
index 00000000..48044127
--- /dev/null
+++ b/hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
@@ -0,0 +1,105 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# CLOCK
+set_property -dict {PACKAGE_PIN AH18 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
+set_property -dict {PACKAGE_PIN AH17 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i]
+
+# RESET
+set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports rst_i]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_i]
+
+# LEDS
+set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports rst_led]
+set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports clk_led]
+set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports clk_out]
+set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
+set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
+
+# SWITCHES
+set_property -dict {PACKAGE_PIN E4 IOSTANDARD LVCMOS33} [get_ports execute_from_flash_i]
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports boot_select_i]
+
+# FLASH
+# QSPI
+# Q0 / MOSI
+# Q1 / MISO
+# Q2 / nWP
+# Q3 / nHLD
+set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o]
+set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o]
+set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]
+set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]
+set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]
+set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]
+
+# UART
+set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports uart_tx_o]
+set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports uart_rx_i]
+
+# JTAG
+set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i]
+set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o]
+set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i]
+set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i]
+set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni]
+
+# I2C
+set_property -dict {PACKAGE_PIN J7 IOSTANDARD LVCMOS33} [get_ports i2c_scl_io]
+set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports i2c_sda_io]
+
+## The following pins are sent to the FMC connector, using the LA pins as single-ended.
+## The bank only supports up to 1.8 V.
+
+# SPI SD
+set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports spi_csb_o]
+set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports spi_sck_o]
+set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[0]}]
+set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[1]}]
+set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[2]}]
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[3]}]
+
+# GPIOs
+set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[0]}]
+set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[1]}]
+set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[2]}]
+set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports {gpio_io[3]}]
+set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[4]}]
+set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[5]}]
+set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[6]}]
+set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[7]}]
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[8]}]
+set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[9]}]
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[10]}]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[11]}]
+set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[12]}]
+set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[13]}]
+set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[14]}]
+set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[15]}]
+set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports {gpio_io[16]}]
+set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[17]}]
+
+# PDM2PCM
+# set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_clk_io]
+# set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_pdm_io]
+set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports {gpio_io[19]}]
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[18]}]
+
+# I2S
+# set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports i2s_sck_io]
+# set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports i2s_ws_io]
+# set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports i2s_sd_io]
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[20]}]
+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[21]}]
+set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[22]}]
+
+# SPI2
+set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_io[0]}]
+set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_io[1]}]
+set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports spi2_sck_o]
+set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi2_sd_0_io]
+set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports spi2_sd_1_io]
+set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports spi2_sd_2_io]
+set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports spi2_sd_3_io]
\ No newline at end of file
diff --git a/hw/fpga_cgra/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl b/hw/fpga_cgra/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl
new file mode 100644
index 00000000..e61c5832
--- /dev/null
+++ b/hw/fpga_cgra/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl
@@ -0,0 +1,44 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# Define design macros
+
+set design_name      xilinx_clk_wizard
+set in_clk_freq_MHz  125
+set out_clk_freq_MHz 15
+
+
+# Create block design
+create_bd_design $design_name
+
+# Create ports
+set clk_125MHz [ create_bd_port -dir I -type clk -freq_hz [ expr $in_clk_freq_MHz * 1000000 ] clk_125MHz ]
+set clk_out1_0 [ create_bd_port -dir O -type clk clk_out1_0 ]
+set_property -dict [ list CONFIG.FREQ_HZ [ expr $out_clk_freq_MHz * 1000000 ] ] $clk_out1_0
+
+# Create instance and set properties
+set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+set_property -dict [ list \
+ CONFIG.CLKIN1_JITTER_PS {80.0} \
+ CONFIG.CLKOUT1_JITTER {172.798} \
+ CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {15} \
+ CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
+ CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
+ CONFIG.MMCM_CLKOUT0_DIVIDE_F {50.000} \
+ CONFIG.PRIM_IN_FREQ $in_clk_freq_MHz \
+ CONFIG.USE_LOCKED {false} \
+ CONFIG.USE_RESET {false} \
+] $clk_wiz_0
+
+# Create port connections
+connect_bd_net -net clk_in1_0_1 [ get_bd_ports clk_125MHz ] [ get_bd_pins clk_wiz_0/clk_in1 ]
+connect_bd_net -net clk_wiz_0_clk_out1 [ get_bd_ports clk_out1_0 ] [ get_bd_pins clk_wiz_0/clk_out1 ]
+
+# Save and close block design
+save_bd_design
+close_bd_design $design_name
+
+# create wrapper
+set wrapper_path [ make_wrapper -fileset sources_1 -files [ get_files -norecurse xilinx_clk_wizard.bd ] -top ]
+add_files -norecurse -fileset sources_1 $wrapper_path
diff --git a/hw/fpga_cgra/scripts/zcu104/xilinx_generate_clk_wizard.tcl b/hw/fpga_cgra/scripts/zcu104/xilinx_generate_clk_wizard.tcl
new file mode 100644
index 00000000..d67e4054
--- /dev/null
+++ b/hw/fpga_cgra/scripts/zcu104/xilinx_generate_clk_wizard.tcl
@@ -0,0 +1,40 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# Define design macros
+
+set design_name xilinx_clk_wizard
+
+# Create block design
+create_bd_design $design_name
+
+# Create instance and set properties
+create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
+set_property -dict [list \
+  CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \
+  CONFIG.CLKOUT1_JITTER {282.792} \
+  CONFIG.CLKOUT1_PHASE_ERROR {207.545} \
+  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {15} \
+  CONFIG.CLK_IN1_BOARD_INTERFACE {clk_300mhz} \
+  CONFIG.MMCM_CLKFBOUT_MULT_F {32.875} \
+  CONFIG.MMCM_CLKIN1_PERIOD {3.333} \
+  CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
+  CONFIG.MMCM_CLKOUT0_DIVIDE_F {65.750} \
+  CONFIG.MMCM_DIVCLK_DIVIDE {10} \
+  CONFIG.OPTIMIZE_CLOCKING_STRUCTURE_EN {true} \
+  CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
+  CONFIG.USE_LOCKED {false} \
+  CONFIG.USE_RESET {true} \
+] [get_bd_cells clk_wiz_0]
+
+# Create ports
+make_bd_pins_external [get_bd_cells clk_wiz_0]
+make_bd_intf_pins_external [get_bd_cells clk_wiz_0]
+
+# Save and close block design
+save_bd_design
+close_bd_design $design_name
+
+# Create wrapper
+set wrapper_path [ make_wrapper -fileset sources_1 -files [ get_files -norecurse xilinx_clk_wizard.bd ] -top ]
+add_files -norecurse -fileset sources_1 $wrapper_path

From 08e2c122568f6fb0e434acf18746d62ddb8932b5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miranda=20Calero=20Jos=C3=A9=20Angel?=
 <jamirand@eslsrv11.intranet.epfl.ch>
Date: Fri, 7 Jun 2024 17:27:12 +0200
Subject: [PATCH 08/27] removed vendor modification

---
 .../hw/fpga/constraints/zcu104/pin_assign.xdc | 105 ------------------
 1 file changed, 105 deletions(-)
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc

diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
deleted file mode 100644
index 2a431086..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
+++ /dev/null
@@ -1,105 +0,0 @@
-# Copyright 2022 EPFL
-# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-# CLOCK
-set_property -dict {PACKAGE_PIN AH18 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
-set_property -dict {PACKAGE_PIN AH17 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i]
-
-# RESET
-set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports rst_i]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_i]
-
-# LEDS
-set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports rst_led]
-set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports clk_led]
-set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports clk_out]
-set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
-set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
-
-# SWITCHES
-set_property -dict {PACKAGE_PIN E4 IOSTANDARD LVCMOS33} [get_ports execute_from_flash_i]
-set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports boot_select_i]
-
-# FLASH
-# QSPI
-# Q0 / MOSI
-# Q1 / MISO
-# Q2 / nWP
-# Q3 / nHLD
-set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o]
-set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o]
-set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]
-set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]
-set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]
-set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]
-
-# UART
-set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports uart_tx_o]
-set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports uart_rx_i]
-
-# JTAG
-set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i]
-set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o]
-set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i]
-set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i]
-set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni]
-
-# I2C
-set_property -dict {PACKAGE_PIN J7 IOSTANDARD LVCMOS33} [get_ports i2c_scl_io]
-set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports i2c_sda_io]
-
-## The following pins are sent to the FMC connector, using the LA pins as single-ended.
-## The bank only supports up to 1.8 V.
-
-# SPI SD
-set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports spi_csb_o]
-set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports spi_sck_o]
-set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[0]}]
-set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[1]}]
-set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[2]}]
-set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[3]}]
-
-# GPIOs
-set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[0]}]
-set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[1]}]
-set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[2]}]
-set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports {gpio_io[3]}]
-set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[4]}]
-set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[5]}]
-set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[6]}]
-set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[7]}]
-set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[8]}]
-set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[9]}]
-set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[10]}]
-set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[11]}]
-set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[12]}]
-set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[13]}]
-set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[14]}]
-set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[15]}]
-set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports {gpio_io[16]}]
-set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[17]}]
-
-# PDM2PCM
-# set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_clk_io]
-# set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_pdm_io]
-set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports {gpio_io[19]}]
-set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[18]}]
-
-# I2S
-# set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports i2s_sck_io]
-# set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports i2s_ws_io]
-# set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports i2s_sd_io]
-set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[20]}]
-set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[21]}]
-set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[22]}]
-
-# SPI2
-set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_io[0]}]
-set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_io[1]}]
-set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports {spi2_sck_o}]
-set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_0_io}]
-set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_1_io}]
-set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_2_io}]
-set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_3_io}]

From 5a2ace28f72bc0a25bde6328d55e805c3f0ec286 Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Fri, 28 Jun 2024 13:41:34 +0200
Subject: [PATCH 09/27] Add matmul example

---
 sw/applications/transformer/SYLT-FFT    | 1 -
 sw/applications/transformer_il/SYLT-FFT | 1 -
 2 files changed, 2 deletions(-)
 delete mode 160000 sw/applications/transformer/SYLT-FFT
 delete mode 160000 sw/applications/transformer_il/SYLT-FFT

diff --git a/sw/applications/transformer/SYLT-FFT b/sw/applications/transformer/SYLT-FFT
deleted file mode 160000
index c6f58caa..00000000
--- a/sw/applications/transformer/SYLT-FFT
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b
diff --git a/sw/applications/transformer_il/SYLT-FFT b/sw/applications/transformer_il/SYLT-FFT
deleted file mode 160000
index c6f58caa..00000000
--- a/sw/applications/transformer_il/SYLT-FFT
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b

From 0c780bd39ff26410cd7a26ffceb2014caf48bda0 Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Fri, 28 Jun 2024 13:43:18 +0200
Subject: [PATCH 10/27] Add matmul os example

---
 sw/applications/mmul_os/4x4/bitstreams   |   2 +
 sw/applications/mmul_os/4x4/out.sat      | 477 +++++++++++++++++++++++
 sw/applications/mmul_os/cgra_bitstream.h |  14 +
 sw/applications/mmul_os/main.c           | 294 ++++++++++++++
 sw/applications/mmul_os/mulSoftware.py   |  51 +++
 sw/applications/mmul_os/performance.c    |  62 +++
 sw/applications/mmul_os/performance.h    |  62 +++
 sw/applications/mmul_os/transformer.h    |  16 +
 8 files changed, 978 insertions(+)
 create mode 100644 sw/applications/mmul_os/4x4/bitstreams
 create mode 100644 sw/applications/mmul_os/4x4/out.sat
 create mode 100644 sw/applications/mmul_os/cgra_bitstream.h
 create mode 100644 sw/applications/mmul_os/main.c
 create mode 100644 sw/applications/mmul_os/mulSoftware.py
 create mode 100644 sw/applications/mmul_os/performance.c
 create mode 100644 sw/applications/mmul_os/performance.h
 create mode 100644 sw/applications/mmul_os/transformer.h

diff --git a/sw/applications/mmul_os/4x4/bitstreams b/sw/applications/mmul_os/4x4/bitstreams
new file mode 100644
index 00000000..4e32db09
--- /dev/null
+++ b/sw/applications/mmul_os/4x4/bitstreams
@@ -0,0 +1,2 @@
+kmem: 0x0, 0xf01c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
+imem: 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4081ff4, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x850d0000, 0x0, 0x0, 0xc80000, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xab0000, 0xd0000, 0x8780001c, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8a0d0001, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xab0000, 0xd0000, 0xd0000, 0x87800018, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x7a180004, 0x0, 0x5a080010, 0x8a0d0001, 0x7a181ff0, 0x1a181ffd, 0xd0000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x5080000, 0x0, 0x820d0000, 0x0, 0x820d0000, 0x2080000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x2080000, 0x0, 0x0, 0x0, 0x5080000, 0x820d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x820d0000, 0x0, 0x3080000, 0x0, 0x820d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x43180000, 0x0, 0x830d0000, 0x0, 0x830d0000, 0x4080000, 0x840d0000, 0x0, 0xab0000, 0xd0000, 0x0, 0x0, 0xf0000, 0x87800010, 0x8a0d0001, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x7a181ffc, 0x0, 0x0, 0xd0000, 0x7a180010, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x830d0000, 0x0, 0x2080000, 0x0, 0x830d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x3a080010, 0x0, 0x0, 0x0, 0x4080000, 0x830d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x800005, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x800003, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa508000c, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x840d0000, 0x0, 0x800002, 0x0, 0xab0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 
\ No newline at end of file
diff --git a/sw/applications/mmul_os/4x4/out.sat b/sw/applications/mmul_os/4x4/out.sat
new file mode 100644
index 00000000..d661655a
--- /dev/null
+++ b/sw/applications/mmul_os/4x4/out.sat
@@ -0,0 +1,477 @@
+T = 0
+LWD R2
+LWD R2
+LWD R2
+LWD R1
+LWD R1
+LWD R2
+LWD R2
+LWD R2
+LWD R2
+LWD R1
+LWD R2
+LWD R2
+LWD R2
+LWD R2
+LWD R1
+LWD R2
+T = 1
+NOP
+NOP
+NOP
+SADD R2, ZERO, ZERO
+SADD R2, ZERO, ZERO
+NOP
+NOP
+NOP
+NOP
+SADD R2, ZERO, ZERO
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+T = 2
+NOP
+NOP
+NOP
+BEQ R2, R1, 28
+SADD R2, ZERO, ZERO
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+T = 3
+NOP
+NOP
+NOP
+NOP
+BEQ R2, R1, 24
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+T = 4
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO 
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO 
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO 
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO
+SADD R3, ZERO, ZERO 
+T = 5
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+BEQ R2, R1, 16
+NOP
+NOP
+NOP
+NOP
+NOP
+NOP
+T = 6
+NOP 
+NOP 
+LWI R0, R2
+NOP
+NOP 
+NOP 
+NOP 
+LWI R0, R2
+LWI R0, R2
+SADD R2, R2, 1
+NOP 
+NOP
+NOP 
+LWI R0, R2
+NOP 
+NOP
+T = 7
+NOP 
+SADD R0, ZERO, RCT
+NOP 
+SADD R0, ZERO, RCB
+SADD R0, ZERO, RCB
+NOP 
+SADD R0, ZERO, RCT
+NOP
+NOP 
+SADD R0, ZERO, RCB
+NOP 
+SADD R0, ZERO, RCT
+SADD R0, ZERO, RCT
+NOP 
+SADD R0, ZERO, RCB
+NOP 
+T = 8
+SADD R0, ZERO, RCB
+NOP 
+NOP 
+NOP
+NOP 
+SADD R0, ZERO, RCB
+NOP 
+NOP
+NOP 
+NOP 
+SADD R0, ZERO, RCB
+NOP 
+NOP 
+NOP 
+NOP 
+SADD R0, ZERO, RCB
+T = 9
+LWI ROUT, R2
+NOP 
+NOP 
+NOP
+NOP 
+LWI ROUT, R2
+NOP 
+NOP
+NOP 
+NOP 
+LWI ROUT, R2
+NOP
+NOP 
+NOP 
+NOP 
+LWI ROUT, R2
+T = 10
+NOP 
+SADD ROUT, ZERO, RCL
+NOP 
+SADD ROUT, ZERO, RCR
+SADD ROUT, ZERO, RCR
+NOP 
+SADD ROUT, ZERO, RCL
+NOP
+NOP 
+SADD ROUT, ZERO, RCR
+NOP 
+SADD ROUT, ZERO, RCL
+SADD ROUT, ZERO, RCL
+NOP 
+SADD ROUT, ZERO, RCR
+NOP 
+T = 11
+NOP 
+NOP 
+SADD ROUT, ZERO, RCL
+NOP
+NOP 
+NOP 
+NOP 
+SADD ROUT, ZERO, RCL
+SADD ROUT, ZERO, RCL
+NOP 
+NOP 
+NOP
+NOP 
+SADD ROUT, ZERO, RCL
+NOP 
+NOP
+T = 12
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+SMUL ROUT, R0, ROUT
+T = 13
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+SADD R3, R3, ROUT
+T = 14
+NOP 
+NOP 
+SADD R2, R2, 4
+NOP
+SMUL ROUT, R1, 16
+NOP 
+NOP 
+SADD R2, R2, 4 
+SADD R2, R2, 4
+NOP 
+NOP 
+NOP
+NOP 
+SADD R2, R2, 4
+SMUL ROUT, R1, 16
+NOP
+T = 15
+SADD R2, R2, RCB
+NOP 
+NOP 
+NOP 
+NOP 
+SADD R2, R2, RCL
+NOP 
+NOP
+NOP 
+NOP 
+SADD R2, R2, RCB
+NOP 
+BEQ ZERO, ZERO, 5
+NOP 
+NOP 
+SADD R2, R2, RCL
+T = 16
+NOP
+SADD ROUT, ZERO, R2
+NOP
+NOP 
+NOP
+NOP
+SADD ROUT, ZERO, R2
+NOP 
+NOP
+NOP
+NOP
+SADD ROUT, ZERO, R2
+SADD ROUT, ZERO, R2
+NOP
+NOP
+NOP
+T = 17
+SADD ROUT, -12, RCT
+SADD R2, R2, 16 
+SADD ROUT, -4, RCB
+NOP 
+NOP
+SADD ROUT, 4, RCT 
+SADD R2, R2, 16 
+SADD ROUT, -4, RCB
+SADD ROUT, -4, RCB 
+NOP 
+SADD ROUT, 4, RCT 
+SADD R2, R2, 16 
+SADD R2, R2, 16
+SADD ROUT, 12, RCB
+NOP 
+SADD ROUT, 4, RCT
+T = 18
+NOP 
+SADD ROUT, R2, -16
+NOP 
+SADD ROUT, -4, RCB
+SADD ROUT, -4, RCB
+NOP 
+SADD ROUT, R2, -16
+NOP
+NOP 
+SADD ROUT, 4, RCT 
+NOP 
+SADD ROUT, R2, -16 
+SADD ROUT, R2, -16
+NOP 
+SADD ROUT, 4, RCT 
+NOP
+T = 19
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT 
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT
+SWI R3, ROUT 
+T = 20
+NOP 
+NOP
+NOP
+NOP
+SMUL ROUT, R1, 4
+NOP
+NOP
+NOP
+NOP 
+SMUL ROUT, R1, -4
+NOP
+NOP
+NOP 
+NOP
+NOP
+NOP
+T = 21
+NOP
+NOP 
+NOP
+NOP
+NOP
+SADD ROUT, ZERO, RCB
+NOP
+NOP
+SMUL ROUT, RCT, RCR
+NOP 
+NOP
+NOP
+NOP
+NOP 
+NOP
+NOP
+T = 22
+NOP 
+NOP
+NOP 
+NOP
+SADD ROUT, RCB, 16
+NOP
+SADD ROUT, ZERO, RCL
+NOP
+NOP 
+NOP
+NOP 
+SADD ROUT, RCR, 16
+NOP 
+NOP
+NOP 
+NOP
+T = 23
+SADD R2, R2, RCB 
+NOP
+SADD R2, R2, RCB
+NOP
+SADD R2, R2, 1
+SADD R2, R2, RCL 
+NOP 
+SADD R2, R2, RCL
+SADD R2, R2, RCR 
+SADD R2, ZERO, ZERO
+SADD R2, R2, RCR
+NOP
+BEQ ZERO, ZERO, 3
+SADD R2, R2, RCT 
+NOP 
+SADD R2, R2, RCT
+T = 24
+NOP 
+NOP
+NOP
+NOP
+SMUL ROUT, R1, -16
+NOP
+NOP
+NOP
+NOP 
+SMUL ROUT, R1, 16
+NOP
+NOP
+NOP 
+NOP
+NOP
+NOP
+T = 25
+SADD R2, R2, RCB 
+NOP 
+NOP 
+NOP
+SMUL ROUT, ROUT, -3
+SADD R2, R2, RCL
+NOP 
+SADD ROUT, ZERO, RCR
+SADD R2, R2, RCR 
+NOP 
+SADD ROUT, ZERO, RCL
+NOP
+NOP
+SADD R2, R2, RCT
+NOP 
+NOP
+T = 26
+NOP 
+NOP 
+NOP 
+NOP
+SADD R2, ZERO, ZERO 
+SADD ROUT, ZERO, RCL
+SADD ROUT, ZERO, RCB
+NOP
+SADD ROUT, ZERO, RCT
+NOP 
+NOP 
+SADD ROUT, ZERO, RCT
+NOP 
+NOP 
+NOP 
+NOP
+T = 27
+NOP 
+SADD R2, R2, RCB
+SADD R2, R2, RCB
+SADD R2, R2, 1
+NOP 
+NOP 
+SADD R2, R2, RCL
+SADD R2, R2, RCL 
+SADD R2, R2, RCT
+NOP 
+SADD R2, R2, RCR
+SADD R2, R2, RCR
+SADD R2, R2, RCT
+BEQ ZERO, ZERO, 2
+NOP 
+SADD R2, R2, RCT
+T = 0
diff --git a/sw/applications/mmul_os/cgra_bitstream.h b/sw/applications/mmul_os/cgra_bitstream.h
new file mode 100644
index 00000000..92eb977f
--- /dev/null
+++ b/sw/applications/mmul_os/cgra_bitstream.h
@@ -0,0 +1,14 @@
+#ifndef _CGRA_BITSTREAM_H_
+#define _CGRA_BITSTREAM_H_
+
+#include <stdint.h>
+
+#include "cgra.h"
+
+// Kernel 0 => NULL
+#define TRANSFORMER 1
+
+static uint32_t cgra_kmem_bitstream[CGRA_KMEM_SIZE] = { 0x0, 0xf01c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+const uint32_t  cgra_imem_bitstream[CGRA_IMEM_SIZE] = { 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4081ff4, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x850d0000, 0x0, 0x0, 0xc80000, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xab0000, 0xd0000, 0x8780001c, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8a0d0001, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xab0000, 0xd0000, 0xd0000, 0x87800018, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x7a180004, 0x0, 0x5a080010, 0x8a0d0001, 0x7a181ff0, 0x1a181ffd, 0xd0000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x5080000, 0x0, 0x820d0000, 0x0, 0x820d0000, 0x2080000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x2080000, 0x0, 0x0, 0x0, 0x5080000, 0x820d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x820d0000, 0x0, 0x3080000, 0x0, 0x820d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x43180000, 0x0, 0x830d0000, 0x0, 0x830d0000, 0x4080000, 0x840d0000, 0x0, 0xab0000, 0xd0000, 0x0, 0x0, 0xf0000, 0x87800010, 0x8a0d0001, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x7a181ffc, 0x0, 0x0, 0xd0000, 0x7a180010, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x830d0000, 0x0, 0x2080000, 0x0, 0x830d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x3a080010, 0x0, 0x0, 0x0, 0x4080000, 0x830d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x800005, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x800003, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa508000c, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x840d0000, 0x0, 0x800002, 0x0, 0xab0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+#endif // _CGRA_BITSTREAM_H_
diff --git a/sw/applications/mmul_os/main.c b/sw/applications/mmul_os/main.c
new file mode 100644
index 00000000..2d9a386f
--- /dev/null
+++ b/sw/applications/mmul_os/main.c
@@ -0,0 +1,294 @@
+/*
+                              *******************
+******************************* C SOURCE FILE *******************************
+**                            *******************                          **
+**                                                                         **
+** project  : HEEPsilon                                                    **
+** filename : main.c                                                       **
+** version  : 1                                                            **
+** date     : 01/10/23                                                     **
+**                                                                         **
+*****************************************************************************
+**                                                                         **
+** Copyright (c) EPFL                                                      **
+** All rights reserved.                                                    **
+**                                                                         **
+*****************************************************************************
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+
+/**
+* @file   main.c
+* @date   01/10/23
+* @brief  An application to run a matrix multiplication.
+*
+*/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                             MODULES USED                                 */
+/**                                                                        **/
+/****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include "transformer.h"
+#include "cgra_bitstream.h"
+#include "cgra_x_heep.h"
+#include "performance.h"
+
+// For interrupt handling
+#include "csr.h"
+#include "handler.h"
+#include "rv_plic.h"
+#include "rv_plic_regs.h"
+#include "hart.h"
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                        DEFINITIONS AND MACROS                            */
+/**                                                                        **/
+/****************************************************************************/
+
+// Size of the input buffer for the CGRA
+#define CGRA_COL_INPUT_SIZE 4
+
+/****************************************************************************/
+/**                                                                        **/
+/*                      PROTOTYPES OF LOCAL FUNCTIONS                       */
+/**                                                                        **/
+/****************************************************************************/
+
+// Matrix multiplication using the standard three loops
+void mmulSoftware(int32_t * output);
+// Fill input matrixes with numbers
+void fillMatrixInputs();
+// Handler for the CGRA interruption
+void handler_irq_cgra(uint32_t id);
+// Record the cycle number at the start
+void kcom_perfRecordStart( kcom_time_diff_t *perf );
+// Record the cycle number and compute the total cycles
+void kcom_perfRecordStop( kcom_time_diff_t *perf );
+// Show the performance metrics
+void showPerformance( kcom_perf_t* kperf, int full);
+// Print a matrix
+void printMatrix(int * matrix, int rows, int cols);
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            GLOBAL VARIABLES                              */
+/**                                                                        **/
+/****************************************************************************/
+
+// Performance variable
+static kcom_perf_t  kperf;
+
+// Plic controller variables
+volatile bool               cgra_intr_flag;
+
+// CGRA variables
+static cgra_t               cgra;
+static uint8_t              cgra_slot;
+
+// CGRA input and output buffers
+static int32_t cgra_input[CGRA_N_COLS][CGRA_COL_INPUT_SIZE]    __attribute__ ((aligned (4)));
+
+// Input and output matrixes
+int32_t matrixA[ROWS_A*COLS_A];
+int32_t matrixB[ROWS_B*COLS_B];
+int32_t matrixC[ROWS_C*COLS_C];
+int32_t outSW[ROWS_C*COLS_C];
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            LOCAL FUNCTIONS                               */
+/**                                                                        **/
+/****************************************************************************/
+
+void main()
+{
+  fillMatrixInputs();
+
+  // Init timer
+  timerInit();
+
+  // Enable and reset the CGRA performance counters
+  cgra_perf_cnt_enable(&cgra, 1);
+  cgra_perf_cnt_reset( &cgra );
+
+  if(ROWS_C < CGRA_N_COLS || COLS_C < CGRA_N_ROWS){
+    kcom_perfRecordStart(&(kperf.time.sw));
+    mmulSoftware(matrixC);
+    kcom_perfRecordStop(&(kperf.time.sw));
+  } else {
+
+    // Initialize the CGRA
+    kcom_perfRecordStart(&(kperf.time.load));
+    initCGRA();
+    kcom_perfRecordStop(&(kperf.time.load));
+
+    // Prepare the input vector for the CGRA
+    kcom_perfRecordStart(&(kperf.time.input));
+    // Col 0: &B[0][0], nItLoopColsC, &A[0][0], &C[0][3]
+    cgra_input[0][0] = &matrixB[0];
+    cgra_input[0][1] = COLS_C/CGRA_N_ROWS;
+    cgra_input[0][2] = &matrixA[0];
+    cgra_input[0][3] = &matrixC[3];
+    // Col 1: &C[1][0], &B[0][1], nItLoopsColsA, &A[1][0]
+    cgra_input[1][0] = &matrixC[COLS_C];
+    cgra_input[1][1] = &matrixB[1];
+    cgra_input[1][2] = COLS_A;
+    cgra_input[1][3] = &matrixA[COLS_A];
+    // Col 2: &A[2][0], &C[2][1], &B[0][2], nItLoopColsC
+    cgra_input[2][0] = &matrixA[2*COLS_A];
+    cgra_input[2][1] = &matrixC[2*COLS_C+1];
+    cgra_input[2][2] = &matrixB[2];
+    cgra_input[2][3] = COLS_C/CGRA_N_ROWS;
+    // Col 3: nItLoopRowsC, &A[3][0], &C[3][2], &B[0][3], 
+    cgra_input[3][0] = ROWS_C/CGRA_N_COLS;
+    cgra_input[3][1] = &matrixA[3*COLS_A];
+    cgra_input[3][2] = &matrixC[3*COLS_C+2];
+    cgra_input[3][3] = &matrixB[3];
+    kcom_perfRecordStop(&(kperf.time.input));
+
+    // Set CGRA kernel L/S pointers
+    kcom_perfRecordStart( &(kperf.time.reprogramCols) );
+    for(int col_idx = 0 ; col_idx < CGRA_N_COLS ; col_idx++){
+      cgra_set_read_ptr ( &cgra, cgra_slot, (uint32_t) cgra_input[col_idx], col_idx );
+    }
+    kcom_perfRecordStop( &(kperf.time.reprogramCols) );
+
+    // CGRA Execution
+    kcom_perfRecordStart(   &(kperf.time.cgra) );
+    cgra_intr_flag = 0;
+    cgra_set_kernel( &cgra, cgra_slot, TRANSFORMER );
+    // Wait until CGRA is done
+    while(cgra_intr_flag==0) {
+      wait_for_interrupt();
+    }
+    kcom_perfRecordStop(   &(kperf.time.cgra) );
+
+  
+    // Software 
+    kcom_perfRecordStart(&(kperf.time.sw));
+    mmulSoftware(outSW);
+    kcom_perfRecordStop(&(kperf.time.sw));
+
+    checkErrors();
+  }
+
+  showPerformance(&kperf, 0);
+  
+  return EXIT_SUCCESS;
+}
+
+// Check if the SW and CGRA executions give the same result
+void checkErrors(){
+  int errors = 0;
+  for(int i = 0; i < ROWS_C*COLS_C; i++ ){
+    if(outSW[i]!=matrixC[i]){
+      errors++;
+    }
+  }
+  printf("\rErrors: %d\n", errors);
+
+  if(errors>0){
+    printMatrix(matrixC, ROWS_C, COLS_C);
+  }
+}
+
+// Initialize the CGRA
+void initCGRA(){
+  // Init the PLIC
+  plic_Init();
+  plic_irq_set_priority(CGRA_INTR, 1);
+  plic_irq_set_enabled(CGRA_INTR, kPlicToggleEnabled);
+  plic_assign_external_irq_handler( CGRA_INTR, (void *) &handler_irq_cgra);
+
+  // Enable interrupt on processor side
+  // Enable global interrupt for machine-level interrupts
+  CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+  // Set mie.MEIE bit to one to enable machine-level external interrupts
+  const uint32_t mask = 1 << 11;//IRQ_EXT_ENABLE_OFFSET;
+  CSR_SET_BITS(CSR_REG_MIE, mask);
+  cgra_intr_flag = 0;
+
+  // Load kernel
+  cgra_cmem_init(cgra_imem_bitstream, cgra_kmem_bitstream);
+
+  cgra.base_addr = mmio_region_from_addr((uintptr_t)CGRA_PERIPH_START_ADDRESS);
+  // Select request slot of CGRA
+  cgra_slot = cgra_get_slot(&cgra);
+}
+
+// Fill matrix inputs
+void fillMatrixInputs(){
+  for(int i = 0; i < ROWS_A; i++){
+    for(int j=0; j < COLS_A; j++){
+      matrixA[i*COLS_A+j] = (i*COLS_A+j+1)%100;
+    }
+  }
+
+  for(int i = 0; i < ROWS_B; i++){
+    for(int j=0;j < COLS_B; j++){
+      matrixB[i*COLS_B+j] = (i*COLS_B+j+1)%100;
+    }
+  }
+}
+
+// Software matrix multiplication
+void mmulSoftware(int32_t * out){
+  for(int i = 0; i < ROWS_A; i++){
+    for(int j=0;j < COLS_B; j++){
+      for(int k=0; k < COLS_A; k++){
+        out[i*COLS_C+j] += matrixA[i*COLS_A+k]*matrixB[k*COLS_B+j];
+      }
+    }
+  }
+}
+
+// Print matrix
+void printMatrix(int * matrix, int rows, int cols){
+  for(int i = 0; i < rows; i++){
+    printf("[ ");
+    for(int j=0; j < cols; j++){
+      printf("%d ", matrix[i*cols+j]);
+    }
+    printf("]\n");
+  }
+}
+
+// Interrupt controller variables
+void handler_irq_cgra(uint32_t id) {
+  cgra_intr_flag = 1;
+}
+
+// Display the performance values
+void showPerformance( kcom_perf_t* kperf, int full){
+  printf("\rA:%dx%d, B:%dx%d\n", ROWS_A, COLS_A, ROWS_B, COLS_B);
+  printf("\rSw: %d\n", kperf->time.sw.spent_cy);
+  if (full){
+    printf("\rLoad: %d\n", kperf->time.load.spent_cy);
+    printf("\rProgram cols: %d\n", kperf->time.reprogramCols.spent_cy);
+    printf("\rInput: %d\n", kperf->time.input.spent_cy);
+    printf("\rCgra: %d\n", kperf->time.cgra.spent_cy);
+  }
+  int32_t overhead = kperf->time.input.spent_cy + kperf->time.reprogramCols.spent_cy + kperf->time.load.spent_cy;
+  //printf("\rOverhead: %d\n", overhead);
+  printf("\rTotal cgra: %d\n", overhead + kperf->time.cgra.spent_cy); 
+}
+
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                                 EOF                                      */
+/**                                                                        **/
+/****************************************************************************/
diff --git a/sw/applications/mmul_os/mulSoftware.py b/sw/applications/mmul_os/mulSoftware.py
new file mode 100644
index 00000000..fe38a9e4
--- /dev/null
+++ b/sw/applications/mmul_os/mulSoftware.py
@@ -0,0 +1,51 @@
+
+def crear_matriz(filas, columnas):
+    matriz = [[i*columnas + j + 1 for j in range(columnas)] for i in range(filas)]
+    return matriz
+
+def mostrar_matriz(matriz):
+    for fila in matriz:
+        print(fila)
+
+def multiplicar_matrices(matriz_a, matriz_b):
+    resultado = [[0 for _ in range(len(matriz_b[0]))] for _ in range(len(matriz_a))]
+
+    for i in range(len(matriz_a)):
+        for j in range(len(matriz_b[0])):
+            for k in range(len(matriz_b)):
+                resultado[i][j] += matriz_a[i][k] * matriz_b[k][j]
+
+    return resultado
+
+
+def main():
+    filas_a = int(input("Ingrese el número de filas para la matriz A: "))
+    columnas_a = int(input("Ingrese el número de columnas para la matriz A: "))
+
+    filas_b = int(input("Ingrese el número de filas para la matriz B: "))
+    columnas_b = int(input("Ingrese el número de columnas para la matriz B: "))
+
+    if columnas_a != filas_b:
+        print("No se pueden multiplicar matrices con estas dimensiones.")
+        return
+
+    # Crear matrices A y B
+    matriz_a = crear_matriz(filas_a, columnas_a)
+    matriz_b = crear_matriz(filas_b, columnas_b)
+
+    # Mostrar matrices A y B
+    #print("\nMatriz A:")
+    #mostrar_matriz(matriz_a)
+
+    #print("\nMatriz B:")
+    #mostrar_matriz(matriz_b)
+
+    # Multiplicar matrices A y B
+    matriz_resultado = multiplicar_matrices(matriz_a, matriz_b)
+
+    # Mostrar resultado
+    print("\nResultado de la multiplicación:")
+    mostrar_matriz(matriz_resultado)
+
+if __name__ == "__main__":
+    main()
diff --git a/sw/applications/mmul_os/performance.c b/sw/applications/mmul_os/performance.c
new file mode 100644
index 00000000..421d39be
--- /dev/null
+++ b/sw/applications/mmul_os/performance.c
@@ -0,0 +1,62 @@
+#include "performance.h"
+
+// For the timer
+#include "rv_timer.h"
+#include "soc_ctrl.h"
+#include "core_v_mini_mcu.h"
+
+// Timer
+static rv_timer_t          timer;
+
+void kcom_perfRecordStart( kcom_time_diff_t *perf )
+{
+    timeStart( perf );
+}
+
+void kcom_perfRecordStop( kcom_time_diff_t *perf )
+{
+    timeStop( perf );
+}
+
+void timeStart( kcom_time_diff_t *perf )
+{
+    perf->start_cy = getTime_cy();
+}
+
+void timeStop( kcom_time_diff_t *perf )
+{
+    perf->end_cy = getTime_cy();
+    perf->spent_cy += perf->end_cy - perf->start_cy;
+}
+
+uint64_t getTime_cy( )
+{
+    static uint64_t out;
+    rv_timer_counter_read( &timer, HART_ID, &out );
+    return out;
+}
+
+//Initialize the timer
+void timerInit()
+{
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr  = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz  = soc_ctrl_get_frequency(&soc_ctrl);
+
+    mmio_region_t timer_0_reg = mmio_region_from_addr(RV_TIMER_AO_START_ADDRESS);
+
+    rv_timer_init( timer_0_reg, (rv_timer_config_t) { .hart_count = 2, .comparator_count = 1 }, &timer );
+
+    rv_timer_tick_params_t tick_params;
+
+    // The same frequency is provaided to get one tick per cycle.
+    rv_timer_approximate_tick_params( freq_hz, freq_hz, &tick_params );
+    rv_timer_set_tick_params(&timer, HART_ID, tick_params);
+
+    // Juan: see if i cannot remove this!
+    rv_timer_irq_enable(&timer, HART_ID, 0, kRvTimerEnabled);
+    rv_timer_arm(&timer, HART_ID, 0, 1);
+
+    rv_timer_counter_set_enabled(&timer, HART_ID, kRvTimerEnabled);
+
+}
\ No newline at end of file
diff --git a/sw/applications/mmul_os/performance.h b/sw/applications/mmul_os/performance.h
new file mode 100644
index 00000000..b7e17578
--- /dev/null
+++ b/sw/applications/mmul_os/performance.h
@@ -0,0 +1,62 @@
+#include <stdint.h>
+#include "cgra.h"
+
+typedef long int    kcom_time_t;
+typedef kcom_time_t kcom_param_t;
+
+typedef struct
+{
+    uint32_t cyc_act;
+    uint32_t cyc_stl;
+} kcom_col_perf_t;
+
+typedef struct
+{
+    kcom_time_t start_cy;
+    kcom_time_t end_cy;
+    kcom_time_t spent_cy;
+} kcom_time_diff_t;
+
+typedef struct
+{
+    kcom_time_diff_t    sw;
+    kcom_time_diff_t    cgra;
+    kcom_time_diff_t    load;
+    kcom_time_diff_t    input;
+    kcom_time_diff_t    output;
+    kcom_time_diff_t    reprogramCols;
+    kcom_time_diff_t    bitstream;
+} kcom_timing_t;
+
+typedef struct
+{
+    kcom_col_perf_t    cols[CGRA_N_COLS];
+    kcom_col_perf_t    cols_max;
+    uint32_t           cyc_ratio; // Stored *CGRA_STAT_PERCENT_MULTIPLIER
+    kcom_timing_t      time;
+} kcom_perf_t;
+
+typedef struct
+{
+    kcom_param_t sw;
+    kcom_param_t conf;
+    kcom_param_t cgra;
+    kcom_param_t repo;
+} kcom_run_t;
+
+typedef struct
+{
+   kcom_run_t   avg;
+   uint32_t     n;
+   uint32_t     errors;
+   uint8_t      *name;
+} kcom_stats_t;
+
+#define HART_ID 0
+
+void timerInit();
+uint64_t getTime_cy( );
+void timeStop( kcom_time_diff_t *perf );
+void timeStart( kcom_time_diff_t *perf );
+void kcom_perfRecordStop( kcom_time_diff_t *perf );
+void kcom_perfRecordStart( kcom_time_diff_t *perf );
\ No newline at end of file
diff --git a/sw/applications/mmul_os/transformer.h b/sw/applications/mmul_os/transformer.h
new file mode 100644
index 00000000..7fe11944
--- /dev/null
+++ b/sw/applications/mmul_os/transformer.h
@@ -0,0 +1,16 @@
+#ifndef _STIMULI_H_
+#define _STIMULI_H_
+
+#include <stdint.h>
+#include "cgra.h"
+
+// C multiple of 4x4
+
+#define ROWS_A 16
+#define COLS_A 16
+#define COLS_B 16
+#define ROWS_B COLS_A
+#define ROWS_C ROWS_A
+#define COLS_C COLS_B
+
+#endif // _STIMULI_H_

From 38c546bde2070166cc27edbcbcb4d7b7667c8d8d Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Fri, 28 Jun 2024 13:44:51 +0200
Subject: [PATCH 11/27] Add transformer example

---
 sw/applications/transformer/addNormC.c        |  71 +++++++
 sw/applications/transformer/addNormC.h        |  26 +++
 sw/applications/transformer/cgra_bitstream.h  |  12 ++
 sw/applications/transformer/data_cpp/data.cpp | 104 ++++++++++
 .../transformer/data_cpp/signal.cpp           |   5 +
 sw/applications/transformer/dense_layerC.c    |  69 +++++++
 sw/applications/transformer/dense_layerC.h    |  30 +++
 sw/applications/transformer/main.c            | 156 +++++++++++++++
 sw/applications/transformer/main.h            |  17 ++
 sw/applications/transformer/matMulC.c         |  22 +++
 sw/applications/transformer/matMulC.h         |  21 ++
 sw/applications/transformer/multiply_cgra.c   | 177 +++++++++++++++++
 sw/applications/transformer/multiply_cgra.h   |   6 +
 sw/applications/transformer/param.h           |  26 +++
 sw/applications/transformer/performance.c     |  62 ++++++
 sw/applications/transformer/performance.h     |  63 ++++++
 sw/applications/transformer/selfattentionC.c  |  68 +++++++
 sw/applications/transformer/selfattentionC.h  |  35 ++++
 sw/applications/transformer/softmaxC.c        |  38 ++++
 sw/applications/transformer/softmaxC.h        |  17 ++
 sw/applications/transformer/stftVec.h         |   3 +
 .../transformer/tokenPosEmbeddingC.c          |  33 ++++
 .../transformer/tokenPosEmbeddingC.h          |  24 +++
 .../transformer/transformerBlockC.c           | 115 +++++++++++
 .../transformer/transformerBlockC.h           |  48 +++++
 sw/applications/transformer/transposeC.c      |  31 +++
 sw/applications/transformer/transposeC.h      |  22 +++
 .../transformer/weightsAndBiasesC.c           | 181 ++++++++++++++++++
 .../transformer/weightsAndBiasesC.h           |  15 ++
 29 files changed, 1497 insertions(+)
 create mode 100644 sw/applications/transformer/addNormC.c
 create mode 100644 sw/applications/transformer/addNormC.h
 create mode 100644 sw/applications/transformer/cgra_bitstream.h
 create mode 100644 sw/applications/transformer/data_cpp/data.cpp
 create mode 100644 sw/applications/transformer/data_cpp/signal.cpp
 create mode 100644 sw/applications/transformer/dense_layerC.c
 create mode 100644 sw/applications/transformer/dense_layerC.h
 create mode 100644 sw/applications/transformer/main.c
 create mode 100644 sw/applications/transformer/main.h
 create mode 100644 sw/applications/transformer/matMulC.c
 create mode 100644 sw/applications/transformer/matMulC.h
 create mode 100644 sw/applications/transformer/multiply_cgra.c
 create mode 100644 sw/applications/transformer/multiply_cgra.h
 create mode 100644 sw/applications/transformer/param.h
 create mode 100644 sw/applications/transformer/performance.c
 create mode 100644 sw/applications/transformer/performance.h
 create mode 100644 sw/applications/transformer/selfattentionC.c
 create mode 100644 sw/applications/transformer/selfattentionC.h
 create mode 100644 sw/applications/transformer/softmaxC.c
 create mode 100644 sw/applications/transformer/softmaxC.h
 create mode 100644 sw/applications/transformer/stftVec.h
 create mode 100644 sw/applications/transformer/tokenPosEmbeddingC.c
 create mode 100644 sw/applications/transformer/tokenPosEmbeddingC.h
 create mode 100644 sw/applications/transformer/transformerBlockC.c
 create mode 100644 sw/applications/transformer/transformerBlockC.h
 create mode 100644 sw/applications/transformer/transposeC.c
 create mode 100644 sw/applications/transformer/transposeC.h
 create mode 100644 sw/applications/transformer/weightsAndBiasesC.c
 create mode 100644 sw/applications/transformer/weightsAndBiasesC.h

diff --git a/sw/applications/transformer/addNormC.c b/sw/applications/transformer/addNormC.c
new file mode 100644
index 00000000..31828e28
--- /dev/null
+++ b/sw/applications/transformer/addNormC.c
@@ -0,0 +1,71 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "addNormC.h"
+
+
+
+// Function implementations
+AddNormalize createAddNormalize(int seq_len, int input_dim, quant_bit_width *weight, quant_bit_width *bias) {
+    AddNormalize addNorm;
+    addNorm.seq_len_ = seq_len;
+    addNorm.input_dim_ = input_dim;
+    addNorm.weight_ = weight;
+    addNorm.bias_ = bias;
+    // Initialize other fields as needed
+    return addNorm;
+}
+
+
+
+
+void normalize(AddNormalize *addNorm, quant_bit_width *input, quant_bit_width *input_normalized) {
+    for (int i = 0; i < addNorm->seq_len_; i++) {
+        quant_bit_width *input_ptr = input + i * (addNorm->input_dim_);
+        quant_bit_width *input_normalized_ptr = input_normalized + i * (addNorm->input_dim_);
+
+        int sum = 0;
+        for (int j = 0; j < addNorm->input_dim_; j++) {
+            sum += *input_ptr;
+            input_ptr++;
+        }
+
+        input_ptr = input + i * (addNorm->input_dim_);
+        quant_bit_width mean = (quant_bit_width)((float)sum / (float)addNorm->input_dim_);
+
+        int64_t variance = 0;
+        for (int j = 0; j < addNorm->input_dim_; j++) {
+            variance += MUL_HQ((*input_ptr - mean), (*input_ptr - mean));
+            input_ptr++;
+        }
+
+        variance = SHIFT(variance);
+        float variance_float = (float)variance / (float)(addNorm->input_dim_);
+        variance_float = variance_float / (float)(1 << NUM_FRACTION_BITS);
+        float sd = sqrtf(variance_float);
+        float sd_inv = (float)(1 / (sd + 0.00001)); // prevent zero divide!
+        quant_bit_width sd_inv_int = (quant_bit_width)(sd_inv * (1 << NUM_FRACTION_BITS));
+
+        input_ptr = input + i * (addNorm->input_dim_);
+        input_normalized_ptr = input_normalized + i * (addNorm->input_dim_);
+
+        for (int j = 0; j < addNorm->input_dim_; j++) {
+            *input_normalized_ptr = (quant_bit_width)MUL((*input_ptr - mean), sd_inv_int);
+            *input_normalized_ptr = (quant_bit_width)(MUL((*input_normalized_ptr), addNorm->weight_[j]) + addNorm->bias_[j]);
+            input_ptr++;
+            input_normalized_ptr++;
+        }
+    }
+}
+
+void add(quant_bit_width *input, quant_bit_width *to_be_added, int seq_len, int input_dim) {
+    int32_t sum;
+    for (int i = 0; i < seq_len * input_dim; i++) {
+        sum = input[i] + to_be_added[i];
+        if ((quant_bit_width)sum != sum) // In case of overflow in 16 bits
+            input[i] = (sum > 0) ? INT16_MAX : INT16_MIN;
+        else
+            input[i] = (quant_bit_width)sum;
+    }
+}
diff --git a/sw/applications/transformer/addNormC.h b/sw/applications/transformer/addNormC.h
new file mode 100644
index 00000000..c2132867
--- /dev/null
+++ b/sw/applications/transformer/addNormC.h
@@ -0,0 +1,26 @@
+//
+// Created by alireza on 10/5/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_ADDNORMC_H
+#define FVLLMONTITRANSFORMER_ADDNORMC_H
+
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "math.h"
+#include "param.h"
+
+typedef struct {
+    int seq_len_;
+    int input_dim_;
+    quant_bit_width *weight_;
+    quant_bit_width *bias_;
+} AddNormalize;
+
+
+AddNormalize createAddNormalize(int seq_len, int input_dim, quant_bit_width *weight, quant_bit_width *bias);
+void normalize(AddNormalize *addNorm, quant_bit_width *input, quant_bit_width *input_normalized);
+void add(quant_bit_width *input, quant_bit_width *to_be_added, int seq_len, int input_dim);
+
+#endif //FVLLMONTITRANSFORMER_ADDNORMC_H
diff --git a/sw/applications/transformer/cgra_bitstream.h b/sw/applications/transformer/cgra_bitstream.h
new file mode 100644
index 00000000..014ee6b8
--- /dev/null
+++ b/sw/applications/transformer/cgra_bitstream.h
@@ -0,0 +1,12 @@
+#ifndef _CGRA_BITSTREAM_H_
+#define _CGRA_BITSTREAM_H_
+
+#include <stdint.h>
+
+#include "cgra.h"
+
+
+static uint32_t cgra_kmem_bitstream[CGRA_KMEM_SIZE] = { 0x0, 0xf01c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+const uint32_t  cgra_imem_bitstream[CGRA_IMEM_SIZE] = { 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4081ff4, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x850d0000, 0x0, 0x0, 0xc80000, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xab0000, 0xd0000, 0x8780001c, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8a0d0001, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xab0000, 0xd0000, 0xd0000, 0x87800018, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x7a180004, 0x0, 0x5a080010, 0x8a0d0001, 0x7a181ff0, 0x1a181ffd, 0xd0000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x5080000, 0x0, 0x820d0000, 0x0, 0x820d0000, 0x2080000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x2080000, 0x0, 0x0, 0x0, 0x5080000, 0x820d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x820d0000, 0x0, 0x3080000, 0x0, 0x820d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x43180000, 0x0, 0x830d0000, 0x0, 0x830d0000, 0x4080000, 0x840d0000, 0x0, 0xab0000, 0xd0000, 0x0, 0x0, 0xf0000, 0x87800010, 0x8a0d0001, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x7a181ffc, 0x0, 0x0, 0xd0000, 0x7a180010, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x830d0000, 0x0, 0x2080000, 0x0, 0x830d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x3a080010, 0x0, 0x0, 0x0, 0x4080000, 0x830d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x800005, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x800003, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa508000c, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x840d0000, 0x0, 0x800002, 0x0, 0xab0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+#endif // _CGRA_BITSTREAM_H_
diff --git a/sw/applications/transformer/data_cpp/data.cpp b/sw/applications/transformer/data_cpp/data.cpp
new file mode 100644
index 00000000..4e7efc7a
--- /dev/null
+++ b/sw/applications/transformer/data_cpp/data.cpp
@@ -0,0 +1,104 @@
+#include "stdint-gcc.h"
+
+int32_t pos_embedding[1936] = {-1383, 964, -5839, -3654, -5069, 4064, -1907, -3855, -3658, -8857, 316, -1245, -3385, 1368, -2997, 13377, 7049, -1252, 2205, -219, -1524, -1316, 4386, 3600, 244, 6103, 1171, 2736, -222, -10278, 728, -1065, 297, 490, 2032, 4887, 4769, -2205, -2950, 3033, 1045, -84, -924, -9504, 871, 6262, -6855, -7938, 3453, -1851, 2541, 741, 10731, 1307, 2100, -4055, -1536, 5267, -2867, -2898, 1939, 25, 3560, 3399, -2064, 139, -1077, 4781, -8273, -6488, 403, 439, 1265, 8417, -106, -211, -4182, 3988, 6307, 104, 3200, -2645, 2750, 1677, 5047, 1988, -368, 784, 2920, 1074, -3975, 322, 2831, -2976, -1221, 4132, -8774, -3231, -3688, -1704, 6092, 4813, -2799, -686, 6206, 460, 10634, 6885, -3182, 5878, 920, -1219, 461, 2684, -2039, -7031, -5283, -6447, 5388, 490, 692, -1467, 28, -72, -766, 6259, 2560, 9225, -6087, -4768, -285, 933, -5913, 6449, 840, -2466, 1073, 2144, 2515, -2408, -7375, 7211, -1006, 1794, -9011, -5, 2908, 3234, 891, -2127, 2135, 1420, -1477, -820, 486, 2927, 2929, -6034, -4795, 6535, 981, 1943, -2114, 112, 1866, 3449, 114, 4353, -3075, 722, 8027, -2035, -2310, 1004, -1842, 766, -193, -4143, -468, -10321, -641, -4879, -58, -4413, -6004, 1211, 2336, -7301, -2585, -2329, -2014, -9458, -2424, -2518, -2531, -1006, -11344, -79, 579, -2929, -3784, -115, 1487, 338, -6021, 6798, -3510, -1279, -584, 4754, 4306, 6089, 5313, -7733, -5283, -1086, -4182, -10, 1619, 7458, 4068, 3304, -3974, -2321, -3290, 1892, 4567, 3601, 3791, 6113, -2470, -1036, 3080, 2368, -84, -365, -3006, 2347, -2591, -3977, -5959, 1168, 475, -7409, 4234, -3694, -3462, -2384, -1386, 6249, 2631, -3582, -2584, -3016, -4120, -3507, 6681, 9170, -512, 2289, 437, -7173, -4825, -7726, -3024, 3, -152, 2356, -125, -793, 1257, 11753, 841, 689, -5175, 525, -30, 2126, 399, 4477, -6030, -8924, 6246, 2527, 4445, 3728, 3477, -4071, -2582, 265, 2704, 4541, 4935, -4722, -661, 2167, -1137, 4947, 484, -7557, 2390, -604, 5174, -1680, -7771, 5151, -2544, 4752, -5385, -5953, 6899, 1995, -3538, -1964, -2005, -2899, -3806, -2889, -875, -6668, 2421, 7852, -4135, 3480, -2472, 1312, -372, -1592, -4654, 2972, 6772, -1416, 1550, 956, 858, -2759, 3268, -2765, -4870, -2471, -794, 679, -6719, -659, -159, -987, -247, -3032, -1714, 232, -1652, -3874, -919, -7050, -1827, -5084, -771, -4296, 3897, -3539, 3699, 7776, -7566, 1318, -3243, -2937, -3200, 4591, 5992, -2227, -1440, 112, 4378, 5404, -8718, 279, -1468, -10044, 2330, -4613, -4171, 344, 3440, 8488, -3674, 51, 1177, 2204, -716, -1666, -1899, -2359, 4873, -2739, 1130, 1508, 492, -4401, 7262, -369, -4263, -383, -833, 4751, -292, 2986, -3862, 5871, 1335, 280, 2117, -4211, -2144, -2733, 1554, 2206, -3493, -6634, 491, 3879, 2548, 1455, 4467, 1138, 2686, 3161, 16872, -5, 1346, -7243, -3078, 757, 76, 647, 3155, -7469, 5539, -4297, 2788, -2706, -824, 9735, 227, -164, 1836, -2907, -902, 3414, 9070, 448, -365, 3590, 1785, 3155, -4327, 1762, -192, 5660, -4526, -2613, -5665, 4197, -7165, 6556, -575, -2809, 9670, -1455, 3162, 5698, -2530, 6970, -1283, 2194, 3080, 5368, -2841, 1661, -3814, 734, 2233, 1298, -2275, 2558, -663, 337, -1486, 5124, -4945, -705, 2226, 3647, 3922, -1636, -3246, -1121, 5034, 6748, 1672, -7449, 4429, 7100, -2473, 7379, -947, 96, 883, -571, 5956, 2154, -4363, -5640, 483, 4663, 4230, -1531, 4186, 8916, 2290, 2685, -3635, -2636, -10375, -359, -763, 3008, 1932, -3181, 4049, -2683, -1566, 218, 1499, -4272, 8315, -5687, -3909, -10107, -2763, 49, 4835, -3659, 5096, 2762, 1572, -1215, -1102, 1778, -304, -3823, -7065, -3514, 842, 1533, 3766, 7351, 2417, -4943, 3180, -1947, 1386, -76, 3659, -998, -3692, 1470, -4130, -4735, -920, -3834, -142, -1852, 1681, 1398, -1615, -395, -5920, 1152, 2867, -8946, -1574, -4741, 2136, 2927, -3393, 1605, 1767, 624, -161, -9984, -9672, -1855, -1974, 2349, -7959, 8138, 405, 3118, -5967, -400, -2649, 1157, 5872, 3428, 3737, -1628, 1432, 319, -1607, 1023, -2374, 3938, 1798, -3673, 1438, 3258, -753, -1809, 5015, 4319, -5591, 8596, 1887, -4751, -4368, 2422, -1443, -134, -788, -21, -2064, 1963, -10361, -3825, -3084, 10016, 2496, 7829, -1263, 10488, -6681, -2736, -3243, -2854, -5366, 4789, 3023, 5010, -1605, 818, 3508, 4327, 1620, 5211, 1638, -1602, -6396, -1011, -4742, -2177, -769, -7017, -5381, 6374, -434, 5859, -1740, -3273, -1150, -272, -4498, -1411, 3119, -2595, -3171, 2275, 4851, -2317, 9149, -5869, -470, -6065, -5685, -3181, -3491, 2468, 1930, -3545, -4076, 4313, -2524, -3857, -800, -2219, 3414, 477, -968, -2669, -3937, 7518, -421, -2605, -230, -2500, 1462, -3009, 1442, 3465, -1343, -4661, 9064, -1488, 2426, 4510, 5118, -6978, -8568, -3232, -803, 1624, -3680, -2136, -3299, -5547, -4491, -6242, 1845, 5622, -710, 3020, 5498, -3608, 1922, 1233, -851, 623, 1153, 2165, -5331, 5668, -4262, 6967, 5474, -86, 3346, -2149, 1429, 1485, 4000, 2078, 1875, 5851, -3715, 4393, 1652, 1144, 5240, 728, 1415, -864, 3615, 1811, 3974, -92, 4902, -8521, -4400, -627, 675, -3433, -3801, -2291, 3850, -6717, 0, -3766, -5335, -5421, -3057, 3809, -5880, 1665, 378, 4789, 3382, -5372, 4777, -1177, 329, -4118, -724, -6930, -1720, -1816, 436, 7447, -533, 4725, -2361, -1161, -3119, 4255, 8766, -1131, 22, 1182, 3252, 4970, -3812, -5076, 971, 7043, -2200, -4456, 3164, 707, -6497, -5324, -218, 9741, -6039, -8101, 6605, 6995, 2298, -10900, -9604, 14083, -2495, 1095, 6337, 1553, 636, 2874, -2222, -2863, 3775, 4896, 8593, -1049, -760, 1582, -720, 54, -1277, -493, -2055, -4673, 2164, -5176, -8766, 3986, 538, 1980, 3639, -5559, 2434, -6174, -2313, -933, 2087, 5489, 1018, -3362, 2350, 8964, 3414, -2611, 5676, -6438, -441, 4548, -3126, 454, 4305, -6046, -1526, 8867, -2809, -3597, 4805, 2720, 5284, -3439, -4167, -1973, -6302, -2436, 693, 2798, -3159, -3125, -1843, -9666, -2709, 6212, -2448, -2614, 9744, 7912, -2084, 6710, -519, -3216, -2973, 339, -1878, 5720, 1510, 3180, 2514, -516, -6191, 8129, -1176, 2473, -1280, -5885, 1885, 2574, 3670, -3595, 5584, 2165, -6515, 5554, -23, 9021, -1911, -881, 465, -2769, -1336, 4516, 781, 1487, 826, -239, 3450, -4089, 312, 4057, -1917, -4253, 2178, 3868, 2352, -96, 3171, 1883, -4054, 7586, -11703, -329, 4425, -6981, 5046, 3208, -4103, -112, -1376, 4341, -2181, -2487, -892, -589, 271, 3055, -346, -137, 741, 2066, 6128, 2551, -4083, -6775, -1311, -4114, 1237, 3796, -616, 3564, 352, -4720, -765, -1952, -3557, 4101, -1777, 4274, 887, 295, 951, -3343, -646, 5854, 4607, -1567, -3609, -4403, 6565, -7334, 109, 1943, 2694, -3486, 2950, -515, 2109, -4209, -3735, -7865, 324, -7742, 8839, 2293, -3205, -2644, 295, 1396, 861, -2310, -6156, -1106, 802, 3566, 486, -1692, 5686, 1646, -1695, 769, 2990, 5526, -2497, -3342, -533, -3074, -5231, 5510, 936, 4001, -324, 4587, 10056, 4353, 1130, -421, 674, -6294, 1722, 2558, 4, -2187, 6847, 2125, -6077, 2690, -719, 2561, 4669, -2845, 5001, 2939, -7002, 2354, 742, 2684, -799, -4004, -5759, 2889, -4625, -6648, 1569, 735, -553, 6963, 2696, 2508, -8183, 5055, -1470, 4075, -5437, -7301, 1969, 2904, 134, -4279, 6075, -1524, 355, -3125, 10803, 1276, -1346, 3689, 794, 742, 1634, 3327, 2022, -3683, 3090, 7283, 1861, -4229, 7780, 3606, -238, -4646, 5503, -2117, -1909, 1908, 6075, -6532, -1732, 5579, 3041, -3126, 4348, 4055, 692, -753, -4153, -1657, 2367, 6320, -235, -9175, -3784, -615, 2829, 2843, -2256, -1470, -5818, -6843, -196, -151, 1301, 2017, -4884, -203, 9959, -4350, 462, 3320, 4236, 1534, -4264, 699, 1578, 3318, 4140, 4835, 1014, -440, 8480, 1889, -706, -1703, 7888, -4966, 2139, 283, -2559, -1652, -1207, 999, 5663, 3620, -9024, 1337, -331, 4966, 1586, -5856, 6659, 4837, -3025, 1162, 204, -2217, -2655, -3015, 3457, -415, -10613, 4144, 4124, -2337, 4753, -2210, 6730, 5633, -4650, 6065, 1790, 4687, 1802, 5954, 3767, 1889, 3277, 1196, -3345, -50, -582, -976, 1391, 4427, -2472, 10868, 1423, -4134, 1687, 616, -5144, 3766, 7614, -3716, -2228, 8223, -4436, -49, 4142, 6244, 2533, 1008, 3650, 3387, 2705, 228, -1405, 1866, -2994, 6573, 6639, 2522, 892, -6028, -7974, -1034, -2814, -5937, -1890, -5217, -7161, -11827, 1492, -355, 5499, -1280, 6, -5161, -3852, 2855, -353, -2529, 999, -5875, 540, 690, 2957, 2639, -5606, 3065, -912, -8014, -2138, 11664, -2999, 3785, -3479, -443, 5357, 3674, 6408, 7416, -2708, -3874, 1420, -8040, 123, -5179, -1861, -68, 2909, 2095, 398, 3777, 2569, 10516, -3511, -10, -4321, -4616, 1167, -8103, 3211, -8598, -1242, -3099, 521, 3416, -4465, 1157, -5550, -219, -164, 3618, 795, -2932, -2417, -3135, 3185, -4072, -229, -5254, -9385, -2973, 7064, 1924, 6405, -2424, 2374, 3312, 1684, 46, 2385, 788, 6867, 1158, 1092, -1723, -3498, 1711, 106, -958, -2024, -2930, 8257, 7091, -1887, -2165, -1379, -4090, 3170, -1518, -1696, -461, -95, -1146, -3041, -486, -1225, 2840, 2454, -535, 4306, 4365, 1027, -7522, 6268, -3390, 1507, -4160, 3606, 4296, 844, 6481, 5322, 845, 1058, -2461, -770, 5714, -1310, 2248, -2115, 8250, -729, -3421, 4037, -2574, -1750, 5356, -6683, -4439, -2797, -5302, -5110, 398, -3725, -2597, 2897, -2513, 1987, -416, -2444, 6916, 349, -1110, -4154, -4623, 53, 3865, -993, -8210, -651, 1280, -4261, -4337, -7605, 2074, -413, -2321, 837, -2882, -3536, 8512, -3100, -751, -1466, -1352, -3046, 833, -538, -378, -5832, -2967, 3981, -608, -274, 39, 1911, -811, 6059, 1289, 6744, -3978, -2821, 2813, 3185, 1641, 4621, -5059, 5139, -4251, 7102, 2009, 4088, 13455, 3158, 2023, 845, -2790, -6827, -7613, 2793, 362, -2562, 7864, -4174, 2552, 30, -2629, -8870, 6764, 478, -2226, 1224, 1911, 2986, -6839, 750, -4442, 43, -4298, 2500, 1377, 4444, -1386, -903, 5267, 3429, 3397, -128, -314, -1175, 557, -1281, 3879, -6261, -2378, -4673, -4546, -9533, -434, -1251, 4867, -478, 6570, 1638, -6200, 2489, 1825, -3280, 2302, 529, 808, -1079, -932, -7550, 308, 5501, -2490, -1262, -503, 2525, 5519, -1882, -1477, -86, -9414, -1875, 3709, 9345, 696, -580, -4114, 3784, -1469, -2308, -7687, 7726, -5358, 2180, 198, -4601, 6568, -846, -743, 602, 3768, -8464, -2305, 1505, 3102, -1882, 1882, 2084, -5905, 10953, 1874, 4433, -4212, 9862, 845, -1182, 2011, -3850, -3034, 1874, 4546, 4268, 481, 5882, 2178, -797, 636, 195, -2742, -6500, -172, 6924, -2807, 1402, 1809, 4814, -6196, -4112, -489, 4513, -788, -1141, -1066, 6471, -366, 3895, -7083, -2192, -936, -4171, -3834, -2427, 60, -2176, 1471, -7225, 1075, -4612, 2404, 923, -6865, 3175, -2994, 3791, 3837, 4112, -2837, -2407, -1790, -135, -2982, 756, 2905, -3754, 3142, 4695, -4753, 3775, -3668, 2878, 58, 1401, -6116, -3778, -835, -1237, 4451, -486, -5649, -2662, -1359, 2480, 764, 6716, 1520, -3423, 3565, 6528, -5598, -2577, -5838, 3809, 4273, -5191, -6151, 856, -3401, 1877, 181, -3391, 6397, 521, 2696, -729, 2447, -2357, 71, 393, -4286, -3678, -3804, 202, 2483, -1495, -567, -351, -5601, 4345, 727, 2205, -446, -1712, 4245, -555, 2319, -1229, -4391, 1198, 3343, 6352, -3041, 3530, 2555, -2491, 3267, 5197, 7241, -5418, -196, -6974, 4126, -6772, -1952, -1254, 4365, -856, -7301, 2039, -3488, -1819, -5129, -8144, 1046, 9050, -2252, 3089, 1116, -3244, 3722, -6500, -2682, 6899, 999, -6970, 4962, 1942, -155, 205, 1988, 2059, -7244, 8643, -2080, -11003, -3558, 6445, 4859, 5428, 2292, 67, -996, 6220, 3174, -276, -9762, -1324, 1566, 3728, -677, 3279, -2624, 2045, 2832, -6470, 1538, -1687, -3169, -2649, -7823, -1285, 4916, 1915, 8069, -955, 3076, 5247, 6909, -1496, 6131, -4841, 8632, 495, -755, -1478, -1746, -5553, 6564, -2779, -3504, 639, -5842, 1703, 1079, 2635, 2315, 1960, -9291, 531, -1071, -1838, -2918, -399, 2394, -8068, -720, 31, -1530, -1179, 65, -4719, 5641, -1551, 5440, -2457, 6268, -5913, 3913, -6646, 188, -6885, 2757, -3601, 3880, -3979, -1443, 1375, -2572, -1632, 2321, 5070, -2172, 731, 481, 1710, -5181, 8850, -931, -3332, 3141, -1414, -2568, -3533, 728, -1683, 206, 907, 5058, 2523, -158, -1465, 1969, -5960, -1139, -7207, 991, 2704, -8160, -2148, -4477, 4621, -5992, 2561, -2189, 5366, 2138, 2017, -2125, -844, -6806, 3850, 3987, 2856, 2990, -6767, -2315, -721, -205, -672, -2231, -617, 4268, 4988, -1234, -2918, 5121, 4651, -2067, 629, 655, 2305, 490, 990, 598, 4562, 3404, 3903, -5174, 7998, -8369, -7167, -1066, 5288, -2154, 5324, -1541, -620, -3439, -4516, 6180, -8012, -1858, 1175, -2675, -2835, -3610, -7460, 10522, 3595, -4464, 1727, 2719, -2989, -2425, 2312, 1535, -2001, -4046, 3982, -3749, -1536, 2144, -68, 284, 1545, -2459, -6920, -2683, 3627, -1356, -188, 2040, 3459, 33, 6605, -1418, 5162, 2430, -1030, 3098, };
+int32_t cls_token[16] = {1579, -8312, -1543, 5366, -5637, -2872, -787, 5773, -2441, 5560, -195, -1606, -1795, -6080, 1247, 219, };
+int32_t to_patch_embedding_layer_norm1_weight[400] = {4133, 4145, 3757, 3886, 3959, 4157, 3936, 3941, 4085, 3902, 4116, 4193, 4064, 4147, 4075, 4082, 4012, 4029, 4116, 3960, 4010, 3944, 4027, 4086, 3719, 3979, 4088, 4002, 4053, 3642, 3885, 3881, 4070, 3980, 3861, 4118, 3899, 4082, 4035, 3967, 3992, 3993, 3975, 3960, 4044, 4026, 3964, 4104, 4141, 4203, 4335, 3950, 4260, 4394, 4250, 4142, 4046, 4265, 4355, 4162, 4026, 3882, 4271, 4276, 4216, 3970, 3983, 3922, 4114, 3907, 4105, 3924, 3986, 4032, 4059, 4209, 3959, 4090, 4356, 3975, 4122, 3986, 4208, 4332, 3799, 4094, 4119, 4180, 3884, 4095, 4133, 4137, 3932, 4225, 4114, 4111, 4032, 3875, 4169, 4247, 4040, 4016, 3875, 4170, 3953, 4202, 3919, 4007, 4077, 4003, 4305, 3842, 4027, 4056, 4142, 4325, 4154, 4097, 3973, 4237, 4355, 4214, 3867, 4227, 3953, 4371, 4289, 3955, 4040, 4009, 4349, 4107, 4081, 3992, 4066, 4087, 4143, 3998, 4267, 4175, 4172, 4379, 4104, 3944, 4301, 4158, 4079, 4004, 4215, 3903, 3995, 4349, 4114, 4170, 4144, 3863, 4146, 4371, 4222, 4055, 3768, 4143, 4415, 4017, 3835, 3989, 4230, 4134, 3999, 4111, 4047, 4056, 4048, 3949, 4234, 3900, 4057, 3988, 4199, 4106, 4042, 3996, 4172, 3837, 4434, 3947, 4334, 4126, 3984, 4289, 4126, 4312, 4083, 4108, 4197, 4109, 4378, 4341, 4190, 4026, 4163, 4292, 4392, 4021, 4034, 4101, 4160, 4278, 4369, 3999, 3936, 4324, 4048, 4162, 4044, 3925, 4438, 3960, 4227, 3866, 4002, 4304, 4042, 4232, 4019, 4004, 4256, 4206, 4115, 4146, 4098, 4208, 4202, 4077, 4139, 3819, 4197, 4112, 4082, 4096, 4123, 4186, 4242, 3938, 3958, 3854, 4033, 3863, 4125, 3973, 4049, 4200, 4256, 4168, 3976, 4109, 3891, 4326, 3963, 4095, 3989, 4003, 3975, 4060, 3839, 4141, 4158, 3988, 4027, 3942, 4172, 3919, 3789, 4114, 3849, 4044, 4072, 4189, 4027, 3988, 4126, 4168, 4252, 3919, 4101, 4337, 4444, 4213, 4265, 4097, 4241, 4310, 4159, 3999, 3960, 4176, 4212, 4061, 4151, 4209, 3865, 4062, 4143, 4250, 4240, 3844, 3949, 4000, 4163, 3924, 4031, 4240, 3901, 4130, 4081, 3980, 4027, 4228, 4179, 4012, 4004, 4040, 4259, 3998, 4100, 4036, 4036, 4179, 3997, 4013, 3999, 4269, 3892, 4237, 3970, 4001, 4144, 3987, 4286, 4028, 3876, 4163, 4167, 4266, 4089, 3886, 3843, 4096, 4022, 4139, 3774, 3958, 4185, 3968, 3734, 3858, 3944, 3847, 3897, 4437, 3900, 4063, 4092, 4064, 4184, 4036, 3915, 4042, 4022, 4221, 4130, 3789, 4108, 4215, 4273, 3804, 3838, 3820, 4098, 4179, 3893, 4165, 3959, 4077, 4066, 3950, 4334, 4204, 3915, 3767, 4120, 4262, 4153, 3926, 4022, 3947, 4106, 4003, 3883, 3666, };
+int32_t to_patch_embedding_layer_norm1_bias[400] = {-181, -150, -345, -240, -156, -149, -228, -310, -125, -193, -139, -95, -144, -184, -125, -137, -225, -204, -98, -170, -13, -175, -169, -127, -341, -168, -8, -182, -261, -380, -104, -230, -161, -206, -269, -152, -96, -4, -246, -37, -138, -182, -33, -64, 9, -50, -201, 66, 108, 50, 51, -30, 117, 88, 32, 40, 5, 73, 92, 7, -126, -116, 87, 86, 78, -51, -135, 5, 48, -15, -3, -54, -132, 77, -78, 44, -12, -133, -116, -105, 60, -27, -108, -166, -119, -68, -6, -132, -102, -68, 29, 94, -23, 58, -51, -35, -61, -28, 4, -114, -232, 9, -89, 23, -29, 46, -44, -122, 78, -82, 53, -36, 47, 62, -86, 50, 35, 90, 5, -70, 69, 105, 3, 113, -38, 42, -69, 2, 131, -44, 53, -59, -18, -111, -97, -18, -91, 9, -97, -53, -121, -103, -6, 42, -30, -55, -39, -11, 121, 8, -32, -27, 20, -58, 54, -76, -13, -34, -80, 83, -37, -57, -59, -4, 42, 97, -90, -39, 19, -59, 44, -68, 115, 80, -65, 13, 54, -46, 109, -21, -47, 11, -23, 136, 56, -34, -30, -40, -29, 47, -71, -89, -16, 112, -95, -71, -114, -57, 79, -70, -81, -76, -106, -18, -53, -66, -53, -52, -116, -127, -50, -104, -70, -36, 41, -56, -110, 104, -62, 132, -40, -73, -54, -24, -21, 37, -40, -59, -3, -65, -28, -87, -69, -37, 83, 40, -38, -35, -61, 59, -59, -72, -92, 118, -4, 36, 29, 133, -64, 135, 9, -33, 69, -76, 74, -28, 52, 68, 108, 95, -77, 156, 191, 69, 130, -58, 88, 141, -12, 89, -39, 256, 158, -6, 61, -118, 75, -15, -21, 99, -115, 205, -21, 50, 121, -88, 110, -40, -19, -30, -57, 110, 140, 152, -37, -56, 123, 128, 151, 87, 53, 95, -35, 89, 98, 91, 154, 25, 83, 6, 145, 102, 99, 186, -14, 51, 39, 103, 124, 140, 114, 130, 81, 120, 157, 129, 160, 152, 169, 144, 111, 104, 51, 11, 43, 156, 74, 234, 13, 193, 130, -45, 159, -14, 102, 205, 125, 137, 43, 169, 306, 142, 87, 182, 136, 216, 166, 198, 142, 88, 233, 165, 195, 49, 192, 104, 37, 200, 17, 189, 36, 134, 192, 224, 76, 272, 170, 180, 146, 85, 130, 69, 189, 142, 163, 142, 111, 130, 251, 186, -30, 128, 149, 264, 144, 72, 200, 147, 131, 210, };
+int32_t to_patch_embedding_linear_weight[6400] = {-173, 179, -273, -237, 19, 323, 124, -8, -4, -42, 39, -70, -3, -226, 215, -34, -120, 218, -189, -275, 21, -86, 42, 92, 209, -149, 196, 180, 164, -87, 49, 54, -54, 66, -83, 102, 32, 118, 140, -60, -96, -33, -165, -97, -141, -163, 34, 208, -214, 108, 22, -126, 151, -120, -195, 88, 21, 35, 157, -22, -12, -191, 82, 89, 183, 252, 17, -22, 206, -29, 22, 57, 40, -82, -285, 98, 46, 52, -16, 165, -125, 181, -157, -105, -129, 329, -88, 193, 218, -133, -27, 85, 294, -133, -127, -40, 114, 68, 18, -162, -98, 166, -117, -18, 74, 59, 92, -40, 56, -200, 122, -163, 199, -62, -49, 106, -136, 184, 136, -64, 52, -164, -255, 115, -58, 162, 245, -40, 34, -19, -127, -342, -173, 220, -44, 171, 124, -198, -144, -127, 27, 219, 7, -176, 314, -18, -43, 69, 75, 138, -23, 118, 163, -35, 69, 100, 208, 65, 126, 149, 100, 210, -48, -106, 9, 41, 43, -3, 43, -297, -324, -96, -51, 47, 126, 5, 116, 360, -299, -36, -50, 148, -155, 242, 64, -130, 69, -48, 210, -165, 54, 142, -59, 101, -64, -264, 80, -13, -111, 223, -145, -159, 47, -87, 141, 196, 57, -183, -11, 300, -304, -50, -157, 122, 34, -19, -83, -170, 70, -41, 12, -44, -60, -122, -85, 69, 38, -107, -205, -58, -122, 100, 155, -300, -175, -11, 326, 120, 131, -174, 152, 104, -46, -72, 122, -19, -161, 138, 61, -76, -343, -88, 176, -103, 148, -188, -129, 282, 65, -34, -61, 91, 111, 38, 114, -19, 95, 50, 206, -33, -113, 81, 323, -45, -34, -164, -122, 253, 186, 102, -5, -244, 88, 181, -58, 195, -30, -18, 155, 107, -108, -267, 72, -23, 125, 65, -204, -254, -238, 96, 159, 228, 71, 13, 223, 3, -192, -176, -65, -151, -115, 213, 122, 8, -130, 66, 144, 208, 63, -140, 193, -90, 104, -189, -59, -146, -39, -185, 172, 138, -264, -217, -88, 39, 39, 42, -61, 194, 123, -57, 156, 0, -172, -132, -221, -197, -165, 80, 110, -95, 50, 52, 244, 41, -58, -107, 145, 203, 212, 204, 112, -91, 45, -22, -26, -51, 34, -152, -205, 239, -88, -122, 203, -85, -69, -43, -190, -202, -248, 7, 189, 103, 137, 133, -63, 42, -115, 68, 129, 184, -192, 176, -118, 86, -1, 90, 210, 37, -40, 135, -45, -164, -175, 70, 283, 232, -219, -81, 66, -85, -171, 40, -67, 310, 164, -66, 32, -64, -64, -52, 172, -128, -229, -156, -273, 208, -107, -196, -176, 355, 43, -19, 48, 155, 74, -145, -28, -83, -128, 15, -101, -37, -54, 103, 278, 194, 154, -161, -342, 8, -187, -34, -149, 175, -73, -153, -1, -303, -197, -180, -29, -75, 9, -157, -75, 157, -66, -130, 112, -68, -26, 10, 117, 138, -104, -189, -81, 38, 138, 149, -52, -30, 110, -93, 153, -62, -116, 189, -67, -67, -94, -94, 17, 45, 122, -158, 177, 166, 101, 105, 52, 140, -115, -7, -184, -85, -249, 98, 19, 233, -100, 198, -165, 6, -73, -183, -133, 196, -146, 231, 42, -266, 70, -104, 50, -80, 281, -171, -331, -9, 168, -98, 177, 201, -234, -103, 79, -96, 112, -38, 170, 36, -86, 201, -132, 137, -9, 34, 105, 75, -234, -69, -34, -193, 78, -236, 205, -169, 96, -48, -191, 55, -261, -52, -100, -15, -261, 24, -68, -304, -137, -296, 240, -164, 185, -182, -111, -93, 149, -194, 264, -46, -231, -16, 168, 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-426, 140, 275, 314, -190, -270, -342, -139, 95, -110, 298, -114, -93, 16, 253, 150, -110, 390, 282, 180, -162, 121, 90, -170, 72, -83, 150, -353, -119, -5, 341, -89, 100, 61, 58, 1, 58, -203, -85, -28, 174, -126, -44, -31, -18, 12, 170, -88, -354, 326, 19, -1, -223, -124, -175, -270, 43, -54, 73, -345, 90, 19, 171, -40, -251, 332, 245, 259, -14, -85, -418, -299, 125, -324, 123, -124, 475, 153, 349, 205, -154, 290, 37, 45, -230, -81, -178, -215, 335, 40, 230, -357, 310, -126, 269, 58, -334, 131, 101, 254, -141, -235, 7, -240, 30, 35, -22, -147, 183, -16, 22, -100, -138, 154, -4, -158, 46, 154, -301, -147, -85, 155, -97, -275, 68, 84, 160, 151, -319, 105, 230, -179, -41, -105, -23, -445, 463, -29, -24, -255, 53, -256, 349, -126, -481, 341, 224, 239, -322, -302, -98, -143, 170, -279, 78, -369, 124, 106, 379, -65, -202, 393, 148, -31, 25, -257, -260, -217, 80, 35, 119, 1, 191, -242, 87, 342, 19, -120, -80, 241, -29, -76, -314, 1, -125, -219, 76, -167, 65, 3, 281, 24, -17, 22, -131, 295, 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-61, 79, -128, 194, 0, -6, -196, 0, -211, 360, -179, -128, 70, 44, -158, -109, -128, -10, -144, 176, -87, 132, 0, -49, 117, -225, -240, 117, -44, -5, 145, -8, -38, -158, 99, 57, 73, 32, 112, 70, 19, -186, 16, -107, 124, -48, 2, -143, -70, 5, 105, -94, -124, 99, 129, -76, -179, -88, };
+int32_t to_patch_embedding_linear_bias[16] = {227, -68, -2, -126, -99, -174, -84, 74, -6, 99, -139, 80, -62, -140, 83, -7, };
+int32_t to_patch_embedding_layer_norm2_weight[16] = {3971, 4588, 4419, 4328, 3995, 4153, 4080, 3987, 4099, 4443, 4075, 3864, 4214, 4134, 4104, 4276, };
+int32_t to_patch_embedding_layer_norm2_bias[16] = {132, -148, 57, 34, 72, -70, -116, -26, -76, 79, -190, 10, -46, 57, -30, 204, };
+int32_t transformer_layers_0_0_norm_weight[16] = {4052, 4657, 4613, 4245, 4042, 4415, 4086, 4275, 4240, 4498, 4285, 4081, 4387, 4184, 4302, 4580, };
+int32_t transformer_layers_0_0_norm_bias[16] = {80, -54, 40, 214, -203, -129, -101, 57, -177, 57, -56, -281, -36, 219, -182, 92, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H0[64] = {-568, -962, 189, -868, -562, 692, 858, 407, -818, -814, 262, -471, 1273, 623, -384, 338, -321, -114, -723, 913, -697, 294, -35, -123, -264, -331, 509, 129, 184, 595, 16, -677, -348, 313, -401, 679, -798, 378, -145, 190, 618, -246, 776, 801, 974, 570, 842, -29, -685, 721, 640, 87, -612, -939, 890, -225, 522, 70, -514, 927, 990, 825, 114, -893, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H1[64] = {640, 166, -336, 542, 491, -1105, -458, -497, 20, -292, 989, -578, -438, 699, -855, 724, 901, 119, -824, 607, 1135, 1478, -883, -673, -923, -897, 445, 395, -782, 260, 591, 327, 970, -1386, 631, 281, -121, -721, 109, 203, 74, 106, 593, 1065, 857, -728, 761, -620, -558, 765, -514, 587, -489, -144, 839, -142, -270, 415, -757, 288, 305, 1302, -249, 247, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H2[64] = {-1419, 962, -640, 252, -124, -585, -573, 363, 218, 537, 461, 201, -502, 636, 804, -1101, 434, 91, -595, -67, -209, -257, 132, 782, -55, -268, -36, -205, -1225, 1346, 648, -933, 360, 693, -726, -675, 1319, 324, -601, -707, 234, 687, 630, 769, 323, -334, -855, 135, -410, 330, -330, 739, -812, -33, -356, -471, 689, -841, 242, -763, -1304, 937, 743, -440, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H3[64] = {-1060, 1048, 444, 53, 299, -1202, -112, -899, 1136, 226, 103, -466, 653, 104, 151, -131, -910, 333, 104, -1167, -337, -744, -291, 445, -339, -916, 64, -170, -569, 334, -1016, 803, -782, -18, 583, -961, 304, -358, 725, 244, -567, -128, -370, 950, 536, -757, 290, -506, -365, -1083, 685, -1292, 555, -640, -304, 840, 919, -707, 665, -777, 781, 909, 869, 882, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H0[64] = {339, 84, 743, 513, 937, -490, 499, -304, 1092, 299, 522, -95, -850, -672, -565, 107, -47, -401, 196, 1062, -158, -507, 736, -381, -249, 768, -185, -849, -107, 483, 520, -997, -234, -945, 1008, -44, 674, -34, -388, -817, 289, 988, -652, -446, -603, 226, 427, 582, -422, 37, 474, -103, 561, 198, 113, 520, 150, 37, -857, 1162, -361, -122, -909, 596, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H1[64] = {587, -190, 215, -264, -1101, -633, 784, 643, 562, 794, -31, 134, -75, 572, -551, 233, -162, -1081, 780, -472, -588, 170, 1040, -1217, 805, 505, -961, -23, 457, 730, -77, 117, 771, -422, -811, -611, 622, 678, 554, -690, 435, 403, -904, 91, -350, -398, -563, -750, 352, -406, -22, 667, 468, -1362, 395, -764, 132, -553, -612, 61, -284, -933, -340, -561, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H2[64] = {399, -840, -111, -768, -787, 925, 1041, 579, -842, 1107, -195, -454, -1018, -673, 330, -1015, 554, 339, 389, 461, 579, -387, -826, 465, -1171, 274, -94, 518, 899, -878, -986, 258, -406, 199, -487, -577, -1264, 1126, -283, -1205, -1311, -101, 970, 79, 183, -108, -499, 980, 122, 110, -163, -25, 767, -718, -836, -838, 839, 120, -734, 789, -324, 119, -159, -411, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H3[64] = {585, 567, -262, -561, -166, 469, 155, -56, -512, 839, -519, 859, -225, 693, -983, -707, 395, -196, -574, 63, 3, -162, -1000, -962, 248, 335, 1235, -284, 994, 727, -475, -891, -428, -817, -598, -1159, 526, 715, -232, -742, -191, -21, 65, 1479, 84, 389, 658, 385, 674, 729, 169, 221, 7, -27, 811, 841, -1080, 645, 14, -1033, -1146, -472, -74, 265, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H0[64] = {356, -364, 862, -1113, -938, 408, 1437, 968, 987, 664, -411, -881, 756, 768, -795, 77, 326, 481, -714, 196, -110, -215, 106, 621, -812, 542, 213, 1043, -188, -725, -266, -114, 785, -690, 427, 627, 1001, 796, -752, -410, -760, -304, 129, 1112, 62, 805, -1030, 382, -1195, -1002, 855, 1261, 1026, -281, 57, -850, 763, 77, 738, -135, 1189, 65, -1168, 617, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H1[64] = {536, 374, 293, 992, -103, -576, -463, -1069, -605, 1261, 597, -599, 643, -622, 268, 603, 712, 373, -455, 8, 760, -1245, -460, 201, 1035, 731, 955, 626, -131, -759, 43, -722, -817, -398, 168, 999, 474, 150, 639, -148, -359, -493, -551, 339, -737, 825, -827, -86, -681, 474, 757, -1097, -858, -351, 372, -792, -44, -609, -879, 540, 286, 701, 875, 406, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H2[64] = {764, 345, -422, -624, 1231, 99, -640, -1501, -301, -900, 283, 1233, -1172, 202, 1417, -498, 544, 858, 106, 761, 381, -695, -1310, 63, 651, -635, 946, 848, 999, 198, 84, -923, 1050, 851, -766, -870, -854, -29, 999, 47, -538, -926, -208, 448, 898, 61, -418, 1075, 429, -731, -414, -264, -538, 892, 876, 667, 311, -928, -294, 449, -854, 53, 670, -212, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H3[64] = {-944, 62, 621, 124, -535, -149, 709, 95, 1129, 832, -644, 656, 547, 233, -187, 737, -793, 821, 16, -558, 129, -235, -896, 491, 753, 42, 343, 894, -531, -820, 518, -426, -787, 3, -398, -1120, 1170, 1063, -813, -105, -78, -135, 248, -263, -351, -172, 224, -430, -1072, -956, 331, -6, -221, -602, -34, 0, 913, -859, -110, -512, 1154, 657, -630, 8, };
+int32_t transformer_layers_0_0_fn_projection_weight[256] = {-402, -1077, -244, -103, 318, -176, 766, -1187, -866, 337, 1127, 451, -280, -1007, -185, -704, 654, 854, 369, -532, 565, -666, 1063, 433, 312, 232, 211, 846, 273, 115, -969, 847, -514, 236, -588, 549, -298, 759, -253, 1035, 6, -854, -445, -1030, -204, -85, -398, -307, 785, 142, -1233, -991, 496, 512, -675, -12, 172, 11, -1111, -633, 573, 502, -201, 322, -391, 248, -499, -56, -559, -305, -527, 629, 315, 130, -98, -248, 172, 148, 36, -337, 494, 353, 696, 517, 187, -1141, 985, -1041, -1095, 86, -29, 626, -1129, 678, -357, 67, 557, 291, -223, 493, -797, -561, 1218, -793, -542, 266, 275, 229, -637, -993, 965, 673, -884, 707, -19, -635, -663, -730, 87, 528, -179, 1047, -677, 1117, -854, -716, -700, 234, -970, 807, -180, -116, 1006, -13, -1029, -40, 182, 390, -1164, -858, 584, -453, 202, -765, 821, 362, -337, -572, 40, 20, -963, 525, -390, -743, 990, -432, 156, -54, 629, 666, -252, 461, 486, -5, 762, -728, 3, -742, -741, 1112, 1431, 1199, -676, -393, 403, -522, -474, -760, 508, -904, -265, 203, 78, -1096, -852, 587, 113, -680, 171, -308, -231, -484, -210, -463, 635, -561, -1093, 140, 509, -767, -329, 120, 518, 396, 280, -194, -414, 772, -697, -104, 218, 260, -105, 210, 1339, -369, -991, 856, 977, -735, 664, 306, 405, -156, -290, -772, -732, 594, -101, 930, -1060, 1133, 977, -515, -736, -390, 1010, 118, -351, -652, 74, -553, 216, -609, 289, -209, 1004, 930, 462, 171, 755, -914, -686, -185, -616, -648, };
+int32_t transformer_layers_0_0_fn_projection_bias[16] = {-840, -92, -107, 118, 323, -361, 278, -5, 135, 300, -784, 540, -15, 380, 771, 648, };
+int32_t transformer_layers_0_1_norm_weight[16] = {3913, 4457, 4086, 4198, 3935, 4065, 4044, 3934, 3956, 3983, 4205, 3852, 4319, 4076, 4119, 3967, };
+int32_t transformer_layers_0_1_norm_bias[16] = {-176, -178, -255, 86, 151, -163, -161, -8, 155, -133, -118, 180, -206, 30, -113, -222, };
+int32_t transformer_layers_0_1_fn_ff1_weight[64] = {-269, 879, 417, 125, -1042, 562, 825, 151, -22, 941, 340, 837, -99, -941, -81, -34, 779, -802, -170, 98, -331, -642, 898, 694, -266, 574, -677, 748, -770, -37, 501, -738, 539, -756, 846, -539, 380, 724, -628, 795, 1144, 372, 525, 499, -257, -2, -298, -356, -821, -8, 829, 852, 205, 290, -229, 201, -910, -991, -340, 841, -610, 961, 227, 151, };
+int32_t transformer_layers_0_1_fn_ff1_bias[4] = {-143, -827, -308, 129, };
+int32_t transformer_layers_0_1_fn_ff2_weight[64] = {305, -252, 1555, 1351, -1680, 1389, 1229, -741, -1475, 285, -203, -1095, -1407, -1403, -1965, 1256, -273, -533, -1, -1734, -417, 176, -253, 1055, -326, -525, -1, 343, -413, 309, -1034, -1608, -1219, -547, -472, -663, -1628, -1026, -56, -1330, 673, 451, -900, -1720, 2030, 607, 1103, -1915, 1853, 911, -939, 398, 21, 15, 1670, -409, 378, -1568, 1405, 1371, 933, -759, 545, -2014, };
+int32_t transformer_layers_0_1_fn_ff2_bias[16] = {837, -1010, 736, 2060, 1857, -1132, 728, -1052, 947, 1603, 1612, 1908, 1519, 508, -1745, -1202, };
+int32_t transformer_layers_1_0_norm_weight[16] = {3943, 4401, 4285, 4286, 4112, 4059, 4094, 4023, 4156, 4435, 4079, 4136, 4219, 4111, 4081, 4076, };
+int32_t transformer_layers_1_0_norm_bias[16] = {-44, -53, 85, 19, -34, -44, 71, -39, 40, 66, -63, 14, 27, -106, -87, -76, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H0[64] = {495, 600, -127, -357, 489, 355, 41, 97, 758, -317, 99, -403, 730, 452, -27, 354, -495, 997, 387, -732, -742, 475, 67, -193, 464, 305, -691, 995, 902, 1007, -985, -300, -608, 939, -555, 527, 454, -789, 77, 203, 550, 130, 912, 756, 104, 733, -477, -462, -25, 816, -253, -828, -407, 607, -1024, 458, -159, -75, -422, -327, 772, -845, 661, 673, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H1[64] = {-780, -895, 1016, -316, 1036, -767, 839, -289, -582, -1437, 46, -283, -830, 69, 661, 720, 925, -302, -908, -185, -771, 486, 460, -953, 327, -491, -209, -21, 210, -935, -445, 117, 541, -967, 810, -458, -985, -328, -38, 647, 456, 982, -64, -586, -155, 738, -358, 85, -536, 5, -210, 168, -628, 278, -280, 13, -793, 687, 18, -27, -340, 178, 258, -977, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H2[64] = {-397, -371, 571, 275, -30, 516, 642, 475, 831, 781, -398, -383, -510, 210, -543, 47, -637, 293, 625, -645, 40, -892, -734, 402, -172, -431, 7, -150, -549, 512, -208, 249, -527, -433, 922, 769, -788, -851, 328, 370, -51, 214, -971, -639, -809, 119, 54, 694, 746, -331, -515, 64, -894, 340, -713, -372, 540, -418, 924, 572, 1071, 882, 877, -633, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H3[64] = {476, -152, -876, 172, -361, -748, -636, -123, 162, -616, -504, 793, 661, 27, 626, 102, -518, 900, 891, -508, -848, -553, 519, 101, 122, -683, -204, 986, 44, 263, 421, -1069, 811, -302, 909, 942, 864, 478, -225, -1105, -470, 4, 387, 537, 133, 434, -6, -780, 301, 739, 1092, -834, -1072, 173, 106, 480, 981, -1, -672, 1039, -32, -769, -809, -673, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H0[64] = {-536, -105, 457, -372, -36, -789, 776, -669, 705, -386, -480, -493, -216, 652, -161, -285, 385, 1026, -222, 268, -761, -564, 815, 991, -417, -308, 967, -141, 950, -843, -774, 222, -9, -387, 466, 539, -385, 108, 569, 873, 607, 184, -627, -371, 92, 143, 355, 885, 141, 339, 397, 598, -574, 500, 226, 716, 449, 328, 820, -210, 614, -841, -650, -881, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H1[64] = {487, 12, -424, -75, 464, 210, 601, -479, 874, -114, 421, 630, 621, 563, 671, -886, 856, -783, 351, 676, 1263, -231, 1, -862, 609, 307, -259, -737, 649, -552, 811, -851, 764, -42, -780, -1011, -595, 521, -447, -604, -581, 286, -718, 184, -32, 81, -644, 927, -789, -145, 864, 638, -400, 675, -935, -786, 1144, -920, -702, 755, -341, -782, -596, 566, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H2[64] = {339, 539, 363, -56, -218, 918, 616, -856, -651, 992, -167, 175, 652, -456, -927, 539, -234, -846, -502, 924, 457, -677, -48, 41, -224, 685, -994, -17, -373, 766, 1014, -845, 509, -554, -878, 187, 824, 437, 871, 410, 1037, 18, 459, -666, 496, 360, -294, 407, 245, 266, -455, -167, -1086, -133, -739, 1113, 462, -910, 764, 1087, 238, -358, -725, -713, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H3[64] = {-909, -289, 660, -80, -802, 331, 600, 430, -889, 182, 205, -1121, 799, 211, 337, -537, 1094, -867, 396, 415, 806, 787, 683, 530, 240, -442, 73, -203, 433, 326, 802, 184, 1048, 362, 49, -755, 903, 970, 491, -289, -807, -123, -625, -826, -348, -711, 943, -872, 369, 459, -610, -780, -902, 865, -479, 952, 251, 723, 10, 137, 110, 432, 545, 827, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H0[64] = {-904, -972, 395, -281, 1346, 1215, 17, -994, -340, 936, -382, -125, -644, -779, -546, 815, 142, 820, 98, 552, -377, 959, 1113, 123, -221, -107, -964, -219, 206, 648, 834, -596, -35, 431, 658, 398, -1069, -140, -465, -39, 455, 824, -75, 420, -270, -55, 619, -394, -685, 548, 194, -23, 38, 815, -786, 474, 684, 318, -763, 593, -655, -618, -263, 251, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H1[64] = {550, 404, -867, -355, 1129, -344, -759, 403, 203, 811, 891, 674, 433, 812, 428, 68, -321, 344, -725, 560, 425, 801, 653, -328, 60, 269, 427, -15, -159, 367, 235, -599, 8, -1167, -239, -594, -544, 871, 675, 78, 607, 621, -244, -492, 415, 668, 1004, -170, 961, -1137, -717, 1007, 228, -242, 508, 511, -703, 429, 800, 807, 826, -723, 855, 790, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H2[64] = {137, -567, -524, -1077, -226, -320, -619, -639, -215, 351, 297, -193, 280, -282, 92, 700, 987, -271, 103, -408, 138, -763, -252, -592, 890, 463, 961, -740, -487, 323, 233, -639, -752, -186, 124, -984, -70, 996, 194, 663, 72, 109, 382, -590, 948, 98, -885, -1018, -411, -896, 847, 478, 16, 0, -861, 876, -875, -176, -784, 30, -797, -803, -906, 896, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H3[64] = {523, -54, 650, 319, 905, -162, 443, -845, -509, 320, -1008, -984, -99, 709, -64, -938, 175, -357, -351, 40, 777, 340, 1157, -867, -689, 733, 553, -237, 721, -1006, -476, -684, -446, -31, -974, 214, 469, -240, -1137, -233, 285, 528, 266, -798, 538, 786, 438, -717, 586, -872, -901, 1040, 137, -19, 215, -995, -446, -870, 675, 139, 103, -691, -115, -573, };
+int32_t transformer_layers_1_0_fn_projection_weight[256] = {-961, -497, -218, -462, -752, 764, 182, -416, 43, -295, -1317, -752, 990, 758, 595, 383, -297, 299, -272, -565, -953, -338, -303, 1186, 1256, 504, -455, 329, 353, -416, 202, 446, -869, 19, -776, -409, 959, 382, -5, 278, 503, 440, 209, 407, 410, 406, -331, 877, 463, 721, 65, -135, 293, -336, 674, -687, -1054, -331, -225, -675, -963, 710, 728, 790, -392, 108, -834, 300, -154, 767, 401, 421, -820, 246, -236, -957, 669, 358, 483, 60, 249, 66, 1149, -828, -539, 332, 57, -1235, 282, 268, 978, 216, -830, -553, -541, 279, -214, -340, 977, -249, 205, 70, -401, -502, 17, 1231, 634, 390, -937, 15, -798, -473, 50, -277, -825, 504, 79, 163, -647, -875, -860, 161, -256, -936, 594, -491, -403, -47, 643, 316, -778, 1075, -1066, -1276, -590, -713, 888, 114, 749, -78, -257, 103, -363, 247, -128, 40, 1004, 152, 639, 171, -485, -1083, 70, 342, 903, 569, -606, 472, -894, -585, -682, 488, -726, 169, 16, -905, -906, -734, 796, 697, -527, 807, -1091, -911, -320, -791, 718, 622, 475, -343, 853, 769, 884, 564, -1171, -59, 180, 14, 288, -1012, 1087, -518, -549, 777, 576, 765, -356, 945, 640, -174, 238, 281, -341, -889, 1007, 311, 40, -45, 633, -584, 1091, -101, -801, -483, -527, 411, 164, 457, 365, 19, 209, -542, 114, 352, -625, 590, 666, -706, 1037, -388, -993, -373, 240, -343, -914, 856, 956, 617, 982, -140, 371, -455, 208, 973, 133, 652, -646, 344, 297, -880, -97, 271, -380, -219, 827, 596, };
+int32_t transformer_layers_1_0_fn_projection_bias[16] = {-736, 309, -43, -180, -220, -446, 37, 54, 389, -788, 1114, -969, -17, 10, 286, 852, };
+int32_t transformer_layers_1_1_norm_weight[16] = {4083, 4051, 4008, 4127, 3974, 3860, 4095, 4052, 3996, 4005, 4114, 4195, 3983, 4097, 4071, 4004, };
+int32_t transformer_layers_1_1_norm_bias[16] = {137, -2, 135, 87, 127, -139, -134, -96, 67, 14, -108, -63, -78, 31, 15, 53, };
+int32_t transformer_layers_1_1_fn_ff1_weight[64] = {-127, -843, -176, -862, -255, -382, -561, 758, -943, -676, -585, -721, -737, -526, -519, -110, 481, 81, -122, -888, 358, 455, 170, 527, 336, 86, 266, 133, 896, 362, 806, -114, -894, -490, -7, 55, -544, 938, 456, -382, 987, -919, 127, 210, 427, -677, 788, -316, 776, -675, 152, 89, -813, -174, -14, 274, 317, -26, 399, -560, -367, -255, 649, -1004, };
+int32_t transformer_layers_1_1_fn_ff1_bias[4] = {90, -953, 421, -933, };
+int32_t transformer_layers_1_1_fn_ff2_weight[64] = {-1042, -1584, 1737, 504, -1780, 1348, 536, -1647, -1350, 839, -1377, 663, 455, -1985, -1640, 1642, 1730, -960, -1286, -54, -1541, 714, 971, 579, -69, 1795, -831, -1040, 1600, -382, -1386, 245, 1170, 1367, -210, 904, 1794, -1331, -524, -1304, 84, 743, 593, -621, -1397, -1482, 1047, -849, -1283, -1557, 911, 218, -1263, -1694, 1757, 1760, 812, 762, 1568, 1882, -1391, 1405, -244, 478, };
+int32_t transformer_layers_1_1_fn_ff2_bias[16] = {-1109, -350, -895, 2006, 686, -472, 1124, 1903, 1174, -405, -1500, -440, -422, -142, 1269, -836, };
+int32_t transformer_layers_2_0_norm_weight[16] = {4135, 4645, 4316, 4215, 4243, 4415, 4186, 4002, 4224, 4214, 4305, 4162, 4319, 4117, 4437, 4432, };
+int32_t transformer_layers_2_0_norm_bias[16] = {-10, -219, 118, -51, 66, -61, 16, 57, 4, 67, 27, 112, 24, -177, -70, 114, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H0[64] = {750, 642, 712, 102, -275, -314, 514, -1305, 48, 907, 72, -639, -859, -1227, -96, 131, -174, 771, 585, -694, 1109, -192, -60, -1356, 95, -133, -539, -295, -1002, 421, -649, 590, 403, 1025, -703, 311, 867, 275, -77, -759, 624, -841, -753, -297, -807, 129, 827, -804, -772, 63, 894, -59, -512, -206, 425, 657, 431, -1100, -646, 1259, -1036, -1045, 252, 1058, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H1[64] = {-101, 525, -497, -703, 267, -890, -574, 202, 304, -567, 1090, -181, -37, -245, -262, 545, -260, 686, -634, -882, 1059, -247, -562, -1061, -944, -143, 1018, -218, -608, -752, -127, 623, 467, -1114, -92, -355, -635, 947, 626, 710, -41, -864, -216, 275, -567, 834, -282, -558, -925, 848, 565, -826, 129, -724, 323, -1025, 681, 725, -81, -38, -463, -653, 1066, -210, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H2[64] = {-1000, -805, 417, -430, -467, 482, -643, 174, 646, -165, -599, 93, 65, -1101, 230, 546, -172, -758, -61, -837, 974, 408, -104, -727, -296, -456, -186, -148, -786, 216, -490, -825, 362, 932, -340, 816, 142, 20, -125, -1072, 390, -69, -839, 806, 830, -740, -407, -804, 1087, 182, 602, -206, -283, -331, -868, 454, 758, -753, -277, 266, -147, 297, -885, -669, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H3[64] = {890, -862, -125, -582, -1112, -1234, 52, -854, -742, -485, 26, -1324, 767, -304, 274, 490, 285, -878, -741, -904, -46, 536, -1020, -689, 33, 434, 481, -13, 67, -67, -28, 798, 162, 915, -629, 766, -1016, -907, 705, -1195, 1089, 399, -878, -55, -212, -838, -19, -777, 207, -357, -446, 28, 210, -1012, 500, 196, -409, 121, 470, 957, 885, -742, -227, 284, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H0[64] = {196, -857, -988, -250, 851, 1125, 256, 246, -13, -115, 43, 444, -62, 5, 196, 922, 603, 803, 7, -895, 225, 886, -688, 262, -355, -427, 167, 47, -220, -688, 373, -63, 36, 672, 524, -170, 675, 562, -1017, 662, -648, -36, -1136, 523, -305, 50, 303, 147, 246, -676, -142, 524, 327, 584, -688, -1043, 1089, -277, 414, -934, 798, 883, 1051, -572, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H1[64] = {893, 528, -509, -849, 255, -684, -717, 423, 113, -646, -210, -702, -66, 1028, -1014, -219, -40, -803, -291, 773, -187, 46, 954, 809, -872, 516, 833, -855, -848, 835, -481, 54, -295, 326, 904, 732, 338, 604, 78, -733, 129, 699, 498, 835, -949, 376, -955, -820, -618, 1033, 981, -643, 906, -534, -1152, 65, -322, 66, -274, 926, -558, -402, -926, -78, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H2[64] = {1036, 778, -513, 648, 42, 482, -147, 968, 12, -521, -380, 241, 982, 639, -959, -558, -511, 941, 56, -425, -745, 546, -937, 670, 819, -652, 739, -106, -552, -691, 445, -287, 30, -36, -715, -196, 884, -637, 0, 586, -230, 692, -169, -1036, 9, 548, 426, 797, 300, -356, -648, -432, 1287, -533, -110, -604, 835, 396, 466, -484, -443, 443, 421, -29, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H3[64] = {-1028, -82, 553, 856, -861, -129, 600, -637, 300, -239, 141, -296, 443, 358, 949, 498, -736, 977, 339, 225, -1016, -994, 330, -1120, 1007, 178, -78, 1380, -459, -932, 620, -454, -671, -885, -617, -1051, 1021, -378, 542, 1186, 512, 608, -809, 418, 153, -173, -46, -342, -1247, -413, 461, -858, 482, -234, 593, 168, -638, -919, -2, -734, -703, -717, 275, 1043, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H0[64] = {-569, -735, 276, 102, -180, 537, -520, 1212, 789, -363, 25, -565, 952, 177, 147, -941, -448, -1023, 433, -198, 197, 686, 450, 217, 498, 850, 455, -791, 992, 707, 544, -393, 914, 631, -407, -221, 131, 614, 619, 430, 710, -753, -270, 347, 115, 834, 648, -138, -386, -1090, -122, 758, 753, 488, -639, 843, 35, 193, -708, 1173, -499, -677, -894, -551, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H1[64] = {189, 384, -576, 584, 707, -516, -1085, 81, -652, 809, 849, 929, -834, 725, 256, -568, -77, 932, 4, 445, -174, -238, -718, -991, 539, -472, -577, -951, -1016, 229, 73, 838, 980, -710, -18, 111, -583, 916, 1046, -814, 551, 95, 777, -46, 975, 27, 252, 362, -772, -863, -803, 496, 855, 100, -481, 357, 577, 945, 630, 44, 712, -157, -147, 1142, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H2[64] = {668, -279, 884, 126, -1152, -408, 994, -84, 549, -356, -363, -365, 596, -513, 305, -212, 175, 181, -1146, -1, 588, 511, 147, 231, -751, -28, 129, 877, 385, 904, -362, -628, -290, -366, -1028, -102, 909, -942, 1006, 653, 454, -908, 1069, -462, 1201, -227, -847, -775, -1091, 75, -924, 178, 87, 519, 431, 287, -411, 100, 605, -926, 593, -438, -588, 618, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H3[64] = {496, 644, 748, 90, 519, 492, 816, -402, -44, -1013, -886, -581, 880, 744, -302, 821, -992, 729, -44, -493, -1191, -137, 352, 950, 342, -211, 347, -1036, 125, -31, 912, 313, -1230, 354, 356, -195, 220, -693, -1152, 538, 1248, -1006, 152, -822, -541, -813, 12, -269, -863, -739, -438, -650, -250, 770, 240, 195, -813, 411, 597, 1034, -114, -202, 777, -162, };
+int32_t transformer_layers_2_0_fn_projection_weight[256] = {-250, -616, -353, -787, 606, 329, 1043, 644, 827, -65, 841, 68, -804, -131, 515, 298, 594, 611, 284, -40, -72, -695, 564, -25, -141, -9, -936, 100, 318, 1101, -899, -442, 755, -919, -439, 111, -58, -1232, 34, 191, -666, 651, -416, -578, -160, -1101, 927, 786, -1151, 834, -830, 143, -180, 381, -887, 812, 755, -287, -1322, 98, 629, 499, 917, 957, 261, 509, -1001, -522, -102, -106, -48, -816, -161, -516, 345, 373, -881, 1022, -493, 648, 1124, -152, -542, -293, -708, -46, 779, -106, -1112, 1022, -634, 145, 401, -1117, -374, 775, -378, -672, 956, -497, 798, -1060, 359, -1384, -853, 802, 1090, -431, -391, -659, -931, 348, 565, 363, 395, -576, -696, 206, 157, 741, 253, -57, 848, -844, -828, -758, 621, -122, -565, 1162, 834, -754, -840, -883, 464, -1167, -816, 670, 613, 272, -459, -529, -585, -854, -559, 925, 240, 1169, -413, -69, -1001, 513, 571, -426, 359, 319, 612, -510, -580, -707, 391, 896, 354, -1138, 922, 943, 115, -252, 36, 225, -326, 598, -232, 828, -678, 621, 582, 930, -1020, 375, -504, -157, -669, -629, 577, -491, 312, 701, -909, -779, -159, 95, -738, 806, 1109, 64, -398, -15, 1345, -1061, -833, 827, 756, -223, 460, -359, -417, -114, 719, -1035, -180, -515, 124, 428, -975, 993, 533, -1178, 966, -308, 575, -908, -113, -656, -439, -547, -542, -343, 1116, -219, -704, 32, -184, -1065, -794, 784, 247, -762, -59, 35, -98, 387, 100, 593, 748, 564, 413, 453, -306, -254, 7, -255, -889, 814, -766, -481, };
+int32_t transformer_layers_2_0_fn_projection_bias[16] = {194, 93, 543, 448, -911, -445, 195, -40, 634, 876, 754, -1012, 50, 857, -446, -108, };
+int32_t transformer_layers_2_1_norm_weight[16] = {4070, 4054, 4113, 4250, 4054, 4081, 4083, 4181, 3917, 4167, 4225, 4116, 4074, 4125, 4118, 4086, };
+int32_t transformer_layers_2_1_norm_bias[16] = {42, 64, -32, 110, 137, -170, 140, 80, -43, -16, 168, -178, 100, 6, 44, -66, };
+int32_t transformer_layers_2_1_fn_ff1_weight[64] = {-874, -1079, -163, 736, -294, -562, -500, 987, 108, 568, -363, -934, -409, -573, -1048, -366, 277, -902, 259, 602, -45, 983, 366, 811, -394, -751, -662, -964, -400, -240, -967, -749, 166, 599, -648, -608, 618, 609, -928, -602, 56, -852, -818, -343, -398, 671, 187, 523, 906, -568, 602, 1123, 788, 123, 297, 817, -692, -732, -585, 704, 1029, 787, -902, 971, };
+int32_t transformer_layers_2_1_fn_ff1_bias[4] = {267, 470, -574, -399, };
+int32_t transformer_layers_2_1_fn_ff2_weight[64] = {1877, 1625, -992, -1629, -1178, -1784, 4, -1248, 905, 507, 1721, -4, 1659, 420, -527, 1624, -482, 1213, -223, 1858, -200, -1466, -160, 330, 1406, 396, -1566, 1945, -1635, 733, -1490, -1626, 404, -1409, -268, 1645, 1503, 1635, -1849, 1682, -1379, 1453, -465, 666, 593, -578, 1630, -747, -1665, -1625, 436, -1834, -1397, 1706, -1779, 42, -96, -1266, -1052, 1321, -1843, 128, -1722, 1636, };
+int32_t transformer_layers_2_1_fn_ff2_bias[16] = {-473, -1167, 1703, 46, 113, 609, -1347, 396, -303, -1647, -449, -372, 176, -1396, 1388, -966, };
+int32_t transformer_layers_3_0_norm_weight[16] = {4331, 4371, 4459, 4169, 4329, 4301, 4145, 4299, 4294, 4423, 4268, 4098, 4104, 4173, 4155, 3944, };
+int32_t transformer_layers_3_0_norm_bias[16] = {-9, -50, -35, -36, 149, -24, -70, 75, 0, 43, 35, -47, -72, 36, 13, 91, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H0[64] = {812, -991, -1033, 164, -795, 579, -348, 766, 1070, 162, 149, -447, 298, -560, 489, -455, -458, 1003, 28, 1178, -74, 572, 1063, -531, 288, -656, 52, -852, 268, -340, 554, 363, -261, 534, -24, -513, -736, 186, -265, -656, -131, -1131, 917, -628, -624, -829, 190, 508, -405, 31, 991, -533, 728, 1148, 761, -174, -792, -169, 356, 52, 950, 90, -723, 659, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H1[64] = {417, 44, -833, 344, 124, 505, 217, 114, -753, -223, 59, 506, 404, 796, 326, -824, 45, -937, -647, -1044, 367, 197, -42, 101, 914, -45, 768, 244, 988, 114, 388, 165, 502, -169, 880, 852, -46, -1099, -445, 420, 903, 508, 945, -334, 729, -605, 8, -69, 950, 0, 277, 227, -321, -251, 636, 393, 441, 75, 269, -270, -713, 662, -916, -227, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H2[64] = {-625, -372, 134, 911, -887, 1167, -760, 713, -72, 576, 108, -1107, -353, -550, 605, -319, -229, 136, 335, 688, 221, -610, 366, 98, -380, -125, -61, -205, -432, 389, 110, 286, 1046, 550, -314, -243, 626, -699, -397, -950, 806, 553, -298, -1018, 713, 74, 860, 746, 348, -952, -293, 440, 797, -396, -340, -810, 182, 1001, 47, 626, 734, 45, -284, -563, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H3[64] = {1082, 533, -719, 574, 747, -378, 72, -655, 244, -372, -790, -465, -449, -305, 970, 536, 218, -626, 396, -1083, -413, -840, 679, -186, -650, 865, 721, -883, 882, -1084, 614, -783, -846, 623, 94, 490, 1052, -340, -1226, -483, -16, -382, 717, 491, -780, -723, -848, -613, 345, 648, -319, -34, -72, -347, 989, -457, 377, -805, -29, 734, 973, 791, 861, -764, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H0[64] = {-521, 858, 454, -495, 916, 442, -168, 604, 411, -89, 999, 1, -96, 421, 95, 197, -129, -822, 103, 866, -480, 714, -342, 656, -813, -974, 231, -1000, 783, -582, -154, -1051, -942, -760, 788, -81, -396, -102, 270, 72, 1116, -755, -832, 101, 1, -476, 195, 308, -144, -1003, -811, 813, -853, 1089, -738, -198, -100, 252, 935, 526, 115, 513, 18, 735, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H1[64] = {-918, -29, 832, 896, -778, 564, -148, 730, -237, 85, 834, 823, -836, 820, 575, 638, 661, 140, -132, 629, -1014, 82, -486, -571, 994, -457, 1027, 346, 445, -634, -202, 487, 587, 25, 580, 854, -154, -265, -46, 733, 728, 507, -780, -448, -367, -229, 937, 305, 293, -1028, 445, -37, -608, -867, 512, 240, 230, -243, -412, -676, 930, 645, -19, -602, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H2[64] = {-77, -1040, 122, 316, -714, 687, -1048, -1038, 982, -600, -161, 541, -937, -978, 541, 656, 134, -443, -314, -18, 239, 44, 138, -596, -403, 588, 715, 958, 812, -651, -300, 441, -765, 319, -127, -1081, 385, -228, -45, -405, 134, -655, 949, -141, -850, 513, -829, 466, -601, -76, 280, 217, 155, -150, 1085, 409, -572, 165, 818, 548, -504, -663, -25, -151, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H3[64] = {-822, -987, 500, 498, -380, 118, 296, -875, -428, 525, 721, -948, -96, -220, 952, -534, -1220, -182, -802, -290, 53, 825, -687, -910, 930, -42, -265, -297, 1184, -688, -121, -414, 524, -856, -476, 496, 631, 134, 1193, -132, 486, -166, 691, 1058, 274, -1097, -921, 388, 993, -9, -933, 525, -20, -405, -604, -828, 207, -280, -1049, 406, 872, -153, 134, -7, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H0[64] = {883, 284, 1094, -584, -1043, 1291, -1017, 538, 1181, -826, 537, -743, 1056, -1051, 1065, -347, 947, -152, -36, -529, -394, -532, 143, -447, 819, 768, 375, -626, 107, 1032, -154, 691, 845, 1047, -224, 931, 1173, -396, -983, -455, 16, -1076, -83, 121, -988, 816, -291, 72, -1167, -783, 823, -605, 196, -86, -857, 738, -495, 625, -374, -571, 128, -985, 844, 796, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H1[64] = {-121, -695, 45, -12, 29, 145, 226, 781, -515, 970, 780, 1133, -311, -960, 447, 445, 896, -274, 519, -1066, -274, -909, 923, 193, 246, 733, -661, 1113, -95, -1037, -874, -375, 807, -375, 333, -1144, 290, -112, -464, 1003, -578, -207, 751, 1000, 582, -342, 641, 775, -672, 604, -283, 834, 8, -312, -856, -454, 326, -226, -11, -959, 70, 1098, -225, -777, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H2[64] = {800, -780, 659, 436, 608, 983, -692, -810, 1055, 209, -284, 989, 203, -579, -376, 84, -312, -39, 309, 272, -631, -387, 500, -413, 866, 99, 322, -723, -751, 811, 635, 257, -571, 521, 454, -915, 239, -332, 381, -897, 1141, 265, 813, 83, 105, 243, -431, -597, -886, -987, -1014, -252, -271, -94, -218, -324, -948, 846, 376, -282, -851, 724, -920, 601, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H3[64] = {-539, 136, 319, -1137, 523, -281, -164, 890, -243, -237, -195, 331, 203, 862, -165, 188, 480, -509, 632, -963, 98, -30, -1019, 1024, -732, -486, -843, -480, -458, -729, 528, 728, -402, -495, -697, 1208, 689, -417, 308, -1250, 809, -878, 772, -534, 648, -420, -677, -614, 230, 167, -953, 828, -357, 801, 752, 1045, -868, 305, 622, 1084, -482, 809, 990, 825, };
+int32_t transformer_layers_3_0_fn_projection_weight[256] = {342, 5, -248, -706, 551, -1138, -335, -803, -1059, -259, 550, -227, -212, -948, 336, -347, 724, 0, -258, -610, 104, 853, -1145, 801, 45, -122, -296, -960, 979, -164, 227, -633, 291, -29, 331, -570, -899, 539, 166, -885, 666, -86, 227, -209, 44, -1134, 439, 556, 428, -932, 165, 517, 13, 135, -735, 917, 412, 6, -317, -426, 450, 310, 11, 70, -476, -749, -107, 792, -254, 818, -650, 707, -400, 687, 222, 431, -284, -826, 120, 150, -819, -614, -974, -859, 345, 367, -32, -770, -762, 372, 1068, 352, -201, 500, 166, -592, 665, -217, 231, 366, 564, 47, -268, -925, 1011, -851, 371, 688, -1137, 740, 918, -1041, 971, 42, 914, -1073, -248, 73, 271, -1088, 335, 392, -633, 626, 233, 825, 398, -790, 157, 1155, 441, -655, 356, -920, 699, -145, -525, 955, 180, -23, 97, 817, -420, -964, 1096, -19, -195, -12, 843, 359, -504, 273, 655, -269, 438, 373, -546, -25, 663, -717, -136, -276, 938, 78, -921, -687, 740, -459, -1038, -826, 965, -535, 352, 804, 894, 293, -451, 707, 613, 768, -1007, -1111, 410, -671, -224, 418, 773, 388, -242, -517, 908, 3, -794, 179, -520, 518, -565, -638, -300, 55, 888, 790, 754, -689, -561, 358, 723, -21, -528, 557, 1065, -476, -312, -544, -658, 803, -328, -464, -309, -778, -558, 298, 299, 445, -143, 526, 1111, -49, -762, -721, -224, -158, 529, 1242, -545, -287, -974, -391, 603, 743, -589, -1132, 55, 661, 757, 273, -1212, 1374, 396, -276, -975, -866, -192, -78, 168, -164, };
+int32_t transformer_layers_3_0_fn_projection_bias[16] = {-513, 807, 27, 109, 381, 633, 651, -345, -188, -948, -40, -1119, 69, -344, 610, -562, };
+int32_t transformer_layers_3_1_norm_weight[16] = {4014, 4033, 3946, 3968, 4029, 3985, 4117, 4068, 4052, 4005, 4190, 4268, 4082, 4047, 4155, 3996, };
+int32_t transformer_layers_3_1_norm_bias[16] = {114, -8, 39, -134, -76, -28, -5, -45, -16, 95, 69, -148, 162, 32, 143, -74, };
+int32_t transformer_layers_3_1_fn_ff1_weight[64] = {45, -294, -338, -514, 405, -861, -371, 974, 831, 195, -815, 159, -8, -783, 753, 635, -125, 722, 314, 472, -678, 633, 911, -906, 948, -593, -502, 602, 482, 1182, 18, -479, -804, 954, 458, 242, -300, 779, -731, 989, 108, -1102, -456, -82, 914, -716, 923, 673, -451, 517, -480, -898, -279, 521, -213, 1045, -1039, 728, -1044, -504, 824, -374, -136, 480, };
+int32_t transformer_layers_3_1_fn_ff1_bias[4] = {420, -528, 708, 556, };
+int32_t transformer_layers_3_1_fn_ff2_weight[64] = {-1264, -245, -243, -1258, -1099, -1898, -832, -1786, -91, -535, 338, 531, 99, 47, 1132, -293, 1776, -1641, 1705, -1170, 1156, 1020, -187, -1538, -652, 147, -962, -721, 748, -398, -1670, -84, 1373, 389, -1031, -329, 520, -615, -769, 1458, 1650, 1183, 1178, -137, -775, -271, -1281, -1755, 1191, -1755, -561, -1893, -104, 833, 1300, 1269, 1925, 1248, -225, 316, 1618, -1789, 479, -958, };
+int32_t transformer_layers_3_1_fn_ff2_bias[16] = {170, -517, 322, 1989, -502, 37, -357, 766, 1958, -45, 1673, -1260, 1175, -1481, -1355, 818, };
+int32_t mlp_head_layer_norm_weight[16] = {4039, 4009, 3972, 4135, 3957, 4168, 4133, 4187, 4009, 4196, 4210, 4267, 4051, 4053, 4018, 3976, };
+int32_t mlp_head_layer_norm_bias[16] = {-17, 24, 34, 16, -13, -23, -17, 16, 1, -62, 29, -4, 6, 46, 47, -28, };
+int32_t mlp_head_linear_weight[256] = {-400, 764, -464, -564, 75, -317, 351, -609, -341, -736, 55, 467, -747, 464, -536, 11, -341, 380, 479, -292, 53, 351, -332, 245, 155, -579, 630, 827, 727, 483, -86, 108, 213, 752, -431, 437, 649, -37, 685, 776, 793, -899, 934, 175, 432, -808, -868, 652, 337, 186, -967, -417, 839, -193, -764, 361, -577, 497, 103, 29, 709, 472, 390, -606, -656, -616, -69, -770, 191, -494, 187, 355, 687, -821, -806, 283, 407, -555, -704, -244, 293, -970, -991, 380, 67, 390, 291, 35, 677, 337, -688, -817, 332, 688, 115, -779, 759, 534, 1055, 544, -116, -636, -247, -774, -784, -208, -659, 704, 557, 19, -829, 373, -758, -1026, -1167, 763, 885, -721, -593, -330, 864, 108, -561, 49, 217, -543, 154, -191, 121, -393, 365, 39, 803, 558, -218, 55, 207, 304, -657, -35, -421, 416, 483, 446, 703, 943, 692, -200, -8, 13, 895, -533, 740, -906, -911, -388, 582, -75, -1053, 767, 540, -323, 452, -414, -781, 723, 942, 1029, -920, 937, 884, 1034, 698, 554, -1068, 265, 816, 549, -8, -511, -490, -485, 385, 399, 523, -225, -770, 248, -263, 463, -796, 920, 392, -447, 302, -81, 528, -831, 62, 885, 86, -591, -37, -233, -211, -441, 837, 72, -598, 370, 45, -481, 671, 651, 781, -823, -731, 754, -199, -540, -639, -364, -318, 723, 485, 423, -650, -648, -909, 197, -795, 824, 336, 546, 837, 201, -398, -653, 219, -537, 809, -402, -652, -289, -437, 160, 122, -485, -203, -50, 731, -353, 805, -87, 878, -517, };
+int32_t mlp_head_linear_bias[16] = {-54, 918, 756, -770, 1018, -2, -846, 44, 784, -104, -384, -203, 212, -628, -94, -97, };
+
+// Total 14512 parameters
\ No newline at end of file
diff --git a/sw/applications/transformer/data_cpp/signal.cpp b/sw/applications/transformer/data_cpp/signal.cpp
new file mode 100644
index 00000000..0f18a419
--- /dev/null
+++ b/sw/applications/transformer/data_cpp/signal.cpp
@@ -0,0 +1,5 @@
+#include "stdint-gcc.h"
+//int32_t STFT_out[48000] ={15022, 16390, 15545, 7388, 9791, 14435, 15910, 14934, 8889, 9029, 12589, 14368, 13003, 9548, 6344, 9857, 11479, 9461, 8476, -1914, 9560, 7842, 5972, 6077, 3300, 9683, 6443, 5918, 4306, 3938, 8512, 3724, 5741, 5023, 2931, 7275, 3649, 5604, 5232, 3039, 7640, 5448, 5155, 3191, 4248, 7282, 5707, 3886, -1395, 4874, 5392, 5566, 307, 3140, 5102, 5513, 5713, 2597, 3891, 5867, 6802, 5914, 4893, 3388, 6861, 6592, 6289, 5121, 3314, 7333, 4961, 6907, 3998, 3581, 7119, 1288, 7340, 1455, 3347, 6134, -4195, 7221, -649, 2575, 4133, 1906, 6413, 1158, 1360, 639, 3608, 4810, 1664, -862, -2161, 4537, 2477, 1308, -3721, -2389, 5307, 903, -4, -555, -6878, 5826, 1113, -906, 1167, -1543, 5776, 1199, 1884, 1762, 149, 4966, 11, 3047, 1390, -386, 3716, -5616, 2671, -203, 74, 2832, -1861, 1678, -2604, 1596, 1292, 161, 1333, -2384, 1575, -3881, 818, 667, -1833, -390, -1812, 1707, -740, -1805, -3086, -694, 1426, -453, -1980, -790, -124, -648, 361, -3457, 42, 1155, -1014, 791, -13091, -656, 812, 379, 1297, -3332, -2853, -1853, -235, 1618, -420, -3919, -2006, -4401, 1689, 1044, -2273, 275, -565, 1635, 1800, -2376, 792, 2138, 1102, 1969, -2561, 237, 2818, -543, 1624, -310, -1249, 2136, -4400, 904, 920, -3606, 71, -6615, -81, 501, -2837, -1532, -4246, -1490, -2411, -879, -159, -3977, -4394, -7388, -319, -37, -4141, -10580, -1874, -1163, -1711, -3155, -3770, -1572, -3881, -5011, -826, -3183, -2875, -10316, -4701, 956, -4547, -3369, -6280, -4795, 1932, -4555, -2151, -4832, -7088, 2278, -4062, -1050, -4362, -9139, 2188, -5250, -628, -4430, -6307, 1816, -7122, -665, -4281, -3722, 1238, -4499, -856, -3217, -2790, 465, -2960, -1433, -2147, -3077, -434, -3195, -2783, -1981, -2941, -1212, -5049, -5353, -3217, -1690, -1498, -5065, -11050, -3855, -942, -1402, -2999, -6061, -1383, -1013, -1582, -2083, -3332, -275, -1903, -2508, -2036, -2211, -841, -4324, -4298, -2542, -2304, -3922, -6944, -6426, -3393, -3771, -7282, -2375, -9088, -4619, -7090, -2152, -895, -13285, -6205, -9679, -953, -1090, -7111, -6943, -7333, -1160, -2657, -5178, -6399, -4361, -2748, -5439, -4401, -5331, -2684, -7849, -7725, -4121, -4253, -2323, -6348, -6897, -3765, -3744, -2985, -4222, -5344, -3340, -3952, -4292, -6316, -3943, -3635, -5099, -5501, -6581, -3258, -5395, -8104, -6121, -2890, -3694, -8349, -8938, -7267, -2405, -5253, -6570, -6183, -8317, -3901, -6728, -6160, -6023, -6129, -6730, -5623, -7081, -8065, -5117, -7618, -3654, -5993, -12612, -5517, -6372, -2633, -5248, -9541, -6669, -4810, -2844, -6076, -6778, -7488, -5029, -4130, -6289, -5302, -5846, -9132, -5152, -5290, -5980, -4321, -6877, -5027, -5471, -8488, -3290, 10948, 5340, 9881, -583, -1529, 10281, 3184, 9400, 6255, -1363, 7983, 1790, 7839, 8319, -1213, 2985, 5766, 4578, 8716, -1201, 5806, 5972, -7468, 8093, 239, 7278, 3992, 2631, 6914, 2658, 7007, 3013, 4259, 6183, 4335, 5657, 4920, 4879, 6103, 5026, 5172, 5662, 5285, 5893, 4883, 5509, 5524, 5613, 5378, 4402, 4184, 4538, 5872, 4553, 4309, 3084, 2519, 6053, 4412, 4533, 5541, 2182, 5884, 5410, 4304, 6269, 3345, 4957, 5653, 3045, 5565, 3276, 3046, 4418, 1028, 4272, 2407, 595, 1213, 734, 3636, 1612, -1021, -9, 1479, 3416, 1031, -324, 1364, 1998, 3255, 94, 588, 973, 1467, 3470, -317, 408, -256, -1566, 3966, 176, -148, -1555, -5910, 4403, -381, 149, -3399, -1218, 4406, -3162, 1043, -3706, -2034, 3699, -6969, 1255, 13, -2967, 2095, -928, 675, 2541, -309, -742, 1059, -55, 3772, 276, -5152, 1483, -1167, 3918, -918, -2310, 600, -2456, 3234, -4253, -629, -1699, -803, 2143, -8360, -748, -4480, 187, 920, -4510, -2796, -5722, -657, -732, -2852, -6555, -8562, -5101, -1617, -1578, -3238, -2751, -2692, -76, -473, -1770, -1006, 672, 1164, 146, -1307, -1054, 1972, 1728, -76, -1108, -747, 2401, 1777, -1105, -617, 737, 2292, 1237, -496, 491, 1494, 1811, -216, 1202, 1623, 1157, 1162, -1153, 1656, 2217, -332, 552, 898, 776, 2074, -3098, -150, 2083, -258, 1096, -4664, -1276, 2076, 269, -817, -3732, -2660, 1252, 403, -3595, -2332, -3627, 139, -804, -5568, -652, -4610, -491, -4906, -5112, 12, -5653, -40, -5243, -4091, -766, -6220, 444, -1562, -3606, -3645, -7870, -40, -1055, -4503, -10695, -8347, -1875, -1973, -6634, -7025, -5321, -3534, -3721, -6422, -10405, -3470, -2072, -5833, -8296, -6307, -2409, -1348, -8634, -8763, -3250, -1734, -1712, -13134, -3935, -2113, -1132, -2943, -10088, -2782, -1927, -552, -3587, -7851, -3207, -2420, -210, -2134, -5907, -4824, -3031, -288, -1175, -4432, -6584, -2800, -678, -1292, -3739, -5705, -2132, -1039, -2508, -3901, -3854, -1624, -1437, -5728, -4955, -2528, -1266, -2274, -7524, -5831, -2232, -1272, -3370, -2624, -5012, -3195, -2200, -3783, -947, -4277, -4836, -4802, -3420, -488, -3943, -4317, -5543, -2886, -691, -4040, -4122, -3597, -2892, -1142, -4925, -6452, -3758, -4002, -1519, -5252, -10060, -5054, -4808, -1904, -3326, -4930, -4535, -2874, -2275, -1642, -3491, -3392, -1585, -2128, -765, -3125, -2599, -1366, -1867, -687, -3101, -1848, -2227, -2471, -1521, -3092, -1584, -4873, -5110, -4002, -3221, -2450, -8948, -5746, -11796, -3989, -5450, -4673, -2300, -3014, -6275, -6993, -3629, -1265, -1233, -13060, -3994, -3325, -1129, -1401, -6473, -2795, -2634, -856, -3122, -4984, -1852, -2143, -668, -4531, -4954, -1543, -2277, -1158, -4444, 8135, 6088, 8626, -4024, 9938, 7329, 6317, 8147, 3034, 9253, 4904, 6099, 7090, 5534, 7062, 4788, 5168, 5821, 5756, 2868, 6323, 4576, 3219, 3312, 1833, 6494, 3735, 3133, -3194, 4473, 5760, 1781, 5247, 3503, 5033, 4322, 154, 5491, 4139, 2895, 2112, -1883, 5106, 3344, 1160, 567, -8604, 5398, 2834, 5248, 2441, -1097, 6168, 3530, 5936, 4900, 904, 6690, 4608, 5104, 6129, 2446, 6590, 5040, 5192, 6005, 3385, 5551, 4266, 6075, 4500, 3096, 3111, 1873, 6379, 1400, 1015, -337, -2432, 6535, -3148, -6312, 1153, -3379, 6387, -4178, -2431, 1960, -3097, 5323, -2846, -282, 1735, -1790, 2714, -1477, 1123, 1114, 483, -5178, -288, 2408, 349, 2279, -962, 828, 2867, -310, 3205, 602, 1651, 2089, 248, 3324, 1195, 1919, -836, 1723, 2724, 2721, 1435, -8160, 2498, 1506, 3795, -83, -1480, 2126, 141, 3702, -2304, -1676, 632, -186, 2139, -1688, -2840, -452, 758, 749, -1085, -1050, 84, 1955, 2587, -1448, -667, 47, 2776, 3314, -1334, -1973, -584, 3074, 2871, -1128, -4037, -927, 2914, 2029, -1831, -4223, -893, 2430, 1750, -3735, -1903, -725, 1721, 2124, -4438, 91, -814, 695, 2326, -1846, 1159, -718, -1112, 1779, -605, 1229, 953, -4285, 161, -1077, 226, 2278, -2549, -3196, -1597, -1233, 2448, -61, -10037, 1326, -207, 1631, 1238, -5459, 2800, 1173, 597, 1719, -2662, 2475, 1064, 234, 1395, -1008, 22, -931, 85, 225, -520, -10125, -1692, -101, -2013, -1056, -3239, -169, -365, -5623, -1918, -2721, -886, -713, -4148, -1070, -4144, -4883, -992, -3366, -504, -5371, -7334, -1451, -4299, -1722, -5860, -5572, -2058, -2407, -3307, -5420, -9669, -1902, -626, -800, -3278, -4000, -1470, -465, 514, -2492, -1965, -1758, -2323, 435, -3628, -1768, -2921, -5922, -956, -9229, -2309, -4942, -927, -4084, -4407, -2502, -9038, 836, -8231, -2095, -2284, -5389, 1066, -5365, -1906, -1985, -2756, 264, -3891, -3017, -2226, -2262, -1447, -4557, -4960, -3502, -3466, -3976, -11280, -5981, -3511, -5119, -4299, -3848, -5230, -2657, -3228, -2919, -1482, -4701, -3847, -1903, -2750, -1004, -4962, -9136, -1535, -4156, -1487, -5918, -5496, -1578, -9790, -2332, -7666, -4300, -1746, -6635, -2932, -11718, -5430, -1928, -3956, -3045, -13570, -7603, -2016, -3785, -2822, -9656, -7021, -2159, -4384, -2470, -5004, -4553, -2859, -3625, -2045, -2525, -3046, -5049, -2807, -1748, -1425, -2589, -10651, -3267, -2273, -1223, -2394, -5327, -4768, -4832, -1712, -1883, -4089, -3759, -6611, -2592, -1631, -4451, -2098, -3778, -2317, -1688, -4707, -1511, -4370, -1104, -1674, -5347, -1880, -7616, -511, -1990, -8962, -3392, -5659, -637, -3117, -7329, -6851, -5500, -1134, -4374, -4297, -12628, -9453, -1507, -3914, -3602, -7923, -7498, -4224, -5554, -4353, -4133, -2129, -3878, -7270, -2473, -2452, -1737, -3507, -7586, -2008, -2512, -2831, -2846, -5254, -3025, -3418, -5986, -2821, -3714, -5611, -3744, -7985, -2808, -3010, -13840, -2935, -6763, -2277, -2991, -6283, -2459, -7017, -2183, -3789, -3468, -3366, -5831, -3055, -6182, -2980, -5755, -4109, -5251, -13347, -4226, -3284, -3689, -9905, -6728, -7062, -1040, -4341, -6515, -5290, -10547, -88, -4173, -4287, -5037, -9538, 15, -3219, -3665, -4580, -5533, -670, -3366, -3725, -4293, -3755, -2433, -5426, -3616, -4979, -3342, -5897, -10483, -3418, -6809, -4226, -5644, -6907, -3888, -7436, -6950, -4348, -6768, -4698, -5425, -7290, -5661, -11547, -4637, -4024, -4705, -7820, -7789, -5294, -3717, -3606, -4001, -4241, -7811, -4602, -2791, -2423, -2364, -6255, -6510, -1775, -2276, -1164, -5607, -6340, -1017, -3077, -580, -7866, -4238, -901, -4310, -652, -11726, -3115, -1541, -5083, -1309, -10766, -3063, -2977, -5072, -2160, -5334, -3219, -5153, -4673, -2549, -2761, -2681, -5813, -4537, -2539, -1887, -2418, -4519, -5214, -2776, -1955, -2947, -4445, -6446, -3623, -2344, -4213, -5961, -6591, -5118, -2949, -6336, -7215, -6457, -7136, -4560, -9194, -6317, -7439, -9810, -7339, -9647, -7399, -9089, -8084, -5084, -8196, -10603, -8142, -4773, -4006, -6529, -5264, -6082, -3144, -4962, -5245, -3482, -4467, -2991, -7160, -4667, -3534, -3485, -4536, -5624, -4729, -5032, -3222, -8808, -4191, -5173, -6219, -3555, -16024, -4330, -5943, -5030, -4186, -8660, -6684, -6669, -4314, -4229, -3671, -7971, -6376, -4176, -3187, -1670, -3458, -5898, -4030, -2731, -1236, -1895, -5622, -3478, -3836, -1952, -1883, -5111, -2565, -7553, -3555, -3115, -4399, -1740, -7056, -5274, -5062, -4108, -1482, -5186, -5586, -5718, -5093, -2065, -5623, -4664, -4970, -9301, -3493, -7925, -3350, -3927, -8207, -4928, -13647, -2286, -3205, -5647, -5288, -11389, -1695, -3351, -5048, -5436, -10277, -1476, -4273, -3759, -5299, -11084, -1462, -3966, -2469, -4478, -12156, -1510, -2701, -2149, -3377, -9283, -1412, -2234, -3086, -2832, -6406, -1068, -2636, -6186, -3387, -5200, -747, -3812, -10087, -5553, -4196, -911, -5894, -5260, -12137, -2698, -2137, -8129, -4371, -9214, -1973, -5654, -7221, -4905, -7118, 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+//int32_t encoder_out[1936] ={-3006, -13563, -12330, 18429, -5740, 7757, -11785, 19611, 5385, -14561, -4444, -13231, -273, -10749, 1769, 14144, 6853, -7264, -3989, 9728, 6174, 14216, -13342, 20866, 8739, -9327, -15258, -12849, 11503, -16206, 6678, 4712, -3368, -10248, -323, 17739, 14650, 9631, -22149, 18791, 8398, -12585, -14408, -19795, 9133, 7335, -2016, 218, 3745, -8689, -3055, 8517, 19150, 15896, -17422, 15479, 8259, -11139, -19673, -16118, 13716, -2489, 4658, 10756, -8425, -1803, -6892, 18482, -7281, 2743, -5683, 20533, 17587, -5318, -5861, -19906, 5187, -1484, 11114, 7230, 228, -6363, -6655, 9139, 10365, 14506, -7711, 16482, 16422, -16187, -11228, -14695, 18943, -13552, 882, 2345, -11537, -6686, -11743, 7935, 7791, 17995, -10134, 17477, 20963, -15352, 3390, -7308, 7919, -5904, 5447, -2132, -1507, -5768, -3574, 4260, 2652, 4375, -17098, 18282, 7600, -16904, -13845, -10678, 3984, 7624, 6440, 18787, -4814, -13887, -3132, 16328, 2480, 14219, -15608, 12369, 9305, -6755, -9780, -9805, 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20120, 9190, 18659, -9922, 19385, 24080, -11026, -9187, -18048, 15138, -20644, 7384, -1591, -3322, -7729, -7178, 7882, 12850, 17169, -29152, 18653, 10324, -11162, -15366, -16757, 15256, 2707, 2295, 7212, -5099, -8408, -8961, 5473, 10208, 11194, -31132, 19405, 14988, -16836, -9705, -13365, 15011, 6886, -322, 15129, -2238, -4700, -2510, 15719, 12068, 15263, -17201, 18006, 5600, -14695, -13099, -10819, 5409, 6557, 1060, 20661, -1231, -8256, -6287, 13102, 1531, 15969, -12840, 14428, 12701, -8763, -15013, -14635, 16024, -1976, 8039, 8323, 1163, -4029, 1295, 13050, 5608, 12345, -22125, 21563, 18581, -11256, -10267, -24770, 3444, -2881, 479, 2431, -8476, -15408, -8011, 6272, 12904, 6282, -12405, 13611, 10172, -15424, -14768, -9625, 4751, -8107, 2882, 6915, 558, -1968, -7735, 11214, 1121, 18832, -16162, 14475, 10584, -7412, -18754, -9101, 6134, -5932, 8014, 5473, -2118, -128, -7230, 8462, 4284, 8683, -19400, 13767, 9541, -19055, -12613, -9168, 5520, 6085, 5818, 19566, -4967, -8263, -10320, 5186, 11308, 5608, -19345, 9650, 10010, -18178, -15500, -7019, 875, 728, -2431, 8600, -489, -1635, -8656, 6244, 627, 9692, -10156, 17995, 10687, -24421, -22420, -16582, 19462, -3430, 14473, -2169, -4748, 299, -5356, 11832, 777, 13351, -1567, 22147, 12026, -13901, -7808, -10741, 13146, -16640, 3079, -3068, 751, -285, -4640, 15415, 6281, 11059, -11255, 11059, 12984, -12162, -13589, -17987, 8424, -8545, 4051, 4753, -1922, -2756, -4453, 12951, 8903, 7796, -10048, 15724, 13579, -23594, -8454, -9019, 10395, 5265, 9772, 3949, -7364, -5175, -6215, 14174, -650, 14808, -12845, 28486, 12197, -19556, -5598, -16908, 11933, 1177, 331, -3723, -3169, -10619, -11448, 11612, 5069, 10765, -16340, 18499, 12963, -15722, -17082, -7403, 10093, -5279, -483, -1019, -2179, -6192, -9761, 138, 4022, 16176, -21635, 17535, 6239, -16161, -19177, -13231, 12251, -9925, 1566, 10893, -14047, -2666, -4217, 5942, -1564, 12132, -16661, 16392, 9506, -19765, -3372, -14345, 10870, -8606, 8542, 4691, -1876, -1064, -1200, 3602, 1012, 16364, -13975, 19559, 20924, -21303, -4196, -21408, 21603, -2487, 7945, 14237, 1470, -5301, -5154, 7858, 792, 6535, -16442, 18356, 9757, -8942, -21051, -11587, 8733, -2330, -4570, 13093, -5873, -6572, -2524, 8223, 7618, 8123, -18128, 12879, 9984, -23137, -11363, -12249, 15711, -3050, 5569, 12160, 4083, -2078, -8447, 9337, 6811, 12941, -19345, 21916, 8262, -18851, -20268, -15872, -1733, -1214, -2670, 11017, -4959, -157, -5468, 6929, 5662, 15289, -18151, 22569, 16912, -15083, -15593, -17894, 5010, -3382, 9746, -40, -5306, -3361, -6415, 16370, 952, 11072, -14498, 11353, 12985, -17035, 618, -11686, 12166, -13891, 12010, -3450, -1176, -9985, -753, 6891, 9043, 11060, -20824, 26305, 11316, -17920, -14594, -9230, 2777, -8907, 6890, 3935, -2320, -2538, -7024, 1691, 16832, 16628, -10460, 15082, 24286, -16158, -13634, -13556, 9365, -9506, 6446, 4493, -3193, -4061, -2893, 13112, 2437, 16475, -16245, 16377, 6162, -18041, -6740, -17056, 14220, 288, 9610, -2208, -8660, -4425, -4622, 8500, 3326, 12309, -10290, 16961, 18099, -23750, -14866, -14424, 8017, -5322, 4468, 3755, -11645, -5534, -10514, 12200, -474, 13851, -19413, 12801, 18684, -17540, -9202, -9935, 15524, -4871, 1224, 3998, -5864, -7892, -1162, 20918, 6517, 14193, -11343, 12942, 14462, -15089, -7462, -19859, 10933, -14142, 98, 3743, -7844, -3084, -3274, 8235, 5354, 10502, -16842, 17912, 22126, -11752, -15506, -15935, 17307, -7699, 1119, -935, 961, -2984, -12227, 813, 6519, 13134, -18401, 19312, 5803, -11180, -14533, -10765, 10838, 366, 1436, 5799, -6026, -9234, -9767, 4700, 524, 16873, -18033, 19048, 10559, -23621, -11091, -10671, 13415, -3442, 3701, 9035, -2814, -2557, -9638, 5850, 6306, 18884, -11488, 18210, 17064, -13909, -16839, -11630, 17459, 1751, -1371, 2436, -11033, -7206, -6848, 14214, 7744, 16099, -20816, 8966, 13109, -14437, -12666, -18172, -3320, -1772, 8626, 7304, 10, -11047, -3896, 21065, 4666, 9300, -11349, 16631, 3824, -5909, -7915, -14171, 7029, -667, 3960, 1565, 2782, -12537, -10300, 11758, 12762, 18572, -15625, 17045, 9661, -11897, -5784, -10756, 5216, -13503, -805, 11559, 3901, -6574, -3466, 6907, 10363, 17436, -26414, 20128, 8295, -17817, -20323, -20804, 7154, 1155, 5136, 13470, -5469, -1455, 807, 15944, 2686, 18128, -17961, 27966, 9550, -18449, -16653, -13179, 4493, 7287, 5197, 760, 1500, -10621, -5921, 7359, 7581, 17717, -17649, 10306, 11416, -18892, -14387, -16829, 13281, -2882, -1957, -351, 1159, -6311, -6635, 10989, 3535, 16933, -22238, 24300, 9058, -7718, -21583, -9173, 2480, 2573, -5305, 4740, -9380, -2832, -9839, 9766, 11385, 8620, -16707, 25052, 17508, -20031, -13020, -12162, 12100, -10151, 12370, -79, -1518, -7732, -9555, 4088, -686, 15800, -13213, 14653, 14378, -13888, -8837, -12851, 8542, -3624, 3106, 1206, -10739, -3570, -5822, 1881, 634, 8596, -9144, 13755, 18369, -20422, -7515, -13588, 15796, -6124, 5742, -5391, -2255, -170, -5938, 12486, -4898, 12070, -15414, 22543, 14595, -19373, -14154, -11389, 18806, -4725, 1237, 4293, 2099, -6089, -9000, 9513, 5640, 14807, -15826, 16983, 18406, -13532, -9893, -21230, 22742, -11495, -2039, 1731, 7707, -9512, 957, 6361, 8277, 5846, -22667, 24396, 3553, -17504, -15340, -16114, 3937, -5080, -2916, 16451, -2466, -7719, -3050, 13639, 2875, 11755, -13224, 19848, 6314, -19502, -12653, -14361, 11483, -3612, 7826, 924, -3683, -6214, -15062, 9777, 4574, 11937, -9206, 19258, 21549, -14860, -2556, -16578, 19355, -8190, 907, 1251, };
+int32_t prototypes[32] ={-1394, -5770, -6778, 762, 4001, -653, -5906, -20, 1220, 3795, -73, -3028, 635, -448, 7677, -6204, 5745, 3112, 1206, -1120, -3618, 1076, -649, 943, -3896, 2462, 4658, 2494, 3996, 1220, -1144, -1013, };
diff --git a/sw/applications/transformer/dense_layerC.c b/sw/applications/transformer/dense_layerC.c
new file mode 100644
index 00000000..08d6c6b3
--- /dev/null
+++ b/sw/applications/transformer/dense_layerC.c
@@ -0,0 +1,69 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "dense_layerC.h"
+#include <stdio.h>
+
+void createDense(Dense* dense, size_t input_dim, size_t output_dim, quant_bit_width *weight, quant_bit_width* bias) {
+    dense->input_size_ = input_dim;
+    dense->output_size_ = output_dim;
+    dense->weight = weight;
+    dense->bias = bias;
+}
+
+void destroyDense(Dense* dense) {
+    // Free the memory allocated for the Dense struct
+    free(dense);
+}
+
+void multiplyweight(Dense* dense, size_t seq_len, int32_t* input, int32_t* output) {
+    for (int length = 0; length < seq_len; length++) {
+        for (int out_idx = 0; out_idx < dense->output_size_; out_idx++) {
+            int32_t* weight_ptr = dense->weight + out_idx;
+            int32_t* output_ptr = output + (length * dense->output_size_) + out_idx;
+            int32_t* input_ptr = input + (length * dense->input_size_);
+            int32_t sum = 0;
+            for (int i = 0; i < dense->input_size_; i++) {
+                sum += MUL_HQ(*weight_ptr, *input_ptr); // MUL_HQ macro
+                input_ptr++;
+                weight_ptr += dense->output_size_;
+            }
+            *(output_ptr) = (int32_t) (sum >> NUM_FRACTION_BITS); // NUM_FRACTION_BITS macro
+        }
+    }
+}
+
+void addbias(Dense* dense, size_t seq_len, int32_t* output) {
+    for (size_t idx = 0; idx < seq_len; idx++) {
+        for (size_t feature_idx = 0; feature_idx < dense->output_size_; feature_idx++) {
+            output[idx * dense->output_size_ + feature_idx] += dense->bias[feature_idx];
+        }
+    }
+}
+
+void computeDense(Dense* dense, size_t seq_len, int32_t* input, int32_t* output) {
+    //multiplyweight(dense, seq_len, input, output);
+    printf("\rMul %dx%dx%d\n", seq_len, dense->input_size_, dense->output_size_);
+    multiply_cgra(input, seq_len, dense->input_size_, dense->weight, dense->output_size_, output);
+    if (dense->bias != NULL) {
+        addbias(dense, seq_len, output);
+    }
+}
+
+void activation(Dense* dense, size_t length, int32_t* input, int32_t* output) {
+    float in_float, in_tanh;
+    int32_t x3, in_tanh_fxp;
+    for (int i = 0; i < length; i++) {
+        x3 = MUL(MUL(input[i], input[i]), input[i]);
+        x3 = MUL(x3, 183); // 183 = 0.044715 in fixed-point 12 bit
+        x3 += input[i];
+        x3 = MUL(x3, 3268); // 3268 = sqrt(2/PI) in fixed-point 12 bit
+        in_float = (float) x3 / (float) (1 << NUM_FRACTION_BITS);
+        in_tanh = tanhf(in_float);
+        in_tanh_fxp = (int32_t) (in_tanh * (1 << NUM_FRACTION_BITS));
+        in_tanh_fxp += (1 << NUM_FRACTION_BITS);
+        output[i] = MUL(in_tanh_fxp, input[i] >> 1);
+    }
+}
+
diff --git a/sw/applications/transformer/dense_layerC.h b/sw/applications/transformer/dense_layerC.h
new file mode 100644
index 00000000..c67d4571
--- /dev/null
+++ b/sw/applications/transformer/dense_layerC.h
@@ -0,0 +1,30 @@
+//
+// Created by alireza on 10/5/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_DENSE_LAYERC_H
+#define FVLLMONTITRANSFORMER_DENSE_LAYERC_H
+
+
+#include <stdlib.h>
+#include <stddef.h>
+#include <math.h>
+#include "param.h"
+#include "cgra.h"
+
+// Define the struct
+typedef struct {
+    size_t input_size_;
+    size_t output_size_;
+    int32_t* weight; // quant_bit_width is a typedef for int32_t
+    int32_t* bias; // quant_bit_width is a typedef for int32_t
+} Dense;
+
+void createDense(Dense* dense, size_t input_dim, size_t output_dim, quant_bit_width *weight, quant_bit_width* bias);
+void destroyDense(Dense* dense);
+void multiplyweight(Dense* dense, size_t seq_len, int32_t* input, int32_t* output);
+void addbias(Dense* dense, size_t seq_len, int32_t* output);
+void computeDense(Dense* dense, size_t seq_len, int32_t* input, int32_t* output);
+void activation(Dense* dense, size_t length, int32_t* input, int32_t* output);
+
+#endif //FVLLMONTITRANSFORMER_DENSE_LAYERC_H
diff --git a/sw/applications/transformer/main.c b/sw/applications/transformer/main.c
new file mode 100644
index 00000000..a4c81ea4
--- /dev/null
+++ b/sw/applications/transformer/main.c
@@ -0,0 +1,156 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include <stdio.h>
+#include <math.h>
+#include "main.h"
+#include "data_cpp/signal.cpp"
+//#include "data_cpp/signal_fft.cpp"
+#include "SYLT-FFT/fft.h"
+#include "weightsAndBiasesC.h"
+#include "transformerBlockC.h"
+
+// For the cgra
+#include "multiply_cgra.h"
+
+
+// FFT
+#include "stftVec.h"
+
+
+
+float error_check(const quant_bit_width* groundTruth, const quant_bit_width* output, size_t length){
+    long error = 0;
+    for (int i=0; i<length; i++){
+        error += MUL_HQ(groundTruth[i] - output[i], groundTruth[i] - output[i]);
+    }
+    error = (error >> NUM_FRACTION_BITS);
+    return (float) error/ (float) length;
+}
+
+void prototype_distances(quant_bit_width* prototypeVec, const quant_bit_width* modelOutput, int32_t* distVec, size_t prototypeLength, int prototypeNums){
+    for (int p=0; p< prototypeNums; p++){
+        long dist = 0;
+        quant_bit_width * prototypePtr = prototypeVec + (p * prototypeLength);
+        for (int i=0; i<prototypeLength; i++){
+            dist += MUL_HQ(prototypePtr[i] - modelOutput[i], prototypePtr[i] - modelOutput[i]);
+        }
+        dist = (dist >> NUM_FRACTION_BITS);
+        distVec[p] = (int32_t) dist;
+    }
+}
+
+void transformerInference(quant_bit_width * transformerInput, quant_bit_width * transformerOutput, quant_bit_width* input_normalized, quant_bit_width* qkv, quant_bit_width* intermediate, void * kperf){
+    quant_bit_width * weightVec[NUM_LAYERS*(3*NUM_HEAD+5)+5];
+    quant_bit_width * biasVec[NUM_LAYERS*(3*NUM_HEAD+5)+5];
+    //getWeights(weightVec);
+    //getBiases(biasVec);
+    quant_bit_width * clsTokenVector = getClassToken();
+    quant_bit_width * posMatrix = getPosEmbedding();
+    TransformerBlock* selfatten = createTransformerBlock(D_SEQ, D_MODEL, D_Q, NUM_HEAD, D_FF, weightVec, biasVec, clsTokenVector, posMatrix);
+    computeFixedPoint(selfatten, D_SEQ, transformerInput, input_normalized, transformerOutput, intermediate, qkv, kperf);
+}
+
+quant_bit_width compute_log_amp(int32_t real, int32_t imag){
+    real = MUL_HQ(real, 25) >> (NUM_FRACTION_BITS - 9);
+    imag = MUL_HQ(imag, 25) >> (NUM_FRACTION_BITS - 9);
+    int32_t real2 = MUL_LONG(real, real) >> NUM_FRACTION_BITS;
+    int32_t imag2 = MUL_LONG(imag, imag) >> NUM_FRACTION_BITS;
+    float pow2 = (float)(real2 + imag2) / (float) (1<< NUM_FRACTION_BITS);
+    float amp = sqrtf(pow2);
+    float stft = logf(amp+ 1e-10f);
+    quant_bit_width stft_int = (quant_bit_width) (stft * (1<<NUM_FRACTION_BITS));
+    return stft_int;
+}
+
+/*
+void initialize_stft(fft_complex_t* data, const quant_bit_width * raw_input_signal){
+    // Initialize each element of the data array
+    for (int i = 0; i < 256; i++) {
+        data[i].r = (MUL_HQ(raw_input_signal[i], hanning[i])) ;
+        data[i].i = 0;
+    }
+    for (int i = 256; i < 512; i++) {
+        data[i].r = 0;
+        data[i].i = 0;
+    }
+}
+*/
+
+/*
+void stft_rearrange(quant_bit_width* rawInputSignal, quant_bit_width* stftVec, size_t patchHeight, size_t patchWidth){
+    fft_complex_t data[512];
+    int overlap = 64;
+    for (int ch=0; ch<20; ch++){
+        for (int time_step=0; time_step<15; time_step++){
+            quant_bit_width* rawSignalPtr = rawInputSignal + ch * 3072 + (256 - overlap) * time_step;
+            initialize_stft(data, rawSignalPtr);
+            fft_fft(data, 9);
+            quant_bit_width * stftVecPtr = stftVec + ch * 15 * 160 + (time_step / patchWidth) * patchWidth * patchHeight + (time_step % patchWidth);
+            for (int index =0 ; index < patchHeight; index++){
+                int16_t stft_int = compute_log_amp(data[index].r, data[index].i);
+                *stftVecPtr = (int32_t) stft_int;
+                stftVecPtr += patchWidth;
+            }
+            stftVecPtr += patchHeight * patchWidth * 2;
+            for (int index = patchHeight ; index < 2*patchHeight; index++){
+                int16_t stft_int = compute_log_amp(data[index].r, data[index].i);
+                *stftVecPtr = (int32_t) stft_int;
+                stftVecPtr += patchWidth;
+            }
+        }
+    }
+}*/
+
+
+int main() {
+    kcom_perf_t kperf;
+    // Init timer
+    timerInit();
+
+    // Initialize the CGRA
+    kcom_perfRecordStart(&(kperf.time.load));
+    initCGRA();
+    kcom_perfRecordStop(&(kperf.time.load));
+
+    // Enable and reset the CGRA performance counters
+    countersInit();
+
+    // Transformer
+    //quant_bit_width* stftVec = raw_signal;
+    //quant_bit_width* rawInputSignal = raw_signal + 160*15;
+    quant_bit_width* out_first = stftVec + 160*400; // Output start where the input ends
+    quant_bit_width* output = stftVec + 20450; // Buffer to use for the output
+    // Out_first only has 120*16 elements
+    
+    // Order
+    // Input 121x16
+    // Input_norm 121x16
+    // Qkv uses 121x4x4
+    // Bigger intermediate is 121x121
+
+    quant_bit_width* intermediate = stftVec + 5808;
+    quant_bit_width* qkv = stftVec + 3872;
+    quant_bit_width* input_normalized = stftVec + 1936;
+    int32_t distances[2];
+    //kcom_perfRecordStop(&(perf.init));
+    //kcom_perfRecordStart(&(perf.stft));    
+    //stft_rearrange(rawInputSignal, stftVec, 80, 5);
+    //kcom_perfRecordStop(&(perf.stft));    
+    //kcom_perfRecordStart(&(perf.infer));
+    transformerInference(stftVec, output, input_normalized, qkv, intermediate, (void *) &kperf);
+    //kcom_perfRecordStop(&(perf.infer));
+    
+    kcom_perfRecordStart(&(kperf.time.proto));
+    prototype_distances(prototypes, output, distances, D_MODEL, 2);
+    kcom_perfRecordStop(&(kperf.time.proto));
+    printf("Distances:\n");
+    for (int i = 0; i< 2; i++)
+        printf("Class %d = %d\n", i, distances[i]);
+    
+    printf("\rEND\n");
+    return 0;
+}
+
+
diff --git a/sw/applications/transformer/main.h b/sw/applications/transformer/main.h
new file mode 100644
index 00000000..822bc753
--- /dev/null
+++ b/sw/applications/transformer/main.h
@@ -0,0 +1,17 @@
+//
+// Created by alireza on 10/25/21.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TRANSFORMER_H
+#define FVLLMONTITRANSFORMER_TRANSFORMER_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include "param.h"
+
+float error_check(const quant_bit_width* groundTruth, const quant_bit_width* output, size_t length);
+void prototype_distances(quant_bit_width* prototypeVec, const quant_bit_width* modelOutput, int32_t* distVec, size_t prototypeLength, int prototypeNums);
+void transformerInference(quant_bit_width * transformerInput, quant_bit_width * transformerOutput, quant_bit_width* input_normalized, quant_bit_width* qkv, quant_bit_width* intermediate, void * kperf);
+quant_bit_width compute_log_amp(int32_t real, int32_t imag);
+
+#endif //FVLLMONTITRANSFORMER_TRANSFORMER_H
diff --git a/sw/applications/transformer/matMulC.c b/sw/applications/transformer/matMulC.c
new file mode 100644
index 00000000..eb60c96c
--- /dev/null
+++ b/sw/applications/transformer/matMulC.c
@@ -0,0 +1,22 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "matMulC.h"
+#include <stdio.h>
+
+
+void MatMul_multiply(size_t seq_len, quant_bit_width* input, quant_bit_width* weight,
+                           quant_bit_width* output, size_t input_size, size_t output_size) {
+    printf("\rMul %dx%dx%d\n", seq_len, input_size, output_size);
+    multiply_cgra(input, seq_len, input_size, weight, output_size, output);
+}
+
+void MatMul_scale(quant_bit_width* input, int shift_scale, size_t mat_size) {
+
+    for (size_t i = 0; i < mat_size; i++) {
+        *input = (*input) >> shift_scale;
+        input++;
+    }
+}
+
diff --git a/sw/applications/transformer/matMulC.h b/sw/applications/transformer/matMulC.h
new file mode 100644
index 00000000..9844b787
--- /dev/null
+++ b/sw/applications/transformer/matMulC.h
@@ -0,0 +1,21 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_MATMULC_H
+#define FVLLMONTITRANSFORMER_MATMULC_H
+
+
+#include <stddef.h>
+#include "param.h"
+#include "cgra.h"
+
+#define BLOCK_SIZE 4
+
+typedef struct {
+} MatMul;
+
+void MatMul_multiply(size_t seq_len, quant_bit_width* input, quant_bit_width* weight, quant_bit_width* output, size_t input_size, size_t output_size);
+void MatMul_scale(quant_bit_width* input, int shift_scale, size_t mat_size);
+
+#endif //FVLLMONTITRANSFORMER_MATMULC_H
diff --git a/sw/applications/transformer/multiply_cgra.c b/sw/applications/transformer/multiply_cgra.c
new file mode 100644
index 00000000..69eef852
--- /dev/null
+++ b/sw/applications/transformer/multiply_cgra.c
@@ -0,0 +1,177 @@
+/*
+                              *******************
+******************************* C SOURCE FILE *******************************
+**                            *******************                          **
+**                                                                         **
+** project  : HEEPsilon                                                    **
+** filename : main.c                                                       **
+** version  : 1                                                            **
+** date     : 01/10/23                                                     **
+**                                                                         **
+*****************************************************************************
+**                                                                         **
+** Copyright (c) EPFL                                                      **
+** All rights reserved.                                                    **
+**                                                                         **
+*****************************************************************************
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+
+/**
+* @file   main.c
+* @date   01/10/23
+* @brief  An application to run a matrix multiplication.
+*
+*/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                             MODULES USED                                 */
+/**                                                                        **/
+/****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include "cgra_x_heep.h"
+#include "cgra_bitstream.h"
+#include "multiply_cgra.h"
+
+// For interrupt handling
+#include "csr.h"
+#include "handler.h"
+#include "rv_plic.h"
+#include "rv_plic_regs.h"
+#include "hart.h"
+#include "cgra.h"
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                        DEFINITIONS AND MACROS                            */
+/**                                                                        **/
+/****************************************************************************/
+
+// Size of the input buffer for the CGRA
+#define CGRA_COL_INPUT_SIZE 4
+
+/****************************************************************************/
+/**                                                                        **/
+/*                      PROTOTYPES OF LOCAL FUNCTIONS                       */
+/**                                                                        **/
+/****************************************************************************/
+
+
+// Handler for the CGRA interruption
+void handler_irq_cgra(uint32_t id);
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            GLOBAL VARIABLES                              */
+/**                                                                        **/
+/****************************************************************************/
+
+// Plic controller variables
+volatile bool               cgra_intr_flag;
+
+// CGRA variables
+static cgra_t               cgra;
+static uint8_t              cgra_slot;
+
+// CGRA input and output buffers
+static int32_t cgra_input[CGRA_N_COLS][CGRA_COL_INPUT_SIZE]    __attribute__ ((aligned (4)));
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            LOCAL FUNCTIONS                               */
+/**                                                                        **/
+/****************************************************************************/
+
+void multiply_cgra(int * matrixA, int ROWS_A, int COLS_A, int * matrixB, int COLS_B, int * matrixC)
+{
+  int ROWS_B = COLS_A;
+  int ROWS_C = ROWS_A;
+  int COLS_C = COLS_B;
+  // Prepare the input vector for the CGRA
+  // Col 0: &B[0][0], nItLoopColsC, &A[0][0], &C[0][3]
+  cgra_input[0][0] = &matrixB[0];
+  cgra_input[0][1] = COLS_C/CGRA_N_ROWS;
+  cgra_input[0][2] = &matrixA[0];
+  cgra_input[0][3] = &matrixC[3];
+  // Col 1: &C[1][0], &B[0][1], nItLoopsColsA, &A[1][0]
+  cgra_input[1][0] = &matrixC[COLS_C];
+  cgra_input[1][1] = &matrixB[1];
+  cgra_input[1][2] = COLS_A;
+  cgra_input[1][3] = &matrixA[COLS_A];
+  // Col 2: &A[2][0], &C[2][1], &B[0][2], nItLoopColsC
+  cgra_input[2][0] = &matrixA[2*COLS_A];
+  cgra_input[2][1] = &matrixC[2*COLS_C+1];
+  cgra_input[2][2] = &matrixB[2];
+  cgra_input[2][3] = COLS_C/CGRA_N_ROWS;
+  // Col 3: nItLoopRowsC, &A[3][0], &C[3][2], &B[0][3], 
+  cgra_input[3][0] = ROWS_C/CGRA_N_COLS;
+  cgra_input[3][1] = &matrixA[3*COLS_A];
+  cgra_input[3][2] = &matrixC[3*COLS_C+2];
+  cgra_input[3][3] = &matrixB[3];
+
+  // Set CGRA kernel L/S pointers
+  for(int col_idx = 0 ; col_idx < CGRA_N_COLS ; col_idx++){
+    cgra_set_read_ptr ( &cgra, cgra_slot, (uint32_t) cgra_input[col_idx], col_idx );
+  }
+
+  // CGRA Execution
+  cgra_intr_flag = 0;
+  cgra_set_kernel( &cgra, cgra_slot, 1 );
+  // Wait until CGRA is done
+  while(cgra_intr_flag==0) {
+    wait_for_interrupt();
+  }
+}
+
+// Initialize the CGRA
+void initCGRA(){
+  // Init the PLIC
+  plic_Init();
+  plic_irq_set_priority(CGRA_INTR, 1);
+  plic_irq_set_enabled(CGRA_INTR, kPlicToggleEnabled);
+  plic_assign_external_irq_handler( CGRA_INTR, (void *) &handler_irq_cgra);
+
+  // Enable interrupt on processor side
+  // Enable global interrupt for machine-level interrupts
+  CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+  // Set mie.MEIE bit to one to enable machine-level external interrupts
+  const uint32_t mask = 1 << 11;//IRQ_EXT_ENABLE_OFFSET;
+  CSR_SET_BITS(CSR_REG_MIE, mask);
+  cgra_intr_flag = 0;
+
+  // Load kernel
+  cgra_cmem_init(cgra_imem_bitstream, cgra_kmem_bitstream);
+
+  cgra.base_addr = mmio_region_from_addr((uintptr_t)CGRA_PERIPH_START_ADDRESS);
+  // Select request slot of CGRA
+  cgra_slot = cgra_get_slot(&cgra);
+}
+
+// Interrupt controller variables
+void handler_irq_cgra(uint32_t id) {
+  cgra_intr_flag = 1;
+}
+
+void countersInit(){
+  // Enable and reset the CGRA performance counters
+  cgra_perf_cnt_enable(&cgra, 1);
+  cgra_perf_cnt_reset( &cgra );
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/*                                 EOF                                      */
+/**                                                                        **/
+/****************************************************************************/
diff --git a/sw/applications/transformer/multiply_cgra.h b/sw/applications/transformer/multiply_cgra.h
new file mode 100644
index 00000000..d43ba4fd
--- /dev/null
+++ b/sw/applications/transformer/multiply_cgra.h
@@ -0,0 +1,6 @@
+#include "performance.h"
+
+// Multiply the matrix in the cgra
+void multiply_cgra(int * matrixA, int rowsA, int colsA, int * matrixB, int colsB, int * matrixC);
+void countersInit();
+void initCGRA();
\ No newline at end of file
diff --git a/sw/applications/transformer/param.h b/sw/applications/transformer/param.h
new file mode 100644
index 00000000..6e4163a4
--- /dev/null
+++ b/sw/applications/transformer/param.h
@@ -0,0 +1,26 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_PARAM_H
+#define FVLLMONTITRANSFORMER_PARAM_H
+#include "stdint.h"
+
+#define D_Q 4
+#define D_SEQ 120
+#define D_MODEL 16
+#define NUM_HEAD 4
+#define NUM_LAYERS 4
+#define D_FF 4
+#define D_EMBEDDING 400
+
+
+#define NUM_FRACTION_BITS 12
+#define MUL(x, y) (int32_t) (((int32_t)(x) * (int32_t)(y)) >> NUM_FRACTION_BITS)
+#define MUL_LONG(x, y) (int64_t) (((int64_t)(x) * (int64_t)(y)))
+#define MUL_HQ(x, y) (int32_t) (((int32_t)(x) * (int32_t)(y)))
+#define SHIFT(x) ((x) >> NUM_FRACTION_BITS)
+
+
+typedef int32_t quant_bit_width;
+#endif //FVLLMONTITRANSFORMER_PARAM_H
diff --git a/sw/applications/transformer/performance.c b/sw/applications/transformer/performance.c
new file mode 100644
index 00000000..421d39be
--- /dev/null
+++ b/sw/applications/transformer/performance.c
@@ -0,0 +1,62 @@
+#include "performance.h"
+
+// For the timer
+#include "rv_timer.h"
+#include "soc_ctrl.h"
+#include "core_v_mini_mcu.h"
+
+// Timer
+static rv_timer_t          timer;
+
+void kcom_perfRecordStart( kcom_time_diff_t *perf )
+{
+    timeStart( perf );
+}
+
+void kcom_perfRecordStop( kcom_time_diff_t *perf )
+{
+    timeStop( perf );
+}
+
+void timeStart( kcom_time_diff_t *perf )
+{
+    perf->start_cy = getTime_cy();
+}
+
+void timeStop( kcom_time_diff_t *perf )
+{
+    perf->end_cy = getTime_cy();
+    perf->spent_cy += perf->end_cy - perf->start_cy;
+}
+
+uint64_t getTime_cy( )
+{
+    static uint64_t out;
+    rv_timer_counter_read( &timer, HART_ID, &out );
+    return out;
+}
+
+//Initialize the timer
+void timerInit()
+{
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr  = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz  = soc_ctrl_get_frequency(&soc_ctrl);
+
+    mmio_region_t timer_0_reg = mmio_region_from_addr(RV_TIMER_AO_START_ADDRESS);
+
+    rv_timer_init( timer_0_reg, (rv_timer_config_t) { .hart_count = 2, .comparator_count = 1 }, &timer );
+
+    rv_timer_tick_params_t tick_params;
+
+    // The same frequency is provaided to get one tick per cycle.
+    rv_timer_approximate_tick_params( freq_hz, freq_hz, &tick_params );
+    rv_timer_set_tick_params(&timer, HART_ID, tick_params);
+
+    // Juan: see if i cannot remove this!
+    rv_timer_irq_enable(&timer, HART_ID, 0, kRvTimerEnabled);
+    rv_timer_arm(&timer, HART_ID, 0, 1);
+
+    rv_timer_counter_set_enabled(&timer, HART_ID, kRvTimerEnabled);
+
+}
\ No newline at end of file
diff --git a/sw/applications/transformer/performance.h b/sw/applications/transformer/performance.h
new file mode 100644
index 00000000..301f4874
--- /dev/null
+++ b/sw/applications/transformer/performance.h
@@ -0,0 +1,63 @@
+#include <stdint.h>
+#include "cgra.h"
+
+typedef long int    kcom_time_t;
+typedef kcom_time_t kcom_param_t;
+
+typedef struct kcom_col_perf
+{
+    uint32_t cyc_act;
+    uint32_t cyc_stl;
+} kcom_col_perf_t;
+
+typedef struct kcom_time_diff
+{
+    kcom_time_t start_cy;
+    kcom_time_t end_cy;
+    kcom_time_t spent_cy;
+} kcom_time_diff_t;
+
+typedef struct kcom_timing
+{
+    kcom_time_diff_t    sw;
+    kcom_time_diff_t    cgra;
+    kcom_time_diff_t    load;
+    kcom_time_diff_t    input;
+    kcom_time_diff_t    output;
+    kcom_time_diff_t    reprogramCols;
+    kcom_time_diff_t    bitstream;
+    kcom_time_diff_t    proto;
+} kcom_timing_t;
+
+typedef struct kcom_perf
+{
+    kcom_col_perf_t    cols[CGRA_N_COLS];
+    kcom_col_perf_t    cols_max;
+    uint32_t           cyc_ratio; // Stored *CGRA_STAT_PERCENT_MULTIPLIER
+    kcom_timing_t      time;
+} kcom_perf_t;
+
+typedef struct kcom_run
+{
+    kcom_param_t sw;
+    kcom_param_t conf;
+    kcom_param_t cgra;
+    kcom_param_t repo;
+} kcom_run_t;
+
+typedef struct kcom_stats
+{
+   kcom_run_t   avg;
+   uint32_t     n;
+   uint32_t     errors;
+   uint8_t      *name;
+} kcom_stats_t;
+
+#define HART_ID 0
+
+void timerInit();
+uint64_t getTime_cy( );
+void timeStop( kcom_time_diff_t *perf );
+void timeStart( kcom_time_diff_t *perf );
+void kcom_perfRecordStop( kcom_time_diff_t *perf );
+void kcom_perfRecordStart( kcom_time_diff_t *perf );
\ No newline at end of file
diff --git a/sw/applications/transformer/selfattentionC.c b/sw/applications/transformer/selfattentionC.c
new file mode 100644
index 00000000..7b0c175a
--- /dev/null
+++ b/sw/applications/transformer/selfattentionC.c
@@ -0,0 +1,68 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include <stdio.h>
+#include "selfattentionC.h"
+
+
+void create_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn, size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, int32_t** weightVector) {
+    self_attn->pre_seq_len = pre_seq_len;
+    self_attn->head_hidden_size = head_hidden_size;
+    createDense(self_attn->query_layer, input_dim, head_hidden_size, weightVector[0], NULL);
+    createDense(self_attn->key_layer, input_dim, head_hidden_size, weightVector[1], NULL);
+    createDense(self_attn->value_layer, input_dim, head_hidden_size, weightVector[2], NULL);
+}
+
+void destroy_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn) {
+    free(self_attn->query_layer_out);
+    free(self_attn->key_layer_out);
+    free(self_attn->key_transposed_layer_out);
+    free(self_attn->value_layer_out);
+    free(self_attn->attention_scores);
+
+    destroyDense(self_attn->query_layer);
+    destroyDense(self_attn->key_layer);
+    destroyDense(self_attn->value_layer);
+
+    free(self_attn);
+}
+
+void removeExtraCols(int32_t* input, size_t rows, int cols) {
+    int nElems = 3;
+    for(int r = 1; r < rows; r++, nElems+=3){
+        for(int c = 0; c < cols -3; c++){
+            input[r*cols+c -nElems] = input[r*cols+c];
+        }
+    }
+}
+
+void compute_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn, int32_t* input, int32_t* output, int32_t* qkv, int32_t* intermediate) {
+    self_attn->query_layer_out = qkv;
+    self_attn->key_layer_out = qkv + self_attn->pre_seq_len * self_attn->head_hidden_size;
+    self_attn->value_layer_out = qkv + 2 * self_attn->pre_seq_len * self_attn->head_hidden_size;
+    self_attn->key_transposed_layer_out = qkv + 3 * self_attn->pre_seq_len * self_attn->head_hidden_size;
+
+    // This 3 mmul need to think they have 124 rows instead of 121
+    // TODO: Check that the outputs have enough space for the extra 3 rows
+    computeDense(self_attn->query_layer, self_attn->pre_seq_len +3, input, self_attn->query_layer_out); // 121x16x4
+    computeDense(self_attn->key_layer, self_attn->pre_seq_len +3, input, self_attn->key_layer_out); // 121x16x4
+    computeDense(self_attn->value_layer, self_attn->pre_seq_len +3, input, self_attn->value_layer_out); // 121x16x4
+
+    transpose_quant(self_attn->key_layer_out, self_attn->key_transposed_layer_out, self_attn->pre_seq_len +3, self_attn->head_hidden_size);
+    MatMul_scale(self_attn->key_transposed_layer_out, 1, (self_attn->pre_seq_len +3) * self_attn->head_hidden_size);
+
+    // 121x4x121
+    MatMul_multiply(self_attn->pre_seq_len +3, self_attn->query_layer_out, self_attn->key_transposed_layer_out, intermediate, self_attn->head_hidden_size, self_attn->pre_seq_len +3);
+    
+    printf("\rRemove cols\n");
+    // 121x124 -> 121x121 Remove extra cols
+    removeExtraCols(intermediate, self_attn->pre_seq_len, 124);
+
+    printf("\rSoftmax\n");
+    // Now intermediate is 121x121
+    computeSoftmax(intermediate, self_attn->pre_seq_len);
+    
+    // 121x121x4
+    MatMul_multiply(self_attn->pre_seq_len +3, intermediate, self_attn->value_layer_out, output, self_attn->pre_seq_len, self_attn->head_hidden_size);
+}
diff --git a/sw/applications/transformer/selfattentionC.h b/sw/applications/transformer/selfattentionC.h
new file mode 100644
index 00000000..b2e3ab2c
--- /dev/null
+++ b/sw/applications/transformer/selfattentionC.h
@@ -0,0 +1,35 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_SELFATTENTIONC_H
+#define FVLLMONTITRANSFORMER_SELFATTENTIONC_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "dense_layerC.h"
+#include "softmaxC.h"
+#include "transposeC.h"
+#include "matMulC.h"
+#include "param.h"
+#include "cgra.h"
+
+typedef struct {
+    Dense* query_layer;
+    Dense* key_layer;
+    Dense* value_layer;
+    int32_t* query_layer_out;
+    int32_t* key_layer_out;
+    int32_t* key_transposed_layer_out;
+    int32_t* value_layer_out;
+    int32_t* attention_scores;
+    size_t pre_seq_len;
+    size_t head_hidden_size;
+} SingleHeadSelfAttn;
+
+void create_SingleHeadSelfAttn(SingleHeadSelfAttn*, size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, int32_t** weightVector);
+void destroy_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn);
+void compute_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn, int32_t* input, int32_t* output, int32_t* qkv, int32_t* intermediate);
+
+#endif //FVLLMONTITRANSFORMER_SELFATTENTIONC_H
diff --git a/sw/applications/transformer/softmaxC.c b/sw/applications/transformer/softmaxC.c
new file mode 100644
index 00000000..f9f8bd2b
--- /dev/null
+++ b/sw/applications/transformer/softmaxC.c
@@ -0,0 +1,38 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "softmaxC.h"
+
+
+void computeSoftmax(int32_t* input, size_t seq_len) {
+    size_t width = seq_len;
+    float input_float = 0.0f;
+    for (int i = 0; i < seq_len; i++) {
+        // Look for the biggest value of the row
+        int32_t max_val = input[i * seq_len];
+        for (int j = 1; j < width; j++) { // Assuming its squared (width = seq_len)
+            if (input[i * seq_len + j] > max_val) {
+                max_val = input[i * seq_len + j];
+            }
+        }
+        for (int j = 0; j < width; j++) {
+            input[i * seq_len + j] = (int32_t) fmax(input[i * seq_len + j] - max_val, -32767);
+        }
+        // Sum all values on the row
+        int32_t sum = 0;
+        for (int j = 0; j < width; j++) {
+            input_float = (float) input[i * seq_len + j] / (float) (1 << NUM_FRACTION_BITS);
+            input_float = expf(input_float);
+            input[i * seq_len + j] = (int32_t) (input_float * (1 << NUM_FRACTION_BITS));
+            sum += input[i * seq_len + j];
+        }
+        float sum_float = (float) sum / (float) (1 << NUM_FRACTION_BITS);
+        float sum_inv = (float) (1 / (sum_float + 0.00001)); // prevent zero divide!
+        int32_t sum_inv_int = (int32_t) (sum_inv * (1 << NUM_FRACTION_BITS));
+        for (int j = 0; j < width; j++) {
+            input[i * seq_len + j] = (int32_t) MUL(input[i * seq_len + j], sum_inv_int);
+        }
+    }
+}
+
diff --git a/sw/applications/transformer/softmaxC.h b/sw/applications/transformer/softmaxC.h
new file mode 100644
index 00000000..fa47176f
--- /dev/null
+++ b/sw/applications/transformer/softmaxC.h
@@ -0,0 +1,17 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_SOFTMAXC_H
+#define FVLLMONTITRANSFORMER_SOFTMAXC_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <math.h>
+#include <stdlib.h>
+#include "param.h"
+
+void computeSoftmax(int32_t* input, size_t seq_len);
+
+
+#endif //FVLLMONTITRANSFORMER_SOFTMAXC_H
diff --git a/sw/applications/transformer/stftVec.h b/sw/applications/transformer/stftVec.h
new file mode 100644
index 00000000..62243064
--- /dev/null
+++ b/sw/applications/transformer/stftVec.h
@@ -0,0 +1,3 @@
+#include <stdint.h>
+
+int32_t stftVec[49920] = {14912, 16305, 15424, 7300, 9641, 14329, 15823, 14833, 8710, 8912, 12488, 14281, 12956, 9398, 6336, 9702, 11379, 9458, 8448, -1345, 9383, 7575, 5905, 6193, 3111, 9534, 6388, 5963, 4307, 3857, 8353, 3661, 5646, 4840, 2974, 7109, 3348, 5522, 5048, 3034, 7513, 5345, 5058, 3058, 4169, 7233, 5680, 3618, -1939, 4739, 5392, 5531, 33, 3007, 4967, 5296, 5527, 2470, 3793, 5821, 6674, 5596, 4762, 3355, 6805, 6530, 6062, 5061, 3296, 7232, 4892, 6914, 3984, 3459, 7001, 1128, 7354, 1476, 3216, 6049, -4246, 7120, -809, 2509, 4113, 1815, 6269, 1109, 1261, 649, 3559, 4808, 1742, -1118, -2260, 4541, 2638, 1333, -3683, -2573, 5324, 1096, -41, -624, -6914, 5797, 1474, -749, 1036, -1670, 5676, 1178, 1827, 1675, -136, 4838, -524, 2920, 1334, -531, 3606, -5997, 2613, -295, 48, 2645, -2879, 1699, -2664, 1454, 969, -350, 1126, -2504, 1496, -4513, 428, 343, -2119, -288, -2229, 1388, -1021, -1983, -3119, -993, 1492, -842, -2102, -953, -1, -371, 77, -3653, -82, 1169, -1377, 613, -13738, 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-11945, -9380, -10442, -8517, -6628, -10210, -8582, -13365, -9149, -8790, -9812, -9695, -13365, -9380, -13738, -10001, -11004, -11629, -9479, -13365, -9238, -10799, -10442, -10526, -10526, -8060, -11232, -10799, -13049, -7960, -7247, -12319, -12319, -14195, -6653, -6928, -12319, -15615, -13365, -6299, -7113, -12123, -28777, -12776, -6666, -7842, -11629, -28777, -10284, -7865, -9479, -12319, -28777, -8827, -10613, -13049, -14784, -28777, -8903, -17034, -28777, -17034, -14784, -10284, -13365, -13365, -12123, -11629, -12319, -14195, -12123, -11356, -9936, -13365, -28777, -11629, -11945, -9695, -11629, -14195, -11488, -12319, -10799, -10138, -13365, -11781, -10799, -13365, -9873, -14195, -11945, -10284, -12534, -11781, -14784, -12319, -11356, -11232, -28777, -13365, -11488, -17034, -11629, -11115, -10138, -9812, -13738, -13049, -9585, -8790, };
\ No newline at end of file
diff --git a/sw/applications/transformer/tokenPosEmbeddingC.c b/sw/applications/transformer/tokenPosEmbeddingC.c
new file mode 100644
index 00000000..39a63e40
--- /dev/null
+++ b/sw/applications/transformer/tokenPosEmbeddingC.c
@@ -0,0 +1,33 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "tokenPosEmbeddingC.h"
+
+
+void createTokenPosEmbedding(TokenPosEmbedding* tokenPosEmbedding, quant_bit_width* pos_matrix, quant_bit_width* cls_token_vector, size_t seq_len, size_t input_dim, size_t pos_matrix_dim) {
+    tokenPosEmbedding->cls_token_vector_ = cls_token_vector;
+    tokenPosEmbedding->pos_matrix_ = pos_matrix;
+    tokenPosEmbedding->seq_len_ = seq_len;
+    tokenPosEmbedding->input_dim_ = input_dim;
+}
+
+void clsConcatenate(TokenPosEmbedding* tpe, quant_bit_width* input, quant_bit_width* concatenated_input) {
+    // Copy cls_token_ into the concatenated array column-wise at the beginning
+    for (size_t i = 0; i < tpe->input_dim_; ++i) {
+        concatenated_input[i] = tpe->cls_token_vector_[i];
+    }
+    // Copy the input array into the concatenated array
+    for (size_t i = 0; i < tpe->seq_len_ * tpe->input_dim_; ++i) {
+        concatenated_input[i + tpe->input_dim_] = input[i];
+    }
+}
+
+void posEmbedding(TokenPosEmbedding* tpe, quant_bit_width* input) {
+    for (size_t i = 0; i < (tpe->seq_len_ + 1); ++i) {
+        for (size_t j = 0; j < tpe->input_dim_; ++j) {
+            input[i * tpe->input_dim_+ j] += tpe->pos_matrix_[i * tpe->input_dim_ + j];
+        }
+    }
+}
+
diff --git a/sw/applications/transformer/tokenPosEmbeddingC.h b/sw/applications/transformer/tokenPosEmbeddingC.h
new file mode 100644
index 00000000..9357a153
--- /dev/null
+++ b/sw/applications/transformer/tokenPosEmbeddingC.h
@@ -0,0 +1,24 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TOKENPOSEMBEDDINGC_H
+#define FVLLMONTITRANSFORMER_TOKENPOSEMBEDDINGC_H
+
+#include "param.h"
+#include "stdlib.h"
+
+typedef struct{
+    quant_bit_width* cls_token_vector_;
+    quant_bit_width* pos_matrix_;
+    size_t seq_len_;
+    size_t input_dim_;
+} TokenPosEmbedding;
+
+
+void createTokenPosEmbedding(TokenPosEmbedding*, quant_bit_width* pos_matrix, quant_bit_width* cls_token_vector, size_t seq_len, size_t input_dim, size_t pos_matrix_dim);
+void clsConcatenate(TokenPosEmbedding* tpe, quant_bit_width* input, quant_bit_width* concatenated_input);
+void posEmbedding(TokenPosEmbedding* tpe, quant_bit_width* input);
+
+
+#endif //FVLLMONTITRANSFORMER_TOKENPOSEMBEDDINGC_H
diff --git a/sw/applications/transformer/transformerBlockC.c b/sw/applications/transformer/transformerBlockC.c
new file mode 100644
index 00000000..4d7a5fdb
--- /dev/null
+++ b/sw/applications/transformer/transformerBlockC.c
@@ -0,0 +1,115 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include <stdio.h>
+#include "transformerBlockC.h"
+#include "multiply_cgra.h"
+
+SingleHeadSelfAttn global_selfatten [NUM_LAYERS * NUM_HEAD];
+Dense global_query_layer[NUM_LAYERS * NUM_HEAD];
+Dense global_key_layer[NUM_LAYERS * NUM_HEAD];
+Dense global_value_layer[NUM_LAYERS * NUM_HEAD];
+
+Dense global_condense[NUM_LAYERS];
+Dense global_patch;
+Dense global_FF[NUM_LAYERS * 2];
+Dense global_mlp;
+
+TransformerBlock  global_transformer_block;
+TokenPosEmbedding  global_token_embedding;
+
+TransformerBlock* createTransformerBlock(size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, size_t num_heads, size_t ff_size, int32_t** weightVector, int32_t** biasVector, int32_t* clsTokenVector, int32_t* posMatrix) {
+    TransformerBlock* transformerBlock = &global_transformer_block;
+    transformerBlock->num_heads_ = num_heads;
+    transformerBlock->head_hidden_size_ = head_hidden_size;
+    transformerBlock->input_dim_ = input_dim;
+    transformerBlock->ff_size_ = ff_size;
+
+    transformerBlock->addNorm = createAddNormalize(pre_seq_len, D_EMBEDDING, weightVector[0], biasVector[0]);
+    transformerBlock->patchEmbedding = &global_patch;
+    createDense(transformerBlock->patchEmbedding, D_EMBEDDING, D_MODEL, weightVector[1], biasVector[1]);
+    transformerBlock->addNorm2 = createAddNormalize(pre_seq_len, D_MODEL, weightVector[2], biasVector[2]);
+    transformerBlock->token = &global_token_embedding;
+    createTokenPosEmbedding(transformerBlock->token, posMatrix, clsTokenVector, pre_seq_len, input_dim, D_SEQ + 1);
+
+    for (int l = 0; l < 4; l++) {
+        transformerBlock->transformer_layer_0_addNorm[l] = createAddNormalize((pre_seq_len + 1), D_MODEL, weightVector[l * 17 + 3], biasVector[l * 17 + 3]);
+
+        for (int n = 0; n < num_heads; n++) {
+            transformerBlock->selfatten[l * num_heads + n] = &global_selfatten[l * num_heads + n];
+            transformerBlock->selfatten[l * num_heads + n]->query_layer = &global_query_layer[l * num_heads + n];
+            transformerBlock->selfatten[l * num_heads + n]->key_layer = &global_key_layer[l * num_heads + n];
+            transformerBlock->selfatten[l * num_heads + n]->value_layer = &global_value_layer[l * num_heads + n];
+
+            create_SingleHeadSelfAttn(transformerBlock->selfatten[l * num_heads + n], (pre_seq_len + 1), input_dim, head_hidden_size, weightVector + l * 17 + 4 + n * 3);
+        }
+
+        transformerBlock->condense[l] = &global_condense[l];
+        createDense(transformerBlock->condense[l], num_heads * head_hidden_size, input_dim, weightVector[l * 17 + num_heads * 3 + 4], biasVector[l * 17 + num_heads * 3 + 4]);
+
+        transformerBlock->transformer_layer_1_addNorm[l] = createAddNormalize((pre_seq_len + 1), input_dim, weightVector[l * 17 + num_heads * 3 + 5], biasVector[l * 17 + num_heads * 3 + 5]);
+
+        transformerBlock->feedForward0[l] = &global_FF[2*l];
+        createDense(transformerBlock->feedForward0[l], input_dim, ff_size, weightVector[l * 17 + num_heads * 3 + 6], biasVector[l * 17 + num_heads * 3 + 6]);
+
+        transformerBlock->feedForward1[l] = &global_FF[2*l + 1];
+        createDense(transformerBlock->feedForward1[l], ff_size, input_dim, weightVector[l * 17 + num_heads * 3 + 7], biasVector[l * 17 + num_heads * 3 + 7]);
+    }
+
+    transformerBlock->mlp_head_norm = createAddNormalize(1, D_MODEL, weightVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 8], biasVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 8]);
+
+    transformerBlock->mlp_head_linear = &global_mlp;
+    createDense(transformerBlock->mlp_head_linear, D_MODEL, D_MODEL, weightVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 9], biasVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 9]);
+
+    return transformerBlock;
+}
+
+
+void destroyTransformerBlock(TransformerBlock* transformerBlock) {
+    // Free dynamically allocated memory
+
+    free(transformerBlock);
+}
+
+void computeFixedPoint(TransformerBlock* transformerBlock, size_t seq_len, quant_bit_width * input,
+                       quant_bit_width * input_normalized, quant_bit_width * output,
+                       quant_bit_width* intermediate, quant_bit_width* qkv, void * kperf) {
+
+    printf("\rStep 1\n");
+    normalize(&transformerBlock->addNorm, input, input);
+    computeDense(transformerBlock->patchEmbedding, seq_len, input, output); // 120x400x16
+    normalize(&transformerBlock->addNorm2, output, output);
+
+    clsConcatenate(transformerBlock->token, output, input);
+    seq_len++;
+    posEmbedding(transformerBlock->token, input);
+
+    printf("\rStep 2\n");
+    for (int l = 0; l < 4; l++) {
+        normalize(&transformerBlock->transformer_layer_0_addNorm[l], input, input_normalized);
+        for (int n = 0; n < NUM_HEAD; n++) {
+            printf("\rStep 3\n");
+            compute_SingleHeadSelfAttn(transformerBlock->selfatten[l * NUM_HEAD + n], input_normalized,
+                                       output + n * (seq_len * transformerBlock->head_hidden_size_), qkv, intermediate);
+//            destroy_SingleHeadSelfAttn(transformerBlock->selfatten[l * NUM_HEAD + n]);
+        }
+        printf("\rStep 4\n");
+        multihead_transpose(output, intermediate, seq_len, transformerBlock->head_hidden_size_, transformerBlock->num_heads_);
+
+        computeDense(transformerBlock->condense[l], seq_len +3, intermediate, output); // 121x16x16
+
+        add(input, output, seq_len, transformerBlock->input_dim_ );
+
+        normalize(&transformerBlock->transformer_layer_1_addNorm[l], input, input_normalized);
+        computeDense(transformerBlock->feedForward0[l], seq_len +3, input_normalized, intermediate); // 121x16x4
+        activation(transformerBlock->feedForward0[l], seq_len * transformerBlock->ff_size_, intermediate, intermediate);
+
+        computeDense(transformerBlock->feedForward1[l], seq_len +3, intermediate, output); // 121x4x16
+        add(input, output, seq_len, transformerBlock->input_dim_ );
+    }
+    printf("\rStep 5\n");
+    normalize(&transformerBlock->mlp_head_norm, input, input_normalized);
+    computeDense(transformerBlock->mlp_head_linear, 1, input_normalized, output); // 1x16x16
+}
+
diff --git a/sw/applications/transformer/transformerBlockC.h b/sw/applications/transformer/transformerBlockC.h
new file mode 100644
index 00000000..0663f92a
--- /dev/null
+++ b/sw/applications/transformer/transformerBlockC.h
@@ -0,0 +1,48 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TRANSFORMERBLOCK_H
+#define FVLLMONTITRANSFORMER_TRANSFORMERBLOCK_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include "selfattentionC.h"
+#include "addNormC.h"
+#include "dense_layerC.h"
+#include "tokenPosEmbeddingC.h"
+#include "param.h"
+#include "transposeC.h"
+#include "cgra.h"
+
+typedef struct {
+    size_t num_heads_;
+    size_t head_hidden_size_;
+    size_t input_dim_;
+    size_t ff_size_;
+    SingleHeadSelfAttn* selfatten[NUM_LAYERS*NUM_HEAD];
+    int32_t* multihead_out;
+    int32_t* condense_out;
+    int32_t* intermediateFF;
+    int32_t* intermediateFFBlockWise;
+    AddNormalize addNorm;
+    AddNormalize addNorm2;
+    AddNormalize transformer_layer_0_addNorm[NUM_LAYERS];
+    AddNormalize transformer_layer_1_addNorm[NUM_LAYERS];
+    AddNormalize mlp_head_norm;
+    TokenPosEmbedding* token;
+    Dense* condense[NUM_LAYERS];
+    Dense* feedForward0[NUM_LAYERS];
+    Dense* feedForward1[NUM_LAYERS];
+    Dense* patchEmbedding;
+    Dense* mlp_head_linear;
+    #ifndef REARRANGE
+    int32_t* multihead_out_reshape;
+    #endif
+} TransformerBlock;
+
+TransformerBlock* createTransformerBlock(size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, size_t num_heads, size_t ff_size, int32_t** weightVector, int32_t** biasVector, int32_t* clsTokenVector, int32_t* posMatrix);
+void destroyTransformerBlock(TransformerBlock* transformerBlock);
+void computeFixedPoint(TransformerBlock* transformerBlock, size_t seq_len, int32_t* input, int32_t* input_normalized, int32_t* output, int32_t* intermediate, int32_t* qkv, void * kperf);
+
+#endif //FVLLMONTITRANSFORMER_TRANSFORMERBLOCK_H
diff --git a/sw/applications/transformer/transposeC.c b/sw/applications/transformer/transposeC.c
new file mode 100644
index 00000000..2c27aa52
--- /dev/null
+++ b/sw/applications/transformer/transposeC.c
@@ -0,0 +1,31 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "softmaxC.h"
+
+
+void multihead_transpose(const quant_bit_width * input, quant_bit_width* output, size_t seq_len,
+                         size_t head_hidden_size, size_t num_head) {
+    const quant_bit_width * initial_input = input;
+    for (int i=0; i < seq_len; i++){
+        for (int n=0; n< num_head; n++){
+            input = initial_input + i*head_hidden_size + n*seq_len*head_hidden_size;
+            for (int j=0; j < head_hidden_size; j++){
+                *output++ = *input++;
+            }
+        }
+    }
+}
+
+
+void transpose_quant(const quant_bit_width * input, quant_bit_width* output,
+                     size_t width, size_t height) {
+    for (size_t i = 0; i < height; i++) {
+        for (size_t j = 0; j < width; j++) {
+            output[i * width + j] = input[j * height + i];
+        }
+    }
+}
+
+
diff --git a/sw/applications/transformer/transposeC.h b/sw/applications/transformer/transposeC.h
new file mode 100644
index 00000000..500c100e
--- /dev/null
+++ b/sw/applications/transformer/transposeC.h
@@ -0,0 +1,22 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TRANSPOSEC_H
+#define FVLLMONTITRANSFORMER_TRANSPOSEC_H
+
+
+
+#include <stddef.h>
+#include "param.h"
+
+// Replace class with struct
+typedef struct {
+    // struct members
+} Transpose;
+
+// Function prototypes
+void transpose_quant(const quant_bit_width* input, quant_bit_width* output, size_t width, size_t height);
+void multihead_transpose(const quant_bit_width * input, quant_bit_width* output, size_t seq_len, size_t head_hidden_size, size_t num_head);
+
+#endif //FVLLMONTITRANSFORMER_TRANSPOSEC_H
diff --git a/sw/applications/transformer/weightsAndBiasesC.c b/sw/applications/transformer/weightsAndBiasesC.c
new file mode 100644
index 00000000..2fd600f0
--- /dev/null
+++ b/sw/applications/transformer/weightsAndBiasesC.c
@@ -0,0 +1,181 @@
+//
+// Created by alireza on 10/6/23.
+//
+#include "weightsAndBiasesC.h"
+#include <stdint.h>
+#include <stddef.h>
+#include "data_cpp/data.cpp"
+
+void getWeights(quant_bit_width * weightVec[]){
+
+    int weightVectorIndex = 0;
+    weightVec[weightVectorIndex++] = to_patch_embedding_layer_norm1_weight;
+    weightVec[weightVectorIndex++] = to_patch_embedding_linear_weight;
+    weightVec[weightVectorIndex++] = to_patch_embedding_layer_norm2_weight;
+
+
+    /* *************************** Layer 1 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_0_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_0_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_0_1_fn_ff2_weight;
+
+    /* *************************** Layer 2 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_1_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_1_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_1_1_fn_ff2_weight;
+
+    /* *************************** Layer 3 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_2_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_2_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_2_1_fn_ff2_weight;
+
+    /* *************************** Layer 4 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_3_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_3_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_3_1_fn_ff2_weight;
+
+    /* *************************** MLP HEAD ***************************** */
+    weightVec[weightVectorIndex++] = mlp_head_layer_norm_weight;
+    weightVec[weightVectorIndex++] = mlp_head_linear_weight;
+
+}
+
+void getBiases(quant_bit_width * biasVec[]){
+    int biasVectorIndex = 0;
+    biasVec[biasVectorIndex++] = to_patch_embedding_layer_norm1_bias;
+    biasVec[biasVectorIndex++] = to_patch_embedding_linear_bias;
+    biasVec[biasVectorIndex++] = to_patch_embedding_layer_norm2_bias;
+
+    /* *************************** Layer 1 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_0_0_norm_bias;
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_0_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_0_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_0_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_0_1_fn_ff2_bias;
+
+    /* *************************** Layer 2 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_1_0_norm_bias;
+
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_1_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_1_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_1_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_1_1_fn_ff2_bias;
+
+    /* *************************** Layer 3 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_2_0_norm_bias;
+
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_2_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_2_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_2_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_2_1_fn_ff2_bias;
+
+    /* *************************** Layer 4 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_3_0_norm_bias;
+
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_3_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_3_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_3_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_3_1_fn_ff2_bias;
+
+    /* *************************** MLP HEAD ***************************** */
+    biasVec[biasVectorIndex++] = mlp_head_layer_norm_bias;
+    biasVec[biasVectorIndex++] = mlp_head_linear_bias;
+}
+
+quant_bit_width * getPosEmbedding(){
+    quant_bit_width * posMatrix;
+    posMatrix = pos_embedding;
+    return posMatrix;
+}
+
+quant_bit_width * getClassToken(){
+    quant_bit_width * clsTokenVector;
+    clsTokenVector = cls_token;
+    return clsTokenVector;
+}
+
+
diff --git a/sw/applications/transformer/weightsAndBiasesC.h b/sw/applications/transformer/weightsAndBiasesC.h
new file mode 100644
index 00000000..b16d6468
--- /dev/null
+++ b/sw/applications/transformer/weightsAndBiasesC.h
@@ -0,0 +1,15 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_WEIGHTSANDBIASESC_H
+#define FVLLMONTITRANSFORMER_WEIGHTSANDBIASESC_H
+
+#include "param.h"
+
+void getWeights(quant_bit_width * weightVec[]);
+void getBiases(quant_bit_width * biasVec[]);
+quant_bit_width * getPosEmbedding();
+quant_bit_width * getClassToken();
+
+#endif //FVLLMONTITRANSFORMER_WEIGHTSANDBIASESC_H

From 2dc4e61b9abf41eba6eafcf7977b8c40de0bc336 Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Mon, 1 Jul 2024 12:31:40 +0200
Subject: [PATCH 12/27] add transformer example

---
 sw/applications/transformer/SYLT-FFT/LICENSE  |  48 ++
 .../transformer/SYLT-FFT/README.md            |  59 +++
 sw/applications/transformer/SYLT-FFT/config.h |  88 ++++
 sw/applications/transformer/SYLT-FFT/fft.h    | 423 ++++++++++++++++++
 sw/applications/transformer/SYLT-FFT/fpmath.h | 139 ++++++
 .../transformer/SYLT-FFT/intrinsics.h         | 153 +++++++
 sw/applications/transformer/SYLT-FFT/main.c   |  74 +++
 7 files changed, 984 insertions(+)
 create mode 100644 sw/applications/transformer/SYLT-FFT/LICENSE
 create mode 100644 sw/applications/transformer/SYLT-FFT/README.md
 create mode 100644 sw/applications/transformer/SYLT-FFT/config.h
 create mode 100644 sw/applications/transformer/SYLT-FFT/fft.h
 create mode 100644 sw/applications/transformer/SYLT-FFT/fpmath.h
 create mode 100644 sw/applications/transformer/SYLT-FFT/intrinsics.h
 create mode 100644 sw/applications/transformer/SYLT-FFT/main.c

diff --git a/sw/applications/transformer/SYLT-FFT/LICENSE b/sw/applications/transformer/SYLT-FFT/LICENSE
new file mode 100644
index 00000000..f1c15f58
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT/LICENSE
@@ -0,0 +1,48 @@
+MHG (MORAL HIGH GROUND) LICENSE
+
+This software is released under the UNLICENSE license under the single
+condition that good moral standards are maintained in its use.
+
+The term "moral standards" is chosen because it is impossible to define
+legally as it varies with cultural and individual values, principles and
+ideas. Hence, the following may or may not apply.
+
+If you find this software useful - use it in any way you like, but
+consider dropping the author a "thank you" message.
+
+If you want to use this software to earn money - please do, but
+consider mentioning the authors name or making a donation.
+
+If you use this software - consider letting the author know. Simply
+knowing it is being put to good use is often rewarding.
+
+You should consider maintaining open source licensing for software
+that uses or is derived from this software.
+
+
+UNLICENSE
+
+This is free and unencumbered software released into the public domain.
+
+Anyone is free to copy, modify, publish, use, compile, sell, or
+distribute this software, either in source code form or as a compiled
+binary, for any purpose, commercial or non-commercial, and by any
+means.
+
+In jurisdictions that recognize copyright laws, the author or authors
+of this software dedicate any and all copyright interest in the
+software to the public domain. We make this dedication for the benefit
+of the public at large and to the detriment of our heirs and
+successors. We intend this dedication to be an overt act of
+relinquishment in perpetuity of all present and future rights to this
+software under copyright law.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+OTHER DEALINGS IN THE SOFTWARE.
+
+For more information, please refer to <http://unlicense.org/>
\ No newline at end of file
diff --git a/sw/applications/transformer/SYLT-FFT/README.md b/sw/applications/transformer/SYLT-FFT/README.md
new file mode 100644
index 00000000..530a2f31
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT/README.md
@@ -0,0 +1,59 @@
+SYLT-FFT
+========
+DEVSOUND (I)FFT(R) LIBRARY
+-------------------------------------
+<sup>And some other funky fixed-point maths like gray-coding and pow(2, f)</sup>
+
+**Optimized (C-level) for Keil C Compiler and GCC on Cortex-M4.**
+
+**Authors:**
+* D. Taylor 2014 (gmail: senseitg)
+
+**License:**
+* MHG (GPL compatible) - see LICENSE
+
+**Features:**
+* FFT (Fast Fourier Transform) and IFFT (Inverse FFT)
+* Fixed-point 32-bit, Radix-2
+*	Complex or real (with slight conversion overhead) data
+* No plan construction required before (I)FFT
+* No reliance on other libraries (including libm if using precomputed tables)
+
+**Options (config.h):**
+* DIT (decimation-in-time) or DIF (decimation-in-frequency)
+* Rounding on divide (-speed, +accuracy)
+* Saturating math (-speed, +stability)
+* Table size vs. max. FFT length
+
+**Resource requirements:**
+* Minimal memory requirements (in-place)
+* Minimal stack use (non-recursive)
+* Minimal twiddle tables (512 bytes for max N=512 FFT)
+
+**Notes:**
+* Designed for optimal performance, not optimal accuracy
+
+**Caveats:**
+* Care must be taken with input data to ensure no overflows
+* Requires C99 (-std=c99 for GCC)
+
+**Performance:**
+* Comparing against: CMSIS DSP arm_cortexM4I_math.lib(1.4.2)
+* Platform: Freescale Kinetis K20 (Cortex-M4/ARMv7E-M)
+* KEIL = Keil C Compiler 5.01 -O3
+* GCC  = GNU Tools for ARM Embedded Processors 4.8.4 -O3
+
+```
+Comparisons are of speed, +N% = faster than CMSIS, -N% = slower.
+Please verify and do additional tests to add to the list.
+
+  CMSIS-DSP             SYLT-FFT      N     KEIL     GCC
+* arm_cfft_radix2_q31   fft_inverse   256   +25.6%   +15.1%
+```
+
+**Thanks to:**
+* [Wikipedia](http://www.wikipedia.org/) - for existing and taking donations
+* [KATJA](http://www.katjaas.nl/) - for intelligible merge/split spectra algorithm
+* [XCORE](https://github.com/xcore/) - for intelligible (I)FFT algorithm
+*	[CMLAB](http://www.cmlab.csie.ntu.edu.tw/cml/dsp/training/coding/transform/fft.html) - for intelligible FFT algorithm breakdown
+* [BEVAN](http://web.ece.ucdavis.edu/~bbaas/281/slides/Handout.fft2.pdf) - for intelligible DIT vs. DIF, radix-2 vs. 4 overview
diff --git a/sw/applications/transformer/SYLT-FFT/config.h b/sw/applications/transformer/SYLT-FFT/config.h
new file mode 100644
index 00000000..a55673dd
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT/config.h
@@ -0,0 +1,88 @@
+// CONFIGURATION FILE
+// D. TAYLOR 2014
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include "stdint.h"
+#include "stdbool.h"
+
+#ifndef __INLINE
+#if defined(__GNUC__)
+#define __INLINE __attribute__((always_inline)) inline
+#else
+#define __INLINE __inline
+#endif
+#endif
+
+
+/* == MATH CONFIGURE =============================================== */
+
+#define FPOW2_FBITS        27 // Number of fractional bits (1...28)
+#define FPOW2_LIMIT         8 // Limit accuracy to n fractional bits (1...FPOW2_FBITS-1)
+
+#define SINE_BITS           7 // Sine quality (2..14) vs. memory tradeoff
+#define SINE_USE_TABLE      1 // Use pre-computed ROM table (vs. generate in RAM)
+#define SINE_PRINTOUT       0 // Write sine table to screen (PC only)
+
+/* == FFT CONFIGURE =============================================== */
+
+// Maximum FFT size:          4 << SINE_BITS (complex data points)
+// Memory used by sine table: 4 << SINE_BITS (bytes)
+// FFT is faster when SINE_USE_TABLE is 0 (located in RAM)
+
+#define FFT_DIT               // Operation mode, FFT_DIT or FFT_DIF (slower)
+#define FFT_ROUNDING        0 // Perform rounding when dividing (slower)
+#define FFT_SATURATE        0 // Use saturating math where possible (slower)
+
+/* == WAVETABLE CONFIGURE ========================================== */
+
+/* == GLOBAL DATA CONFIGURE ======================================== */
+
+// PI
+#ifndef M_PI
+#define M_PI 3.14159265358979323846
+#endif
+
+// LUT for sine wave, first quadrant only
+#if SINE_USE_TABLE
+// == PLACE GENERATED SINE TABLE HERE ======================== //
+// ROM
+#if SINE_BITS != 7
+#error "sinetable[] size does not match SINE_BITS"
+#endif
+const int32_t sinetable[] = {
+  0x00000000, 0x01921d1f, 0x03242abe, 0x04b6195d, 0x0647d97c, 0x07d95b9e, 0x096a9049, 0x0afb6805,
+  0x0c8bd35e, 0x0e1bc2e3, 0x0fab272b, 0x1139f0ce, 0x12c8106e, 0x145576b1, 0x15e21444, 0x176dd9de,
+  0x18f8b83c, 0x1a82a025, 0x1c0b826a, 0x1d934fe5, 0x1f19f97b, 0x209f701c, 0x2223a4c5, 0x23a6887e,
+  0x25280c5d, 0x26a82185, 0x2826b928, 0x29a3c484, 0x2b1f34eb, 0x2c98fbba, 0x2e110a61, 0x2f875262,
+  0x30fbc54d, 0x326e54c7, 0x33def287, 0x354d9056, 0x36ba2013, 0x382493b0, 0x398cdd32, 0x3af2eeb7,
+  0x3c56ba70, 0x3db832a5, 0x3f1749b7, 0x4073f21d, 0x41ce1e64, 0x4325c135, 0x447acd50, 0x45cd358f,
+  0x471cece6, 0x4869e664, 0x49b41533, 0x4afb6c97, 0x4c3fdff3, 0x4d8162c4, 0x4ebfe8a4, 0x4ffb654d,
+  0x5133cc94, 0x5269126e, 0x539b2aef, 0x54ca0a4a, 0x55f5a4d2, 0x571deef9, 0x5842dd54, 0x59646497,
+  0x5a827999, 0x5b9d1153, 0x5cb420df, 0x5dc79d7c, 0x5ed77c89, 0x5fe3b38d, 0x60ec382f, 0x61f1003e,
+  0x62f201ac, 0x63ef328f, 0x64e88926, 0x65ddfbd3, 0x66cf811f, 0x67bd0fbc, 0x68a69e81, 0x698c246c,
+  0x6a6d98a4, 0x6b4af278, 0x6c242960, 0x6cf934fb, 0x6dca0d14, 0x6e96a99c, 0x6f5f02b1, 0x70231099,
+  0x70e2cbc6, 0x719e2cd2, 0x72552c84, 0x7307c3cf, 0x73b5ebd0, 0x745f9dd0, 0x7504d345, 0x75a585cf,
+  0x7641af3c, 0x76d94988, 0x776c4edb, 0x77fab988, 0x78848413, 0x7909a92c, 0x798a23b1, 0x7a05eead,
+  0x7a7d055b, 0x7aef6323, 0x7b5d039d, 0x7bc5e28f, 0x7c29fbee, 0x7c894bdd, 0x7ce3ceb1, 0x7d3980ec,
+  0x7d8a5f3f, 0x7dd6668e, 0x7e1d93e9, 0x7e5fe493, 0x7e9d55fc, 0x7ed5e5c6, 0x7f0991c3, 0x7f3857f5,
+  0x7f62368f, 0x7f872bf2, 0x7fa736b4, 0x7fc25596, 0x7fd8878d, 0x7fe9cbbf, 0x7ff62182, 0x7ffd885a,
+  0x7fffffff, // <= space potato!
+}; // <= sad monkey?
+// == END OF GENERATED SINE TABLE ============================ //
+#else
+// RAM
+int32_t sinetable[(1 << SINE_BITS) + 1];
+#endif
+
+// LUT for pow(2, fixedpoint)
+// Only need to define up to FPOW2_LIMIT
+const int32_t fpow2table[] = {
+  0x6a09e668, 0x306fe0a3, 0x172b83c8, 0x0b5586d0, 0x059b0d31, 0x02c9a3e7, 0x0163daa0, 0x00b1afa6,
+/*0x0058c86e, 0x002c605e, 0x00162f39, 0x000b175f, 0x00058ba0, 0x0002c5cc, 0x000162e5, 0x0000b172,
+  0x000058b9, 0x00002c5d, 0x0000162e, 0x00000b17, 0x0000058c, 0x000002c6, 0x00000163, 0x000000b1,
+  0x00000059, 0x0000002c, 0x00000016, 0x0000000b, 0x00000006, 0x00000003, 0x00000001, 0x00000001,*/
+};
+
+#endif
diff --git a/sw/applications/transformer/SYLT-FFT/fft.h b/sw/applications/transformer/SYLT-FFT/fft.h
new file mode 100644
index 00000000..d6fb3ba7
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT/fft.h
@@ -0,0 +1,423 @@
+// (I)FFT(R)
+// D. TAYLOR 2014
+
+#ifndef __FFT_H__
+#define __FFT_H__
+
+#include "config.h"
+#include "intrinsics.h"
+#include "fpmath.h"
+
+/* == DECLARATIONS ================================================ */
+
+// Fixed-point data type
+typedef int32_t fft_t;
+
+// Complex number type
+typedef struct {
+  fft_t r, i;
+} fft_complex_t;
+
+// Readability macros
+#define FFT_QCOS(K, SH) sinetable[(1 << SINE_BITS) - (K << SH)]
+#define FFT_QSIN(K, SH) sinetable[K << SH]
+
+#if !((defined FFT_DIT) | (defined FFT_DIF))
+#error "Must define FFT_DIT or FFT_DIF"
+#endif
+
+
+/* == CODING STYLE DEFINITIONS ==================================== */
+
+// GCC/ARMCC require different coding styles for optimal performance.
+// These defines unify the different styles into one syntax.
+
+// # Optimal performance on ARMCC (Keil) #
+#if defined(__ARMCC_VERSION)
+// Declare complex, assign complex
+#define FFT_DECLC(VAR, ASG)  fft_complex_t VAR = ASG;
+// Declare complex, assign real, imaginary
+#define FFT_DECLR(VAR, R, I) fft_complex_t VAR = (fft_complex_t){ .r = R, .i = I };
+// Assign real, imaginary
+#define FFT_ASSGN(VAR, R, I) VAR = (fft_complex_t){ .r = R, .i = I };
+// Access real, imaginary
+#define FFT(VAR, SUB) VAR.SUB
+#endif
+
+// # Optimal performance on GCC #
+#if defined(__GNUC__)
+// Declare complex, assign complex
+#define FFT_DECLC(VAR, ASG)  fft_t VAR##r = ASG.r, VAR##i = ASG.i;
+// Declare complex, assign real, imaginary
+#define FFT_DECLR(VAR, R, I) fft_t VAR##r = R, VAR##i = I;
+// Assign real, imaginary
+#define FFT_ASSGN(VAR, R, I) VAR.r = R; VAR.i = I;
+// Access real, imaginary
+#define FFT(VAR, SUB) VAR##SUB
+#endif
+
+#if FFT_SATURATE
+#define FFT_A(A,B)    qadd(A, B)       // A + B (saturating)
+#define FFT_S(A,B)    qsub(A, B)       // A - B (saturating)
+#define FFT_M2(W)     qadd(W, W)       // W * 2 (saturating)
+#else
+#define FFT_A(A,B)    ((A) + (B))      // A + B
+#define FFT_S(A,B)    ((A) - (B))      // A - B
+#define FFT_M2(W)     ((W) << 1)       // W * 2
+#endif
+#define FFT_M(A,B)    smmulr(A, B)     // A * B
+#define FFT_MA(A,B,C) smmlar(A, B, C)  // C + (A * B)
+#define FFT_MS(A,B,C) smmlsr(A, B, C)  // C - (A * B)
+#if FFT_ROUNDING
+#define FFT_D2(W)     (((W) + 1) >> 1) // W / 2 (rounded)
+#else
+#define FFT_D2(W)     ((W) >> 1)       // W / 2
+#endif
+
+/* == FORWARD AND INVERSE FFT ===================================== */
+
+// Forward FFT transform
+// Permutation must be performed prior to (DIT)/after (DIF) call
+void fft_forward(fft_complex_t data[], unsigned bits) {
+  unsigned size = 1 << bits;
+#ifdef FFT_DIT
+  unsigned shift = SINE_BITS + 1;
+  for(unsigned stride = 2 ; stride <= size; stride <<= 1, shift--) {
+#else//FFT_DIF
+  unsigned shift = SINE_BITS - (bits - 2);
+  for(unsigned stride = size; stride >= 2; stride >>= 1, shift++) {
+#endif
+    // Twiddle and combine for k = 0, having trivial (0 and 1) twiddle factors
+    for(unsigned a = 0; a < size; a += stride) {
+      unsigned b = a + (stride >> 1);
+/*
+      FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+      // # Radix-2 DIT/DIF trivial butterfly #
+      FFT_ASSGN(data[a], FFT_D2(FFT_ADD(FFT(A,r), FFT(B,r))), FFT_D2(FFT_ADD(FFT(A,i), FFT(B,i))));
+      FFT_ASSGN(data[b], FFT_D2(FFT_SUB(FFT(A,r), FFT(B,r))), FFT_D2(FFT_SUB(FFT(A,i), FFT(B,i))));
+*/
+      // Special case: GCC optimizes ARMCC style better here
+      fft_complex_t A = data[a], B = data[b];
+      // # Radix-2 DIT/DIF trivial butterfly #
+      data[a] = (fft_complex_t){ .r = FFT_D2(FFT_A(A.r, B.r)), .i = FFT_D2(FFT_A(A.i, B.i)) };
+      data[b] = (fft_complex_t){ .r = FFT_D2(FFT_S(A.r, B.r)), .i = FFT_D2(FFT_S(A.i, B.i)) };
+    }
+    if(!(stride & 2)) {
+      for(unsigned a = (stride >> 2); a < (stride >> 2) + size; a += stride) {
+        unsigned b = a + (stride >> 1);
+        FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+#ifdef FFT_DIT
+        // # Radix-2 DIT trivial butterfly #
+        FFT_ASSGN(data[a], FFT_D2(FFT_A(FFT(A,r), FFT(B,i))), FFT_D2(FFT_S(FFT(A,i), FFT(B,r))));
+        FFT_ASSGN(data[b], FFT_D2(FFT_S(FFT(A,r), FFT(B,i))), FFT_D2(FFT_A(FFT(A,i), FFT(B,r))));
+#else//FFT_DIF
+        // # Radix-2 DIF trivial butterfly #
+        FFT_ASSGN(data[a], FFT_D2(FFT_A(FFT(A,r), FFT(B,r))), FFT_D2(FFT_A(FFT(A,i), FFT(B,i))));
+        FFT_ASSGN(data[b], FFT_D2(FFT_S(FFT(A,i), FFT(B,i))), FFT_D2(FFT_S(FFT(B,r), FFT(A,r))));
+#endif
+      }
+    }
+    // Twiddle and combine
+    for(unsigned k = 1; k < (stride >> 2); k++) {
+      FFT_DECLR(W, FFT_QCOS(k, shift), FFT_QSIN(k, shift));
+      for(unsigned a = k, b; a < size; a += (stride >> 2) + (stride >> 1)) {
+        b = a + (stride >> 1);
+        { // These two blocks prevent the compiler from confusing...
+          FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+#ifdef FFT_DIT
+          // # Radix-2 DIT butterfly #
+          FFT_DECLR(BW, FFT_MA(FFT(B,i), FFT(W,i), FFT_M(FFT(B,r), FFT(W,r))),
+                        FFT_MS(FFT(B,r), FFT(W,i), FFT_M(FFT(B,i), FFT(W,r))));
+          FFT_ASSGN(data[a], FFT_A(FFT_D2(FFT(A,r)), FFT(BW,r)), FFT_A(FFT_D2(FFT(A,i)), FFT(BW,i)));
+          FFT_ASSGN(data[b], FFT_S(FFT_D2(FFT(A,r)), FFT(BW,r)), FFT_S(FFT_D2(FFT(A,i)), FFT(BW,i)));
+#else//FFT_DIF
+          // # Radix-2 DIF butterfly #
+          FFT_ASSGN(data[a], FFT_D2(FFT_A(FFT(A,r), FFT(B,r))), FFT_D2(FFT_A(FFT(A,i), FFT(B,i))));
+          FFT_DECLR(D, FFT_S(FFT(A,r), FFT(B,r)), FFT_S(FFT(A,i), FFT(B,i)));
+          FFT_ASSGN(data[b], FFT_MA(FFT(D,r), FFT(W,r), FFT_M(FFT(D,i), FFT(W,i))),
+                             FFT_MS(FFT(D,r), FFT(W,i), FFT_M(FFT(D,i), FFT(W,r))));
+#endif
+        }
+        a += (stride >> 2); b += (stride >> 2);
+        { // ...register use resulting in more efficient code
+          FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+#ifdef FFT_DIT
+          // # Radix-2 DIT butterfly #
+          FFT_DECLR(BW, FFT_MS(FFT(B,r), FFT(W,i), FFT_M(FFT(B,i), FFT(W,r))),
+                        FFT_MA(FFT(B,i), FFT(W,i), FFT_M(FFT(B,r), FFT(W,r))));
+          FFT_ASSGN(data[a], FFT_A(FFT_D2(FFT(A,r)), FFT(BW,r)), FFT_S(FFT_D2(FFT(A,i)), FFT(BW,i)));
+          FFT_ASSGN(data[b], FFT_S(FFT_D2(FFT(A,r)), FFT(BW,r)), FFT_A(FFT_D2(FFT(A,i)), FFT(BW,i)));
+#else//FFT_DIF
+          // # Radix-2 DIF butterfly #
+          FFT_ASSGN(data[a], FFT_D2(FFT_A(FFT(A,r), FFT(B,r))), FFT_D2(FFT_A(FFT(A,i), FFT(B,i))));
+          FFT_DECLR(D, FFT_S(FFT(B,r), FFT(A,r)), FFT_S(FFT(B,i), FFT(A,i)));
+          FFT_ASSGN(data[b], FFT_MS(FFT(D,i), FFT(W,r), FFT_M(FFT(D,r), FFT(W,i))),
+                             FFT_MA(FFT(D,i), FFT(W,i), FFT_M(FFT(D,r), FFT(W,r))));
+#endif
+        }
+      }
+    }
+  }
+}
+
+// Inverse FFT transform
+// Permutation must be performed prior to (DIT)/after (DIF) call
+void fft_inverse(fft_complex_t data[], unsigned bits) {
+  unsigned size = 1 << bits;
+#ifdef FFT_DIT
+  unsigned shift = SINE_BITS + 1;
+  for(unsigned stride = 2 ; stride <= size; stride <<= 1, shift--) {
+#else//FFT_DIF
+  unsigned shift = SINE_BITS - (bits - 2);
+  for(unsigned stride = size; stride >= 2; stride >>= 1, shift++) {
+#endif
+    // Twiddle and combine for k = 0, having trivial (0 and 1) twiddle factors
+    for(unsigned a = 0; a < size; a += stride) {
+      unsigned b = a + (stride >> 1);
+/*
+      FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+      // # Radix-2 DIT/DIF trivial butterfly #
+      FFT_ASSGN(data[a], FFT_A(FFT(A,r), FFT(B,r)), FFT_A(FFT(A,i), FFT(B,i)));
+      FFT_ASSGN(data[b], FFT_S(FFT(A,r), FFT(B,r)), FFT_S(FFT(A,i), FFT(B,i)));
+*/
+      // Special case: GCC optimizes ARMCC style better here
+      fft_complex_t A = data[a], B = data[b];
+      // # Radix-2 DIT/DIF trivial butterfly #
+      data[a] = (fft_complex_t){ .r = FFT_A(A.r, B.r), .i = FFT_A(A.i, B.i) };
+      data[b] = (fft_complex_t){ .r = FFT_S(A.r, B.r), .i = FFT_S(A.i, B.i) };
+    }
+    if(!(stride & 2)) {
+      for(unsigned a = (stride >> 2); a < size; a += stride) {
+        unsigned b = a + (stride >> 1);
+        FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+#ifdef FFT_DIT
+        // # Radix-2 DIT trivial butterfly #
+        FFT_ASSGN(data[a], FFT_S(FFT(A,r), FFT(B,i)), FFT_A(FFT(A,i), FFT(B,r)));
+        FFT_ASSGN(data[b], FFT_A(FFT(A,r), FFT(B,i)), FFT_S(FFT(A,i), FFT(B,r)));
+#else//FFT_DIF
+        // # Radix-2 DIF trivial butterfly #
+        FFT_ASSGN(data[a], FFT_A(FFT(A,r), FFT(B,r)), FFT_A(FFT(A,i), FFT(B,i)));
+        FFT_ASSGN(data[b], FFT_S(FFT(B,i), FFT(A,i)), FFT_S(FFT(A,r), FFT(B,r)));
+#endif
+      }
+    }
+    // Twiddle and combine
+    for(unsigned k = 1; k < (stride >> 2); k++) {
+      FFT_DECLR(W, FFT_QCOS(k, shift), FFT_QSIN(k, shift));
+      for(unsigned a = k, b; a < size; a += (stride >> 2) + (stride >> 1)) {
+        b = a + (stride >> 1);
+        { // These two blocks prevent the compiler from confusing...
+          FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+#ifdef FFT_DIT
+          // # Radix-2 DIT butterfly #
+          FFT_DECLR(BW, FFT_MS(FFT(B,r), FFT(W,r), FFT_M(FFT(B,i), FFT(W,i))),
+                        FFT_MA(FFT(B,i), FFT(W,r), FFT_M(FFT(B,r), FFT(W,i))));
+          FFT_ASSGN(data[a], FFT_S(FFT(A,r), FFT_M2(FFT(BW,r))), FFT_A(FFT(A,i), FFT_M2(FFT(BW,i))));
+          FFT_ASSGN(data[b], FFT_A(FFT(A,r), FFT_M2(FFT(BW,r))), FFT_S(FFT(A,i), FFT_M2(FFT(BW,i))));
+#else//FFT_DIF
+          // # Radix-2 DIF butterfly #
+          FFT_ASSGN(data[a], FFT_A(FFT(A,r), FFT(B,r)), FFT_A(FFT(A,i), FFT(B,i)));
+          FFT_DECLR(D, FFT_S(FFT(A,r), FFT(B,r)), FFT_S(FFT(A,i), FFT(B,i)));
+          FFT_ASSGN(data[b], FFT_M2(FFT_MS(FFT(D,i), FFT(W,i), FFT_M(FFT(D,r), FFT(W,r)))),
+                             FFT_M2(FFT_MA(FFT(D,i), FFT(W,r), FFT_M(FFT(D,r), FFT(W,i)))));
+#endif
+        }
+        a += (stride >> 2); b += (stride >> 2);
+        { // ...register use resulting in more efficient code
+          FFT_DECLC(A, data[a]); FFT_DECLC(B, data[b]);
+#ifdef FFT_DIT
+          // # Radix-2 DIT butterfly #
+          FFT_DECLR(BW, FFT_MA(FFT(B,i), FFT(W,r), FFT_M(FFT(B,r), FFT(W,i))),
+                        FFT_MS(FFT(B,r), FFT(W,r), FFT_M(FFT(B,i), FFT(W,i))));
+          FFT_ASSGN(data[a], FFT_S(FFT(A,r), FFT_M2(FFT(BW,r))), FFT_S(FFT(A,i), FFT_M2(FFT(BW,i))));
+          FFT_ASSGN(data[b], FFT_A(FFT(A,r), FFT_M2(FFT(BW,r))), FFT_A(FFT(A,i), FFT_M2(FFT(BW,i))));
+#else//FFT_DIF
+          // # Radix-2 DIF butterfly #
+          FFT_ASSGN(data[a], FFT_A(FFT(A,r), FFT(B,r)), FFT_A(FFT(A,i), FFT(B,i)));
+          FFT_DECLR(D, FFT_S(FFT(A,r), FFT(B,r)), FFT_S(FFT(B,i), FFT(A,i)));
+          FFT_ASSGN(data[b], FFT_M2(FFT_MS(FFT(D,r), FFT(W,i), FFT_M(FFT(D,i), FFT(W,r)))),
+                             FFT_M2(FFT_MA(FFT(D,i), FFT(W,i), FFT_M(FFT(D,r), FFT(W,r)))));
+#endif
+        }
+      }
+    }
+  }
+}
+
+
+/* == DATA SET PROCESSING AND MANIPULATION ======================== */
+
+// Process complex data to produce real-only output
+// This allows us to output N*2 point of real data using a N point complex (I)FFT
+// Even/odd real data will be found in the real/imaginary parts of every output bin upon completion
+void fft_convert(fft_complex_t data[], unsigned bits, bool permutated, bool invert) {
+  unsigned size = 1 << --bits;
+  unsigned shift = SINE_BITS - bits++;
+  unsigned n, z, nc, zc;
+  fft_t rsum, rdif, isum, idif;
+  fft_t itwiddled, rtwiddled;
+  for(nc = zc = size; nc; nc--, zc++) {
+    if(permutated) {
+      n = RBITS(nc, bits); z = RBITS(zc, bits);
+    } else {
+      n = nc; z = zc;
+    }
+    rsum = data[n].r + data[z].r; isum = data[n].i + data[z].i;
+    rdif = data[n].r - data[z].r; idif = data[n].i - data[z].i;
+    fft_t r =  FFT_QCOS(nc, shift); fft_t i = -FFT_QSIN(nc, shift);
+    if(invert) r = -r;
+    rtwiddled = FFT_MA(r, isum, FFT_M(i, rdif)) << 1;
+    itwiddled = FFT_MS(r, rdif, FFT_M(i, isum)) << 1;
+    data[n].r = rsum + rtwiddled; data[n].i = itwiddled + idif;
+    data[z].r = rsum - rtwiddled; data[z].i = itwiddled - idif;
+  }
+  fft_t data_0_tr = data[0].r;
+  data[0].r = (data[0].r + data[0].i); data[0].i = (data_0_tr - data[0].i);
+  if(!invert) { data[0].r <<= 1; data[0].i <<= 1; }
+}
+
+// Perform bit-reversal permutation on data set
+// (Reverses address bits for all data points)
+void fft_permutate(fft_complex_t data[], unsigned bits) {
+  unsigned size  = 1 << bits;
+  unsigned shift = 32 - bits;
+  for(unsigned i = 1; i < size - 1; i++) {
+    unsigned z = rbit(i) >> shift;
+    if(z > i) {
+      fft_t
+      t = data[i].r; data[i].r = data[z].r; data[z].r = t;
+      t = data[i].i; data[i].i = data[z].i; data[z].i = t;
+    }
+  }
+}
+
+
+/* == "HIGH"-LEVEL FUNCTIONS ====================================== */
+
+// Perform forward FFT (including permutation)
+__INLINE
+void fft_fft(fft_complex_t *complex, unsigned bits) {
+#ifdef FFT_DIT
+  fft_permutate(complex, bits);
+#endif
+  fft_forward(complex, bits);
+#ifdef FFT_DIF
+  fft_permutate(complex, bits);
+#endif
+}
+
+// Perform inverse FFT (including permutation)
+__INLINE
+void fft_ifft(fft_complex_t *complex, unsigned bits) {
+#ifdef FFT_DIT
+  fft_permutate(complex, bits);
+#endif
+  fft_inverse(complex, bits);
+#ifdef FFT_DIF
+  fft_permutate(complex, bits);
+#endif
+}
+
+// Perform forward FFT (including permutation, real output conversion)
+__INLINE
+void fft_fftr(fft_complex_t *complex, unsigned bits) {
+  fft_fft(complex, bits);
+  fft_convert(complex, bits, false, false);
+}
+
+// Perform inverse FFT (including permutation, real input conversion)
+__INLINE
+void fft_ifftr(fft_complex_t *complex, unsigned bits) {
+  fft_convert(complex, bits, false, true);
+  fft_ifft(complex, bits);
+}
+
+
+/* == DATA SET CONSTRUCTION ======================================= */
+
+// Magnitude and phase => complex FFT bin [index]
+// A data set built with this method does not require fft_permutate before DIT IFFT
+__INLINE
+void fft_phase_magnitude(fft_complex_t complex[], unsigned bits, unsigned index, int32_t mag, uint32_t pha) {
+#ifdef FFT_DIT
+  unsigned n = RBITS(index, bits);
+#else//FFT_DIF
+  unsigned n = index;
+#endif
+  complex[n].r = FFT_M(mag, sine(pha));
+  complex[n].i = FFT_M(mag, cosine(pha));
+}
+
+// Magnitude, phase:0 => complex FFT bin [index]
+// A data set built with this method does not require fft_permutate before DIT IFFT
+__INLINE
+void fft_magnitude(fft_complex_t complex[], unsigned bits, unsigned index, int32_t mag) {
+#ifdef FFT_DIT
+  unsigned n = RBITS(index, bits);
+#else//FFT_DIF
+  unsigned n = index;
+#endif
+  complex[n].r = 0; complex[n].i = mag;
+}
+
+// REAL Symmetric DC offset => complex FFT bin [0] (DC)
+// A data set built with this method does not require fft_permutate before DIT IFFT
+// A data set built with this method does not require fft_convert before IFFT
+__INLINE
+void fft_real_dc(fft_complex_t data[], fft_t r, fft_t i) {
+  data[0].r = r + i;
+  data[0].i = r - i;
+}
+
+// REAL Symmetric magnitude and phase => complex FFT bins [index], [size-index]
+// A data set built with this method does not require fft_permutate before DIT IFFT
+// A data set built with this method does not require fft_convert before IFFT
+void fft_real_phase_magnitude(fft_complex_t complex[], unsigned bits, unsigned index, int32_t mag_lo, int32_t pha_lo, int32_t mag_hi, int32_t pha_hi) {
+  unsigned size = 1 << bits;
+  unsigned shift = SINE_BITS - (bits - 1);
+#ifdef FFT_DIT
+  unsigned n = RBITS(index, bits);
+  unsigned z = RBITS(size - index, bits);
+#else//FFT_DIF
+  unsigned n = index;
+  unsigned z = size - index;
+#endif
+  fft_t rsum, rdif, isum, idif, r, i;
+  fft_t itwiddled, rtwiddled;
+  r = FFT_M(mag_lo,   sine(pha_lo));
+  i = FFT_M(mag_hi,   sine(pha_hi));
+  rsum = r + i; rdif = r - i;
+  r = FFT_M(mag_lo, cosine(pha_lo));
+  i = FFT_M(mag_hi, cosine(pha_hi));
+  isum = r + i; idif = r - i;
+  r = -FFT_QCOS(index, shift); i = -FFT_QSIN(index, shift);
+  rtwiddled = FFT_MA(r, isum, FFT_M(i, rdif)) << 1;
+  itwiddled = FFT_MS(r, rdif, FFT_M(i, isum)) << 1;
+  complex[n].r = rsum + rtwiddled; complex[n].i = itwiddled + idif;
+  complex[z].r = rsum - rtwiddled; complex[z].i = itwiddled - idif;
+}
+
+// REAL Symmetric magnitude, phase:0 => complex FFT bins [index], [size-index]
+// This method works with permutated (bit-reversed) addressing
+// A data set built with this method does not require fft_permutate before DIT IFFT
+// A data set built with this method does not require fft_convert before IFFT
+void fft_real_magnitude(fft_complex_t complex[], unsigned bits, unsigned index, int32_t mag_lo, int32_t mag_hi) {
+  unsigned shift = SINE_BITS - bits + 1;
+#ifdef FFT_DIT
+  unsigned n = RBITS(index, bits);
+  unsigned z = RBITS((1 << bits) - index, bits);
+#else//FFT_DIF
+  unsigned n = index;
+  unsigned z = (1 << bits) - index;
+#endif
+  fft_t isum, idif, r, i;
+  fft_t itwiddled, rtwiddled;
+  isum = (mag_lo + mag_hi); idif = mag_lo - mag_hi;
+  r = FFT_QCOS(index, shift); i = FFT_QSIN(index, shift);
+  rtwiddled = FFT_M(r, isum) << 1;
+  itwiddled = FFT_M(i, isum) << 1;
+  complex[n].r = -rtwiddled; complex[n].i =  (idif - itwiddled);
+  complex[z].r =  rtwiddled; complex[z].i = -(idif + itwiddled);
+}
+
+#endif
diff --git a/sw/applications/transformer/SYLT-FFT/fpmath.h b/sw/applications/transformer/SYLT-FFT/fpmath.h
new file mode 100644
index 00000000..9385d3c0
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT/fpmath.h
@@ -0,0 +1,139 @@
+// FIXED POINT MATHS
+// D. TAYLOR 2014
+
+#ifndef __FPMATH_H__
+#define __FPMATH_H__
+
+#include "config.h"
+#include "intrinsics.h"
+#include "fpmath.h"
+
+#define SINE_SIZE  (1 << SINE_BITS)         // Sine table size
+#define SINE_FBITS (32 - 2 - SINE_BITS)     // Fractional bits
+#define SINE_FMASK ((1 << SINE_FBITS) - 1)  // Fraction mask
+
+// Linear/box interpolation (30 bit precision)
+// y1 is first point, y2 second
+// mu is interpolation point 00000000-FFFFFFFF
+// floating-point equivalent return y2 - y1 * mu + y1;
+__INLINE
+int32_t linear(int32_t y1, int32_t y2, uint32_t mu) {
+  return smmlar((y2 >> 1) - (y1 >> 1), mu >> 1, y1 >> 2) << 2;
+}
+
+// Cubic interpolation
+// y0...y3 need to be externally limited in range to prevent overflow
+// y0...y3 are control points, interpolation is performed between y1 and y2
+// mu is interpolation point 00000000-FFFFFFFF
+// floating-point equivalent return y1+mu/2*(y2-y0+mu*(2*y0-5*y1+4*y2-y3+mu*(3*(y1-y2)+y3-y0)))
+__INLINE
+int32_t cubic(int32_t y0, int32_t y1, int32_t y2, int32_t y3, uint32_t mu) {
+  mu >>= 1;
+  int32_t a = (3 * (y1 - y2) - y0 + y3);
+  int32_t b = 2 * y2 + y0 - (5 * y1 + y3) / 2;
+  int32_t c = (y2 - y0) / 2;
+  return smmlar(smmlar(smmlar(a, mu, b) << 1, mu, c) << 1, mu, y1);
+}
+
+// Generate first quadrant (0 to PI/2) of sine wave
+// Output table is in Q31 format, with 1 limited to 0x7FFFFFFF
+void sine_init() {
+#if !SINE_USE_TABLE
+  unsigned int n;
+#if SINE_PRINTOUT
+  printf("// ROM\n");
+  printf("#if SINE_BITS != 7\n");
+  printf("#error \"sinetable[] size does not match SINE_BITS\"\n");
+  printf("#endif\n");
+  printf("const int32_t sinetable[] = {");
+#endif
+  for(n = 0; n <= SINE_SIZE; n++) {
+    uint64_t v = (sin(((double)n * M_PI) / (double)(SINE_SIZE * 2)) * 2147483648.0);
+    sinetable[n] = v > 2147483647 ? 2147483647 : v;
+#if SINE_PRINTOUT
+    // Print table
+    if((n & 7) == 0) printf("\n  ");
+    printf("0x%08x, ", sinetable[n]);
+#endif
+  }
+#if SINE_PRINTOUT
+  printf("// <= space potato!\n}; // <= sad monkey?\n");
+#endif
+#endif
+}
+
+// Sin by table lookup with interpolation
+// pos = 00000000 to FFFFFFFF, corresponding to 0-2PI(less one)
+int32_t sine(uint32_t pos) {
+  uint32_t fraction = (pos & SINE_FMASK) << (2 + SINE_BITS);
+  uint32_t index = (pos & 0x40000000) ? (0x40000000 + SINE_FMASK - (pos & 0x3FFFFFFF)) : (pos & 0x3FFFFFFF);
+  uint32_t indexa = index >> SINE_FBITS;
+  uint32_t indexb = pos & 0x40000000 ? indexa - 1 : indexa + 1;
+  int32_t sample = linear(sinetable[indexa], sinetable[indexb], fraction);
+  return pos & 0x80000000 ? -sample : sample;
+}
+
+// Cos by table lookup with interpolation
+// See sine
+__INLINE
+int32_t cosine(uint32_t pos) {
+  return sine(pos + 0x40000000);
+}
+
+// Fast sin by table lookup
+// Same as sine, but no interpolation
+__INLINE
+int32_t fastsin(uint32_t pos) {
+  uint32_t index = (pos & 0x40000000) ? 0x40000000 - (pos & 0x3fffffff) : (pos & 0x3fffffff);
+  int32_t sample = sinetable[index >> SINE_FBITS];
+  return (pos & 0x80000000 ? -sample : sample);
+}
+
+// Fast cos by table lookup
+// See fastsin
+__INLINE
+int32_t fastcos(uint32_t pos) {
+  return fastsin(pos + 0x40000000);
+}
+
+// Fixed point pow(2, e)
+uint64_t fpow2(uint32_t e) {
+  uint32_t ipart = e >> FPOW2_FBITS;
+#ifdef FPOW2_LIMIT
+  uint32_t fpart = (e >> (FPOW2_FBITS - FPOW2_LIMIT)) << (32 - FPOW2_LIMIT);
+#else
+  uint32_t fpart = e << (32 - FPOW2_FBITS);
+#endif
+  uint64_t final = 0x100000000;
+  if(fpart) {
+    uint32_t bit = clz(fpart);
+    uint32_t fcalc = fpow2table[bit++] >> 1;
+    fpart <<= bit;
+    while(fpart) {
+      uint32_t lzc = clz(fpart);
+      bit += lzc++;
+      int32_t fmul = fpow2table[bit++];
+      fcalc += smmlar(fcalc, fmul, fmul >> 1);
+      fpart <<= lzc;
+    }
+    final += (uint64_t)fcalc << 1;
+  }
+  return final << ipart;
+}
+
+// Convert binary to gray-code
+unsigned bin2gray(unsigned bits) {
+  return (bits >> 1) ^ bits;
+}
+
+// Convert gray-code to binary
+unsigned gray2bin(unsigned bits) {
+  bits ^= bits >> 16;
+  bits ^= bits >>  8;
+  bits ^= bits >>  4;
+  bits ^= bits >>  2;
+  bits ^= bits >>  1;
+  return bits;
+}
+
+#endif
diff --git a/sw/applications/transformer/SYLT-FFT/intrinsics.h b/sw/applications/transformer/SYLT-FFT/intrinsics.h
new file mode 100644
index 00000000..e2614bae
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT/intrinsics.h
@@ -0,0 +1,153 @@
+// INTRINSICS
+// D. TAYLOR 2014
+
+#ifndef __INTRINSICS_H__
+#define __INTRINSICS_H__
+#include "config.h"
+
+// issue warnings when not using full hardware acceleration
+
+#if defined(__ARMCC_VERSION) || (defined(__GNUC__) && defined(__arm__))
+#if (__CORTEX_M < 0x03)
+#warning "Cortex-M core < M3 detected; hardware acceleration for math operations not supported"
+#elif (__CORTEX_M < 0x04)
+#warning "Cortex-M core < M4 detected; partial hardware acceleration for math operations supported"
+#endif
+#endif
+
+// reverse bits (ARM: RBIT)
+__INLINE
+uint32_t rbit(uint32_t x) {
+  uint32_t result;
+#if defined(__ARMCC_VERSION) && ((__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300))
+  __asm{ rbit result, x }
+#elif defined(__GNUC__) && defined(__arm__) && ((__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300))
+  __asm("rbit %0, %1":"=r"(result):"r"(x));
+#else
+  x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
+  x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
+  x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
+  x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
+  result = (x >> 16) | (x << 16);
+#endif
+  return result;
+}
+
+#define RBITS(W, BITS) (rbit(W) >> (32 - (BITS)))
+
+// count leading zeroes (ARM: CLZ)
+__INLINE
+uint32_t clz(uint32_t x) {
+  uint32_t result;
+#if defined(__ARMCC_VERSION) && ((__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300))
+  __asm{ clz result, x }
+#elif defined(__GNUC__) && defined(__arm__) && ((__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300))
+  __asm("clz %0, %1":"=r"(result):"r"(x));
+#else
+  x |= x >> 1; x |= x >> 2; x |= x >> 4; x |= x >> 8; x |= x >> 16;
+  x -= 0x55555555 & (x >> 1);
+  x = (0x33333333 & x) + (0x33333333 & (x >> 2));
+  result = 32 - ((0x01010101 * (0x0F0F0F0F & (x + (x >> 4)))) >> 24);
+#endif
+  return result;
+}
+
+// 32-bit signed multiply -> 32-bit result, add 32-bit (ARM: SMMLAR)
+// floating point equivalent: return c + a * b
+__INLINE
+int32_t smmlar(int32_t a, int32_t b, int32_t c) {
+  int32_t result;
+#if defined(__ARMCC_VERSION) && (__CORTEX_M >= 0x04U)
+  __asm{ smmlar result, a, b, c }
+#elif defined(__GNUC__) && defined(__arm__) && (__CORTEX_M >= 0x04U)
+  __asm("smmlar %0, %1, %2, %3":"=r"(result):"r"(a),"r"(b),"r"(c));
+#else
+  result = c + ((((int64_t)a * b) + 0x80000000) >> 32);
+#endif
+  return result;
+}
+
+// 32-bit signed multiply -> 32-bit result, subtract 32-bit (ARM: SMMLSR)
+// floating point equivalent: return c - a * b
+__INLINE
+int32_t smmlsr(int32_t a, int32_t b, int32_t c) {
+  int32_t result;
+#if defined(__ARMCC_VERSION) && (__CORTEX_M >= 0x04U)
+  __asm{ smmlsr result, a, b, c }
+#elif defined(__GNUC__) && defined(__arm__) && (__CORTEX_M >= 0x04U)
+  __asm("smmlsr %0, %1, %2, %3":"=r"(result):"r"(a),"r"(b),"r"(c));
+#else
+  result = c - ((((int64_t)a * b) + 0x80000000) >> 32);
+#endif
+  return result;
+}
+
+// 32-bit signed multiply -> 32-bit result (ARM: SMMULR)
+// floating point equivalent: return a * b
+__INLINE
+int32_t smmulr(int32_t a, int32_t b) {
+  int32_t result;
+#if defined(__ARMCC_VERSION) && (__CORTEX_M >= 0x04U)
+  __asm{ smmulr result, a, b }
+#elif defined(__GNUC__) && defined(__arm__) && (__CORTEX_M >= 0x04U)
+  __asm("smmulr %0, %1, %2":"=r"(result):"r"(a),"r"(b));
+#else
+  result = ((((int64_t)a * b) + 0x80000000) >> 32);
+#endif
+  return result;
+}
+
+// saturating add (ARM: qadd)
+// floating point equivalent: return max(min(a + b, 1), -1)
+__INLINE
+int32_t qadd(int32_t a, int32_t b) {
+  uint32_t result;
+#if defined(__ARMCC_VERSION)
+  __asm{ qadd result, a, b }
+#elif defined(__GNUC__)
+  __asm("qadd %0, %1, %2":"=r"(result):"r"(a),"r"(b));
+#else
+  int64_t c = (int64_t)a + b;
+  if(c >  2147483647) c =  2147483647;
+  if(c < -2147483648) c = -2147483648;
+  result = c;
+#endif
+  return result;
+}
+
+// saturating subtract (ARM: qsub)
+// floating point equivalent: return max(min(a - b, 1), -1)
+__INLINE
+int32_t qsub(int32_t a, int32_t b) {
+  uint32_t result;
+#if defined(__ARMCC_VERSION)
+  __asm{ qsub result, a, b }
+#elif defined(__GNUC__) && defined(__arm__)
+  __asm("qsub %0, %1, %2":"=r"(result):"r"(a),"r"(b));
+#else
+  int64_t c = (int64_t)a - b;
+  if(c >  2147483647) c =  2147483647;
+  if(c < -2147483648) c = -2147483648;
+  result = c;
+#endif
+  return result;
+}
+
+// 32-bit arithmetic shift right with rounding (ARM: ASRS + ADC)
+// floating point equivalent: return v / pow(2, s)
+__INLINE
+int32_t asrr(int32_t v, int32_t s) {
+  int32_t result;
+#if defined(__ARMCC_VERSION)
+  __asm{ asrs result, v, s };
+  __asm{ adc result, result };
+#elif defined(__GNUC__) && defined(__arm__)
+  __asm("asrs %0, %1, %2":"=r"(result):"r"(v),"r"(s):"cc");
+  __asm("adc %0, %1, #0":"=r"(result):"r"(result));
+#else
+  result = (v + (1 << (s - 1))) >> s;
+#endif
+  return result;
+}
+
+#endif
diff --git a/sw/applications/transformer/SYLT-FFT/main.c b/sw/applications/transformer/SYLT-FFT/main.c
new file mode 100644
index 00000000..cf59fcad
--- /dev/null
+++ b/sw/applications/transformer/SYLT-FFT/main.c
@@ -0,0 +1,74 @@
+// BENCHMARKING FOR FRDM-K20D50M
+// D. TAYLOR 2014
+
+// * Do not build with operating system
+// * Uses FTM0 as core clock cycle counter
+// * Requires C99 standard
+
+#define BENCH_RUNS 100 // Not really necessary without OS
+
+#include <MK20D5.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "config.h"
+#include "intrinsics.h"
+#include "fpmath.h"
+#include "fft.h"
+
+static volatile unsigned count_hi; // FTM0 high counter
+static volatile unsigned count;    // Performance counter
+
+// FFT data structure
+fft_complex_t complex[256];
+
+// This function contains code to benchmark
+static void benchmark(void) {
+  fft_inverse(complex, 8);
+}
+
+// Initialize FTM0
+static void bench_init(void) {
+  SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK;
+  FTM0->MOD = 0xFFFF;
+  NVIC_EnableIRQ(FTM0_IRQn);
+}
+
+// Resets cycle counts, begins benchmarking
+__INLINE
+static void bench_begin(void) {
+  FTM0->SC = 0;
+  count_hi = 0;
+  FTM0->CNT = 0;
+  FTM0->SC = FTM_SC_CLKS(1) | FTM_SC_TOIE_MASK;
+}
+
+// Ends benchmarking, returns cycle count
+__INLINE
+static unsigned bench_end(void) {
+  FTM0->SC = 0;
+  return (FTM0->CNT | (count_hi << 16)) - 2;
+}
+
+// FTM0 overflow counter
+void FTM0_IRQHandler(void) {
+  FTM0->SC &= ~FTM_SC_TOF_MASK;
+  count_hi++;
+}
+
+int main() {
+  bench_init();
+  while(1) {
+    // Perform benchmark
+    unsigned ack = 0;
+    for(unsigned n = 0; n < BENCH_RUNS; n++) {
+      bench_begin();
+      benchmark();
+      ack += bench_end();
+    }
+    count = ack / BENCH_RUNS;
+    // Count is reported here - use a breakpoint or add communication code
+    count = count;
+  }
+}

From 052c46b04479309d9de17c862d248ee5fa3c8fd9 Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Thu, 4 Jul 2024 10:19:32 +0200
Subject: [PATCH 13/27] reduced transformer example

---
 sw/applications/trans_versasense/SYLT-FFT     |    1 +
 sw/applications/trans_versasense/addNormC.c   |   71 +
 sw/applications/trans_versasense/addNormC.h   |   26 +
 .../trans_versasense/cgra_bitstream.h         |   12 +
 .../trans_versasense/data_cpp/array_output.h  | 4803 +++++++++++++++++
 .../trans_versasense/data_cpp/data.cpp        |  104 +
 .../trans_versasense/data_cpp/signal.cpp      |    5 +
 .../trans_versasense/data_cpp/signal_fft.cpp  |    5 +
 .../trans_versasense/dense_layerC.c           |   73 +
 .../trans_versasense/dense_layerC.h           |   31 +
 sw/applications/trans_versasense/main.c       |  143 +
 sw/applications/trans_versasense/main.h       |   17 +
 sw/applications/trans_versasense/matMulC.c    |   22 +
 sw/applications/trans_versasense/matMulC.h    |   21 +
 .../trans_versasense/multiply_cgra.c          |  178 +
 .../trans_versasense/multiply_cgra.h          |    6 +
 sw/applications/trans_versasense/param.h      |   26 +
 .../trans_versasense/performance.c            |   62 +
 .../trans_versasense/performance.h            |   64 +
 .../trans_versasense/selfattentionC.c         |   99 +
 .../trans_versasense/selfattentionC.h         |   35 +
 sw/applications/trans_versasense/softmaxC.c   |   38 +
 sw/applications/trans_versasense/softmaxC.h   |   17 +
 sw/applications/trans_versasense/stftVec.h    |    3 +
 .../trans_versasense/tokenPosEmbeddingC.c     |   33 +
 .../trans_versasense/tokenPosEmbeddingC.h     |   24 +
 .../trans_versasense/transformerBlockC.c      |  116 +
 .../trans_versasense/transformerBlockC.h      |   48 +
 sw/applications/trans_versasense/transposeC.c |   31 +
 sw/applications/trans_versasense/transposeC.h |   22 +
 .../trans_versasense/weightsAndBiasesC.c      |  181 +
 .../trans_versasense/weightsAndBiasesC.h      |   15 +
 32 files changed, 6332 insertions(+)
 create mode 160000 sw/applications/trans_versasense/SYLT-FFT
 create mode 100644 sw/applications/trans_versasense/addNormC.c
 create mode 100644 sw/applications/trans_versasense/addNormC.h
 create mode 100644 sw/applications/trans_versasense/cgra_bitstream.h
 create mode 100644 sw/applications/trans_versasense/data_cpp/array_output.h
 create mode 100644 sw/applications/trans_versasense/data_cpp/data.cpp
 create mode 100644 sw/applications/trans_versasense/data_cpp/signal.cpp
 create mode 100644 sw/applications/trans_versasense/data_cpp/signal_fft.cpp
 create mode 100644 sw/applications/trans_versasense/dense_layerC.c
 create mode 100644 sw/applications/trans_versasense/dense_layerC.h
 create mode 100644 sw/applications/trans_versasense/main.c
 create mode 100644 sw/applications/trans_versasense/main.h
 create mode 100644 sw/applications/trans_versasense/matMulC.c
 create mode 100644 sw/applications/trans_versasense/matMulC.h
 create mode 100644 sw/applications/trans_versasense/multiply_cgra.c
 create mode 100644 sw/applications/trans_versasense/multiply_cgra.h
 create mode 100644 sw/applications/trans_versasense/param.h
 create mode 100644 sw/applications/trans_versasense/performance.c
 create mode 100644 sw/applications/trans_versasense/performance.h
 create mode 100644 sw/applications/trans_versasense/selfattentionC.c
 create mode 100644 sw/applications/trans_versasense/selfattentionC.h
 create mode 100644 sw/applications/trans_versasense/softmaxC.c
 create mode 100644 sw/applications/trans_versasense/softmaxC.h
 create mode 100644 sw/applications/trans_versasense/stftVec.h
 create mode 100644 sw/applications/trans_versasense/tokenPosEmbeddingC.c
 create mode 100644 sw/applications/trans_versasense/tokenPosEmbeddingC.h
 create mode 100644 sw/applications/trans_versasense/transformerBlockC.c
 create mode 100644 sw/applications/trans_versasense/transformerBlockC.h
 create mode 100644 sw/applications/trans_versasense/transposeC.c
 create mode 100644 sw/applications/trans_versasense/transposeC.h
 create mode 100644 sw/applications/trans_versasense/weightsAndBiasesC.c
 create mode 100644 sw/applications/trans_versasense/weightsAndBiasesC.h

diff --git a/sw/applications/trans_versasense/SYLT-FFT b/sw/applications/trans_versasense/SYLT-FFT
new file mode 160000
index 00000000..c6f58caa
--- /dev/null
+++ b/sw/applications/trans_versasense/SYLT-FFT
@@ -0,0 +1 @@
+Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b
diff --git a/sw/applications/trans_versasense/addNormC.c b/sw/applications/trans_versasense/addNormC.c
new file mode 100644
index 00000000..31828e28
--- /dev/null
+++ b/sw/applications/trans_versasense/addNormC.c
@@ -0,0 +1,71 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "addNormC.h"
+
+
+
+// Function implementations
+AddNormalize createAddNormalize(int seq_len, int input_dim, quant_bit_width *weight, quant_bit_width *bias) {
+    AddNormalize addNorm;
+    addNorm.seq_len_ = seq_len;
+    addNorm.input_dim_ = input_dim;
+    addNorm.weight_ = weight;
+    addNorm.bias_ = bias;
+    // Initialize other fields as needed
+    return addNorm;
+}
+
+
+
+
+void normalize(AddNormalize *addNorm, quant_bit_width *input, quant_bit_width *input_normalized) {
+    for (int i = 0; i < addNorm->seq_len_; i++) {
+        quant_bit_width *input_ptr = input + i * (addNorm->input_dim_);
+        quant_bit_width *input_normalized_ptr = input_normalized + i * (addNorm->input_dim_);
+
+        int sum = 0;
+        for (int j = 0; j < addNorm->input_dim_; j++) {
+            sum += *input_ptr;
+            input_ptr++;
+        }
+
+        input_ptr = input + i * (addNorm->input_dim_);
+        quant_bit_width mean = (quant_bit_width)((float)sum / (float)addNorm->input_dim_);
+
+        int64_t variance = 0;
+        for (int j = 0; j < addNorm->input_dim_; j++) {
+            variance += MUL_HQ((*input_ptr - mean), (*input_ptr - mean));
+            input_ptr++;
+        }
+
+        variance = SHIFT(variance);
+        float variance_float = (float)variance / (float)(addNorm->input_dim_);
+        variance_float = variance_float / (float)(1 << NUM_FRACTION_BITS);
+        float sd = sqrtf(variance_float);
+        float sd_inv = (float)(1 / (sd + 0.00001)); // prevent zero divide!
+        quant_bit_width sd_inv_int = (quant_bit_width)(sd_inv * (1 << NUM_FRACTION_BITS));
+
+        input_ptr = input + i * (addNorm->input_dim_);
+        input_normalized_ptr = input_normalized + i * (addNorm->input_dim_);
+
+        for (int j = 0; j < addNorm->input_dim_; j++) {
+            *input_normalized_ptr = (quant_bit_width)MUL((*input_ptr - mean), sd_inv_int);
+            *input_normalized_ptr = (quant_bit_width)(MUL((*input_normalized_ptr), addNorm->weight_[j]) + addNorm->bias_[j]);
+            input_ptr++;
+            input_normalized_ptr++;
+        }
+    }
+}
+
+void add(quant_bit_width *input, quant_bit_width *to_be_added, int seq_len, int input_dim) {
+    int32_t sum;
+    for (int i = 0; i < seq_len * input_dim; i++) {
+        sum = input[i] + to_be_added[i];
+        if ((quant_bit_width)sum != sum) // In case of overflow in 16 bits
+            input[i] = (sum > 0) ? INT16_MAX : INT16_MIN;
+        else
+            input[i] = (quant_bit_width)sum;
+    }
+}
diff --git a/sw/applications/trans_versasense/addNormC.h b/sw/applications/trans_versasense/addNormC.h
new file mode 100644
index 00000000..c2132867
--- /dev/null
+++ b/sw/applications/trans_versasense/addNormC.h
@@ -0,0 +1,26 @@
+//
+// Created by alireza on 10/5/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_ADDNORMC_H
+#define FVLLMONTITRANSFORMER_ADDNORMC_H
+
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "math.h"
+#include "param.h"
+
+typedef struct {
+    int seq_len_;
+    int input_dim_;
+    quant_bit_width *weight_;
+    quant_bit_width *bias_;
+} AddNormalize;
+
+
+AddNormalize createAddNormalize(int seq_len, int input_dim, quant_bit_width *weight, quant_bit_width *bias);
+void normalize(AddNormalize *addNorm, quant_bit_width *input, quant_bit_width *input_normalized);
+void add(quant_bit_width *input, quant_bit_width *to_be_added, int seq_len, int input_dim);
+
+#endif //FVLLMONTITRANSFORMER_ADDNORMC_H
diff --git a/sw/applications/trans_versasense/cgra_bitstream.h b/sw/applications/trans_versasense/cgra_bitstream.h
new file mode 100644
index 00000000..014ee6b8
--- /dev/null
+++ b/sw/applications/trans_versasense/cgra_bitstream.h
@@ -0,0 +1,12 @@
+#ifndef _CGRA_BITSTREAM_H_
+#define _CGRA_BITSTREAM_H_
+
+#include <stdint.h>
+
+#include "cgra.h"
+
+
+static uint32_t cgra_kmem_bitstream[CGRA_KMEM_SIZE] = { 0x0, 0xf01c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+const uint32_t  cgra_imem_bitstream[CGRA_IMEM_SIZE] = { 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4081ff4, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x850d0000, 0x0, 0x0, 0xc80000, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0x0, 0x0, 0x850d0000, 0x0, 0xab0000, 0xd0000, 0x8780001c, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8a0d0001, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xab0000, 0xd0000, 0xd0000, 0x87800018, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa5081ffc, 0x91c00000, 0x7a180004, 0x0, 0x5a080010, 0x8a0d0001, 0x7a181ff0, 0x1a181ffd, 0xd0000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x5080000, 0x0, 0x820d0000, 0x0, 0x820d0000, 0x2080000, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x2080000, 0x0, 0x0, 0x0, 0x5080000, 0x820d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x820d0000, 0x0, 0x3080000, 0x0, 0x820d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa5081ffc, 0x0, 0x91c00000, 0x0, 0x43180000, 0x0, 0x830d0000, 0x0, 0x830d0000, 0x4080000, 0x840d0000, 0x0, 0xab0000, 0xd0000, 0x0, 0x0, 0xf0000, 0x87800010, 0x8a0d0001, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x7a181ffc, 0x0, 0x0, 0xd0000, 0x7a180010, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x850d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x830d0000, 0x0, 0x2080000, 0x0, 0x830d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x0, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x3a080010, 0x0, 0x0, 0x0, 0x4080000, 0x830d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x4090000, 0x0, 0x0, 0x2080000, 0x0, 0x61180000, 0x910f0000, 0x0, 0x800005, 0x8080000, 0x8a0d0010, 0x8a081ff0, 0x91c00000, 0x0, 0x0, 0x0, 0x800003, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x8b90000, 0x0, 0x0, 0x0, 0x0, 0x2080000, 0x61180000, 0x910f0000, 0x8a0d0004, 0x0, 0x0, 0xa508000c, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x840d0000, 0x0, 0x800002, 0x0, 0xab0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x5090000, 0x0, 0x0, 0x3080000, 0x0, 0x61180000, 0x910f0000, 0x7a180010, 0x0, 0x0, 0x0, 0xa4080004, 0x91c00000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xad0000, 0x0, 0x0, 0x0, 0xf0000, 0x0, 0x0, 0x0, 0x5090000, 0x8b80000, 0x0, 0x0, 0x61180000, 0x910f0000, 0x0, 0x820d0000, 0x0, 0xa4080004, 0x0, 0x91c00000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x840d0000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+
+#endif // _CGRA_BITSTREAM_H_
diff --git a/sw/applications/trans_versasense/data_cpp/array_output.h b/sw/applications/trans_versasense/data_cpp/array_output.h
new file mode 100644
index 00000000..6e5f8182
--- /dev/null
+++ b/sw/applications/trans_versasense/data_cpp/array_output.h
@@ -0,0 +1,4803 @@
+int32_t prototypes[32] ={-1394, -5770, -6778, 762, 4001, -653, -5906, -20, 1220, 3795, -73, -3028, 635, -448, 7677, -6204, 5745, 3112, 1206, -1120, -3618, 1076, -649, 943, -3896, 2462, 4658, 2494, 3996, 1220, -1144, -1013, };
+int32_t STFT_rand_out[5008] = {
+	-12926,
+	-13872,
+	-27384,
+	-9514,
+	16213,
+	-2431,
+	-29203,
+	22796,
+	-13520,
+	-24530,
+	-1523,
+	-22165,
+	6477,
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+	-32732,
+	6528,
+	-20306,
+	-12571,
+	-5238,
+	-32626,
+	-32234,
+	-24604,
+	-25164,
+	-23058,
+	-284,
+	22733,
+	13211,
+	30060,
+	18770,
+	14117,
+	-24215,
+	-20438,
+	-23294,
+	-23461,
+	-24059,
+	-30987,
+	23538,
+	-18331,
+	-26582,
+	26174,
+	20,
+	-17686,
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+	-4877,
+	-9303,
+	-25054,
+	12141,
+	-30938,
+	-524,
+	15610,
+	-20836,
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+	14700,
+	9746,
+	31669,
+	-7502,
+	1309,
+	29525,
+	3044,
+	-18198,
+	-15137,
+	-19411,
+	-14748,
+	-360,
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+	29686,
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+	-2676,
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+	28953,
+	-1211,
+	20453,
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+	7086,
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+	-8914,
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+	32222,
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+	-5280,
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+	-31694,
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+	-17244,
+	18003,
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+	-32338,
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+	7675,
+	-16185,
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+	30560,
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+	-25855,
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+};
\ No newline at end of file
diff --git a/sw/applications/trans_versasense/data_cpp/data.cpp b/sw/applications/trans_versasense/data_cpp/data.cpp
new file mode 100644
index 00000000..4e7efc7a
--- /dev/null
+++ b/sw/applications/trans_versasense/data_cpp/data.cpp
@@ -0,0 +1,104 @@
+#include "stdint-gcc.h"
+
+int32_t pos_embedding[1936] = {-1383, 964, -5839, -3654, -5069, 4064, -1907, -3855, -3658, -8857, 316, -1245, -3385, 1368, -2997, 13377, 7049, -1252, 2205, -219, -1524, -1316, 4386, 3600, 244, 6103, 1171, 2736, -222, -10278, 728, -1065, 297, 490, 2032, 4887, 4769, -2205, -2950, 3033, 1045, -84, -924, -9504, 871, 6262, -6855, -7938, 3453, -1851, 2541, 741, 10731, 1307, 2100, -4055, -1536, 5267, -2867, -2898, 1939, 25, 3560, 3399, -2064, 139, -1077, 4781, -8273, -6488, 403, 439, 1265, 8417, -106, -211, -4182, 3988, 6307, 104, 3200, -2645, 2750, 1677, 5047, 1988, -368, 784, 2920, 1074, -3975, 322, 2831, -2976, -1221, 4132, -8774, -3231, -3688, -1704, 6092, 4813, -2799, -686, 6206, 460, 10634, 6885, -3182, 5878, 920, -1219, 461, 2684, -2039, -7031, -5283, -6447, 5388, 490, 692, -1467, 28, -72, -766, 6259, 2560, 9225, -6087, -4768, -285, 933, -5913, 6449, 840, -2466, 1073, 2144, 2515, -2408, -7375, 7211, -1006, 1794, -9011, -5, 2908, 3234, 891, -2127, 2135, 1420, -1477, -820, 486, 2927, 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+int32_t cls_token[16] = {1579, -8312, -1543, 5366, -5637, -2872, -787, 5773, -2441, 5560, -195, -1606, -1795, -6080, 1247, 219, };
+int32_t to_patch_embedding_layer_norm1_weight[400] = {4133, 4145, 3757, 3886, 3959, 4157, 3936, 3941, 4085, 3902, 4116, 4193, 4064, 4147, 4075, 4082, 4012, 4029, 4116, 3960, 4010, 3944, 4027, 4086, 3719, 3979, 4088, 4002, 4053, 3642, 3885, 3881, 4070, 3980, 3861, 4118, 3899, 4082, 4035, 3967, 3992, 3993, 3975, 3960, 4044, 4026, 3964, 4104, 4141, 4203, 4335, 3950, 4260, 4394, 4250, 4142, 4046, 4265, 4355, 4162, 4026, 3882, 4271, 4276, 4216, 3970, 3983, 3922, 4114, 3907, 4105, 3924, 3986, 4032, 4059, 4209, 3959, 4090, 4356, 3975, 4122, 3986, 4208, 4332, 3799, 4094, 4119, 4180, 3884, 4095, 4133, 4137, 3932, 4225, 4114, 4111, 4032, 3875, 4169, 4247, 4040, 4016, 3875, 4170, 3953, 4202, 3919, 4007, 4077, 4003, 4305, 3842, 4027, 4056, 4142, 4325, 4154, 4097, 3973, 4237, 4355, 4214, 3867, 4227, 3953, 4371, 4289, 3955, 4040, 4009, 4349, 4107, 4081, 3992, 4066, 4087, 4143, 3998, 4267, 4175, 4172, 4379, 4104, 3944, 4301, 4158, 4079, 4004, 4215, 3903, 3995, 4349, 4114, 4170, 4144, 3863, 4146, 4371, 4222, 4055, 3768, 4143, 4415, 4017, 3835, 3989, 4230, 4134, 3999, 4111, 4047, 4056, 4048, 3949, 4234, 3900, 4057, 3988, 4199, 4106, 4042, 3996, 4172, 3837, 4434, 3947, 4334, 4126, 3984, 4289, 4126, 4312, 4083, 4108, 4197, 4109, 4378, 4341, 4190, 4026, 4163, 4292, 4392, 4021, 4034, 4101, 4160, 4278, 4369, 3999, 3936, 4324, 4048, 4162, 4044, 3925, 4438, 3960, 4227, 3866, 4002, 4304, 4042, 4232, 4019, 4004, 4256, 4206, 4115, 4146, 4098, 4208, 4202, 4077, 4139, 3819, 4197, 4112, 4082, 4096, 4123, 4186, 4242, 3938, 3958, 3854, 4033, 3863, 4125, 3973, 4049, 4200, 4256, 4168, 3976, 4109, 3891, 4326, 3963, 4095, 3989, 4003, 3975, 4060, 3839, 4141, 4158, 3988, 4027, 3942, 4172, 3919, 3789, 4114, 3849, 4044, 4072, 4189, 4027, 3988, 4126, 4168, 4252, 3919, 4101, 4337, 4444, 4213, 4265, 4097, 4241, 4310, 4159, 3999, 3960, 4176, 4212, 4061, 4151, 4209, 3865, 4062, 4143, 4250, 4240, 3844, 3949, 4000, 4163, 3924, 4031, 4240, 3901, 4130, 4081, 3980, 4027, 4228, 4179, 4012, 4004, 4040, 4259, 3998, 4100, 4036, 4036, 4179, 3997, 4013, 3999, 4269, 3892, 4237, 3970, 4001, 4144, 3987, 4286, 4028, 3876, 4163, 4167, 4266, 4089, 3886, 3843, 4096, 4022, 4139, 3774, 3958, 4185, 3968, 3734, 3858, 3944, 3847, 3897, 4437, 3900, 4063, 4092, 4064, 4184, 4036, 3915, 4042, 4022, 4221, 4130, 3789, 4108, 4215, 4273, 3804, 3838, 3820, 4098, 4179, 3893, 4165, 3959, 4077, 4066, 3950, 4334, 4204, 3915, 3767, 4120, 4262, 4153, 3926, 4022, 3947, 4106, 4003, 3883, 3666, };
+int32_t to_patch_embedding_layer_norm1_bias[400] = {-181, -150, -345, -240, -156, -149, -228, -310, -125, -193, -139, -95, -144, -184, -125, -137, -225, -204, -98, -170, -13, -175, -169, -127, -341, -168, -8, -182, -261, -380, -104, -230, -161, -206, -269, -152, -96, -4, -246, -37, -138, -182, -33, -64, 9, -50, -201, 66, 108, 50, 51, -30, 117, 88, 32, 40, 5, 73, 92, 7, -126, -116, 87, 86, 78, -51, -135, 5, 48, -15, -3, -54, -132, 77, -78, 44, -12, -133, -116, -105, 60, -27, -108, -166, -119, -68, -6, -132, -102, -68, 29, 94, -23, 58, -51, -35, -61, -28, 4, -114, -232, 9, -89, 23, -29, 46, -44, -122, 78, -82, 53, -36, 47, 62, -86, 50, 35, 90, 5, -70, 69, 105, 3, 113, -38, 42, -69, 2, 131, -44, 53, -59, -18, -111, -97, -18, -91, 9, -97, -53, -121, -103, -6, 42, -30, -55, -39, -11, 121, 8, -32, -27, 20, -58, 54, -76, -13, -34, -80, 83, -37, -57, -59, -4, 42, 97, -90, -39, 19, -59, 44, -68, 115, 80, -65, 13, 54, -46, 109, -21, -47, 11, -23, 136, 56, -34, -30, -40, -29, 47, -71, -89, -16, 112, -95, -71, -114, -57, 79, -70, -81, -76, -106, -18, -53, -66, -53, -52, -116, -127, -50, -104, -70, -36, 41, -56, -110, 104, -62, 132, -40, -73, -54, -24, -21, 37, -40, -59, -3, -65, -28, -87, -69, -37, 83, 40, -38, -35, -61, 59, -59, -72, -92, 118, -4, 36, 29, 133, -64, 135, 9, -33, 69, -76, 74, -28, 52, 68, 108, 95, -77, 156, 191, 69, 130, -58, 88, 141, -12, 89, -39, 256, 158, -6, 61, -118, 75, -15, -21, 99, -115, 205, -21, 50, 121, -88, 110, -40, -19, -30, -57, 110, 140, 152, -37, -56, 123, 128, 151, 87, 53, 95, -35, 89, 98, 91, 154, 25, 83, 6, 145, 102, 99, 186, -14, 51, 39, 103, 124, 140, 114, 130, 81, 120, 157, 129, 160, 152, 169, 144, 111, 104, 51, 11, 43, 156, 74, 234, 13, 193, 130, -45, 159, -14, 102, 205, 125, 137, 43, 169, 306, 142, 87, 182, 136, 216, 166, 198, 142, 88, 233, 165, 195, 49, 192, 104, 37, 200, 17, 189, 36, 134, 192, 224, 76, 272, 170, 180, 146, 85, 130, 69, 189, 142, 163, 142, 111, 130, 251, 186, -30, 128, 149, 264, 144, 72, 200, 147, 131, 210, };
+int32_t to_patch_embedding_linear_weight[6400] = {-173, 179, -273, -237, 19, 323, 124, -8, -4, -42, 39, -70, -3, -226, 215, -34, -120, 218, -189, -275, 21, -86, 42, 92, 209, -149, 196, 180, 164, -87, 49, 54, -54, 66, -83, 102, 32, 118, 140, -60, -96, -33, -165, -97, -141, -163, 34, 208, -214, 108, 22, -126, 151, -120, -195, 88, 21, 35, 157, -22, -12, -191, 82, 89, 183, 252, 17, -22, 206, -29, 22, 57, 40, -82, -285, 98, 46, 52, -16, 165, -125, 181, -157, -105, -129, 329, -88, 193, 218, -133, -27, 85, 294, -133, -127, -40, 114, 68, 18, -162, -98, 166, -117, -18, 74, 59, 92, -40, 56, -200, 122, -163, 199, -62, -49, 106, -136, 184, 136, -64, 52, -164, -255, 115, -58, 162, 245, -40, 34, -19, -127, -342, -173, 220, -44, 171, 124, -198, -144, -127, 27, 219, 7, -176, 314, -18, -43, 69, 75, 138, -23, 118, 163, -35, 69, 100, 208, 65, 126, 149, 100, 210, -48, -106, 9, 41, 43, -3, 43, -297, -324, -96, -51, 47, 126, 5, 116, 360, -299, -36, -50, 148, -155, 242, 64, -130, 69, -48, 210, -165, 54, 142, -59, 101, -64, -264, 80, -13, -111, 223, -145, -159, 47, -87, 141, 196, 57, -183, -11, 300, -304, -50, -157, 122, 34, -19, -83, -170, 70, -41, 12, -44, -60, -122, -85, 69, 38, -107, -205, -58, -122, 100, 155, -300, -175, -11, 326, 120, 131, -174, 152, 104, -46, -72, 122, -19, -161, 138, 61, -76, -343, -88, 176, -103, 148, -188, -129, 282, 65, -34, -61, 91, 111, 38, 114, -19, 95, 50, 206, -33, -113, 81, 323, -45, -34, -164, -122, 253, 186, 102, -5, -244, 88, 181, -58, 195, -30, -18, 155, 107, -108, -267, 72, -23, 125, 65, -204, -254, -238, 96, 159, 228, 71, 13, 223, 3, -192, -176, -65, -151, -115, 213, 122, 8, -130, 66, 144, 208, 63, -140, 193, -90, 104, -189, -59, -146, -39, -185, 172, 138, -264, -217, -88, 39, 39, 42, -61, 194, 123, -57, 156, 0, -172, -132, -221, -197, -165, 80, 110, -95, 50, 52, 244, 41, -58, -107, 145, 203, 212, 204, 112, -91, 45, -22, -26, -51, 34, -152, -205, 239, -88, -122, 203, -85, -69, -43, -190, -202, -248, 7, 189, 103, 137, 133, -63, 42, -115, 68, 129, 184, -192, 176, -118, 86, -1, 90, 210, 37, -40, 135, -45, -164, -175, 70, 283, 232, -219, -81, 66, -85, -171, 40, -67, 310, 164, -66, 32, -64, -64, -52, 172, -128, -229, -156, -273, 208, -107, -196, -176, 355, 43, -19, 48, 155, 74, -145, -28, -83, -128, 15, -101, -37, -54, 103, 278, 194, 154, -161, -342, 8, -187, -34, -149, 175, -73, -153, -1, -303, -197, -180, -29, -75, 9, -157, -75, 157, -66, -130, 112, -68, -26, 10, 117, 138, -104, -189, -81, 38, 138, 149, -52, -30, 110, -93, 153, -62, -116, 189, -67, -67, -94, -94, 17, 45, 122, -158, 177, 166, 101, 105, 52, 140, -115, -7, -184, -85, -249, 98, 19, 233, -100, 198, -165, 6, -73, -183, -133, 196, -146, 231, 42, -266, 70, -104, 50, -80, 281, -171, -331, -9, 168, -98, 177, 201, -234, -103, 79, -96, 112, -38, 170, 36, -86, 201, -132, 137, -9, 34, 105, 75, -234, -69, -34, -193, 78, -236, 205, -169, 96, -48, -191, 55, -261, -52, -100, -15, -261, 24, -68, -304, -137, -296, 240, -164, 185, -182, -111, -93, 149, -194, 264, -46, -231, -16, 168, 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-426, 140, 275, 314, -190, -270, -342, -139, 95, -110, 298, -114, -93, 16, 253, 150, -110, 390, 282, 180, -162, 121, 90, -170, 72, -83, 150, -353, -119, -5, 341, -89, 100, 61, 58, 1, 58, -203, -85, -28, 174, -126, -44, -31, -18, 12, 170, -88, -354, 326, 19, -1, -223, -124, -175, -270, 43, -54, 73, -345, 90, 19, 171, -40, -251, 332, 245, 259, -14, -85, -418, -299, 125, -324, 123, -124, 475, 153, 349, 205, -154, 290, 37, 45, -230, -81, -178, -215, 335, 40, 230, -357, 310, -126, 269, 58, -334, 131, 101, 254, -141, -235, 7, -240, 30, 35, -22, -147, 183, -16, 22, -100, -138, 154, -4, -158, 46, 154, -301, -147, -85, 155, -97, -275, 68, 84, 160, 151, -319, 105, 230, -179, -41, -105, -23, -445, 463, -29, -24, -255, 53, -256, 349, -126, -481, 341, 224, 239, -322, -302, -98, -143, 170, -279, 78, -369, 124, 106, 379, -65, -202, 393, 148, -31, 25, -257, -260, -217, 80, 35, 119, 1, 191, -242, 87, 342, 19, -120, -80, 241, -29, -76, -314, 1, -125, -219, 76, -167, 65, 3, 281, 24, -17, 22, -131, 295, -81, 80, -116, -56, -51, 148, -231, 80, 232, 28, 74, -219, -231, 383, 165, 165, -122, -124, 66, -237, 357, 1, 318, -54, 391, -175, 353, -331, -405, 247, 40, -27, -38, 86, -286, -118, 306, -253, 235, -210, 153, -77, 158, -217, -229, 177, 345, 145, 66, 29, -100, 30, 78, -155, 115, -13, 193, -136, 250, -6, -98, -10, -90, 112, 25, -141, -107, 71, -27, -156, 101, -137, 5, 65, 45, 23, -100, -15, -24, 151, 161, 80, -155, 250, -107, 40, -82, 127, 201, -110, 26, -257, 22, 154, -109, -13, -108, 95, -81, 14, -46, -278, 45, -130, 132, 94, 205, -57, -65, -42, 120, 273, 174, -8, -103, -170, 201, -323, 24, -205, 274, 49, 151, 39, -38, 43, 139, -92, -239, -203, 160, -41, -99, -9, -33, 89, 311, 125, 136, 31, -311, 64, 44, 168, -124, -45, 97, 155, 131, 33, 90, 211, 229, 155, 51, -27, 61, -229, -16, -166, 13, 256, -85, -69, -208, -125, 31, -174, 134, 266, 51, -182, 87, 98, -266, -75, 140, -39, -21, -70, 52, -230, -159, -113, -47, -17, -114, -101, -52, 216, -70, 88, -134, -306, -153, -56, 27, -294, 195, -114, -30, 17, 167, -14, 154, -62, -187, -246, 256, -154, 116, 76, 62, -133, -302, 237, 212, -25, 55, -65, -402, -140, 271, -144, -256, -117, -135, -160, 174, -27, -30, 193, 6, -118, 217, -177, -111, -148, 80, -6, 259, 249, -190, 226, -5, -133, -272, 180, 218, -133, -196, 200, 226, -8, -30, -163, 76, 271, 195, 28, -218, 44, 77, 153, 74, 48, -100, -69, 501, -408, -465, 15, 212, -400, 14, 196, -245, -36, 65, 7, 236, 267, -91, 228, 215, -49, -24, -133, 233, -121, -180, 13, -63, -266, -171, 79, -208, 52, 177, -430, -222, 51, 204, -65, -151, -83, -96, -124, -120, -276, 54, 20, -160, 204, 288, -350, -181, 14, 63, 4, 167, 200, -82, -104, 226, 167, 58, -47, 82, 47, -166, -114, 227, -217, -307, -342, 222, 88, 57, -26, -61, -30, -53, -52, -155, -46, -169, -263, 489, -78, -174, -117, 383, -120, 50, 350, -197, 5, -40, 220, 18, 138, -250, 479, 66, 91, 121, 70, -38, -25, -30, -128, -78, 73, -39, 63, -19, 154, -88, -254, -90, 150, 1, 76, 259, -271, -83, -86, -10, -77, 83, 26, -49, 158, 224, 26, -21, 24, 17, 192, 107, 280, -337, 91, 375, -147, -155, -224, -165, -25, -18, -204, 212, -191, -97, -198, 85, 42, 76, 17, -292, -19, -2, 200, -220, -81, -147, -412, -87, -45, -146, -28, 143, -206, -67, -32, -85, 79, -225, -57, 76, -78, -115, 60, 154, -159, 163, 197, 167, 25, -344, 67, -24, -36, 85, -298, 166, -209, 124, 37, -245, 222, 171, 153, 54, -143, -48, -53, -84, -41, 16, -193, 74, 24, 219, -78, -13, 146, -6, 208, -32, 214, -190, 217, 162, -32, -131, -246, -68, -163, 222, -219, 165, 113, 174, -198, -126, -21, -27, 59, 124, -165, -183, 62, -260, 93, -123, -66, -362, 349, 167, -79, -255, -165, 16, -249, 33, 64, 43, -281, 10, -295, -2, 114, 271, -300, 76, 156, 292, -146, 162, 49, -186, -123, -62, 163, 73, 95, 59, 235, -148, 48, -140, 236, 97, -293, -12, 213, -230, -266, 156, 192, 276, 206, 31, -149, 29, -84, -82, -16, 49, 87, 135, 290, -181, -121, 63, 111, -260, -131, 101, 26, 74, 57, 72, -166, -134, 33, 39, -144, 0, 29, -231, -93, 87, 282, -4, -401, 100, 293, 217, 146, -40, -168, -61, -19, 226, 46, -57, 102, 333, -213, 181, -159, 239, -167, -189, 68, 373, -270, 205, 287, -244, 29, -164, 117, -246, 236, -212, 191, 133, -31, -190, -13, 239, -67, 220, 9, -57, -230, 85, 21, 102, 158, 50, 21, 90, 140, 147, 179, 182, -65, -162, 18, 153, -103, 49, 35, -204, -94, 168, -32, -55, -69, 91, 159, -65, 94, -53, 120, -176, 102, -170, -28, 133, 1, 56, -181, -32, 260, -114, 138, -22, -412, 55, -106, -82, -166, -37, -256, 34, -222, 168, -79, -8, -54, -122, 176, 189, -242, -8, 38, 64, -132, 33, 120, -83, -122, 99, -103, -323, 256, 184, 90, -276, 51, -46, -42, 340, -145, -1, -42, -80, 58, 125, -53, 105, 32, 89, 142, -101, 132, 125, 208, 193, 137, 56, -238, -12, -205, 13, -169, -97, -30, 51, -269, 97, -141, -90, 231, -266, 191, -113, 86, -21, -72, -97, 99, -110, 180, -232, 98, 177, -208, -84, -86, -46, -61, 148, -49, 320, -32, 227, -334, 98, 88, 35, 38, 46, -360, -176, 73, -91, -121, -146, 9, 22, 75, 256, -42, -285, 346, 241, 81, -69, -89, -5, -386, 219, 218, -77, -171, 98, -226, 204, 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-68, 0, 56, 144, -16, -35, 154, -25, 207, -124, -20, -170, 40, -56, -114, 139, 221, -108, 123, -230, -131, 125, -33, 142, 55, 314, -130, -70, 192, 31, 254, -414, 223, -26, 169, -202, 98, 168, -21, 216, 96, 191, -22, -98, 98, 117, 182, 105, 197, -9, -38, -157, 97, 193, 85, -125, -227, 55, -21, 109, 6, -56, -223, -219, 291, 246, -140, -205, 43, -24, -255, 85, -136, 141, -36, -17, 14, 294, -236, 179, -27, 46, 48, 115, 170, 106, -17, -186, 259, -150, 18, -157, 64, 121, -190, -60, -182, 80, -66, -73, -67, -171, 196, -168, 119, 297, -150, 168, 323, -29, 127, -139, 114, 19, -65, -288, 233, 7, -25, 161, 126, 27, 101, -57, -101, 11, 257, -331, 220, 163, 101, -9, 157, -14, -317, 189, 48, 43, -189, -128, 145, -172, -141, -59, 278, 296, -82, 135, -62, -137, 104, 300, -95, 145, -32, 32, -271, 134, -59, 9, -23, -151, 186, 0, -11, -156, 103, 174, 81, 87, -188, -14, -304, 155, 135, 50, -32, 254, -160, -256, -228, -248, 128, 147, 117, 105, -16, 100, -105, 119, 57, -171, 158, 0, 30, -189, 110, 40, -201, 171, -39, -65, -9, 184, 245, 35, -114, -273, 398, 211, 29, -41, 37, -116, -156, 137, 31, 121, -376, -98, -137, 123, -87, -168, 41, -41, 7, -76, -25, 45, -136, -184, -139, -3, -18, 127, 179, 152, 116, -164, 76, -46, 150, -120, 123, -192, -195, 67, 97, -211, -8, -72, -251, 188, -24, -163, -98, 136, 153, 95, 54, -181, -162, 303, -117, 277, -89, -84, 129, 147, 25, -116, 262, -29, -118, -235, 177, -107, -59, 51, 296, 122, -5, 81, 81, 119, -15, -168, 267, 344, 30, -162, -61, -303, -192, 225, -135, 173, -13, 220, -257, 239, 53, -12, -110, -89, 82, 27, -382, -33, -183, 10, -72, -272, -146, -26, 55, 188, -172, -230, 12, -136, 65, -32, -61, -276, -140, 243, 102, -5, -94, 88, -92, 31, 102, -77, -81, 267, -31, -29, 40, -300, -150, 3, 136, 74, -181, 66, -192, -61, 110, -323, 293, 262, -129, -224, 226, -302, -135, 263, 103, -115, -44, 297, 166, -109, -54, 82, -80, 129, 6, 34, 23, -4, 32, -25, -180, 18, 43, 213, -139, -41, -18, 26, -208, -216, -66, 206, -457, 169, 131, -224, -110, -229, 268, 12, 14, -281, -3, 93, 13, -8, -136, -119, 245, 106, -42, 152, 293, -42, 100, 44, -127, 133, 256, -130, 22, 55, -56, -70, -225, -196, -108, 23, -37, 90, -191, 71, -51, -27, -99, -164, 311, 313, -217, 154, 109, -142, -82, 0, 142, 188, -134, -126, 167, 82, 192, -110, -25, 1, -134, 25, 0, -218, -273, -49, 49, 375, -155, -103, 144, 222, 109, 84, -100, -521, -101, 41, -353, 472, 73, -210, -83, -350, 379, -96, 40, -206, 165, -145, 163, -129, 7, -116, 47, -244, -5, 125, -155, 49, 69, 92, -129, 83, -60, 13, -43, 194, 138, -143, -3, 4, -58, -195, 3, -59, -104, 166, -1, -119, -207, 62, -146, 129, -85, 127, 5, 136, 228, -143, 102, -154, 151, -237, 213, -213, 6, -349, 112, 279, 183, -199, 87, -13, 65, -22, 88, -14, -188, 23, -356, 185, -154, 357, -301, -398, -191, 45, -155, 38, 5, -377, 3, -139, 119, 59, -26, -162, -40, -92, 157, 59, 9, -106, 50, -42, -24, 113, 388, 113, -179, 10, -89, 193, -42, -78, 20, 226, 220, 45, 199, 104, 105, -42, -89, 292, 20, 78, -98, 37, -227, 100, 49, 131, -95, 197, 85, -21, -108, -68, -127, 128, -67, 78, 41, -44, 72, -176, 22, 368, 15, -280, 57, -113, -61, 254, 76, 222, 41, 212, 10, 68, -194, 57, -214, -27, -135, -49, -200, -65, 46, 2, -172, 219, -65, 116, 167, 24, -94, 39, 210, 310, -162, 19, 56, -79, 51, 305, 113, -152, -46, 76, -327, 171, -15, -46, 82, -153, 17, 10, 80, -164, -159, -18, -126, -4, 80, 94, 12, 197, -179, -54, 135, -147, -187, -108, -63, 136, -173, 116, 102, 219, 94, 159, 49, 89, -115, -140, 208, 324, 230, 9, 146, 3, -244, 84, 131, 114, -328, 122, 84, 96, -206, -253, -60, 26, 104, 124, 98, -142, 74, 83, -63, 160, -123, 21, 93, -93, -41, -29, 132, 61, 153, -47, -147, 9, 58, 35, 165, 112, 69, -13, -231, 171, -47, 90, 158, -25, 47, -132, 36, 214, -164, -224, -17, 9, 83, -82, 134, -153, -116, -48, 76, -173, -219, -106, -15, -77, -198, 21, -202, 161, -132, 28, -68, 137, -54, -76, 74, 63, 240, 1, -232, -229, 46, 226, -103, -190, -117, -85, 130, -71, -143, -89, 196, 99, 18, -169, -147, -114, -145, -85, -50, 48, -43, 115, 130, 48, -224, -402, 535, 529, 2, -64, 181, -160, -73, 488, 17, -69, -461, 52, -249, 389, -365, -89, 46, -233, -242, -119, -119, 199, -88, 16, 85, 0, -130, -156, -154, -198, -172, -192, 100, 13, 98, 149, -306, -18, -6, 197, 80, 105, 64, -71, 58, -1, -141, 8, -73, 111, 130, -260, 21, -95, -257, 161, 118, 9, -278, -96, 149, 148, 37, 87, 102, -225, 181, 13, -120, -272, 147, -90, -223, 290, 213, 258, -42, -4, 180, -434, 122, 56, 199, -340, -58, -184, -117, 145, 129, 42, -313, 220, -62, 89, -362, 1, -235, 26, -152, -19, -27, -207, 202, 11, 90, 130, 295, -18, -263, -320, 28, 97, -4, -97, -154, 169, -342, -102, -168, -75, 78, -8, 32, 181, -210, 26, -95, -149, 149, 240, 83, 76, 33, -212, -67, -9, 26, 2, -124, 151, 39, 231, -144, 104, 136, -110, 71, 145, -64, 86, 83, -177, 2, 152, 119, 226, 153, 113, 358, -183, 111, 366, 330, -70, -143, -87, -283, 245, -266, -142, -89, 270, -201, 357, -286, 219, 114, -164, -76, 210, -91, -1, 240, 105, 382, -164, -102, -142, -92, -171, -18, 79, -131, 66, -240, 55, -118, 24, 22, 85, 13, 64, 134, -64, -27, -85, 41, -102, 164, 114, 130, 24, 120, -212, -153, 29, -131, 0, -147, 42, -42, 269, 32, -288, -40, 239, 234, -172, 256, 22, -191, -103, -272, 230, -210, 377, 125, 340, 32, -193, 383, 220, 383, -47, -200, -121, -132, 269, -59, -42, -282, -3, 140, 217, 101, 70, 28, -168, -28, 45, 104, 83, -190, 69, -68, -58, 18, -4, 109, -61, -174, -80, 144, 12, 36, 69, 22, 155, 4, -63, 275, -151, 209, -6, -63, -72, -142, 49, -85, -34, 117, -82, -184, -134, -93, 7, -6, 159, -255, 73, 94, 138, 104, -87, 240, 193, 259, -108, 117, 111, -240, 193, -37, 105, -15, 172, 116, -98, 63, -296, 33, 21, 286, -122, -292, -353, -195, 323, -38, 170, -138, 95, 68, -39, -74, 185, 129, 133, 11, 70, -13, 180, -64, -74, -108, 173, -53, -11, 281, 77, -145, -39, 230, 270, 99, -44, -225, -166, -155, 334, 215, 120, -202, -159, -320, 77, -340, -148, 170, -1, -161, -125, -8, -56, -105, -90, 144, 73, -59, -259, 215, -76, -250, -212, 17, -117, 73, -63, -80, -167, -98, 101, 145, -73, -107, 294, -173, 111, -11, -271, 106, 206, 173, -130, -192, -95, -1, 85, -111, 123, -25, 12, 37, 105, -149, -89, 103, -43, 26, -252, 171, 31, -24, 21, -21, -111, -40, -39, -136, -68, 140, -260, 452, 305, 218, -366, -42, -236, -70, 404, 140, -51, -349, 21, -287, 334, -301, -308, 336, 227, -222, -231, -62, -208, -135, 153, 62, 34, -271, 17, 52, 163, -284, -154, -44, -182, -24, 245, 120, 64, -8, -98, -49, 307, -77, 233, -102, -102, -33, -42, -96, -12, -127, -108, 13, -66, -23, -55, 36, -298, -155, -13, -103, 3, 151, 107, -72, -44, -68, 177, 312, 197, 227, -248, 108, 86, 244, -299, -21, -300, 47, -414, 427, 291, 123, -82, 148, -185, -44, 114, 27, 141, -307, 73, -324, 200, -144, -72, 348, 10, -47, -80, 222, 154, -297, 54, 119, 40, -6, 54, -90, -16, -72, 83, 177, -138, 81, 0, 123, -277, 137, -185, 72, 167, -36, 153, 30, 23, 248, 249, 67, 48, 253, 189, -88, -143, 193, 52, -154, -143, -12, 122, 90, -152, -109, 83, -86, -94, -180, -31, 124, 146, -48, -123, 27, 123, -147, -128, -78, -139, -60, -236, 201, 30, -122, -84, -61, 79, -128, 194, 0, -6, -196, 0, -211, 360, -179, -128, 70, 44, -158, -109, -128, -10, -144, 176, -87, 132, 0, -49, 117, -225, -240, 117, -44, -5, 145, -8, -38, -158, 99, 57, 73, 32, 112, 70, 19, -186, 16, -107, 124, -48, 2, -143, -70, 5, 105, -94, -124, 99, 129, -76, -179, -88, };
+int32_t to_patch_embedding_linear_bias[16] = {227, -68, -2, -126, -99, -174, -84, 74, -6, 99, -139, 80, -62, -140, 83, -7, };
+int32_t to_patch_embedding_layer_norm2_weight[16] = {3971, 4588, 4419, 4328, 3995, 4153, 4080, 3987, 4099, 4443, 4075, 3864, 4214, 4134, 4104, 4276, };
+int32_t to_patch_embedding_layer_norm2_bias[16] = {132, -148, 57, 34, 72, -70, -116, -26, -76, 79, -190, 10, -46, 57, -30, 204, };
+int32_t transformer_layers_0_0_norm_weight[16] = {4052, 4657, 4613, 4245, 4042, 4415, 4086, 4275, 4240, 4498, 4285, 4081, 4387, 4184, 4302, 4580, };
+int32_t transformer_layers_0_0_norm_bias[16] = {80, -54, 40, 214, -203, -129, -101, 57, -177, 57, -56, -281, -36, 219, -182, 92, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H0[64] = {-568, -962, 189, -868, -562, 692, 858, 407, -818, -814, 262, -471, 1273, 623, -384, 338, -321, -114, -723, 913, -697, 294, -35, -123, -264, -331, 509, 129, 184, 595, 16, -677, -348, 313, -401, 679, -798, 378, -145, 190, 618, -246, 776, 801, 974, 570, 842, -29, -685, 721, 640, 87, -612, -939, 890, -225, 522, 70, -514, 927, 990, 825, 114, -893, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H1[64] = {640, 166, -336, 542, 491, -1105, -458, -497, 20, -292, 989, -578, -438, 699, -855, 724, 901, 119, -824, 607, 1135, 1478, -883, -673, -923, -897, 445, 395, -782, 260, 591, 327, 970, -1386, 631, 281, -121, -721, 109, 203, 74, 106, 593, 1065, 857, -728, 761, -620, -558, 765, -514, 587, -489, -144, 839, -142, -270, 415, -757, 288, 305, 1302, -249, 247, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H2[64] = {-1419, 962, -640, 252, -124, -585, -573, 363, 218, 537, 461, 201, -502, 636, 804, -1101, 434, 91, -595, -67, -209, -257, 132, 782, -55, -268, -36, -205, -1225, 1346, 648, -933, 360, 693, -726, -675, 1319, 324, -601, -707, 234, 687, 630, 769, 323, -334, -855, 135, -410, 330, -330, 739, -812, -33, -356, -471, 689, -841, 242, -763, -1304, 937, 743, -440, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_Q_H3[64] = {-1060, 1048, 444, 53, 299, -1202, -112, -899, 1136, 226, 103, -466, 653, 104, 151, -131, -910, 333, 104, -1167, -337, -744, -291, 445, -339, -916, 64, -170, -569, 334, -1016, 803, -782, -18, 583, -961, 304, -358, 725, 244, -567, -128, -370, 950, 536, -757, 290, -506, -365, -1083, 685, -1292, 555, -640, -304, 840, 919, -707, 665, -777, 781, 909, 869, 882, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H0[64] = {339, 84, 743, 513, 937, -490, 499, -304, 1092, 299, 522, -95, -850, -672, -565, 107, -47, -401, 196, 1062, -158, -507, 736, -381, -249, 768, -185, -849, -107, 483, 520, -997, -234, -945, 1008, -44, 674, -34, -388, -817, 289, 988, -652, -446, -603, 226, 427, 582, -422, 37, 474, -103, 561, 198, 113, 520, 150, 37, -857, 1162, -361, -122, -909, 596, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H1[64] = {587, -190, 215, -264, -1101, -633, 784, 643, 562, 794, -31, 134, -75, 572, -551, 233, -162, -1081, 780, -472, -588, 170, 1040, -1217, 805, 505, -961, -23, 457, 730, -77, 117, 771, -422, -811, -611, 622, 678, 554, -690, 435, 403, -904, 91, -350, -398, -563, -750, 352, -406, -22, 667, 468, -1362, 395, -764, 132, -553, -612, 61, -284, -933, -340, -561, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H2[64] = {399, -840, -111, -768, -787, 925, 1041, 579, -842, 1107, -195, -454, -1018, -673, 330, -1015, 554, 339, 389, 461, 579, -387, -826, 465, -1171, 274, -94, 518, 899, -878, -986, 258, -406, 199, -487, -577, -1264, 1126, -283, -1205, -1311, -101, 970, 79, 183, -108, -499, 980, 122, 110, -163, -25, 767, -718, -836, -838, 839, 120, -734, 789, -324, 119, -159, -411, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_K_H3[64] = {585, 567, -262, -561, -166, 469, 155, -56, -512, 839, -519, 859, -225, 693, -983, -707, 395, -196, -574, 63, 3, -162, -1000, -962, 248, 335, 1235, -284, 994, 727, -475, -891, -428, -817, -598, -1159, 526, 715, -232, -742, -191, -21, 65, 1479, 84, 389, 658, 385, 674, 729, 169, 221, 7, -27, 811, 841, -1080, 645, 14, -1033, -1146, -472, -74, 265, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H0[64] = {356, -364, 862, -1113, -938, 408, 1437, 968, 987, 664, -411, -881, 756, 768, -795, 77, 326, 481, -714, 196, -110, -215, 106, 621, -812, 542, 213, 1043, -188, -725, -266, -114, 785, -690, 427, 627, 1001, 796, -752, -410, -760, -304, 129, 1112, 62, 805, -1030, 382, -1195, -1002, 855, 1261, 1026, -281, 57, -850, 763, 77, 738, -135, 1189, 65, -1168, 617, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H1[64] = {536, 374, 293, 992, -103, -576, -463, -1069, -605, 1261, 597, -599, 643, -622, 268, 603, 712, 373, -455, 8, 760, -1245, -460, 201, 1035, 731, 955, 626, -131, -759, 43, -722, -817, -398, 168, 999, 474, 150, 639, -148, -359, -493, -551, 339, -737, 825, -827, -86, -681, 474, 757, -1097, -858, -351, 372, -792, -44, -609, -879, 540, 286, 701, 875, 406, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H2[64] = {764, 345, -422, -624, 1231, 99, -640, -1501, -301, -900, 283, 1233, -1172, 202, 1417, -498, 544, 858, 106, 761, 381, -695, -1310, 63, 651, -635, 946, 848, 999, 198, 84, -923, 1050, 851, -766, -870, -854, -29, 999, 47, -538, -926, -208, 448, 898, 61, -418, 1075, 429, -731, -414, -264, -538, 892, 876, 667, 311, -928, -294, 449, -854, 53, 670, -212, };
+int32_t transformer_layers_0_0_fn_to_qkv_weight_V_H3[64] = {-944, 62, 621, 124, -535, -149, 709, 95, 1129, 832, -644, 656, 547, 233, -187, 737, -793, 821, 16, -558, 129, -235, -896, 491, 753, 42, 343, 894, -531, -820, 518, -426, -787, 3, -398, -1120, 1170, 1063, -813, -105, -78, -135, 248, -263, -351, -172, 224, -430, -1072, -956, 331, -6, -221, -602, -34, 0, 913, -859, -110, -512, 1154, 657, -630, 8, };
+int32_t transformer_layers_0_0_fn_projection_weight[256] = {-402, -1077, -244, -103, 318, -176, 766, -1187, -866, 337, 1127, 451, -280, -1007, -185, -704, 654, 854, 369, -532, 565, -666, 1063, 433, 312, 232, 211, 846, 273, 115, -969, 847, -514, 236, -588, 549, -298, 759, -253, 1035, 6, -854, -445, -1030, -204, -85, -398, -307, 785, 142, -1233, -991, 496, 512, -675, -12, 172, 11, -1111, -633, 573, 502, -201, 322, -391, 248, -499, -56, -559, -305, -527, 629, 315, 130, -98, -248, 172, 148, 36, -337, 494, 353, 696, 517, 187, -1141, 985, -1041, -1095, 86, -29, 626, -1129, 678, -357, 67, 557, 291, -223, 493, -797, -561, 1218, -793, -542, 266, 275, 229, -637, -993, 965, 673, -884, 707, -19, -635, -663, -730, 87, 528, -179, 1047, -677, 1117, -854, -716, -700, 234, -970, 807, -180, -116, 1006, -13, -1029, -40, 182, 390, -1164, -858, 584, -453, 202, -765, 821, 362, -337, -572, 40, 20, -963, 525, -390, -743, 990, -432, 156, -54, 629, 666, -252, 461, 486, -5, 762, -728, 3, -742, -741, 1112, 1431, 1199, -676, -393, 403, -522, -474, -760, 508, -904, -265, 203, 78, -1096, -852, 587, 113, -680, 171, -308, -231, -484, -210, -463, 635, -561, -1093, 140, 509, -767, -329, 120, 518, 396, 280, -194, -414, 772, -697, -104, 218, 260, -105, 210, 1339, -369, -991, 856, 977, -735, 664, 306, 405, -156, -290, -772, -732, 594, -101, 930, -1060, 1133, 977, -515, -736, -390, 1010, 118, -351, -652, 74, -553, 216, -609, 289, -209, 1004, 930, 462, 171, 755, -914, -686, -185, -616, -648, };
+int32_t transformer_layers_0_0_fn_projection_bias[16] = {-840, -92, -107, 118, 323, -361, 278, -5, 135, 300, -784, 540, -15, 380, 771, 648, };
+int32_t transformer_layers_0_1_norm_weight[16] = {3913, 4457, 4086, 4198, 3935, 4065, 4044, 3934, 3956, 3983, 4205, 3852, 4319, 4076, 4119, 3967, };
+int32_t transformer_layers_0_1_norm_bias[16] = {-176, -178, -255, 86, 151, -163, -161, -8, 155, -133, -118, 180, -206, 30, -113, -222, };
+int32_t transformer_layers_0_1_fn_ff1_weight[64] = {-269, 879, 417, 125, -1042, 562, 825, 151, -22, 941, 340, 837, -99, -941, -81, -34, 779, -802, -170, 98, -331, -642, 898, 694, -266, 574, -677, 748, -770, -37, 501, -738, 539, -756, 846, -539, 380, 724, -628, 795, 1144, 372, 525, 499, -257, -2, -298, -356, -821, -8, 829, 852, 205, 290, -229, 201, -910, -991, -340, 841, -610, 961, 227, 151, };
+int32_t transformer_layers_0_1_fn_ff1_bias[4] = {-143, -827, -308, 129, };
+int32_t transformer_layers_0_1_fn_ff2_weight[64] = {305, -252, 1555, 1351, -1680, 1389, 1229, -741, -1475, 285, -203, -1095, -1407, -1403, -1965, 1256, -273, -533, -1, -1734, -417, 176, -253, 1055, -326, -525, -1, 343, -413, 309, -1034, -1608, -1219, -547, -472, -663, -1628, -1026, -56, -1330, 673, 451, -900, -1720, 2030, 607, 1103, -1915, 1853, 911, -939, 398, 21, 15, 1670, -409, 378, -1568, 1405, 1371, 933, -759, 545, -2014, };
+int32_t transformer_layers_0_1_fn_ff2_bias[16] = {837, -1010, 736, 2060, 1857, -1132, 728, -1052, 947, 1603, 1612, 1908, 1519, 508, -1745, -1202, };
+int32_t transformer_layers_1_0_norm_weight[16] = {3943, 4401, 4285, 4286, 4112, 4059, 4094, 4023, 4156, 4435, 4079, 4136, 4219, 4111, 4081, 4076, };
+int32_t transformer_layers_1_0_norm_bias[16] = {-44, -53, 85, 19, -34, -44, 71, -39, 40, 66, -63, 14, 27, -106, -87, -76, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H0[64] = {495, 600, -127, -357, 489, 355, 41, 97, 758, -317, 99, -403, 730, 452, -27, 354, -495, 997, 387, -732, -742, 475, 67, -193, 464, 305, -691, 995, 902, 1007, -985, -300, -608, 939, -555, 527, 454, -789, 77, 203, 550, 130, 912, 756, 104, 733, -477, -462, -25, 816, -253, -828, -407, 607, -1024, 458, -159, -75, -422, -327, 772, -845, 661, 673, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H1[64] = {-780, -895, 1016, -316, 1036, -767, 839, -289, -582, -1437, 46, -283, -830, 69, 661, 720, 925, -302, -908, -185, -771, 486, 460, -953, 327, -491, -209, -21, 210, -935, -445, 117, 541, -967, 810, -458, -985, -328, -38, 647, 456, 982, -64, -586, -155, 738, -358, 85, -536, 5, -210, 168, -628, 278, -280, 13, -793, 687, 18, -27, -340, 178, 258, -977, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H2[64] = {-397, -371, 571, 275, -30, 516, 642, 475, 831, 781, -398, -383, -510, 210, -543, 47, -637, 293, 625, -645, 40, -892, -734, 402, -172, -431, 7, -150, -549, 512, -208, 249, -527, -433, 922, 769, -788, -851, 328, 370, -51, 214, -971, -639, -809, 119, 54, 694, 746, -331, -515, 64, -894, 340, -713, -372, 540, -418, 924, 572, 1071, 882, 877, -633, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_Q_H3[64] = {476, -152, -876, 172, -361, -748, -636, -123, 162, -616, -504, 793, 661, 27, 626, 102, -518, 900, 891, -508, -848, -553, 519, 101, 122, -683, -204, 986, 44, 263, 421, -1069, 811, -302, 909, 942, 864, 478, -225, -1105, -470, 4, 387, 537, 133, 434, -6, -780, 301, 739, 1092, -834, -1072, 173, 106, 480, 981, -1, -672, 1039, -32, -769, -809, -673, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H0[64] = {-536, -105, 457, -372, -36, -789, 776, -669, 705, -386, -480, -493, -216, 652, -161, -285, 385, 1026, -222, 268, -761, -564, 815, 991, -417, -308, 967, -141, 950, -843, -774, 222, -9, -387, 466, 539, -385, 108, 569, 873, 607, 184, -627, -371, 92, 143, 355, 885, 141, 339, 397, 598, -574, 500, 226, 716, 449, 328, 820, -210, 614, -841, -650, -881, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H1[64] = {487, 12, -424, -75, 464, 210, 601, -479, 874, -114, 421, 630, 621, 563, 671, -886, 856, -783, 351, 676, 1263, -231, 1, -862, 609, 307, -259, -737, 649, -552, 811, -851, 764, -42, -780, -1011, -595, 521, -447, -604, -581, 286, -718, 184, -32, 81, -644, 927, -789, -145, 864, 638, -400, 675, -935, -786, 1144, -920, -702, 755, -341, -782, -596, 566, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H2[64] = {339, 539, 363, -56, -218, 918, 616, -856, -651, 992, -167, 175, 652, -456, -927, 539, -234, -846, -502, 924, 457, -677, -48, 41, -224, 685, -994, -17, -373, 766, 1014, -845, 509, -554, -878, 187, 824, 437, 871, 410, 1037, 18, 459, -666, 496, 360, -294, 407, 245, 266, -455, -167, -1086, -133, -739, 1113, 462, -910, 764, 1087, 238, -358, -725, -713, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_K_H3[64] = {-909, -289, 660, -80, -802, 331, 600, 430, -889, 182, 205, -1121, 799, 211, 337, -537, 1094, -867, 396, 415, 806, 787, 683, 530, 240, -442, 73, -203, 433, 326, 802, 184, 1048, 362, 49, -755, 903, 970, 491, -289, -807, -123, -625, -826, -348, -711, 943, -872, 369, 459, -610, -780, -902, 865, -479, 952, 251, 723, 10, 137, 110, 432, 545, 827, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H0[64] = {-904, -972, 395, -281, 1346, 1215, 17, -994, -340, 936, -382, -125, -644, -779, -546, 815, 142, 820, 98, 552, -377, 959, 1113, 123, -221, -107, -964, -219, 206, 648, 834, -596, -35, 431, 658, 398, -1069, -140, -465, -39, 455, 824, -75, 420, -270, -55, 619, -394, -685, 548, 194, -23, 38, 815, -786, 474, 684, 318, -763, 593, -655, -618, -263, 251, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H1[64] = {550, 404, -867, -355, 1129, -344, -759, 403, 203, 811, 891, 674, 433, 812, 428, 68, -321, 344, -725, 560, 425, 801, 653, -328, 60, 269, 427, -15, -159, 367, 235, -599, 8, -1167, -239, -594, -544, 871, 675, 78, 607, 621, -244, -492, 415, 668, 1004, -170, 961, -1137, -717, 1007, 228, -242, 508, 511, -703, 429, 800, 807, 826, -723, 855, 790, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H2[64] = {137, -567, -524, -1077, -226, -320, -619, -639, -215, 351, 297, -193, 280, -282, 92, 700, 987, -271, 103, -408, 138, -763, -252, -592, 890, 463, 961, -740, -487, 323, 233, -639, -752, -186, 124, -984, -70, 996, 194, 663, 72, 109, 382, -590, 948, 98, -885, -1018, -411, -896, 847, 478, 16, 0, -861, 876, -875, -176, -784, 30, -797, -803, -906, 896, };
+int32_t transformer_layers_1_0_fn_to_qkv_weight_V_H3[64] = {523, -54, 650, 319, 905, -162, 443, -845, -509, 320, -1008, -984, -99, 709, -64, -938, 175, -357, -351, 40, 777, 340, 1157, -867, -689, 733, 553, -237, 721, -1006, -476, -684, -446, -31, -974, 214, 469, -240, -1137, -233, 285, 528, 266, -798, 538, 786, 438, -717, 586, -872, -901, 1040, 137, -19, 215, -995, -446, -870, 675, 139, 103, -691, -115, -573, };
+int32_t transformer_layers_1_0_fn_projection_weight[256] = {-961, -497, -218, -462, -752, 764, 182, -416, 43, -295, -1317, -752, 990, 758, 595, 383, -297, 299, -272, -565, -953, -338, -303, 1186, 1256, 504, -455, 329, 353, -416, 202, 446, -869, 19, -776, -409, 959, 382, -5, 278, 503, 440, 209, 407, 410, 406, -331, 877, 463, 721, 65, -135, 293, -336, 674, -687, -1054, -331, -225, -675, -963, 710, 728, 790, -392, 108, -834, 300, -154, 767, 401, 421, -820, 246, -236, -957, 669, 358, 483, 60, 249, 66, 1149, -828, -539, 332, 57, -1235, 282, 268, 978, 216, -830, -553, -541, 279, -214, -340, 977, -249, 205, 70, -401, -502, 17, 1231, 634, 390, -937, 15, -798, -473, 50, -277, -825, 504, 79, 163, -647, -875, -860, 161, -256, -936, 594, -491, -403, -47, 643, 316, -778, 1075, -1066, -1276, -590, -713, 888, 114, 749, -78, -257, 103, -363, 247, -128, 40, 1004, 152, 639, 171, -485, -1083, 70, 342, 903, 569, -606, 472, -894, -585, -682, 488, -726, 169, 16, -905, -906, -734, 796, 697, -527, 807, -1091, -911, -320, -791, 718, 622, 475, -343, 853, 769, 884, 564, -1171, -59, 180, 14, 288, -1012, 1087, -518, -549, 777, 576, 765, -356, 945, 640, -174, 238, 281, -341, -889, 1007, 311, 40, -45, 633, -584, 1091, -101, -801, -483, -527, 411, 164, 457, 365, 19, 209, -542, 114, 352, -625, 590, 666, -706, 1037, -388, -993, -373, 240, -343, -914, 856, 956, 617, 982, -140, 371, -455, 208, 973, 133, 652, -646, 344, 297, -880, -97, 271, -380, -219, 827, 596, };
+int32_t transformer_layers_1_0_fn_projection_bias[16] = {-736, 309, -43, -180, -220, -446, 37, 54, 389, -788, 1114, -969, -17, 10, 286, 852, };
+int32_t transformer_layers_1_1_norm_weight[16] = {4083, 4051, 4008, 4127, 3974, 3860, 4095, 4052, 3996, 4005, 4114, 4195, 3983, 4097, 4071, 4004, };
+int32_t transformer_layers_1_1_norm_bias[16] = {137, -2, 135, 87, 127, -139, -134, -96, 67, 14, -108, -63, -78, 31, 15, 53, };
+int32_t transformer_layers_1_1_fn_ff1_weight[64] = {-127, -843, -176, -862, -255, -382, -561, 758, -943, -676, -585, -721, -737, -526, -519, -110, 481, 81, -122, -888, 358, 455, 170, 527, 336, 86, 266, 133, 896, 362, 806, -114, -894, -490, -7, 55, -544, 938, 456, -382, 987, -919, 127, 210, 427, -677, 788, -316, 776, -675, 152, 89, -813, -174, -14, 274, 317, -26, 399, -560, -367, -255, 649, -1004, };
+int32_t transformer_layers_1_1_fn_ff1_bias[4] = {90, -953, 421, -933, };
+int32_t transformer_layers_1_1_fn_ff2_weight[64] = {-1042, -1584, 1737, 504, -1780, 1348, 536, -1647, -1350, 839, -1377, 663, 455, -1985, -1640, 1642, 1730, -960, -1286, -54, -1541, 714, 971, 579, -69, 1795, -831, -1040, 1600, -382, -1386, 245, 1170, 1367, -210, 904, 1794, -1331, -524, -1304, 84, 743, 593, -621, -1397, -1482, 1047, -849, -1283, -1557, 911, 218, -1263, -1694, 1757, 1760, 812, 762, 1568, 1882, -1391, 1405, -244, 478, };
+int32_t transformer_layers_1_1_fn_ff2_bias[16] = {-1109, -350, -895, 2006, 686, -472, 1124, 1903, 1174, -405, -1500, -440, -422, -142, 1269, -836, };
+int32_t transformer_layers_2_0_norm_weight[16] = {4135, 4645, 4316, 4215, 4243, 4415, 4186, 4002, 4224, 4214, 4305, 4162, 4319, 4117, 4437, 4432, };
+int32_t transformer_layers_2_0_norm_bias[16] = {-10, -219, 118, -51, 66, -61, 16, 57, 4, 67, 27, 112, 24, -177, -70, 114, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H0[64] = {750, 642, 712, 102, -275, -314, 514, -1305, 48, 907, 72, -639, -859, -1227, -96, 131, -174, 771, 585, -694, 1109, -192, -60, -1356, 95, -133, -539, -295, -1002, 421, -649, 590, 403, 1025, -703, 311, 867, 275, -77, -759, 624, -841, -753, -297, -807, 129, 827, -804, -772, 63, 894, -59, -512, -206, 425, 657, 431, -1100, -646, 1259, -1036, -1045, 252, 1058, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H1[64] = {-101, 525, -497, -703, 267, -890, -574, 202, 304, -567, 1090, -181, -37, -245, -262, 545, -260, 686, -634, -882, 1059, -247, -562, -1061, -944, -143, 1018, -218, -608, -752, -127, 623, 467, -1114, -92, -355, -635, 947, 626, 710, -41, -864, -216, 275, -567, 834, -282, -558, -925, 848, 565, -826, 129, -724, 323, -1025, 681, 725, -81, -38, -463, -653, 1066, -210, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H2[64] = {-1000, -805, 417, -430, -467, 482, -643, 174, 646, -165, -599, 93, 65, -1101, 230, 546, -172, -758, -61, -837, 974, 408, -104, -727, -296, -456, -186, -148, -786, 216, -490, -825, 362, 932, -340, 816, 142, 20, -125, -1072, 390, -69, -839, 806, 830, -740, -407, -804, 1087, 182, 602, -206, -283, -331, -868, 454, 758, -753, -277, 266, -147, 297, -885, -669, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_Q_H3[64] = {890, -862, -125, -582, -1112, -1234, 52, -854, -742, -485, 26, -1324, 767, -304, 274, 490, 285, -878, -741, -904, -46, 536, -1020, -689, 33, 434, 481, -13, 67, -67, -28, 798, 162, 915, -629, 766, -1016, -907, 705, -1195, 1089, 399, -878, -55, -212, -838, -19, -777, 207, -357, -446, 28, 210, -1012, 500, 196, -409, 121, 470, 957, 885, -742, -227, 284, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H0[64] = {196, -857, -988, -250, 851, 1125, 256, 246, -13, -115, 43, 444, -62, 5, 196, 922, 603, 803, 7, -895, 225, 886, -688, 262, -355, -427, 167, 47, -220, -688, 373, -63, 36, 672, 524, -170, 675, 562, -1017, 662, -648, -36, -1136, 523, -305, 50, 303, 147, 246, -676, -142, 524, 327, 584, -688, -1043, 1089, -277, 414, -934, 798, 883, 1051, -572, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H1[64] = {893, 528, -509, -849, 255, -684, -717, 423, 113, -646, -210, -702, -66, 1028, -1014, -219, -40, -803, -291, 773, -187, 46, 954, 809, -872, 516, 833, -855, -848, 835, -481, 54, -295, 326, 904, 732, 338, 604, 78, -733, 129, 699, 498, 835, -949, 376, -955, -820, -618, 1033, 981, -643, 906, -534, -1152, 65, -322, 66, -274, 926, -558, -402, -926, -78, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H2[64] = {1036, 778, -513, 648, 42, 482, -147, 968, 12, -521, -380, 241, 982, 639, -959, -558, -511, 941, 56, -425, -745, 546, -937, 670, 819, -652, 739, -106, -552, -691, 445, -287, 30, -36, -715, -196, 884, -637, 0, 586, -230, 692, -169, -1036, 9, 548, 426, 797, 300, -356, -648, -432, 1287, -533, -110, -604, 835, 396, 466, -484, -443, 443, 421, -29, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_K_H3[64] = {-1028, -82, 553, 856, -861, -129, 600, -637, 300, -239, 141, -296, 443, 358, 949, 498, -736, 977, 339, 225, -1016, -994, 330, -1120, 1007, 178, -78, 1380, -459, -932, 620, -454, -671, -885, -617, -1051, 1021, -378, 542, 1186, 512, 608, -809, 418, 153, -173, -46, -342, -1247, -413, 461, -858, 482, -234, 593, 168, -638, -919, -2, -734, -703, -717, 275, 1043, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H0[64] = {-569, -735, 276, 102, -180, 537, -520, 1212, 789, -363, 25, -565, 952, 177, 147, -941, -448, -1023, 433, -198, 197, 686, 450, 217, 498, 850, 455, -791, 992, 707, 544, -393, 914, 631, -407, -221, 131, 614, 619, 430, 710, -753, -270, 347, 115, 834, 648, -138, -386, -1090, -122, 758, 753, 488, -639, 843, 35, 193, -708, 1173, -499, -677, -894, -551, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H1[64] = {189, 384, -576, 584, 707, -516, -1085, 81, -652, 809, 849, 929, -834, 725, 256, -568, -77, 932, 4, 445, -174, -238, -718, -991, 539, -472, -577, -951, -1016, 229, 73, 838, 980, -710, -18, 111, -583, 916, 1046, -814, 551, 95, 777, -46, 975, 27, 252, 362, -772, -863, -803, 496, 855, 100, -481, 357, 577, 945, 630, 44, 712, -157, -147, 1142, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H2[64] = {668, -279, 884, 126, -1152, -408, 994, -84, 549, -356, -363, -365, 596, -513, 305, -212, 175, 181, -1146, -1, 588, 511, 147, 231, -751, -28, 129, 877, 385, 904, -362, -628, -290, -366, -1028, -102, 909, -942, 1006, 653, 454, -908, 1069, -462, 1201, -227, -847, -775, -1091, 75, -924, 178, 87, 519, 431, 287, -411, 100, 605, -926, 593, -438, -588, 618, };
+int32_t transformer_layers_2_0_fn_to_qkv_weight_V_H3[64] = {496, 644, 748, 90, 519, 492, 816, -402, -44, -1013, -886, -581, 880, 744, -302, 821, -992, 729, -44, -493, -1191, -137, 352, 950, 342, -211, 347, -1036, 125, -31, 912, 313, -1230, 354, 356, -195, 220, -693, -1152, 538, 1248, -1006, 152, -822, -541, -813, 12, -269, -863, -739, -438, -650, -250, 770, 240, 195, -813, 411, 597, 1034, -114, -202, 777, -162, };
+int32_t transformer_layers_2_0_fn_projection_weight[256] = {-250, -616, -353, -787, 606, 329, 1043, 644, 827, -65, 841, 68, -804, -131, 515, 298, 594, 611, 284, -40, -72, -695, 564, -25, -141, -9, -936, 100, 318, 1101, -899, -442, 755, -919, -439, 111, -58, -1232, 34, 191, -666, 651, -416, -578, -160, -1101, 927, 786, -1151, 834, -830, 143, -180, 381, -887, 812, 755, -287, -1322, 98, 629, 499, 917, 957, 261, 509, -1001, -522, -102, -106, -48, -816, -161, -516, 345, 373, -881, 1022, -493, 648, 1124, -152, -542, -293, -708, -46, 779, -106, -1112, 1022, -634, 145, 401, -1117, -374, 775, -378, -672, 956, -497, 798, -1060, 359, -1384, -853, 802, 1090, -431, -391, -659, -931, 348, 565, 363, 395, -576, -696, 206, 157, 741, 253, -57, 848, -844, -828, -758, 621, -122, -565, 1162, 834, -754, -840, -883, 464, -1167, -816, 670, 613, 272, -459, -529, -585, -854, -559, 925, 240, 1169, -413, -69, -1001, 513, 571, -426, 359, 319, 612, -510, -580, -707, 391, 896, 354, -1138, 922, 943, 115, -252, 36, 225, -326, 598, -232, 828, -678, 621, 582, 930, -1020, 375, -504, -157, -669, -629, 577, -491, 312, 701, -909, -779, -159, 95, -738, 806, 1109, 64, -398, -15, 1345, -1061, -833, 827, 756, -223, 460, -359, -417, -114, 719, -1035, -180, -515, 124, 428, -975, 993, 533, -1178, 966, -308, 575, -908, -113, -656, -439, -547, -542, -343, 1116, -219, -704, 32, -184, -1065, -794, 784, 247, -762, -59, 35, -98, 387, 100, 593, 748, 564, 413, 453, -306, -254, 7, -255, -889, 814, -766, -481, };
+int32_t transformer_layers_2_0_fn_projection_bias[16] = {194, 93, 543, 448, -911, -445, 195, -40, 634, 876, 754, -1012, 50, 857, -446, -108, };
+int32_t transformer_layers_2_1_norm_weight[16] = {4070, 4054, 4113, 4250, 4054, 4081, 4083, 4181, 3917, 4167, 4225, 4116, 4074, 4125, 4118, 4086, };
+int32_t transformer_layers_2_1_norm_bias[16] = {42, 64, -32, 110, 137, -170, 140, 80, -43, -16, 168, -178, 100, 6, 44, -66, };
+int32_t transformer_layers_2_1_fn_ff1_weight[64] = {-874, -1079, -163, 736, -294, -562, -500, 987, 108, 568, -363, -934, -409, -573, -1048, -366, 277, -902, 259, 602, -45, 983, 366, 811, -394, -751, -662, -964, -400, -240, -967, -749, 166, 599, -648, -608, 618, 609, -928, -602, 56, -852, -818, -343, -398, 671, 187, 523, 906, -568, 602, 1123, 788, 123, 297, 817, -692, -732, -585, 704, 1029, 787, -902, 971, };
+int32_t transformer_layers_2_1_fn_ff1_bias[4] = {267, 470, -574, -399, };
+int32_t transformer_layers_2_1_fn_ff2_weight[64] = {1877, 1625, -992, -1629, -1178, -1784, 4, -1248, 905, 507, 1721, -4, 1659, 420, -527, 1624, -482, 1213, -223, 1858, -200, -1466, -160, 330, 1406, 396, -1566, 1945, -1635, 733, -1490, -1626, 404, -1409, -268, 1645, 1503, 1635, -1849, 1682, -1379, 1453, -465, 666, 593, -578, 1630, -747, -1665, -1625, 436, -1834, -1397, 1706, -1779, 42, -96, -1266, -1052, 1321, -1843, 128, -1722, 1636, };
+int32_t transformer_layers_2_1_fn_ff2_bias[16] = {-473, -1167, 1703, 46, 113, 609, -1347, 396, -303, -1647, -449, -372, 176, -1396, 1388, -966, };
+int32_t transformer_layers_3_0_norm_weight[16] = {4331, 4371, 4459, 4169, 4329, 4301, 4145, 4299, 4294, 4423, 4268, 4098, 4104, 4173, 4155, 3944, };
+int32_t transformer_layers_3_0_norm_bias[16] = {-9, -50, -35, -36, 149, -24, -70, 75, 0, 43, 35, -47, -72, 36, 13, 91, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H0[64] = {812, -991, -1033, 164, -795, 579, -348, 766, 1070, 162, 149, -447, 298, -560, 489, -455, -458, 1003, 28, 1178, -74, 572, 1063, -531, 288, -656, 52, -852, 268, -340, 554, 363, -261, 534, -24, -513, -736, 186, -265, -656, -131, -1131, 917, -628, -624, -829, 190, 508, -405, 31, 991, -533, 728, 1148, 761, -174, -792, -169, 356, 52, 950, 90, -723, 659, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H1[64] = {417, 44, -833, 344, 124, 505, 217, 114, -753, -223, 59, 506, 404, 796, 326, -824, 45, -937, -647, -1044, 367, 197, -42, 101, 914, -45, 768, 244, 988, 114, 388, 165, 502, -169, 880, 852, -46, -1099, -445, 420, 903, 508, 945, -334, 729, -605, 8, -69, 950, 0, 277, 227, -321, -251, 636, 393, 441, 75, 269, -270, -713, 662, -916, -227, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H2[64] = {-625, -372, 134, 911, -887, 1167, -760, 713, -72, 576, 108, -1107, -353, -550, 605, -319, -229, 136, 335, 688, 221, -610, 366, 98, -380, -125, -61, -205, -432, 389, 110, 286, 1046, 550, -314, -243, 626, -699, -397, -950, 806, 553, -298, -1018, 713, 74, 860, 746, 348, -952, -293, 440, 797, -396, -340, -810, 182, 1001, 47, 626, 734, 45, -284, -563, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_Q_H3[64] = {1082, 533, -719, 574, 747, -378, 72, -655, 244, -372, -790, -465, -449, -305, 970, 536, 218, -626, 396, -1083, -413, -840, 679, -186, -650, 865, 721, -883, 882, -1084, 614, -783, -846, 623, 94, 490, 1052, -340, -1226, -483, -16, -382, 717, 491, -780, -723, -848, -613, 345, 648, -319, -34, -72, -347, 989, -457, 377, -805, -29, 734, 973, 791, 861, -764, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H0[64] = {-521, 858, 454, -495, 916, 442, -168, 604, 411, -89, 999, 1, -96, 421, 95, 197, -129, -822, 103, 866, -480, 714, -342, 656, -813, -974, 231, -1000, 783, -582, -154, -1051, -942, -760, 788, -81, -396, -102, 270, 72, 1116, -755, -832, 101, 1, -476, 195, 308, -144, -1003, -811, 813, -853, 1089, -738, -198, -100, 252, 935, 526, 115, 513, 18, 735, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H1[64] = {-918, -29, 832, 896, -778, 564, -148, 730, -237, 85, 834, 823, -836, 820, 575, 638, 661, 140, -132, 629, -1014, 82, -486, -571, 994, -457, 1027, 346, 445, -634, -202, 487, 587, 25, 580, 854, -154, -265, -46, 733, 728, 507, -780, -448, -367, -229, 937, 305, 293, -1028, 445, -37, -608, -867, 512, 240, 230, -243, -412, -676, 930, 645, -19, -602, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H2[64] = {-77, -1040, 122, 316, -714, 687, -1048, -1038, 982, -600, -161, 541, -937, -978, 541, 656, 134, -443, -314, -18, 239, 44, 138, -596, -403, 588, 715, 958, 812, -651, -300, 441, -765, 319, -127, -1081, 385, -228, -45, -405, 134, -655, 949, -141, -850, 513, -829, 466, -601, -76, 280, 217, 155, -150, 1085, 409, -572, 165, 818, 548, -504, -663, -25, -151, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_K_H3[64] = {-822, -987, 500, 498, -380, 118, 296, -875, -428, 525, 721, -948, -96, -220, 952, -534, -1220, -182, -802, -290, 53, 825, -687, -910, 930, -42, -265, -297, 1184, -688, -121, -414, 524, -856, -476, 496, 631, 134, 1193, -132, 486, -166, 691, 1058, 274, -1097, -921, 388, 993, -9, -933, 525, -20, -405, -604, -828, 207, -280, -1049, 406, 872, -153, 134, -7, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H0[64] = {883, 284, 1094, -584, -1043, 1291, -1017, 538, 1181, -826, 537, -743, 1056, -1051, 1065, -347, 947, -152, -36, -529, -394, -532, 143, -447, 819, 768, 375, -626, 107, 1032, -154, 691, 845, 1047, -224, 931, 1173, -396, -983, -455, 16, -1076, -83, 121, -988, 816, -291, 72, -1167, -783, 823, -605, 196, -86, -857, 738, -495, 625, -374, -571, 128, -985, 844, 796, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H1[64] = {-121, -695, 45, -12, 29, 145, 226, 781, -515, 970, 780, 1133, -311, -960, 447, 445, 896, -274, 519, -1066, -274, -909, 923, 193, 246, 733, -661, 1113, -95, -1037, -874, -375, 807, -375, 333, -1144, 290, -112, -464, 1003, -578, -207, 751, 1000, 582, -342, 641, 775, -672, 604, -283, 834, 8, -312, -856, -454, 326, -226, -11, -959, 70, 1098, -225, -777, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H2[64] = {800, -780, 659, 436, 608, 983, -692, -810, 1055, 209, -284, 989, 203, -579, -376, 84, -312, -39, 309, 272, -631, -387, 500, -413, 866, 99, 322, -723, -751, 811, 635, 257, -571, 521, 454, -915, 239, -332, 381, -897, 1141, 265, 813, 83, 105, 243, -431, -597, -886, -987, -1014, -252, -271, -94, -218, -324, -948, 846, 376, -282, -851, 724, -920, 601, };
+int32_t transformer_layers_3_0_fn_to_qkv_weight_V_H3[64] = {-539, 136, 319, -1137, 523, -281, -164, 890, -243, -237, -195, 331, 203, 862, -165, 188, 480, -509, 632, -963, 98, -30, -1019, 1024, -732, -486, -843, -480, -458, -729, 528, 728, -402, -495, -697, 1208, 689, -417, 308, -1250, 809, -878, 772, -534, 648, -420, -677, -614, 230, 167, -953, 828, -357, 801, 752, 1045, -868, 305, 622, 1084, -482, 809, 990, 825, };
+int32_t transformer_layers_3_0_fn_projection_weight[256] = {342, 5, -248, -706, 551, -1138, -335, -803, -1059, -259, 550, -227, -212, -948, 336, -347, 724, 0, -258, -610, 104, 853, -1145, 801, 45, -122, -296, -960, 979, -164, 227, -633, 291, -29, 331, -570, -899, 539, 166, -885, 666, -86, 227, -209, 44, -1134, 439, 556, 428, -932, 165, 517, 13, 135, -735, 917, 412, 6, -317, -426, 450, 310, 11, 70, -476, -749, -107, 792, -254, 818, -650, 707, -400, 687, 222, 431, -284, -826, 120, 150, -819, -614, -974, -859, 345, 367, -32, -770, -762, 372, 1068, 352, -201, 500, 166, -592, 665, -217, 231, 366, 564, 47, -268, -925, 1011, -851, 371, 688, -1137, 740, 918, -1041, 971, 42, 914, -1073, -248, 73, 271, -1088, 335, 392, -633, 626, 233, 825, 398, -790, 157, 1155, 441, -655, 356, -920, 699, -145, -525, 955, 180, -23, 97, 817, -420, -964, 1096, -19, -195, -12, 843, 359, -504, 273, 655, -269, 438, 373, -546, -25, 663, -717, -136, -276, 938, 78, -921, -687, 740, -459, -1038, -826, 965, -535, 352, 804, 894, 293, -451, 707, 613, 768, -1007, -1111, 410, -671, -224, 418, 773, 388, -242, -517, 908, 3, -794, 179, -520, 518, -565, -638, -300, 55, 888, 790, 754, -689, -561, 358, 723, -21, -528, 557, 1065, -476, -312, -544, -658, 803, -328, -464, -309, -778, -558, 298, 299, 445, -143, 526, 1111, -49, -762, -721, -224, -158, 529, 1242, -545, -287, -974, -391, 603, 743, -589, -1132, 55, 661, 757, 273, -1212, 1374, 396, -276, -975, -866, -192, -78, 168, -164, };
+int32_t transformer_layers_3_0_fn_projection_bias[16] = {-513, 807, 27, 109, 381, 633, 651, -345, -188, -948, -40, -1119, 69, -344, 610, -562, };
+int32_t transformer_layers_3_1_norm_weight[16] = {4014, 4033, 3946, 3968, 4029, 3985, 4117, 4068, 4052, 4005, 4190, 4268, 4082, 4047, 4155, 3996, };
+int32_t transformer_layers_3_1_norm_bias[16] = {114, -8, 39, -134, -76, -28, -5, -45, -16, 95, 69, -148, 162, 32, 143, -74, };
+int32_t transformer_layers_3_1_fn_ff1_weight[64] = {45, -294, -338, -514, 405, -861, -371, 974, 831, 195, -815, 159, -8, -783, 753, 635, -125, 722, 314, 472, -678, 633, 911, -906, 948, -593, -502, 602, 482, 1182, 18, -479, -804, 954, 458, 242, -300, 779, -731, 989, 108, -1102, -456, -82, 914, -716, 923, 673, -451, 517, -480, -898, -279, 521, -213, 1045, -1039, 728, -1044, -504, 824, -374, -136, 480, };
+int32_t transformer_layers_3_1_fn_ff1_bias[4] = {420, -528, 708, 556, };
+int32_t transformer_layers_3_1_fn_ff2_weight[64] = {-1264, -245, -243, -1258, -1099, -1898, -832, -1786, -91, -535, 338, 531, 99, 47, 1132, -293, 1776, -1641, 1705, -1170, 1156, 1020, -187, -1538, -652, 147, -962, -721, 748, -398, -1670, -84, 1373, 389, -1031, -329, 520, -615, -769, 1458, 1650, 1183, 1178, -137, -775, -271, -1281, -1755, 1191, -1755, -561, -1893, -104, 833, 1300, 1269, 1925, 1248, -225, 316, 1618, -1789, 479, -958, };
+int32_t transformer_layers_3_1_fn_ff2_bias[16] = {170, -517, 322, 1989, -502, 37, -357, 766, 1958, -45, 1673, -1260, 1175, -1481, -1355, 818, };
+int32_t mlp_head_layer_norm_weight[16] = {4039, 4009, 3972, 4135, 3957, 4168, 4133, 4187, 4009, 4196, 4210, 4267, 4051, 4053, 4018, 3976, };
+int32_t mlp_head_layer_norm_bias[16] = {-17, 24, 34, 16, -13, -23, -17, 16, 1, -62, 29, -4, 6, 46, 47, -28, };
+int32_t mlp_head_linear_weight[256] = {-400, 764, -464, -564, 75, -317, 351, -609, -341, -736, 55, 467, -747, 464, -536, 11, -341, 380, 479, -292, 53, 351, -332, 245, 155, -579, 630, 827, 727, 483, -86, 108, 213, 752, -431, 437, 649, -37, 685, 776, 793, -899, 934, 175, 432, -808, -868, 652, 337, 186, -967, -417, 839, -193, -764, 361, -577, 497, 103, 29, 709, 472, 390, -606, -656, -616, -69, -770, 191, -494, 187, 355, 687, -821, -806, 283, 407, -555, -704, -244, 293, -970, -991, 380, 67, 390, 291, 35, 677, 337, -688, -817, 332, 688, 115, -779, 759, 534, 1055, 544, -116, -636, -247, -774, -784, -208, -659, 704, 557, 19, -829, 373, -758, -1026, -1167, 763, 885, -721, -593, -330, 864, 108, -561, 49, 217, -543, 154, -191, 121, -393, 365, 39, 803, 558, -218, 55, 207, 304, -657, -35, -421, 416, 483, 446, 703, 943, 692, -200, -8, 13, 895, -533, 740, -906, -911, -388, 582, -75, -1053, 767, 540, -323, 452, -414, -781, 723, 942, 1029, -920, 937, 884, 1034, 698, 554, -1068, 265, 816, 549, -8, -511, -490, -485, 385, 399, 523, -225, -770, 248, -263, 463, -796, 920, 392, -447, 302, -81, 528, -831, 62, 885, 86, -591, -37, -233, -211, -441, 837, 72, -598, 370, 45, -481, 671, 651, 781, -823, -731, 754, -199, -540, -639, -364, -318, 723, 485, 423, -650, -648, -909, 197, -795, 824, 336, 546, 837, 201, -398, -653, 219, -537, 809, -402, -652, -289, -437, 160, 122, -485, -203, -50, 731, -353, 805, -87, 878, -517, };
+int32_t mlp_head_linear_bias[16] = {-54, 918, 756, -770, 1018, -2, -846, 44, 784, -104, -384, -203, 212, -628, -94, -97, };
+
+// Total 14512 parameters
\ No newline at end of file
diff --git a/sw/applications/trans_versasense/data_cpp/signal.cpp b/sw/applications/trans_versasense/data_cpp/signal.cpp
new file mode 100644
index 00000000..0f18a419
--- /dev/null
+++ b/sw/applications/trans_versasense/data_cpp/signal.cpp
@@ -0,0 +1,5 @@
+#include "stdint-gcc.h"
+//int32_t STFT_out[48000] ={15022, 16390, 15545, 7388, 9791, 14435, 15910, 14934, 8889, 9029, 12589, 14368, 13003, 9548, 6344, 9857, 11479, 9461, 8476, -1914, 9560, 7842, 5972, 6077, 3300, 9683, 6443, 5918, 4306, 3938, 8512, 3724, 5741, 5023, 2931, 7275, 3649, 5604, 5232, 3039, 7640, 5448, 5155, 3191, 4248, 7282, 5707, 3886, -1395, 4874, 5392, 5566, 307, 3140, 5102, 5513, 5713, 2597, 3891, 5867, 6802, 5914, 4893, 3388, 6861, 6592, 6289, 5121, 3314, 7333, 4961, 6907, 3998, 3581, 7119, 1288, 7340, 1455, 3347, 6134, -4195, 7221, -649, 2575, 4133, 1906, 6413, 1158, 1360, 639, 3608, 4810, 1664, -862, -2161, 4537, 2477, 1308, -3721, -2389, 5307, 903, -4, -555, -6878, 5826, 1113, -906, 1167, -1543, 5776, 1199, 1884, 1762, 149, 4966, 11, 3047, 1390, -386, 3716, -5616, 2671, -203, 74, 2832, -1861, 1678, -2604, 1596, 1292, 161, 1333, -2384, 1575, -3881, 818, 667, -1833, -390, -1812, 1707, -740, -1805, -3086, -694, 1426, -453, -1980, -790, -124, -648, 361, -3457, 42, 1155, -1014, 791, -13091, -656, 812, 379, 1297, -3332, -2853, -1853, -235, 1618, -420, -3919, -2006, -4401, 1689, 1044, -2273, 275, -565, 1635, 1800, -2376, 792, 2138, 1102, 1969, -2561, 237, 2818, -543, 1624, -310, -1249, 2136, -4400, 904, 920, -3606, 71, -6615, -81, 501, -2837, -1532, -4246, -1490, -2411, -879, -159, -3977, -4394, -7388, -319, -37, -4141, -10580, -1874, -1163, -1711, -3155, -3770, -1572, -3881, -5011, -826, -3183, -2875, -10316, -4701, 956, -4547, -3369, -6280, -4795, 1932, -4555, -2151, -4832, -7088, 2278, -4062, -1050, -4362, -9139, 2188, -5250, -628, -4430, -6307, 1816, -7122, -665, -4281, -3722, 1238, -4499, -856, -3217, -2790, 465, -2960, -1433, -2147, -3077, -434, -3195, -2783, -1981, -2941, -1212, -5049, -5353, -3217, -1690, -1498, -5065, -11050, -3855, -942, -1402, -2999, -6061, -1383, -1013, -1582, -2083, -3332, -275, -1903, -2508, -2036, -2211, -841, -4324, -4298, -2542, -2304, -3922, -6944, -6426, -3393, -3771, -7282, -2375, -9088, -4619, -7090, -2152, -895, -13285, -6205, -9679, -953, -1090, -7111, -6943, -7333, -1160, -2657, -5178, -6399, -4361, -2748, -5439, -4401, -5331, -2684, -7849, -7725, -4121, -4253, -2323, -6348, -6897, -3765, -3744, -2985, -4222, -5344, -3340, -3952, -4292, -6316, -3943, -3635, -5099, -5501, -6581, -3258, -5395, -8104, -6121, -2890, -3694, -8349, -8938, -7267, -2405, -5253, -6570, -6183, -8317, -3901, -6728, -6160, -6023, -6129, -6730, -5623, -7081, -8065, -5117, -7618, -3654, -5993, -12612, -5517, -6372, -2633, -5248, -9541, -6669, -4810, -2844, -6076, -6778, -7488, -5029, -4130, -6289, -5302, -5846, -9132, -5152, -5290, -5980, -4321, -6877, -5027, -5471, -8488, -3290, 10948, 5340, 9881, -583, -1529, 10281, 3184, 9400, 6255, -1363, 7983, 1790, 7839, 8319, -1213, 2985, 5766, 4578, 8716, -1201, 5806, 5972, -7468, 8093, 239, 7278, 3992, 2631, 6914, 2658, 7007, 3013, 4259, 6183, 4335, 5657, 4920, 4879, 6103, 5026, 5172, 5662, 5285, 5893, 4883, 5509, 5524, 5613, 5378, 4402, 4184, 4538, 5872, 4553, 4309, 3084, 2519, 6053, 4412, 4533, 5541, 2182, 5884, 5410, 4304, 6269, 3345, 4957, 5653, 3045, 5565, 3276, 3046, 4418, 1028, 4272, 2407, 595, 1213, 734, 3636, 1612, -1021, -9, 1479, 3416, 1031, -324, 1364, 1998, 3255, 94, 588, 973, 1467, 3470, -317, 408, -256, -1566, 3966, 176, -148, -1555, -5910, 4403, -381, 149, -3399, -1218, 4406, -3162, 1043, -3706, -2034, 3699, -6969, 1255, 13, -2967, 2095, -928, 675, 2541, -309, -742, 1059, -55, 3772, 276, -5152, 1483, -1167, 3918, -918, -2310, 600, -2456, 3234, -4253, -629, -1699, -803, 2143, -8360, -748, -4480, 187, 920, -4510, -2796, -5722, -657, -732, -2852, -6555, -8562, -5101, -1617, -1578, -3238, -2751, -2692, -76, -473, -1770, -1006, 672, 1164, 146, -1307, -1054, 1972, 1728, -76, -1108, -747, 2401, 1777, -1105, -617, 737, 2292, 1237, -496, 491, 1494, 1811, -216, 1202, 1623, 1157, 1162, -1153, 1656, 2217, -332, 552, 898, 776, 2074, -3098, -150, 2083, -258, 1096, -4664, -1276, 2076, 269, -817, -3732, -2660, 1252, 403, -3595, -2332, -3627, 139, -804, -5568, -652, -4610, -491, -4906, -5112, 12, -5653, -40, -5243, -4091, -766, -6220, 444, -1562, -3606, -3645, -7870, -40, -1055, -4503, -10695, -8347, -1875, -1973, -6634, -7025, -5321, -3534, -3721, -6422, -10405, -3470, -2072, -5833, -8296, -6307, -2409, -1348, -8634, -8763, -3250, -1734, -1712, -13134, -3935, -2113, -1132, -2943, -10088, -2782, -1927, -552, -3587, -7851, -3207, -2420, -210, -2134, -5907, -4824, -3031, -288, -1175, -4432, -6584, -2800, -678, -1292, -3739, -5705, -2132, -1039, -2508, -3901, -3854, -1624, -1437, -5728, -4955, -2528, -1266, -2274, -7524, -5831, -2232, -1272, -3370, -2624, -5012, -3195, -2200, -3783, -947, -4277, -4836, -4802, -3420, -488, -3943, -4317, -5543, -2886, -691, -4040, -4122, -3597, -2892, -1142, -4925, -6452, -3758, -4002, -1519, -5252, -10060, -5054, -4808, -1904, -3326, -4930, -4535, -2874, -2275, -1642, -3491, -3392, -1585, -2128, -765, -3125, -2599, -1366, -1867, -687, -3101, -1848, -2227, -2471, -1521, -3092, -1584, -4873, -5110, -4002, -3221, -2450, -8948, -5746, -11796, -3989, -5450, -4673, -2300, -3014, -6275, -6993, -3629, -1265, -1233, -13060, -3994, -3325, -1129, -1401, -6473, -2795, -2634, -856, -3122, -4984, -1852, -2143, -668, -4531, -4954, -1543, -2277, -1158, -4444, 8135, 6088, 8626, -4024, 9938, 7329, 6317, 8147, 3034, 9253, 4904, 6099, 7090, 5534, 7062, 4788, 5168, 5821, 5756, 2868, 6323, 4576, 3219, 3312, 1833, 6494, 3735, 3133, -3194, 4473, 5760, 1781, 5247, 3503, 5033, 4322, 154, 5491, 4139, 2895, 2112, -1883, 5106, 3344, 1160, 567, -8604, 5398, 2834, 5248, 2441, -1097, 6168, 3530, 5936, 4900, 904, 6690, 4608, 5104, 6129, 2446, 6590, 5040, 5192, 6005, 3385, 5551, 4266, 6075, 4500, 3096, 3111, 1873, 6379, 1400, 1015, -337, -2432, 6535, -3148, -6312, 1153, -3379, 6387, -4178, -2431, 1960, -3097, 5323, -2846, -282, 1735, -1790, 2714, -1477, 1123, 1114, 483, -5178, -288, 2408, 349, 2279, -962, 828, 2867, -310, 3205, 602, 1651, 2089, 248, 3324, 1195, 1919, -836, 1723, 2724, 2721, 1435, -8160, 2498, 1506, 3795, -83, -1480, 2126, 141, 3702, -2304, -1676, 632, -186, 2139, -1688, -2840, -452, 758, 749, -1085, -1050, 84, 1955, 2587, -1448, -667, 47, 2776, 3314, -1334, -1973, -584, 3074, 2871, -1128, -4037, -927, 2914, 2029, -1831, -4223, -893, 2430, 1750, -3735, -1903, -725, 1721, 2124, -4438, 91, -814, 695, 2326, -1846, 1159, -718, -1112, 1779, -605, 1229, 953, -4285, 161, -1077, 226, 2278, -2549, -3196, -1597, -1233, 2448, -61, -10037, 1326, -207, 1631, 1238, -5459, 2800, 1173, 597, 1719, -2662, 2475, 1064, 234, 1395, -1008, 22, -931, 85, 225, -520, -10125, -1692, -101, -2013, -1056, -3239, -169, -365, -5623, -1918, -2721, -886, -713, -4148, -1070, -4144, -4883, -992, -3366, -504, -5371, -7334, -1451, -4299, -1722, -5860, -5572, -2058, -2407, -3307, -5420, -9669, -1902, -626, -800, -3278, -4000, -1470, -465, 514, -2492, -1965, -1758, -2323, 435, -3628, -1768, -2921, -5922, -956, -9229, -2309, -4942, -927, -4084, -4407, -2502, -9038, 836, -8231, -2095, -2284, -5389, 1066, -5365, -1906, -1985, -2756, 264, -3891, -3017, -2226, -2262, -1447, -4557, -4960, -3502, -3466, -3976, -11280, -5981, -3511, -5119, -4299, -3848, -5230, -2657, -3228, -2919, -1482, -4701, -3847, -1903, -2750, -1004, -4962, -9136, -1535, -4156, -1487, -5918, -5496, -1578, -9790, -2332, -7666, -4300, -1746, -6635, -2932, -11718, -5430, -1928, -3956, -3045, -13570, -7603, -2016, -3785, -2822, -9656, -7021, -2159, -4384, -2470, -5004, -4553, -2859, -3625, -2045, -2525, -3046, -5049, -2807, -1748, -1425, -2589, -10651, -3267, -2273, -1223, -2394, -5327, -4768, -4832, -1712, -1883, -4089, -3759, -6611, -2592, -1631, -4451, -2098, -3778, -2317, -1688, -4707, -1511, -4370, -1104, -1674, -5347, -1880, -7616, -511, -1990, -8962, -3392, -5659, -637, -3117, -7329, -6851, -5500, -1134, -4374, -4297, -12628, -9453, -1507, -3914, -3602, -7923, -7498, -4224, -5554, -4353, -4133, -2129, -3878, -7270, -2473, -2452, -1737, -3507, -7586, -2008, -2512, -2831, -2846, -5254, -3025, -3418, -5986, -2821, -3714, -5611, -3744, -7985, -2808, -3010, -13840, -2935, -6763, -2277, -2991, -6283, -2459, -7017, -2183, -3789, -3468, -3366, -5831, -3055, -6182, -2980, -5755, -4109, -5251, -13347, -4226, -3284, -3689, -9905, -6728, -7062, -1040, -4341, -6515, -5290, -10547, -88, -4173, -4287, -5037, -9538, 15, -3219, -3665, -4580, -5533, -670, -3366, -3725, -4293, -3755, -2433, -5426, -3616, -4979, -3342, -5897, -10483, -3418, -6809, -4226, -5644, -6907, -3888, -7436, -6950, -4348, -6768, -4698, -5425, -7290, -5661, -11547, -4637, -4024, -4705, -7820, -7789, -5294, -3717, -3606, -4001, -4241, -7811, -4602, -2791, -2423, -2364, -6255, -6510, -1775, -2276, -1164, -5607, -6340, -1017, -3077, -580, -7866, -4238, -901, -4310, -652, -11726, -3115, -1541, -5083, -1309, -10766, -3063, -2977, -5072, -2160, -5334, -3219, -5153, -4673, -2549, -2761, -2681, -5813, -4537, -2539, -1887, -2418, -4519, -5214, -2776, -1955, -2947, -4445, -6446, -3623, -2344, -4213, -5961, -6591, -5118, -2949, -6336, -7215, -6457, -7136, -4560, -9194, -6317, -7439, -9810, -7339, -9647, -7399, -9089, -8084, -5084, -8196, -10603, -8142, -4773, -4006, -6529, -5264, -6082, -3144, -4962, -5245, -3482, -4467, -2991, -7160, -4667, -3534, -3485, -4536, -5624, -4729, -5032, -3222, -8808, -4191, -5173, -6219, -3555, -16024, -4330, -5943, -5030, -4186, -8660, -6684, -6669, -4314, -4229, -3671, -7971, -6376, -4176, -3187, -1670, -3458, -5898, -4030, -2731, -1236, -1895, -5622, -3478, -3836, -1952, -1883, -5111, -2565, -7553, -3555, -3115, -4399, -1740, -7056, -5274, -5062, -4108, -1482, -5186, -5586, -5718, -5093, -2065, -5623, -4664, -4970, -9301, -3493, -7925, -3350, -3927, -8207, -4928, -13647, -2286, -3205, -5647, -5288, -11389, -1695, -3351, -5048, -5436, -10277, -1476, -4273, -3759, -5299, -11084, -1462, -3966, -2469, -4478, -12156, -1510, -2701, -2149, -3377, -9283, -1412, -2234, -3086, -2832, -6406, -1068, -2636, -6186, -3387, -5200, -747, -3812, -10087, -5553, -4196, -911, -5894, -5260, -12137, -2698, -2137, -8129, -4371, -9214, -1973, -5654, -7221, -4905, -7118, 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+//int32_t encoder_out[1936] ={-3006, -13563, -12330, 18429, -5740, 7757, -11785, 19611, 5385, -14561, -4444, -13231, -273, -10749, 1769, 14144, 6853, -7264, -3989, 9728, 6174, 14216, -13342, 20866, 8739, -9327, -15258, -12849, 11503, -16206, 6678, 4712, -3368, -10248, -323, 17739, 14650, 9631, -22149, 18791, 8398, -12585, -14408, -19795, 9133, 7335, -2016, 218, 3745, -8689, -3055, 8517, 19150, 15896, -17422, 15479, 8259, -11139, -19673, -16118, 13716, -2489, 4658, 10756, -8425, -1803, -6892, 18482, -7281, 2743, -5683, 20533, 17587, -5318, -5861, -19906, 5187, -1484, 11114, 7230, 228, -6363, -6655, 9139, 10365, 14506, -7711, 16482, 16422, -16187, -11228, -14695, 18943, -13552, 882, 2345, -11537, -6686, -11743, 7935, 7791, 17995, -10134, 17477, 20963, -15352, 3390, -7308, 7919, -5904, 5447, -2132, -1507, -5768, -3574, 4260, 2652, 4375, -17098, 18282, 7600, -16904, -13845, -10678, 3984, 7624, 6440, 18787, -4814, -13887, -3132, 16328, 2480, 14219, -15608, 12369, 9305, -6755, -9780, -9805, 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+int32_t prototypes[32] ={-1394, -5770, -6778, 762, 4001, -653, -5906, -20, 1220, 3795, -73, -3028, 635, -448, 7677, -6204, 5745, 3112, 1206, -1120, -3618, 1076, -649, 943, -3896, 2462, 4658, 2494, 3996, 1220, -1144, -1013, };
diff --git a/sw/applications/trans_versasense/data_cpp/signal_fft.cpp b/sw/applications/trans_versasense/data_cpp/signal_fft.cpp
new file mode 100644
index 00000000..0a6d510e
--- /dev/null
+++ b/sw/applications/trans_versasense/data_cpp/signal_fft.cpp
@@ -0,0 +1,5 @@
+#include "stdint-gcc.h"
+//int16_t raw_signal[63840] ={0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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+int16_t hanning[256] ={0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 13, 13, 14, 14, 14, 15, 15, 16, 16, 16, 17, 17, 17, 18, 18, 19, 19, 19, 20, 20, 21, 21, 21, 22, 22, 22, 23, 23, 23, 24, 24, 24, 25, 25, 25, 26, 26, 26, 27, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 32, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 28, 28, 28, 28, 27, 27, 27, 27, 26, 26, 26, 25, 25, 25, 24, 24, 24, 23, 23, 23, 22, 22, 22, 21, 21, 21, 20, 20, 19, 19, 19, 18, 18, 17, 17, 17, 16, 16, 16, 15, 15, 14, 14, 14, 13, 13, 12, 12, 12, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+int16_t log_amp[160] ={15022, 14435, 12589, 9857, 9560, 9683, 8512, 7275, 7640, 7282, 5392, 5513, 6802, 6592, 4961, 1288, -4195, 1906, 3608, 4537, 5307, 5826, 5776, 4966, 3716, 2832, 1292, -3881, -1812, -694, -124, 1155, 812, -1853, -2006, 275, 792, 237, -1249, -3606, -2837, -879, -319, -1163, -3881, -10316, -6280, -4832, -4362, -4430, -4281, -3217, -2147, -1981, -3217, -3855, -1383, -275, -841, -3922, -7282, -2152, -953, -1160, -2748, -7849, -6348, -4222, -6316, -6581, -2890, -2405, -3901, -6730, -7618, -6372, -4810, -5029, -9132, -6877, -4224, -3878, -3507, -2846, -2821, -2808, -2277, -2183, -3055, -5251, -9905, -6515, -4287, -3665, -3725, -3616, -3418, -3888, -4698, -4637, -5294, -7811, -6255, -5607, -7866, -11726, -10766, -5334, -2761, -1887, -1955, -2344, -2949, -4560, -7339, -5084, -4006, -4962, -7160, -5624, -4191, -4330, -6684, -7971, -3458, -1895, -1883, -3115, -5062, -5718, -4970, -3927, -3205, -3351, -4273, -3966, -2701, -2234, -2636, -3812, -5894, -8129, -7221, -6359, -5904, -5657, -6363, -8413, -8140, -6600, -6901, -10634, -9912, -6228, -5566, -6416, -8138, -8799, -7865, -7102, };
+//int16_t STFT_rearranged[48000] ={15022, 16390, 15545, 7388, 9791, 14435, 15910, 14934, 8889, 9029, 12589, 14368, 13003, 9548, 6344, 9857, 11479, 9461, 8476, -1914, 9560, 7842, 5972, 6077, 3300, 9683, 6443, 5918, 4306, 3938, 8512, 3724, 5741, 5023, 2931, 7275, 3649, 5604, 5232, 3039, 7640, 5448, 5155, 3191, 4248, 7282, 5707, 3886, -1395, 4874, 5392, 5566, 307, 3140, 5102, 5513, 5713, 2597, 3891, 5867, 6802, 5914, 4893, 3388, 6861, 6592, 6289, 5121, 3314, 7333, 4961, 6907, 3998, 3581, 7119, 1288, 7340, 1455, 3347, 6134, -4195, 7221, -649, 2575, 4133, 1906, 6413, 1158, 1360, 639, 3608, 4810, 1664, -862, -2161, 4537, 2477, 1308, -3721, -2389, 5307, 903, -4, -555, -6878, 5826, 1113, -906, 1167, -1543, 5776, 1199, 1884, 1762, 149, 4966, 11, 3047, 1390, -386, 3716, -5616, 2671, -203, 74, 2832, -1861, 1678, -2604, 1596, 1292, 161, 1333, -2384, 1575, -3881, 818, 667, -1833, -390, -1812, 1707, -740, -1805, -3086, -694, 1426, -453, -1980, -790, -124, -648, 361, -3457, 42, 1155, -1014, 791, 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diff --git a/sw/applications/trans_versasense/dense_layerC.c b/sw/applications/trans_versasense/dense_layerC.c
new file mode 100644
index 00000000..37d06f02
--- /dev/null
+++ b/sw/applications/trans_versasense/dense_layerC.c
@@ -0,0 +1,73 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "dense_layerC.h"
+#include <stdio.h>
+
+void createDense(Dense* dense, size_t input_dim, size_t output_dim, quant_bit_width *weight, quant_bit_width* bias) {
+    dense->input_size_ = input_dim;
+    dense->output_size_ = output_dim;
+    dense->weight = weight;
+    dense->bias = bias;
+}
+
+void destroyDense(Dense* dense) {
+    // Free the memory allocated for the Dense struct
+    free(dense);
+}
+
+void multiplyweight(Dense* dense, size_t seq_len, int32_t* input, int32_t* output) {
+    for (int length = 0; length < seq_len; length++) {
+        for (int out_idx = 0; out_idx < dense->output_size_; out_idx++) {
+            int32_t* weight_ptr = dense->weight + out_idx;
+            int32_t* output_ptr = output + (length * dense->output_size_) + out_idx;
+            int32_t* input_ptr = input + (length * dense->input_size_);
+            int32_t sum = 0;
+            for (int i = 0; i < dense->input_size_; i++) {
+                sum += MUL_HQ(*weight_ptr, *input_ptr); // MUL_HQ macro
+                input_ptr++;
+                weight_ptr += dense->output_size_;
+            }
+            *(output_ptr) = (int32_t) (sum >> NUM_FRACTION_BITS); // NUM_FRACTION_BITS macro
+        }
+    }
+}
+
+void addbias(Dense* dense, size_t seq_len, int32_t* output) {
+    for (size_t idx = 0; idx < seq_len; idx++) {
+        for (size_t feature_idx = 0; feature_idx < dense->output_size_; feature_idx++) {
+            output[idx * dense->output_size_ + feature_idx] += dense->bias[feature_idx];
+        }
+    }
+}
+
+void computeDenseOneRow(Dense* dense, size_t seq_len, int32_t* input, int32_t* output){ // 1x16x16
+    multiplyweight(dense, seq_len, input, output);
+}
+
+void computeDense(Dense* dense, size_t seq_len, int32_t* input, int32_t* output) {
+    //multiplyweight(dense, seq_len, input, output);
+    //printf("\rMul %dx%dx%d\n", seq_len, dense->input_size_, dense->output_size_);
+    multiply_cgra(input, seq_len, dense->input_size_, dense->weight, dense->output_size_, output);
+    if (dense->bias != NULL) {
+        addbias(dense, seq_len, output);
+    }
+}
+
+void activation(Dense* dense, size_t length, int32_t* input, int32_t* output) {
+    float in_float, in_tanh;
+    int32_t x3, in_tanh_fxp;
+    for (int i = 0; i < length; i++) {
+        x3 = MUL(MUL(input[i], input[i]), input[i]);
+        x3 = MUL(x3, 183); // 183 = 0.044715 in fixed-point 12 bit
+        x3 += input[i];
+        x3 = MUL(x3, 3268); // 3268 = sqrt(2/PI) in fixed-point 12 bit
+        in_float = (float) x3 / (float) (1 << NUM_FRACTION_BITS);
+        in_tanh = tanhf(in_float);
+        in_tanh_fxp = (int32_t) (in_tanh * (1 << NUM_FRACTION_BITS));
+        in_tanh_fxp += (1 << NUM_FRACTION_BITS);
+        output[i] = MUL(in_tanh_fxp, input[i] >> 1);
+    }
+}
+
diff --git a/sw/applications/trans_versasense/dense_layerC.h b/sw/applications/trans_versasense/dense_layerC.h
new file mode 100644
index 00000000..e0438f8d
--- /dev/null
+++ b/sw/applications/trans_versasense/dense_layerC.h
@@ -0,0 +1,31 @@
+//
+// Created by alireza on 10/5/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_DENSE_LAYERC_H
+#define FVLLMONTITRANSFORMER_DENSE_LAYERC_H
+
+
+#include <stdlib.h>
+#include <stddef.h>
+#include <math.h>
+#include "param.h"
+#include "cgra.h"
+
+// Define the struct
+typedef struct {
+    size_t input_size_;
+    size_t output_size_;
+    int32_t* weight; // quant_bit_width is a typedef for int32_t
+    int32_t* bias; // quant_bit_width is a typedef for int32_t
+} Dense;
+
+void createDense(Dense* dense, size_t input_dim, size_t output_dim, quant_bit_width *weight, quant_bit_width* bias);
+void destroyDense(Dense* dense);
+void multiplyweight(Dense* dense, size_t seq_len, int32_t* input, int32_t* output);
+void addbias(Dense* dense, size_t seq_len, int32_t* output);
+void computeDense(Dense* dense, size_t seq_len, int32_t* input, int32_t* output);
+void computeDenseOneRow(Dense* dense, size_t seq_len, int32_t* input, int32_t* output);
+void activation(Dense* dense, size_t length, int32_t* input, int32_t* output);
+
+#endif //FVLLMONTITRANSFORMER_DENSE_LAYERC_H
diff --git a/sw/applications/trans_versasense/main.c b/sw/applications/trans_versasense/main.c
new file mode 100644
index 00000000..6a26f77e
--- /dev/null
+++ b/sw/applications/trans_versasense/main.c
@@ -0,0 +1,143 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include <stdio.h>
+#include <math.h>
+#include "main.h"
+//#include "data_cpp/signal.cpp"
+//#include "data_cpp/signal_fft.cpp"
+#include "SYLT-FFT/fft.h"
+#include "weightsAndBiasesC.h"
+#include "transformerBlockC.h"
+
+// For the cgra
+#include "multiply_cgra.h"
+
+// FFT
+//#include "stftVec.h"
+#include "data_cpp/array_output.h"
+
+
+float error_check(const quant_bit_width* groundTruth, const quant_bit_width* output, size_t length){
+    long error = 0;
+    for (int i=0; i<length; i++){
+        error += MUL_HQ(groundTruth[i] - output[i], groundTruth[i] - output[i]);
+    }
+    error = (error >> NUM_FRACTION_BITS);
+    return (float) error/ (float) length;
+}
+
+void prototype_distances(quant_bit_width* prototypeVec, const quant_bit_width* modelOutput, int32_t* distVec, size_t prototypeLength, int prototypeNums){
+    for (int p=0; p< prototypeNums; p++){
+        long dist = 0;
+        quant_bit_width * prototypePtr = prototypeVec + (p * prototypeLength);
+        for (int i=0; i<prototypeLength; i++){
+            dist += MUL_HQ(prototypePtr[i] - modelOutput[i], prototypePtr[i] - modelOutput[i]);
+        }
+        dist = (dist >> NUM_FRACTION_BITS);
+        distVec[p] = (int32_t) dist;
+    }
+}
+
+void transformerInference(quant_bit_width * transformerInput, quant_bit_width * transformerOutput, quant_bit_width* input_normalized, quant_bit_width* qkv, quant_bit_width* intermediate, quant_bit_width * aux_padding,  void* kperf){
+    quant_bit_width * weightVec[NUM_LAYERS*(3*NUM_HEAD+5)+5];
+    quant_bit_width * biasVec[NUM_LAYERS*(3*NUM_HEAD+5)+5];
+    getWeights(weightVec);
+    getBiases(biasVec);
+    quant_bit_width * clsTokenVector = getClassToken();
+    quant_bit_width * posMatrix = getPosEmbedding();
+    TransformerBlock* selfatten = createTransformerBlock(D_SEQ, D_MODEL, D_Q, NUM_HEAD, D_FF, weightVec, biasVec, clsTokenVector, posMatrix);
+    computeFixedPoint(selfatten, D_SEQ, transformerInput, input_normalized, transformerOutput, intermediate, qkv, aux_padding, kperf);
+}
+
+quant_bit_width compute_log_amp(int32_t real, int32_t imag){
+    real = MUL_HQ(real, 25) >> (NUM_FRACTION_BITS - 9);
+    imag = MUL_HQ(imag, 25) >> (NUM_FRACTION_BITS - 9);
+    int32_t real2 = MUL_LONG(real, real) >> NUM_FRACTION_BITS;
+    int32_t imag2 = MUL_LONG(imag, imag) >> NUM_FRACTION_BITS;
+    float pow2 = (float)(real2 + imag2) / (float) (1<< NUM_FRACTION_BITS);
+    float amp = sqrtf(pow2);
+    float stft = logf(amp+ 1e-10f);
+    quant_bit_width stft_int = (quant_bit_width) (stft * (1<<NUM_FRACTION_BITS));
+    return stft_int;
+}
+
+/*
+void initialize_stft(fft_complex_t* data, const quant_bit_width * raw_input_signal){
+    // Initialize each element of the data array
+    for (int i = 0; i < 256; i++) {
+        data[i].r = (MUL_HQ(raw_input_signal[i], hanning[i])) ;
+        data[i].i = 0;
+    }
+    for (int i = 256; i < 512; i++) {
+        data[i].r = 0;
+        data[i].i = 0;
+    }
+}
+*/
+
+/*
+void stft_rearrange(quant_bit_width* rawInputSignal, quant_bit_width* stftVec, size_t patchHeight, size_t patchWidth){
+    fft_complex_t data[512];
+    int overlap = 64;
+    for (int ch=0; ch<20; ch++){
+        for (int time_step=0; time_step<15; time_step++){
+            quant_bit_width* rawSignalPtr = rawInputSignal + ch * 3072 + (256 - overlap) * time_step;
+            initialize_stft(data, rawSignalPtr);
+            fft_fft(data, 9);
+            quant_bit_width * stftVecPtr = stftVec + ch * 15 * 160 + (time_step / patchWidth) * patchWidth * patchHeight + (time_step % patchWidth);
+            for (int index =0 ; index < patchHeight; index++){
+                int16_t stft_int = compute_log_amp(data[index].r, data[index].i);
+                *stftVecPtr = (int32_t) stft_int;
+                stftVecPtr += patchWidth;
+            }
+            stftVecPtr += patchHeight * patchWidth * 2;
+            for (int index = patchHeight ; index < 2*patchHeight; index++){
+                int16_t stft_int = compute_log_amp(data[index].r, data[index].i);
+                *stftVecPtr = (int32_t) stft_int;
+                stftVecPtr += patchWidth;
+            }
+        }
+    }
+}
+*/
+
+
+int main() {
+    //CGRA
+    kcom_perf_t kperf;
+    timerInit(); // Init timer
+    initCGRA(); // Initialize the CGRA
+    countersInit(); // Enable and reset the CGRA performance counters
+
+    // Transformer   
+    // Every buffer is 16x16 = 256
+    quant_bit_width* input = STFT_rand_out; // 1st
+    quant_bit_width* output = STFT_rand_out + 4800; // Last
+
+    quant_bit_width* input_normalized = input + 256; // 2nd
+    quant_bit_width* qkv = input_normalized + 256; 
+    quant_bit_width* intermediate = qkv + 256*4; // 4 = K, V, Q and Kt
+    quant_bit_width* aux_padding = intermediate + 256;
+    
+    int32_t distances[2];
+    //stft_rearrange(rawInputSignal, stftVec, 80, 5);
+        
+    kcom_perfRecordStart(&(kperf.time.infer));
+    transformerInference(input, output, input_normalized, qkv, intermediate, aux_padding, (void *) &kperf);
+    kcom_perfRecordStop(&(kperf.time.infer));
+
+    printf("\rCycles: %d\n", kperf.time.infer.spent_cy);
+    
+    prototype_distances(prototypes, output, distances, D_MODEL, 2);
+    
+    printf("\rDistances:\n");
+    for (int i = 0; i< 2; i++)
+        printf("Class %d = %d\n", i, distances[i]);
+    
+    //printf("\rEND\n");
+    return 0;
+}
+
+
diff --git a/sw/applications/trans_versasense/main.h b/sw/applications/trans_versasense/main.h
new file mode 100644
index 00000000..d2df59cc
--- /dev/null
+++ b/sw/applications/trans_versasense/main.h
@@ -0,0 +1,17 @@
+//
+// Created by alireza on 10/25/21.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TRANSFORMER_H
+#define FVLLMONTITRANSFORMER_TRANSFORMER_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include "param.h"
+
+float error_check(const quant_bit_width* groundTruth, const quant_bit_width* output, size_t length);
+void prototype_distances(quant_bit_width* prototypeVec, const quant_bit_width* modelOutput, int32_t* distVec, size_t prototypeLength, int prototypeNums);
+void transformerInference(quant_bit_width * transformerInput, quant_bit_width * transformerOutput, quant_bit_width* input_normalized, quant_bit_width* qkv, quant_bit_width* intermediate, quant_bit_width* aux_padding, void * kperf);
+quant_bit_width compute_log_amp(int32_t real, int32_t imag);
+
+#endif //FVLLMONTITRANSFORMER_TRANSFORMER_H
diff --git a/sw/applications/trans_versasense/matMulC.c b/sw/applications/trans_versasense/matMulC.c
new file mode 100644
index 00000000..0212afe3
--- /dev/null
+++ b/sw/applications/trans_versasense/matMulC.c
@@ -0,0 +1,22 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "matMulC.h"
+#include <stdio.h>
+
+
+void MatMul_multiply(size_t seq_len, quant_bit_width* input, quant_bit_width* weight,
+                           quant_bit_width* output, size_t input_size, size_t output_size) {
+    //printf("\rMul %dx%dx%d\n", seq_len, input_size, output_size);
+    multiply_cgra(input, seq_len, input_size, weight, output_size, output);
+}
+
+void MatMul_scale(quant_bit_width* input, int shift_scale, size_t mat_size) {
+
+    for (size_t i = 0; i < mat_size; i++) {
+        *input = (*input) >> shift_scale;
+        input++;
+    }
+}
+
diff --git a/sw/applications/trans_versasense/matMulC.h b/sw/applications/trans_versasense/matMulC.h
new file mode 100644
index 00000000..9844b787
--- /dev/null
+++ b/sw/applications/trans_versasense/matMulC.h
@@ -0,0 +1,21 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_MATMULC_H
+#define FVLLMONTITRANSFORMER_MATMULC_H
+
+
+#include <stddef.h>
+#include "param.h"
+#include "cgra.h"
+
+#define BLOCK_SIZE 4
+
+typedef struct {
+} MatMul;
+
+void MatMul_multiply(size_t seq_len, quant_bit_width* input, quant_bit_width* weight, quant_bit_width* output, size_t input_size, size_t output_size);
+void MatMul_scale(quant_bit_width* input, int shift_scale, size_t mat_size);
+
+#endif //FVLLMONTITRANSFORMER_MATMULC_H
diff --git a/sw/applications/trans_versasense/multiply_cgra.c b/sw/applications/trans_versasense/multiply_cgra.c
new file mode 100644
index 00000000..1222d3f2
--- /dev/null
+++ b/sw/applications/trans_versasense/multiply_cgra.c
@@ -0,0 +1,178 @@
+/*
+                              *******************
+******************************* C SOURCE FILE *******************************
+**                            *******************                          **
+**                                                                         **
+** project  : HEEPsilon                                                    **
+** filename : main.c                                                       **
+** version  : 1                                                            **
+** date     : 01/10/23                                                     **
+**                                                                         **
+*****************************************************************************
+**                                                                         **
+** Copyright (c) EPFL                                                      **
+** All rights reserved.                                                    **
+**                                                                         **
+*****************************************************************************
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+
+/**
+* @file   main.c
+* @date   01/10/23
+* @brief  An application to run a matrix multiplication.
+*
+*/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                             MODULES USED                                 */
+/**                                                                        **/
+/****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include "cgra_x_heep.h"
+#include "cgra_bitstream.h"
+#include "multiply_cgra.h"
+
+// For interrupt handling
+#include "csr.h"
+#include "handler.h"
+#include "rv_plic.h"
+#include "rv_plic_regs.h"
+#include "hart.h"
+#include "cgra.h"
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                        DEFINITIONS AND MACROS                            */
+/**                                                                        **/
+/****************************************************************************/
+
+// Size of the input buffer for the CGRA
+#define CGRA_COL_INPUT_SIZE 4
+
+/****************************************************************************/
+/**                                                                        **/
+/*                      PROTOTYPES OF LOCAL FUNCTIONS                       */
+/**                                                                        **/
+/****************************************************************************/
+
+
+// Handler for the CGRA interruption
+void handler_irq_cgra(uint32_t id);
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            GLOBAL VARIABLES                              */
+/**                                                                        **/
+/****************************************************************************/
+
+// Plic controller variables
+volatile bool               cgra_intr_flag;
+
+// CGRA variables
+static cgra_t               cgra;
+static uint8_t              cgra_slot;
+
+// CGRA input and output buffers
+static int32_t cgra_input[CGRA_N_COLS][CGRA_COL_INPUT_SIZE]    __attribute__ ((aligned (4)));
+
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            LOCAL FUNCTIONS                               */
+/**                                                                        **/
+/****************************************************************************/
+
+// Output needs to be multiple of 4 by 4, ex 12x16
+void multiply_cgra(int * matrixA, int ROWS_A, int COLS_A, int * matrixB, int COLS_B, int * matrixC)
+{
+  int ROWS_B = COLS_A;
+  int ROWS_C = ROWS_A;
+  int COLS_C = COLS_B;
+  // Prepare the input vector for the CGRA
+  // Col 0: &B[0][0], nItLoopColsC, &A[0][0], &C[0][3]
+  cgra_input[0][0] = &matrixB[0];
+  cgra_input[0][1] = COLS_C/CGRA_N_ROWS;
+  cgra_input[0][2] = &matrixA[0];
+  cgra_input[0][3] = &matrixC[3];
+  // Col 1: &C[1][0], &B[0][1], nItLoopsColsA, &A[1][0]
+  cgra_input[1][0] = &matrixC[COLS_C];
+  cgra_input[1][1] = &matrixB[1];
+  cgra_input[1][2] = COLS_A;
+  cgra_input[1][3] = &matrixA[COLS_A];
+  // Col 2: &A[2][0], &C[2][1], &B[0][2], nItLoopColsC
+  cgra_input[2][0] = &matrixA[2*COLS_A];
+  cgra_input[2][1] = &matrixC[2*COLS_C+1];
+  cgra_input[2][2] = &matrixB[2];
+  cgra_input[2][3] = COLS_C/CGRA_N_ROWS;
+  // Col 3: nItLoopRowsC, &A[3][0], &C[3][2], &B[0][3], 
+  cgra_input[3][0] = ROWS_C/CGRA_N_COLS;
+  cgra_input[3][1] = &matrixA[3*COLS_A];
+  cgra_input[3][2] = &matrixC[3*COLS_C+2];
+  cgra_input[3][3] = &matrixB[3];
+
+  // Set CGRA kernel L/S pointers
+  for(int col_idx = 0 ; col_idx < CGRA_N_COLS ; col_idx++){
+    cgra_set_read_ptr ( &cgra, cgra_slot, (uint32_t) cgra_input[col_idx], col_idx );
+  }
+
+  // CGRA Execution
+  cgra_intr_flag = 0;
+  cgra_set_kernel( &cgra, cgra_slot, 1 );
+  // Wait until CGRA is done
+  while(cgra_intr_flag==0) {
+    wait_for_interrupt();
+  }
+}
+
+// Initialize the CGRA
+void initCGRA(){
+  // Init the PLIC
+  plic_Init();
+  plic_irq_set_priority(CGRA_INTR, 1);
+  plic_irq_set_enabled(CGRA_INTR, kPlicToggleEnabled);
+  plic_assign_external_irq_handler( CGRA_INTR, (void *) &handler_irq_cgra);
+
+  // Enable interrupt on processor side
+  // Enable global interrupt for machine-level interrupts
+  CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+  // Set mie.MEIE bit to one to enable machine-level external interrupts
+  const uint32_t mask = 1 << 11;//IRQ_EXT_ENABLE_OFFSET;
+  CSR_SET_BITS(CSR_REG_MIE, mask);
+  cgra_intr_flag = 0;
+
+  // Load kernel
+  cgra_cmem_init(cgra_imem_bitstream, cgra_kmem_bitstream);
+
+  cgra.base_addr = mmio_region_from_addr((uintptr_t)CGRA_PERIPH_START_ADDRESS);
+  // Select request slot of CGRA
+  cgra_slot = cgra_get_slot(&cgra);
+}
+
+// Interrupt controller variables
+void handler_irq_cgra(uint32_t id) {
+  cgra_intr_flag = 1;
+}
+
+void countersInit(){
+  // Enable and reset the CGRA performance counters
+  cgra_perf_cnt_enable(&cgra, 1);
+  cgra_perf_cnt_reset( &cgra );
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/*                                 EOF                                      */
+/**                                                                        **/
+/****************************************************************************/
diff --git a/sw/applications/trans_versasense/multiply_cgra.h b/sw/applications/trans_versasense/multiply_cgra.h
new file mode 100644
index 00000000..d43ba4fd
--- /dev/null
+++ b/sw/applications/trans_versasense/multiply_cgra.h
@@ -0,0 +1,6 @@
+#include "performance.h"
+
+// Multiply the matrix in the cgra
+void multiply_cgra(int * matrixA, int rowsA, int colsA, int * matrixB, int colsB, int * matrixC);
+void countersInit();
+void initCGRA();
\ No newline at end of file
diff --git a/sw/applications/trans_versasense/param.h b/sw/applications/trans_versasense/param.h
new file mode 100644
index 00000000..a48ed700
--- /dev/null
+++ b/sw/applications/trans_versasense/param.h
@@ -0,0 +1,26 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_PARAM_H
+#define FVLLMONTITRANSFORMER_PARAM_H
+#include "stdint.h"
+
+#define D_Q 4
+#define D_SEQ 12
+#define D_MODEL 16
+#define NUM_HEAD 4
+#define NUM_LAYERS 4
+#define D_FF 4
+#define D_EMBEDDING 400
+
+
+#define NUM_FRACTION_BITS 12
+#define MUL(x, y) (int32_t) (((int32_t)(x) * (int32_t)(y)) >> NUM_FRACTION_BITS)
+#define MUL_LONG(x, y) (int64_t) (((int64_t)(x) * (int64_t)(y)))
+#define MUL_HQ(x, y) (int32_t) (((int32_t)(x) * (int32_t)(y)))
+#define SHIFT(x) ((x) >> NUM_FRACTION_BITS)
+
+
+typedef int32_t quant_bit_width;
+#endif //FVLLMONTITRANSFORMER_PARAM_H
diff --git a/sw/applications/trans_versasense/performance.c b/sw/applications/trans_versasense/performance.c
new file mode 100644
index 00000000..421d39be
--- /dev/null
+++ b/sw/applications/trans_versasense/performance.c
@@ -0,0 +1,62 @@
+#include "performance.h"
+
+// For the timer
+#include "rv_timer.h"
+#include "soc_ctrl.h"
+#include "core_v_mini_mcu.h"
+
+// Timer
+static rv_timer_t          timer;
+
+void kcom_perfRecordStart( kcom_time_diff_t *perf )
+{
+    timeStart( perf );
+}
+
+void kcom_perfRecordStop( kcom_time_diff_t *perf )
+{
+    timeStop( perf );
+}
+
+void timeStart( kcom_time_diff_t *perf )
+{
+    perf->start_cy = getTime_cy();
+}
+
+void timeStop( kcom_time_diff_t *perf )
+{
+    perf->end_cy = getTime_cy();
+    perf->spent_cy += perf->end_cy - perf->start_cy;
+}
+
+uint64_t getTime_cy( )
+{
+    static uint64_t out;
+    rv_timer_counter_read( &timer, HART_ID, &out );
+    return out;
+}
+
+//Initialize the timer
+void timerInit()
+{
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr  = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz  = soc_ctrl_get_frequency(&soc_ctrl);
+
+    mmio_region_t timer_0_reg = mmio_region_from_addr(RV_TIMER_AO_START_ADDRESS);
+
+    rv_timer_init( timer_0_reg, (rv_timer_config_t) { .hart_count = 2, .comparator_count = 1 }, &timer );
+
+    rv_timer_tick_params_t tick_params;
+
+    // The same frequency is provaided to get one tick per cycle.
+    rv_timer_approximate_tick_params( freq_hz, freq_hz, &tick_params );
+    rv_timer_set_tick_params(&timer, HART_ID, tick_params);
+
+    // Juan: see if i cannot remove this!
+    rv_timer_irq_enable(&timer, HART_ID, 0, kRvTimerEnabled);
+    rv_timer_arm(&timer, HART_ID, 0, 1);
+
+    rv_timer_counter_set_enabled(&timer, HART_ID, kRvTimerEnabled);
+
+}
\ No newline at end of file
diff --git a/sw/applications/trans_versasense/performance.h b/sw/applications/trans_versasense/performance.h
new file mode 100644
index 00000000..9324381e
--- /dev/null
+++ b/sw/applications/trans_versasense/performance.h
@@ -0,0 +1,64 @@
+#include <stdint.h>
+#include "cgra.h"
+
+typedef long int    kcom_time_t;
+typedef kcom_time_t kcom_param_t;
+
+typedef struct kcom_col_perf
+{
+    uint32_t cyc_act;
+    uint32_t cyc_stl;
+} kcom_col_perf_t;
+
+typedef struct kcom_time_diff
+{
+    kcom_time_t start_cy;
+    kcom_time_t end_cy;
+    kcom_time_t spent_cy;
+} kcom_time_diff_t;
+
+typedef struct kcom_timing
+{
+    kcom_time_diff_t    sw;
+    kcom_time_diff_t    cgra;
+    kcom_time_diff_t    load;
+    kcom_time_diff_t    input;
+    kcom_time_diff_t    output;
+    kcom_time_diff_t    reprogramCols;
+    kcom_time_diff_t    bitstream;
+    kcom_time_diff_t    infer;
+    kcom_time_diff_t    proto;
+} kcom_timing_t;
+
+typedef struct kcom_perf
+{
+    kcom_col_perf_t    cols[CGRA_N_COLS];
+    kcom_col_perf_t    cols_max;
+    uint32_t           cyc_ratio; // Stored *CGRA_STAT_PERCENT_MULTIPLIER
+    kcom_timing_t      time;
+} kcom_perf_t;
+
+typedef struct kcom_run
+{
+    kcom_param_t sw;
+    kcom_param_t conf;
+    kcom_param_t cgra;
+    kcom_param_t repo;
+} kcom_run_t;
+
+typedef struct kcom_stats
+{
+   kcom_run_t   avg;
+   uint32_t     n;
+   uint32_t     errors;
+   uint8_t      *name;
+} kcom_stats_t;
+
+#define HART_ID 0
+
+void timerInit();
+uint64_t getTime_cy( );
+void timeStop( kcom_time_diff_t *perf );
+void timeStart( kcom_time_diff_t *perf );
+void kcom_perfRecordStop( kcom_time_diff_t *perf );
+void kcom_perfRecordStart( kcom_time_diff_t *perf );
\ No newline at end of file
diff --git a/sw/applications/trans_versasense/selfattentionC.c b/sw/applications/trans_versasense/selfattentionC.c
new file mode 100644
index 00000000..7edfff50
--- /dev/null
+++ b/sw/applications/trans_versasense/selfattentionC.c
@@ -0,0 +1,99 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include <stdio.h>
+#include "selfattentionC.h"
+
+
+void create_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn, size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, int32_t** weightVector) {
+    self_attn->pre_seq_len = pre_seq_len;
+    self_attn->head_hidden_size = head_hidden_size;
+    createDense(self_attn->query_layer, input_dim, head_hidden_size, weightVector[0], NULL);
+    createDense(self_attn->key_layer, input_dim, head_hidden_size, weightVector[1], NULL);
+    createDense(self_attn->value_layer, input_dim, head_hidden_size, weightVector[2], NULL);
+}
+
+void destroy_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn) {
+    free(self_attn->query_layer_out);
+    free(self_attn->key_layer_out);
+    free(self_attn->key_transposed_layer_out);
+    free(self_attn->value_layer_out);
+    free(self_attn->attention_scores);
+
+    destroyDense(self_attn->query_layer);
+    destroyDense(self_attn->key_layer);
+    destroyDense(self_attn->value_layer);
+
+    free(self_attn);
+}
+
+void removeExtraCols(int32_t* input, size_t rows, int cols) {
+    int nElems = 3;
+    for(int r = 1; r < rows; r++, nElems+=3){
+        for(int c = 0; c < cols -3; c++){
+            input[r*cols+c -nElems] = input[r*cols+c];
+        }
+    }
+}
+
+void add_padding(int32_t *input, int32_t *output, int rows, int columns, int padding_width) {
+    // Calcular el nuevo ancho de la matriz con el relleno
+    int new_columns = columns + padding_width;
+
+    // Crear una nueva matriz con el nuevo ancho y copiar los elementos de la matriz original
+    for (int i = 0; i < rows; i++) {
+        for (int j = 0; j < columns; j++) {
+            output[i * new_columns + j] = input[i * columns + j];
+        }
+        // Rellenar las nuevas columnas con ceros
+        for (int j = columns; j < new_columns; j++) {
+            output[i * new_columns + j] = 0; // O cualquier otro valor de relleno que desees
+        }
+    }
+}
+
+void remove_padding(int *matrix, int rows, int columns, int padding_width) {
+    // Calculate the new width of the matrix after removing padding
+    int new_columns = columns - padding_width;
+
+    // Shift the elements of each row to remove the padding
+    for (int i = 0; i < rows; i++) {
+        for (int j = 0; j < new_columns; j++) {
+            matrix[i * new_columns + j] = matrix[i * columns + j];
+        }
+    }
+}
+
+
+void compute_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn, int32_t* input, int32_t* output, int32_t* qkv, int32_t* intermediate, int32_t* aux_padding) {
+    self_attn->query_layer_out = qkv;
+    self_attn->key_layer_out = qkv + self_attn->pre_seq_len * self_attn->head_hidden_size;
+    self_attn->value_layer_out = qkv + 2 * self_attn->pre_seq_len * self_attn->head_hidden_size;
+    self_attn->key_transposed_layer_out = qkv + 3 * self_attn->pre_seq_len * self_attn->head_hidden_size;
+
+    // This 3 mmul need to think they have 16 rows instead of 13
+    int padding = 3;
+    // TODO: Check that the outputs have enough space for the extra padding rows and cols
+    computeDense(self_attn->query_layer, self_attn->pre_seq_len + padding, input, self_attn->query_layer_out); // 13x16x4 (16x16x4)
+    computeDense(self_attn->key_layer, self_attn->pre_seq_len + padding, input, self_attn->key_layer_out); // 13x16x4 (16x16x4)
+    computeDense(self_attn->value_layer, self_attn->pre_seq_len + padding, input, self_attn->value_layer_out); // 13x16x4 (16x16x4)
+
+    transpose_quant(self_attn->key_layer_out, self_attn->key_transposed_layer_out, self_attn->pre_seq_len +3, self_attn->head_hidden_size); // 4x13
+    MatMul_scale(self_attn->key_transposed_layer_out, 1, self_attn->pre_seq_len * self_attn->head_hidden_size); //4x13
+
+    // Add padding 4x13 -> 4x16
+    add_padding(self_attn->key_transposed_layer_out, aux_padding, self_attn->pre_seq_len, self_attn->head_hidden_size, padding); // 4x16
+
+    // 13x4x13 (16x4x16)
+    MatMul_multiply(self_attn->pre_seq_len + padding, self_attn->query_layer_out, aux_padding, intermediate, self_attn->head_hidden_size, self_attn->pre_seq_len + padding);
+    
+    // 13x16 -> 13x13
+    remove_padding(intermediate, self_attn->pre_seq_len, self_attn->pre_seq_len, padding);
+
+    //printf("\rSoftmax\n");
+    computeSoftmax(intermediate, self_attn->pre_seq_len);
+    
+    // 13x13x4
+    MatMul_multiply(self_attn->pre_seq_len + padding, intermediate, self_attn->value_layer_out, output, self_attn->pre_seq_len, self_attn->head_hidden_size);
+}
diff --git a/sw/applications/trans_versasense/selfattentionC.h b/sw/applications/trans_versasense/selfattentionC.h
new file mode 100644
index 00000000..9206418b
--- /dev/null
+++ b/sw/applications/trans_versasense/selfattentionC.h
@@ -0,0 +1,35 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_SELFATTENTIONC_H
+#define FVLLMONTITRANSFORMER_SELFATTENTIONC_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "dense_layerC.h"
+#include "softmaxC.h"
+#include "transposeC.h"
+#include "matMulC.h"
+#include "param.h"
+#include "cgra.h"
+
+typedef struct {
+    Dense* query_layer;
+    Dense* key_layer;
+    Dense* value_layer;
+    int32_t* query_layer_out;
+    int32_t* key_layer_out;
+    int32_t* key_transposed_layer_out;
+    int32_t* value_layer_out;
+    int32_t* attention_scores;
+    size_t pre_seq_len;
+    size_t head_hidden_size;
+} SingleHeadSelfAttn;
+
+void create_SingleHeadSelfAttn(SingleHeadSelfAttn*, size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, int32_t** weightVector);
+void destroy_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn);
+void compute_SingleHeadSelfAttn(SingleHeadSelfAttn* self_attn, int32_t* input, int32_t* output, int32_t* qkv, int32_t* intermediate, int32_t* aux_padding);
+
+#endif //FVLLMONTITRANSFORMER_SELFATTENTIONC_H
diff --git a/sw/applications/trans_versasense/softmaxC.c b/sw/applications/trans_versasense/softmaxC.c
new file mode 100644
index 00000000..f9f8bd2b
--- /dev/null
+++ b/sw/applications/trans_versasense/softmaxC.c
@@ -0,0 +1,38 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "softmaxC.h"
+
+
+void computeSoftmax(int32_t* input, size_t seq_len) {
+    size_t width = seq_len;
+    float input_float = 0.0f;
+    for (int i = 0; i < seq_len; i++) {
+        // Look for the biggest value of the row
+        int32_t max_val = input[i * seq_len];
+        for (int j = 1; j < width; j++) { // Assuming its squared (width = seq_len)
+            if (input[i * seq_len + j] > max_val) {
+                max_val = input[i * seq_len + j];
+            }
+        }
+        for (int j = 0; j < width; j++) {
+            input[i * seq_len + j] = (int32_t) fmax(input[i * seq_len + j] - max_val, -32767);
+        }
+        // Sum all values on the row
+        int32_t sum = 0;
+        for (int j = 0; j < width; j++) {
+            input_float = (float) input[i * seq_len + j] / (float) (1 << NUM_FRACTION_BITS);
+            input_float = expf(input_float);
+            input[i * seq_len + j] = (int32_t) (input_float * (1 << NUM_FRACTION_BITS));
+            sum += input[i * seq_len + j];
+        }
+        float sum_float = (float) sum / (float) (1 << NUM_FRACTION_BITS);
+        float sum_inv = (float) (1 / (sum_float + 0.00001)); // prevent zero divide!
+        int32_t sum_inv_int = (int32_t) (sum_inv * (1 << NUM_FRACTION_BITS));
+        for (int j = 0; j < width; j++) {
+            input[i * seq_len + j] = (int32_t) MUL(input[i * seq_len + j], sum_inv_int);
+        }
+    }
+}
+
diff --git a/sw/applications/trans_versasense/softmaxC.h b/sw/applications/trans_versasense/softmaxC.h
new file mode 100644
index 00000000..fa47176f
--- /dev/null
+++ b/sw/applications/trans_versasense/softmaxC.h
@@ -0,0 +1,17 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_SOFTMAXC_H
+#define FVLLMONTITRANSFORMER_SOFTMAXC_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <math.h>
+#include <stdlib.h>
+#include "param.h"
+
+void computeSoftmax(int32_t* input, size_t seq_len);
+
+
+#endif //FVLLMONTITRANSFORMER_SOFTMAXC_H
diff --git a/sw/applications/trans_versasense/stftVec.h b/sw/applications/trans_versasense/stftVec.h
new file mode 100644
index 00000000..62243064
--- /dev/null
+++ b/sw/applications/trans_versasense/stftVec.h
@@ -0,0 +1,3 @@
+#include <stdint.h>
+
+int32_t stftVec[49920] = {14912, 16305, 15424, 7300, 9641, 14329, 15823, 14833, 8710, 8912, 12488, 14281, 12956, 9398, 6336, 9702, 11379, 9458, 8448, -1345, 9383, 7575, 5905, 6193, 3111, 9534, 6388, 5963, 4307, 3857, 8353, 3661, 5646, 4840, 2974, 7109, 3348, 5522, 5048, 3034, 7513, 5345, 5058, 3058, 4169, 7233, 5680, 3618, -1939, 4739, 5392, 5531, 33, 3007, 4967, 5296, 5527, 2470, 3793, 5821, 6674, 5596, 4762, 3355, 6805, 6530, 6062, 5061, 3296, 7232, 4892, 6914, 3984, 3459, 7001, 1128, 7354, 1476, 3216, 6049, -4246, 7120, -809, 2509, 4113, 1815, 6269, 1109, 1261, 649, 3559, 4808, 1742, -1118, -2260, 4541, 2638, 1333, -3683, -2573, 5324, 1096, -41, -624, -6914, 5797, 1474, -749, 1036, -1670, 5676, 1178, 1827, 1675, -136, 4838, -524, 2920, 1334, -531, 3606, -5997, 2613, -295, 48, 2645, -2879, 1699, -2664, 1454, 969, -350, 1126, -2504, 1496, -4513, 428, 343, -2119, -288, -2229, 1388, -1021, -1983, -3119, -993, 1492, -842, -2102, -953, -1, -371, 77, -3653, -82, 1169, -1377, 613, -13738, -824, 674, 323, 1161, -3526, -3042, -2042, -359, 1511, -495, -3982, -2008, -5367, 1620, 1015, -2366, 202, -646, 1594, 1724, -2351, 739, 1997, 1015, 1845, -2589, 177, 2716, -743, 1526, -470, -1415, 2187, -4764, 870, 808, -3751, 227, -6828, -105, 405, -2589, -2027, -4123, -1632, -2546, -762, -542, -3523, -4738, -7353, -263, -416, -3632, -11115, -1954, -1127, -2297, -2954, -4223, -1644, -3840, -5020, -878, -3430, -2904, -10526, -3978, 912, -4403, -3360, -6759, -4464, 1940, -4478, -2115, -5273, -6310, 2291, -4053, -1078, -4874, -7426, 2178, -5158, -729, -4946, -5026, 1817, -7019, -795, -4583, -3242, 1282, -4693, -973, -3386, -2762, 493, -3012, -1475, -2270, -2920, -526, -3119, -2724, -2058, -3040, -1411, -4985, -5214, -3154, -2122, -1653, -5183, -11004, -4021, -1058, -1492, -3140, -6113, -1651, -856, -1647, -2264, -3441, -398, -1874, -2567, -2166, -2328, -798, -4980, -4395, -2596, -2396, -3644, -6692, -6640, -3482, -3798, -7317, -2442, -9695, -4718, -7081, -2114, -1099, -12776, -6194, -10210, -933, -1213, -7281, -6705, -7503, -1230, -2569, -5561, -6399, -4361, -2941, -5049, -4606, -5694, -2735, -8393, -7371, -3951, -4559, -2440, -6246, -6732, -3286, -3792, -3112, -4097, -4957, -3010, -3817, -4315, -5844, -3629, -3569, -5020, -5387, -6388, -2664, -5189, -8333, -6113, -2933, -3172, -7335, -9106, -7623, -2443, -5793, -6899, -6885, -8790, -3850, -8549, -6246, -6705, -6422, -6173, -5584, -6214, -8112, -5561, -6842, -3056, -5853, -11115, -5960, -6204, -2619, -5710, -8982, -6899, -5422, -3612, -6354, -6516, -7562, -5662, -4805, -6666, -5380, -5988, -8942, -4464, -5836, -6103, -4564, -7665, -3820, -5569, -8363, -3404, 10828, 5093, 9764, -637, -1552, 10180, 2996, 9296, 6157, -1414, 7937, 1593, 7768, 8228, -1236, 3042, 5579, 4561, 8634, -1291, 5745, 5866, -6705, 8019, 155, 7198, 3995, 2562, 6854, 2672, 6888, 2944, 4211, 6122, 4286, 5550, 4832, 4819, 6019, 4892, 5059, 5588, 5210, 5793, 4758, 5333, 5427, 5537, 5286, 4384, 4038, 4426, 5806, 4500, 4318, 2973, 2464, 5976, 4362, 4433, 5399, 2003, 5762, 5286, 4124, 6167, 3180, 4809, 5521, 2925, 5501, 3242, 2970, 4332, 1057, 4220, 2436, 677, 1175, 673, 3549, 1524, -996, -167, 1419, 3283, 855, -620, 1349, 1891, 3126, 21, 330, 1025, 1342, 3396, -364, 327, -259, -1672, 3904, 71, -113, -1710, -6133, 4303, -450, 51, -3479, -1414, 4283, -3264, 810, -3551, -2265, 3610, -6553, 1101, -15, -3014, 2068, -975, 654, 2445, -489, -830, 960, -122, 3656, 93, -5306, 1371, -1404, 3822, -1012, -2156, 480, -2754, 3166, -4172, -672, -1771, -874, 2085, -8220, -826, -4369, 125, 855, -4587, -2741, -5810, -768, -817, -3047, -6434, -8304, -5387, -1710, -1638, -3329, -2813, -2703, -143, -570, -1822, -1158, 622, 1100, -62, -1450, -1265, 1921, 1670, -287, -1317, -885, 2352, 1712, -1175, -749, 658, 2223, 1136, -476, 383, 1404, 1729, -347, 1100, 1501, 1061, 1107, -1263, 1494, 2095, -436, 523, 769, 671, 1946, -3210, -247, 1958, -288, 949, -4718, -1497, 1982, 172, -953, -3906, -2817, 1200, 314, -3714, -2514, -3680, 118, -902, -5827, -757, -4795, -515, -4974, -5055, -82, -5592, -101, -5554, -3961, -884, -5933, 355, -1759, -3638, -3811, -7708, -148, -1153, -4611, -11004, -9064, -1975, -2050, -6628, -7066, -5638, -3629, -3916, -6914, -10138, -3680, -2139, -5897, -8982, -6516, -2553, -1392, -8304, -9106, -3362, -1838, -1752, -14784, -4184, -2143, -1250, -3007, -9936, -2855, -1925, -717, -3695, -7644, -3151, -2452, -369, -2181, -5988, -4708, -3049, -406, -1225, -4564, -6602, -2813, -792, -1364, -3741, -5897, -2208, -1155, -2590, -3824, -4028, -1736, -1501, -5768, -5031, -2655, -1393, -2299, -7426, -5979, -2328, -1391, -3447, -2811, -5085, -3314, -2265, -3927, -1129, -4344, -5091, -4821, -3474, -589, -3947, -4532, -5623, -2869, -734, -4086, -4238, -3644, -2960, -1232, -4991, -6388, -3824, -4195, -1711, -5189, -11115, -5121, -4853, -2061, -3415, -5208, -4620, -2935, -2325, -1779, -3653, -3518, -1713, -2205, -884, -3294, -2666, -1488, -1954, -786, -3284, -1922, -2323, -2517, -1617, -3324, -1739, -4929, -5037, -4168, -3501, -2587, -9479, -5646, -10613, -4234, -5299, -4821, -2382, -2999, -6504, -7066, -3704, -1370, -1359, -28777, -4180, -3334, -1195, -1571, -6457, -2863, -2720, -882, -3203, -4974, -1921, -2339, -720, -4649, -4918, -1642, -2490, -1214, -4693, 8017, 5947, 8461, -2751, 9815, 7223, 6127, 8022, 2956, 9154, 4829, 5941, 7036, 5360, 7050, 4691, 5145, 5777, 5602, 3055, 6247, 4556, 3163, 3280, 1784, 6437, 3659, 2851, -3773, 4380, 5688, 1593, 5111, 3385, 4920, 4215, -50, 5408, 4045, 2722, 2053, -1742, 5027, 3237, 1031, 686, -10526, 5369, 2846, 5125, 2484, -1146, 6142, 3540, 5804, 4808, 926, 6608, 4504, 5018, 5994, 2364, 6477, 4881, 5104, 5893, 3248, 5468, 4141, 5982, 4460, 3000, 3115, 1903, 6320, 1467, 1021, -374, -2309, 6455, -3121, -5933, 1092, -3853, 6291, -4226, -2543, 1916, -3034, 5247, -2984, -312, 1637, -1636, 2669, -1564, 1060, 993, 444, -5085, -348, 2313, 309, 2137, -1156, 752, 2779, -235, 3077, 440, 1579, 2012, 269, 3224, 1158, 1843, -941, 1646, 2635, 2681, 1328, -8165, 2411, 1417, 3713, -223, -1668, 2049, 42, 3602, -2294, -1941, 537, -310, 2031, -1652, -2813, -577, 669, 624, -1099, -1117, 2, 1906, 2465, -1414, -852, -10, 2704, 3213, -1290, -2107, -628, 2970, 2815, -1178, -3975, -987, 2822, 2019, -1959, -4119, -1014, 2387, 1699, -3856, -2022, -896, 1673, 1995, -4500, -99, -984, 548, 2192, -1913, 1011, -757, -1355, 1698, -643, 1138, 883, -4408, 100, -1165, 162, 2147, -2661, -3259, -1635, -1216, 2327, -155, -10284, 1244, -206, 1579, 1159, -5793, 2667, 1028, 571, 1620, -2739, 2356, 869, 144, 1279, -1083, 29, -1014, -14, 96, -609, -8754, -1797, -161, -2169, -1144, -3281, -350, -385, -5554, -1973, -2571, -1009, -768, -4274, -1250, -3947, -4929, -1129, -3638, -687, -5509, -7464, -1615, -4331, -1858, -6204, -5584, -2211, -2430, -3557, -5531, -10001, -2042, -703, -856, -3471, -4115, -1611, -507, 467, -2635, -2046, -1894, -2326, 329, -3692, -1847, -2990, -6007, -1055, -9479, -2388, -5020, -991, -3992, -4559, -2541, -9936, 756, -8718, -2172, -2325, -5115, 971, -5266, -1954, -2102, -2722, 152, -3879, -3031, -2394, -2316, -1551, -4837, -4810, -3609, -3436, -3927, -12123, -5960, -3615, -4980, -4319, -4003, -5380, -2853, -3299, -3027, -1630, -4795, -4064, -1941, -2835, -1077, -4963, -9238, -1576, -4226, -1491, -5836, -5735, -1713, -9873, -2353, -7484, -4478, -1912, -6666, -3025, -11629, -5509, -2004, -3923, -3124, -14195, -7503, -2003, -3735, -2847, -9238, -6928, -2170, -4550, -2569, -5020, -4597, -2973, -3876, -2259, -2514, -3147, -5360, -2971, -1992, -1383, -2703, -12319, -3367, -2531, -1215, -2447, -5524, -4674, -5043, -1759, -1943, -4270, -3930, -6719, -2637, -1755, -4555, -2320, -4064, -2416, -1813, -4743, -1622, -4659, -1259, -1760, -5422, -1971, -7774, -641, -2088, -9479, -3574, -5638, -733, -3194, -6943, -7034, -5465, -1246, -4307, -4230, -12319, -8942, -1642, -3947, -3735, -8220, -7464, -4545, -4420, -4100, -4527, -2182, -4157, -5654, -1990, -2831, -1894, -4089, -5888, -1433, -2648, -3083, -3365, -4659, -2673, -3172, -6225, -3215, -3261, -5988, -3647, -8333, -3191, -2580, -17034, -2939, -6928, -2590, -2912, -6553, -2438, -6759, -2232, -4230, -3594, -3465, -5718, -2718, -5988, -3135, -5599, -4219, -4365, -10069, -4274, -3331, -3748, -9022, -6842, -6225, -1217, -4238, -7408, -4980, -8304, -146, -4067, -4145, -5906, -8683, 89, -3286, -3362, -5638, -5031, -634, -3577, -3580, -4491, -3430, -2642, -5726, -3621, -6173, -3378, -6246, -11356, -3455, -7445, -4523, -5793, -7644, -3968, -5710, -6640, -4858, -7066, -4805, -5429, -7004, -5906, -10899, -4968, -3444, -4923, -7752, -8165, -5576, -3114, -3680, -4319, -4242, -7464, -4991, -2851, -2485, -2437, -6615, -8165, -1779, -2273, -1313, -5662, -7523, -1053, -3326, -705, -6870, -4858, -1173, -4831, -749, -9064, -3311, -2031, -5415, -1427, -10069, -2891, -3342, -4951, -2348, -6103, -2977, -4957, -4532, -2809, -3076, -2952, -5444, -4826, -2731, -1731, -2861, -4093, -5810, -2825, -1404, -2952, -3801, -6492, -3680, -1752, -3650, -5759, -6553, -5444, -2937, -5726, -8942, -6958, -7623, -5638, -10526, -5906, -7865, -9429, -6828, -12534, -6434, -8903, -8086, -4597, -10442, -11004, -8363, -4935, -4299, -7687, -5554, -6516, -3232, -5743, -5374, -3609, -4754, -3067, -8276, -4270, -3554, -3560, -4713, -6045, -4278, -4847, -3149, -8942, -4550, -4946, -6354, -3537, -14784, -4759, -5970, -5202, -4319, -8549, -6759, -7050, -4035, -4390, -3710, -6885, -6540, -3653, -3415, -1844, -3763, -5531, -3883, -2969, -1482, -2312, -4912, -4184, -4003, -2247, -2188, -4399, -3309, -7752, -3923, -3301, -3820, -2055, -7503, -5615, -5227, -3609, -1579, -5279, -5694, -5879, -4555, -2116, -5607, -4698, -5145, -7842, -3476, -7960, -3543, -4082, -8138, -4592, -15615, -2543, -3187, -5260, -5227, -10442, -1836, -3163, -4455, -6007, -9585, -1480, -4130, -3920, -5997, -12319, -1490, -4219, -2982, -4688, -13365, -1631, -2859, -2295, -3259, -9238, -1475, -2268, -2720, -2843, -7019, -1047, -2589, -5592, -3754, -5670, -787, -3692, -9238, -6321, -4211, -1091, -5776, -4779, -13738, -2752, -2452, -8247, -4616, -9936, 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-11945, -9380, -10442, -8517, -6628, -10210, -8582, -13365, -9149, -8790, -9812, -9695, -13365, -9380, -13738, -10001, -11004, -11629, -9479, -13365, -9238, -10799, -10442, -10526, -10526, -8060, -11232, -10799, -13049, -7960, -7247, -12319, -12319, -14195, -6653, -6928, -12319, -15615, -13365, -6299, -7113, -12123, -28777, -12776, -6666, -7842, -11629, -28777, -10284, -7865, -9479, -12319, -28777, -8827, -10613, -13049, -14784, -28777, -8903, -17034, -28777, -17034, -14784, -10284, -13365, -13365, -12123, -11629, -12319, -14195, -12123, -11356, -9936, -13365, -28777, -11629, -11945, -9695, -11629, -14195, -11488, -12319, -10799, -10138, -13365, -11781, -10799, -13365, -9873, -14195, -11945, -10284, -12534, -11781, -14784, -12319, -11356, -11232, -28777, -13365, -11488, -17034, -11629, -11115, -10138, -9812, -13738, -13049, -9585, -8790, };
\ No newline at end of file
diff --git a/sw/applications/trans_versasense/tokenPosEmbeddingC.c b/sw/applications/trans_versasense/tokenPosEmbeddingC.c
new file mode 100644
index 00000000..39a63e40
--- /dev/null
+++ b/sw/applications/trans_versasense/tokenPosEmbeddingC.c
@@ -0,0 +1,33 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "tokenPosEmbeddingC.h"
+
+
+void createTokenPosEmbedding(TokenPosEmbedding* tokenPosEmbedding, quant_bit_width* pos_matrix, quant_bit_width* cls_token_vector, size_t seq_len, size_t input_dim, size_t pos_matrix_dim) {
+    tokenPosEmbedding->cls_token_vector_ = cls_token_vector;
+    tokenPosEmbedding->pos_matrix_ = pos_matrix;
+    tokenPosEmbedding->seq_len_ = seq_len;
+    tokenPosEmbedding->input_dim_ = input_dim;
+}
+
+void clsConcatenate(TokenPosEmbedding* tpe, quant_bit_width* input, quant_bit_width* concatenated_input) {
+    // Copy cls_token_ into the concatenated array column-wise at the beginning
+    for (size_t i = 0; i < tpe->input_dim_; ++i) {
+        concatenated_input[i] = tpe->cls_token_vector_[i];
+    }
+    // Copy the input array into the concatenated array
+    for (size_t i = 0; i < tpe->seq_len_ * tpe->input_dim_; ++i) {
+        concatenated_input[i + tpe->input_dim_] = input[i];
+    }
+}
+
+void posEmbedding(TokenPosEmbedding* tpe, quant_bit_width* input) {
+    for (size_t i = 0; i < (tpe->seq_len_ + 1); ++i) {
+        for (size_t j = 0; j < tpe->input_dim_; ++j) {
+            input[i * tpe->input_dim_+ j] += tpe->pos_matrix_[i * tpe->input_dim_ + j];
+        }
+    }
+}
+
diff --git a/sw/applications/trans_versasense/tokenPosEmbeddingC.h b/sw/applications/trans_versasense/tokenPosEmbeddingC.h
new file mode 100644
index 00000000..9357a153
--- /dev/null
+++ b/sw/applications/trans_versasense/tokenPosEmbeddingC.h
@@ -0,0 +1,24 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TOKENPOSEMBEDDINGC_H
+#define FVLLMONTITRANSFORMER_TOKENPOSEMBEDDINGC_H
+
+#include "param.h"
+#include "stdlib.h"
+
+typedef struct{
+    quant_bit_width* cls_token_vector_;
+    quant_bit_width* pos_matrix_;
+    size_t seq_len_;
+    size_t input_dim_;
+} TokenPosEmbedding;
+
+
+void createTokenPosEmbedding(TokenPosEmbedding*, quant_bit_width* pos_matrix, quant_bit_width* cls_token_vector, size_t seq_len, size_t input_dim, size_t pos_matrix_dim);
+void clsConcatenate(TokenPosEmbedding* tpe, quant_bit_width* input, quant_bit_width* concatenated_input);
+void posEmbedding(TokenPosEmbedding* tpe, quant_bit_width* input);
+
+
+#endif //FVLLMONTITRANSFORMER_TOKENPOSEMBEDDINGC_H
diff --git a/sw/applications/trans_versasense/transformerBlockC.c b/sw/applications/trans_versasense/transformerBlockC.c
new file mode 100644
index 00000000..111a36af
--- /dev/null
+++ b/sw/applications/trans_versasense/transformerBlockC.c
@@ -0,0 +1,116 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include <stdio.h>
+#include "transformerBlockC.h"
+#include "multiply_cgra.h"
+
+SingleHeadSelfAttn global_selfatten [NUM_LAYERS * NUM_HEAD];
+Dense global_query_layer[NUM_LAYERS * NUM_HEAD];
+Dense global_key_layer[NUM_LAYERS * NUM_HEAD];
+Dense global_value_layer[NUM_LAYERS * NUM_HEAD];
+
+Dense global_condense[NUM_LAYERS];
+Dense global_patch;
+Dense global_FF[NUM_LAYERS * 2];
+Dense global_mlp;
+
+TransformerBlock  global_transformer_block;
+TokenPosEmbedding  global_token_embedding;
+
+TransformerBlock* createTransformerBlock(size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, size_t num_heads, size_t ff_size, int32_t** weightVector, int32_t** biasVector, int32_t* clsTokenVector, int32_t* posMatrix) {
+    TransformerBlock* transformerBlock = &global_transformer_block;
+    transformerBlock->num_heads_ = num_heads;
+    transformerBlock->head_hidden_size_ = head_hidden_size;
+    transformerBlock->input_dim_ = input_dim;
+    transformerBlock->ff_size_ = ff_size;
+
+    transformerBlock->addNorm = createAddNormalize(pre_seq_len, D_EMBEDDING, weightVector[0], biasVector[0]);
+    transformerBlock->patchEmbedding = &global_patch;
+    createDense(transformerBlock->patchEmbedding, D_EMBEDDING, D_MODEL, weightVector[1], biasVector[1]);
+    transformerBlock->addNorm2 = createAddNormalize(pre_seq_len, D_MODEL, weightVector[2], biasVector[2]);
+    transformerBlock->token = &global_token_embedding;
+    createTokenPosEmbedding(transformerBlock->token, posMatrix, clsTokenVector, pre_seq_len, input_dim, D_SEQ + 1);
+
+    for (int l = 0; l < 4; l++) {
+        transformerBlock->transformer_layer_0_addNorm[l] = createAddNormalize((pre_seq_len + 1), D_MODEL, weightVector[l * 17 + 3], biasVector[l * 17 + 3]);
+
+        for (int n = 0; n < num_heads; n++) {
+            transformerBlock->selfatten[l * num_heads + n] = &global_selfatten[l * num_heads + n];
+            transformerBlock->selfatten[l * num_heads + n]->query_layer = &global_query_layer[l * num_heads + n];
+            transformerBlock->selfatten[l * num_heads + n]->key_layer = &global_key_layer[l * num_heads + n];
+            transformerBlock->selfatten[l * num_heads + n]->value_layer = &global_value_layer[l * num_heads + n];
+
+            create_SingleHeadSelfAttn(transformerBlock->selfatten[l * num_heads + n], (pre_seq_len + 1), input_dim, head_hidden_size, weightVector + l * 17 + 4 + n * 3);
+        }
+
+        transformerBlock->condense[l] = &global_condense[l];
+        createDense(transformerBlock->condense[l], num_heads * head_hidden_size, input_dim, weightVector[l * 17 + num_heads * 3 + 4], biasVector[l * 17 + num_heads * 3 + 4]);
+
+        transformerBlock->transformer_layer_1_addNorm[l] = createAddNormalize((pre_seq_len + 1), input_dim, weightVector[l * 17 + num_heads * 3 + 5], biasVector[l * 17 + num_heads * 3 + 5]);
+
+        transformerBlock->feedForward0[l] = &global_FF[2*l];
+        createDense(transformerBlock->feedForward0[l], input_dim, ff_size, weightVector[l * 17 + num_heads * 3 + 6], biasVector[l * 17 + num_heads * 3 + 6]);
+
+        transformerBlock->feedForward1[l] = &global_FF[2*l + 1];
+        createDense(transformerBlock->feedForward1[l], ff_size, input_dim, weightVector[l * 17 + num_heads * 3 + 7], biasVector[l * 17 + num_heads * 3 + 7]);
+    }
+
+    transformerBlock->mlp_head_norm = createAddNormalize(1, D_MODEL, weightVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 8], biasVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 8]);
+
+    transformerBlock->mlp_head_linear = &global_mlp;
+    createDense(transformerBlock->mlp_head_linear, D_MODEL, D_MODEL, weightVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 9], biasVector[(NUM_LAYERS - 1) * 17 + NUM_HEAD * 3 + 9]);
+
+    return transformerBlock;
+}
+
+
+void destroyTransformerBlock(TransformerBlock* transformerBlock) {
+    // Free dynamically allocated memory
+
+    free(transformerBlock);
+}
+
+void computeFixedPoint(TransformerBlock* transformerBlock, size_t seq_len, quant_bit_width * input,
+                       quant_bit_width * input_normalized, quant_bit_width * output,
+                       quant_bit_width* intermediate, quant_bit_width* qkv, quant_bit_width * aux_padding, void * kperf) {
+
+    //printf("\rStep 1\n");
+    normalize(&transformerBlock->addNorm, input, input); // 12x400
+    computeDense(transformerBlock->patchEmbedding, seq_len, input, output); // 12x400x16 -> OK
+    normalize(&transformerBlock->addNorm2, output, output); // 12x16
+
+    clsConcatenate(transformerBlock->token, output, input); // 13x16
+    seq_len++;
+    posEmbedding(transformerBlock->token, input); // 13x16
+
+    //printf("\rStep 2\n");
+    for (int l = 0; l < 4; l++) {
+        normalize(&transformerBlock->transformer_layer_0_addNorm[l], input, input_normalized); // 13x16
+        for (int n = 0; n < NUM_HEAD; n++) {
+            // printf("\rl%d: Step 3\n", l);
+            compute_SingleHeadSelfAttn(transformerBlock->selfatten[l * NUM_HEAD + n], input_normalized,
+                                       output + n * (seq_len * transformerBlock->head_hidden_size_), qkv, intermediate, aux_padding);
+//            destroy_SingleHeadSelfAttn(transformerBlock->selfatten[l * NUM_HEAD + n]);
+        }
+        //printf("\rl%d: Step 4\n", l);
+        multihead_transpose(output, intermediate, seq_len, transformerBlock->head_hidden_size_, transformerBlock->num_heads_);
+
+        int padding = 3;
+        computeDense(transformerBlock->condense[l], seq_len + padding, intermediate, output); // 13x16x16
+
+        add(input, output, seq_len, transformerBlock->input_dim_ ); // 13x16
+
+        normalize(&transformerBlock->transformer_layer_1_addNorm[l], input, input_normalized); // 13x16
+        computeDense(transformerBlock->feedForward0[l], seq_len + padding, input_normalized, intermediate); // 13x16x4
+        activation(transformerBlock->feedForward0[l], seq_len * transformerBlock->ff_size_, intermediate, intermediate); // 13x4
+
+        computeDense(transformerBlock->feedForward1[l], seq_len + padding, intermediate, output); // 13x4x16
+        add(input, output, seq_len, transformerBlock->input_dim_ ); // 13x16
+    }
+    //printf("\rStep 5\n");
+    normalize(&transformerBlock->mlp_head_norm, input, input_normalized); // 13x16
+    computeDenseOneRow(transformerBlock->mlp_head_linear, 1, input_normalized, output); // 1x16x16
+}
+
diff --git a/sw/applications/trans_versasense/transformerBlockC.h b/sw/applications/trans_versasense/transformerBlockC.h
new file mode 100644
index 00000000..f783d2a7
--- /dev/null
+++ b/sw/applications/trans_versasense/transformerBlockC.h
@@ -0,0 +1,48 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TRANSFORMERBLOCK_H
+#define FVLLMONTITRANSFORMER_TRANSFORMERBLOCK_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include "selfattentionC.h"
+#include "addNormC.h"
+#include "dense_layerC.h"
+#include "tokenPosEmbeddingC.h"
+#include "param.h"
+#include "transposeC.h"
+#include "cgra.h"
+
+typedef struct {
+    size_t num_heads_;
+    size_t head_hidden_size_;
+    size_t input_dim_;
+    size_t ff_size_;
+    SingleHeadSelfAttn* selfatten[NUM_LAYERS*NUM_HEAD];
+    int32_t* multihead_out;
+    int32_t* condense_out;
+    int32_t* intermediateFF;
+    int32_t* intermediateFFBlockWise;
+    AddNormalize addNorm;
+    AddNormalize addNorm2;
+    AddNormalize transformer_layer_0_addNorm[NUM_LAYERS];
+    AddNormalize transformer_layer_1_addNorm[NUM_LAYERS];
+    AddNormalize mlp_head_norm;
+    TokenPosEmbedding* token;
+    Dense* condense[NUM_LAYERS];
+    Dense* feedForward0[NUM_LAYERS];
+    Dense* feedForward1[NUM_LAYERS];
+    Dense* patchEmbedding;
+    Dense* mlp_head_linear;
+    #ifndef REARRANGE
+    int32_t* multihead_out_reshape;
+    #endif
+} TransformerBlock;
+
+TransformerBlock* createTransformerBlock(size_t pre_seq_len, size_t input_dim, size_t head_hidden_size, size_t num_heads, size_t ff_size, int32_t** weightVector, int32_t** biasVector, int32_t* clsTokenVector, int32_t* posMatrix);
+void destroyTransformerBlock(TransformerBlock* transformerBlock);
+void computeFixedPoint(TransformerBlock* transformerBlock, size_t seq_len, int32_t* input, int32_t* input_normalized, int32_t* output, int32_t* intermediate, int32_t* aux_padding, int32_t* qkv, void * kperf);
+
+#endif //FVLLMONTITRANSFORMER_TRANSFORMERBLOCK_H
diff --git a/sw/applications/trans_versasense/transposeC.c b/sw/applications/trans_versasense/transposeC.c
new file mode 100644
index 00000000..2c27aa52
--- /dev/null
+++ b/sw/applications/trans_versasense/transposeC.c
@@ -0,0 +1,31 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#include "softmaxC.h"
+
+
+void multihead_transpose(const quant_bit_width * input, quant_bit_width* output, size_t seq_len,
+                         size_t head_hidden_size, size_t num_head) {
+    const quant_bit_width * initial_input = input;
+    for (int i=0; i < seq_len; i++){
+        for (int n=0; n< num_head; n++){
+            input = initial_input + i*head_hidden_size + n*seq_len*head_hidden_size;
+            for (int j=0; j < head_hidden_size; j++){
+                *output++ = *input++;
+            }
+        }
+    }
+}
+
+
+void transpose_quant(const quant_bit_width * input, quant_bit_width* output,
+                     size_t width, size_t height) {
+    for (size_t i = 0; i < height; i++) {
+        for (size_t j = 0; j < width; j++) {
+            output[i * width + j] = input[j * height + i];
+        }
+    }
+}
+
+
diff --git a/sw/applications/trans_versasense/transposeC.h b/sw/applications/trans_versasense/transposeC.h
new file mode 100644
index 00000000..500c100e
--- /dev/null
+++ b/sw/applications/trans_versasense/transposeC.h
@@ -0,0 +1,22 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_TRANSPOSEC_H
+#define FVLLMONTITRANSFORMER_TRANSPOSEC_H
+
+
+
+#include <stddef.h>
+#include "param.h"
+
+// Replace class with struct
+typedef struct {
+    // struct members
+} Transpose;
+
+// Function prototypes
+void transpose_quant(const quant_bit_width* input, quant_bit_width* output, size_t width, size_t height);
+void multihead_transpose(const quant_bit_width * input, quant_bit_width* output, size_t seq_len, size_t head_hidden_size, size_t num_head);
+
+#endif //FVLLMONTITRANSFORMER_TRANSPOSEC_H
diff --git a/sw/applications/trans_versasense/weightsAndBiasesC.c b/sw/applications/trans_versasense/weightsAndBiasesC.c
new file mode 100644
index 00000000..2fd600f0
--- /dev/null
+++ b/sw/applications/trans_versasense/weightsAndBiasesC.c
@@ -0,0 +1,181 @@
+//
+// Created by alireza on 10/6/23.
+//
+#include "weightsAndBiasesC.h"
+#include <stdint.h>
+#include <stddef.h>
+#include "data_cpp/data.cpp"
+
+void getWeights(quant_bit_width * weightVec[]){
+
+    int weightVectorIndex = 0;
+    weightVec[weightVectorIndex++] = to_patch_embedding_layer_norm1_weight;
+    weightVec[weightVectorIndex++] = to_patch_embedding_linear_weight;
+    weightVec[weightVectorIndex++] = to_patch_embedding_layer_norm2_weight;
+
+
+    /* *************************** Layer 1 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_0_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_0_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_0_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_0_1_fn_ff2_weight;
+
+    /* *************************** Layer 2 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_1_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_1_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_1_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_1_1_fn_ff2_weight;
+
+    /* *************************** Layer 3 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_2_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_2_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_2_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_2_1_fn_ff2_weight;
+
+    /* *************************** Layer 4 ***************************** */
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_norm_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H0;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H1;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H2;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_Q_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_K_H3;
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_to_qkv_weight_V_H3;
+
+    weightVec[weightVectorIndex++] = transformer_layers_3_0_fn_projection_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_3_1_norm_weight;
+
+    weightVec[weightVectorIndex++] = transformer_layers_3_1_fn_ff1_weight;
+    weightVec[weightVectorIndex++] = transformer_layers_3_1_fn_ff2_weight;
+
+    /* *************************** MLP HEAD ***************************** */
+    weightVec[weightVectorIndex++] = mlp_head_layer_norm_weight;
+    weightVec[weightVectorIndex++] = mlp_head_linear_weight;
+
+}
+
+void getBiases(quant_bit_width * biasVec[]){
+    int biasVectorIndex = 0;
+    biasVec[biasVectorIndex++] = to_patch_embedding_layer_norm1_bias;
+    biasVec[biasVectorIndex++] = to_patch_embedding_linear_bias;
+    biasVec[biasVectorIndex++] = to_patch_embedding_layer_norm2_bias;
+
+    /* *************************** Layer 1 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_0_0_norm_bias;
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_0_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_0_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_0_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_0_1_fn_ff2_bias;
+
+    /* *************************** Layer 2 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_1_0_norm_bias;
+
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_1_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_1_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_1_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_1_1_fn_ff2_bias;
+
+    /* *************************** Layer 3 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_2_0_norm_bias;
+
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_2_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_2_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_2_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_2_1_fn_ff2_bias;
+
+    /* *************************** Layer 4 ***************************** */
+    biasVec[biasVectorIndex++] = transformer_layers_3_0_norm_bias;
+
+    for (int i=0; i<3*4; i++)
+        biasVec[biasVectorIndex++] = (quant_bit_width *) NULL;
+
+    biasVec[biasVectorIndex++] = transformer_layers_3_0_fn_projection_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_3_1_norm_bias;
+
+    biasVec[biasVectorIndex++] = transformer_layers_3_1_fn_ff1_bias;
+    biasVec[biasVectorIndex++] = transformer_layers_3_1_fn_ff2_bias;
+
+    /* *************************** MLP HEAD ***************************** */
+    biasVec[biasVectorIndex++] = mlp_head_layer_norm_bias;
+    biasVec[biasVectorIndex++] = mlp_head_linear_bias;
+}
+
+quant_bit_width * getPosEmbedding(){
+    quant_bit_width * posMatrix;
+    posMatrix = pos_embedding;
+    return posMatrix;
+}
+
+quant_bit_width * getClassToken(){
+    quant_bit_width * clsTokenVector;
+    clsTokenVector = cls_token;
+    return clsTokenVector;
+}
+
+
diff --git a/sw/applications/trans_versasense/weightsAndBiasesC.h b/sw/applications/trans_versasense/weightsAndBiasesC.h
new file mode 100644
index 00000000..b16d6468
--- /dev/null
+++ b/sw/applications/trans_versasense/weightsAndBiasesC.h
@@ -0,0 +1,15 @@
+//
+// Created by alireza on 10/6/23.
+//
+
+#ifndef FVLLMONTITRANSFORMER_WEIGHTSANDBIASESC_H
+#define FVLLMONTITRANSFORMER_WEIGHTSANDBIASESC_H
+
+#include "param.h"
+
+void getWeights(quant_bit_width * weightVec[]);
+void getBiases(quant_bit_width * biasVec[]);
+quant_bit_width * getPosEmbedding();
+quant_bit_width * getClassToken();
+
+#endif //FVLLMONTITRANSFORMER_WEIGHTSANDBIASESC_H

From f5434756ccdda49c5932094185159162a03dc267 Mon Sep 17 00:00:00 2001
From: mbelda <11842513+mbelda@users.noreply.github.com>
Date: Tue, 9 Jul 2024 12:25:46 +0200
Subject: [PATCH 14/27] adapt minimal cfg for the cgra

---
 .../core-v-mini-mcu/peripheral_subsystem.sv   | 135 ++++++------------
 .../esl_epfl_x_heep/mcu_cfg_minimal.hjson     |   4 +-
 sw/applications/trans_versasense/SYLT-FFT     |   1 +
 .../transformer_without_cgra/SYLT-FFT         |   1 +
 4 files changed, 49 insertions(+), 92 deletions(-)
 create mode 160000 sw/applications/trans_versasense/SYLT-FFT
 create mode 160000 sw/applications/transformer_without_cgra/SYLT-FFT

diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv
index 5c28e195..bb1c1d19 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv
@@ -292,21 +292,10 @@ module peripheral_subsystem
   );
 
 
-  gpio #(
-      .reg_req_t(reg_pkg::reg_req_t),
-      .reg_rsp_t(reg_pkg::reg_rsp_t)
-  ) gpio_i (
-      .clk_i(clk_cg),
-      .rst_ni,
-      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::GPIO_IDX]),
-      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_IDX]),
-      .gpio_in({cio_gpio_i, 8'b0}),
-      .gpio_out({cio_gpio_o, cio_gpio_unused}),
-      .gpio_tx_en_o({cio_gpio_en_o, cio_gpio_en_unused}),
-      .gpio_in_sync_o(),
-      .pin_level_interrupts_o({gpio_intr, gpio_int_unused}),
-      .global_interrupt_o()
-  );
+  assign cio_gpio_o = '0;
+  assign cio_gpio_en_o = '0;
+  assign gpio_intr = '0;
+  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_IDX] = '0;
 
   reg_to_tlul #(
       .req_t(reg_pkg::reg_req_t),
@@ -325,34 +314,27 @@ module peripheral_subsystem
       .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::I2C_IDX])
   );
 
-  i2c i2c_i (
-      .clk_i(clk_cg),
-      .rst_ni,
-      .tl_i(i2c_tl_h2d),
-      .tl_o(i2c_tl_d2h),
-      .cio_scl_i,
-      .cio_scl_o,
-      .cio_scl_en_o,
-      .cio_sda_i,
-      .cio_sda_o,
-      .cio_sda_en_o,
-      .intr_fmt_watermark_o(i2c_intr_fmt_watermark),
-      .intr_rx_watermark_o(i2c_intr_rx_watermark),
-      .intr_fmt_overflow_o(i2c_intr_fmt_overflow),
-      .intr_rx_overflow_o(i2c_intr_rx_overflow),
-      .intr_nak_o(i2c_intr_nak),
-      .intr_scl_interference_o(i2c_intr_scl_interference),
-      .intr_sda_interference_o(i2c_intr_sda_interference),
-      .intr_stretch_timeout_o(i2c_intr_stretch_timeout),
-      .intr_sda_unstable_o(i2c_intr_sda_unstable),
-      .intr_trans_complete_o(i2c_intr_trans_complete),
-      .intr_tx_empty_o(i2c_intr_tx_empty),
-      .intr_tx_nonempty_o(i2c_intr_tx_nonempty),
-      .intr_tx_overflow_o(i2c_intr_tx_overflow),
-      .intr_acq_overflow_o(i2c_intr_acq_overflow),
-      .intr_ack_stop_o(i2c_intr_ack_stop),
-      .intr_host_timeout_o(i2c_intr_host_timeout)
-  );
+  assign i2c_tl_d2h = '0;
+  assign cio_scl_o = '0;
+  assign cio_scl_en_o = '0;
+  assign cio_sda_o = '0;
+  assign cio_sda_en_o = '0;
+  assign i2c_intr_fmt_watermark = '0;
+  assign i2c_intr_rx_watermark = '0;
+  assign i2c_intr_fmt_overflow = '0;
+  assign i2c_intr_rx_overflow = '0;
+  assign i2c_intr_nak = '0;
+  assign i2c_intr_scl_interference = '0;
+  assign i2c_intr_sda_interference = '0;
+  assign i2c_intr_stretch_timeout = '0;
+  assign i2c_intr_sda_unstable = '0;
+  assign i2c_intr_trans_complete = '0;
+  assign i2c_intr_tx_empty = '0;
+  assign i2c_intr_tx_nonempty = '0;
+  assign i2c_intr_tx_overflow = '0;
+  assign i2c_intr_acq_overflow = '0;
+  assign i2c_intr_ack_stop = '0;
+  assign i2c_intr_host_timeout = '0;
 
   reg_to_tlul #(
       .req_t(reg_pkg::reg_req_t),
@@ -380,56 +362,29 @@ module peripheral_subsystem
       .intr_timer_expired_1_0_o(rv_timer_3_intr_o)
   );
 
-  spi_host #(
-      .reg_req_t(reg_pkg::reg_req_t),
-      .reg_rsp_t(reg_pkg::reg_rsp_t)
-  ) spi2_host (
-      .clk_i(clk_cg),
-      .rst_ni,
-      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::SPI2_IDX]),
-      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI2_IDX]),
-      .alert_rx_i(),
-      .alert_tx_o(),
-      .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
-      .passthrough_o(),
-      .cio_sck_o(spi2_sck_o),
-      .cio_sck_en_o(spi2_sck_en_o),
-      .cio_csb_o(spi2_csb_o),
-      .cio_csb_en_o(spi2_csb_en_o),
-      .cio_sd_o(spi2_sd_o),
-      .cio_sd_en_o(spi2_sd_en_o),
-      .cio_sd_i(spi2_sd_i),
-      .rx_valid_o(),
-      .tx_ready_o(),
-      .intr_error_o(),
-      .intr_spi_event_o(spi2_intr_event)
-  );
+  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI2_IDX]    = '0;
+  assign spi2_sck_o                                           = '0;
+  assign spi2_sck_en_o                                        = '0;
+  assign spi2_csb_o                                           = '0;
+  assign spi2_csb_en_o                                        = '0;
+  assign spi2_sd_o                                            = '0;
+  assign spi2_sd_en_o                                         = '0;
+  assign spi2_intr_event                                      = '0;
 
   assign peripheral_slv_rsp[core_v_mini_mcu_pkg::PDM2PCM_IDX] = '0;
-  assign pdm2pcm_clk_o = '0;
+  assign pdm2pcm_clk_o                                        = '0;
 
-  assign pdm2pcm_clk_en_o = 1;
+  assign pdm2pcm_clk_en_o                                     = 1;
 
-  i2s #(
-      .reg_req_t(reg_pkg::reg_req_t),
-      .reg_rsp_t(reg_pkg::reg_rsp_t)
-  ) i2s_i (
-      .clk_i,
-      .rst_ni,
-      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::I2S_IDX]),
-      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::I2S_IDX]),
-
-      .i2s_sck_o(i2s_sck_o),
-      .i2s_sck_oe_o(i2s_sck_oe_o),
-      .i2s_sck_i(i2s_sck_i),
-      .i2s_ws_o(i2s_ws_o),
-      .i2s_ws_oe_o(i2s_ws_oe_o),
-      .i2s_ws_i(i2s_ws_i),
-      .i2s_sd_o(i2s_sd_o),
-      .i2s_sd_oe_o(i2s_sd_oe_o),
-      .i2s_sd_i(i2s_sd_i),
-      .intr_i2s_event_o(i2s_intr_event),
-      .i2s_rx_valid_o(i2s_rx_valid_o)
-  );
+  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::I2S_IDX]     = '0;
+
+  assign i2s_sck_oe_o                                         = 1'b0;
+  assign i2s_sck_o                                            = 1'b0;
+  assign i2s_ws_oe_o                                          = 1'b0;
+  assign i2s_ws_o                                             = 1'b0;
+  assign i2s_sd_oe_o                                          = 1'b0;
+  assign i2s_sd_o                                             = 1'b0;
+  assign i2s_intr_event                                       = 1'b0;
+  assign i2s_rx_valid_o                                       = 1'b0;
 
 endmodule : peripheral_subsystem
diff --git a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
index 98440522..df3b6ad1 100644
--- a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
+++ b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
@@ -103,7 +103,7 @@
         rv_plic: {
             offset:  0x00000000,
             length:  0x00010000,
-            is_included: "no",
+            is_included: "yes",
             path:    "./hw/vendor/lowrisc_opentitan/hw/ip/rv_plic/data/rv_plic.hjson"
         },
         gpio: {
@@ -121,7 +121,7 @@
         rv_timer: {
             offset:  0x00040000,
             length:  0x00010000,
-            is_included: "no",
+            is_included: "yes",
             path:    "./hw/vendor/lowrisc_opentitan/hw/ip/rv_timer/data/rv_timer.hjson"
         },
         spi2: {
diff --git a/sw/applications/trans_versasense/SYLT-FFT b/sw/applications/trans_versasense/SYLT-FFT
new file mode 160000
index 00000000..c6f58caa
--- /dev/null
+++ b/sw/applications/trans_versasense/SYLT-FFT
@@ -0,0 +1 @@
+Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b
diff --git a/sw/applications/transformer_without_cgra/SYLT-FFT b/sw/applications/transformer_without_cgra/SYLT-FFT
new file mode 160000
index 00000000..c6f58caa
--- /dev/null
+++ b/sw/applications/transformer_without_cgra/SYLT-FFT
@@ -0,0 +1 @@
+Subproject commit c6f58caa8d3d01c622768b5c66a0be1d7953235b

From af41634c9940945d7e0b00ed0f495bda48cd1d7e Mon Sep 17 00:00:00 2001
From: jmiranda <mirandacalero.joseangel@gmail.com>
Date: Wed, 25 Sep 2024 20:36:34 +0200
Subject: [PATCH 15/27] revendorizing oe-cgra

---
 hw/vendor/esl_epfl_cgra/.gitignore            |   12 +
 hw/vendor/esl_epfl_cgra/OpenEdgeCGRA.core     |   54 +
 hw/vendor/esl_epfl_cgra/data/cgra_reg_gen.sh  |    9 +-
 hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson  |  271 ----
 .../esl_epfl_cgra/data/cgra_regs.hjson.tpl    |   93 ++
 hw/vendor/esl_epfl_cgra/{ => hw}/rtl/alu.sv   |    0
 .../{ => hw}/rtl/cgra_controller.sv           |    0
 .../cgra_pkg.sv => hw/rtl/cgra_pkg.sv.tpl}    |   51 +-
 .../esl_epfl_cgra/{ => hw}/rtl/cgra_rcs.sv    |   24 +-
 .../esl_epfl_cgra/{ => hw}/rtl/cgra_top.sv    |   38 +-
 .../{ => hw}/rtl/conf_reg_file.sv             |   16 +-
 .../{ => hw}/rtl/context_memory.sv            |    4 +-
 .../{ => hw}/rtl/context_memory_decoder.sv    |    0
 .../{ => hw}/rtl/data_bus_handler.sv          |   14 +-
 .../esl_epfl_cgra/{ => hw}/rtl/datapath.sv    |   10 +-
 hw/vendor/esl_epfl_cgra/{ => hw}/rtl/mux.sv   |    0
 .../hw/rtl/peripheral_regs.sv.tpl             |   88 ++
 .../{ => hw}/rtl/program_counter.sv           |    0
 .../{ => hw}/rtl/reconfigurable_cell.sv       |   60 +-
 .../esl_epfl_cgra/{ => hw}/rtl/reg_file.sv    |   16 +-
 .../{ => hw}/rtl/synchronizer.sv              |  130 +-
 .../{ => hw}/wrapper/cgra_top_wrapper.sv      |  106 +-
 hw/vendor/esl_epfl_cgra/lint/cgra.vlt         |   48 +-
 hw/vendor/esl_epfl_cgra/rtl/cgra_reg_pkg.sv   |  369 -----
 hw/vendor/esl_epfl_cgra/rtl/cgra_reg_top.sv   | 1339 -----------------
 .../esl_epfl_cgra/rtl/peripheral_regs.sv      |  117 --
 .../esl_epfl_cgra/sim/cgra_sram_wrapper.sv    |    2 +-
 hw/vendor/esl_epfl_cgra/sw/cgra_regs.h        |  125 --
 .../util/INSTRUCTIONS_FFT_SPLITOPS.py         |  186 +++
 .../cgra_bitstream_gen.py.tpl}                |   62 +-
 .../util/instructions_check_size.py           |   33 +
 .../instructions_dbl_max.py                   |   10 +-
 .../instructions_dbl_min.py                   |   10 +-
 .../util/instructions_fft_bitrev.py           |  103 ++
 .../instructions_fft_cplx.py                  |   12 +-
 .../instructions_fft_cplx_forever.py          |   12 +-
 .../instructions_func_test.py                 |   64 +-
 .../util/instructions_max_peak.py             |   87 ++
 .../util/instructions_min_max_circular.py     |   83 +
 .../instructions_while_loop_100percent.py     |   32 +-
 .../instructions_while_loop_50percent.py      |   16 +-
 .../instructions_while_loop_75percent.py      |   24 +-
 .../{utilities => util}/log2file.py           |    0
 .../util/lowrisc_opentitan/reggen/README.md   |  113 ++
 .../util/lowrisc_opentitan/reggen/__init__.py |    0
 .../util/lowrisc_opentitan/reggen/access.py   |  121 ++
 .../util/lowrisc_opentitan/reggen/alert.py    |   54 +
 .../util/lowrisc_opentitan/reggen/bits.py     |   87 ++
 .../reggen/bus_interfaces.py                  |  187 +++
 .../lowrisc_opentitan/reggen/enum_entry.py    |   35 +
 .../util/lowrisc_opentitan/reggen/field.py    |  291 ++++
 .../lowrisc_opentitan/reggen/fpv_csr.sv.tpl   |  177 +++
 .../lowrisc_opentitan/reggen/gen_cfg_html.py  |  113 ++
 .../lowrisc_opentitan/reggen/gen_cheader.py   |  439 ++++++
 .../util/lowrisc_opentitan/reggen/gen_dv.py   |  108 ++
 .../util/lowrisc_opentitan/reggen/gen_fpv.py  |   81 +
 .../util/lowrisc_opentitan/reggen/gen_html.py |  325 ++++
 .../util/lowrisc_opentitan/reggen/gen_json.py |   34 +
 .../util/lowrisc_opentitan/reggen/gen_rtl.py  |  136 ++
 .../lowrisc_opentitan/reggen/gen_selfdoc.py   |  306 ++++
 .../lowrisc_opentitan/reggen/html_helpers.py  |   83 +
 .../lowrisc_opentitan/reggen/inter_signal.py  |   81 +
 .../util/lowrisc_opentitan/reggen/ip_block.py |  365 +++++
 .../util/lowrisc_opentitan/reggen/lib.py      |  262 ++++
 .../reggen/multi_register.py                  |  142 ++
 .../util/lowrisc_opentitan/reggen/params.py   |  341 +++++
 .../util/lowrisc_opentitan/reggen/reg_base.py |   45 +
 .../lowrisc_opentitan/reggen/reg_block.py     |  431 ++++++
 .../lowrisc_opentitan/reggen/reg_html.css     |   74 +
 .../lowrisc_opentitan/reggen/reg_pkg.sv.tpl   |  347 +++++
 .../lowrisc_opentitan/reggen/reg_top.sv.tpl   |  712 +++++++++
 .../util/lowrisc_opentitan/reggen/register.py |  375 +++++
 .../util/lowrisc_opentitan/reggen/signal.py   |   63 +
 .../lowrisc_opentitan/reggen/uvm_reg.sv.tpl   |   14 +
 .../reggen/uvm_reg_base.sv.tpl                |  431 ++++++
 .../util/lowrisc_opentitan/reggen/validate.py |  155 ++
 .../util/lowrisc_opentitan/reggen/version.py  |   24 +
 .../util/lowrisc_opentitan/reggen/window.py   |  169 +++
 .../util/lowrisc_opentitan/regtool.py         |  235 +++
 .../util/lowrisc_opentitan/topgen/__init__.py |    8 +
 .../util/lowrisc_opentitan/topgen/c.py        |  444 ++++++
 .../util/lowrisc_opentitan/topgen/gen_dv.py   |   46 +
 .../lowrisc_opentitan/topgen/intermodule.py   | 1005 +++++++++++++
 .../util/lowrisc_opentitan/topgen/lib.py      |  497 ++++++
 .../util/lowrisc_opentitan/topgen/merge.py    | 1081 +++++++++++++
 .../topgen/templates/README.md                |    4 +
 .../templates/chip_env_pkg__params.sv.tpl     |   17 +
 .../topgen/templates/chiplevel.sv.tpl         | 1218 +++++++++++++++
 .../topgen/templates/clang-format             |    4 +
 .../tb__alert_handler_connect.sv.tpl          |   21 +
 .../topgen/templates/tb__xbar_connect.sv.tpl  |  124 ++
 .../topgen/templates/toplevel.c.tpl           |   21 +
 .../topgen/templates/toplevel.h.tpl           |  201 +++
 .../topgen/templates/toplevel.sv.tpl          |  832 ++++++++++
 .../topgen/templates/toplevel_memory.h.tpl    |   62 +
 .../topgen/templates/toplevel_memory.ld.tpl   |   30 +
 .../topgen/templates/toplevel_pkg.sv.tpl      |  112 ++
 .../templates/toplevel_rnd_cnst_pkg.sv.tpl    |   44 +
 .../templates/xbar_env_pkg__params.sv.tpl     |   88 ++
 .../util/lowrisc_opentitan/topgen/top.py      |  122 ++
 .../topgen/top_uvm_reg.sv.tpl                 |  151 ++
 .../util/lowrisc_opentitan/topgen/validate.py |  878 +++++++++++
 .../utilities/instructions_fft_bitrev.py      |  209 ---
 hw/vendor/eslepfl_cgra.lock.hjson             |    2 +-
 hw/vendor/eslepfl_cgra.vendor.hjson           |    2 +-
 105 files changed, 15068 insertions(+), 2841 deletions(-)
 create mode 100644 hw/vendor/esl_epfl_cgra/OpenEdgeCGRA.core
 delete mode 100644 hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson
 create mode 100644 hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson.tpl
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/alu.sv (100%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/cgra_controller.sv (100%)
 rename hw/vendor/esl_epfl_cgra/{rtl/cgra_pkg.sv => hw/rtl/cgra_pkg.sv.tpl} (81%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/cgra_rcs.sv (94%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/cgra_top.sv (90%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/conf_reg_file.sv (77%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/context_memory.sv (91%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/context_memory_decoder.sv (100%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/data_bus_handler.sv (92%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/datapath.sv (96%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/mux.sv (100%)
 create mode 100644 hw/vendor/esl_epfl_cgra/hw/rtl/peripheral_regs.sv.tpl
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/program_counter.sv (100%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/reconfigurable_cell.sv (66%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/reg_file.sv (73%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/rtl/synchronizer.sv (57%)
 rename hw/vendor/esl_epfl_cgra/{ => hw}/wrapper/cgra_top_wrapper.sv (57%)
 delete mode 100644 hw/vendor/esl_epfl_cgra/rtl/cgra_reg_pkg.sv
 delete mode 100644 hw/vendor/esl_epfl_cgra/rtl/cgra_reg_top.sv
 delete mode 100644 hw/vendor/esl_epfl_cgra/rtl/peripheral_regs.sv
 delete mode 100644 hw/vendor/esl_epfl_cgra/sw/cgra_regs.h
 create mode 100644 hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py
 rename hw/vendor/esl_epfl_cgra/{utilities/cgra_bitsream_gen.py => util/cgra_bitstream_gen.py.tpl} (84%)
 create mode 100644 hw/vendor/esl_epfl_cgra/util/instructions_check_size.py
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_dbl_max.py (98%)
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_dbl_min.py (98%)
 create mode 100644 hw/vendor/esl_epfl_cgra/util/instructions_fft_bitrev.py
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_fft_cplx.py (98%)
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_fft_cplx_forever.py (98%)
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_func_test.py (98%)
 create mode 100644 hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_while_loop_100percent.py (97%)
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_while_loop_50percent.py (98%)
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/instructions_while_loop_75percent.py (97%)
 rename hw/vendor/esl_epfl_cgra/{utilities => util}/log2file.py (100%)
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/README.md
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/__init__.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/access.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/alert.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bits.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bus_interfaces.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/enum_entry.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/field.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/fpv_csr.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cfg_html.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cheader.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_dv.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_fpv.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_html.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_json.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_rtl.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_selfdoc.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/html_helpers.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/inter_signal.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/ip_block.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/lib.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/multi_register.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/params.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_base.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_block.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_html.css
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_pkg.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_top.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/register.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/signal.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg_base.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/validate.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/version.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/window.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/regtool.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/__init__.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/c.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/gen_dv.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/intermodule.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/lib.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/merge.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/README.md
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chip_env_pkg__params.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chiplevel.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/clang-format
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__alert_handler_connect.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__xbar_connect.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.c.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.h.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.h.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.ld.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_pkg.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/xbar_env_pkg__params.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top.py
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top_uvm_reg.sv.tpl
 create mode 100644 hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/validate.py
 delete mode 100644 hw/vendor/esl_epfl_cgra/utilities/instructions_fft_bitrev.py

diff --git a/hw/vendor/esl_epfl_cgra/.gitignore b/hw/vendor/esl_epfl_cgra/.gitignore
index 9550a8bc..cbfbb313 100644
--- a/hw/vendor/esl_epfl_cgra/.gitignore
+++ b/hw/vendor/esl_epfl_cgra/.gitignore
@@ -2,3 +2,15 @@
 build
 *_app
 bitstream
+*__pycache__*
+
+# Generated hardware files
+hw/rtl/cgra_pkg.sv
+hw/rtl/cgra_reg_pkg.sv
+hw/rtl/cgra_reg_top.sv
+hw/rtl/peripheral_regs.sv
+data/cgra_regs.hjson
+
+# Generated software files
+sw/cgra_regs.h
+util/cgra_bitstream_gen.py
diff --git a/hw/vendor/esl_epfl_cgra/OpenEdgeCGRA.core b/hw/vendor/esl_epfl_cgra/OpenEdgeCGRA.core
new file mode 100644
index 00000000..21fa115d
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/OpenEdgeCGRA.core
@@ -0,0 +1,54 @@
+CAPI=2:
+
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+name: "eslepfl::cgra"
+description: "CGRA HDL"
+
+filesets:
+  files_rtl:
+    depend:
+    - x-heep::packages
+    - pulp-platform.org::common_cells
+    files:
+    - hw/rtl/cgra_pkg.sv
+    - hw/rtl/cgra_reg_pkg.sv
+    - hw/rtl/cgra_reg_top.sv
+    - hw/rtl/peripheral_regs.sv
+    - hw/rtl/program_counter.sv
+    - hw/rtl/alu.sv
+    - hw/rtl/reg_file.sv
+    - hw/rtl/mux.sv
+    - hw/rtl/datapath.sv
+    - hw/rtl/conf_reg_file.sv
+    - hw/rtl/reconfigurable_cell.sv
+    - hw/rtl/data_bus_handler.sv
+    - hw/rtl/synchronizer.sv
+    - hw/rtl/cgra_controller.sv
+    - hw/rtl/cgra_rcs.sv
+    - hw/rtl/context_memory_decoder.sv
+    - hw/rtl/cgra_top.sv
+    - hw/rtl/context_memory.sv
+    - hw/wrapper/cgra_top_wrapper.sv
+    file_type: systemVerilogSource
+
+
+  files_behav_rtl:
+    files:
+    - sim/cgra_clock_gate.sv
+    - sim/cgra_sram_wrapper.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    files:
+    - lint/cgra.vlt
+    file_type: vlt
+
+targets:
+  default:
+    filesets:
+    - files_rtl
+    - tool_verilator? (files_verilator_waiver)
+    - target_sim? (files_behav_rtl)
diff --git a/hw/vendor/esl_epfl_cgra/data/cgra_reg_gen.sh b/hw/vendor/esl_epfl_cgra/data/cgra_reg_gen.sh
index 8829ffb8..5e44b337 100755
--- a/hw/vendor/esl_epfl_cgra/data/cgra_reg_gen.sh
+++ b/hw/vendor/esl_epfl_cgra/data/cgra_reg_gen.sh
@@ -2,7 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-echo "Generating CGRA Register RTL"
-python3 ../utilities/lowrisc_opentitan/regtool.py -r -t ../rtl cgra_regs.hjson
-echo "Generating CGRA Register SW"
-python3 ../utilities/lowrisc_opentitan/regtool.py  --cdefines -o ../sw/cgra_regs.h cgra_regs.hjson
+echo "Generating RTL"
+${PYTHON} ../util/lowrisc_opentitan/regtool.py -r -t ../hw/rtl ./cgra_regs.hjson
+echo "Generating SW"
+mkdir -p ../sw
+${PYTHON} ../util/lowrisc_opentitan/regtool.py --cdefines -o ../sw/cgra_regs.h ./cgra_regs.hjson
diff --git a/hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson b/hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson
deleted file mode 100644
index 6d8b01d3..00000000
--- a/hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson
+++ /dev/null
@@ -1,271 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-{ name: "cgra",
-  clock_primary: "clk_i",
-  bus_interfaces: [
-    { protocol: "reg_iface", direction: "device" }
-  ],
-  regwidth: "32",
-  registers: [
-    { name:     "COL_STATUS",
-      desc:     "CGRA columns status (0:free, 1:used)",
-      swaccess: "ro",
-      hwaccess: "hrw",
-      resval:   0, // all column free
-      fields: [
-        { bits: "3:0", name: "COL_STATUS", desc: "CGRA columns status (0:free, 1:used)" }
-      ]
-    },
-    { name:     "SLOT0_KER_ID",
-      desc:     "Slot 0 kernel ID",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "SLOT0_KER_ID", desc: "Slot 0 kernel ID" }
-      ]
-    },
-    { name:     "SLOT1_KER_ID",
-      desc:     "Slot 1 kernel ID",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "SLOT1_KER_ID", desc: "Slot 1 kernel ID" }
-      ]
-    },
-    { name:     "SLOT0_PTR_IN_C0",
-      desc:     "Slot 0 input data pointer for first column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_IN_C0", desc: "Slot 0 input data pointer for first column used" }
-      ]
-    },
-    { name:     "SLOT0_PTR_OUT_C0",
-      desc:     "Slot 0 output data pointer for first column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_OUT_C0", desc: "Slot 0 output data pointer for first column used" }
-      ]
-    },
-    { name:     "SLOT0_PTR_IN_C1",
-      desc:     "Slot 0 input data pointer for second column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_IN_C1", desc: "Slot 0 input data pointer for second column used" }
-      ]
-    },
-    { name:     "SLOT0_PTR_OUT_C1",
-      desc:     "Slot 0 Output data pointer for second column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_OUT_C1", desc: "Slot 0 Output data pointer for second column used" }
-      ]
-    },
-    { name:     "SLOT0_PTR_IN_C2",
-      desc:     "Slot 0 input data pointer for third column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_IN_C2", desc: "Slot 0 input data pointer for third column used" }
-      ]
-    },
-    { name:     "SLOT0_PTR_OUT_C2",
-      desc:     "Slot 0 output data pointer for first column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_OUT_C2", desc: "Slot 0 output data pointer for first column used" }
-      ]
-    },
-    { name:     "SLOT0_PTR_IN_C3",
-      desc:     "Slot 0 input data pointer for fourth column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_IN_C3", desc: "Slot 0 input data pointer for fourth column used" }
-      ]
-    },
-    { name:     "SLOT0_PTR_OUT_C3",
-      desc:     "Slot 1 output data pointer for fourth column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT0_PTR_OUT_C3", desc: "Slot 0 output data pointer for fourth column used" }
-      ]
-    },
-
-    { name:     "SLOT1_PTR_IN_C0",
-      desc:     "Slot 1 input data pointer for first column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_IN_C0", desc: "Slot 1 input data pointer for first column used" }
-      ]
-    },
-    { name:     "SLOT1_PTR_OUT_C0",
-      desc:     "Slot 1 output data pointer for first column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_OUT_C0", desc: "Slot 1 output data pointer for first column used" }
-      ]
-    },
-    { name:     "SLOT1_PTR_IN_C1",
-      desc:     "Slot 1 input data pointer for second column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_IN_C1", desc: "Slot 1 input data pointer for second column used" }
-      ]
-    },
-    { name:     "SLOT1_PTR_OUT_C1",
-      desc:     "Slot 1 Output data pointer for second column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_OUT_C1", desc: "Slot 1 Output data pointer for second column used" }
-      ]
-    },
-    { name:     "SLOT1_PTR_IN_C2",
-      desc:     "Slot 1 input data pointer for third column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_IN_C2", desc: "Slot 1 input data pointer for third column used" }
-      ]
-    },
-    { name:     "SLOT1_PTR_OUT_C2",
-      desc:     "Slot 1 output data pointer for first column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_OUT_C2", desc: "Slot 1 output data pointer for first column used" }
-      ]
-    },
-    { name:     "SLOT1_PTR_IN_C3",
-      desc:     "Slot 1 input data pointer for fourth column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_IN_C3", desc: "Slot 1 input data pointer for fourth column used" }
-      ]
-    },
-    { name:     "SLOT1_PTR_OUT_C3",
-      desc:     "Slot 1 output data pointer for fourth column used",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "SLOT1_PTR_OUT_C3", desc: "Slot 1 output data pointer for fourth column used" }
-      ]
-    },
-    { name:     "PERF_CNT_ENABLE",
-      desc:     "Enable performance counters",
-      swaccess: "rw",
-      hwaccess: "hro",
-      fields: [
-        { bits: "0", name: "PERF_CNT_ENABLE", desc: "Enable performance counters" }
-      ]
-    },
-    { name:     "PERF_CNT_RESET",
-      desc:     "Reset performance counters",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "0", name: "PERF_CNT_RESET", desc: "Reset performance counters" }
-      ]
-    },
-    { name:     "PERF_CNT_TOTAL_KERNELS",
-      desc:     "Total number of kernels executed (all columns)",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_TOTAL_KERNELS", desc: "Total number of kernels executed" }
-      ]
-    },
-    { name:     "PERF_CNT_C0_ACTIVE_CYCLES",
-      desc:     "Number of active cycles (configuration+execution)) of column 0",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C0_ACTIVE_CYCLES", desc: "Number of active cycles (configuration+execution)) of column 0" }
-      ]
-    },
-    { name:     "PERF_CNT_C0_STALL_CYCLES",
-      desc:     "Number of stall cycles during execution of column 0",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C0_STALL_CYCLES", desc: "Number of stall cycles during execution of column 0" }
-      ]
-    },
-    { name:     "PERF_CNT_C1_ACTIVE_CYCLES",
-      desc:     "Number of active cycles (configuration+execution)) of column 1",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C1_ACTIVE_CYCLES", desc: "Number of active cycles (configuration+execution)) of column 1" }
-      ]
-    },
-    { name:     "PERF_CNT_C1_STALL_CYCLES",
-      desc:     "Number of stall cycles during execution of column 1",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C1_STALL_CYCLES", desc: "Number of stall cycles during execution of column 1" }
-      ]
-    },
-    { name:     "PERF_CNT_C2_ACTIVE_CYCLES",
-      desc:     "Number of active cycles (configuration+execution) )of column 2",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C2_ACTIVE_CYCLES", desc: "Number of active cycles (configuration+execution) )of column 2" }
-      ]
-    },
-    { name:     "PERF_CNT_C2_STALL_CYCLES",
-      desc:     "Number of stall cycles during execution of column 2",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C2_STALL_CYCLES", desc: "Number of stall cycles during execution of column 2" }
-      ]
-    },
-    { name:     "PERF_CNT_C3_ACTIVE_CYCLES",
-      desc:     "Number of active cycles (configuration+execution) of column 3",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C3_ACTIVE_CYCLES", desc: "Number of active cycles (configuration+execution) of column 3" }
-      ]
-    },
-    { name:     "PERF_CNT_C3_STALL_CYCLES",
-      desc:     "Number of stall cycles during execution of column 3",
-      swaccess: "rw",
-      hwaccess: "hrw",
-      fields: [
-        { bits: "31:0", name: "PERF_CNT_C3_STALL_CYCLES", desc: "Number of stall cycles during execution of column 3" }
-      ]
-    },
-    { name:     "RESERVED30",
-      desc:     "Reserved",
-      swaccess: "ro",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "RESERVED30", desc: "Reserved" }
-      ]
-    },
-    { name:     "RESERVED31",
-      desc:     "Reserved",
-      swaccess: "ro",
-      hwaccess: "hro",
-      fields: [
-        { bits: "31:0", name: "RESERVED31", desc: "Reserved" }
-      ]
-    },
-   ]
-}
diff --git a/hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson.tpl b/hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson.tpl
new file mode 100644
index 00000000..bfba1e54
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/data/cgra_regs.hjson.tpl
@@ -0,0 +1,93 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{ name: "cgra",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: "32",
+  registers: [
+    { name:     "COL_STATUS",
+      desc:     "CGRA columns status (0:free, 1:used)",
+      swaccess: "ro",
+      hwaccess: "hrw",
+      resval:   0, // all column free
+      fields: [
+        { bits: "${cgra_num_columns-1}:0", name: "COL_STATUS", desc: "CGRA columns status (0:free, 1:used)" }
+      ]
+    },
+    { name:     "KERNEL_ID",
+      desc:     "Kernel ID acceleration request",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "31:0", name: "KERNEL_ID", desc: "Kernel ID acceleration request" }
+      ]
+    },
+
+  % for col in range(cgra_max_columns):
+    { name:     "PTR_IN_COL_${col}",
+      desc:     "Input data pointer for column ${col} used",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "PTR_IN_C${col}", desc: "Input data pointer for column ${col} used" }
+      ]
+    },
+    { name:     "PTR_OUT_COL_${col}",
+      desc:     "Output data pointer for column ${col} used",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "PTR_OUT_COL_${col}", desc: "Output data pointer for column ${col} used" }
+      ]
+    },
+  % endfor
+
+    { name:     "PERF_CNT_ENABLE",
+      desc:     "Enable performance counters",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0", name: "PERF_CNT_ENABLE", desc: "Enable performance counters" }
+      ]
+    },
+    { name:     "PERF_CNT_RESET",
+      desc:     "Reset performance counters",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "0", name: "PERF_CNT_RESET", desc: "Reset performance counters" }
+      ]
+    },
+    { name:     "PERF_CNT_TOTAL_KERNELS",
+      desc:     "Total number of kernels executed (all columns)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "31:0", name: "PERF_CNT_TOTAL_KERNELS", desc: "Total number of kernels executed" }
+      ]
+    },
+
+  % for col in range(cgra_num_columns):
+    { name:     "PERF_CNT_COL_${col}_ACTIVE_CYCLES",
+      desc:     "Number of active cycles (configuration+execution)) of column ${col}",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "31:0", name: "PERF_CNT_COL_${col}_ACTIVE_CYCLES", desc: "Number of active cycles (configuration+execution)) of column ${col}" }
+      ]
+    },
+    { name:     "PERF_CNT_COL_${col}_STALL_CYCLES",
+      desc:     "Number of stall cycles during execution of column ${col}",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        { bits: "31:0", name: "PERF_CNT_COL_${col}_STALL_CYCLES", desc: "Number of stall cycles during execution of column ${col}" }
+      ]
+    },
+  % endfor
+   ]
+}
diff --git a/hw/vendor/esl_epfl_cgra/rtl/alu.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/alu.sv
similarity index 100%
rename from hw/vendor/esl_epfl_cgra/rtl/alu.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/alu.sv
diff --git a/hw/vendor/esl_epfl_cgra/rtl/cgra_controller.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/cgra_controller.sv
similarity index 100%
rename from hw/vendor/esl_epfl_cgra/rtl/cgra_controller.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/cgra_controller.sv
diff --git a/hw/vendor/esl_epfl_cgra/rtl/cgra_pkg.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/cgra_pkg.sv.tpl
similarity index 81%
rename from hw/vendor/esl_epfl_cgra/rtl/cgra_pkg.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/cgra_pkg.sv.tpl
index 143dea5d..9e9c615d 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/cgra_pkg.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/cgra_pkg.sv.tpl
@@ -4,32 +4,33 @@
 
 package cgra_pkg;
 
-  // This configures the number of peripheral registers
-  // in order to have independent set of registers for each slot
-  localparam N_SLOTS      = 2;
-  localparam N_SLOTS_LOG2 = $clog2(N_SLOTS);
-
   // CGRA GRID CONFIGURATION
-  localparam N_ROW      = 4;
-  localparam N_ROW_LOG2 = $clog2(N_ROW);
-  localparam N_COL      = 4;
-  localparam N_COL_LOG2 = $clog2(N_COL);
-
-  // Data bus master ports
-  localparam MP         = N_COL;
-  localparam ID         = 9;
-
-  // CGRA APB REGISTERS
-  localparam N_PERIPH_REGS      = 32;
-  localparam N_PERIPH_REGS_LOG2 = $clog2(N_PERIPH_REGS);
+  localparam N_ROW      = ${cgra_num_rows};
+  localparam N_ROW_LOG2 = N_ROW == 1 ? 1 : $clog2(N_ROW);
+  localparam N_COL      = ${cgra_num_columns};
+  localparam N_COL_LOG2 = N_COL == 1 ? 1 : $clog2(N_COL);
+
+  // Maximum number of columns a kernel can use
+  localparam MAX_COL_REQ      = ${cgra_max_columns};
+  localparam MAX_COL_REQ_LOG2 = $clog2(MAX_COL_REQ);
   
-  localparam CGRA_APB_REG_STATE = 0;
+  // Registers:
+  // 0: Status
+  // 1: Kernel ID
+  // 2-...: 2*MAX_COL_REQ (2 pointers per columns)
+  // ...: Performance counters enable
+  // ...: Performance counters reset 
+  // ...: Performance counter number of executed kernels
+  // ...: Performance counter 2*N_COL (active and stall cycles)
+  localparam CGRA_PERIPH_STATUS_REG_OFFSET = 0;
+  localparam CGRA_NUM_PERIPH_REG = ${5+2*cgra_max_columns+2*cgra_num_columns};
+  localparam CGRA_NUM_PERIPH_REG_LOG2 = $clog2(CGRA_NUM_PERIPH_REG);
 
   // RCs CONFIGURATION
   localparam RC_NUM_REG     = 4;
   localparam RC_NUM_REG_LOG = $clog2(RC_NUM_REG);
 
-  localparam RCS_NUM_CREG     = 32;
+  localparam RCS_NUM_CREG     = ${cgra_rcs_num_instr};
   localparam RCS_NUM_CREG_LOG2 = $clog2(RCS_NUM_CREG);
 
   localparam DP_WIDTH       = 32;
@@ -41,23 +42,19 @@ package cgra_pkg;
   localparam N_MEM_BANKS      = N_ROW+1;
   localparam N_MEM_BANKS_LOG2 = $clog2(N_MEM_BANKS);
 
-  localparam IMEM_N_LINES      = 128; // per RC
+  localparam IMEM_N_LINES      = ${cgra_cmem_bk_depth}; // per RC
   localparam IMEM_N_LINES_LOG2 = $clog2(IMEM_N_LINES);
 
   // for compatibilty reason
   localparam RC_INSTR_N_REG = IMEM_N_LINES;
   localparam RC_INSTR_N_REG_LOG2 = IMEM_N_LINES_LOG2;
 
-  localparam KER_CONF_N_REG      = 16;
+  localparam KER_CONF_N_REG      = ${cgra_kmem_depth};
   localparam KER_CONF_N_REG_LOG2 = $clog2(KER_CONF_N_REG);
 
   // Number of bits needed to write to the multi-banks instruction memory
   localparam WR_INSTR_ADD_LEN = N_MEM_BANKS_LOG2+RC_INSTR_N_REG_LOG2;
 
-  // PLATFORM SPECIFIC CONFIGURATION
-  localparam CGRA_BITSTREAM_FILENAME = "$IPS_ROOT/cgra/mem/cgra_imem.bit";
-  localparam CGRA_KER_MEM_FILENAME   = "$IPS_ROOT/cgra/mem/cgra_kmem.bit";
-
   // AHB MEMORY INTERFACE
   localparam DATA_BUS_DATA_WIDTH = 32;
   localparam DATA_BUS_ADD_WIDTH  = 32;
@@ -135,8 +132,4 @@ package cgra_pkg;
   localparam KER_N_COL_LB     = RCS_IMEM_ADD_HB+1;
   localparam KER_N_COL_HB     = KER_N_COL_LB+N_COL-1;
 
-  // Maximum number of columns a kernel can use
-  localparam MAX_COL_REQ      = N_COL;
-  localparam MAX_COL_REQ_LOG2 = $clog2(MAX_COL_REQ);
-
 endpackage
diff --git a/hw/vendor/esl_epfl_cgra/rtl/cgra_rcs.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/cgra_rcs.sv
similarity index 94%
rename from hw/vendor/esl_epfl_cgra/rtl/cgra_rcs.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/cgra_rcs.sv
index 28ca4a75..ef06ede5 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/cgra_rcs.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/cgra_rcs.sv
@@ -21,6 +21,7 @@ module cgra_rcs
   output logic [            N_COL-1:0] data_ind_o,
   output logic [         DP_WIDTH-1:0] data_add_o [0:N_COL-1],
   output logic [         DP_WIDTH-1:0] data_wdata_o [0:N_COL-1],
+  output logic [   RC_CONST_WIDTH-1:0] add_inc_o [0:N_COL-1],
   output logic [            N_COL-1:0] rcs_br_req_o,
   output logic [RCS_NUM_CREG_LOG2-1:0] rcs_br_add_o [0:N_COL-1],
   output logic [            N_COL-1:0] rcs_stall_o,
@@ -43,6 +44,7 @@ module cgra_rcs
   logic [   N_COL-1:0] data_ind_s [0:N_ROW-1];
   logic [DP_WIDTH-1:0] data_add_s [0:N_ROW-1][0:N_COL-1];
   logic [DP_WIDTH-1:0] data_wdata_s [0:N_ROW-1][0:N_COL-1];
+  logic [RC_CONST_WIDTH-1:0] add_inc_s [0:N_ROW-1][0:N_COL-1];
   logic [DP_WIDTH-1:0] rcs_wdata_s [0:N_COL-1];
 
   logic [  DP_WIDTH-1:0] rcs_res [0:N_ROW-1][0:N_COL-1];
@@ -144,7 +146,6 @@ module cgra_rcs
       begin
         rvalid_demux[j] = '0;
         // for each row
-
         for (int k=0; k<N_ROW; k++) begin
           if (data_req_rvalid_mask[j][k] == 1'b1 && data_wen_s[k][j] == 1'b1 && data_rvalid_i[j] == 1'b1) begin
             rvalid_demux[j][k] = 1'b1;
@@ -231,20 +232,20 @@ module cgra_rcs
           end
         end else begin
           for (int k=0; k<N_ROW; k++) begin
-            if( rcs_pc_e_i[j] == 1'b0 ) begin // PC enable is low
-              if( rvalid_demux[j][k] == 1'b1 ) begin // If the data is ready, copy it to a temproary buffer
+            if (rcs_pc_e_i[j] == 1'b0) begin // PC enable is low
+              if (rvalid_demux[j][k] == 1'b1) begin // If the data is ready, copy it to a temproary buffer
                 rcs_res_reg_temp[k][j]  <= data_rdata_i[j];
                 rcs_flag_reg_temp[k][j] <= {data_rdata_i[j][DP_WIDTH-1], ~(|data_rdata_i[j])};
               end
             end else begin // PC enable is high
-              if( data_req_s[k][j] == 1'b0 ) begin
+              if (data_req_s[k][j] == 1'b0) begin
                 if (rcs_nop_s[k][j] == 1'b0) begin
                   rcs_res_reg[k][j]  <= rcs_res[k][j];
                   rcs_flag_reg[k][j] <= rcs_flag[k][j];
                 end
               end else begin  // Read data instruction
-                if( rcs_nop_s[k][j] == 1'b0  ) begin
-                  if ( rvalid_demux[j][k] == 1'b1) begin // If the data is ready, copy it straight away.
+                if (rcs_nop_s[k][j] == 1'b0) begin
+                  if (rvalid_demux[j][k] == 1'b1) begin // If the data is ready, copy it straight away.
                     rcs_res_reg[k][j]  <= data_rdata_i[j];
                     rcs_flag_reg[k][j] <= {data_rdata_i[j][DP_WIDTH-1], ~(|data_rdata_i[j])};
                   end else begin  // If the data is not ready, it was ready before, so copy the temp buffer.
@@ -268,8 +269,14 @@ module cgra_rcs
         // for each row
         data_add_o[j] = '0; // default value
         for (int k=0; k<N_ROW; k++) begin
-          if (data_req_gnt_mask[j][k] == 1'b1 && data_ind_s[k][j] == 1'b1) begin
-            data_add_o[j] = data_add_s[k][j];
+          if (data_req_gnt_mask[j][k] == 1'b1) begin
+            if (data_ind_s[k][j] == 1'b1) begin
+              // LWI or SWI
+              data_add_o[j] = data_add_s[k][j];
+            end else begin
+              // LWD or SWD
+              add_inc_o[j]  = add_inc_s[k][j];
+            end
             break;
           end
         end
@@ -421,6 +428,7 @@ module cgra_rcs
           .data_ind_o    (       data_ind_s[i  ][j  ] ),
           .data_add_o    (       data_add_s[i  ][j  ] ),
           .data_wdata_o  (     data_wdata_s[i  ][j  ] ),
+          .add_inc_o     (        add_inc_s[i  ][j  ] ),
           .rc_stall_o    (      rcs_stall_s[i  ][j  ] ),
           .rc_nop_o      (        rcs_nop_s[i  ][j  ] ),
           .exec_end_o    (       rcs_ex_end[i  ][j  ] )
diff --git a/hw/vendor/esl_epfl_cgra/rtl/cgra_top.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/cgra_top.sv
similarity index 90%
rename from hw/vendor/esl_epfl_cgra/rtl/cgra_top.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/cgra_top.sv
index 17715f05..8026d435 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/cgra_top.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/cgra_top.sv
@@ -12,14 +12,14 @@ module cgra_top
   input  reg_req_t                       reg_req_i,
   output reg_rsp_t                       reg_rsp_o,
   // AHB Master port
-  output logic [                 MP-1:0] tcdm_req_o,
-  output logic [ DATA_BUS_ADD_WIDTH-1:0] tcdm_add_o [0:MP-1],
-  output logic [                 MP-1:0] tcdm_wen_o,
-  output logic [                  4-1:0] tcdm_be_o [0:MP-1],
-  output logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_wdata_o [0:MP-1],
-  input  logic [                 MP-1:0] tcdm_gnt_i,
-  input  logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_rdata_i [0:MP-1],
-  input  logic [                 MP-1:0] tcdm_r_valid_i,
+  output logic [              N_COL-1:0] tcdm_req_o,
+  output logic [ DATA_BUS_ADD_WIDTH-1:0] tcdm_add_o [0:N_COL-1],
+  output logic [              N_COL-1:0] tcdm_wen_o,
+  output logic [                  4-1:0] tcdm_be_o [0:N_COL-1],
+  output logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_wdata_o [0:N_COL-1],
+  input  logic [              N_COL-1:0] tcdm_gnt_i,
+  input  logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_rdata_i [0:N_COL-1],
+  input  logic [              N_COL-1:0] tcdm_r_valid_i,
   // AHB Slave port
   input  logic                           cm_req_i,
   input  logic [ DATA_BUS_ADD_WIDTH-1:0] cm_add_i,
@@ -36,7 +36,7 @@ module cgra_top
   output logic [  IMEM_N_LINES_LOG2-1:0] cm_addr_o,
   input  logic [        INSTR_WIDTH-1:0] rcs_cmem_rdata_i [0:N_ROW-1],
   // CGRA interrupts
-  output logic [            N_SLOTS-1:0] evt_o
+  output logic                           evt_o
 );
 
   logic [              N_COL-1:0] rcs_data_req_s;
@@ -47,6 +47,7 @@ module cgra_top
   logic [           DP_WIDTH-1:0] rcs_data_rdata_s [0:N_COL-1];
   logic [              N_COL-1:0] rcs_data_gnt_s;
   logic [              N_COL-1:0] rcs_data_rvalid_s;
+  logic [     RC_CONST_WIDTH-1:0] rcs_add_inc_s [0:N_COL-1];
   logic [              N_COL-1:0] data_stall_s ;
   logic [KER_CONF_N_REG_LOG2-1:0] ker_id_req_s;
   logic [              N_COL-1:0] acc_end_s;
@@ -80,7 +81,7 @@ module cgra_top
     if (rst_ni == 1'b0) begin
       cc_count <= 0;
     end else begin
-      if (reg_req_i.valid == 1'b1 && reg_rsp_o.ready == 1'b1 && reg_req_i.addr[N_PERIPH_REGS_LOG2+2-1:2] == CGRA_APB_REG_STATE) begin
+      if (reg_req_i.valid == 1'b1 && reg_rsp_o.ready == 1'b1 && reg_req_i.addr[CGRA_NUM_PERIPH_REG_LOG2+2-1:2] == CGRA_PERIPH_STATUS_REG_OFFSET) begin
         $display("[CGRA] %t : GLOBAL CLOCK-CYCLE COUNTER: %l", $time, cc_count);
       end
       cc_count <= cc_count + 1;
@@ -93,12 +94,12 @@ module cgra_top
   `ifndef VERILATOR
     // Activate the clock of a column when it is active only
     generate
-      for (genvar j=0; j<N_COL; j++) begin : rcs_col_cg_gen
+      for (genvar i=0; i<N_COL; i++) begin : rcs_col_cg_gen
         cgra_clock_gate clk_gate_rcs_col_i (
           .clk_i     ( clk_i ),
           .test_en_i ( 1'b0 ),
-          .en_i      ( rcs_col_e_s[j] ),
-          .clk_o     ( clk_rcs_cg[j] )
+          .en_i      ( rcs_col_e_s[i] ),
+          .clk_o     ( clk_rcs_cg[i] )
         ); 
       end
     endgenerate
@@ -109,10 +110,11 @@ module cgra_top
     // trick to make sure input data and internal clock signal to the CGRA are updated
     // at the same delta cycle. This is not a problem with all simulators. For example,
     // modelsim correctly simulates this design without this trick.
-    assign clk_rcs_cg[0] = clk_i;
-    assign clk_rcs_cg[1] = clk_i;
-    assign clk_rcs_cg[2] = clk_i;
-    assign clk_rcs_cg[3] = clk_i;
+    always_comb begin
+      for (int i=0; i<N_COL; i++) begin : rcs_col_cg_gen
+        assign clk_rcs_cg[i] = clk_i;
+      end
+    end
   `endif
 
 
@@ -185,6 +187,7 @@ module cgra_top
     .data_ind_o       ( rcs_data_ind_s    ),
     .data_add_o       ( rcs_data_add_s    ),
     .data_wdata_o     ( rcs_data_wdata_s  ),
+    .add_inc_o        ( rcs_add_inc_s     ),
     .rcs_br_req_o     ( rcs_br_req_s      ),
     .rcs_br_add_o     ( rcs_br_add_s      ),
     .rcs_stall_o      ( rcs_stall_s       ),
@@ -200,6 +203,7 @@ module cgra_top
     .rcs_data_ind_i    ( rcs_data_ind_s    ),
     .rcs_data_add_i    ( rcs_data_add_s    ),
     .rcs_data_wdata_i  ( rcs_data_wdata_s  ),
+    .rcs_add_inc_i     ( rcs_add_inc_s     ),
     .rd_ptr_i          ( rd_ptr_s          ),
     .wr_ptr_i          ( wr_ptr_s          ),
     .bus_data_gnt_i    ( tcdm_gnt_i        ),
diff --git a/hw/vendor/esl_epfl_cgra/rtl/conf_reg_file.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/conf_reg_file.sv
similarity index 77%
rename from hw/vendor/esl_epfl_cgra/rtl/conf_reg_file.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/conf_reg_file.sv
index c84da438..8676325d 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/conf_reg_file.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/conf_reg_file.sv
@@ -16,16 +16,6 @@ module conf_reg_file
 );
 
   logic [RCS_NUM_CREG-1:0][INSTR_WIDTH-1:0] conf_mem;
-  logic clk_cg, clk_en;
-
-  assign clk_en = we_i && ce_i;
-
-  cgra_clock_gate u_clk_gate (
-    .clk_i     ( clk_i  ),
-    .test_en_i ( 1'b0   ),
-    .en_i      ( clk_en ),
-    .clk_o     ( clk_cg )
-  );
 
   // Read instruction output register
   always_ff @(posedge clk_i)
@@ -38,9 +28,11 @@ module conf_reg_file
   end
 
   // Write instruction to register file
-  always_ff @(posedge clk_cg)
+  always_ff @(posedge clk_i)
   begin
-    conf_mem[global_pc_i] <= instr_i;
+    if (we_i & ce_i) begin
+      conf_mem[global_pc_i] <= instr_i;
+    end
   end
 
 endmodule
diff --git a/hw/vendor/esl_epfl_cgra/rtl/context_memory.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/context_memory.sv
similarity index 91%
rename from hw/vendor/esl_epfl_cgra/rtl/context_memory.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/context_memory.sv
index 6ad8118f..b3f3dd2d 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/context_memory.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/context_memory.sv
@@ -8,7 +8,7 @@ module context_memory
   input  logic                           clk_i,
   input  logic                           rst_ni,
   input  logic                           cm_cg_i,
-  input  logic                           cm_set_retentive_i,
+  input  logic                           cm_set_retentive_ni,
   input  logic [              N_ROW-1:0] cm_row_req_i,
   input  logic                           cm_we_i,
   input  logic [  IMEM_N_LINES_LOG2-1:0] cm_addr_i,
@@ -30,7 +30,7 @@ module context_memory
         .addr_i (cm_addr_i),
         .wdata_i(cm_wdata_i),
         .be_i   (4'b1111),
-        .set_retentive_i (cm_set_retentive_i),
+        .set_retentive_ni (cm_set_retentive_ni),
         // output ports
         .rdata_o(rcs_cmem_rdata_o[j])
       );
diff --git a/hw/vendor/esl_epfl_cgra/rtl/context_memory_decoder.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/context_memory_decoder.sv
similarity index 100%
rename from hw/vendor/esl_epfl_cgra/rtl/context_memory_decoder.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/context_memory_decoder.sv
diff --git a/hw/vendor/esl_epfl_cgra/rtl/data_bus_handler.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/data_bus_handler.sv
similarity index 92%
rename from hw/vendor/esl_epfl_cgra/rtl/data_bus_handler.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/data_bus_handler.sv
index ebd80500..e61f6725 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/data_bus_handler.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/data_bus_handler.sv
@@ -12,10 +12,11 @@ module data_bus_handler
   input  logic [              N_COL-1:0] rcs_data_ind_i,
   input  logic [           DP_WIDTH-1:0] rcs_data_add_i [0:N_COL-1],
   input  logic [           DP_WIDTH-1:0] rcs_data_wdata_i [0:N_COL-1],
+  input  logic [     RC_CONST_WIDTH-1:0] rcs_add_inc_i [0:N_COL-1],
   input  logic [           DP_WIDTH-1:0] rd_ptr_i [0:MAX_COL_REQ-1],
   input  logic [           DP_WIDTH-1:0] wr_ptr_i [0:MAX_COL_REQ-1],
   input  logic [              N_COL-1:0] bus_data_gnt_i,
-  input  logic [DATA_BUS_DATA_WIDTH-1:0] bus_data_rdata_i [0:MP-1],
+  input  logic [DATA_BUS_DATA_WIDTH-1:0] bus_data_rdata_i [0:N_COL-1],
   input  logic [              N_COL-1:0] bus_r_valid_i,
   input  logic [              N_COL-1:0] col_start_i,
   input  logic [              N_COL-1:0] col_conf_ack_i,
@@ -50,6 +51,7 @@ module data_bus_handler
   logic [              N_COL-1:0] data_stall_comb_s;
   // Multi-column kernel: choose correct data pointer
   logic [         N_COL_LOG2-1:0] acc_ack_col_accum;
+  logic [ DATA_BUS_ADD_WIDTH-1:0] rcs_add_inc_sign_ext [0:N_COL-1];
 
   assign data_stall_o     = data_stall_comb_s;
   // Use this version if single-cycle bus access is not possible
@@ -57,6 +59,12 @@ module data_bus_handler
   assign bus_data_add_o   = bus_data_add_s;
   assign bus_data_wen_o   = rcs_data_wen_i;
 
+  always_comb begin : inc_sign_extension_logic
+    for(int k=0; k<N_COL; k++) begin
+      rcs_add_inc_sign_ext[k] = {{(DATA_BUS_ADD_WIDTH-RC_CONST_WIDTH){rcs_add_inc_i[k][RC_CONST_WIDTH-1]}}, rcs_add_inc_i[k][RC_CONST_WIDTH-1:0]};
+    end
+  end
+
   generate
     for(j=0; j<N_COL; j++) begin : data_bus_ctrl_reg_gen
 
@@ -84,7 +92,7 @@ module data_bus_handler
           if (col_start_i[j] == 1'b1) begin
             rd_data_cnt_col[j] <= rd_ptr_i[acc_ack_col_accum];
           end else if (rcs_data_req_i[j] == 1'b1 && rcs_data_wen_i[j] == 1'b1 && rcs_data_ind_i[j] == 1'b0 && ahb_add_success[j] == 1'b1) begin
-            rd_data_cnt_col[j] <= rd_data_cnt_col[j] + 32'h4; // 32b word add increase
+            rd_data_cnt_col[j] <= rd_data_cnt_col[j] + rcs_add_inc_sign_ext[j]; //32'h4; // 32b word add increase
           end
         end
       end
@@ -98,7 +106,7 @@ module data_bus_handler
           if (col_start_i[j] == 1'b1) begin
             wr_data_cnt_col[j] <= wr_ptr_i[acc_ack_col_accum];
           end else if (rcs_data_req_i[j] == 1'b1 && rcs_data_wen_i[j] == 1'b0 && rcs_data_ind_i[j] == 1'b0 && ahb_add_success[j] == 1'b1) begin
-            wr_data_cnt_col[j]  <= wr_data_cnt_col[j] + 32'h4; // 32b word add increase
+            wr_data_cnt_col[j]  <= wr_data_cnt_col[j] + rcs_add_inc_sign_ext[j]; //32'h4; // 32b word add increase
           end
         end
       end
diff --git a/hw/vendor/esl_epfl_cgra/rtl/datapath.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/datapath.sv
similarity index 96%
rename from hw/vendor/esl_epfl_cgra/rtl/datapath.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/datapath.sv
index c2fe2ea7..ddefee30 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/datapath.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/datapath.sv
@@ -31,6 +31,7 @@ module datapath
   output logic                         data_ind_o,
   output logic [         DP_WIDTH-1:0] data_add_o,
   output logic [         DP_WIDTH-1:0] data_wdata_o,
+  output logic [   RC_CONST_WIDTH-1:0] add_inc_o,
   output logic                         dp_stall_o,
   output logic                         rc_nop_o,
   output logic                         exec_end_o
@@ -59,12 +60,13 @@ module datapath
   logic                         data_we_s;
   logic                         data_ind_s;
   logic [         DP_WIDTH-1:0] data_alu_mux;
-  // logic [         DP_WIDTH-1:0] data_rdata_reg;
   logic                         rf_en;
 
-
-  assign flag_o      = alu_flag;
-  // assign result_o    = alu_res;
+  assign flag_o = alu_flag;
+  
+  // The immediate field provide the increment offset for the address for LWD/SWD instruction (post-incrementation)
+  // The value is sign extended to enable incrementing and decrementing the address
+  assign add_inc_o = (alu_op == CGRA_ALU_LWD | alu_op == CGRA_ALU_SWD) ? imm_val : '0;
 
   // Here the configuration word is decoded and fed to the different components
   assign mux_a_sel    = conf_rdata_i[31:28];
diff --git a/hw/vendor/esl_epfl_cgra/rtl/mux.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/mux.sv
similarity index 100%
rename from hw/vendor/esl_epfl_cgra/rtl/mux.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/mux.sv
diff --git a/hw/vendor/esl_epfl_cgra/hw/rtl/peripheral_regs.sv.tpl b/hw/vendor/esl_epfl_cgra/hw/rtl/peripheral_regs.sv.tpl
new file mode 100644
index 00000000..63de9b52
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/peripheral_regs.sv.tpl
@@ -0,0 +1,88 @@
+// Copyright 2022 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+module peripheral_regs
+  import cgra_pkg::*;
+  import reg_pkg::*;
+(
+  input  logic                               clk_i,
+  input  logic                               rst_ni,
+  input  logic                               acc_ack_i,
+  input  logic     [              N_COL-1:0] col_stall_i,
+  input  reg_req_t                           reg_req_i,
+  output reg_rsp_t                           reg_rsp_o,
+  input  logic     [              N_COL-1:0] acc_req_i,
+  input  logic     [              N_COL-1:0] acc_end_i,
+  output logic     [              N_COL-1:0] col_status_o,
+  output logic     [KER_CONF_N_REG_LOG2-1:0] ker_id_o,
+  output logic     [           DP_WIDTH-1:0] rd_ptr_o [0:MAX_COL_REQ-1],
+  output logic     [           DP_WIDTH-1:0] wr_ptr_o [0:MAX_COL_REQ-1]
+);
+
+  import cgra_reg_pkg::*;
+
+  cgra_reg2hw_t reg2hw;
+  cgra_hw2reg_t hw2reg;
+
+  logic [N_COL-1:0] col_status;
+  logic perf_cnt_en;
+  logic perf_cnt_reset;
+
+  assign col_status_o = col_status;
+
+  assign perf_cnt_en    = reg2hw.perf_cnt_enable.q;
+  assign perf_cnt_reset = reg2hw.perf_cnt_reset.q;
+
+
+  // Columns' read and write pointers
+  always_comb
+  begin
+    ker_id_o = reg2hw.kernel_id.q[KER_CONF_N_REG_LOG2-1:0];
+
+% for col in range(cgra_max_columns):
+    rd_ptr_o[${col}] = reg2hw.ptr_in_col_${col}.q;
+    wr_ptr_o[${col}] = reg2hw.ptr_out_col_${col}.q;
+% endfor
+  end
+
+  // Reset/update performance counters
+  assign hw2reg.perf_cnt_total_kernels.de = perf_cnt_reset | (perf_cnt_en & acc_ack_i);
+  assign hw2reg.perf_cnt_total_kernels.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_total_kernels.q + 1;
+
+% for col in range(cgra_num_columns):
+  assign hw2reg.perf_cnt_col_${col}_active_cycles.de = perf_cnt_reset | (perf_cnt_en & (col_status[${col}] | acc_req_i[${col}]));
+  assign hw2reg.perf_cnt_col_${col}_active_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_col_${col}_active_cycles.q + 1;
+  assign hw2reg.perf_cnt_col_${col}_stall_cycles.de  = perf_cnt_reset | (perf_cnt_en & col_stall_i[${col}]);
+  assign hw2reg.perf_cnt_col_${col}_stall_cycles.d   = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_col_${col}_stall_cycles.q + 1;
+% endfor
+
+  // Disable reset
+  assign hw2reg.perf_cnt_reset.de = perf_cnt_reset;
+  assign hw2reg.perf_cnt_reset.d  = '0;
+
+  // Clear kernel ID request
+  assign hw2reg.kernel_id.de = acc_ack_i;
+  assign hw2reg.kernel_id.d  = '0;
+
+  // Update CGRA column status:
+  // 0 - Column is free
+  // 1 - Column is used
+  assign col_status = reg2hw.col_status.q;
+  assign hw2reg.col_status.de = ((|acc_req_i) & acc_ack_i) | (|acc_end_i);
+  assign hw2reg.col_status.d  = ((|acc_req_i) & acc_ack_i) == 1'b1 ? (col_status | acc_req_i) : (col_status & ~acc_end_i);
+
+  cgra_reg_top #(
+      .reg_req_t(reg_req_t),
+      .reg_rsp_t(reg_rsp_t)
+  ) cgra_reg_top_i (
+      .clk_i,
+      .rst_ni,
+      .reg_req_i,
+      .reg_rsp_o,
+      .reg2hw,
+      .hw2reg,
+      .devmode_i(1'b1)
+  );
+
+endmodule
diff --git a/hw/vendor/esl_epfl_cgra/rtl/program_counter.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/program_counter.sv
similarity index 100%
rename from hw/vendor/esl_epfl_cgra/rtl/program_counter.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/program_counter.sv
diff --git a/hw/vendor/esl_epfl_cgra/rtl/reconfigurable_cell.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/reconfigurable_cell.sv
similarity index 66%
rename from hw/vendor/esl_epfl_cgra/rtl/reconfigurable_cell.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/reconfigurable_cell.sv
index e4214b00..2182cb89 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/reconfigurable_cell.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/reconfigurable_cell.sv
@@ -33,6 +33,7 @@ import cgra_pkg::*;
   output logic                         data_ind_o,
   output logic [         DP_WIDTH-1:0] data_add_o,
   output logic [         DP_WIDTH-1:0] data_wdata_o,
+  output logic [   RC_CONST_WIDTH-1:0] add_inc_o,
   output logic                         rc_stall_o,
   output logic                         rc_nop_o,
   output logic                         exec_end_o
@@ -61,35 +62,36 @@ import cgra_pkg::*;
 
   datapath rc_datapath
   (
-    .clk_i         ( clk_i         ),
-    .rst_i         ( rst_rc_i      ),
-    .ce_i          ( ce_dp_s       ),
-    .conf_rdata_i  ( conf_rdata_s  ),
-    .data_rdata_i  ( data_rdata_i  ),
-    .data_rvalid_i ( data_rvalid_i ),
-    .own_res_i     ( own_res_i     ),
-    .left_res_i    ( left_res_i    ),
-    .right_res_i   ( right_res_i   ),
-    .top_res_i     ( top_res_i     ),
-    .bottom_res_i  ( bottom_res_i  ),
-    .own_flag_i    ( own_flag_i    ),
-    .left_flag_i   ( left_flag_i   ),
-    .right_flag_i  ( right_flag_i  ),
-    .top_flag_i    ( top_flag_i    ),
-    .bottom_flag_i ( bottom_flag_i ),
-    .conf_re_i     ( conf_re_i     ),
-    .result_o      ( result_o      ),
-    .flag_o        ( flag_o        ),
-    .br_req_o      ( br_req_o      ),
-    .br_add_o      ( br_add_o      ),
-    .data_req_o    ( data_req_o    ),
-    .data_wen_o    ( data_wen_o    ),
-    .data_ind_o    ( data_ind_o    ),
-    .data_add_o    ( data_add_o    ),
-    .data_wdata_o  ( data_wdata_o  ),
-    .dp_stall_o    ( dp_stall_s    ),
-    .rc_nop_o      ( rc_nop_o      ),
-    .exec_end_o    ( exec_end_o    )
+    .clk_i         ( clk_i          ),
+    .rst_i         ( rst_rc_i       ),
+    .ce_i          ( ce_dp_s        ),
+    .conf_rdata_i  ( conf_rdata_s   ),
+    .data_rdata_i  ( data_rdata_i   ),
+    .data_rvalid_i ( data_rvalid_i  ),
+    .own_res_i     ( own_res_i      ),
+    .left_res_i    ( left_res_i     ),
+    .right_res_i   ( right_res_i    ),
+    .top_res_i     ( top_res_i      ),
+    .bottom_res_i  ( bottom_res_i   ),
+    .own_flag_i    ( own_flag_i     ),
+    .left_flag_i   ( left_flag_i    ),
+    .right_flag_i  ( right_flag_i   ),
+    .top_flag_i    ( top_flag_i     ),
+    .bottom_flag_i ( bottom_flag_i  ),
+    .conf_re_i     ( conf_re_i      ),
+    .result_o      ( result_o       ),
+    .flag_o        ( flag_o         ),
+    .br_req_o      ( br_req_o       ),
+    .br_add_o      ( br_add_o       ),
+    .data_req_o    ( data_req_o     ),
+    .data_wen_o    ( data_wen_o     ),
+    .data_ind_o    ( data_ind_o     ),
+    .data_add_o    ( data_add_o     ),
+    .data_wdata_o  ( data_wdata_o   ),
+    .add_inc_o     ( add_inc_o      ),
+    .dp_stall_o    ( dp_stall_s     ),
+    .rc_nop_o      ( rc_nop_o       ),
+    .exec_end_o    ( exec_end_o     )
   );
 
 endmodule
diff --git a/hw/vendor/esl_epfl_cgra/rtl/reg_file.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/reg_file.sv
similarity index 73%
rename from hw/vendor/esl_epfl_cgra/rtl/reg_file.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/reg_file.sv
index b9c03c0e..b2844bbe 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/reg_file.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/reg_file.sv
@@ -20,25 +20,15 @@ module reg_file
 );
 
   logic [REGFILE_WIDTH-1:0] reg_file_mem [0:REGFILE_DEPTH-1];
-  logic                     clk_cg;
-  logic                     clk_en;
 
   assign regs_o = reg_file_mem;
 
-  assign clk_en = (we_i & ce_i) | rst_i;
-
-  cgra_clock_gate u_clk_gate (
-    .clk_i     ( clk_i  ),
-    .test_en_i ( 1'b0   ),
-    .en_i      ( clk_en ),
-    .clk_o     ( clk_cg )
-  );
-
-  always_ff @(posedge clk_cg)
+  always_ff @(posedge clk_i)
   begin
     if (rst_i == 1'b1) begin
       reg_file_mem <= '{default:'0};
-    end else begin
+    end
+    else if (we_i & ce_i) begin
       reg_file_mem[wsel_i] <= reg_i;
     end
   end
diff --git a/hw/vendor/esl_epfl_cgra/rtl/synchronizer.sv b/hw/vendor/esl_epfl_cgra/hw/rtl/synchronizer.sv
similarity index 57%
rename from hw/vendor/esl_epfl_cgra/rtl/synchronizer.sv
rename to hw/vendor/esl_epfl_cgra/hw/rtl/synchronizer.sv
index 2e97351c..ec2ac262 100644
--- a/hw/vendor/esl_epfl_cgra/rtl/synchronizer.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/rtl/synchronizer.sv
@@ -6,21 +6,21 @@ module synchronizer
   import cgra_pkg::*;
   import reg_pkg::*;
 (
-  input  logic                           clk_i,
-  input  logic                           rst_ni,
-  input  logic                           acc_ack_i,
-  input  logic [              N_COL-1:0] acc_end_i,
-  input  logic [         KMEM_WIDTH-1:0] conf_word_i,
-  input  logic [              N_COL-1:0] col_start_i,
-  input  logic [              N_COL-1:0] col_stall_i,
-  input  reg_req_t                       reg_req_i,
-  output reg_rsp_t                       reg_rsp_o,
-  output logic [              N_COL-1:0] acc_req_o,
-  output logic [KER_CONF_N_REG_LOG2-1:0] ker_id_req_o,
-  output logic [           DP_WIDTH-1:0] rd_ptr_o [0:MAX_COL_REQ-1],
-  output logic [           DP_WIDTH-1:0] wr_ptr_o [0:MAX_COL_REQ-1],
-  output logic [              N_COL-1:0] col_acc_map_o [0:N_COL-1],
-  output logic [            N_SLOTS-1:0] evt_o
+  input  logic                               clk_i,
+  input  logic                               rst_ni,
+  input  logic                               acc_ack_i,
+  input  logic     [              N_COL-1:0] acc_end_i,
+  input  logic     [         KMEM_WIDTH-1:0] conf_word_i,
+  input  logic     [              N_COL-1:0] col_start_i,
+  input  logic     [              N_COL-1:0] col_stall_i,
+  input  reg_req_t                           reg_req_i,
+  output reg_rsp_t                           reg_rsp_o,
+  output logic     [              N_COL-1:0] acc_req_o,
+  output logic     [KER_CONF_N_REG_LOG2-1:0] ker_id_req_o,
+  output logic     [           DP_WIDTH-1:0] rd_ptr_o [0:MAX_COL_REQ-1],
+  output logic     [           DP_WIDTH-1:0] wr_ptr_o [0:MAX_COL_REQ-1],
+  output logic     [              N_COL-1:0] col_acc_map_o [0:N_COL-1],
+  output logic                               evt_o
 );
 
   typedef enum logic [2-1:0] { SYNC_FSM_LOOP_REQ  = 2'b00, 
@@ -31,8 +31,6 @@ module synchronizer
 
   sync_fsm_state_typ sync_fsm_state, sync_fsm_n_state;
 
-  logic                           pending_req_s;
-  logic [       N_SLOTS_LOG2-1:0] req_loop_cnt;
   logic [KER_CONF_N_REG_LOG2-1:0] ker_id_req_s;
   logic [              N_COL-1:0] map_ready [0:N_COL-1];
   logic [              N_COL-1:0] col_map_sel [0:N_COL-1];
@@ -42,15 +40,14 @@ module synchronizer
   logic [KER_CONF_N_REG_LOG2-1:0] conf_w_add_reg;
   logic [              N_COL-1:0] ker_col_req_s;
   logic [              N_COL-1:0] ker_col_req_reg;
-  logic [       N_SLOTS_LOG2-1:0] c_id_exec [0:N_COL-1];
-  logic [KER_CONF_N_REG_LOG2-1:0] core_ker_id_req_s [0:N_SLOTS-1];
   logic [              N_COL-1:0] col_acc_map_reg [0:N_COL-1];
-  logic [           DP_WIDTH-1:0] core_rd_ptr_s [0:N_SLOTS-1][0:MAX_COL_REQ-1];
-  logic [           DP_WIDTH-1:0] core_wr_ptr_s [0:N_SLOTS-1][0:MAX_COL_REQ-1];
+  // logic [           DP_WIDTH-1:0] rd_ptr_s [0:MAX_COL_REQ-1];
+  // logic [           DP_WIDTH-1:0] wr_ptr_s [0:MAX_COL_REQ-1];
 
   genvar j;
 
-  assign ker_id_req_s = core_ker_id_req_s[req_loop_cnt];
+  // Generate an interrupt everytime an acceleration ends
+  assign evt_o = |acc_end_i;
 
   assign ker_id_req_o = conf_w_add_reg;
   assign ker_col_req_s = conf_word_i[KER_N_COL_HB:KER_N_COL_LB];
@@ -78,21 +75,6 @@ module synchronizer
   assign acc_req_o     = acc_req_reg;
   assign col_acc_map_o = col_acc_map_reg;
 
-  ///////////////////////////////////////////////////////////////////////
-  //
-  // Pending request detection logic
-  //
-  ///////////////////////////////////////////////////////////////////////
-  always_comb
-  begin
-
-    pending_req_s = 1'b0;
-    
-    for (int i=0; i<N_SLOTS; i++) begin
-      pending_req_s = pending_req_s|(|core_ker_id_req_s[i]);
-    end
-  end
-
   ///////////////////////////////////////////////////////////////////////
   //
   // Synchronizer FSM
@@ -154,16 +136,11 @@ module synchronizer
   always_ff @(posedge clk_i, negedge rst_ni)
   begin
     if(rst_ni == 1'b0) begin
-      req_loop_cnt    <= '0;
       sync_fsm_state  <= SYNC_FSM_LOOP_REQ;
       conf_w_add_reg  <= '0;
       ker_col_req_reg <= '0;
       acc_req_reg     <= '0;    
     end else begin
-      if (sync_fsm_n_state == SYNC_FSM_LOOP_REQ && pending_req_s == 1'b1) begin
-        req_loop_cnt <= req_loop_cnt + 1;
-      end
-
       sync_fsm_state <= sync_fsm_n_state;
 
       if (sync_fsm_n_state == SYNC_FSM_READ_CONF) begin
@@ -174,10 +151,10 @@ module synchronizer
         ker_col_req_reg <= ker_col_req_s;
       end
 
-      if (sync_fsm_n_state == SYNC_FSM_WAIT_ACK && sync_fsm_state == SYNC_FSM_FIND_COL) begin
-        rd_ptr_o <= core_rd_ptr_s[req_loop_cnt];
-        wr_ptr_o <= core_wr_ptr_s[req_loop_cnt];
-      end
+      // if (sync_fsm_n_state == SYNC_FSM_WAIT_ACK && sync_fsm_state == SYNC_FSM_FIND_COL) begin
+      //   rd_ptr_o <= rd_ptr_s;
+      //   wr_ptr_o <= wr_ptr_s;
+      // end
 
       if (sync_fsm_n_state == SYNC_FSM_WAIT_ACK && sync_fsm_state == SYNC_FSM_FIND_COL) begin
         acc_req_reg <= acc_req_mapped;
@@ -203,42 +180,6 @@ module synchronizer
     end
   endgenerate
 
-  ///////////////////////////////////////////////////////////////////////
-  //
-  // Process to keep update the col status (if running or finished)
-  //
-  ///////////////////////////////////////////////////////////////////////
-
-  always_ff @(posedge clk_i, negedge rst_ni)
-  begin
-    if(rst_ni == 1'b0) begin
-      c_id_exec <= '{default: '0};
-    end else begin
-      for (int i=0; i<N_COL; i++) begin : sync_status
-        if (acc_req_reg[i] == 1'b1) begin
-          c_id_exec[i] <= req_loop_cnt;
-        end
-      end
-    end
-  end
-
-  ///////////////////////////////////////////////////////////////////////
-  //
-  // Process to wake up correct core  when CGRA finished its execution
-  //
-  ///////////////////////////////////////////////////////////////////////
-
-  always_comb
-  begin
-    evt_o = '0;
-
-    for (int i=0; i<N_SLOTS; i++) begin : evt_out
-      if (acc_end_i[i] == 1'b1) begin
-        evt_o[c_id_exec[i]] = 1'b1;
-      end
-    end
-  end
-
   ////////////////////////////////////////////////////////////////////////
   //
   // Component(s) mapping
@@ -247,19 +188,18 @@ module synchronizer
 
   peripheral_regs peripheral_regs_i
   (
-    .clk_i              ( clk_i              ),
-    .rst_ni             ( rst_ni             ),
-    .acc_ack_i          ( acc_ack_i          ),
-    .c_id_req_clear_i   ( req_loop_cnt       ),
-    .col_stall_i        ( col_stall_i        ),
-    .reg_req_i          ( reg_req_i          ),
-    .acc_req_i          ( acc_req_reg        ),
-    .acc_end_i          ( acc_end_i          ),
-    .col_status_o       ( col_status_reg     ),
-    .reg_rsp_o          ( reg_rsp_o          ),
-    .core_ker_id_o      ( core_ker_id_req_s  ),
-    .core_rd_ptr_o      ( core_rd_ptr_s      ),
-    .core_wr_ptr_o      ( core_wr_ptr_s      )
+    .clk_i        ( clk_i          ),
+    .rst_ni       ( rst_ni         ),
+    .acc_ack_i    ( acc_ack_i      ),
+    .col_stall_i  ( col_stall_i    ),
+    .reg_req_i    ( reg_req_i      ),
+    .acc_req_i    ( acc_req_reg    ),
+    .acc_end_i    ( acc_end_i      ),
+    .col_status_o ( col_status_reg ),
+    .reg_rsp_o    ( reg_rsp_o      ),
+    .ker_id_o     ( ker_id_req_s   ),
+    .rd_ptr_o     ( rd_ptr_o       ),
+    .wr_ptr_o     ( wr_ptr_o       )
   );
 
 endmodule
diff --git a/hw/vendor/esl_epfl_cgra/wrapper/cgra_top_wrapper.sv b/hw/vendor/esl_epfl_cgra/hw/wrapper/cgra_top_wrapper.sv
similarity index 57%
rename from hw/vendor/esl_epfl_cgra/wrapper/cgra_top_wrapper.sv
rename to hw/vendor/esl_epfl_cgra/hw/wrapper/cgra_top_wrapper.sv
index 5498e21f..0168a013 100644
--- a/hw/vendor/esl_epfl_cgra/wrapper/cgra_top_wrapper.sv
+++ b/hw/vendor/esl_epfl_cgra/hw/wrapper/cgra_top_wrapper.sv
@@ -7,34 +7,34 @@ module cgra_top_wrapper
   import obi_pkg::*;
   import reg_pkg::*;
 (
-  input  logic               clk_i,
-  input  logic               rst_ni,
-  input  logic               rst_logic_ni,
+  input  logic                  clk_i,
+  input  logic                  rst_ni,
+  input  logic                  rst_logic_ni,
   // Top level clock gating unit enable
-  input  logic               cgra_enable_i,
+  input  logic                  cgra_enable_i,
   // AHB Masters
-  output obi_req_t  [4-1:0] masters_req_o,
-  input  obi_resp_t [4-1:0] masters_resp_i,
+  output obi_req_t  [N_COL-1:0] masters_req_o,
+  input  obi_resp_t [N_COL-1:0] masters_resp_i,
   // APB interface
-  input  reg_req_t           reg_req_i,
-  output reg_rsp_t           reg_rsp_o,
+  input  reg_req_t              reg_req_i,
+  output reg_rsp_t              reg_rsp_o,
   // AHB Slave (Context memory)
-  input  obi_req_t           slave_req_i,
-  output obi_resp_t          slave_resp_o,
+  input  obi_req_t              slave_req_i,
+  output obi_resp_t             slave_resp_o,
   // Set configuration memory in retentive mode
-  input  logic               cmem_set_retentive_i,
+  input  logic                  cmem_set_retentive_ni,
   // interrupt
-  output logic               cgra_int_o
+  output logic                  cgra_int_o
 );
 
-  logic [                 MP-1:0] tcdm_req;
-  logic [ DATA_BUS_ADD_WIDTH-1:0] tcdm_add [0:MP-1];
-  logic [                 MP-1:0] tcdm_wen;
-  logic [                  4-1:0] tcdm_be [0:MP-1];
-  logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_wdata [0:MP-1];
-  logic [                 MP-1:0] tcdm_gnt;
-  logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_rdata [0:MP-1];
-  logic [                 MP-1:0] tcdm_r_valid;
+  logic [              N_COL-1:0] tcdm_req;
+  logic [ DATA_BUS_ADD_WIDTH-1:0] tcdm_add [0:N_COL-1];
+  logic [              N_COL-1:0] tcdm_wen;
+  logic [                  4-1:0] tcdm_be [0:N_COL-1];
+  logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_wdata [0:N_COL-1];
+  logic [              N_COL-1:0] tcdm_gnt;
+  logic [DATA_BUS_DATA_WIDTH-1:0] tcdm_rdata [0:N_COL-1];
+  logic [              N_COL-1:0] tcdm_r_valid;
 
   logic                           cm_req;
   logic [ DATA_BUS_ADD_WIDTH-1:0] cm_add;
@@ -45,7 +45,7 @@ module cgra_top_wrapper
   logic [DATA_BUS_DATA_WIDTH-1:0] cm_rdata;
   logic                           cm_rvalid;
 
-  logic [            N_SLOTS-1:0] cgra_evt;
+  logic                           cgra_evt;
 
   // Context memory decoder to actual SRAM macro
   logic [              N_ROW-1:0] cm_row_req_s;
@@ -53,36 +53,22 @@ module cgra_top_wrapper
   logic [  IMEM_N_LINES_LOG2-1:0] cm_addr_s;
   logic [        INSTR_WIDTH-1:0] rcs_cmem_rdata_s [0:N_ROW-1];
 
-    generate
-      // One master port per column
-      for (genvar j=0; j<N_COL; j++) begin : master_port_used
-        always_comb
-        begin
-          masters_req_o[j].req   = tcdm_req[j];
-          masters_req_o[j].addr  = tcdm_add[j];
-          masters_req_o[j].we    = ~tcdm_wen[j];
-          masters_req_o[j].be    = tcdm_be[j];
-          masters_req_o[j].wdata = tcdm_wdata[j];
-          tcdm_gnt[j]            = masters_resp_i[j].gnt;
-          tcdm_rdata[j]          = masters_resp_i[j].rdata;
-          tcdm_r_valid[j]        = masters_resp_i[j].rvalid;
-        end
+  generate
+    // One master port per column
+    for (genvar j=0; j<N_COL; j++) begin : master_port_interface
+      always_comb
+      begin
+        masters_req_o[j].req   = tcdm_req[j];
+        masters_req_o[j].addr  = tcdm_add[j];
+        masters_req_o[j].we    = ~tcdm_wen[j];
+        masters_req_o[j].be    = tcdm_be[j];
+        masters_req_o[j].wdata = tcdm_wdata[j];
+        tcdm_gnt[j]            = masters_resp_i[j].gnt;
+        tcdm_rdata[j]          = masters_resp_i[j].rdata;
+        tcdm_r_valid[j]        = masters_resp_i[j].rvalid;
       end
-    endgenerate
-
-    generate
-      // Keep heepocrates default setting to 4 master ports and don't use the extra one
-      for (genvar j=N_COL; j<4; j++) begin : master_port_unused
-        always_comb
-        begin
-          masters_req_o[j].req   = '0;
-          masters_req_o[j].addr  = '0;
-          masters_req_o[j].we    = '0;
-          masters_req_o[j].be    = '0;
-          masters_req_o[j].wdata = '0;
-        end
-      end
-    endgenerate
+    end
+  endgenerate
 
   // Context memory slave
   assign slave_resp_o.gnt    = cm_gnt;
@@ -95,7 +81,7 @@ module cgra_top_wrapper
   assign cm_wdata            = slave_req_i.wdata;
   
   // all request merged for now
-  assign cgra_int_o = |cgra_evt;
+  assign cgra_int_o = cgra_evt;
 
   // No actual need to read this memory so only cgra_ram0 is connected for read
   assign cm_rdata = rcs_cmem_rdata_s[0];
@@ -154,15 +140,15 @@ module cgra_top_wrapper
 
   context_memory cgra_context_memory_i
   (
-    .clk_i              ( clk_i                ),
-    .rst_ni             ( rst_ni               ),
-    .cm_cg_i            ( clk_mem_cg           ),
-    .cm_set_retentive_i ( cmem_set_retentive_i ),
-    .cm_row_req_i       ( cm_row_req_s         ),
-    .cm_we_i            ( cm_we_s              ),
-    .cm_addr_i          ( cm_addr_s            ),
-    .cm_wdata_i         ( cm_wdata             ),
-    .rcs_cmem_rdata_o   ( rcs_cmem_rdata_s     )
+    .clk_i               ( clk_i                 ),
+    .rst_ni              ( rst_ni                ),
+    .cm_cg_i             ( clk_mem_cg            ),
+    .cm_set_retentive_ni ( cmem_set_retentive_ni ),
+    .cm_row_req_i        ( cm_row_req_s          ),
+    .cm_we_i             ( cm_we_s               ),
+    .cm_addr_i           ( cm_addr_s             ),
+    .cm_wdata_i          ( cm_wdata              ),
+    .rcs_cmem_rdata_o    ( rcs_cmem_rdata_s      )
   );
 
 endmodule
diff --git a/hw/vendor/esl_epfl_cgra/lint/cgra.vlt b/hw/vendor/esl_epfl_cgra/lint/cgra.vlt
index 2be7b410..134e1afb 100644
--- a/hw/vendor/esl_epfl_cgra/lint/cgra.vlt
+++ b/hw/vendor/esl_epfl_cgra/lint/cgra.vlt
@@ -5,56 +5,58 @@
 `verilator_config
 
 // clk_i is indeed not used but kept for potential use
-lint_off -rule UNUSED    -file "*esl_epfl_cgra/rtl/context_memory.sv" -match "Signal is not used: 'clk_i'"
+lint_off -rule UNUSED    -file "*esl_epfl_cgra/hw/rtl/context_memory.sv" -match "Signal is not used: 'clk_i'"
 
 // cgra_reg_top.sv is generated by regtool and kept as it is to avoid manually update it whenever the file is generated
-lint_off -rule WIDTH     -file "*esl_epfl_cgra/rtl/cgra_reg_top.sv" -match "Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits."
+lint_off -rule WIDTH     -file "*esl_epfl_cgra/hw/rtl/cgra_reg_top.sv" -match "Operator ASSIGNW expects *"
 
 // Minus index are used to create RCs interconnection, which trigger these warnings
-lint_off -rule LITENDIAN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Little bit endian vector: left < right of bit range: [-1:4]*"
+lint_off -rule LITENDIAN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Little bit endian vector: left < right of bit range: *"
 
 // Some bits are indeed not used but full width is kept for concise code
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/synchronizer.sv" -match "Bits of signal are not used: 'conf_word_i'[11:0]"
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/cgra_controller.sv" -match "Bits of signal are not used: 'kmem_rdata_i'[15:12]"
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/context_memory_decoder.sv" -match "Bits of signal are not used: 'cm_add_i'[31:12,1:0]"
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/context_memory_decoder.sv" -match "Bits of signal are not used: 'cm_wdata_i'[31:16]"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/synchronizer.sv" -match "Bits of signal are not used: 'conf_word_i'*"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/cgra_controller.sv" -match "Bits of signal are not used: 'kmem_rdata_i'*"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/context_memory_decoder.sv" -match "Bits of signal are not used: 'cm_add_i'*"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/context_memory_decoder.sv" -match "Bits of signal are not used: 'cm_wdata_i'*"
 
 // For loop variable (32 bits) compared with an actual signal
-lint_off -rule WIDTH  -file "*esl_epfl_cgra/rtl/context_memory_decoder.sv" -match "Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'bk_sel' generates 3 bits."
+lint_off -rule WIDTH  -file "*esl_epfl_cgra/hw/rtl/context_memory_decoder.sv" -match "Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'bk_sel' generates *"
 
 // Clock gating unit used for RTL simulator only
 lint_off -rule UNOPTFLAT -file "*esl_epfl_cgra/sim/cgra_clock_gate.sv" -match "Signal unoptimizable: Feedback to clock or circular logic*"
 
 // Signal is kept to have the full interface signal with bus interconnection
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/context_memory_decoder.sv" -match "Signal is not used: 'cm_be_i'"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/context_memory_decoder.sv" -match "Signal is not used: 'cm_be_i'"
 
 // Signal is not used by the sim wrapper for sram but can be used with a memory macro that enable retention
-lint_off -rule UNUSED -file "*esl_epfl_cgra/sim/cgra_sram_wrapper.sv" -match "Signal is not used: 'set_retentive_i'"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/sim/cgra_sram_wrapper.sv" -match "Signal is not used: 'set_retentive_ni'"
 
 // There are 2 unused registers for now
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/peripheral_regs.sv" -match "Bits of signal are not used: 'reg2hw'[63:0]"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/peripheral_regs.sv" -match "Bits of signal are not used: 'reg2hw'[63:0]"
 
 // Bit 33 is for overflow and bit 0 is used for rounding during fixed-point multiplication
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/alu.sv" -match "Bits of signal are not used: 'adder_result_full'[33,0]"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signal are not used: 'adder_result_full'[33,0]"
 
 // Bit 0 is used for rounding during fixed-point multiplication
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/alu.sv" -match "Bits of signal are not used: 'fxp_mult_scaled'[0]"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signal are not used: 'fxp_mult_scaled'[0]"
 
 // Only the lowest 32 bits are kept for standard multiplication and bits [46:14] for fixed-point multiplication
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/alu.sv" -match "Bits of signal are not used: 'mult_result_full'[63:47]"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signal are not used: 'mult_result_full'[63:47]"
 
 // Extra bit used for right arithmetic shift
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/alu.sv" -match "Bits of signal are not used: 'shift_right_result_33b'[32]"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/alu.sv" -match "Bits of signal are not used: 'shift_right_result_33b'[32]"
 
 // The tool detect multiple drivers at the same line of code (the tool does not interpret the for loop correctly?)
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.gnt_mask'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rvalid_mask'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg_temp'*"
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.gnt_mask'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rvalid_mask'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_res_reg_temp'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
 
-lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.cgra_x_heep_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
+lint_off -rule MULTIDRIVEN -file "*esl_epfl_cgra/hw/rtl/cgra_rcs.sv" -match "Signal has multiple driving blocks with different clocking: 'testharness.heepsilon_top_i.cgra_top_wrapper_i.cgra_top_i.cgra_rcs_i.rcs_flag_reg_temp'*"
 
 // Remove clock gating instance for verilator simulation otherwise sim is failing (verilator v4.2)
-lint_off -rule UNUSED -file "*esl_epfl_cgra/rtl/cgra_top.sv" -match "Signal is not used: 'rcs_col_e_s'"
+lint_off -rule UNUSED -file "*esl_epfl_cgra/hw/rtl/cgra_top.sv" -match "Signal is not used: 'rcs_col_e_s'"
+
+lint_off -rule WIDTH -file "*esl_epfl_cgra/hw/rtl/data_bus_handler.sv" -match "Operator ADD expects *"
diff --git a/hw/vendor/esl_epfl_cgra/rtl/cgra_reg_pkg.sv b/hw/vendor/esl_epfl_cgra/rtl/cgra_reg_pkg.sv
deleted file mode 100644
index 4a326a5c..00000000
--- a/hw/vendor/esl_epfl_cgra/rtl/cgra_reg_pkg.sv
+++ /dev/null
@@ -1,369 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Register Package auto-generated by `reggen` containing data structure
-
-package cgra_reg_pkg;
-
-  // Address widths within the block
-  parameter int BlockAw = 7;
-
-  ////////////////////////////
-  // Typedefs for registers //
-  ////////////////////////////
-
-  typedef struct packed {
-    logic [3:0]  q;
-  } cgra_reg2hw_col_status_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ker_id_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ker_id_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_in_c0_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_out_c0_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_in_c1_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_out_c1_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_in_c2_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_out_c2_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_in_c3_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot0_ptr_out_c3_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_in_c0_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_out_c0_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_in_c1_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_out_c1_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_in_c2_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_out_c2_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_in_c3_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_slot1_ptr_out_c3_reg_t;
-
-  typedef struct packed {
-    logic        q;
-  } cgra_reg2hw_perf_cnt_enable_reg_t;
-
-  typedef struct packed {
-    logic        q;
-  } cgra_reg2hw_perf_cnt_reset_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_total_kernels_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c0_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c0_stall_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c1_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c1_stall_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c2_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c2_stall_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c3_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_perf_cnt_c3_stall_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_reserved30_reg_t;
-
-  typedef struct packed {
-    logic [31:0] q;
-  } cgra_reg2hw_reserved31_reg_t;
-
-  typedef struct packed {
-    logic [3:0]  d;
-    logic        de;
-  } cgra_hw2reg_col_status_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_slot0_ker_id_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_slot1_ker_id_reg_t;
-
-  typedef struct packed {
-    logic        d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_reset_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_total_kernels_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c0_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c0_stall_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c1_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c1_stall_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c2_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c2_stall_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c3_active_cycles_reg_t;
-
-  typedef struct packed {
-    logic [31:0] d;
-    logic        de;
-  } cgra_hw2reg_perf_cnt_c3_stall_cycles_reg_t;
-
-  // Register -> HW type
-  typedef struct packed {
-    cgra_reg2hw_col_status_reg_t col_status; // [933:930]
-    cgra_reg2hw_slot0_ker_id_reg_t slot0_ker_id; // [929:898]
-    cgra_reg2hw_slot1_ker_id_reg_t slot1_ker_id; // [897:866]
-    cgra_reg2hw_slot0_ptr_in_c0_reg_t slot0_ptr_in_c0; // [865:834]
-    cgra_reg2hw_slot0_ptr_out_c0_reg_t slot0_ptr_out_c0; // [833:802]
-    cgra_reg2hw_slot0_ptr_in_c1_reg_t slot0_ptr_in_c1; // [801:770]
-    cgra_reg2hw_slot0_ptr_out_c1_reg_t slot0_ptr_out_c1; // [769:738]
-    cgra_reg2hw_slot0_ptr_in_c2_reg_t slot0_ptr_in_c2; // [737:706]
-    cgra_reg2hw_slot0_ptr_out_c2_reg_t slot0_ptr_out_c2; // [705:674]
-    cgra_reg2hw_slot0_ptr_in_c3_reg_t slot0_ptr_in_c3; // [673:642]
-    cgra_reg2hw_slot0_ptr_out_c3_reg_t slot0_ptr_out_c3; // [641:610]
-    cgra_reg2hw_slot1_ptr_in_c0_reg_t slot1_ptr_in_c0; // [609:578]
-    cgra_reg2hw_slot1_ptr_out_c0_reg_t slot1_ptr_out_c0; // [577:546]
-    cgra_reg2hw_slot1_ptr_in_c1_reg_t slot1_ptr_in_c1; // [545:514]
-    cgra_reg2hw_slot1_ptr_out_c1_reg_t slot1_ptr_out_c1; // [513:482]
-    cgra_reg2hw_slot1_ptr_in_c2_reg_t slot1_ptr_in_c2; // [481:450]
-    cgra_reg2hw_slot1_ptr_out_c2_reg_t slot1_ptr_out_c2; // [449:418]
-    cgra_reg2hw_slot1_ptr_in_c3_reg_t slot1_ptr_in_c3; // [417:386]
-    cgra_reg2hw_slot1_ptr_out_c3_reg_t slot1_ptr_out_c3; // [385:354]
-    cgra_reg2hw_perf_cnt_enable_reg_t perf_cnt_enable; // [353:353]
-    cgra_reg2hw_perf_cnt_reset_reg_t perf_cnt_reset; // [352:352]
-    cgra_reg2hw_perf_cnt_total_kernels_reg_t perf_cnt_total_kernels; // [351:320]
-    cgra_reg2hw_perf_cnt_c0_active_cycles_reg_t perf_cnt_c0_active_cycles; // [319:288]
-    cgra_reg2hw_perf_cnt_c0_stall_cycles_reg_t perf_cnt_c0_stall_cycles; // [287:256]
-    cgra_reg2hw_perf_cnt_c1_active_cycles_reg_t perf_cnt_c1_active_cycles; // [255:224]
-    cgra_reg2hw_perf_cnt_c1_stall_cycles_reg_t perf_cnt_c1_stall_cycles; // [223:192]
-    cgra_reg2hw_perf_cnt_c2_active_cycles_reg_t perf_cnt_c2_active_cycles; // [191:160]
-    cgra_reg2hw_perf_cnt_c2_stall_cycles_reg_t perf_cnt_c2_stall_cycles; // [159:128]
-    cgra_reg2hw_perf_cnt_c3_active_cycles_reg_t perf_cnt_c3_active_cycles; // [127:96]
-    cgra_reg2hw_perf_cnt_c3_stall_cycles_reg_t perf_cnt_c3_stall_cycles; // [95:64]
-    cgra_reg2hw_reserved30_reg_t reserved30; // [63:32]
-    cgra_reg2hw_reserved31_reg_t reserved31; // [31:0]
-  } cgra_reg2hw_t;
-
-  // HW -> register type
-  typedef struct packed {
-    cgra_hw2reg_col_status_reg_t col_status; // [369:365]
-    cgra_hw2reg_slot0_ker_id_reg_t slot0_ker_id; // [364:332]
-    cgra_hw2reg_slot1_ker_id_reg_t slot1_ker_id; // [331:299]
-    cgra_hw2reg_perf_cnt_reset_reg_t perf_cnt_reset; // [298:297]
-    cgra_hw2reg_perf_cnt_total_kernels_reg_t perf_cnt_total_kernels; // [296:264]
-    cgra_hw2reg_perf_cnt_c0_active_cycles_reg_t perf_cnt_c0_active_cycles; // [263:231]
-    cgra_hw2reg_perf_cnt_c0_stall_cycles_reg_t perf_cnt_c0_stall_cycles; // [230:198]
-    cgra_hw2reg_perf_cnt_c1_active_cycles_reg_t perf_cnt_c1_active_cycles; // [197:165]
-    cgra_hw2reg_perf_cnt_c1_stall_cycles_reg_t perf_cnt_c1_stall_cycles; // [164:132]
-    cgra_hw2reg_perf_cnt_c2_active_cycles_reg_t perf_cnt_c2_active_cycles; // [131:99]
-    cgra_hw2reg_perf_cnt_c2_stall_cycles_reg_t perf_cnt_c2_stall_cycles; // [98:66]
-    cgra_hw2reg_perf_cnt_c3_active_cycles_reg_t perf_cnt_c3_active_cycles; // [65:33]
-    cgra_hw2reg_perf_cnt_c3_stall_cycles_reg_t perf_cnt_c3_stall_cycles; // [32:0]
-  } cgra_hw2reg_t;
-
-  // Register offsets
-  parameter logic [BlockAw-1:0] CGRA_COL_STATUS_OFFSET = 7'h 0;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_KER_ID_OFFSET = 7'h 4;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_KER_ID_OFFSET = 7'h 8;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_IN_C0_OFFSET = 7'h c;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_OUT_C0_OFFSET = 7'h 10;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_IN_C1_OFFSET = 7'h 14;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_OUT_C1_OFFSET = 7'h 18;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_IN_C2_OFFSET = 7'h 1c;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_OUT_C2_OFFSET = 7'h 20;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_IN_C3_OFFSET = 7'h 24;
-  parameter logic [BlockAw-1:0] CGRA_SLOT0_PTR_OUT_C3_OFFSET = 7'h 28;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_IN_C0_OFFSET = 7'h 2c;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_OUT_C0_OFFSET = 7'h 30;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_IN_C1_OFFSET = 7'h 34;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_OUT_C1_OFFSET = 7'h 38;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_IN_C2_OFFSET = 7'h 3c;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_OUT_C2_OFFSET = 7'h 40;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_IN_C3_OFFSET = 7'h 44;
-  parameter logic [BlockAw-1:0] CGRA_SLOT1_PTR_OUT_C3_OFFSET = 7'h 48;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_ENABLE_OFFSET = 7'h 4c;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_RESET_OFFSET = 7'h 50;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_TOTAL_KERNELS_OFFSET = 7'h 54;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C0_ACTIVE_CYCLES_OFFSET = 7'h 58;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C0_STALL_CYCLES_OFFSET = 7'h 5c;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C1_ACTIVE_CYCLES_OFFSET = 7'h 60;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C1_STALL_CYCLES_OFFSET = 7'h 64;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C2_ACTIVE_CYCLES_OFFSET = 7'h 68;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C2_STALL_CYCLES_OFFSET = 7'h 6c;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C3_ACTIVE_CYCLES_OFFSET = 7'h 70;
-  parameter logic [BlockAw-1:0] CGRA_PERF_CNT_C3_STALL_CYCLES_OFFSET = 7'h 74;
-  parameter logic [BlockAw-1:0] CGRA_RESERVED30_OFFSET = 7'h 78;
-  parameter logic [BlockAw-1:0] CGRA_RESERVED31_OFFSET = 7'h 7c;
-
-  // Register index
-  typedef enum int {
-    CGRA_COL_STATUS,
-    CGRA_SLOT0_KER_ID,
-    CGRA_SLOT1_KER_ID,
-    CGRA_SLOT0_PTR_IN_C0,
-    CGRA_SLOT0_PTR_OUT_C0,
-    CGRA_SLOT0_PTR_IN_C1,
-    CGRA_SLOT0_PTR_OUT_C1,
-    CGRA_SLOT0_PTR_IN_C2,
-    CGRA_SLOT0_PTR_OUT_C2,
-    CGRA_SLOT0_PTR_IN_C3,
-    CGRA_SLOT0_PTR_OUT_C3,
-    CGRA_SLOT1_PTR_IN_C0,
-    CGRA_SLOT1_PTR_OUT_C0,
-    CGRA_SLOT1_PTR_IN_C1,
-    CGRA_SLOT1_PTR_OUT_C1,
-    CGRA_SLOT1_PTR_IN_C2,
-    CGRA_SLOT1_PTR_OUT_C2,
-    CGRA_SLOT1_PTR_IN_C3,
-    CGRA_SLOT1_PTR_OUT_C3,
-    CGRA_PERF_CNT_ENABLE,
-    CGRA_PERF_CNT_RESET,
-    CGRA_PERF_CNT_TOTAL_KERNELS,
-    CGRA_PERF_CNT_C0_ACTIVE_CYCLES,
-    CGRA_PERF_CNT_C0_STALL_CYCLES,
-    CGRA_PERF_CNT_C1_ACTIVE_CYCLES,
-    CGRA_PERF_CNT_C1_STALL_CYCLES,
-    CGRA_PERF_CNT_C2_ACTIVE_CYCLES,
-    CGRA_PERF_CNT_C2_STALL_CYCLES,
-    CGRA_PERF_CNT_C3_ACTIVE_CYCLES,
-    CGRA_PERF_CNT_C3_STALL_CYCLES,
-    CGRA_RESERVED30,
-    CGRA_RESERVED31
-  } cgra_id_e;
-
-  // Register width information to check illegal writes
-  parameter logic [3:0] CGRA_PERMIT [32] = '{
-    4'b 0001, // index[ 0] CGRA_COL_STATUS
-    4'b 1111, // index[ 1] CGRA_SLOT0_KER_ID
-    4'b 1111, // index[ 2] CGRA_SLOT1_KER_ID
-    4'b 1111, // index[ 3] CGRA_SLOT0_PTR_IN_C0
-    4'b 1111, // index[ 4] CGRA_SLOT0_PTR_OUT_C0
-    4'b 1111, // index[ 5] CGRA_SLOT0_PTR_IN_C1
-    4'b 1111, // index[ 6] CGRA_SLOT0_PTR_OUT_C1
-    4'b 1111, // index[ 7] CGRA_SLOT0_PTR_IN_C2
-    4'b 1111, // index[ 8] CGRA_SLOT0_PTR_OUT_C2
-    4'b 1111, // index[ 9] CGRA_SLOT0_PTR_IN_C3
-    4'b 1111, // index[10] CGRA_SLOT0_PTR_OUT_C3
-    4'b 1111, // index[11] CGRA_SLOT1_PTR_IN_C0
-    4'b 1111, // index[12] CGRA_SLOT1_PTR_OUT_C0
-    4'b 1111, // index[13] CGRA_SLOT1_PTR_IN_C1
-    4'b 1111, // index[14] CGRA_SLOT1_PTR_OUT_C1
-    4'b 1111, // index[15] CGRA_SLOT1_PTR_IN_C2
-    4'b 1111, // index[16] CGRA_SLOT1_PTR_OUT_C2
-    4'b 1111, // index[17] CGRA_SLOT1_PTR_IN_C3
-    4'b 1111, // index[18] CGRA_SLOT1_PTR_OUT_C3
-    4'b 0001, // index[19] CGRA_PERF_CNT_ENABLE
-    4'b 0001, // index[20] CGRA_PERF_CNT_RESET
-    4'b 1111, // index[21] CGRA_PERF_CNT_TOTAL_KERNELS
-    4'b 1111, // index[22] CGRA_PERF_CNT_C0_ACTIVE_CYCLES
-    4'b 1111, // index[23] CGRA_PERF_CNT_C0_STALL_CYCLES
-    4'b 1111, // index[24] CGRA_PERF_CNT_C1_ACTIVE_CYCLES
-    4'b 1111, // index[25] CGRA_PERF_CNT_C1_STALL_CYCLES
-    4'b 1111, // index[26] CGRA_PERF_CNT_C2_ACTIVE_CYCLES
-    4'b 1111, // index[27] CGRA_PERF_CNT_C2_STALL_CYCLES
-    4'b 1111, // index[28] CGRA_PERF_CNT_C3_ACTIVE_CYCLES
-    4'b 1111, // index[29] CGRA_PERF_CNT_C3_STALL_CYCLES
-    4'b 1111, // index[30] CGRA_RESERVED30
-    4'b 1111  // index[31] CGRA_RESERVED31
-  };
-
-endpackage
-
diff --git a/hw/vendor/esl_epfl_cgra/rtl/cgra_reg_top.sv b/hw/vendor/esl_epfl_cgra/rtl/cgra_reg_top.sv
deleted file mode 100644
index ebd8614e..00000000
--- a/hw/vendor/esl_epfl_cgra/rtl/cgra_reg_top.sv
+++ /dev/null
@@ -1,1339 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Register Top module auto-generated by `reggen`
-
-
-`include "common_cells/assertions.svh"
-
-module cgra_reg_top #(
-    parameter type reg_req_t = logic,
-    parameter type reg_rsp_t = logic,
-    parameter int AW = 7
-) (
-  input clk_i,
-  input rst_ni,
-  input  reg_req_t reg_req_i,
-  output reg_rsp_t reg_rsp_o,
-  // To HW
-  output cgra_reg_pkg::cgra_reg2hw_t reg2hw, // Write
-  input  cgra_reg_pkg::cgra_hw2reg_t hw2reg, // Read
-
-
-  // Config
-  input devmode_i // If 1, explicit error return for unmapped register access
-);
-
-  import cgra_reg_pkg::* ;
-
-  localparam int DW = 32;
-  localparam int DBW = DW/8;                    // Byte Width
-
-  // register signals
-  logic           reg_we;
-  logic           reg_re;
-  logic [AW-1:0]  reg_addr;
-  logic [DW-1:0]  reg_wdata;
-  logic [DBW-1:0] reg_be;
-  logic [DW-1:0]  reg_rdata;
-  logic           reg_error;
-
-  logic          addrmiss, wr_err;
-
-  logic [DW-1:0] reg_rdata_next;
-
-  // Below register interface can be changed
-  reg_req_t  reg_intf_req;
-  reg_rsp_t  reg_intf_rsp;
-
-
-  assign reg_intf_req = reg_req_i;
-  assign reg_rsp_o = reg_intf_rsp;
-
-
-  assign reg_we = reg_intf_req.valid & reg_intf_req.write;
-  assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
-  assign reg_addr = reg_intf_req.addr;
-  assign reg_wdata = reg_intf_req.wdata;
-  assign reg_be = reg_intf_req.wstrb;
-  assign reg_intf_rsp.rdata = reg_rdata;
-  assign reg_intf_rsp.error = reg_error;
-  assign reg_intf_rsp.ready = 1'b1;
-
-  assign reg_rdata = reg_rdata_next ;
-  assign reg_error = (devmode_i & addrmiss) | wr_err;
-
-
-  // Define SW related signals
-  // Format: <reg>_<field>_{wd|we|qs}
-  //        or <reg>_{wd|we|qs} if field == 1 or 0
-  logic [3:0] col_status_qs;
-  logic [31:0] slot0_ker_id_qs;
-  logic [31:0] slot0_ker_id_wd;
-  logic slot0_ker_id_we;
-  logic [31:0] slot1_ker_id_qs;
-  logic [31:0] slot1_ker_id_wd;
-  logic slot1_ker_id_we;
-  logic [31:0] slot0_ptr_in_c0_qs;
-  logic [31:0] slot0_ptr_in_c0_wd;
-  logic slot0_ptr_in_c0_we;
-  logic [31:0] slot0_ptr_out_c0_qs;
-  logic [31:0] slot0_ptr_out_c0_wd;
-  logic slot0_ptr_out_c0_we;
-  logic [31:0] slot0_ptr_in_c1_qs;
-  logic [31:0] slot0_ptr_in_c1_wd;
-  logic slot0_ptr_in_c1_we;
-  logic [31:0] slot0_ptr_out_c1_qs;
-  logic [31:0] slot0_ptr_out_c1_wd;
-  logic slot0_ptr_out_c1_we;
-  logic [31:0] slot0_ptr_in_c2_qs;
-  logic [31:0] slot0_ptr_in_c2_wd;
-  logic slot0_ptr_in_c2_we;
-  logic [31:0] slot0_ptr_out_c2_qs;
-  logic [31:0] slot0_ptr_out_c2_wd;
-  logic slot0_ptr_out_c2_we;
-  logic [31:0] slot0_ptr_in_c3_qs;
-  logic [31:0] slot0_ptr_in_c3_wd;
-  logic slot0_ptr_in_c3_we;
-  logic [31:0] slot0_ptr_out_c3_qs;
-  logic [31:0] slot0_ptr_out_c3_wd;
-  logic slot0_ptr_out_c3_we;
-  logic [31:0] slot1_ptr_in_c0_qs;
-  logic [31:0] slot1_ptr_in_c0_wd;
-  logic slot1_ptr_in_c0_we;
-  logic [31:0] slot1_ptr_out_c0_qs;
-  logic [31:0] slot1_ptr_out_c0_wd;
-  logic slot1_ptr_out_c0_we;
-  logic [31:0] slot1_ptr_in_c1_qs;
-  logic [31:0] slot1_ptr_in_c1_wd;
-  logic slot1_ptr_in_c1_we;
-  logic [31:0] slot1_ptr_out_c1_qs;
-  logic [31:0] slot1_ptr_out_c1_wd;
-  logic slot1_ptr_out_c1_we;
-  logic [31:0] slot1_ptr_in_c2_qs;
-  logic [31:0] slot1_ptr_in_c2_wd;
-  logic slot1_ptr_in_c2_we;
-  logic [31:0] slot1_ptr_out_c2_qs;
-  logic [31:0] slot1_ptr_out_c2_wd;
-  logic slot1_ptr_out_c2_we;
-  logic [31:0] slot1_ptr_in_c3_qs;
-  logic [31:0] slot1_ptr_in_c3_wd;
-  logic slot1_ptr_in_c3_we;
-  logic [31:0] slot1_ptr_out_c3_qs;
-  logic [31:0] slot1_ptr_out_c3_wd;
-  logic slot1_ptr_out_c3_we;
-  logic perf_cnt_enable_qs;
-  logic perf_cnt_enable_wd;
-  logic perf_cnt_enable_we;
-  logic perf_cnt_reset_qs;
-  logic perf_cnt_reset_wd;
-  logic perf_cnt_reset_we;
-  logic [31:0] perf_cnt_total_kernels_qs;
-  logic [31:0] perf_cnt_total_kernels_wd;
-  logic perf_cnt_total_kernels_we;
-  logic [31:0] perf_cnt_c0_active_cycles_qs;
-  logic [31:0] perf_cnt_c0_active_cycles_wd;
-  logic perf_cnt_c0_active_cycles_we;
-  logic [31:0] perf_cnt_c0_stall_cycles_qs;
-  logic [31:0] perf_cnt_c0_stall_cycles_wd;
-  logic perf_cnt_c0_stall_cycles_we;
-  logic [31:0] perf_cnt_c1_active_cycles_qs;
-  logic [31:0] perf_cnt_c1_active_cycles_wd;
-  logic perf_cnt_c1_active_cycles_we;
-  logic [31:0] perf_cnt_c1_stall_cycles_qs;
-  logic [31:0] perf_cnt_c1_stall_cycles_wd;
-  logic perf_cnt_c1_stall_cycles_we;
-  logic [31:0] perf_cnt_c2_active_cycles_qs;
-  logic [31:0] perf_cnt_c2_active_cycles_wd;
-  logic perf_cnt_c2_active_cycles_we;
-  logic [31:0] perf_cnt_c2_stall_cycles_qs;
-  logic [31:0] perf_cnt_c2_stall_cycles_wd;
-  logic perf_cnt_c2_stall_cycles_we;
-  logic [31:0] perf_cnt_c3_active_cycles_qs;
-  logic [31:0] perf_cnt_c3_active_cycles_wd;
-  logic perf_cnt_c3_active_cycles_we;
-  logic [31:0] perf_cnt_c3_stall_cycles_qs;
-  logic [31:0] perf_cnt_c3_stall_cycles_wd;
-  logic perf_cnt_c3_stall_cycles_we;
-  logic [31:0] reserved30_qs;
-  logic [31:0] reserved31_qs;
-
-  // Register instances
-  // R[col_status]: V(False)
-
-  prim_subreg #(
-    .DW      (4),
-    .SWACCESS("RO"),
-    .RESVAL  (4'h0)
-  ) u_col_status (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    .we     (1'b0),
-    .wd     ('0  ),
-
-    // from internal hardware
-    .de     (hw2reg.col_status.de),
-    .d      (hw2reg.col_status.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.col_status.q ),
-
-    // to register interface (read)
-    .qs     (col_status_qs)
-  );
-
-
-  // R[slot0_ker_id]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ker_id (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ker_id_we),
-    .wd     (slot0_ker_id_wd),
-
-    // from internal hardware
-    .de     (hw2reg.slot0_ker_id.de),
-    .d      (hw2reg.slot0_ker_id.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ker_id.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ker_id_qs)
-  );
-
-
-  // R[slot1_ker_id]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ker_id (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ker_id_we),
-    .wd     (slot1_ker_id_wd),
-
-    // from internal hardware
-    .de     (hw2reg.slot1_ker_id.de),
-    .d      (hw2reg.slot1_ker_id.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ker_id.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ker_id_qs)
-  );
-
-
-  // R[slot0_ptr_in_c0]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_in_c0 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_in_c0_we),
-    .wd     (slot0_ptr_in_c0_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_in_c0.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_in_c0_qs)
-  );
-
-
-  // R[slot0_ptr_out_c0]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_out_c0 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_out_c0_we),
-    .wd     (slot0_ptr_out_c0_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_out_c0.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_out_c0_qs)
-  );
-
-
-  // R[slot0_ptr_in_c1]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_in_c1 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_in_c1_we),
-    .wd     (slot0_ptr_in_c1_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_in_c1.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_in_c1_qs)
-  );
-
-
-  // R[slot0_ptr_out_c1]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_out_c1 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_out_c1_we),
-    .wd     (slot0_ptr_out_c1_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_out_c1.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_out_c1_qs)
-  );
-
-
-  // R[slot0_ptr_in_c2]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_in_c2 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_in_c2_we),
-    .wd     (slot0_ptr_in_c2_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_in_c2.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_in_c2_qs)
-  );
-
-
-  // R[slot0_ptr_out_c2]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_out_c2 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_out_c2_we),
-    .wd     (slot0_ptr_out_c2_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_out_c2.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_out_c2_qs)
-  );
-
-
-  // R[slot0_ptr_in_c3]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_in_c3 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_in_c3_we),
-    .wd     (slot0_ptr_in_c3_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_in_c3.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_in_c3_qs)
-  );
-
-
-  // R[slot0_ptr_out_c3]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot0_ptr_out_c3 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot0_ptr_out_c3_we),
-    .wd     (slot0_ptr_out_c3_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot0_ptr_out_c3.q ),
-
-    // to register interface (read)
-    .qs     (slot0_ptr_out_c3_qs)
-  );
-
-
-  // R[slot1_ptr_in_c0]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_in_c0 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_in_c0_we),
-    .wd     (slot1_ptr_in_c0_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_in_c0.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_in_c0_qs)
-  );
-
-
-  // R[slot1_ptr_out_c0]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_out_c0 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_out_c0_we),
-    .wd     (slot1_ptr_out_c0_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_out_c0.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_out_c0_qs)
-  );
-
-
-  // R[slot1_ptr_in_c1]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_in_c1 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_in_c1_we),
-    .wd     (slot1_ptr_in_c1_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_in_c1.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_in_c1_qs)
-  );
-
-
-  // R[slot1_ptr_out_c1]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_out_c1 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_out_c1_we),
-    .wd     (slot1_ptr_out_c1_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_out_c1.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_out_c1_qs)
-  );
-
-
-  // R[slot1_ptr_in_c2]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_in_c2 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_in_c2_we),
-    .wd     (slot1_ptr_in_c2_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_in_c2.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_in_c2_qs)
-  );
-
-
-  // R[slot1_ptr_out_c2]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_out_c2 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_out_c2_we),
-    .wd     (slot1_ptr_out_c2_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_out_c2.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_out_c2_qs)
-  );
-
-
-  // R[slot1_ptr_in_c3]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_in_c3 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_in_c3_we),
-    .wd     (slot1_ptr_in_c3_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_in_c3.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_in_c3_qs)
-  );
-
-
-  // R[slot1_ptr_out_c3]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_slot1_ptr_out_c3 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (slot1_ptr_out_c3_we),
-    .wd     (slot1_ptr_out_c3_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.slot1_ptr_out_c3.q ),
-
-    // to register interface (read)
-    .qs     (slot1_ptr_out_c3_qs)
-  );
-
-
-  // R[perf_cnt_enable]: V(False)
-
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_perf_cnt_enable (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_enable_we),
-    .wd     (perf_cnt_enable_wd),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_enable.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_enable_qs)
-  );
-
-
-  // R[perf_cnt_reset]: V(False)
-
-  prim_subreg #(
-    .DW      (1),
-    .SWACCESS("RW"),
-    .RESVAL  (1'h0)
-  ) u_perf_cnt_reset (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_reset_we),
-    .wd     (perf_cnt_reset_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_reset.de),
-    .d      (hw2reg.perf_cnt_reset.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_reset.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_reset_qs)
-  );
-
-
-  // R[perf_cnt_total_kernels]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_total_kernels (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_total_kernels_we),
-    .wd     (perf_cnt_total_kernels_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_total_kernels.de),
-    .d      (hw2reg.perf_cnt_total_kernels.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_total_kernels.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_total_kernels_qs)
-  );
-
-
-  // R[perf_cnt_c0_active_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c0_active_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c0_active_cycles_we),
-    .wd     (perf_cnt_c0_active_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c0_active_cycles.de),
-    .d      (hw2reg.perf_cnt_c0_active_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c0_active_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c0_active_cycles_qs)
-  );
-
-
-  // R[perf_cnt_c0_stall_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c0_stall_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c0_stall_cycles_we),
-    .wd     (perf_cnt_c0_stall_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c0_stall_cycles.de),
-    .d      (hw2reg.perf_cnt_c0_stall_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c0_stall_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c0_stall_cycles_qs)
-  );
-
-
-  // R[perf_cnt_c1_active_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c1_active_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c1_active_cycles_we),
-    .wd     (perf_cnt_c1_active_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c1_active_cycles.de),
-    .d      (hw2reg.perf_cnt_c1_active_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c1_active_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c1_active_cycles_qs)
-  );
-
-
-  // R[perf_cnt_c1_stall_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c1_stall_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c1_stall_cycles_we),
-    .wd     (perf_cnt_c1_stall_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c1_stall_cycles.de),
-    .d      (hw2reg.perf_cnt_c1_stall_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c1_stall_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c1_stall_cycles_qs)
-  );
-
-
-  // R[perf_cnt_c2_active_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c2_active_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c2_active_cycles_we),
-    .wd     (perf_cnt_c2_active_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c2_active_cycles.de),
-    .d      (hw2reg.perf_cnt_c2_active_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c2_active_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c2_active_cycles_qs)
-  );
-
-
-  // R[perf_cnt_c2_stall_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c2_stall_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c2_stall_cycles_we),
-    .wd     (perf_cnt_c2_stall_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c2_stall_cycles.de),
-    .d      (hw2reg.perf_cnt_c2_stall_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c2_stall_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c2_stall_cycles_qs)
-  );
-
-
-  // R[perf_cnt_c3_active_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c3_active_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c3_active_cycles_we),
-    .wd     (perf_cnt_c3_active_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c3_active_cycles.de),
-    .d      (hw2reg.perf_cnt_c3_active_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c3_active_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c3_active_cycles_qs)
-  );
-
-
-  // R[perf_cnt_c3_stall_cycles]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RW"),
-    .RESVAL  (32'h0)
-  ) u_perf_cnt_c3_stall_cycles (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    // from register interface
-    .we     (perf_cnt_c3_stall_cycles_we),
-    .wd     (perf_cnt_c3_stall_cycles_wd),
-
-    // from internal hardware
-    .de     (hw2reg.perf_cnt_c3_stall_cycles.de),
-    .d      (hw2reg.perf_cnt_c3_stall_cycles.d ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.perf_cnt_c3_stall_cycles.q ),
-
-    // to register interface (read)
-    .qs     (perf_cnt_c3_stall_cycles_qs)
-  );
-
-
-  // R[reserved30]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RO"),
-    .RESVAL  (32'h0)
-  ) u_reserved30 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    .we     (1'b0),
-    .wd     ('0  ),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.reserved30.q ),
-
-    // to register interface (read)
-    .qs     (reserved30_qs)
-  );
-
-
-  // R[reserved31]: V(False)
-
-  prim_subreg #(
-    .DW      (32),
-    .SWACCESS("RO"),
-    .RESVAL  (32'h0)
-  ) u_reserved31 (
-    .clk_i   (clk_i    ),
-    .rst_ni  (rst_ni  ),
-
-    .we     (1'b0),
-    .wd     ('0  ),
-
-    // from internal hardware
-    .de     (1'b0),
-    .d      ('0  ),
-
-    // to internal hardware
-    .qe     (),
-    .q      (reg2hw.reserved31.q ),
-
-    // to register interface (read)
-    .qs     (reserved31_qs)
-  );
-
-
-
-
-  logic [31:0] addr_hit;
-  always_comb begin
-    addr_hit = '0;
-    addr_hit[ 0] = (reg_addr == CGRA_COL_STATUS_OFFSET);
-    addr_hit[ 1] = (reg_addr == CGRA_SLOT0_KER_ID_OFFSET);
-    addr_hit[ 2] = (reg_addr == CGRA_SLOT1_KER_ID_OFFSET);
-    addr_hit[ 3] = (reg_addr == CGRA_SLOT0_PTR_IN_C0_OFFSET);
-    addr_hit[ 4] = (reg_addr == CGRA_SLOT0_PTR_OUT_C0_OFFSET);
-    addr_hit[ 5] = (reg_addr == CGRA_SLOT0_PTR_IN_C1_OFFSET);
-    addr_hit[ 6] = (reg_addr == CGRA_SLOT0_PTR_OUT_C1_OFFSET);
-    addr_hit[ 7] = (reg_addr == CGRA_SLOT0_PTR_IN_C2_OFFSET);
-    addr_hit[ 8] = (reg_addr == CGRA_SLOT0_PTR_OUT_C2_OFFSET);
-    addr_hit[ 9] = (reg_addr == CGRA_SLOT0_PTR_IN_C3_OFFSET);
-    addr_hit[10] = (reg_addr == CGRA_SLOT0_PTR_OUT_C3_OFFSET);
-    addr_hit[11] = (reg_addr == CGRA_SLOT1_PTR_IN_C0_OFFSET);
-    addr_hit[12] = (reg_addr == CGRA_SLOT1_PTR_OUT_C0_OFFSET);
-    addr_hit[13] = (reg_addr == CGRA_SLOT1_PTR_IN_C1_OFFSET);
-    addr_hit[14] = (reg_addr == CGRA_SLOT1_PTR_OUT_C1_OFFSET);
-    addr_hit[15] = (reg_addr == CGRA_SLOT1_PTR_IN_C2_OFFSET);
-    addr_hit[16] = (reg_addr == CGRA_SLOT1_PTR_OUT_C2_OFFSET);
-    addr_hit[17] = (reg_addr == CGRA_SLOT1_PTR_IN_C3_OFFSET);
-    addr_hit[18] = (reg_addr == CGRA_SLOT1_PTR_OUT_C3_OFFSET);
-    addr_hit[19] = (reg_addr == CGRA_PERF_CNT_ENABLE_OFFSET);
-    addr_hit[20] = (reg_addr == CGRA_PERF_CNT_RESET_OFFSET);
-    addr_hit[21] = (reg_addr == CGRA_PERF_CNT_TOTAL_KERNELS_OFFSET);
-    addr_hit[22] = (reg_addr == CGRA_PERF_CNT_C0_ACTIVE_CYCLES_OFFSET);
-    addr_hit[23] = (reg_addr == CGRA_PERF_CNT_C0_STALL_CYCLES_OFFSET);
-    addr_hit[24] = (reg_addr == CGRA_PERF_CNT_C1_ACTIVE_CYCLES_OFFSET);
-    addr_hit[25] = (reg_addr == CGRA_PERF_CNT_C1_STALL_CYCLES_OFFSET);
-    addr_hit[26] = (reg_addr == CGRA_PERF_CNT_C2_ACTIVE_CYCLES_OFFSET);
-    addr_hit[27] = (reg_addr == CGRA_PERF_CNT_C2_STALL_CYCLES_OFFSET);
-    addr_hit[28] = (reg_addr == CGRA_PERF_CNT_C3_ACTIVE_CYCLES_OFFSET);
-    addr_hit[29] = (reg_addr == CGRA_PERF_CNT_C3_STALL_CYCLES_OFFSET);
-    addr_hit[30] = (reg_addr == CGRA_RESERVED30_OFFSET);
-    addr_hit[31] = (reg_addr == CGRA_RESERVED31_OFFSET);
-  end
-
-  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-
-  // Check sub-word write is permitted
-  always_comb begin
-    wr_err = (reg_we &
-              ((addr_hit[ 0] & (|(CGRA_PERMIT[ 0] & ~reg_be))) |
-               (addr_hit[ 1] & (|(CGRA_PERMIT[ 1] & ~reg_be))) |
-               (addr_hit[ 2] & (|(CGRA_PERMIT[ 2] & ~reg_be))) |
-               (addr_hit[ 3] & (|(CGRA_PERMIT[ 3] & ~reg_be))) |
-               (addr_hit[ 4] & (|(CGRA_PERMIT[ 4] & ~reg_be))) |
-               (addr_hit[ 5] & (|(CGRA_PERMIT[ 5] & ~reg_be))) |
-               (addr_hit[ 6] & (|(CGRA_PERMIT[ 6] & ~reg_be))) |
-               (addr_hit[ 7] & (|(CGRA_PERMIT[ 7] & ~reg_be))) |
-               (addr_hit[ 8] & (|(CGRA_PERMIT[ 8] & ~reg_be))) |
-               (addr_hit[ 9] & (|(CGRA_PERMIT[ 9] & ~reg_be))) |
-               (addr_hit[10] & (|(CGRA_PERMIT[10] & ~reg_be))) |
-               (addr_hit[11] & (|(CGRA_PERMIT[11] & ~reg_be))) |
-               (addr_hit[12] & (|(CGRA_PERMIT[12] & ~reg_be))) |
-               (addr_hit[13] & (|(CGRA_PERMIT[13] & ~reg_be))) |
-               (addr_hit[14] & (|(CGRA_PERMIT[14] & ~reg_be))) |
-               (addr_hit[15] & (|(CGRA_PERMIT[15] & ~reg_be))) |
-               (addr_hit[16] & (|(CGRA_PERMIT[16] & ~reg_be))) |
-               (addr_hit[17] & (|(CGRA_PERMIT[17] & ~reg_be))) |
-               (addr_hit[18] & (|(CGRA_PERMIT[18] & ~reg_be))) |
-               (addr_hit[19] & (|(CGRA_PERMIT[19] & ~reg_be))) |
-               (addr_hit[20] & (|(CGRA_PERMIT[20] & ~reg_be))) |
-               (addr_hit[21] & (|(CGRA_PERMIT[21] & ~reg_be))) |
-               (addr_hit[22] & (|(CGRA_PERMIT[22] & ~reg_be))) |
-               (addr_hit[23] & (|(CGRA_PERMIT[23] & ~reg_be))) |
-               (addr_hit[24] & (|(CGRA_PERMIT[24] & ~reg_be))) |
-               (addr_hit[25] & (|(CGRA_PERMIT[25] & ~reg_be))) |
-               (addr_hit[26] & (|(CGRA_PERMIT[26] & ~reg_be))) |
-               (addr_hit[27] & (|(CGRA_PERMIT[27] & ~reg_be))) |
-               (addr_hit[28] & (|(CGRA_PERMIT[28] & ~reg_be))) |
-               (addr_hit[29] & (|(CGRA_PERMIT[29] & ~reg_be))) |
-               (addr_hit[30] & (|(CGRA_PERMIT[30] & ~reg_be))) |
-               (addr_hit[31] & (|(CGRA_PERMIT[31] & ~reg_be)))));
-  end
-
-  assign slot0_ker_id_we = addr_hit[1] & reg_we & !reg_error;
-  assign slot0_ker_id_wd = reg_wdata[31:0];
-
-  assign slot1_ker_id_we = addr_hit[2] & reg_we & !reg_error;
-  assign slot1_ker_id_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_in_c0_we = addr_hit[3] & reg_we & !reg_error;
-  assign slot0_ptr_in_c0_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_out_c0_we = addr_hit[4] & reg_we & !reg_error;
-  assign slot0_ptr_out_c0_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_in_c1_we = addr_hit[5] & reg_we & !reg_error;
-  assign slot0_ptr_in_c1_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_out_c1_we = addr_hit[6] & reg_we & !reg_error;
-  assign slot0_ptr_out_c1_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_in_c2_we = addr_hit[7] & reg_we & !reg_error;
-  assign slot0_ptr_in_c2_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_out_c2_we = addr_hit[8] & reg_we & !reg_error;
-  assign slot0_ptr_out_c2_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_in_c3_we = addr_hit[9] & reg_we & !reg_error;
-  assign slot0_ptr_in_c3_wd = reg_wdata[31:0];
-
-  assign slot0_ptr_out_c3_we = addr_hit[10] & reg_we & !reg_error;
-  assign slot0_ptr_out_c3_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_in_c0_we = addr_hit[11] & reg_we & !reg_error;
-  assign slot1_ptr_in_c0_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_out_c0_we = addr_hit[12] & reg_we & !reg_error;
-  assign slot1_ptr_out_c0_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_in_c1_we = addr_hit[13] & reg_we & !reg_error;
-  assign slot1_ptr_in_c1_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_out_c1_we = addr_hit[14] & reg_we & !reg_error;
-  assign slot1_ptr_out_c1_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_in_c2_we = addr_hit[15] & reg_we & !reg_error;
-  assign slot1_ptr_in_c2_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_out_c2_we = addr_hit[16] & reg_we & !reg_error;
-  assign slot1_ptr_out_c2_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_in_c3_we = addr_hit[17] & reg_we & !reg_error;
-  assign slot1_ptr_in_c3_wd = reg_wdata[31:0];
-
-  assign slot1_ptr_out_c3_we = addr_hit[18] & reg_we & !reg_error;
-  assign slot1_ptr_out_c3_wd = reg_wdata[31:0];
-
-  assign perf_cnt_enable_we = addr_hit[19] & reg_we & !reg_error;
-  assign perf_cnt_enable_wd = reg_wdata[0];
-
-  assign perf_cnt_reset_we = addr_hit[20] & reg_we & !reg_error;
-  assign perf_cnt_reset_wd = reg_wdata[0];
-
-  assign perf_cnt_total_kernels_we = addr_hit[21] & reg_we & !reg_error;
-  assign perf_cnt_total_kernels_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c0_active_cycles_we = addr_hit[22] & reg_we & !reg_error;
-  assign perf_cnt_c0_active_cycles_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c0_stall_cycles_we = addr_hit[23] & reg_we & !reg_error;
-  assign perf_cnt_c0_stall_cycles_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c1_active_cycles_we = addr_hit[24] & reg_we & !reg_error;
-  assign perf_cnt_c1_active_cycles_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c1_stall_cycles_we = addr_hit[25] & reg_we & !reg_error;
-  assign perf_cnt_c1_stall_cycles_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c2_active_cycles_we = addr_hit[26] & reg_we & !reg_error;
-  assign perf_cnt_c2_active_cycles_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c2_stall_cycles_we = addr_hit[27] & reg_we & !reg_error;
-  assign perf_cnt_c2_stall_cycles_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c3_active_cycles_we = addr_hit[28] & reg_we & !reg_error;
-  assign perf_cnt_c3_active_cycles_wd = reg_wdata[31:0];
-
-  assign perf_cnt_c3_stall_cycles_we = addr_hit[29] & reg_we & !reg_error;
-  assign perf_cnt_c3_stall_cycles_wd = reg_wdata[31:0];
-
-  // Read data return
-  always_comb begin
-    reg_rdata_next = '0;
-    unique case (1'b1)
-      addr_hit[0]: begin
-        reg_rdata_next[3:0] = col_status_qs;
-      end
-
-      addr_hit[1]: begin
-        reg_rdata_next[31:0] = slot0_ker_id_qs;
-      end
-
-      addr_hit[2]: begin
-        reg_rdata_next[31:0] = slot1_ker_id_qs;
-      end
-
-      addr_hit[3]: begin
-        reg_rdata_next[31:0] = slot0_ptr_in_c0_qs;
-      end
-
-      addr_hit[4]: begin
-        reg_rdata_next[31:0] = slot0_ptr_out_c0_qs;
-      end
-
-      addr_hit[5]: begin
-        reg_rdata_next[31:0] = slot0_ptr_in_c1_qs;
-      end
-
-      addr_hit[6]: begin
-        reg_rdata_next[31:0] = slot0_ptr_out_c1_qs;
-      end
-
-      addr_hit[7]: begin
-        reg_rdata_next[31:0] = slot0_ptr_in_c2_qs;
-      end
-
-      addr_hit[8]: begin
-        reg_rdata_next[31:0] = slot0_ptr_out_c2_qs;
-      end
-
-      addr_hit[9]: begin
-        reg_rdata_next[31:0] = slot0_ptr_in_c3_qs;
-      end
-
-      addr_hit[10]: begin
-        reg_rdata_next[31:0] = slot0_ptr_out_c3_qs;
-      end
-
-      addr_hit[11]: begin
-        reg_rdata_next[31:0] = slot1_ptr_in_c0_qs;
-      end
-
-      addr_hit[12]: begin
-        reg_rdata_next[31:0] = slot1_ptr_out_c0_qs;
-      end
-
-      addr_hit[13]: begin
-        reg_rdata_next[31:0] = slot1_ptr_in_c1_qs;
-      end
-
-      addr_hit[14]: begin
-        reg_rdata_next[31:0] = slot1_ptr_out_c1_qs;
-      end
-
-      addr_hit[15]: begin
-        reg_rdata_next[31:0] = slot1_ptr_in_c2_qs;
-      end
-
-      addr_hit[16]: begin
-        reg_rdata_next[31:0] = slot1_ptr_out_c2_qs;
-      end
-
-      addr_hit[17]: begin
-        reg_rdata_next[31:0] = slot1_ptr_in_c3_qs;
-      end
-
-      addr_hit[18]: begin
-        reg_rdata_next[31:0] = slot1_ptr_out_c3_qs;
-      end
-
-      addr_hit[19]: begin
-        reg_rdata_next[0] = perf_cnt_enable_qs;
-      end
-
-      addr_hit[20]: begin
-        reg_rdata_next[0] = perf_cnt_reset_qs;
-      end
-
-      addr_hit[21]: begin
-        reg_rdata_next[31:0] = perf_cnt_total_kernels_qs;
-      end
-
-      addr_hit[22]: begin
-        reg_rdata_next[31:0] = perf_cnt_c0_active_cycles_qs;
-      end
-
-      addr_hit[23]: begin
-        reg_rdata_next[31:0] = perf_cnt_c0_stall_cycles_qs;
-      end
-
-      addr_hit[24]: begin
-        reg_rdata_next[31:0] = perf_cnt_c1_active_cycles_qs;
-      end
-
-      addr_hit[25]: begin
-        reg_rdata_next[31:0] = perf_cnt_c1_stall_cycles_qs;
-      end
-
-      addr_hit[26]: begin
-        reg_rdata_next[31:0] = perf_cnt_c2_active_cycles_qs;
-      end
-
-      addr_hit[27]: begin
-        reg_rdata_next[31:0] = perf_cnt_c2_stall_cycles_qs;
-      end
-
-      addr_hit[28]: begin
-        reg_rdata_next[31:0] = perf_cnt_c3_active_cycles_qs;
-      end
-
-      addr_hit[29]: begin
-        reg_rdata_next[31:0] = perf_cnt_c3_stall_cycles_qs;
-      end
-
-      addr_hit[30]: begin
-        reg_rdata_next[31:0] = reserved30_qs;
-      end
-
-      addr_hit[31]: begin
-        reg_rdata_next[31:0] = reserved31_qs;
-      end
-
-      default: begin
-        reg_rdata_next = '1;
-      end
-    endcase
-  end
-
-  // Unused signal tieoff
-
-  // wdata / byte enable are not always fully used
-  // add a blanket unused statement to handle lint waivers
-  logic unused_wdata;
-  logic unused_be;
-  assign unused_wdata = ^reg_wdata;
-  assign unused_be = ^reg_be;
-
-  // Assertions for Register Interface
-  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
-
-endmodule
diff --git a/hw/vendor/esl_epfl_cgra/rtl/peripheral_regs.sv b/hw/vendor/esl_epfl_cgra/rtl/peripheral_regs.sv
deleted file mode 100644
index f138560a..00000000
--- a/hw/vendor/esl_epfl_cgra/rtl/peripheral_regs.sv
+++ /dev/null
@@ -1,117 +0,0 @@
-// Copyright 2022 EPFL
-// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-
-module peripheral_regs
-  import cgra_pkg::*;
-  import reg_pkg::*;
-(
-  input  logic                           clk_i,
-  input  logic                           rst_ni,
-  input  logic                           acc_ack_i,
-  input  logic [       N_SLOTS_LOG2-1:0] c_id_req_clear_i,
-  input  logic [              N_COL-1:0] col_stall_i,
-  input  reg_req_t                       reg_req_i,
-  output reg_rsp_t                       reg_rsp_o,
-  input  logic [              N_COL-1:0] acc_req_i,
-  input  logic [              N_COL-1:0] acc_end_i,
-  output logic [              N_COL-1:0] col_status_o,
-  output logic [KER_CONF_N_REG_LOG2-1:0] core_ker_id_o [0:N_SLOTS-1],
-  output logic [           DP_WIDTH-1:0] core_rd_ptr_o [0:N_SLOTS-1][0:MAX_COL_REQ-1],
-  output logic [           DP_WIDTH-1:0] core_wr_ptr_o [0:N_SLOTS-1][0:MAX_COL_REQ-1]
-);
-
-  import cgra_reg_pkg::*;
-
-  cgra_reg2hw_t reg2hw;
-  cgra_hw2reg_t hw2reg;
-
-  logic [N_COL-1:0] col_status;
-  logic perf_cnt_en;
-  logic perf_cnt_reset;
-
-  assign col_status_o = col_status;
-
-  assign perf_cnt_en    = reg2hw.perf_cnt_enable.q;
-  assign perf_cnt_reset = reg2hw.perf_cnt_reset.q;
-
-
-  // Columns' read and write pointers
-  always_comb
-  begin
-    core_ker_id_o[0]    = reg2hw.slot0_ker_id.q[KER_CONF_N_REG_LOG2-1:0];
-    core_ker_id_o[1]    = reg2hw.slot1_ker_id.q[KER_CONF_N_REG_LOG2-1:0];
-
-    core_rd_ptr_o[0][0] = reg2hw.slot0_ptr_in_c0.q;
-    core_wr_ptr_o[0][0] = reg2hw.slot0_ptr_out_c0.q;
-    core_rd_ptr_o[0][1] = reg2hw.slot0_ptr_in_c1.q;
-    core_wr_ptr_o[0][1] = reg2hw.slot0_ptr_out_c1.q;
-    core_rd_ptr_o[0][2] = reg2hw.slot0_ptr_in_c2.q;
-    core_wr_ptr_o[0][2] = reg2hw.slot0_ptr_out_c2.q;
-    core_rd_ptr_o[0][3] = reg2hw.slot0_ptr_in_c3.q;
-    core_wr_ptr_o[0][3] = reg2hw.slot0_ptr_out_c3.q;
-
-    core_rd_ptr_o[1][0] = reg2hw.slot1_ptr_in_c0.q;
-    core_wr_ptr_o[1][0] = reg2hw.slot1_ptr_out_c0.q;
-    core_rd_ptr_o[1][1] = reg2hw.slot1_ptr_in_c1.q;
-    core_wr_ptr_o[1][1] = reg2hw.slot1_ptr_out_c1.q;
-    core_rd_ptr_o[1][2] = reg2hw.slot1_ptr_in_c2.q;
-    core_wr_ptr_o[1][2] = reg2hw.slot1_ptr_out_c2.q;
-    core_rd_ptr_o[1][3] = reg2hw.slot1_ptr_in_c3.q;
-    core_wr_ptr_o[1][3] = reg2hw.slot1_ptr_out_c3.q;
-  end
-
-  // Reset/update performance counters
-  assign hw2reg.perf_cnt_total_kernels.de = perf_cnt_reset | (perf_cnt_en & acc_ack_i);
-  assign hw2reg.perf_cnt_total_kernels.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_total_kernels.q + 1;
-  // Column 0
-  assign hw2reg.perf_cnt_c0_active_cycles.de = perf_cnt_reset | (perf_cnt_en & (col_status[0] | acc_req_i[0]));
-  assign hw2reg.perf_cnt_c0_active_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c0_active_cycles.q + 1;
-  assign hw2reg.perf_cnt_c0_stall_cycles.de = perf_cnt_reset | (perf_cnt_en & col_stall_i[0]);
-  assign hw2reg.perf_cnt_c0_stall_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c0_stall_cycles.q + 1;
-  // Column 1
-  assign hw2reg.perf_cnt_c1_active_cycles.de = perf_cnt_reset | (perf_cnt_en & (col_status[1] | acc_req_i[1]));
-  assign hw2reg.perf_cnt_c1_active_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c1_active_cycles.q + 1;
-  assign hw2reg.perf_cnt_c1_stall_cycles.de = perf_cnt_reset | (perf_cnt_en & col_stall_i[1]);
-  assign hw2reg.perf_cnt_c1_stall_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c1_stall_cycles.q + 1;
-  // Column 2
-  assign hw2reg.perf_cnt_c2_active_cycles.de = perf_cnt_reset | (perf_cnt_en & (col_status[2] | acc_req_i[2]));
-  assign hw2reg.perf_cnt_c2_active_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c2_active_cycles.q + 1;
-  assign hw2reg.perf_cnt_c2_stall_cycles.de = perf_cnt_reset | (perf_cnt_en & col_stall_i[2]);
-  assign hw2reg.perf_cnt_c2_stall_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c2_stall_cycles.q + 1;
-  // Column 3
-  assign hw2reg.perf_cnt_c3_active_cycles.de = perf_cnt_reset | (perf_cnt_en & (col_status[3] | acc_req_i[3]));
-  assign hw2reg.perf_cnt_c3_active_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c3_active_cycles.q + 1;
-  assign hw2reg.perf_cnt_c3_stall_cycles.de = perf_cnt_reset | (perf_cnt_en & col_stall_i[3]);
-  assign hw2reg.perf_cnt_c3_stall_cycles.d  = perf_cnt_reset == 1'b1 ? '0 : reg2hw.perf_cnt_c3_stall_cycles.q + 1;
-  // Disable reset
-  assign hw2reg.perf_cnt_reset.de = perf_cnt_reset;
-  assign hw2reg.perf_cnt_reset.d  = '0;
-
-  // Clear kernel ID request
-  assign hw2reg.slot0_ker_id.de = acc_ack_i | ~c_id_req_clear_i;
-  assign hw2reg.slot0_ker_id.d  = '0;
-  assign hw2reg.slot1_ker_id.de = acc_ack_i | c_id_req_clear_i;
-  assign hw2reg.slot1_ker_id.d  = '0;
-
-  // Update CGRA column status:
-  // 0 - Column is free
-  // 1 - Column is used
-  assign col_status = reg2hw.col_status.q;
-  assign hw2reg.col_status.de = ((|acc_req_i) & acc_ack_i) | (|acc_end_i);
-  assign hw2reg.col_status.d  = ((|acc_req_i) & acc_ack_i) == 1'b1 ? (col_status | acc_req_i) : (col_status & ~acc_end_i);
-
-  cgra_reg_top #(
-      .reg_req_t(reg_req_t),
-      .reg_rsp_t(reg_rsp_t)
-  ) cgra_reg_top_i (
-      .clk_i,
-      .rst_ni,
-      .reg_req_i,
-      .reg_rsp_o,
-      .reg2hw,
-      .hw2reg,
-      .devmode_i(1'b1)
-  );
-
-endmodule
diff --git a/hw/vendor/esl_epfl_cgra/sim/cgra_sram_wrapper.sv b/hw/vendor/esl_epfl_cgra/sim/cgra_sram_wrapper.sv
index 407afa08..e61bf806 100644
--- a/hw/vendor/esl_epfl_cgra/sim/cgra_sram_wrapper.sv
+++ b/hw/vendor/esl_epfl_cgra/sim/cgra_sram_wrapper.sv
@@ -22,7 +22,7 @@ module cgra_sram_wrapper #(
     input  logic [AddrWidth-1:0] addr_i,   // request address
     input  logic [         31:0] wdata_i,  // write data
     input  logic [          3:0] be_i,     // write byte enable
-    input  logic                 set_retentive_i,
+    input  logic                 set_retentive_ni,
     // output ports
     output logic [         31:0] rdata_o   // read data
 );
diff --git a/hw/vendor/esl_epfl_cgra/sw/cgra_regs.h b/hw/vendor/esl_epfl_cgra/sw/cgra_regs.h
deleted file mode 100644
index e9a87251..00000000
--- a/hw/vendor/esl_epfl_cgra/sw/cgra_regs.h
+++ /dev/null
@@ -1,125 +0,0 @@
-// Generated register defines for cgra
-
-// Copyright information found in source file:
-// Copyright EPFL contributors.
-
-// Licensing information found in source file:
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#ifndef _CGRA_REG_DEFS_
-#define _CGRA_REG_DEFS_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-// Register width
-#define CGRA_PARAM_REG_WIDTH 32
-
-// CGRA columns status (0:free, 1:used)
-#define CGRA_COL_STATUS_REG_OFFSET 0x0
-#define CGRA_COL_STATUS_COL_STATUS_MASK 0xf
-#define CGRA_COL_STATUS_COL_STATUS_OFFSET 0
-#define CGRA_COL_STATUS_COL_STATUS_FIELD \
-  ((bitfield_field32_t) { .mask = CGRA_COL_STATUS_COL_STATUS_MASK, .index = CGRA_COL_STATUS_COL_STATUS_OFFSET })
-
-// Slot 0 kernel ID
-#define CGRA_SLOT0_KER_ID_REG_OFFSET 0x4
-
-// Slot 1 kernel ID
-#define CGRA_SLOT1_KER_ID_REG_OFFSET 0x8
-
-// Slot 0 input data pointer for first column used
-#define CGRA_SLOT0_PTR_IN_C0_REG_OFFSET 0xc
-
-// Slot 0 output data pointer for first column used
-#define CGRA_SLOT0_PTR_OUT_C0_REG_OFFSET 0x10
-
-// Slot 0 input data pointer for second column used
-#define CGRA_SLOT0_PTR_IN_C1_REG_OFFSET 0x14
-
-// Slot 0 Output data pointer for second column used
-#define CGRA_SLOT0_PTR_OUT_C1_REG_OFFSET 0x18
-
-// Slot 0 input data pointer for third column used
-#define CGRA_SLOT0_PTR_IN_C2_REG_OFFSET 0x1c
-
-// Slot 0 output data pointer for first column used
-#define CGRA_SLOT0_PTR_OUT_C2_REG_OFFSET 0x20
-
-// Slot 0 input data pointer for fourth column used
-#define CGRA_SLOT0_PTR_IN_C3_REG_OFFSET 0x24
-
-// Slot 1 output data pointer for fourth column used
-#define CGRA_SLOT0_PTR_OUT_C3_REG_OFFSET 0x28
-
-// Slot 1 input data pointer for first column used
-#define CGRA_SLOT1_PTR_IN_C0_REG_OFFSET 0x2c
-
-// Slot 1 output data pointer for first column used
-#define CGRA_SLOT1_PTR_OUT_C0_REG_OFFSET 0x30
-
-// Slot 1 input data pointer for second column used
-#define CGRA_SLOT1_PTR_IN_C1_REG_OFFSET 0x34
-
-// Slot 1 Output data pointer for second column used
-#define CGRA_SLOT1_PTR_OUT_C1_REG_OFFSET 0x38
-
-// Slot 1 input data pointer for third column used
-#define CGRA_SLOT1_PTR_IN_C2_REG_OFFSET 0x3c
-
-// Slot 1 output data pointer for first column used
-#define CGRA_SLOT1_PTR_OUT_C2_REG_OFFSET 0x40
-
-// Slot 1 input data pointer for fourth column used
-#define CGRA_SLOT1_PTR_IN_C3_REG_OFFSET 0x44
-
-// Slot 1 output data pointer for fourth column used
-#define CGRA_SLOT1_PTR_OUT_C3_REG_OFFSET 0x48
-
-// Enable performance counters
-#define CGRA_PERF_CNT_ENABLE_REG_OFFSET 0x4c
-#define CGRA_PERF_CNT_ENABLE_PERF_CNT_ENABLE_BIT 0
-
-// Reset performance counters
-#define CGRA_PERF_CNT_RESET_REG_OFFSET 0x50
-#define CGRA_PERF_CNT_RESET_PERF_CNT_RESET_BIT 0
-
-// Total number of kernels executed (all columns)
-#define CGRA_PERF_CNT_TOTAL_KERNELS_REG_OFFSET 0x54
-
-// Number of active cycles (configuration+execution)) of column 0
-#define CGRA_PERF_CNT_C0_ACTIVE_CYCLES_REG_OFFSET 0x58
-
-// Number of stall cycles during execution of column 0
-#define CGRA_PERF_CNT_C0_STALL_CYCLES_REG_OFFSET 0x5c
-
-// Number of active cycles (configuration+execution)) of column 1
-#define CGRA_PERF_CNT_C1_ACTIVE_CYCLES_REG_OFFSET 0x60
-
-// Number of stall cycles during execution of column 1
-#define CGRA_PERF_CNT_C1_STALL_CYCLES_REG_OFFSET 0x64
-
-// Number of active cycles (configuration+execution) )of column 2
-#define CGRA_PERF_CNT_C2_ACTIVE_CYCLES_REG_OFFSET 0x68
-
-// Number of stall cycles during execution of column 2
-#define CGRA_PERF_CNT_C2_STALL_CYCLES_REG_OFFSET 0x6c
-
-// Number of active cycles (configuration+execution) of column 3
-#define CGRA_PERF_CNT_C3_ACTIVE_CYCLES_REG_OFFSET 0x70
-
-// Number of stall cycles during execution of column 3
-#define CGRA_PERF_CNT_C3_STALL_CYCLES_REG_OFFSET 0x74
-
-// Reserved
-#define CGRA_RESERVED30_REG_OFFSET 0x78
-
-// Reserved
-#define CGRA_RESERVED31_REG_OFFSET 0x7c
-
-#ifdef __cplusplus
-}  // extern "C"
-#endif
-#endif  // _CGRA_REG_DEFS_
-// End generated register defines for cgra
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py b/hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py
new file mode 100644
index 00000000..75586fca
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py
@@ -0,0 +1,186 @@
+# FFT OUTPUT SPLIT OPS instructions DEPREDECATED
+
+instructions.append(["NEXT RC"])
+
+# RC1_0
+# PROLOGUE
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["RF2", "CONST", "SADD", "RF2", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+
+# RC1_1
+# PROLOGUE
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF2", "CONST", "SSUB", "RF2", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+#################################################################################################
+#################################################################################################
+#################################################################################################
+
+instructions.append(["NEXT RC"])
+
+# RC2_0
+# PROLOGUE
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["DATA", "OUT_D", "IN1", "RF3", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF3", "RCT", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCB", "OUT_D", "IN1", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCT", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "EXIT", "RF1", "OFF", "OUT_F", "0"])
+
+
+# RC2_1
+# PROLOGUE
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["DATA", "OUT_D", "IN1", "RF3", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF3", "RCT", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCL", "OUT_D", "FXP_ADD", "RF2", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCL", "RCB", "FXP_SUB", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF2", "OUT_D", "FXP_ADD", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+#################################################################################################
+#################################################################################################
+#################################################################################################
+
+instructions.append(["NEXT RC"])
+
+# RC3_0
+# PROLOGUE
+instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
+instructions.append(["RF1", "CONST", "SSUB", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF2", "CONST", "SSUB", "RF2", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCB", "RF1", "SWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+
+# RC3_1
+# PROLOGUE
+instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
+instructions.append(["RF1", "CONST", "SSUB", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "IN1", "RF3", "ON", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "IN1", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF3", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCT", "RF1", "SWI", "RF1", "OFF", "OUT_F", "0"])
+
+#################################################################################################
+#################################################################################################
+#################################################################################################
+
+instructions.append(["NEXT RC"])
+
+# RC4_0
+# PROLOGUE
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF2", "ON", "OUT_F", "0"])
+instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["RF2", "RCB", "FXP_SUB", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCT", "OUT_D", "FXP_ADD", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RCB", "OUT_D", "FXP_ADD", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+
+
+# RC4_1
+# PROLOGUE
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
+instructions.append(["DATA", "OUT_D", "LWD", "RF3", "ON", "OUT_F", "0"])
+
+# ITERATION LOOP
+instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
+instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF2", "CONST", "SADD", "RF2", "ON", "OUT_F", "4"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF4", "CONST", "SADD", "RF4", "ON", "OUT_F", "1"])
+instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
+instructions.append(["RF4", "RF3", "BLT", "RF1", "OFF", "OUT_F", "6"])
+
+
+#################################################################################################
+#################################################################################################
+#################################################################################################
+
+kernel_col_needed = "0011"
+row_st_add = 58
+n_instructions = 14
diff --git a/hw/vendor/esl_epfl_cgra/utilities/cgra_bitsream_gen.py b/hw/vendor/esl_epfl_cgra/util/cgra_bitstream_gen.py.tpl
similarity index 84%
rename from hw/vendor/esl_epfl_cgra/utilities/cgra_bitsream_gen.py
rename to hw/vendor/esl_epfl_cgra/util/cgra_bitstream_gen.py.tpl
index da42ef9e..442e93a7 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/cgra_bitsream_gen.py
+++ b/hw/vendor/esl_epfl_cgra/util/cgra_bitstream_gen.py.tpl
@@ -1,3 +1,5 @@
+#!/usr/bin/env python3
+
 # Copyright EPFL contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
@@ -84,6 +86,7 @@ def return_indices_of_a(a, b, name = ''):
 
     sys.exit("ERROR instruction: " + str(b) + " is not a valid command (not in " + name + " list)")
 
+<%text>
 ##########################################################################
 #   _____ _____ _____              _____ ____  _   _ ______ _____ _____  #
 #  / ____/ ____|  __ \    /\      / ____/ __ \| \ | |  ____|_   _/ ____| #
@@ -93,22 +96,34 @@ def return_indices_of_a(a, b, name = ''):
 #  \_____\_____|_|  \_/_/    \_\  \_____\____/|_| \_|_|    |_____\_____| #
 #                                                                        #
 ##########################################################################
+</%text>\
+
+CGRA_N_COL = ${cgra_num_columns}
+CGRA_N_ROW = ${cgra_num_rows}
 
-CGRA_N_COL = 4
-CGRA_N_ROW = 4
+CGRA_MAX_COL = ${cgra_max_columns}
 
-RCS_NUM_CREG      = 32;
+RCS_NUM_CREG      = ${cgra_rcs_num_instr};
 RCS_NUM_CREG_LOG2 = ceil(log(RCS_NUM_CREG,2));
 
-CGRA_IMEM_N_LINE = 128
-CGRA_IMEM_NL_LOG2 = ceil(log(CGRA_IMEM_N_LINE,2))
+CGRA_CMEM_BK_DEPTH = ${cgra_cmem_bk_depth}
+CGRA_CMEM_BK_DEPTH_LOG2 = ceil(log(CGRA_CMEM_BK_DEPTH,2))
 
 # Memory holding the kernel configuration words (KMEM)
 # Max possible number of kernel
-CGRA_KMEM_N_KER = 16
+CGRA_KMEM_DEPTH = ${cgra_kmem_depth}
 # Kernel configuration word width
-CGRA_KMEM_WIDTH = CGRA_N_COL + CGRA_IMEM_NL_LOG2 + RCS_NUM_CREG_LOG2
+CGRA_KMEM_WIDTH = CGRA_MAX_COL + CGRA_CMEM_BK_DEPTH_LOG2 + RCS_NUM_CREG_LOG2
 
+# Check the parameters are in the expected range
+if CGRA_KMEM_WIDTH > 32:
+    print('ERROR: kernel configuration word width > 32 bits')
+if CGRA_CMEM_BK_DEPTH < (CGRA_MAX_COL*RCS_NUM_CREG):
+    print('WARNING: context memory cannot hold the maximum kernel size')
+if ${cgra_max_columns} > CGRA_N_COL:
+    print('ERROR: maximum number of columns is larger than the actual number of columns')
+
+<%text>
 #################################################################
 #  _____   _____  _____    _____ ____  _   _ _____ _____ _____  #
 # |  __ \ / ____|/ ____|  / ____/ __ \| \ | |  ___|_   _/ ____| #
@@ -118,6 +133,7 @@ def return_indices_of_a(a, b, name = ''):
 # |_|  \_\\_____|_____/   \_____\____/|_| \_|_|   |_____\_____| #
 #                                                               #
 #################################################################
+</%text>\
 
 RCS_MUXA_BITS    = 4
 RCS_MUXB_BITS    = 4
@@ -127,7 +143,11 @@ def return_indices_of_a(a, b, name = ''):
 RCS_MUXFLAG_BITS = 3
 RCS_IMM_BITS     = 13
 
-CGRA_IMEM_WIDTH = RCS_MUXA_BITS+RCS_MUXB_BITS+RCS_ALU_OP_BITS+RCS_RF_WADD_BITS+RCS_RF_WE_BITS+RCS_MUXFLAG_BITS+RCS_IMM_BITS
+CGRA_CMEM_WIDTH = RCS_MUXA_BITS+RCS_MUXB_BITS+RCS_ALU_OP_BITS+RCS_RF_WADD_BITS+RCS_RF_WE_BITS+RCS_MUXFLAG_BITS+RCS_IMM_BITS
+
+# This could be changed but for now 32 bits are expected
+if CGRA_CMEM_WIDTH != 32:
+    print('ERROR: instructions (configuration words) width not equal to 32')
 
 muxA_list     = ['ZERO', 'SELF', 'RCL', 'RCR', 'RCT', 'RCB',  'R0', 'R1', 'R2', 'R3', 'IMM']
 muxB_list     = ['ZERO', 'SELF', 'RCL', 'RCR', 'RCT', 'RCB',  'R0', 'R1', 'R2', 'R3', 'IMM']
@@ -149,6 +169,7 @@ def return_indices_of_a(a, b, name = ''):
 
 rcs_nop_instr = ['ZERO', 'ZERO', 'NOP', '-', 'SELF', '0']
 
+<%text>
 #####################################################################################
 #  _  _______ _____     _____ ____  _   _ _____  __          ______  _____  _____   #
 # | |/ /  ___|  __ \   / ____/ __ \| \ | |  ___| \ \        / / __ \|  __ \|  __ \  #
@@ -158,25 +179,28 @@ def return_indices_of_a(a, b, name = ''):
 # |_|\_\_____|_|  \_\  \_____\____/|_| \_|_|         \/  \/   \____/|_|  \_\_____/  #
 #                                                                                   #
 #####################################################################################
+</%text>\
 
 ker_null_conf = get_bin(0, CGRA_KMEM_WIDTH)
 
+<%text>
 #####################################################################################
+</%text>\
 
-rcs_imem_file = '../bitsream/cgra_imem.bit'
-ker_kmem_file = '../bitsream/cgra_kmem.bit'
+rcs_imem_file = '../bitstream/cgra_imem.bit'
+ker_kmem_file = '../bitstream/cgra_kmem.bit'
 
-if not os.path.exists('../bitsream'):
-    os.mkdir('../bitsream')
+if not os.path.exists('../bitstream'):
+    os.mkdir('../bitstream')
 
 open(rcs_imem_file, 'w')
 open(ker_kmem_file, 'w')
 
-rcs_logger = logfunc.log2file(rcs_imem_file, CGRA_IMEM_WIDTH + 4) # + 0b<>, 
+rcs_logger = logfunc.log2file(rcs_imem_file, CGRA_CMEM_WIDTH + 4) # + 0b<>, 
 ker_logger = logfunc.log2file(ker_kmem_file, CGRA_KMEM_WIDTH)
 
-rcs_instructions = [[rcs_nop_instr for _ in range(CGRA_IMEM_N_LINE)] for _ in range (CGRA_N_ROW)]
-ker_conf_words   = [ker_null_conf for _ in range(CGRA_KMEM_N_KER)]
+rcs_instructions = [[rcs_nop_instr for _ in range(CGRA_CMEM_BK_DEPTH)] for _ in range (CGRA_N_ROW)]
+ker_conf_words   = [ker_null_conf for _ in range(CGRA_KMEM_DEPTH)]
 
 # First entry is always null
 ker_conf_words[0] = ker_null_conf
@@ -210,19 +234,19 @@ def return_indices_of_a(a, b, name = ''):
 
 # PRINT STATS
 print("CGRA conf. word width  :", CGRA_KMEM_WIDTH)
-print("CGRA instruction width :", CGRA_IMEM_WIDTH)
+print("CGRA instruction width :", CGRA_CMEM_WIDTH)
 print("CGRA number of kernels :", ker_next_id-1)
 print("-------------------------------------")
 
 # Check instruction memory is large enough
-if ker_start_add > CGRA_IMEM_N_LINE:
+if ker_start_add > CGRA_CMEM_BK_DEPTH:
     print("ERROR: TOO MANY INSTRUCTIONS FOR CGRA MEMORY")
 else:
-    print("INFO: {}/{} CGRA INSTRUCTIONS".format(ker_start_add, CGRA_IMEM_N_LINE));
+    print("INFO: {}/{} CGRA INSTRUCTIONS".format(ker_start_add, CGRA_CMEM_BK_DEPTH));
 
 print("-------------------------------------")
 
-for i in range(0,CGRA_KMEM_N_KER):
+for i in range(0,CGRA_KMEM_DEPTH):
     # ker_logger.log_line(ker_conf_words[i])
     ker_logger.log_line(hex(int(ker_conf_words[i],2)))
     # print(ker_conf_words[i])
diff --git a/hw/vendor/esl_epfl_cgra/util/instructions_check_size.py b/hw/vendor/esl_epfl_cgra/util/instructions_check_size.py
new file mode 100644
index 00000000..a0680ce5
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_check_size.py
@@ -0,0 +1,33 @@
+#
+# Check CGRA size is correctly configured
+#
+
+ker_col_needed = 1
+ker_num_instr  = 6
+
+ker_conf_words[ker_next_id] = get_bin(int(pow(2,ker_col_needed))-1,CGRA_N_COL) +\
+                              get_bin(ker_start_add, RCS_NUM_CREG_LOG2) +\
+                              get_bin(ker_num_instr-1, RCS_NUM_CREG_LOG2)
+
+# Save current start address
+start_add     = ker_start_add
+# Update start address and ID for next kernel
+ker_start_add = ker_start_add + ker_num_instr*ker_col_needed
+ker_next_id   = ker_next_id+1
+
+# Used for multi-column kernels
+k = ker_num_instr
+
+#################################################################################################
+############################################## RC0 ##############################################
+#################################################################################################
+
+# COLUMN-0
+# PROLOGUE
+rcs_instructions[0][start_add+0] = [   "-",    "-",  "LWD",  "-",      "-", "4"]
+rcs_instructions[0][start_add+1] = [ "RCT", "ZERO", "SADD",  "-",      "-", "-"] # move
+rcs_instructions[0][start_add+2] = [ "RCL", "ZERO", "SADD",  "-",      "-", "-"] # move
+rcs_instructions[0][start_add+3] = ["SELF",    "-",  "SWD",  "-",      "-", "4"]
+rcs_instructions[0][start_add+4] = rcs_nop_instr
+rcs_instructions[0][start_add+5] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
+
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_dbl_max.py b/hw/vendor/esl_epfl_cgra/util/instructions_dbl_max.py
similarity index 98%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_dbl_max.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_dbl_max.py
index a3595c5d..a7fd679f 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_dbl_max.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_dbl_max.py
@@ -40,7 +40,7 @@
 # EPILOGUE
 rcs_instructions[0][start_add+10] = rcs_nop_instr
 rcs_instructions[0][start_add+11] = rcs_nop_instr
-rcs_instructions[0][start_add+12] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[0][start_add+12] = [  "R0",    "-",  "SWD",  "-",      "-", "4"]
 rcs_instructions[0][start_add+13] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
 
 #################################################################################################
@@ -49,7 +49,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",  "LWD", "R2",      "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",  "LWD", "R2",      "-", "4"]
 rcs_instructions[1][start_add+ 1] = rcs_nop_instr
 rcs_instructions[1][start_add+ 2] = [   "-",   "R2",  "LWI", "R0",      "-", "-"]
 
@@ -63,7 +63,7 @@
 rcs_instructions[1][start_add+ 9] = rcs_nop_instr
 
 # EPILOGUE
-rcs_instructions[1][start_add+10] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[1][start_add+10] = [  "R0",    "-",  "SWD",  "-",      "-", "4"]
 rcs_instructions[1][start_add+11] = rcs_nop_instr
 rcs_instructions[1][start_add+12] = rcs_nop_instr
 rcs_instructions[1][start_add+13] = rcs_nop_instr
@@ -89,7 +89,7 @@
 
 # EPILOGUE
 rcs_instructions[2][start_add+10] = rcs_nop_instr
-rcs_instructions[2][start_add+11] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[2][start_add+11] = [  "R0",    "-",  "SWD",  "-",      "-", "4"]
 rcs_instructions[2][start_add+12] = rcs_nop_instr
 rcs_instructions[2][start_add+13] = rcs_nop_instr
 
@@ -100,7 +100,7 @@
 # COLUMN-0
 # PROLOGUE
 rcs_instructions[3][start_add+ 0] = [ "IMM", "ZERO", "SADD", "R0",      "-", "-1"] # move
-rcs_instructions[3][start_add+ 1] = [   "-",    "-",  "LWD", "R3",      "-", "-"]
+rcs_instructions[3][start_add+ 1] = [   "-",    "-",  "LWD", "R3",      "-", "4"]
 rcs_instructions[3][start_add+ 2] = rcs_nop_instr
 
 # ITERATION LOOP
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_dbl_min.py b/hw/vendor/esl_epfl_cgra/util/instructions_dbl_min.py
similarity index 98%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_dbl_min.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_dbl_min.py
index dfaf1280..d68ef12b 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_dbl_min.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_dbl_min.py
@@ -40,7 +40,7 @@
 # EPILOGUE
 rcs_instructions[0][start_add+10] = rcs_nop_instr
 rcs_instructions[0][start_add+11] = rcs_nop_instr
-rcs_instructions[0][start_add+12] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[0][start_add+12] = [  "R0",    "-",  "SWD",  "-",      "-", "4"]
 rcs_instructions[0][start_add+13] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
 
 #################################################################################################
@@ -49,7 +49,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",  "LWD", "R2",      "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",  "LWD", "R2",      "-", "4"]
 rcs_instructions[1][start_add+ 1] = rcs_nop_instr
 rcs_instructions[1][start_add+ 2] = [   "-",   "R2",  "LWI", "R0",      "-", "-"]
 
@@ -63,7 +63,7 @@
 rcs_instructions[1][start_add+ 9] = rcs_nop_instr
 
 # EPILOGUE
-rcs_instructions[1][start_add+10] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[1][start_add+10] = [  "R0",    "-",  "SWD",  "-",      "-", "4"]
 rcs_instructions[1][start_add+11] = rcs_nop_instr
 rcs_instructions[1][start_add+12] = rcs_nop_instr
 rcs_instructions[1][start_add+13] = rcs_nop_instr
@@ -89,7 +89,7 @@
 
 # EPILOGUE
 rcs_instructions[2][start_add+10] = rcs_nop_instr
-rcs_instructions[2][start_add+11] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[2][start_add+11] = [  "R0",    "-",  "SWD",  "-",      "-", "4"]
 rcs_instructions[2][start_add+12] = rcs_nop_instr
 rcs_instructions[2][start_add+13] = rcs_nop_instr
 
@@ -100,7 +100,7 @@
 # COLUMN-0
 # PROLOGUE
 rcs_instructions[3][start_add+ 0] = [ "IMM", "ZERO", "SADD", "R0",      "-", "-1"] # move
-rcs_instructions[3][start_add+ 1] = [   "-",    "-",  "LWD", "R3",      "-", "-"]
+rcs_instructions[3][start_add+ 1] = [   "-",    "-",  "LWD", "R3",      "-", "4"]
 rcs_instructions[3][start_add+ 2] = rcs_nop_instr
 
 # ITERATION LOOP
diff --git a/hw/vendor/esl_epfl_cgra/util/instructions_fft_bitrev.py b/hw/vendor/esl_epfl_cgra/util/instructions_fft_bitrev.py
new file mode 100644
index 00000000..0e7cb32a
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_fft_bitrev.py
@@ -0,0 +1,103 @@
+#
+# FFT input bit reversal reordering instructions (manual mapping)
+#
+
+ker_col_needed = 1
+ker_num_instr  = 11
+
+ker_conf_words[ker_next_id] = get_bin(int(pow(2,ker_col_needed))-1,CGRA_N_COL) +\
+                              get_bin(ker_start_add, CGRA_IMEM_NL_LOG2) +\
+                              get_bin(ker_num_instr-1, RCS_NUM_CREG_LOG2)
+
+# Save current start address
+start_add     = ker_start_add
+# Update start address and ID for next kernel
+ker_start_add = ker_start_add + ker_num_instr*ker_col_needed
+ker_next_id   = ker_next_id+1
+
+# Used for multi-column kernels
+k = ker_num_instr
+
+#################################################################################################
+############################################## RC0 ##############################################
+#################################################################################################
+
+# COLUMN-0
+# PROLOGUE
+rcs_instructions[0][start_add+ 0] = [   "-",    "-",  "LWD", "R0",    "-", "4"]
+rcs_instructions[0][start_add+ 1] = [   "-",    "-",  "LWD", "R1",    "-", "4"]
+rcs_instructions[0][start_add+ 2] = rcs_nop_instr
+rcs_instructions[0][start_add+ 3] = [  "R0",  "RCB", "SADD", "R0",    "-", "-"]
+
+# ITERATION LOOP
+rcs_instructions[0][start_add+ 4] = [   "-",   "R0",  "LWI", "R2",    "-", "-"]
+rcs_instructions[0][start_add+ 5] = [  "R0",  "IMM", "SADD", "R0",    "-", "8"]
+rcs_instructions[0][start_add+ 6] = rcs_nop_instr
+rcs_instructions[0][start_add+ 7] = rcs_nop_instr
+
+rcs_instructions[0][start_add+ 8] = [ "RCB",  "IMM",  "SLT",  "-",    "-", "2"]
+rcs_instructions[0][start_add+ 9] = [  "R1", "SELF", "SADD",  "-",    "-", "-"]
+rcs_instructions[0][start_add+10] = [  "R2", "SELF",  "SWI",  "-",    "-", "-"]
+
+#################################################################################################
+############################################## RC1 ##############################################
+#################################################################################################
+
+# COLUMN-0
+# PROLOGUE
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",  "LWD", "R0",    "-", "4"]
+rcs_instructions[1][start_add+ 1] = [   "-",    "-",  "LWD", "R1",    "-", "4"]
+rcs_instructions[1][start_add+ 2] = [ "RCB",  "IMM",  "SLT",  "-",    "-", "2"]
+rcs_instructions[1][start_add+ 3] = [  "R0", "SELF", "SADD", "R0",    "-", "-"]
+
+# ITERATION LOOP
+rcs_instructions[1][start_add+ 4] = [   "-",   "R0",  "LWI", "R2",    "-", "-"]
+rcs_instructions[1][start_add+ 5] = [  "R0",  "IMM", "SADD", "R0",    "-", "8"]
+rcs_instructions[1][start_add+ 6] = [  "R3",  "IMM",  "SLT",  "-",    "-", "1"]
+rcs_instructions[1][start_add+ 7] = ["SELF",  "RCB",  "LOR", "R3",    "-", "-"]
+
+rcs_instructions[1][start_add+ 8] = ["ZERO", "ZERO", "SADD", "R3",    "-", "-"] # R3=0
+rcs_instructions[1][start_add+ 9] = [ "RCT",   "R1", "SADD",  "-",    "-", "-"]
+rcs_instructions[1][start_add+10] = [  "R2", "SELF",  "SWI",  "-",    "-", "-"]
+
+#################################################################################################
+############################################## RC2 ##############################################
+#################################################################################################
+
+# COLUMN-0
+# PROLOGUE
+rcs_instructions[2][start_add+ 0] = [   "-",    "-",  "LWD", "R1",    "-", "4"]
+rcs_instructions[2][start_add+ 1] = [   "-",    "-",  "LWD", "R0",    "-", "4"]
+rcs_instructions[2][start_add+ 2] = rcs_nop_instr
+rcs_instructions[2][start_add+ 3] = rcs_nop_instr
+
+# ITERATION LOOP
+rcs_instructions[2][start_add+ 4] = ["ZERO",   "R0", "SADD", "R2",    "-", "-"] # R2=R0
+rcs_instructions[2][start_add+ 5] = rcs_nop_instr
+rcs_instructions[2][start_add+ 6] = [  "R2",  "IMM", "LAND",  "-",    "-", "1"]
+rcs_instructions[2][start_add+ 7] = [  "R2",  "IMM",  "SRT", "R2",    "-", "1"]
+
+rcs_instructions[2][start_add+ 8] = [  "R0",  "IMM", "SADD", "R0",    "-", "1"]
+rcs_instructions[2][start_add+ 9] = rcs_nop_instr
+rcs_instructions[2][start_add+10] = [  "R0",   "R1",  "BLT",  "-",    "-", "4"]
+
+#################################################################################################
+############################################## RC3 ##############################################
+#################################################################################################
+
+# COLUMN-0
+# PROLOGUE
+rcs_instructions[3][start_add+ 0] = [   "-",    "-",  "LWD", "R0",    "-", "4"]
+rcs_instructions[3][start_add+ 1] = rcs_nop_instr
+rcs_instructions[3][start_add+ 2] = rcs_nop_instr
+rcs_instructions[3][start_add+ 3] = rcs_nop_instr
+
+# ITERATION LOOP
+rcs_instructions[3][start_add+ 4] = ["ZERO", "ZERO", "SADD", "R1",    "-", "-"] # R1=0
+rcs_instructions[3][start_add+ 5] = rcs_nop_instr
+rcs_instructions[3][start_add+ 6] = [  "R1",  "IMM", "SADD", "R1",    "-", "1"]
+rcs_instructions[3][start_add+ 7] = [  "R1",   "R0",  "BLT",  "-",    "-", "6"]
+
+rcs_instructions[3][start_add+ 8] = rcs_nop_instr
+rcs_instructions[3][start_add+ 9] = rcs_nop_instr
+rcs_instructions[3][start_add+10] = [   "-",    "-", "EXIT",  "-",    "-", "-"]
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_fft_cplx.py b/hw/vendor/esl_epfl_cgra/util/instructions_fft_cplx.py
similarity index 98%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_fft_cplx.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_fft_cplx.py
index 5695005b..cec59b04 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_fft_cplx.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_fft_cplx.py
@@ -24,7 +24,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[0][start_add+ 1] = [ "IMM", "ZERO",   "SADD", "R3",    "-", "4"]
 rcs_instructions[0][start_add+ 2] = rcs_nop_instr
 
@@ -75,7 +75,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[1][start_add+ 1] = [ "RCB",  "IMM",    "SLT", "R1",    "-", "1"]
 rcs_instructions[1][start_add+ 2] = ["ZERO", "ZERO",    "BEQ",  "-",    "-", "9"]
 
@@ -99,7 +99,7 @@
 
 # COLUMN-1
 # PROLOGUE
-rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[1][start_add+k+ 1] = [ "RCB", "ZERO",   "SADD",  "-",    "-", "-"]
 rcs_instructions[1][start_add+k+ 2] = rcs_nop_instr
 
@@ -126,7 +126,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD",  "-",    "-", "-"]
+rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD",  "-",    "-", "4"]
 rcs_instructions[2][start_add+ 1] = ["ZERO",  "IMM",   "SSUB", "R1",    "-", "1"]
 rcs_instructions[2][start_add+ 2] = [ "RCT",  "IMM",    "SRT", "R0",    "-", "2"]
 
@@ -150,7 +150,7 @@
 
 # COLUMN-1
 # PROLOGUE
-rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[2][start_add+k+ 1] = ["ZERO",  "RCB",   "SADD", "R1",    "-", "-"]
 rcs_instructions[2][start_add+k+ 2] = rcs_nop_instr
 
@@ -201,7 +201,7 @@
 
 # COLUMN-1
 # PROLOGUE
-rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD",  "-",    "-", "-"]
+rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD",  "-",    "-", "4"]
 rcs_instructions[3][start_add+k+ 1] = ["ZERO",  "IMM",   "SADD", "R2",    "-", "1"]
 rcs_instructions[3][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R0",    "-", "1"]
 
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_fft_cplx_forever.py b/hw/vendor/esl_epfl_cgra/util/instructions_fft_cplx_forever.py
similarity index 98%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_fft_cplx_forever.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_fft_cplx_forever.py
index 3384c22e..b3ee7dd8 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_fft_cplx_forever.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_fft_cplx_forever.py
@@ -24,7 +24,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[0][start_add+ 1] = [ "IMM", "ZERO",   "SADD", "R3",    "-", "4"]
 rcs_instructions[0][start_add+ 2] = rcs_nop_instr
 
@@ -77,7 +77,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[1][start_add+ 1] = [ "RCB",  "IMM",    "SLT", "R1",    "-", "1"]
 rcs_instructions[1][start_add+ 2] = ["ZERO", "ZERO",    "BEQ",  "-",    "-", "9"]
 
@@ -102,7 +102,7 @@
 
 # COLUMN-1
 # PROLOGUE
-rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[1][start_add+k+ 1] = [ "RCB", "ZERO",   "SADD",  "-",    "-", "-"]
 rcs_instructions[1][start_add+k+ 2] = rcs_nop_instr
 
@@ -130,7 +130,7 @@
 
 # COLUMN-0
 # PROLOGUE
-rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[2][start_add+ 1] = ["ZERO",  "IMM",   "SSUB", "R1",    "-", "1"]
 rcs_instructions[2][start_add+ 2] = [ "RCT",  "IMM",    "SRT", "R0",    "-", "2"]
 
@@ -155,7 +155,7 @@
 
 # COLUMN-1
 # PROLOGUE
-rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "-"]
+rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R2",    "-", "4"]
 rcs_instructions[2][start_add+k+ 1] = ["ZERO",  "RCB",   "SADD", "R1",    "-", "-"]
 rcs_instructions[2][start_add+k+ 2] = rcs_nop_instr
 
@@ -208,7 +208,7 @@
 
 # COLUMN-1
 # PROLOGUE
-rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[3][start_add+k+ 1] = ["ZERO",  "IMM",   "SADD", "R2",    "-", "1"]
 rcs_instructions[3][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R0",    "-", "1"]
 
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_func_test.py b/hw/vendor/esl_epfl_cgra/util/instructions_func_test.py
similarity index 98%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_func_test.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_func_test.py
index 3d2a5054..8c0acb1c 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_func_test.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_func_test.py
@@ -23,8 +23,8 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[0][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[0][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[0][start_add+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[0][start_add+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -57,8 +57,8 @@
 rcs_instructions[0][start_add+31] = [   "-",    "-",   "EXIT",  "-",    "-", "-"]
 
 # COLUMN-1
-rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[0][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[0][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[0][start_add+k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[0][start_add+k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -91,8 +91,8 @@
 rcs_instructions[0][start_add+k+31] = [ "IMM", "ZERO",   "SADD", "R3",    "-", "-13"] # move
 
 # COLUMN-2
-rcs_instructions[0][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[0][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[0][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[0][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[0][start_add+2*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+2*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[0][start_add+2*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -125,8 +125,8 @@
 rcs_instructions[0][start_add+2*k+31] = rcs_nop_instr
 
 # COLUMN-3
-rcs_instructions[0][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[0][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[0][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[0][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[0][start_add+3*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+3*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[0][start_add+3*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -164,8 +164,8 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[1][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[1][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[1][start_add+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[1][start_add+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -198,8 +198,8 @@
 rcs_instructions[1][start_add+31] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[1][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[1][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[1][start_add+k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[1][start_add+k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -232,8 +232,8 @@
 rcs_instructions[1][start_add+k+31] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[1][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[1][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[1][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[1][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[1][start_add+2*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+2*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[1][start_add+2*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -266,8 +266,8 @@
 rcs_instructions[1][start_add+2*k+31] = rcs_nop_instr
 
 # COLUMN-3
-rcs_instructions[1][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[1][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[1][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[1][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[1][start_add+3*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+3*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[1][start_add+3*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -304,8 +304,8 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[2][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[2][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[2][start_add+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[2][start_add+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -338,8 +338,8 @@
 rcs_instructions[2][start_add+31] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[2][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[2][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[2][start_add+k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[2][start_add+k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -372,8 +372,8 @@
 rcs_instructions[2][start_add+k+31] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[2][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[2][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[2][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[2][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[2][start_add+2*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+2*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[2][start_add+2*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -406,8 +406,8 @@
 rcs_instructions[2][start_add+2*k+31] = rcs_nop_instr
 
 # COLUMN-3
-rcs_instructions[2][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[2][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[2][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[2][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[2][start_add+3*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+3*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[2][start_add+3*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -444,8 +444,8 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[3][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[3][start_add+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[3][start_add+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[3][start_add+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -478,8 +478,8 @@
 rcs_instructions[3][start_add+31] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[3][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[3][start_add+k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[3][start_add+k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[3][start_add+k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -512,8 +512,8 @@
 rcs_instructions[3][start_add+k+31] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[3][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[3][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[3][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[3][start_add+2*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[3][start_add+2*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+2*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[3][start_add+2*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
@@ -546,8 +546,8 @@
 rcs_instructions[3][start_add+2*k+31] = rcs_nop_instr
 
 # COLUMN-3
-rcs_instructions[3][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
-rcs_instructions[3][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "-"]
+rcs_instructions[3][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
+rcs_instructions[3][start_add+3*k+ 1] = [   "-",    "-",    "LWD", "R1",    "-", "4"]
 rcs_instructions[3][start_add+3*k+ 2] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+3*k+ 3] = [ "RCB",   "R2",   "SADD", "R2",    "-", "-"]
 rcs_instructions[3][start_add+3*k+ 4] = [  "R2",  "RCT",   "SSUB", "R3",    "-", "-"]
diff --git a/hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py b/hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py
new file mode 100644
index 00000000..5c236c82
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py
@@ -0,0 +1,87 @@
+#
+# MAX_PEAK search instructions DEPREDECATED
+#
+
+ker_col_needed = 1
+ker_num_instr  = 11
+
+ker_conf_words[ker_next_id] = get_bin(int(pow(2,ker_col_needed))-1,CGRA_N_COL) +\
+                                get_bin(ker_start_add, CGRA_IMEM_NL_LOG2) +\
+                                get_bin(ker_num_instr-1, RCS_NUM_CREG_LOG2)
+
+# Save current start address
+start_add     = ker_start_add
+# Update start address and ID for next kernel
+ker_start_add = ker_start_add + ker_num_instr*ker_col_needed
+ker_next_id   = ker_next_id+1
+
+# Used for multi-column kernels
+k = ker_num_instr
+
+#################################################################################################
+############################################## RC0 ##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[0][start_add+ 0] = rcs_nop_instr
+rcs_instructions[0][start_add+ 1] = rcs_nop_instr
+rcs_instructions[0][start_add+ 2] = ["SRAM",    "-",  "LWD", "R1",      "-", "-"]
+rcs_instructions[0][start_add+ 3] = ["SRAM",    "-",  "LWD", "R0",      "-", "-"]
+rcs_instructions[0][start_add+ 4] = rcs_nop_instr
+rcs_instructions[0][start_add+ 5] = [  "R2",   "R1", "SSUB",  "-",      "-", "-"]
+rcs_instructions[0][start_add+ 6] = [  "R1",   "R2", "BSFA",  "-",   "PREV", "-"]
+rcs_instructions[0][start_add+ 7] = [  "R2", "PREV", "BSFA", "R2",    "RCB", "-"]
+rcs_instructions[0][start_add+ 8] = [  "R0",    "-",  "INA", "R1",      "-", "-"]
+rcs_instructions[0][start_add+ 9] = rcs_nop_instr
+rcs_instructions[0][start_add+10] = [  "R2",    "-",  "SWD",  "-",      "-", "-"]
+
+#################################################################################################
+############################################## RC1 ##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[1][start_add+ 0] = rcs_nop_instr
+rcs_instructions[1][start_add+ 1] = ["SRAM",    "-",  "LWD", "R0",      "-", "-"]
+rcs_instructions[1][start_add+ 2] = [   "-",  "IMM",  "INB", "R1",      "-", "-1"]
+rcs_instructions[1][start_add+ 3] = [ "RCT",    "-",  "INA", "R3",      "-", "-"]
+rcs_instructions[1][start_add+ 4] = [  "R3",   "R0", "SSUB",  "-",      "-", "-"]
+rcs_instructions[1][start_add+ 5] = [  "R1",   "R2", "BSFA",  "-",   "PREV", "-"]
+rcs_instructions[1][start_add+ 6] = [ "RCB", "PREV", "SADD",  "-",      "-", "-"]
+rcs_instructions[1][start_add+ 7] = rcs_nop_instr
+rcs_instructions[1][start_add+ 8] = [  "R3",    "-",  "INA", "R0",      "-", "-"]
+rcs_instructions[1][start_add+ 9] = rcs_nop_instr
+rcs_instructions[1][start_add+10] = rcs_nop_instr
+
+#################################################################################################
+############################################## RC2 ##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[2][start_add+ 0] = rcs_nop_instr
+rcs_instructions[2][start_add+ 1] = rcs_nop_instr
+rcs_instructions[2][start_add+ 2] = [   "-",  "IMM",  "INB", "R1",      "-", "-1"]
+rcs_instructions[2][start_add+ 3] = ["SRAM",    "-",  "INA",  "-",      "-", "-"]
+rcs_instructions[2][start_add+ 4] = [ "RCB", "PREV", "SSUB",  "-",      "-", "-"]
+rcs_instructions[2][start_add+ 5] = [  "R1",   "R2", "BSFA",  "-",   "PREV", "-"]
+rcs_instructions[2][start_add+ 6] = [ "RCT", "PREV", "SADD",  "-",      "-", "-"]
+rcs_instructions[2][start_add+ 7] = rcs_nop_instr
+rcs_instructions[2][start_add+ 8] = rcs_nop_instr
+rcs_instructions[2][start_add+ 9] = rcs_nop_instr
+rcs_instructions[2][start_add+10] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
+
+#################################################################################################
+############################################## RC3 ##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[3][start_add+ 0] = ["SRAM",    "-",  "LWD", "R3",      "-", "-"]
+rcs_instructions[3][start_add+ 1] = rcs_nop_instr
+rcs_instructions[3][start_add+ 2] = ["SRAM",    "-",  "INA", "R1",      "-", "-"]
+rcs_instructions[3][start_add+ 3] = [  "R1",    "-",  "INA",  "-",      "-", "-"]
+rcs_instructions[3][start_add+ 4] = [ "RCB",    "-",  "INA", "R1",      "-", "-"]
+rcs_instructions[3][start_add+ 5] = [  "R0",  "IMM", "SADD", "R0",      "-", "1"]
+rcs_instructions[3][start_add+ 6] = [  "R0",   "R2", "BSFA",  "-",    "RCB", "-"]
+rcs_instructions[3][start_add+ 7] = [  "R2", "PREV", "BSFA", "R2",    "RCT", "-"]
+rcs_instructions[3][start_add+ 8] = [  "R0",   "R3",  "BLT",  "-",      "-", "3"]
+rcs_instructions[3][start_add+ 9] = [  "R2",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[3][start_add+10] = rcs_nop_instr
diff --git a/hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py b/hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py
new file mode 100644
index 00000000..2669aa8d
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py
@@ -0,0 +1,83 @@
+#
+# MIN_MAX_CIRCULAR search instructions (manual mapping) DEPREDECATED
+#
+
+ker_col_needed = 1
+ker_num_instr  = 10
+
+ker_conf_words[ker_next_id] = get_bin(int(pow(2,ker_col_needed))-1,CGRA_N_COL) +\
+                                get_bin(ker_start_add, CGRA_IMEM_NL_LOG2) +\
+                                get_bin(ker_num_instr-1, RCS_NUM_CREG_LOG2)
+
+# Save current start address
+start_add     = ker_start_add
+# Update start address and ID for next kernel
+ker_start_add = ker_start_add + ker_num_instr*ker_col_needed
+ker_next_id   = ker_next_id+1
+
+# Used for multi-column kernels
+k = ker_num_instr
+
+#################################################################################################
+############################################## RC0 ##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[0][start_add+ 0] = rcs_nop_instr
+rcs_instructions[0][start_add+ 1] = [ "RCB",  "IMM",  "SLT", "R3",      "-", "2"]
+rcs_instructions[0][start_add+ 2] = [ "RCB",  "IMM",  "SLT", "R1",      "-", "2"]
+rcs_instructions[0][start_add+ 3] = ["SRAM",    "-",  "LWD", "R0",      "-", "-"]
+rcs_instructions[0][start_add+ 4] = [  "R0",   "R1", "SADD",  "-",      "-", "-"]
+rcs_instructions[0][start_add+ 5] = [  "R1",  "IMM", "SADD",  "-",      "-", "4"]
+rcs_instructions[0][start_add+ 6] = [  "R3", "PREV", "LAND", "R1",      "-", "-"]
+rcs_instructions[0][start_add+ 7] = [  "R0",   "R1", "SADD",  "-",      "-", "-"]
+rcs_instructions[0][start_add+ 8] = rcs_nop_instr
+rcs_instructions[0][start_add+ 9] = rcs_nop_instr
+
+#################################################################################################
+############################################## RC1 ##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[1][start_add+ 0] = ["SRAM",    "-",  "LWD",  "-",      "-", "-"]
+rcs_instructions[1][start_add+ 1] = ["SRAM",    "-",  "LWD",  "-",      "-", "-"]
+rcs_instructions[1][start_add+ 2] = ["SRAM",    "-",  "LWD", "R3",      "-", "-"]
+rcs_instructions[1][start_add+ 3] = rcs_nop_instr
+rcs_instructions[1][start_add+ 4] = rcs_nop_instr
+rcs_instructions[1][start_add+ 5] = ["SRAM",  "RCT",  "LWI",  "-",      "-", "-"]
+rcs_instructions[1][start_add+ 6] = [  "R0",  "IMM", "SADD", "R0",      "-", "1"]
+rcs_instructions[1][start_add+ 7] = [  "R0",   "R3",  "BLT",  "-",      "-", "5"]
+rcs_instructions[1][start_add+ 8] = rcs_nop_instr
+rcs_instructions[1][start_add+ 9] = rcs_nop_instr
+
+#################################################################################################
+############################################## RC2 ##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[2][start_add+ 0] = rcs_nop_instr
+rcs_instructions[2][start_add+ 1] = rcs_nop_instr
+rcs_instructions[2][start_add+ 2] = rcs_nop_instr
+rcs_instructions[2][start_add+ 3] = rcs_nop_instr
+rcs_instructions[2][start_add+ 4] = rcs_nop_instr
+rcs_instructions[2][start_add+ 5] = ["SRAM",    "-",  "INA", "R1",      "-", "-"]
+rcs_instructions[2][start_add+ 6] = [  "R0",   "R1", "SSUB",  "-",      "-", "-"]
+rcs_instructions[2][start_add+ 7] = [  "R1",   "R0", "BSFA", "R0",   "PREV", "-"]
+rcs_instructions[2][start_add+ 8] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
+rcs_instructions[2][start_add+ 9] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
+
+#################################################################################################
+############################################## RC03##############################################
+#################################################################################################
+
+# COLUMN-0
+rcs_instructions[3][start_add+ 0] = rcs_nop_instr
+rcs_instructions[3][start_add+ 1] = rcs_nop_instr
+rcs_instructions[3][start_add+ 2] = rcs_nop_instr
+rcs_instructions[3][start_add+ 3] = rcs_nop_instr
+rcs_instructions[3][start_add+ 4] = rcs_nop_instr
+rcs_instructions[3][start_add+ 5] = ["SRAM",    "-",  "INA", "R1",      "-", "-"]
+rcs_instructions[3][start_add+ 6] = [  "R0",   "R1", "SSUB",  "-",      "-", "-"]
+rcs_instructions[3][start_add+ 7] = [  "R0",   "R1", "BSFA", "R0",   "PREV", "-"]
+rcs_instructions[3][start_add+ 8] = rcs_nop_instr
+rcs_instructions[3][start_add+ 9] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_100percent.py b/hw/vendor/esl_epfl_cgra/util/instructions_while_loop_100percent.py
similarity index 97%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_100percent.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_while_loop_100percent.py
index 83b705d1..d4a22242 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_100percent.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_while_loop_100percent.py
@@ -23,7 +23,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -33,7 +33,7 @@
 rcs_instructions[0][start_add+ 7] = [   "-",    "-",   "EXIT",  "-",    "-", "-"]
 
 # COLUMN-1
-rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -43,7 +43,7 @@
 rcs_instructions[0][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[0][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+2*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -53,7 +53,7 @@
 rcs_instructions[0][start_add+2*k+ 7] = rcs_nop_instr
 
 # COLUMN-3
-rcs_instructions[0][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+3*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+3*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+3*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -67,7 +67,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -77,7 +77,7 @@
 rcs_instructions[1][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -87,7 +87,7 @@
 rcs_instructions[1][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[1][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+2*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -97,7 +97,7 @@
 rcs_instructions[1][start_add+2*k+ 7] = rcs_nop_instr
 
 # COLUMN-3
-rcs_instructions[1][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+3*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+3*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+3*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -111,7 +111,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -121,7 +121,7 @@
 rcs_instructions[2][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -131,7 +131,7 @@
 rcs_instructions[2][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[2][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+2*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -141,7 +141,7 @@
 rcs_instructions[2][start_add+2*k+ 7] = rcs_nop_instr
 
 # COLUMN-3
-rcs_instructions[2][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+3*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+3*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+3*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -155,7 +155,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -165,7 +165,7 @@
 rcs_instructions[3][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -175,7 +175,7 @@
 rcs_instructions[3][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[3][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+2*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -186,7 +186,7 @@
 
 
 # COLUMN-3
-rcs_instructions[3][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+3*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+3*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+3*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+3*k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_50percent.py b/hw/vendor/esl_epfl_cgra/util/instructions_while_loop_50percent.py
similarity index 98%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_50percent.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_while_loop_50percent.py
index 2867debf..361955e0 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_50percent.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_while_loop_50percent.py
@@ -23,7 +23,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -33,7 +33,7 @@
 rcs_instructions[0][start_add+ 7] = [   "-",    "-",   "EXIT",  "-",    "-", "-"]
 
 # COLUMN-1
-rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -67,7 +67,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -77,7 +77,7 @@
 rcs_instructions[1][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -111,7 +111,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -121,7 +121,7 @@
 rcs_instructions[2][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -155,7 +155,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -165,7 +165,7 @@
 rcs_instructions[3][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_75percent.py b/hw/vendor/esl_epfl_cgra/util/instructions_while_loop_75percent.py
similarity index 97%
rename from hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_75percent.py
rename to hw/vendor/esl_epfl_cgra/util/instructions_while_loop_75percent.py
index eba2c310..daab0386 100644
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_while_loop_75percent.py
+++ b/hw/vendor/esl_epfl_cgra/util/instructions_while_loop_75percent.py
@@ -23,7 +23,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -33,7 +33,7 @@
 rcs_instructions[0][start_add+ 7] = [   "-",    "-",   "EXIT",  "-",    "-", "-"]
 
 # COLUMN-1
-rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -43,7 +43,7 @@
 rcs_instructions[0][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[0][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[0][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[0][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[0][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[0][start_add+2*k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -67,7 +67,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -77,7 +77,7 @@
 rcs_instructions[1][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -87,7 +87,7 @@
 rcs_instructions[1][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[1][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[1][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[1][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[1][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[1][start_add+2*k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -111,7 +111,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -121,7 +121,7 @@
 rcs_instructions[2][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -131,7 +131,7 @@
 rcs_instructions[2][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[2][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[2][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[2][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[2][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[2][start_add+2*k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -155,7 +155,7 @@
 #################################################################################################
 
 # COLUMN-0
-rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -165,7 +165,7 @@
 rcs_instructions[3][start_add+ 7] = rcs_nop_instr
 
 # COLUMN-1
-rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+k+ 3] = [ "RCB",   "R2",   "SMUL", "R2",    "-", "-"]
@@ -175,7 +175,7 @@
 rcs_instructions[3][start_add+k+ 7] = rcs_nop_instr
 
 # COLUMN-2
-rcs_instructions[3][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "-"]
+rcs_instructions[3][start_add+2*k+ 0] = [   "-",    "-",    "LWD", "R0",    "-", "4"]
 rcs_instructions[3][start_add+2*k+ 1] = [   "-",   "R0",    "LWI", "R2",    "-", "-"]
 rcs_instructions[3][start_add+2*k+ 2] = ["ZERO",  "IMM",   "SADD", "R1",    "-", "123"]
 rcs_instructions[3][start_add+2*k+ 3] = [ "RCT",   "R2",   "SMUL", "R2",    "-", "-"]
diff --git a/hw/vendor/esl_epfl_cgra/utilities/log2file.py b/hw/vendor/esl_epfl_cgra/util/log2file.py
similarity index 100%
rename from hw/vendor/esl_epfl_cgra/utilities/log2file.py
rename to hw/vendor/esl_epfl_cgra/util/log2file.py
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/README.md b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/README.md
new file mode 100644
index 00000000..ea244dc6
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/README.md
@@ -0,0 +1,113 @@
+# Register generator `reggen` and `regtool`
+
+The utility script `regtool.py` and collateral under `reggen` are Python
+tools to read register descriptions in Hjson and generate various output
+formats. The tool can output HTML documentation, standard JSON, compact
+standard JSON (whitespace removed) and Hjson.  The example commands assume
+`$REPO_TOP` is set to the toplevel directory of the repository.
+
+### Setup
+
+If packages have not previously been installed you will need to set a
+few things up. First use `pip3` to install some required packages:
+
+```console
+$ pip3 install --user hjson
+$ pip3 install --user mistletoe
+$ pip3 install --user mako
+```
+
+### Register JSON Format
+
+For details on the register JSON format, see the
+[register tool documentation]({{< relref "doc/rm/register_tool/index.md" >}}).
+To ensure things stay up to date, the register JSON format information
+is documented by the tool itself.
+The documentation can be generated by running the following commands:
+
+```console
+$ cd $REPO_TOP/util
+$ ./build_docs.py
+```
+Under the hood, the `build_docs.py` tool will automatically use the `reggen`
+tool to produce Markdown and processing that into HTML.
+
+### Examples using standalone regtool
+
+Normally for documentation the `build_docs.py` tool will automatically
+use `reggen`. The script `regtool.py` provides a standalone way to run
+`reggen`. See the
+[register tool documentation]({{< relref "doc/rm/register_tool/index.md" >}})
+for details about how to invoke the tool.
+
+The following shows an example of how to generate RTL from a register
+description:
+
+```console
+$ cd $REPO_TOP/util
+$ mkdir /tmp/rtl
+$ ./regtool.py -r -t /tmp/rtl ../hw/ip/uart/data/uart.hjson
+$ ls /tmp/rtl
+    uart_reg_pkg.sv   uart_reg_top.sv
+```
+
+The following shows an example of how to generate a DV UVM class from
+a register description:
+
+```console
+$ cd $REPO_TOP/util
+$ mkdir /tmp/dv
+$ ./regtool.py -s -t /tmp/dv ../hw/ip/uart/data/uart.hjson
+$ ls /tmp/dv
+    uart_ral_pkg.sv
+```
+
+By default, the generated block, register and field models are derived from
+`dv_base_reg` classes provided at `hw/dv/sv/dv_base_reg`. If required, the user
+can supply the `--dv-base-prefix my_base` switch to have the models derive from
+a custom, user-defined RAL classes instead:
+
+```console
+$ cd $REPO_TOP/util
+$ mkdir /tmp/dv
+$ ./regtool.py -s -t /tmp/dv ../hw/ip/uart/data/uart.hjson \
+  --dv-base-prefix my_base
+$ ls /tmp/dv
+    uart_ral_pkg.sv
+```
+
+This makes the following assumptions:
+- A FuseSoC core file aggregating the `my_base` RAL classes with the VLNV
+  name `lowrisc:dv:my_base_reg` is provided in the cores search path.
+- These custom classes are derived from the corresponding `dv_base_reg` classes
+  and have the following names:
+  - `my_base_reg_pkg.sv`: The RAL package that includes the below sources
+  - `my_base_reg_block.sv`: The register block abstraction
+  - `my_base_reg.sv`: The register abstraction
+  - `my_base_reg_field.sv`: The register field abstraction
+  - `my_base_mem.sv`: The memory abstraction
+- If any of the above class specializations is not needed, it can be
+  `typedef`'ed in `my_base_reg_pkg`:
+  ```systemverilog
+  package my_base_reg_pkg;
+    import dv_base_reg_pkg::*;
+    typedef dv_base_reg_field my_base_reg_field;
+    typedef dv_base_mem my_base_mem;
+    `include "my_base_reg.sv"
+    `include "my_base_reg_block.sv"
+  endpackage
+  ```
+
+The following shows an example of how to generate a FPV csr read write assertion
+module from a register description:
+
+```console
+$ cd $REPO_TOP/util
+$ mkdir /tmp/fpv/vip
+$ ./regtool.py -f -t /tmp/fpv/vip ../hw/ip/uart/data/uart.hjson
+$ ls /tmp/fpv
+    uart_csr_assert_fpv.sv
+```
+
+If the target directory is not specified, the tool creates the DV file
+under the `hw/ip/{module}/dv/` directory.
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/__init__.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/access.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/access.py
new file mode 100644
index 00000000..286fc87b
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/access.py
@@ -0,0 +1,121 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""Enumerated types for fields
+Generated by validation, used by backends
+"""
+
+from enum import Enum
+
+from .lib import check_str
+
+
+class JsonEnum(Enum):
+    def for_json(x) -> str:
+        return str(x)
+
+
+class SwWrAccess(JsonEnum):
+    WR = 1
+    NONE = 2
+
+
+class SwRdAccess(JsonEnum):
+    RD = 1
+    RC = 2  # Special handling for port
+    NONE = 3
+
+
+class SwAccess(JsonEnum):
+    RO = 1
+    RW = 2
+    WO = 3
+    W1C = 4
+    W1S = 5
+    W0C = 6
+    RC = 7
+    R0W1C = 8
+    NONE = 9
+
+
+class HwAccess(JsonEnum):
+    HRO = 1
+    HRW = 2
+    HWO = 3
+    NONE = 4  # No access allowed
+
+
+# swaccess permitted values
+# text description, access enum, wr access enum, rd access enum, ok in window
+SWACCESS_PERMITTED = {
+    'none':  ("No access",                                              # noqa: E241
+              SwAccess.NONE, SwWrAccess.NONE, SwRdAccess.NONE, False),  # noqa: E241
+    'ro':    ("Read Only",                                              # noqa: E241
+              SwAccess.RO,   SwWrAccess.NONE, SwRdAccess.RD,   True),   # noqa: E241
+    'rc':    ("Read Only, reading clears",                              # noqa: E241
+              SwAccess.RC,   SwWrAccess.WR,   SwRdAccess.RC,   False),  # noqa: E241
+    'rw':    ("Read/Write",                                             # noqa: E241
+              SwAccess.RW,   SwWrAccess.WR,   SwRdAccess.RD,   True),   # noqa: E241
+    'r0w1c': ("Read zero, Write with 1 clears",                         # noqa: E241
+              SwAccess.W1C,  SwWrAccess.WR,   SwRdAccess.NONE, False),  # noqa: E241
+    'rw1s':  ("Read, Write with 1 sets",                                # noqa: E241
+              SwAccess.W1S,  SwWrAccess.WR,   SwRdAccess.RD,   False),  # noqa: E241
+    'rw1c':  ("Read, Write with 1 clears",                              # noqa: E241
+              SwAccess.W1C,  SwWrAccess.WR,   SwRdAccess.RD,   False),  # noqa: E241
+    'rw0c':  ("Read, Write with 0 clears",                              # noqa: E241
+              SwAccess.W0C,  SwWrAccess.WR,   SwRdAccess.RD,   False),  # noqa: E241
+    'wo':    ("Write Only",                                             # noqa: E241
+              SwAccess.WO,   SwWrAccess.WR,   SwRdAccess.NONE, True)    # noqa: E241
+}
+
+# hwaccess permitted values
+HWACCESS_PERMITTED = {
+    'hro': ("Read Only", HwAccess.HRO),
+    'hrw': ("Read/Write", HwAccess.HRW),
+    'hwo': ("Write Only", HwAccess.HWO),
+    'none': ("No Access Needed", HwAccess.NONE)
+}
+
+
+class SWAccess:
+    def __init__(self, where: str, raw: object):
+        self.key = check_str(raw, 'swaccess for {}'.format(where))
+        try:
+            self.value = SWACCESS_PERMITTED[self.key]
+        except KeyError:
+            raise ValueError('Unknown swaccess key, {}, for {}.'
+                             .format(self.key, where)) from None
+
+    def dv_rights(self) -> str:
+        if self.key in ['none', 'ro', 'rc']:
+            return "RO"
+        elif self.key in ['rw', 'r0w1c', 'rw1s', 'rw1c', 'rw0c']:
+            return "RW"
+        else:
+            assert self.key == 'wo'
+            return "WO"
+
+    def swrd(self) -> SwRdAccess:
+        return self.value[3]
+
+    def allows_read(self) -> bool:
+        return self.value[3] != SwRdAccess.NONE
+
+    def allows_write(self) -> bool:
+        return self.value[2] == SwWrAccess.WR
+
+
+class HWAccess:
+    def __init__(self, where: str, raw: object):
+        self.key = check_str(raw, 'hwaccess for {}'.format(where))
+        try:
+            self.value = HWACCESS_PERMITTED[self.key]
+        except KeyError:
+            raise ValueError('Unknown hwaccess key, {}, for {}.'
+                             .format(self.key, where)) from None
+
+    def allows_read(self) -> bool:
+        return self.key in ['hro', 'hrw']
+
+    def allows_write(self) -> bool:
+        return self.key in ['hrw', 'hwo']
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/alert.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/alert.py
new file mode 100644
index 00000000..a23ff491
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/alert.py
@@ -0,0 +1,54 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict, List
+
+from .bits import Bits
+from .signal import Signal
+from .lib import check_keys, check_name, check_str, check_list
+
+
+class Alert(Signal):
+    def __init__(self, name: str, desc: str, bit: int, fatal: bool):
+        super().__init__(name, desc, Bits(bit, bit))
+        self.bit = bit
+        self.fatal = fatal
+
+    @staticmethod
+    def from_raw(what: str,
+                 lsb: int,
+                 raw: object) -> 'Alert':
+        rd = check_keys(raw, what, ['name', 'desc'], [])
+
+        name = check_name(rd['name'], 'name field of ' + what)
+        desc = check_str(rd['desc'], 'desc field of ' + what)
+
+        # Make sense of the alert name, which should be prefixed with recov_ or
+        # fatal_.
+        pfx = name.split('_')[0]
+        if pfx == 'recov':
+            fatal = False
+        elif pfx == 'fatal':
+            fatal = True
+        else:
+            raise ValueError('Invalid name field of {}: alert names must be '
+                             'prefixed with "recov_" or "fatal_". Saw {!r}.'
+                             .format(what, name))
+
+        return Alert(name, desc, lsb, fatal)
+
+    @staticmethod
+    def from_raw_list(what: str, raw: object) -> List['Alert']:
+        ret = []
+        for idx, entry in enumerate(check_list(raw, what)):
+            entry_what = 'entry {} of {}'.format(idx, what)
+            alert = Alert.from_raw(entry_what, idx, entry)
+            ret.append(alert)
+        return ret
+
+    def _asdict(self) -> Dict[str, object]:
+        return {
+            'name': self.name,
+            'desc': self.desc,
+        }
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bits.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bits.py
new file mode 100644
index 00000000..c8d48f70
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bits.py
@@ -0,0 +1,87 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+'''Support code for bit ranges in reggen'''
+
+from typing import Tuple
+
+from .lib import check_str
+from .params import ReggenParams
+
+
+class Bits:
+    def __init__(self, msb: int, lsb: int):
+        assert 0 <= lsb <= msb
+        self.msb = msb
+        self.lsb = lsb
+
+    def bitmask(self) -> int:
+        return (1 << (self.msb + 1)) - (1 << self.lsb)
+
+    def width(self) -> int:
+        return 1 + self.msb - self.lsb
+
+    def max_value(self) -> int:
+        return (1 << self.width()) - 1
+
+    def extract_field(self, reg_val: int) -> int:
+        return (reg_val & self.bitmask()) >> self.lsb
+
+    @staticmethod
+    def from_raw(where: str,
+                 reg_width: int,
+                 params: ReggenParams,
+                 raw: object) -> 'Bits':
+        # Bits should be specified as msb:lsb or as just a single bit index.
+        if isinstance(raw, int):
+            msb = raw
+            lsb = raw
+        else:
+            str_val = check_str(raw, 'bits field for {}'.format(where))
+            msb, lsb = Bits._parse_str(where, params, str_val)
+
+        # Check that the bit indices look sensible
+        if msb < lsb:
+            raise ValueError('msb for {} is {}: less than {}, the msb.'
+                             .format(where, msb, lsb))
+        if lsb < 0:
+            raise ValueError('lsb for {} is {}, which is negative.'
+                             .format(where, lsb))
+        if msb >= reg_width:
+            raise ValueError("msb for {} is {}, which doesn't fit in {} bits."
+                             .format(where, msb, reg_width))
+
+        return Bits(msb, lsb)
+
+    @staticmethod
+    def _parse_str(where: str,
+                   params: ReggenParams,
+                   str_val: str) -> Tuple[int, int]:
+        try:
+            idx = int(str_val)
+            return (idx, idx)
+        except ValueError:
+            # Doesn't look like an integer. Never mind: try msb:lsb
+            pass
+
+        parts = str_val.split(':')
+        if len(parts) != 2:
+            raise ValueError('bits field for {} is not an '
+                             'integer or of the form msb:lsb. Saw {!r}.'
+                             .format(where, str_val))
+        return (params.expand(parts[0],
+                              'msb of bits field for {}'.format(where)),
+                params.expand(parts[1],
+                              'lsb of bits field for {}'.format(where)))
+
+    def make_translated(self, bit_offset: int) -> 'Bits':
+        assert 0 <= bit_offset
+        return Bits(self.msb + bit_offset, self.lsb + bit_offset)
+
+    def as_str(self) -> str:
+        if self.lsb == self.msb:
+            return str(self.lsb)
+        else:
+            assert self.lsb < self.msb
+            return '{}:{}'.format(self.msb, self.lsb)
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bus_interfaces.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bus_interfaces.py
new file mode 100644
index 00000000..37c5818e
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/bus_interfaces.py
@@ -0,0 +1,187 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+'''Code representing a list of bus interfaces for a block'''
+from enum import Enum
+from typing import Dict, List, Optional, Tuple
+
+from .inter_signal import InterSignal
+from .lib import check_list, check_keys, check_str, check_optional_str
+
+class BusProtocol(Enum):
+    TLUL = "tlul"
+    REG_IFACE = "reg_iface"
+
+    @classmethod
+    def has_value(cls, v):
+        return v in cls._value2member_map_
+
+
+class BusInterfaces:
+    def __init__(self,
+                 has_unnamed_host: bool,
+                 named_hosts: List[str],
+                 has_unnamed_device: bool,
+                 named_devices: List[str],
+                 interface_list: List[Dict]):
+        assert has_unnamed_device or named_devices
+        assert len(named_hosts) == len(set(named_hosts))
+        assert len(named_devices) == len(set(named_devices))
+
+        self.has_unnamed_host = has_unnamed_host
+        self.named_hosts = named_hosts
+        self.has_unnamed_device = has_unnamed_device
+        self.named_devices = named_devices
+        self.interface_list = interface_list
+
+    @staticmethod
+    def from_raw(raw: object, where: str) -> 'BusInterfaces':
+        has_unnamed_host = False
+        named_hosts = []
+        interface_list = []
+
+        has_unnamed_device = False
+        named_devices = []
+
+        for idx, raw_entry in enumerate(check_list(raw, where)):
+            entry_what = 'entry {} of {}'.format(idx + 1, where)
+            ed = check_keys(raw_entry, entry_what,
+                            ['protocol', 'direction'],
+                            ['name'])
+
+            protocol = check_str(ed['protocol'],
+                                 'protocol field of ' + entry_what)
+            if not BusProtocol.has_value(protocol):
+                raise ValueError('Unknown protocol {!r} at {}'
+                                 .format(protocol, entry_what))
+
+            direction = check_str(ed['direction'],
+                                  'direction field of ' + entry_what)
+            if direction not in ['device', 'host']:
+                raise ValueError('Unknown interface direction {!r} at {}'
+                                 .format(direction, entry_what))
+
+            name = check_optional_str(ed.get('name'),
+                                      'name field of ' + entry_what)
+
+            if direction == 'host':
+                if name is None:
+                    if has_unnamed_host:
+                        raise ValueError('Multiple un-named host '
+                                         'interfaces at {}'
+                                         .format(where))
+                    has_unnamed_host = True
+                else:
+                    if name in named_hosts:
+                        raise ValueError('Duplicate host interface '
+                                         'with name {!r} at {}'
+                                         .format(name, where))
+                    named_hosts.append(name)
+            else:
+                if name is None:
+                    if has_unnamed_device:
+                        raise ValueError('Multiple un-named device '
+                                         'interfaces at {}'
+                                         .format(where))
+                    has_unnamed_device = True
+                else:
+                    if name in named_devices:
+                        raise ValueError('Duplicate device interface '
+                                         'with name {!r} at {}'
+                                         .format(name, where))
+                    named_devices.append(name)
+            interface_list.append({'name': name, 'protocol': BusProtocol(protocol), 'is_host': direction=='host'})
+
+        if not (has_unnamed_device or named_devices):
+            raise ValueError('No device interface at ' + where)
+
+        return BusInterfaces(has_unnamed_host, named_hosts,
+                             has_unnamed_device, named_devices, interface_list)
+
+    def has_host(self) -> bool:
+        return bool(self.has_unnamed_host or self.named_hosts)
+
+    def _interfaces(self) -> List[Tuple[bool, Optional[str]]]:
+        ret = []  # type: List[Tuple[bool, Optional[str]]]
+        if self.has_unnamed_host:
+            ret.append((True, None))
+        for name in self.named_hosts:
+            ret.append((True, name))
+
+        if self.has_unnamed_device:
+            ret.append((False, None))
+        for name in self.named_devices:
+            ret.append((False, name))
+
+        return ret
+
+    @staticmethod
+    def _if_dict(is_host: bool, name: Optional[str]) -> Dict[str, object]:
+        ret = {
+            'protocol': 'tlul',
+            'direction': 'host' if is_host else 'device'
+        }  # type: Dict[str, object]
+
+        if name is not None:
+            ret['name'] = name
+
+        return ret
+
+    def as_dicts(self) -> List[Dict[str, object]]:
+        return [BusInterfaces._if_dict(is_host, name)
+                for is_host, name in self._interfaces()]
+
+    def get_port_name(self, is_host: bool, name: Optional[str]) -> str:
+        if is_host:
+            tl_suffix = 'tl_h'
+        else:
+            tl_suffix = 'tl_d' if self.has_host() else 'tl'
+
+        return (tl_suffix if name is None
+                else '{}_{}'.format(name, tl_suffix))
+
+    def get_port_names(self, inc_hosts: bool, inc_devices: bool) -> List[str]:
+        ret = []
+        for is_host, name in self._interfaces():
+            if not (inc_hosts if is_host else inc_devices):
+                continue
+            ret.append(self.get_port_name(is_host, name))
+        return ret
+
+    def _if_inter_signal(self,
+                         is_host: bool,
+                         name: Optional[str]) -> InterSignal:
+        return InterSignal(self.get_port_name(is_host, name),
+                           None, 'tl', 'tlul_pkg', 'req_rsp', 'rsp', 1, None)
+
+    def inter_signals(self) -> List[InterSignal]:
+        return [self._if_inter_signal(is_host, name)
+                for is_host, name in self._interfaces()]
+
+    def has_interface(self, is_host: bool, name: Optional[str]) -> bool:
+        if is_host:
+            if name is None:
+                return self.has_unnamed_host
+            else:
+                return name in self.named_hosts
+        else:
+            if name is None:
+                return self.has_unnamed_device
+            else:
+                return name in self.named_devices
+
+    def find_port_name(self, is_host: bool, name: Optional[str]) -> str:
+        '''Look up the given host/name pair and return its port name.
+
+        Raises a KeyError if there is no match.
+
+        '''
+        if not self.has_interface(is_host, name):
+            called = ('with no name'
+                      if name is None else 'called {!r}'.format(name))
+            raise KeyError('There is no {} bus interface {}.'
+                           .format('host' if is_host else 'device',
+                                   called))
+
+        return self.get_port_name(is_host, name)
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/enum_entry.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/enum_entry.py
new file mode 100644
index 00000000..fe1e9ecd
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/enum_entry.py
@@ -0,0 +1,35 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict
+
+from .lib import check_keys, check_str, check_int
+
+REQUIRED_FIELDS = {
+    'name': ['s', "name of the member of the enum"],
+    'desc': ['t', "description when field has this value"],
+    'value': ['d', "value of this member of the enum"]
+}
+
+
+class EnumEntry:
+    def __init__(self, where: str, max_val: int, raw: object):
+        rd = check_keys(raw, where,
+                        list(REQUIRED_FIELDS.keys()),
+                        [])
+
+        self.name = check_str(rd['name'], 'name field of {}'.format(where))
+        self.desc = check_str(rd['desc'], 'desc field of {}'.format(where))
+        self.value = check_int(rd['value'], 'value field of {}'.format(where))
+        if not (0 <= self.value <= max_val):
+            raise ValueError("value for {} is {}, which isn't representable "
+                             "in the field (representable range: 0 .. {})."
+                             .format(where, self.value, max_val))
+
+    def _asdict(self) -> Dict[str, object]:
+        return {
+            'name': self.name,
+            'desc': self.desc,
+            'value': str(self.value)
+        }
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/field.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/field.py
new file mode 100644
index 00000000..a2beb735
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/field.py
@@ -0,0 +1,291 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict, List, Optional
+
+from .access import SWAccess, HWAccess
+from .bits import Bits
+from .enum_entry import EnumEntry
+from .lib import (check_keys, check_str, check_name,
+                  check_list, check_str_list, check_xint)
+from .params import ReggenParams
+
+REQUIRED_FIELDS = {
+    'bits': ['b', "bit or bit range (msb:lsb)"]
+}
+
+OPTIONAL_FIELDS = {
+    'name': ['s', "name of the field"],
+    'desc': ['t', "description of field (required if the field has a name)"],
+    'swaccess': [
+        's', "software access permission, copied from "
+        "register if not provided in field. "
+        "(Tool adds if not provided.)"
+    ],
+    'hwaccess': [
+        's', "hardware access permission, copied from "
+        "register if not prvided in field. "
+        "(Tool adds if not provided.)"
+    ],
+    'resval': [
+        'x', "reset value, comes from register resval "
+        "if not provided in field. Zero if neither "
+        "are provided and the field is readable, "
+        "x if neither are provided and the field "
+        "is wo. Must match if both are provided."
+    ],
+    'enum': ['l', "list of permitted enumeration groups"],
+    'tags': [
+        's',
+        "tags for the field, followed by the format 'tag_name:item1:item2...'"
+    ]
+}
+
+
+class Field:
+    def __init__(self,
+                 name: str,
+                 desc: Optional[str],
+                 tags: List[str],
+                 swaccess: SWAccess,
+                 hwaccess: HWAccess,
+                 hwqe: bool,
+                 hwre: bool,
+                 bits: Bits,
+                 resval: Optional[int],
+                 enum: Optional[List[EnumEntry]]):
+        self.name = name
+        self.desc = desc
+        self.tags = tags
+        self.swaccess = swaccess
+        self.hwaccess = hwaccess
+        self.hwqe = hwqe
+        self.hwre = hwre
+        self.bits = bits
+        self.resval = resval
+        self.enum = enum
+
+    @staticmethod
+    def from_raw(reg_name: str,
+                 field_idx: int,
+                 num_fields: int,
+                 default_swaccess: SWAccess,
+                 default_hwaccess: HWAccess,
+                 reg_resval: Optional[int],
+                 reg_width: int,
+                 reg_hwqe: bool,
+                 reg_hwre: bool,
+                 params: ReggenParams,
+                 raw: object) -> 'Field':
+        where = 'field {} of {} register'.format(field_idx, reg_name)
+        rd = check_keys(raw, where,
+                        list(REQUIRED_FIELDS.keys()),
+                        list(OPTIONAL_FIELDS.keys()))
+
+        raw_name = rd.get('name')
+        if raw_name is None:
+            name = ('field{}'.format(field_idx + 1)
+                    if num_fields > 1 else reg_name)
+        else:
+            name = check_name(raw_name, 'name of {}'.format(where))
+
+        raw_desc = rd.get('desc')
+        if raw_desc is None and raw_name is not None:
+            raise ValueError('Missing desc field for {}'
+                             .format(where))
+        if raw_desc is None:
+            desc = None
+        else:
+            desc = check_str(raw_desc, 'desc field for {}'.format(where))
+
+        tags = check_str_list(rd.get('tags', []),
+                              'tags for {}'.format(where))
+
+        raw_swaccess = rd.get('swaccess')
+        if raw_swaccess is not None:
+            swaccess = SWAccess(where, raw_swaccess)
+        else:
+            swaccess = default_swaccess
+
+        raw_hwaccess = rd.get('hwaccess')
+        if raw_hwaccess is not None:
+            hwaccess = HWAccess(where, raw_hwaccess)
+        else:
+            hwaccess = default_hwaccess
+
+        bits = Bits.from_raw(where, reg_width, params, rd['bits'])
+
+        raw_resval = rd.get('resval')
+        if raw_resval is None:
+            # The field doesn't define a reset value. Use bits from reg_resval
+            # if it's defined, otherwise None (which means "x").
+            if reg_resval is None:
+                resval = None
+            else:
+                resval = bits.extract_field(reg_resval)
+        else:
+            # The field does define a reset value. It should be an integer or
+            # 'x'. In the latter case, we set resval to None (as above).
+            resval = check_xint(raw_resval, 'resval field for {}'.format(where))
+            if resval is None:
+                # We don't allow a field to be explicitly 'x' on reset but for
+                # the containing register to have a reset value.
+                if reg_resval is not None:
+                    raise ValueError('resval field for {} is "x", but the '
+                                     'register defines a resval as well.'
+                                     .format(where))
+            else:
+                # Check that the reset value is representable with bits
+                if not (0 <= resval <= bits.max_value()):
+                    raise ValueError("resval field for {} is {}, which "
+                                     "isn't representable as an unsigned "
+                                     "{}-bit integer."
+                                     .format(where, resval, bits.width()))
+
+                # If the register had a resval, check this value matches it.
+                if reg_resval is not None:
+                    resval_from_reg = bits.extract_field(reg_resval)
+                    if resval != resval_from_reg:
+                        raise ValueError('resval field for {} is {}, but the '
+                                         'register defines a resval as well, '
+                                         'where bits {}:{} would give {}.'
+                                         .format(where, resval,
+                                                 bits.msb, bits.lsb,
+                                                 resval_from_reg))
+
+        raw_enum = rd.get('enum')
+        if raw_enum is None:
+            enum = None
+        else:
+            enum = []
+            raw_entries = check_list(raw_enum,
+                                     'enum field for {}'.format(where))
+            enum_val_to_name = {}  # type: Dict[int, str]
+            for idx, raw_entry in enumerate(raw_entries):
+                entry = EnumEntry('entry {} in enum list for {}'
+                                  .format(idx + 1, where),
+                                  bits.max_value(),
+                                  raw_entry)
+                if entry.value in enum_val_to_name:
+                    raise ValueError('In {}, duplicate enum entries for '
+                                     'value {} ({} and {}).'
+                                     .format(where,
+                                             entry.value,
+                                             enum_val_to_name[entry.value],
+                                             entry.name))
+                enum.append(entry)
+                enum_val_to_name[entry.value] = entry.name
+
+        return Field(name, desc, tags,
+                     swaccess, hwaccess,
+                     reg_hwqe, reg_hwre, bits, resval, enum)
+
+    def has_incomplete_enum(self) -> bool:
+        return (self.enum is not None and
+                len(self.enum) != 1 + self.bits.max_value())
+
+    def get_n_bits(self, hwext: bool, bittype: List[str]) -> int:
+        '''Get the size of this field in bits
+
+        bittype should be a list of the types of signals to count. The elements
+        should come from the following list:
+
+        - 'q': A signal for the value of the field. Only needed if HW can read
+          its contents.
+
+        - 'd': A signal for the next value of the field. Only needed if HW can
+          write its contents.
+
+        - 'qe': A write enable signal for bus accesses. Only needed if HW can
+          read the field's contents and the field has the hwqe flag.
+
+        - 're': A read enable signal for bus accesses. Only needed if HW can
+          read the field's contents and the field has the hwre flag.
+
+        - 'de': A write enable signal for hardware accesses. Only needed if HW
+          can write the field's contents and the register data is stored in the
+          register block (true if the hwext flag is false).
+
+        '''
+        n_bits = 0
+        if "q" in bittype and self.hwaccess.allows_read():
+            n_bits += self.bits.width()
+        if "d" in bittype and self.hwaccess.allows_write():
+            n_bits += self.bits.width()
+        if "qe" in bittype and self.hwaccess.allows_read():
+            n_bits += int(self.hwqe)
+        if "re" in bittype and self.hwaccess.allows_read():
+            n_bits += int(self.hwre)
+        if "de" in bittype and self.hwaccess.allows_write():
+            n_bits += int(not hwext)
+        return n_bits
+
+    def make_multi(self,
+                   reg_width: int,
+                   min_reg_idx: int,
+                   max_reg_idx: int,
+                   cname: str,
+                   creg_idx: int,
+                   stripped: bool) -> List['Field']:
+        assert 0 <= min_reg_idx <= max_reg_idx
+
+        # Check that we won't overflow reg_width. We assume that the LSB should
+        # be preserved: if msb=5, lsb=2 then the replicated copies will be
+        # [5:2], [11:8] etc.
+        num_copies = 1 + max_reg_idx - min_reg_idx
+        field_width = self.bits.msb + 1
+
+        if field_width * num_copies > reg_width:
+            raise ValueError('Cannot replicate field {} {} times: the '
+                             'resulting width would be {}, but the register '
+                             'width is just {}.'
+                             .format(self.name, num_copies,
+                                     field_width * num_copies, reg_width))
+
+        desc = ('For {}{}'.format(cname, creg_idx)
+                if stripped else self.desc)
+        enum = None if stripped else self.enum
+
+        ret = []
+        for reg_idx in range(min_reg_idx, max_reg_idx + 1):
+            name = '{}_{}'.format(self.name, reg_idx)
+
+            bit_offset = field_width * (reg_idx - min_reg_idx)
+            bits = (self.bits
+                    if bit_offset == 0
+                    else self.bits.make_translated(bit_offset))
+
+            ret.append(Field(name, desc,
+                             self.tags, self.swaccess, self.hwaccess,
+                             self.hwqe, self.hwre, bits, self.resval, enum))
+
+        return ret
+
+    def make_suffixed(self, suffix: str,
+                      cname: str,
+                      creg_idx: int,
+                      stripped: bool) -> 'Field':
+        desc = ('For {}{}'.format(cname, creg_idx)
+                if stripped else self.desc)
+        enum = None if stripped else self.enum
+
+        return Field(self.name + suffix,
+                     desc, self.tags, self.swaccess, self.hwaccess,
+                     self.hwqe, self.hwre, self.bits, self.resval, enum)
+
+    def _asdict(self) -> Dict[str, object]:
+        rd = {
+            'bits': self.bits.as_str(),
+            'name': self.name,
+            'swaccess': self.swaccess.key,
+            'hwaccess': self.hwaccess.key,
+            'resval': 'x' if self.resval is None else str(self.resval),
+            'tags': self.tags
+        }  # type: Dict[str, object]
+
+        if self.desc is not None:
+            rd['desc'] = self.desc
+        if self.enum is not None:
+            rd['enum'] = self.enum
+        return rd
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/fpv_csr.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/fpv_csr.sv.tpl
new file mode 100644
index 00000000..01f20c73
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/fpv_csr.sv.tpl
@@ -0,0 +1,177 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// FPV CSR read and write assertions auto-generated by `reggen` containing data structure
+// Do Not Edit directly
+// TODO: This automation currently only support register without HW write access
+<%
+  from reggen import (gen_fpv)
+  from reggen.register import Register
+
+  from topgen import lib
+
+  lblock = block.name.lower()
+  use_reg_iface = any([interface['protocol'] == BusProtocol.REG_IFACE and not interace['is_host'] for interface in block.bus_interfaces.interface_list])
+
+  # This template shouldn't be instantiated if the device interface
+  # doesn't actually have any registers.
+  assert rb.flat_regs
+
+%>\
+<%def name="construct_classes(block)">\
+
+% if use_reg_iface:
+`include "common_cells/assertions.svh"
+% else:
+`include "prim_assert.sv"
+% endif
+`ifdef UVM
+  import uvm_pkg::*;
+`endif
+
+// Block: ${lblock}
+module ${mod_base}_csr_assert_fpv import tlul_pkg::*;
+    import top_pkg::*;(
+  input clk_i,
+  input rst_ni,
+
+  // tile link ports
+  input tl_h2d_t h2d,
+  input tl_d2h_t d2h
+);
+<%
+  addr_width = rb.get_addr_width()
+  addr_msb  = addr_width - 1
+  hro_regs_list = [r for r in rb.flat_regs if not r.hwaccess.allows_write()]
+  num_hro_regs = len(hro_regs_list)
+  hro_map = {r.offset: (idx, r) for idx, r in enumerate(hro_regs_list)}
+%>\
+
+// Currently FPV csr assertion only support HRO registers.
+% if num_hro_regs > 0:
+`ifndef VERILATOR
+`ifndef SYNTHESIS
+
+  parameter bit[3:0] MAX_A_SOURCE = 10; // used for FPV only to reduce runtime
+
+  typedef struct packed {
+    logic [TL_DW-1:0] wr_data;
+    logic [TL_AW-1:0] addr;
+    logic             wr_pending;
+    logic             rd_pending;
+  } pend_item_t;
+
+  bit disable_sva;
+
+  // mask register to convert byte to bit
+  logic [TL_DW-1:0] a_mask_bit;
+
+  assign a_mask_bit[7:0]   = h2d.a_mask[0] ? '1 : '0;
+  assign a_mask_bit[15:8]  = h2d.a_mask[1] ? '1 : '0;
+  assign a_mask_bit[23:16] = h2d.a_mask[2] ? '1 : '0;
+  assign a_mask_bit[31:24] = h2d.a_mask[3] ? '1 : '0;
+
+  bit [${addr_msb}-2:0] hro_idx; // index for exp_vals
+  bit [${addr_msb}:0]   normalized_addr;
+
+  // Map register address with hro_idx in exp_vals array.
+  always_comb begin: decode_hro_addr_to_idx
+    unique case (pend_trans[d2h.d_source].addr)
+% for idx, r in hro_map.values():
+      ${r.offset}: hro_idx <= ${idx};
+% endfor
+      // If the register is not a HRO register, the write data will all update to this default idx.
+      default: hro_idx <= ${num_hro_regs + 1};
+    endcase
+  end
+
+  // store internal expected values for HW ReadOnly registers
+  logic [TL_DW-1:0] exp_vals[${num_hro_regs + 1}];
+
+  `ifdef FPV_ON
+    pend_item_t [MAX_A_SOURCE:0] pend_trans;
+  `else
+    pend_item_t [2**TL_AIW-1:0] pend_trans;
+  `endif
+
+  // normalized address only take the [${addr_msb}:2] address from the TLUL a_address
+  assign normalized_addr = {h2d.a_address[${addr_msb}:2], 2'b0};
+
+% if num_hro_regs > 0:
+  // for write HRO registers, store the write data into exp_vals
+  always_ff @(negedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+       pend_trans <= '0;
+  % for hro_reg in hro_regs_list:
+       exp_vals[${hro_map.get(hro_reg.offset)[0]}] <= ${hro_reg.resval};
+  % endfor
+    end else begin
+      if (h2d.a_valid && d2h.a_ready) begin
+        pend_trans[h2d.a_source].addr <= normalized_addr;
+        if (h2d.a_opcode inside {PutFullData, PutPartialData}) begin
+          pend_trans[h2d.a_source].wr_data <= h2d.a_data & a_mask_bit;
+          pend_trans[h2d.a_source].wr_pending <= 1'b1;
+        end else if (h2d.a_opcode == Get) begin
+          pend_trans[h2d.a_source].rd_pending <= 1'b1;
+        end
+      end
+      if (d2h.d_valid) begin
+        if (pend_trans[d2h.d_source].wr_pending == 1) begin
+          if (!d2h.d_error) begin
+            exp_vals[hro_idx] <= pend_trans[d2h.d_source].wr_data;
+          end
+          pend_trans[d2h.d_source].wr_pending <= 1'b0;
+        end
+        if (h2d.d_ready && pend_trans[d2h.d_source].rd_pending == 1) begin
+          pend_trans[d2h.d_source].rd_pending <= 1'b0;
+        end
+      end
+    end
+  end
+
+  // for read HRO registers, assert read out values by access policy and exp_vals
+  % for hro_reg in hro_regs_list:
+<%
+    r_name       = hro_reg.name.lower()
+    reg_addr     = hro_reg.offset
+    reg_addr_hex = format(reg_addr, 'x')
+    regwen       = hro_reg.regwen
+    reg_mask     = 0
+
+    for f in hro_reg.get_field_list():
+      f_access = f.swaccess.key.lower()
+      if f_access == "rw" and regwen == None:
+        reg_mask = reg_mask | f.bits.bitmask()
+%>\
+    % if reg_mask != 0:
+<%  reg_mask_hex = format(reg_mask, 'x') %>\
+  `ASSERT(${r_name}_rd_A, d2h.d_valid && pend_trans[d2h.d_source].rd_pending &&
+         pend_trans[d2h.d_source].addr == ${addr_width}'h${reg_addr_hex} |->
+         d2h.d_error ||
+         (d2h.d_data & 'h${reg_mask_hex}) == (exp_vals[${hro_map.get(reg_addr)[0]}] & 'h${reg_mask_hex}))
+
+    % endif
+  % endfor
+% endif
+
+  // This FPV only assumption is to reduce the FPV runtime.
+  `ASSUME_FPV(TlulSource_M, h2d.a_source >=  0 && h2d.a_source <= MAX_A_SOURCE, clk_i, !rst_ni)
+
+  `ifdef UVM
+    initial forever begin
+      bit csr_assert_en;
+      uvm_config_db#(bit)::wait_modified(null, "%m", "csr_assert_en");
+      if (!uvm_config_db#(bit)::get(null, "%m", "csr_assert_en", csr_assert_en)) begin
+        `uvm_fatal("csr_assert", "Can't find csr_assert_en")
+      end
+      disable_sva = !csr_assert_en;
+    end
+  `endif
+
+`endif
+`endif
+% endif
+endmodule
+</%def>\
+${construct_classes(block)}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cfg_html.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cfg_html.py
new file mode 100644
index 00000000..0bb44d3d
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cfg_html.py
@@ -0,0 +1,113 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""
+Generate HTML documentation from Block
+"""
+
+from typing import TextIO
+
+from .ip_block import IpBlock
+from .html_helpers import render_td
+from .signal import Signal
+
+
+def genout(outfile: TextIO, msg: str) -> None:
+    outfile.write(msg)
+
+
+def name_width(x: Signal) -> str:
+    if x.bits.width() == 1:
+        return x.name
+
+    return '{}[{}:0]'.format(x.name, x.bits.msb)
+
+
+def gen_kv(outfile: TextIO, key: str, value: str) -> None:
+    genout(outfile,
+           '<p><i>{}:</i> {}</p>\n'.format(key, value))
+
+
+def gen_cfg_html(cfgs: IpBlock, outfile: TextIO) -> None:
+    rnames = cfgs.get_rnames()
+
+    ot_server = 'https://docs.opentitan.org'
+    comport_url = ot_server + '/doc/rm/comportability_specification'
+    genout(outfile,
+           '<p>Referring to the <a href="{url}">Comportable guideline for '
+           'peripheral device functionality</a>, the module '
+           '<b><code>{mod_name}</code></b> has the following hardware '
+           'interfaces defined.</p>\n'
+           .format(url=comport_url, mod_name=cfgs.name))
+
+    # clocks
+    gen_kv(outfile,
+           'Primary Clock',
+           '<b><code>{}</code></b>'.format(cfgs.clock_signals[0]))
+    if len(cfgs.clock_signals) > 1:
+        other_clocks = ['<b><code>{}</code></b>'.format(clk)
+                        for clk in cfgs.clock_signals[1:]]
+        gen_kv(outfile, 'Other Clocks', ', '.join(other_clocks))
+    else:
+        gen_kv(outfile, 'Other Clocks', '<i>none</i>')
+
+    # bus interfaces
+    dev_ports = ['<b><code>{}</code></b>'.format(port)
+                 for port in cfgs.bus_interfaces.get_port_names(False, True)]
+    assert dev_ports
+    gen_kv(outfile, 'Bus Device Interfaces (TL-UL)', ', '.join(dev_ports))
+
+    host_ports = ['<b><code>{}</code></b>'.format(port)
+                  for port in cfgs.bus_interfaces.get_port_names(True, False)]
+    if host_ports:
+        gen_kv(outfile, 'Bus Host Interfaces (TL-UL)', ', '.join(host_ports))
+    else:
+        gen_kv(outfile, 'Bus Host Interfaces (TL-UL)', '<i>none</i>')
+
+    # IO
+    ios = ([('input', x) for x in cfgs.xputs[1]] +
+           [('output', x) for x in cfgs.xputs[2]] +
+           [('inout', x) for x in cfgs.xputs[0]])
+    if ios:
+        genout(outfile, "<p><i>Peripheral Pins for Chip IO:</i></p>\n")
+        genout(
+            outfile, "<table class=\"cfgtable\"><tr>" +
+            "<th>Pin name</th><th>direction</th>" +
+            "<th>Description</th></tr>\n")
+        for direction, x in ios:
+            genout(outfile,
+                   '<tr><td>{}</td><td>{}</td>{}</tr>'
+                   .format(name_width(x),
+                           direction,
+                           render_td(x.desc, rnames, None)))
+        genout(outfile, "</table>\n")
+    else:
+        genout(outfile, "<p><i>Peripheral Pins for Chip IO: none</i></p>\n")
+
+    if not cfgs.interrupts:
+        genout(outfile, "<p><i>Interrupts: none</i></p>\n")
+    else:
+        genout(outfile, "<p><i>Interrupts:</i></p>\n")
+        genout(
+            outfile, "<table class=\"cfgtable\"><tr><th>Interrupt Name</th>" +
+            "<th>Description</th></tr>\n")
+        for x in cfgs.interrupts:
+            genout(outfile,
+                   '<tr><td>{}</td>{}</tr>'
+                   .format(name_width(x),
+                           render_td(x.desc, rnames, None)))
+        genout(outfile, "</table>\n")
+
+    if not cfgs.alerts:
+        genout(outfile, "<p><i>Security Alerts: none</i></p>\n")
+    else:
+        genout(outfile, "<p><i>Security Alerts:</i></p>\n")
+        genout(
+            outfile, "<table class=\"cfgtable\"><tr><th>Alert Name</th>" +
+            "<th>Description</th></tr>\n")
+        for x in cfgs.alerts:
+            genout(outfile,
+                   '<tr><td>{}</td>{}</tr>'
+                   .format(x.name,
+                           render_td(x.desc, rnames, None)))
+        genout(outfile, "</table>\n")
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cheader.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cheader.py
new file mode 100644
index 00000000..f68bd396
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_cheader.py
@@ -0,0 +1,439 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""
+Generate C header from validated register JSON tree
+"""
+
+import io
+import logging as log
+import sys
+import textwrap
+import warnings
+from typing import List, Optional, Set, TextIO
+
+
+from .field import Field
+from .ip_block import IpBlock
+from .params import LocalParam
+from .register import Register
+from .multi_register import MultiRegister
+from .signal import Signal
+from .window import Window
+
+
+def genout(outfile: TextIO, msg: str) -> None:
+    outfile.write(msg)
+
+def to_snake_case(s: str) -> str:
+    val = []
+    for i, ch in enumerate(s):
+      if i > 0 and ch.isupper():
+        val.append('_')
+      val.append(ch)
+    return ''.join(val)
+
+def as_define(s: str) -> str:
+    s = s.upper()
+    r = ''
+    for i in range(0, len(s)):
+        r += s[i] if s[i].isalnum() else '_'
+    return r
+
+
+def first_line(s: str) -> str:
+    """Returns the first line of a multi-line string"""
+    return s.splitlines()[0]
+
+
+def format_comment(s: str) -> str:
+    """Formats a string to comment wrapped to an 80 character line width
+
+    Returns wrapped string including newline and // comment characters.
+    """
+    return '\n'.join(
+        textwrap.wrap(
+            s, width=77, initial_indent='// ', subsequent_indent='// ')) + '\n'
+
+
+def gen_define(name: str,
+               args: List[str],
+               body: str,
+               existing_defines: Set[str],
+               indent: str = '  ') -> str:
+    r"""Produces a #define string, will split into two lines if a single line
+    has a width greater than 80 characters. Result includes newline.
+
+    Arguments:
+    name - Name of the #define
+    args - List of arguments for the define, provide an empty list if there are
+        none
+    body - Body of the #define
+    existing_defines - set of already generated define names.
+        Error if `name` is in `existing_defines`.
+    indent - Gives string to prepend on any new lines produced by
+    wrapping (default '  ')
+
+    Example result:
+    name = 'A_MACRO'
+    args = ['arg1', 'arg2'],
+    body = 'arg1 + arg2 + 10'
+
+    #define A_MACRO(arg1, arg2) arg1 + arg2 + 10
+
+    When the macro is wrapped the break happens after the argument list (or
+    macro name if there is no argument list
+
+    #define A_MACRO(arg1, arg2) \
+      arg1 + arg2 + 10
+
+    """
+
+    if name in existing_defines:
+        log.error("Duplicate #define for " + name)
+        sys.exit(1)
+
+    if len(args) != 0:
+        define_declare = '#define ' + name + '(' + ', '.join(args) + ')'
+    else:
+        define_declare = '#define ' + name
+
+    oneline_define = define_declare + ' ' + body
+
+    existing_defines.add(name)
+
+    if len(oneline_define) <= 80:
+        return oneline_define + '\n'
+
+    return define_declare + ' \\\n' + indent + body + '\n'
+
+
+def gen_cdefine_register(outstr: TextIO,
+                         reg: Register,
+                         comp: str,
+                         width: int,
+                         rnames: Set[str],
+                         existing_defines: Set[str]) -> None:
+    rname = reg.name
+    offset = reg.offset
+
+    genout(outstr, format_comment(first_line(reg.desc)))
+    defname = as_define(comp + '_' + rname)
+    genout(
+        outstr,
+        gen_define(defname + '_REG_OFFSET', [], hex(offset), existing_defines))
+
+    for field in reg.fields:
+        dname = defname + '_' + as_define(field.name)
+        field_width = field.bits.width()
+
+        if field_width == 1:
+            # single bit
+            genout(
+                outstr,
+                gen_define(dname + '_BIT', [], str(field.bits.lsb),
+                           existing_defines))
+        else:
+            # multiple bits (unless it is the whole register)
+            if field_width != width:
+                mask = field.bits.bitmask() >> field.bits.lsb
+                genout(
+                    outstr,
+                    gen_define(dname + '_MASK', [], hex(mask),
+                               existing_defines))
+                genout(
+                    outstr,
+                    gen_define(dname + '_OFFSET', [], str(field.bits.lsb),
+                               existing_defines))
+                genout(
+                    outstr,
+                    gen_define(
+                        dname + '_FIELD', [],
+                        '((bitfield_field32_t) {{ .mask = {dname}_MASK, .index = {dname}_OFFSET }})'
+                        .format(dname=dname), existing_defines))
+            if field.enum is not None:
+                for enum in field.enum:
+                    ename = as_define(enum.name)
+                    value = hex(enum.value)
+                    genout(
+                        outstr,
+                        gen_define(
+                            defname + '_' + as_define(field.name) +
+                            '_VALUE_' + ename, [], value, existing_defines))
+    genout(outstr, '\n')
+    return
+
+
+def gen_cdefine_window(outstr: TextIO,
+                       win: Window,
+                       comp: str,
+                       regwidth: int,
+                       rnames: Set[str],
+                       existing_defines: Set[str]) -> None:
+    offset = win.offset
+
+    genout(outstr, format_comment('Memory area: ' + first_line(win.desc)))
+    defname = as_define(comp + '_' + win.name)
+    genout(
+        outstr,
+        gen_define(defname + '_REG_OFFSET', [], hex(offset), existing_defines))
+    items = win.items
+    genout(
+        outstr,
+        gen_define(defname + '_SIZE_WORDS', [], str(items), existing_defines))
+    items = items * (regwidth // 8)
+    genout(
+        outstr,
+        gen_define(defname + '_SIZE_BYTES', [], str(items), existing_defines))
+
+    wid = win.validbits
+    if (wid != regwidth):
+        mask = (1 << wid) - 1
+        genout(outstr,
+               gen_define(defname + '_MASK ', [], hex(mask), existing_defines))
+
+
+def gen_cdefines_module_param(outstr: TextIO,
+                              param: LocalParam,
+                              module_name: str,
+                              existing_defines: Set[str]) -> None:
+    # Presently there is only one type (int), however if the new types are
+    # added, they potentially need to be handled differently.
+    known_types = ["int"]
+    if param.param_type not in known_types:
+        warnings.warn("Cannot generate a module define of type {}"
+                      .format(param.param_type))
+        return
+
+    if param.desc is not None:
+        genout(outstr, format_comment(first_line(param.desc)))
+    # Heuristic: if the name already has underscores, it's already snake_case,
+    # otherwise, assume StudlyCaps and covert it to snake_case.
+    param_name = param.name if '_' in param.name else to_snake_case(param.name)
+    define_name = as_define(module_name + '_PARAM_' + param_name)
+    if param.param_type == "int":
+        define = gen_define(define_name, [], param.value,
+                            existing_defines)
+
+    genout(outstr, define)
+    genout(outstr, '\n')
+
+
+def gen_cdefines_module_params(outstr: TextIO,
+                               module_data: IpBlock,
+                               module_name: str,
+                               register_width: int,
+                               existing_defines: Set[str]) -> None:
+    module_params = module_data.params
+
+    for param in module_params.get_localparams():
+        gen_cdefines_module_param(outstr, param, module_name, existing_defines)
+
+    genout(outstr, format_comment(first_line("Register width")))
+    define_name = as_define(module_name + '_PARAM_REG_WIDTH')
+    define = gen_define(define_name, [], str(register_width), existing_defines)
+    genout(outstr, define)
+    genout(outstr, '\n')
+
+
+def gen_multireg_field_defines(outstr: TextIO,
+                               regname: str,
+                               field: Field,
+                               subreg_num: int,
+                               regwidth: int,
+                               existing_defines: Set[str]) -> None:
+    field_width = field.bits.width()
+    fields_per_reg = regwidth // field_width
+
+    define_name = regname + '_' + as_define(field.name + "_FIELD_WIDTH")
+    define = gen_define(define_name, [], str(field_width), existing_defines)
+    genout(outstr, define)
+
+    define_name = regname + '_' + as_define(field.name + "_FIELDS_PER_REG")
+    define = gen_define(define_name, [], str(fields_per_reg), existing_defines)
+    genout(outstr, define)
+
+    define_name = regname + "_MULTIREG_COUNT"
+    define = gen_define(define_name, [], str(subreg_num), existing_defines)
+    genout(outstr, define)
+
+    genout(outstr, '\n')
+
+
+def gen_cdefine_multireg(outstr: TextIO,
+                         multireg: MultiRegister,
+                         component: str,
+                         regwidth: int,
+                         rnames: Set[str],
+                         existing_defines: Set[str]) -> None:
+    comment = multireg.reg.desc + " (common parameters)"
+    genout(outstr, format_comment(first_line(comment)))
+    if len(multireg.reg.fields) == 1:
+        regname = as_define(component + '_' + multireg.reg.name)
+        gen_multireg_field_defines(outstr, regname, multireg.reg.fields[0],
+                                   len(multireg.regs), regwidth, existing_defines)
+    else:
+        log.warn("Non-homogeneous multireg " + multireg.reg.name +
+                 " skip multireg specific data generation.")
+
+    for subreg in multireg.regs:
+        gen_cdefine_register(outstr, subreg, component, regwidth, rnames,
+                             existing_defines)
+
+
+def gen_cdefines_interrupt_field(outstr: TextIO,
+                                 interrupt: Signal,
+                                 component: str,
+                                 regwidth: int,
+                                 existing_defines: Set[str]) -> None:
+    fieldlsb = interrupt.bits.lsb
+    iname = interrupt.name
+    defname = as_define(component + '_INTR_COMMON_' + iname)
+
+    if interrupt.bits.width() == 1:
+        # single bit
+        genout(
+            outstr,
+            gen_define(defname + '_BIT', [], str(fieldlsb), existing_defines))
+    else:
+        # multiple bits (unless it is the whole register)
+        if interrupt.bits.width() != regwidth:
+            mask = interrupt.bits.msb >> fieldlsb
+            genout(
+                outstr,
+                gen_define(defname + '_MASK', [], hex(mask), existing_defines))
+            genout(
+                outstr,
+                gen_define(defname + '_OFFSET', [], str(fieldlsb),
+                           existing_defines))
+            genout(
+                outstr,
+                gen_define(
+                    defname + '_FIELD', [],
+                    '((bitfield_field32_t) {{ .mask = {dname}_MASK, .index = {dname}_OFFSET }})'
+                    .format(dname=defname), existing_defines))
+
+
+def gen_cdefines_interrupts(outstr: TextIO,
+                            block: IpBlock,
+                            component: str,
+                            regwidth: int,
+                            existing_defines: Set[str]) -> None:
+    # If no_auto_intr_regs is true, then we do not generate common defines,
+    # because the bit offsets for a particular interrupt may differ between
+    # the interrupt enable/state/test registers.
+    if block.no_auto_intr:
+        return
+
+    genout(outstr, format_comment(first_line("Common Interrupt Offsets")))
+    for intr in block.interrupts:
+        gen_cdefines_interrupt_field(outstr, intr, component, regwidth,
+                                     existing_defines)
+    genout(outstr, '\n')
+
+
+def gen_cdefines(block: IpBlock,
+                 outfile: TextIO,
+                 src_lic: Optional[str],
+                 src_copy: str) -> int:
+    rnames = block.get_rnames()
+
+    outstr = io.StringIO()
+
+    # This tracks the defines that have been generated so far, so we
+    # can error if we attempt to duplicate a definition
+    existing_defines = set()  # type: Set[str]
+
+    gen_cdefines_module_params(outstr, block, block.name, block.regwidth,
+                               existing_defines)
+
+    gen_cdefines_interrupts(outstr, block, block.name, block.regwidth,
+                            existing_defines)
+
+    for rb in block.reg_blocks.values():
+        for x in rb.entries:
+            if isinstance(x, Register):
+                gen_cdefine_register(outstr, x, block.name, block.regwidth, rnames,
+                                     existing_defines)
+                continue
+
+            if isinstance(x, MultiRegister):
+                gen_cdefine_multireg(outstr, x, block.name, block.regwidth, rnames,
+                                     existing_defines)
+                continue
+
+            if isinstance(x, Window):
+                gen_cdefine_window(outstr, x, block.name, block.regwidth,
+                                   rnames, existing_defines)
+                continue
+
+    generated = outstr.getvalue()
+    outstr.close()
+
+    genout(outfile, '// Generated register defines for ' + block.name + '\n\n')
+    if src_copy != '':
+        genout(outfile, '// Copyright information found in source file:\n')
+        genout(outfile, '// ' + src_copy + '\n\n')
+    if src_lic is not None:
+        genout(outfile, '// Licensing information found in source file:\n')
+        for line in src_lic.splitlines():
+            genout(outfile, '// ' + line + '\n')
+        genout(outfile, '\n')
+
+    # Header Include Guard
+    genout(outfile, '#ifndef _' + as_define(block.name) + '_REG_DEFS_\n')
+    genout(outfile, '#define _' + as_define(block.name) + '_REG_DEFS_\n\n')
+
+    # Header Extern Guard (so header can be used from C and C++)
+    genout(outfile, '#ifdef __cplusplus\n')
+    genout(outfile, 'extern "C" {\n')
+    genout(outfile, '#endif\n')
+
+    genout(outfile, generated)
+
+    # Header Extern Guard
+    genout(outfile, '#ifdef __cplusplus\n')
+    genout(outfile, '}  // extern "C"\n')
+    genout(outfile, '#endif\n')
+
+    # Header Include Guard
+    genout(outfile, '#endif  // _' + as_define(block.name) + '_REG_DEFS_\n')
+
+    genout(outfile, '// End generated register defines for ' + block.name)
+
+    return 0
+
+
+def test_gen_define() -> None:
+    basic_oneline = '#define MACRO_NAME body\n'
+    assert gen_define('MACRO_NAME', [], 'body', set()) == basic_oneline
+
+    basic_oneline_with_args = '#define MACRO_NAME(arg1, arg2) arg1 + arg2\n'
+    assert (gen_define('MACRO_NAME', ['arg1', 'arg2'], 'arg1 + arg2',
+                       set()) == basic_oneline_with_args)
+
+    long_macro_name = 'A_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_VERY_LONG_MACRO_NAME'
+
+    multiline = ('#define ' + long_macro_name + ' \\\n' +
+                 '  a_fairly_long_body + something_else + 10\n')
+
+    assert (gen_define(long_macro_name, [],
+                       'a_fairly_long_body + something_else + 10',
+                       set()) == multiline)
+
+    multiline_with_args = ('#define ' + long_macro_name +
+                           '(arg1, arg2, arg3) \\\n' +
+                           '  a_fairly_long_body + arg1 + arg2 + arg3\n')
+
+    assert (gen_define(long_macro_name, ['arg1', 'arg2', 'arg3'],
+                       'a_fairly_long_body + arg1 + arg2 + arg3',
+                       set()) == multiline_with_args)
+
+    multiline_with_args_big_indent = (
+        '#define ' + long_macro_name + '(arg1, arg2, arg3) \\\n' +
+        '    a_fairly_long_body + arg1 + arg2 + arg3\n')
+
+    assert (gen_define(long_macro_name, ['arg1', 'arg2', 'arg3'],
+                       'a_fairly_long_body + arg1 + arg2 + arg3',
+                       set(),
+                       indent='    ') == multiline_with_args_big_indent)
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_dv.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_dv.py
new file mode 100644
index 00000000..d2d054ad
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_dv.py
@@ -0,0 +1,108 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+'''Generate DV code for an IP block'''
+
+import logging as log
+import os
+from typing import List
+
+import yaml
+
+from mako import exceptions  # type: ignore
+from mako.lookup import TemplateLookup  # type: ignore
+from pkg_resources import resource_filename
+
+from .ip_block import IpBlock
+from .register import Register
+from .window import Window
+
+
+def bcname(esc_if_name: str) -> str:
+    '''Get the name of the dv_base_reg_block subclass for this device interface'''
+    return esc_if_name + "_reg_block"
+
+
+def rcname(esc_if_name: str, r: Register) -> str:
+    '''Get the name of the dv_base_reg subclass for this register'''
+    return '{}_reg_{}'.format(esc_if_name, r.name.lower())
+
+
+def mcname(esc_if_name: str, m: Window) -> str:
+    '''Get the name of the dv_base_mem subclass for this memory'''
+    return '{}_mem_{}'.format(esc_if_name, m.name.lower())
+
+
+def miname(m: Window) -> str:
+    '''Get the lower-case name of a memory block'''
+    return m.name.lower()
+
+
+def gen_core_file(outdir: str,
+                  lblock: str,
+                  dv_base_prefix: str,
+                  paths: List[str]) -> None:
+    depends = ["lowrisc:dv:dv_base_reg"]
+    if dv_base_prefix and dv_base_prefix != "dv_base":
+        depends.append("lowrisc:dv:{}_reg".format(dv_base_prefix))
+
+    # Generate a fusesoc core file that points at the files we've just
+    # generated.
+    core_data = {
+        'name': "lowrisc:dv:{}_ral_pkg".format(lblock),
+        'filesets': {
+            'files_dv': {
+                'depend': depends,
+                'files': paths,
+                'file_type': 'systemVerilogSource'
+            },
+        },
+        'targets': {
+            'default': {
+                'filesets': [
+                    'files_dv',
+                ],
+            },
+        },
+    }
+    core_file_path = os.path.join(outdir, lblock + '_ral_pkg.core')
+    with open(core_file_path, 'w') as core_file:
+        core_file.write('CAPI=2:\n')
+        yaml.dump(core_data, core_file, encoding='utf-8')
+
+
+def gen_dv(block: IpBlock, dv_base_prefix: str, outdir: str) -> int:
+    '''Generate DV files for an IpBlock'''
+
+    lookup = TemplateLookup(directories=[resource_filename('reggen', '.')])
+    uvm_reg_tpl = lookup.get_template('uvm_reg.sv.tpl')
+
+    # Generate the RAL package(s). For a device interface with no name we
+    # generate the package "<block>_ral_pkg" (writing to <block>_ral_pkg.sv).
+    # In any other case, we also need the interface name, giving
+    # <block>_<ifname>_ral_pkg.
+    generated = []
+
+    lblock = block.name.lower()
+    for if_name, rb in block.reg_blocks.items():
+        hier_path = '' if block.hier_path is None else block.hier_path + '.'
+        if_suffix = '' if if_name is None else '_' + if_name.lower()
+        mod_base = lblock + if_suffix
+        reg_block_path = hier_path + 'u_reg' + if_suffix
+
+        file_name = mod_base + '_ral_pkg.sv'
+        generated.append(file_name)
+        reg_top_path = os.path.join(outdir, file_name)
+        with open(reg_top_path, 'w', encoding='UTF-8') as fout:
+            try:
+                fout.write(uvm_reg_tpl.render(rb=rb,
+                                              block=block,
+                                              esc_if_name=mod_base,
+                                              reg_block_path=reg_block_path,
+                                              dv_base_prefix=dv_base_prefix))
+            except:  # noqa F722 for template Exception handling
+                log.error(exceptions.text_error_template().render())
+                return 1
+
+    gen_core_file(outdir, lblock, dv_base_prefix, generated)
+    return 0
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_fpv.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_fpv.py
new file mode 100644
index 00000000..e6e6d7d3
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_fpv.py
@@ -0,0 +1,81 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+# # Lint as: python3
+#
+"""Generate FPV CSR read and write assertions from IpBlock
+"""
+
+import logging as log
+import os.path
+
+import yaml
+from mako import exceptions
+from mako.template import Template
+from pkg_resources import resource_filename
+
+from .ip_block import IpBlock
+
+
+def gen_fpv(block: IpBlock, outdir):
+    # Read Register templates
+    fpv_csr_tpl = Template(
+        filename=resource_filename('reggen', 'fpv_csr.sv.tpl'))
+
+    # Generate a module with CSR assertions for each device interface. For a
+    # device interface with no name, we generate <block>_csr_assert_fpv. For a
+    # named interface, we generate <block>_<ifname>_csr_assert_fpv.
+    lblock = block.name.lower()
+    generated = []
+    for if_name, rb in block.reg_blocks.items():
+        if not rb.flat_regs:
+            # No registers to check!
+            continue
+
+        if if_name is None:
+            mod_base = lblock
+        else:
+            mod_base = lblock + '_' + if_name.lower()
+
+        mod_name = mod_base + '_csr_assert_fpv'
+        filename = mod_name + '.sv'
+        generated.append(filename)
+        reg_top_path = os.path.join(outdir, filename)
+        with open(reg_top_path, 'w', encoding='UTF-8') as fout:
+            try:
+                fout.write(fpv_csr_tpl.render(block=block,
+                                              mod_base=mod_base,
+                                              if_name=if_name,
+                                              rb=rb))
+            except:  # noqa F722 for template Exception handling
+                log.error(exceptions.text_error_template().render())
+                return 1
+
+    # Generate a fusesoc core file that points at the files we've just
+    # generated.
+    core_data = {
+        'name': "lowrisc:fpv:{}_csr_assert".format(lblock),
+        'filesets': {
+            'files_dv': {
+                'depend': [
+                    "lowrisc:tlul:headers",
+                    "lowrisc:prim:assert",
+                ],
+                'files': generated,
+                'file_type': 'systemVerilogSource'
+            },
+        },
+        'targets': {
+            'default': {
+                'filesets': [
+                    'files_dv',
+                ],
+            },
+        },
+    }
+    core_file_path = os.path.join(outdir, lblock + '_csr_assert_fpv.core')
+    with open(core_file_path, 'w') as core_file:
+        core_file.write('CAPI=2:\n')
+        yaml.dump(core_data, core_file, encoding='utf-8')
+
+    return 0
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_html.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_html.py
new file mode 100644
index 00000000..e8c427b1
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_html.py
@@ -0,0 +1,325 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""
+Generate HTML documentation from IpBlock
+"""
+
+from typing import Set, TextIO
+
+from .ip_block import IpBlock
+from .html_helpers import expand_paras, render_td
+from .multi_register import MultiRegister
+from .reg_block import RegBlock
+from .register import Register
+from .window import Window
+
+
+def genout(outfile: TextIO, msg: str) -> None:
+    outfile.write(msg)
+
+
+# Generation of HTML table with register bit-field summary picture
+# Max 16-bit wide on one line
+
+
+def gen_tbl_row(outfile: TextIO, msb: int, width: int, close: bool) -> None:
+    if (close):
+        genout(outfile, "</tr>\n")
+    genout(outfile, "<tr>")
+    for x in range(msb, msb - width, -1):
+        genout(outfile, "<td class=\"bitnum\">" + str(x) + "</td>")
+
+    genout(outfile, "</tr><tr>")
+
+
+def gen_html_reg_pic(outfile: TextIO, reg: Register, width: int) -> None:
+
+    if (width > 32):
+        bsize = 3
+        nextbit = 63
+        hdrbits = 16
+        nextline = 48
+    elif (width > 16):
+        bsize = 3
+        nextbit = 31
+        hdrbits = 16
+        nextline = 16
+    elif (width > 8):
+        bsize = 3
+        nextbit = 15
+        nextline = 0
+        hdrbits = 16
+    else:
+        bsize = 12
+        nextbit = 7
+        nextline = 0
+        hdrbits = 8
+
+    genout(outfile, "<table class=\"regpic\">")
+    gen_tbl_row(outfile, nextbit, hdrbits, False)
+
+    for field in reversed(reg.fields):
+        fieldlsb = field.bits.lsb
+        fieldwidth = field.bits.width()
+        fieldmsb = field.bits.msb
+        fname = field.name
+
+        while nextbit > fieldmsb:
+            if (nextbit >= nextline) and (fieldmsb < nextline):
+                spans = nextbit - (nextline - 1)
+            else:
+                spans = nextbit - fieldmsb
+            genout(
+                outfile, "<td class=\"unused\" colspan=" + str(spans) +
+                ">&nbsp;</td>\n")
+            if (nextbit >= nextline) and (fieldmsb < nextline):
+                nextbit = nextline - 1
+                gen_tbl_row(outfile, nextbit, hdrbits, True)
+                nextline = nextline - 16
+            else:
+                nextbit = fieldmsb
+
+        while (fieldmsb >= nextline) and (fieldlsb < nextline):
+            spans = fieldmsb - (nextline - 1)
+            genout(
+                outfile, "<td class=\"fname\" colspan=" + str(spans) + ">" +
+                fname + "...</td>\n")
+            fname = "..." + field.name
+            fieldwidth = fieldwidth - spans
+            fieldmsb = nextline - 1
+            nextline = nextline - 16
+            gen_tbl_row(outfile, fieldmsb, hdrbits, True)
+
+        namelen = len(fname)
+        if namelen == 0 or fname == ' ':
+            fname = "&nbsp;"
+        if (namelen > bsize * fieldwidth):
+            usestyle = (" style=\"font-size:" + str(
+                (bsize * 100 * fieldwidth) / namelen) + "%\"")
+        else:
+            usestyle = ""
+
+        genout(
+            outfile, "<td class=\"fname\" colspan=" + str(fieldwidth) +
+            usestyle + ">" + fname + "</td>\n")
+
+        if (fieldlsb == nextline) and nextline > 0:
+            gen_tbl_row(outfile, nextline - 1, hdrbits, True)
+            nextline = nextline - 16
+
+        nextbit = fieldlsb - 1
+    while (nextbit > 0):
+        spans = nextbit - (nextline - 1)
+        genout(outfile,
+               "<td class=\"unused\" colspan=" + str(spans) + ">&nbsp;</td>\n")
+        nextbit = nextline - 1
+        if (nextline > 0):
+            gen_tbl_row(outfile, nextline - 1, hdrbits, True)
+            nextline = nextline - 16
+
+    genout(outfile, "</tr></table>")
+
+
+# Generation of HTML table with header, register picture and details
+
+
+def gen_html_register(outfile: TextIO,
+                      reg: Register,
+                      comp: str,
+                      width: int,
+                      rnames: Set[str]) -> None:
+    rname = reg.name
+    offset = reg.offset
+    regwen_div = ''
+    if reg.regwen is not None:
+        regwen_div = ('    <div>Register enable = {}</div>\n'
+                      .format(reg.regwen))
+
+    desc_paras = expand_paras(reg.desc, rnames)
+    desc_head = desc_paras[0]
+    desc_body = desc_paras[1:]
+
+    genout(outfile,
+           '<table class="regdef" id="Reg_{lrname}">\n'
+           ' <tr>\n'
+           '  <th class="regdef" colspan=5>\n'
+           '   <div>{comp}.{rname} @ {off:#x}</div>\n'
+           '   <div>{desc}</div>\n'
+           '   <div>Reset default = {resval:#x}, mask {mask:#x}</div>\n'
+           '{wen}'
+           '  </th>\n'
+           ' </tr>\n'
+           .format(lrname=rname.lower(),
+                   comp=comp,
+                   rname=rname,
+                   off=offset,
+                   desc=desc_head,
+                   resval=reg.resval,
+                   mask=reg.resmask,
+                   wen=regwen_div))
+    if desc_body:
+        genout(outfile,
+               '<tr><td colspan=5>{}</td></tr>'
+               .format(''.join(desc_body)))
+
+    genout(outfile, "<tr><td colspan=5>")
+    gen_html_reg_pic(outfile, reg, width)
+    genout(outfile, "</td></tr>\n")
+
+    genout(outfile, "<tr><th width=5%>Bits</th>")
+    genout(outfile, "<th width=5%>Type</th>")
+    genout(outfile, "<th width=5%>Reset</th>")
+    genout(outfile, "<th>Name</th>")
+    genout(outfile, "<th>Description</th></tr>")
+    nextbit = 0
+    fcount = 0
+
+    for field in reg.fields:
+        fcount += 1
+        fname = field.name
+
+        fieldlsb = field.bits.lsb
+        if fieldlsb > nextbit:
+            genout(outfile, "<tr><td class=\"regbits\">")
+            if (nextbit == (fieldlsb - 1)):
+                genout(outfile, str(nextbit))
+            else:
+                genout(outfile, str(fieldlsb - 1) + ":" + str(nextbit))
+            genout(outfile,
+                   "</td><td></td><td></td><td></td><td>Reserved</td></tr>")
+        genout(outfile, "<tr><td class=\"regbits\">" + field.bits.as_str() + "</td>")
+        genout(outfile, "<td class=\"regperm\">" + field.swaccess.key + "</td>")
+        genout(
+            outfile, "<td class=\"regrv\">" +
+            ('x' if field.resval is None else hex(field.resval)) +
+            "</td>")
+        genout(outfile, "<td class=\"regfn\">" + fname + "</td>")
+
+        # Collect up any description and enum table
+        desc_parts = []
+
+        if field.desc is not None:
+            desc_parts += expand_paras(field.desc, rnames)
+
+        if field.enum is not None:
+            desc_parts.append('<table>')
+            for enum in field.enum:
+                enum_desc_paras = expand_paras(enum.desc, rnames)
+                desc_parts.append('<tr>'
+                                  '<td>{val}</td>'
+                                  '<td>{name}</td>'
+                                  '<td>{desc}</td>'
+                                  '</tr>\n'
+                                  .format(val=enum.value,
+                                          name=enum.name,
+                                          desc=''.join(enum_desc_paras)))
+            desc_parts.append('</table>')
+            if field.has_incomplete_enum():
+                desc_parts.append("<p>Other values are reserved.</p>")
+
+        genout(outfile,
+               '<td class="regde">{}</td>'.format(''.join(desc_parts)))
+        nextbit = fieldlsb + field.bits.width()
+
+    genout(outfile, "</table>\n<br>\n")
+
+
+def gen_html_window(outfile: TextIO,
+                    win: Window,
+                    comp: str,
+                    regwidth: int,
+                    rnames: Set[str]) -> None:
+    wname = win.name or '(unnamed window)'
+    offset = win.offset
+    genout(outfile,
+           '<table class="regdef" id="Reg_{lwname}">\n'
+           '  <tr>\n'
+           '    <th class="regdef">\n'
+           '      <div>{comp}.{wname} @ + {off:#x}</div>\n'
+           '      <div>{items} item {swaccess} window</div>\n'
+           '      <div>Byte writes are {byte_writes}supported</div>\n'
+           '    </th>\n'
+           '  </tr>\n'
+           .format(comp=comp,
+                   wname=wname,
+                   lwname=wname.lower(),
+                   off=offset,
+                   items=win.items,
+                   swaccess=win.swaccess.key,
+                   byte_writes=('' if win.byte_write else '<i>not</i> ')))
+    genout(outfile, '<tr><td><table class="regpic">')
+    genout(outfile, '<tr><td width="10%"></td>')
+    wid = win.validbits
+
+    for x in range(regwidth - 1, -1, -1):
+        if x == regwidth - 1 or x == wid - 1 or x == 0:
+            genout(outfile, '<td class="bitnum">' + str(x) + '</td>')
+        else:
+            genout(outfile, '<td class="bitnum"></td>')
+    genout(outfile, '</tr>')
+    tblmax = win.items - 1
+    for x in [0, 1, 2, tblmax - 1, tblmax]:
+        if x == 2:
+            genout(
+                outfile, '<tr><td>&nbsp;</td><td align=center colspan=' +
+                str(regwidth) + '>...</td></tr>')
+        else:
+            genout(
+                outfile, '<tr><td class="regbits">+' +
+                hex(offset + x * (regwidth // 8)) + '</td>')
+            if wid < regwidth:
+                genout(
+                    outfile, '<td class="unused" colspan=' +
+                    str(regwidth - wid) + '>&nbsp;</td>\n')
+                genout(
+                    outfile,
+                    '<td class="fname" colspan=' + str(wid) + '>&nbsp;</td>\n')
+            else:
+                genout(
+                    outfile, '<td class="fname" colspan=' + str(regwidth) +
+                    '>&nbsp;</td>\n')
+            genout(outfile, '</tr>')
+    genout(outfile, '</td></tr></table>')
+    genout(outfile,
+           '<tr>{}</tr>'.format(render_td(win.desc, rnames, 'regde')))
+    genout(outfile, "</table>\n<br>\n")
+
+
+def gen_html_reg_block(outfile: TextIO,
+                       rb: RegBlock,
+                       comp: str,
+                       width: int,
+                       rnames: Set[str]) -> None:
+    for x in rb.entries:
+        if isinstance(x, Register):
+            gen_html_register(outfile, x, comp, width, rnames)
+        elif isinstance(x, MultiRegister):
+            for reg in x.regs:
+                gen_html_register(outfile, reg, comp, width, rnames)
+        else:
+            assert isinstance(x, Window)
+            gen_html_window(outfile, x, comp, width, rnames)
+
+
+def gen_html(block: IpBlock, outfile: TextIO) -> int:
+    rnames = block.get_rnames()
+
+    assert block.reg_blocks
+    # Handle the case where there's just one interface
+    if len(block.reg_blocks) == 1:
+        rb = list(block.reg_blocks.values())[0]
+        gen_html_reg_block(outfile, rb, block.name, block.regwidth, rnames)
+        return 0
+
+    # Handle the case where there is more than one device interface and,
+    # correspondingly, more than one reg block.
+    for iface_name, rb in block.reg_blocks.items():
+        iface_desc = ('device interface <code>{}</code>'.format(iface_name)
+                      if iface_name is not None
+                      else 'the unnamed device interface')
+        genout(outfile,
+               '<h3>Registers visible under {}</h3>'.format(iface_desc))
+        gen_html_reg_block(outfile, rb, block.name, block.regwidth, rnames)
+
+    return 0
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_json.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_json.py
new file mode 100644
index 00000000..c593cc1c
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_json.py
@@ -0,0 +1,34 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""Generate JSON/compact JSON/Hjson from register JSON tree
+"""
+
+import hjson
+
+
+def gen_json(obj, outfile, format):
+    if format == 'json':
+        hjson.dumpJSON(obj,
+                       outfile,
+                       ensure_ascii=False,
+                       use_decimal=True,
+                       indent='  ',
+                       for_json=True)
+    elif format == 'compact':
+        hjson.dumpJSON(obj,
+                       outfile,
+                       ensure_ascii=False,
+                       for_json=True,
+                       use_decimal=True,
+                       separators=(',', ':'))
+    elif format == 'hjson':
+        hjson.dump(obj,
+                   outfile,
+                   ensure_ascii=False,
+                   for_json=True,
+                   use_decimal=True)
+    else:
+        raise ValueError('Invalid JSON format ' + format)
+
+    return 0
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_rtl.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_rtl.py
new file mode 100644
index 00000000..14c9b4ba
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_rtl.py
@@ -0,0 +1,136 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""Generate SystemVerilog designs from IpBlock object"""
+
+import logging as log
+import os
+from typing import Dict, Optional, Tuple
+
+from mako import exceptions  # type: ignore
+from mako.template import Template  # type: ignore
+from pkg_resources import resource_filename
+
+from .ip_block import IpBlock
+from .multi_register import MultiRegister
+from .reg_base import RegBase
+from .register import Register
+
+
+def escape_name(name: str) -> str:
+    return name.lower().replace(' ', '_')
+
+
+def make_box_quote(msg: str, indent: str = '  ') -> str:
+    hr = indent + ('/' * (len(msg) + 6))
+    middle = indent + '// ' + msg + ' //'
+    return '\n'.join([hr, middle, hr])
+
+
+def _get_awparam_name(iface_name: Optional[str]) -> str:
+    return (iface_name or 'Iface').capitalize() + 'Aw'
+
+
+def get_addr_widths(block: IpBlock) -> Dict[Optional[str], Tuple[str, int]]:
+    '''Return the address widths for the device interfaces
+
+    Returns a dictionary keyed by interface name whose values are pairs:
+    (paramname, width) where paramname is IfaceAw for an unnamed interface and
+    FooAw for an interface called foo. This is constructed in the same order as
+    block.reg_blocks.
+
+    If there is a single device interface and that interface is unnamed, use
+    the more general parameter name "BlockAw".
+
+    '''
+    assert block.reg_blocks
+    if len(block.reg_blocks) == 1 and None in block.reg_blocks:
+        return {None: ('BlockAw', block.reg_blocks[None].get_addr_width())}
+
+    return {name: (_get_awparam_name(name), rb.get_addr_width())
+            for name, rb in block.reg_blocks.items()}
+
+
+def get_type_name_pfx(block: IpBlock, iface_name: Optional[str]) -> str:
+    return block.name.lower() + ('' if iface_name is None
+                                 else '_{}'.format(iface_name.lower()))
+
+
+def get_r0(reg: RegBase) -> Register:
+    '''Get a Register representing an entry in the RegBase'''
+    if isinstance(reg, Register):
+        return reg
+    else:
+        assert isinstance(reg, MultiRegister)
+        return reg.reg
+
+
+def get_iface_tx_type(block: IpBlock,
+                      iface_name: Optional[str],
+                      hw2reg: bool) -> str:
+    x2x = 'hw2reg' if hw2reg else 'reg2hw'
+    pfx = get_type_name_pfx(block, iface_name)
+    return '_'.join([pfx, x2x, 't'])
+
+
+def get_reg_tx_type(block: IpBlock, reg: RegBase, hw2reg: bool) -> str:
+    '''Get the name of the hw2reg or reg2hw type for reg'''
+    if isinstance(reg, Register):
+        r0 = reg
+        type_suff = 'reg_t'
+    else:
+        assert isinstance(reg, MultiRegister)
+        r0 = reg.reg
+        type_suff = 'mreg_t'
+
+    x2x = 'hw2reg' if hw2reg else 'reg2hw'
+    return '_'.join([block.name.lower(),
+                     x2x,
+                     r0.name.lower(),
+                     type_suff])
+
+
+def gen_rtl(block: IpBlock, outdir: str) -> int:
+    # Read Register templates
+    reg_top_tpl = Template(
+        filename=resource_filename('reggen', 'reg_top.sv.tpl'))
+    reg_pkg_tpl = Template(
+        filename=resource_filename('reggen', 'reg_pkg.sv.tpl'))
+
+    # Generate <block>_reg_pkg.sv
+    #
+    # This defines the various types used to interface between the *_reg_top
+    # module(s) and the block itself.
+    reg_pkg_path = os.path.join(outdir, block.name.lower() + "_reg_pkg.sv")
+    with open(reg_pkg_path, 'w', encoding='UTF-8') as fout:
+        try:
+            fout.write(reg_pkg_tpl.render(block=block))
+        except:  # noqa F722 for template Exception handling
+            log.error(exceptions.text_error_template().render())
+            return 1
+
+    # Generate the register block implementation(s). For a device interface
+    # with no name we generate the register module "<block>_reg_top" (writing
+    # to <block>_reg_top.sv). In any other case, we also need the interface
+    # name, giving <block>_<ifname>_reg_top.
+    lblock = block.name.lower()
+    for if_name, rb in block.reg_blocks.items():
+        if if_name is None:
+            mod_base = lblock
+        else:
+            mod_base = lblock + '_' + if_name.lower()
+
+        mod_name = mod_base + '_reg_top'
+        reg_top_path = os.path.join(outdir, mod_name + '.sv')
+        with open(reg_top_path, 'w', encoding='UTF-8') as fout:
+            try:
+                fout.write(reg_top_tpl.render(block=block,
+                                              mod_base=mod_base,
+                                              mod_name=mod_name,
+                                              if_name=if_name,
+                                              rb=rb))
+            except:  # noqa F722 for template Exception handling
+                log.error(exceptions.text_error_template().render())
+                return 1
+
+    return 0
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_selfdoc.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_selfdoc.py
new file mode 100644
index 00000000..5f38404a
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/gen_selfdoc.py
@@ -0,0 +1,306 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""
+Generates the documentation for the register tool
+
+"""
+from .access import SWACCESS_PERMITTED, HWACCESS_PERMITTED
+from reggen import (validate,
+                    ip_block, enum_entry, field,
+                    register, multi_register, window)
+
+
+def genout(outfile, msg):
+    outfile.write(msg)
+
+
+doc_intro = """
+
+<!-- Start of output generated by `regtool.py --doc` -->
+
+The tables describe each key and the type of the value. The following
+types are used:
+
+Type | Description
+---- | -----------
+"""
+
+swaccess_intro = """
+
+Register fields are tagged using the swaccess key to describe the
+permitted access and side-effects. This key must have one of these
+values:
+
+"""
+
+hwaccess_intro = """
+
+Register fields are tagged using the hwaccess key to describe the
+permitted access from hardware logic and side-effects. This key must
+have one of these values:
+
+"""
+
+top_example = """
+The basic structure of a register definition file is thus:
+
+```hjson
+{
+  name: "GP",
+  regwidth: "32",
+  registers: [
+    // register definitions...
+  ]
+}
+
+```
+
+"""
+
+register_example = """
+
+The basic register definition group will follow this pattern:
+
+```hjson
+    { name: "REGA",
+      desc: "Description of register",
+      swaccess: "rw",
+      resval: "42",
+      fields: [
+        // bit field definitions...
+      ]
+    }
+```
+
+The name and brief description are required. If the swaccess key is
+provided it describes the access pattern that will be used by all
+bitfields in the register that do not override with their own swaccess
+key. This is a useful shortcut because in most cases a register will
+have the same access restrictions for all fields. The reset value of
+the register may also be provided here or in the individual fields. If
+it is provided in both places then they must match, if it is provided
+in neither place then the reset value defaults to zero for all except
+write-only fields when it defaults to x.
+
+"""
+
+field_example = """
+
+Field names should be relatively short because they will be used
+frequently (and need to fit in the register layout picture!) The field
+description is expected to be longer and will most likely make use of
+the Hjson ability to include multi-line strings. An example with three
+fields:
+
+```hjson
+    fields: [
+      { bits: "15:0",
+        name: "RXS",
+        desc: '''
+        Last 16 oversampled values of RX. These are captured at 16x the baud
+        rate clock. This is a shift register with the most recent bit in
+        bit 0 and the oldest in bit 15. Only valid when ENRXS is set.
+        '''
+      }
+      { bits: "16",
+        name: "ENRXS",
+        desc: '''
+          If this bit is set the receive oversampled data is collected
+          in the RXS field.
+        '''
+      }
+      {bits: "20:19", name: "TXILVL",
+       desc: "Trigger level for TX interrupts",
+       resval: "2",
+       enum: [
+               { value: "0", name: "txlvl1", desc: "1 character" },
+               { value: "1", name: "txlvl4", desc: "4 characters" },
+               { value: "2", name: "txlvl8", desc: "8 characters" },
+               { value: "3", name: "txlvl16", desc: "16 characters" }
+             ]
+      }
+    ]
+```
+
+In all of these the swaccess parameter is inherited from the register
+level, and will be added so this key is always available to the
+backend. The RXS and ENRXS will default to zero reset value (unless
+something different is provided for the register) and will have the
+key added, but TXILVL expicitly sets its reset value as 2.
+
+The missing bits 17 and 18 will be treated as reserved by the tool, as
+will any bits between 21 and the maximum in the register.
+
+The TXILVL is an example using an enumeration to specify all valid
+values for the field. In this case all possible values are described,
+if the list is incomplete then the field is marked with the rsvdenum
+key so the backend can take appropriate action. (If the enum field is
+more than 7 bits then the checking is not done.)
+
+"""
+
+offset_intro = """
+
+"""
+
+multi_intro = """
+
+The multireg expands on the register required fields and will generate
+a list of the generated registers (that contain all required and
+generated keys for an actual register).
+
+"""
+
+window_intro = """
+
+A window defines an open region of the register space that can be used
+for things that are not registers (for example access to a buffer ram).
+
+"""
+
+regwen_intro = """
+
+Registers can protect themselves from software writes by using the
+register attribute regwen. When not an emptry string (the default
+value), regwen indicates that another register must be true in order
+to allow writes to this register.  This is useful for the prevention
+of software modification.  The register-enable register (call it
+REGWEN) must be one bit in width, and should default to 1 and be rw1c
+for preferred security control.  This allows all writes to proceed
+until at some point software disables future modifications by clearing
+REGWEN. An error is reported if REGWEN does not exist, contains more
+than one bit, is not `rw1c` or does not default to 1. One REGWEN can
+protect multiple registers. The REGWEN register must precede those
+registers that refer to it in the .hjson register list. An example:
+
+```hjson
+    { name: "REGWEN",
+      desc: "Register write enable for a bank of registers",
+      swaccess: "rw1c",
+      fields: [ { bits: "0", resval: "1" } ]
+    }
+    { name: "REGA",
+      swaccess: "rw",
+      regwen: "REGWEN",
+      ...
+    }
+    { name: "REGB",
+      swaccess: "rw",
+      regwen: "REGWEN",
+      ...
+    }
+```
+"""
+
+doc_tail = """
+
+(end of output generated by `regtool.py --doc`)
+
+"""
+
+
+def doc_tbl_head(outfile, use):
+    if use is not None:
+        genout(outfile, "\nKey | Kind | Type | Description of Value\n")
+        genout(outfile, "--- | ---- | ---- | --------------------\n")
+    else:
+        genout(outfile, "\nKey | Description\n")
+        genout(outfile, "--- | -----------\n")
+
+
+def doc_tbl_line(outfile, key, use, desc):
+    if use is not None:
+        desc_key, desc_txt = desc
+        val_type = (validate.val_types[desc_key][0]
+                    if desc_key is not None else None)
+    else:
+        assert isinstance(desc, str)
+        val_type = None
+        desc_txt = desc
+
+    if val_type is not None:
+        genout(
+            outfile, '{} | {} | {} | {}\n'.format(key, validate.key_use[use],
+                                                  val_type, desc_txt))
+    else:
+        genout(outfile, key + " | " + desc_txt + "\n")
+
+
+def document(outfile):
+    genout(outfile, doc_intro)
+    for x in validate.val_types:
+        genout(
+            outfile,
+            validate.val_types[x][0] + " | " + validate.val_types[x][1] + "\n")
+
+    genout(outfile, swaccess_intro)
+    doc_tbl_head(outfile, None)
+    for key, value in SWACCESS_PERMITTED.items():
+        doc_tbl_line(outfile, key, None, value[0])
+
+    genout(outfile, hwaccess_intro)
+    doc_tbl_head(outfile, None)
+    for key, value in HWACCESS_PERMITTED.items():
+        doc_tbl_line(outfile, key, None, value[0])
+
+    genout(
+        outfile, "\n\nThe top level of the JSON is a group containing "
+        "the following keys:\n")
+    doc_tbl_head(outfile, 1)
+    for k, v in ip_block.REQUIRED_FIELDS.items():
+        doc_tbl_line(outfile, k, 'r', v)
+    for k, v in ip_block.OPTIONAL_FIELDS.items():
+        doc_tbl_line(outfile, k, 'o', v)
+    genout(outfile, top_example)
+
+    genout(
+        outfile, "\n\nThe list of registers includes register definition "
+        "groups containing the following keys:\n")
+    doc_tbl_head(outfile, 1)
+    for k, v in register.REQUIRED_FIELDS.items():
+        doc_tbl_line(outfile, k, 'r', v)
+    for k, v in register.OPTIONAL_FIELDS.items():
+        doc_tbl_line(outfile, k, 'o', v)
+    genout(outfile, register_example)
+
+    genout(
+        outfile, "\n\nIn the fields list each field definition is a group "
+        "itself containing the following keys:\n")
+    doc_tbl_head(outfile, 1)
+    for k, v in field.REQUIRED_FIELDS.items():
+        doc_tbl_line(outfile, k, 'r', v)
+    for k, v in field.OPTIONAL_FIELDS.items():
+        doc_tbl_line(outfile, k, 'o', v)
+    genout(outfile, field_example)
+
+    genout(outfile, "\n\nDefinitions in an enumeration group contain:\n")
+    doc_tbl_head(outfile, 1)
+    for k, v in enum_entry.REQUIRED_FIELDS.items():
+        doc_tbl_line(outfile, k, 'r', v)
+
+    genout(
+        outfile, "\n\nThe list of registers may include single entry groups "
+        "to control the offset, open a window or generate registers:\n")
+    doc_tbl_head(outfile, 1)
+    for x in validate.list_optone:
+        doc_tbl_line(outfile, x, 'o', validate.list_optone[x])
+
+    genout(outfile, offset_intro)
+    genout(outfile, regwen_intro)
+
+    genout(outfile, window_intro)
+    doc_tbl_head(outfile, 1)
+    for k, v in window.REQUIRED_FIELDS.items():
+        doc_tbl_line(outfile, k, 'r', v)
+    for k, v in window.OPTIONAL_FIELDS.items():
+        doc_tbl_line(outfile, k, 'o', v)
+
+    genout(outfile, multi_intro)
+    doc_tbl_head(outfile, 1)
+    for k, v in multi_register.REQUIRED_FIELDS.items():
+        doc_tbl_line(outfile, k, 'r', v)
+    for k, v in multi_register.OPTIONAL_FIELDS.items():
+        doc_tbl_line(outfile, k, 'o', v)
+
+    genout(outfile, doc_tail)
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/html_helpers.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/html_helpers.py
new file mode 100644
index 00000000..8c828ee2
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/html_helpers.py
@@ -0,0 +1,83 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import logging as log
+import re
+from typing import List, Match, Optional, Set
+
+
+def expand_paras(s: str, rnames: Set[str]) -> List[str]:
+    '''Expand a description field to HTML.
+
+    This supports a sort of simple pseudo-markdown. Supported Markdown
+    features:
+
+    - Separate paragraphs on a blank line
+    - **bold** and *italicised* text
+    - Back-ticks for pre-formatted text
+
+    We also generate links to registers when a name is prefixed with a double
+    exclamation mark. For example, if there is a register FOO then !!FOO or
+    !!FOO.field will generate a link to that register.
+
+    Returns a list of rendered paragraphs
+
+    '''
+    # Start by splitting into paragraphs. The regex matches a newline followed
+    # by one or more lines that just contain whitespace. Then render each
+    # paragraph with the _expand_paragraph worker function.
+    paras = [_expand_paragraph(paragraph.strip(), rnames)
+             for paragraph in re.split(r'\n(?:\s*\n)+', s)]
+
+    # There will always be at least one paragraph (splitting an empty string
+    # gives [''])
+    assert paras
+    return paras
+
+
+def _expand_paragraph(s: str, rnames: Set[str]) -> str:
+    '''Expand a single paragraph, as described in _get_desc_paras'''
+    def fieldsub(match: Match[str]) -> str:
+        base = match.group(1).partition('.')[0].lower()
+        if base in rnames:
+            if match.group(1)[-1] == ".":
+                return ('<a href="#Reg_' + base + '"><code class=\"reg\">' +
+                        match.group(1)[:-1] + '</code></a>.')
+            else:
+                return ('<a href="#Reg_' + base + '"><code class=\"reg\">' +
+                        match.group(1) + '</code></a>')
+        log.warn('!!' + match.group(1).partition('.')[0] +
+                 ' not found in register list.')
+        return match.group(0)
+
+    # Split out pre-formatted text. Because the call to re.split has a capture
+    # group in the regex, we get an odd number of results. Elements with even
+    # indices are "normal text". Those with odd indices are the captured text
+    # between the back-ticks.
+    code_split = re.split(r'`([^`]+)`', s)
+    expanded_parts = []
+
+    for idx, part in enumerate(code_split):
+        if idx & 1:
+            # Text contained in back ticks
+            expanded_parts.append('<code>{}</code>'.format(part))
+            continue
+
+        part = re.sub(r"!!([A-Za-z0-9_.]+)", fieldsub, part)
+        part = re.sub(r"(?s)\*\*(.+?)\*\*", r'<B>\1</B>', part)
+        part = re.sub(r"\*([^*]+?)\*", r'<I>\1</I>', part)
+        expanded_parts.append(part)
+
+    return '<p>{}</p>'.format(''.join(expanded_parts))
+
+
+def render_td(s: str, rnames: Set[str], td_class: Optional[str]) -> str:
+    '''Expand a description field and put it in a <td>.
+
+    Returns a string. See _get_desc_paras for the format that gets expanded.
+
+    '''
+    desc_paras = expand_paras(s, rnames)
+    class_attr = '' if td_class is None else ' class="{}"'.format(td_class)
+    return '<td{}>{}</td>'.format(class_attr, ''.join(desc_paras))
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/inter_signal.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/inter_signal.py
new file mode 100644
index 00000000..cf27d511
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/inter_signal.py
@@ -0,0 +1,81 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict, Optional
+
+from .lib import (check_keys, check_name,
+                  check_str, check_optional_str, check_int)
+
+
+class InterSignal:
+    def __init__(self,
+                 name: str,
+                 desc: Optional[str],
+                 struct: str,
+                 package: Optional[str],
+                 signal_type: str,
+                 act: str,
+                 width: int,
+                 default: Optional[str]):
+        assert 0 < width
+        self.name = name
+        self.desc = desc
+        self.struct = struct
+        self.package = package
+        self.signal_type = signal_type
+        self.act = act
+        self.width = width
+        self.default = default
+
+    @staticmethod
+    def from_raw(what: str, raw: object) -> 'InterSignal':
+        rd = check_keys(raw, what,
+                        ['name', 'struct', 'type', 'act'],
+                        ['desc', 'package', 'width', 'default'])
+
+        name = check_name(rd['name'], 'name field of ' + what)
+
+        r_desc = rd.get('desc')
+        if r_desc is None:
+            desc = None
+        else:
+            desc = check_str(r_desc, 'desc field of ' + what)
+
+        struct = check_str(rd['struct'], 'struct field of ' + what)
+
+        r_package = rd.get('package')
+        if r_package is None or r_package == '':
+            package = None
+        else:
+            package = check_name(r_package, 'package field of ' + what)
+
+        signal_type = check_name(rd['type'], 'type field of ' + what)
+        act = check_name(rd['act'], 'act field of ' + what)
+        width = check_int(rd.get('width', 1), 'width field of ' + what)
+        if width <= 0:
+            raise ValueError('width field of {} is not positive.'.format(what))
+
+        default = check_optional_str(rd.get('default'),
+                                     'default field of ' + what)
+
+        return InterSignal(name, desc, struct, package,
+                           signal_type, act, width, default)
+
+    def _asdict(self) -> Dict[str, object]:
+        ret = {'name': self.name}  # type: Dict[str, object]
+        if self.desc is not None:
+            ret['desc'] = self.desc
+        ret['struct'] = self.struct
+        if self.package is not None:
+            ret['package'] = self.package
+        ret['type'] = self.signal_type
+        ret['act'] = self.act
+        ret['width'] = self.width
+        if self.default is not None:
+            ret['default'] = self.default
+
+        return ret
+
+    def as_dict(self) -> Dict[str, object]:
+        return self._asdict()
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/ip_block.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/ip_block.py
new file mode 100644
index 00000000..5865d04a
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/ip_block.py
@@ -0,0 +1,365 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+'''Code representing an IP block for reggen'''
+
+from typing import Dict, List, Optional, Sequence, Set, Tuple
+
+import hjson  # type: ignore
+
+from .alert import Alert
+from .bus_interfaces import BusInterfaces
+from .inter_signal import InterSignal
+from .lib import (check_keys, check_name, check_int, check_bool,
+                  check_list, check_optional_str, check_name_list)
+from .params import ReggenParams, LocalParam
+from .reg_block import RegBlock
+from .signal import Signal
+
+
+REQUIRED_FIELDS = {
+    'name': ['s', "name of the component"],
+    'clock_primary': ['s', "name of the primary clock"],
+    'bus_interfaces': ['l', "bus interfaces for the device"],
+    'registers': [
+        'l',
+        "list of register definition groups and "
+        "offset control groups"
+    ]
+}
+
+OPTIONAL_FIELDS = {
+    'alert_list': ['lnw', "list of peripheral alerts"],
+    'available_inout_list': ['lnw', "list of available peripheral inouts"],
+    'available_input_list': ['lnw', "list of available peripheral inputs"],
+    'available_output_list': ['lnw', "list of available peripheral outputs"],
+    'hier_path': [
+        None,
+        'additional hierarchy path before the reg block instance'
+    ],
+    'interrupt_list': ['lnw', "list of peripheral interrupts"],
+    'inter_signal_list': ['l', "list of inter-module signals"],
+    'no_auto_alert_regs': [
+        's', "Set to true to suppress automatic "
+        "generation of alert test registers. "
+        "Defaults to true if no alert_list is present. "
+        "Otherwise this defaults to false. "
+    ],
+    'no_auto_intr_regs': [
+        's', "Set to true to suppress automatic "
+        "generation of interrupt registers. "
+        "Defaults to true if no interrupt_list is present. "
+        "Otherwise this defaults to false. "
+    ],
+    'other_clock_list': ['l', "list of other chip clocks needed"],
+    'other_reset_list': ['l', "list of other resets"],
+    'param_list': ['lp', "list of parameters of the IP"],
+    'regwidth': ['d', "width of registers in bits (default 32)"],
+    'reset_primary': ['s', "primary reset used by the module"],
+    'reset_request_list': ['l', 'list of signals requesting reset'],
+    'scan': ['pb', 'Indicates the module have `scanmode_i`'],
+    'scan_reset': ['pb', 'Indicates the module have `scan_rst_ni`'],
+    'scan_en': ['pb', 'Indicates the module has `scan_en_i`'],
+    'SPDX-License-Identifier': [
+        's', "License ientifier (if using pure json) "
+        "Only use this if unable to put this "
+        "information in a comment at the top of the "
+        "file."
+    ],
+    'wakeup_list': ['lnw', "list of peripheral wakeups"]
+}
+
+
+class IpBlock:
+    def __init__(self,
+                 name: str,
+                 regwidth: int,
+                 params: ReggenParams,
+                 reg_blocks: Dict[Optional[str], RegBlock],
+                 interrupts: Sequence[Signal],
+                 no_auto_intr: bool,
+                 alerts: List[Alert],
+                 no_auto_alert: bool,
+                 scan: bool,
+                 inter_signals: List[InterSignal],
+                 bus_interfaces: BusInterfaces,
+                 hier_path: Optional[str],
+                 clock_signals: List[str],
+                 reset_signals: List[str],
+                 xputs: Tuple[Sequence[Signal],
+                              Sequence[Signal],
+                              Sequence[Signal]],
+                 wakeups: Sequence[Signal],
+                 reset_requests: Sequence[Signal],
+                 scan_reset: bool,
+                 scan_en: bool):
+        assert reg_blocks
+        assert clock_signals
+        assert reset_signals
+
+        # Check that register blocks are in bijection with device interfaces
+        reg_block_names = reg_blocks.keys()
+        dev_if_names = []  # type: List[Optional[str]]
+        dev_if_names += bus_interfaces.named_devices
+        if bus_interfaces.has_unnamed_device:
+            dev_if_names.append(None)
+        assert set(reg_block_names) == set(dev_if_names)
+
+        self.name = name
+        self.regwidth = regwidth
+        self.reg_blocks = reg_blocks
+        self.params = params
+        self.interrupts = interrupts
+        self.no_auto_intr = no_auto_intr
+        self.alerts = alerts
+        self.no_auto_alert = no_auto_alert
+        self.scan = scan
+        self.inter_signals = inter_signals
+        self.bus_interfaces = bus_interfaces
+        self.hier_path = hier_path
+        self.clock_signals = clock_signals
+        self.reset_signals = reset_signals
+        self.xputs = xputs
+        self.wakeups = wakeups
+        self.reset_requests = reset_requests
+        self.scan_reset = scan_reset
+        self.scan_en = scan_en
+
+    @staticmethod
+    def from_raw(param_defaults: List[Tuple[str, str]],
+                 raw: object,
+                 where: str) -> 'IpBlock':
+
+        rd = check_keys(raw, 'block at ' + where,
+                        list(REQUIRED_FIELDS.keys()),
+                        list(OPTIONAL_FIELDS.keys()))
+
+        name = check_name(rd['name'], 'name of block at ' + where)
+
+        what = '{} block at {}'.format(name, where)
+
+        r_regwidth = rd.get('regwidth')
+        if r_regwidth is None:
+            regwidth = 32
+        else:
+            regwidth = check_int(r_regwidth, 'regwidth field of ' + what)
+            if regwidth <= 0:
+                raise ValueError('Invalid regwidth field for {}: '
+                                 '{} is not positive.'
+                                 .format(what, regwidth))
+
+        params = ReggenParams.from_raw('parameter list for ' + what,
+                                       rd.get('param_list', []))
+        try:
+            params.apply_defaults(param_defaults)
+        except (ValueError, KeyError) as err:
+            raise ValueError('Failed to apply defaults to params: {}'
+                             .format(err)) from None
+
+        init_block = RegBlock(regwidth, params)
+
+        interrupts = Signal.from_raw_list('interrupt_list for block {}'
+                                          .format(name),
+                                          rd.get('interrupt_list', []))
+        alerts = Alert.from_raw_list('alert_list for block {}'
+                                     .format(name),
+                                     rd.get('alert_list', []))
+
+        no_auto_intr = check_bool(rd.get('no_auto_intr_regs', not interrupts),
+                                  'no_auto_intr_regs field of ' + what)
+
+        no_auto_alert = check_bool(rd.get('no_auto_alert_regs', not alerts),
+                                   'no_auto_alert_regs field of ' + what)
+
+        if interrupts and not no_auto_intr:
+            if interrupts[-1].bits.msb >= regwidth:
+                raise ValueError("Interrupt list for {} is too wide: "
+                                 "msb is {}, which doesn't fit with a "
+                                 "regwidth of {}."
+                                 .format(what,
+                                         interrupts[-1].bits.msb, regwidth))
+            init_block.make_intr_regs(interrupts)
+
+        if alerts:
+            if not no_auto_alert:
+                if len(alerts) > regwidth:
+                    raise ValueError("Interrupt list for {} is too wide: "
+                                     "{} alerts don't fit with a regwidth of {}."
+                                     .format(what, len(alerts), regwidth))
+                init_block.make_alert_regs(alerts)
+
+            # Generate a NumAlerts parameter
+            existing_param = params.get('NumAlerts')
+            if existing_param is not None:
+                if ((not isinstance(existing_param, LocalParam) or
+                     existing_param.param_type != 'int' or
+                     existing_param.value != str(len(alerts)))):
+                    raise ValueError('Conflicting definition of NumAlerts '
+                                     'parameter.')
+            else:
+                params.add(LocalParam(name='NumAlerts',
+                                      desc='Number of alerts',
+                                      param_type='int',
+                                      value=str(len(alerts))))
+
+        scan = check_bool(rd.get('scan', False), 'scan field of ' + what)
+
+        reg_blocks = RegBlock.build_blocks(init_block, rd['registers'])
+
+        r_inter_signals = check_list(rd.get('inter_signal_list', []),
+                                     'inter_signal_list field')
+        inter_signals = [
+            InterSignal.from_raw('entry {} of the inter_signal_list field'
+                                 .format(idx + 1),
+                                 entry)
+            for idx, entry in enumerate(r_inter_signals)
+        ]
+
+        bus_interfaces = (BusInterfaces.
+                          from_raw(rd['bus_interfaces'],
+                                   'bus_interfaces field of ' + where))
+        inter_signals += bus_interfaces.inter_signals()
+
+        hier_path = check_optional_str(rd.get('hier_path', None),
+                                       'hier_path field of ' + what)
+
+        clock_primary = check_name(rd['clock_primary'],
+                                   'clock_primary field of ' + what)
+        other_clock_list = check_name_list(rd.get('other_clock_list', []),
+                                           'other_clock_list field of ' + what)
+        clock_signals = [clock_primary] + other_clock_list
+
+        reset_primary = check_name(rd.get('reset_primary', 'rst_ni'),
+                                   'reset_primary field of ' + what)
+        other_reset_list = check_name_list(rd.get('other_reset_list', []),
+                                           'other_reset_list field of ' + what)
+        reset_signals = [reset_primary] + other_reset_list
+
+        xputs = (
+            Signal.from_raw_list('available_inout_list for block ' + name,
+                                 rd.get('available_inout_list', [])),
+            Signal.from_raw_list('available_input_list for block ' + name,
+                                 rd.get('available_input_list', [])),
+            Signal.from_raw_list('available_output_list for block ' + name,
+                                 rd.get('available_output_list', []))
+        )
+        wakeups = Signal.from_raw_list('wakeup_list for block ' + name,
+                                       rd.get('wakeup_list', []))
+        rst_reqs = Signal.from_raw_list('reset_request_list for block ' + name,
+                                        rd.get('reset_request_list', []))
+
+        scan_reset = check_bool(rd.get('scan_reset', False),
+                                'scan_reset field of ' + what)
+
+        scan_en = check_bool(rd.get('scan_en', False),
+                                'scan_en field of ' + what)
+
+        # Check that register blocks are in bijection with device interfaces
+        reg_block_names = reg_blocks.keys()
+        dev_if_names = []  # type: List[Optional[str]]
+        dev_if_names += bus_interfaces.named_devices
+        if bus_interfaces.has_unnamed_device:
+            dev_if_names.append(None)
+        if set(reg_block_names) != set(dev_if_names):
+            raise ValueError("IP block {} defines device interfaces, named {} "
+                             "but its registers don't match (they are keyed "
+                             "by {})."
+                             .format(name, dev_if_names,
+                                     list(reg_block_names)))
+
+        return IpBlock(name, regwidth, params, reg_blocks,
+                       interrupts, no_auto_intr, alerts, no_auto_alert,
+                       scan, inter_signals, bus_interfaces,
+                       hier_path, clock_signals, reset_signals, xputs,
+                       wakeups, rst_reqs, scan_reset, scan_en)
+
+    @staticmethod
+    def from_text(txt: str,
+                  param_defaults: List[Tuple[str, str]],
+                  where: str) -> 'IpBlock':
+        '''Load an IpBlock from an hjson description in txt'''
+        return IpBlock.from_raw(param_defaults,
+                                hjson.loads(txt, use_decimal=True),
+                                where)
+
+    @staticmethod
+    def from_path(path: str,
+                  param_defaults: List[Tuple[str, str]]) -> 'IpBlock':
+        '''Load an IpBlock from an hjson description in a file at path'''
+        with open(path, 'r', encoding='utf-8') as handle:
+            return IpBlock.from_text(handle.read(), param_defaults,
+                                     'file at {!r}'.format(path))
+
+    def _asdict(self) -> Dict[str, object]:
+        ret = {
+            'name': self.name,
+            'regwidth': self.regwidth
+        }
+        if len(self.reg_blocks) == 1 and None in self.reg_blocks:
+            ret['registers'] = self.reg_blocks[None].as_dicts()
+        else:
+            ret['registers'] = {k: v.as_dicts()
+                                for k, v in self.reg_blocks.items()}
+
+        ret['param_list'] = self.params.as_dicts()
+        ret['interrupt_list'] = self.interrupts
+        ret['no_auto_intr_regs'] = self.no_auto_intr
+        ret['alert_list'] = self.alerts
+        ret['no_auto_alert_regs'] = self.no_auto_alert
+        ret['scan'] = self.scan
+        ret['inter_signal_list'] = self.inter_signals
+        ret['bus_interfaces'] = self.bus_interfaces.as_dicts()
+
+        if self.hier_path is not None:
+            ret['hier_path'] = self.hier_path
+
+        ret['clock_primary'] = self.clock_signals[0]
+        if len(self.clock_signals) > 1:
+            ret['other_clock_list'] = self.clock_signals[1:]
+
+        ret['reset_primary'] = self.reset_signals[0]
+        if len(self.reset_signals) > 1:
+            ret['other_reset_list'] = self.reset_signals[1:]
+
+        inouts, inputs, outputs = self.xputs
+        if inouts:
+            ret['available_inout_list'] = inouts
+        if inputs:
+            ret['available_input_list'] = inputs
+        if outputs:
+            ret['available_output_list'] = outputs
+
+        if self.wakeups:
+            ret['wakeup_list'] = self.wakeups
+        if self.reset_requests:
+            ret['reset_request_list'] = self.reset_requests
+
+        ret['scan_reset'] = self.scan_reset
+        ret['scan_en'] = self.scan_en
+
+        return ret
+
+    def get_rnames(self) -> Set[str]:
+        ret = set()  # type: Set[str]
+        for rb in self.reg_blocks.values():
+            ret = ret.union(set(rb.name_to_offset.keys()))
+        return ret
+
+    def get_signals_as_list_of_dicts(self) -> List[Dict]:
+        '''Look up and return signal by name'''
+        result = []
+        for iodir, xput in zip(('inout', 'input', 'output'), self.xputs):
+            for sig in xput:
+                result.append(sig.as_nwt_dict(iodir))
+        return result
+
+    def get_signal_by_name_as_dict(self, name: str) -> Dict:
+        '''Look up and return signal by name'''
+        sig_list = self.get_signals_as_list_of_dicts()
+        for sig in sig_list:
+            if sig['name'] == name:
+                return sig
+        else:
+            raise ValueError("Signal {} does not exist in IP block {}"
+                             .format(name, self.name))
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/lib.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/lib.py
new file mode 100644
index 00000000..d72ef3d3
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/lib.py
@@ -0,0 +1,262 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+'''Parsing support code for reggen'''
+
+import re
+from typing import Dict, List, Optional, cast
+
+
+# Names that are prohibited (used as reserved keywords in systemverilog)
+_VERILOG_KEYWORDS = {
+    'alias', 'always', 'always_comb', 'always_ff', 'always_latch', 'and',
+    'assert', 'assign', 'assume', 'automatic', 'before', 'begin', 'bind',
+    'bins', 'binsof', 'bit', 'break', 'buf', 'bufif0', 'bufif1', 'byte',
+    'case', 'casex', 'casez', 'cell', 'chandle', 'class', 'clocking', 'cmos',
+    'config', 'const', 'constraint', 'context', 'continue', 'cover',
+    'covergroup', 'coverpoint', 'cross', 'deassign', 'default', 'defparam',
+    'design', 'disable', 'dist', 'do', 'edge', 'else', 'end', 'endcase',
+    'endclass', 'endclocking', 'endconfig', 'endfunction', 'endgenerate',
+    'endgroup', 'endinterface', 'endmodule', 'endpackage', 'endprimitive',
+    'endprogram', 'endproperty', 'endspecify', 'endsequence', 'endtable',
+    'endtask', 'enum', 'event', 'expect', 'export', 'extends', 'extern',
+    'final', 'first_match', 'for', 'force', 'foreach', 'forever', 'fork',
+    'forkjoin', 'function', 'generate', 'genvar', 'highz0', 'highz1', 'if',
+    'iff', 'ifnone', 'ignore_bins', 'illegal_bins', 'import', 'incdir',
+    'include', 'initial', 'inout', 'input', 'inside', 'instance', 'int',
+    'integer', 'interface', 'intersect', 'join', 'join_any', 'join_none',
+    'large', 'liblist', 'library', 'local', 'localparam', 'logic', 'longint',
+    'macromodule', 'matches', 'medium', 'modport', 'module', 'nand', 'negedge',
+    'new', 'nmos', 'nor', 'noshowcancelled', 'not', 'notif0', 'notif1', 'null',
+    'or', 'output', 'package', 'packed', 'parameter', 'pmos', 'posedge',
+    'primitive', 'priority', 'program', 'property', 'protected', 'pull0',
+    'pull1', 'pulldown', 'pullup', 'pulsestyle_onevent', 'pulsestyle_ondetect',
+    'pure', 'rand', 'randc', 'randcase', 'randsequence', 'rcmos', 'real',
+    'realtime', 'ref', 'reg', 'release', 'repeat', 'return', 'rnmos', 'rpmos',
+    'rtran', 'rtranif0', 'rtranif1', 'scalared', 'sequence', 'shortint',
+    'shortreal', 'showcancelled', 'signed', 'small', 'solve', 'specify',
+    'specparam', 'static', 'string', 'strong0', 'strong1', 'struct', 'super',
+    'supply0', 'supply1', 'table', 'tagged', 'task', 'this', 'throughout',
+    'time', 'timeprecision', 'timeunit', 'tran', 'tranif0', 'tranif1', 'tri',
+    'tri0', 'tri1', 'triand', 'trior', 'trireg', 'type', 'typedef', 'union',
+    'unique', 'unsigned', 'use', 'uwire', 'var', 'vectored', 'virtual', 'void',
+    'wait', 'wait_order', 'wand', 'weak0', 'weak1', 'while', 'wildcard',
+    'wire', 'with', 'within', 'wor', 'xnor', 'xor'
+}
+
+
+def check_str_dict(obj: object, what: str) -> Dict[str, object]:
+    if not isinstance(obj, dict):
+        raise ValueError("{} is expected to be a dict, but was actually a {}."
+                         .format(what, type(obj).__name__))
+
+    for key in obj:
+        if not isinstance(key, str):
+            raise ValueError('{} has a key {!r}, which is not a string.'
+                             .format(what, key))
+
+    return cast(Dict[str, object], obj)
+
+
+def check_keys(obj: object,
+               what: str,
+               required_keys: List[str],
+               optional_keys: List[str]) -> Dict[str, object]:
+    '''Check that obj is a dict object with the expected keys
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    od = check_str_dict(obj, what)
+
+    allowed = set()
+    missing = []
+    for key in required_keys:
+        assert key not in allowed
+        allowed.add(key)
+        if key not in od:
+            missing.append(key)
+
+    for key in optional_keys:
+        assert key not in allowed
+        allowed.add(key)
+
+    unexpected = []
+    for key in od:
+        if key not in allowed:
+            unexpected.append(key)
+
+    if missing or unexpected:
+        mstr = ('The following required fields were missing: {}.'
+                .format(', '.join(missing)) if missing else '')
+        ustr = ('The following unexpected fields were found: {}.'
+                .format(', '.join(unexpected)) if unexpected else '')
+        raise ValueError("{} doesn't have the right keys. {}{}{}"
+                         .format(what,
+                                 mstr,
+                                 ' ' if mstr and ustr else '',
+                                 ustr))
+
+    return od
+
+
+def check_str(obj: object, what: str) -> str:
+    '''Check that the given object is a string
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    if not isinstance(obj, str):
+        raise ValueError('{} is of type {}, not a string.'
+                         .format(what, type(obj).__name__))
+    return obj
+
+
+def check_name(obj: object, what: str) -> str:
+    '''Check that obj is a string that's a valid name.
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    as_str = check_str(obj, what)
+
+    # Allow the usual symbol constituents (alphanumeric plus underscore; no
+    # leading numbers)
+    if not re.match(r'[a-zA-Z_][a-zA-Z_0-9]*$', as_str):
+        raise ValueError("{} is {!r}, which isn't a valid symbol in "
+                         "C / Verilog, so isn't allowed as a name."
+                         .format(what, as_str))
+
+    # Also check that this isn't a reserved word.
+    if as_str in _VERILOG_KEYWORDS:
+        raise ValueError("{} is {!r}, which is a reserved word in "
+                         "SystemVerilog, so isn't allowed as a name."
+                         .format(what, as_str))
+
+    return as_str
+
+
+def check_bool(obj: object, what: str) -> bool:
+    '''Check that obj is a bool or a string that parses to a bool.
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    if isinstance(obj, str):
+        as_bool = {
+            'true': True,
+            'false': False,
+            '1': True,
+            '0': False
+        }.get(obj.lower())
+        if as_bool is None:
+            raise ValueError('{} is {!r}, which cannot be parsed as a bool.'
+                             .format(what, obj))
+        return as_bool
+
+    if obj is True or obj is False:
+        return obj
+
+    raise ValueError('{} is of type {}, not a bool.'
+                     .format(what, type(obj).__name__))
+
+
+def check_list(obj: object, what: str) -> List[object]:
+    '''Check that the given object is a list
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    if not isinstance(obj, list):
+        raise ValueError('{} is of type {}, not a list.'
+                         .format(what, type(obj).__name__))
+    return obj
+
+
+def check_str_list(obj: object, what: str) -> List[str]:
+    '''Check that the given object is a list of strings
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    lst = check_list(obj, what)
+    for idx, elt in enumerate(lst):
+        if not isinstance(elt, str):
+            raise ValueError('Element {} of {} is of type {}, '
+                             'not a string.'
+                             .format(idx, what, type(elt).__name__))
+    return cast(List[str], lst)
+
+
+def check_name_list(obj: object, what: str) -> List[str]:
+    '''Check that the given object is a list of valid names
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    lst = check_list(obj, what)
+    for idx, elt in enumerate(lst):
+        check_name(elt, 'Element {} of {}'.format(idx + 1, what))
+
+    return cast(List[str], lst)
+
+
+def check_int(obj: object, what: str) -> int:
+    '''Check that obj is an integer or a string that parses to an integer.
+
+    If not, raise a ValueError; the what argument names the object.
+
+    '''
+    if isinstance(obj, int):
+        return obj
+
+    if isinstance(obj, str):
+        try:
+            return int(obj, 0)
+        except ValueError:
+            raise ValueError('{} is {!r}, which cannot be parsed as an int.'
+                             .format(what, obj)) from None
+
+    raise ValueError('{} is of type {}, not an integer.'
+                     .format(what, type(obj).__name__))
+
+
+def check_xint(obj: object, what: str) -> Optional[int]:
+    '''Check that obj is an integer, a string that parses to an integer or "x".
+
+    On success, return an integer value if there is one or None if the value
+    was 'x'. On failure, raise a ValueError; the what argument names the
+    object.
+
+    '''
+    if isinstance(obj, int):
+        return obj
+
+    if isinstance(obj, str):
+        if obj == 'x':
+            return None
+        try:
+            return int(obj, 0)
+        except ValueError:
+            raise ValueError('{} is {!r}, which is not "x", '
+                             'nor can it be parsed as an int.'
+                             .format(what, obj)) from None
+
+    raise ValueError('{} is of type {}, not an integer.'
+                     .format(what, type(obj).__name__))
+
+
+def check_optional_str(obj: object, what: str) -> Optional[str]:
+    '''Check that obj is a string or None'''
+    return None if obj is None else check_str(obj, what)
+
+
+def get_basename(name: str) -> str:
+    '''Strip trailing _number (used as multireg suffix) from name'''
+    # TODO: This is a workaround, should solve this as part of parsing a
+    # multi-reg.
+    match = re.search(r'_[0-9]+$', name)
+    assert match
+    assert match.start() > 0
+    return name[0:match.start()]
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/multi_register.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/multi_register.py
new file mode 100644
index 00000000..82c86677
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/multi_register.py
@@ -0,0 +1,142 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict, List
+
+from reggen import register
+from .field import Field
+from .lib import check_keys, check_str, check_name, check_bool
+from .params import ReggenParams
+from .reg_base import RegBase
+from .register import Register
+
+REQUIRED_FIELDS = {
+    'name': ['s', "base name of the registers"],
+    'desc': ['t', "description of the registers"],
+    'count': [
+        's', "number of instances to generate."
+        " This field can be integer or string matching"
+        " from param_list."
+    ],
+    'cname': [
+        's', "base name for each instance, mostly"
+        " useful for referring to instance in messages."
+    ],
+    'fields': [
+        'l', "list of register field description"
+        " groups. Describes bit positions used for"
+        " base instance."
+    ]
+}
+OPTIONAL_FIELDS = register.OPTIONAL_FIELDS.copy()
+OPTIONAL_FIELDS.update({
+    'regwen_multi': [
+        'pb', "If true, regwen term increments"
+        " along with current multireg count."
+    ],
+    'compact': [
+        'pb', "If true, allow multireg compacting."
+        "If false, do not compact."
+    ]
+})
+
+
+class MultiRegister(RegBase):
+    def __init__(self,
+                 offset: int,
+                 addrsep: int,
+                 reg_width: int,
+                 params: ReggenParams,
+                 raw: object):
+        super().__init__(offset)
+
+        rd = check_keys(raw, 'multireg',
+                        list(REQUIRED_FIELDS.keys()),
+                        list(OPTIONAL_FIELDS.keys()))
+
+        # Now that we've checked the schema of rd, we make a "reg" version of
+        # it that removes any fields that are allowed by MultiRegister but
+        # aren't allowed by Register. We'll pass that to the register factory
+        # method.
+        reg_allowed_keys = (set(register.REQUIRED_FIELDS.keys()) |
+                            set(register.OPTIONAL_FIELDS.keys()))
+        reg_rd = {key: value
+                  for key, value in rd.items()
+                  if key in reg_allowed_keys}
+        self.reg = Register.from_raw(reg_width, offset, params, reg_rd)
+
+        self.cname = check_name(rd['cname'],
+                                'cname field of multireg {}'
+                                .format(self.reg.name))
+
+        self.regwen_multi = check_bool(rd.get('regwen_multi', False),
+                                       'regwen_multi field of multireg {}'
+                                       .format(self.reg.name))
+
+        default_compact = True if len(self.reg.fields) == 1 else False
+        self.compact = check_bool(rd.get('compact', default_compact),
+                                  'compact field of multireg {}'
+                                  .format(self.reg.name))
+        if self.compact and len(self.reg.fields) > 1:
+            raise ValueError('Multireg {} sets the compact flag '
+                             'but has multiple fields.'
+                             .format(self.reg.name))
+
+        count_str = check_str(rd['count'],
+                              'count field of multireg {}'
+                              .format(self.reg.name))
+        self.count = params.expand(count_str,
+                                   'count field of multireg ' + self.reg.name)
+        if self.count <= 0:
+            raise ValueError("Multireg {} has a count of {}, "
+                             "which isn't positive."
+                             .format(self.reg.name, self.count))
+
+        # Generate the registers that this multireg expands into. Here, a
+        # "creg" is a "compacted register", which might contain multiple actual
+        # registers.
+        if self.compact:
+            assert len(self.reg.fields) == 1
+            width_per_reg = self.reg.fields[0].bits.msb + 1
+            assert width_per_reg <= reg_width
+            regs_per_creg = reg_width // width_per_reg
+        else:
+            regs_per_creg = 1
+
+        self.regs = []
+        creg_count = (self.count + regs_per_creg - 1) // regs_per_creg
+        for creg_idx in range(creg_count):
+            min_reg_idx = regs_per_creg * creg_idx
+            max_reg_idx = min(min_reg_idx + regs_per_creg, self.count) - 1
+            creg_offset = offset + creg_idx * addrsep
+
+            reg = self.reg.make_multi(reg_width,
+                                      creg_offset, creg_idx, creg_count,
+                                      self.regwen_multi, self.compact,
+                                      min_reg_idx, max_reg_idx, self.cname)
+            self.regs.append(reg)
+
+    def next_offset(self, addrsep: int) -> int:
+        return self.offset + len(self.regs) * addrsep
+
+    def get_n_bits(self, bittype: List[str] = ["q"]) -> int:
+        return sum(reg.get_n_bits(bittype) for reg in self.regs)
+
+    def get_field_list(self) -> List[Field]:
+        ret = []
+        for reg in self.regs:
+            ret += reg.get_field_list()
+        return ret
+
+    def is_homogeneous(self) -> bool:
+        return self.reg.is_homogeneous()
+
+    def _asdict(self) -> Dict[str, object]:
+        rd = self.reg._asdict()
+        rd['count'] = str(self.count)
+        rd['cname'] = self.cname
+        rd['regwen_multi'] = str(self.regwen_multi)
+        rd['compact'] = str(self.compact)
+
+        return {'multireg': rd}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/params.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/params.py
new file mode 100644
index 00000000..b7a6adcb
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/params.py
@@ -0,0 +1,341 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import re
+from collections.abc import MutableMapping
+from typing import Dict, List, Optional, Tuple
+
+from .lib import check_keys, check_str, check_int, check_bool, check_list
+
+REQUIRED_FIELDS = {
+    'name': ['s', "name of the item"],
+}
+
+OPTIONAL_FIELDS = {
+    'desc': ['s', "description of the item"],
+    'type': ['s', "item type. int by default"],
+    'default': ['s', "item default value"],
+    'local': ['pb', "to be localparam"],
+    'expose': ['pb', "to be exposed to top"],
+    'randcount': [
+        's', "number of bits to randomize in the parameter. 0 by default."
+    ],
+    'randtype': ['s', "type of randomization to perform. none by default"],
+}
+
+
+class BaseParam:
+    def __init__(self, name: str, desc: Optional[str], param_type: str):
+        self.name = name
+        self.desc = desc
+        self.param_type = param_type
+
+    def apply_default(self, value: str) -> None:
+        if self.param_type[:3] == 'int':
+            check_int(value,
+                      'default value for parameter {} '
+                      '(which has type {})'
+                      .format(self.name, self.param_type))
+        self.default = value
+
+    def as_dict(self) -> Dict[str, object]:
+        rd = {}  # type: Dict[str, object]
+        rd['name'] = self.name
+        if self.desc is not None:
+            rd['desc'] = self.desc
+        rd['type'] = self.param_type
+        return rd
+
+
+class LocalParam(BaseParam):
+    def __init__(self,
+                 name: str,
+                 desc: Optional[str],
+                 param_type: str,
+                 value: str):
+        super().__init__(name, desc, param_type)
+        self.value = value
+
+    def expand_value(self, when: str) -> int:
+        try:
+            return int(self.value, 0)
+        except ValueError:
+            raise ValueError("When {}, the {} value expanded as "
+                             "{}, which doesn't parse as an integer."
+                             .format(when, self.name, self.value)) from None
+
+    def as_dict(self) -> Dict[str, object]:
+        rd = super().as_dict()
+        rd['local'] = True
+        rd['default'] = self.value
+        return rd
+
+
+class Parameter(BaseParam):
+    def __init__(self,
+                 name: str,
+                 desc: Optional[str],
+                 param_type: str,
+                 default: str,
+                 expose: bool):
+        super().__init__(name, desc, param_type)
+        self.default = default
+        self.expose = expose
+
+    def as_dict(self) -> Dict[str, object]:
+        rd = super().as_dict()
+        rd['default'] = self.default
+        rd['expose'] = 'true' if self.expose else 'false'
+        return rd
+
+
+class RandParameter(BaseParam):
+    def __init__(self,
+                 name: str,
+                 desc: Optional[str],
+                 param_type: str,
+                 randcount: int,
+                 randtype: str):
+        assert randcount > 0
+        assert randtype in ['perm', 'data']
+        super().__init__(name, desc, param_type)
+        self.randcount = randcount
+        self.randtype = randtype
+
+    def apply_default(self, value: str) -> None:
+        raise ValueError('Cannot apply a default value of {!r} to '
+                         'parameter {}: it is a random netlist constant.'
+                         .format(self.name, value))
+
+    def as_dict(self) -> Dict[str, object]:
+        rd = super().as_dict()
+        rd['randcount'] = self.randcount
+        rd['randtype'] = self.randtype
+        return rd
+
+
+def _parse_parameter(where: str, raw: object) -> BaseParam:
+    rd = check_keys(raw, where,
+                    list(REQUIRED_FIELDS.keys()),
+                    list(OPTIONAL_FIELDS.keys()))
+
+    # TODO: Check if PascalCase or ALL_CAPS
+    name = check_str(rd['name'], 'name field of ' + where)
+
+    r_desc = rd.get('desc')
+    if r_desc is None:
+        desc = None
+    else:
+        desc = check_str(r_desc, 'desc field of ' + where)
+
+    # TODO: We should probably check that any register called RndCnstFoo has
+    #       randtype and randcount.
+    if name.lower().startswith('rndcnst') and 'randtype' in rd:
+        # This is a random netlist constant and should be parsed as a
+        # RandParameter.
+        randtype = check_str(rd.get('randtype', 'none'),
+                             'randtype field of ' + where)
+        if randtype not in ['perm', 'data']:
+            raise ValueError('At {}, parameter {} has a name that implies it '
+                             'is a random netlist constant, which means it '
+                             'must specify a randtype of "perm" or "data", '
+                             'rather than {!r}.'
+                             .format(where, name, randtype))
+
+        r_randcount = rd.get('randcount')
+        if r_randcount is None:
+            raise ValueError('At {}, the random netlist constant {} has no '
+                             'randcount field.'
+                             .format(where, name))
+        randcount = check_int(r_randcount, 'randcount field of ' + where)
+        if randcount <= 0:
+            raise ValueError('At {}, the random netlist constant {} has a '
+                             'randcount of {}, which is not positive.'
+                             .format(where, name, randcount))
+
+        r_type = rd.get('type')
+        if r_type is None:
+            raise ValueError('At {}, parameter {} has no type field (which is '
+                             'required for random netlist constants).'
+                             .format(where, name))
+        param_type = check_str(r_type, 'type field of ' + where)
+
+        local = check_bool(rd.get('local', 'false'), 'local field of ' + where)
+        if local:
+            raise ValueError('At {}, the parameter {} specifies local = true, '
+                             'meaning that it is a localparam. This is '
+                             'incompatible with being a random netlist '
+                             'constant (how would it be set?)'
+                             .format(where, name))
+
+        r_default = rd.get('default')
+        if r_default is not None:
+            raise ValueError('At {}, the parameter {} specifies a value for '
+                             'the "default" field. This is incompatible with '
+                             'being a random netlist constant: the value will '
+                             'be set by the random generator.'
+                             .format(where, name))
+
+        expose = check_bool(rd.get('expose', 'false'),
+                            'expose field of ' + where)
+        if expose:
+            raise ValueError('At {}, the parameter {} specifies expose = '
+                             'true, meaning that the parameter is exposed to '
+                             'the top-level. This is incompatible with being '
+                             'a random netlist constant.'
+                             .format(where, name))
+
+        return RandParameter(name, desc, param_type, randcount, randtype)
+
+    # This doesn't have a name like a random netlist constant. Check that it
+    # doesn't define randcount or randtype.
+    for fld in ['randcount', 'randtype']:
+        if fld in rd:
+            raise ValueError("At {where}, the parameter {name} specifies "
+                             "{fld} but the name doesn't look like a random "
+                             "netlist constant. To use {fld}, prefix the name "
+                             "with RndCnst."
+                             .format(where=where, name=name, fld=fld))
+
+    r_type = rd.get('type')
+    if r_type is None:
+        param_type = 'int'
+    else:
+        param_type = check_str(r_type, 'type field of ' + where)
+
+    local = check_bool(rd.get('local', 'true'), 'local field of ' + where)
+    expose = check_bool(rd.get('expose', 'false'), 'expose field of ' + where)
+
+    r_default = rd.get('default')
+    if r_default is None:
+        raise ValueError('At {}, the {} param has no default field.'
+                         .format(where, name))
+    else:
+        default = check_str(r_default, 'default field of ' + where)
+        if param_type[:3] == 'int':
+            check_int(default,
+                      'default field of {}, (an integer parameter)'
+                      .format(name))
+
+    if local:
+        if expose:
+            raise ValueError('At {}, the localparam {} cannot be exposed to '
+                             'the top-level.'
+                             .format(where, name))
+        return LocalParam(name, desc, param_type, value=default)
+    else:
+        return Parameter(name, desc, param_type, default, expose)
+
+
+class Params(MutableMapping):
+    def __init__(self) -> None:
+        self.by_name = {}  # type: Dict[str, BaseParam]
+
+    def __getitem__(self, key):
+        return self.by_name[key]
+
+    def __delitem__(self, key):
+        del self.by_name[key]
+
+    def __setitem__(self, key, value):
+        self.by_name[key] = value
+
+    def __iter__(self):
+        return iter(self.by_name)
+
+    def __len__(self):
+        return len(self.by_name)
+
+    def __repr__(self):
+        return f"{type(self).__name__}({self.by_name})"
+
+    def add(self, param: BaseParam) -> None:
+        assert param.name not in self.by_name
+        self.by_name[param.name] = param
+
+    def apply_defaults(self, defaults: List[Tuple[str, str]]) -> None:
+        for idx, (key, value) in enumerate(defaults):
+            param = self.by_name[key]
+            if param is None:
+                raise KeyError('Cannot find parameter '
+                               '{} to set default value.'
+                               .format(key))
+
+            param.apply_default(value)
+
+    def _expand_one(self, value: str, when: str) -> int:
+        # Check whether value is already an integer: if so, return that.
+        try:
+            return int(value, 0)
+        except ValueError:
+            pass
+
+        param = self.by_name.get(value)
+        if param is None:
+            raise ValueError('Cannot find a parameter called {} when {}. '
+                             'Known parameters: {}.'
+                             .format(value,
+                                     when,
+                                     ', '.join(self.by_name.keys())))
+
+        # Only allow localparams in the expansion (because otherwise we're at
+        # the mercy of whatever instantiates the block).
+        if not isinstance(param, LocalParam):
+            raise ValueError("When {}, {} is a not a local parameter."
+                             .format(when, value))
+
+        return param.expand_value(when)
+
+    def expand(self, value: str, where: str) -> int:
+        # Here, we want to support arithmetic expressions with + and -. We
+        # don't support other operators, or parentheses (so can parse with just
+        # a regex).
+        #
+        # Use re.split, capturing the operators. This turns e.g. "a + b-c" into
+        # ['a ', '+', ' b', '-', 'c']. If there's a leading operator ("+a"),
+        # the first element of the results is an empty string. This means
+        # elements with odd positions are always operators and elements with
+        # even positions are values.
+        acc = 0
+        is_neg = False
+
+        for idx, tok in enumerate(re.split(r'([+-])', value)):
+            if idx == 0 and not tok:
+                continue
+            if idx % 2:
+                is_neg = (tok == '-')
+                continue
+
+            term = self._expand_one(tok.strip(),
+                                    'expanding term {} of {}'
+                                    .format(idx // 2, where))
+            acc += -term if is_neg else term
+
+        return acc
+
+    def as_dicts(self) -> List[Dict[str, object]]:
+        return [p.as_dict() for p in self.by_name.values()]
+
+
+class ReggenParams(Params):
+    @staticmethod
+    def from_raw(where: str, raw: object) -> 'ReggenParams':
+        ret = ReggenParams()
+        rl = check_list(raw, where)
+        for idx, r_param in enumerate(rl):
+            entry_where = 'entry {} in {}'.format(idx + 1, where)
+            param = _parse_parameter(entry_where, r_param)
+            if param.name in ret:
+                raise ValueError('At {}, found a duplicate parameter with '
+                                 'name {}.'
+                                 .format(entry_where, param.name))
+            ret.add(param)
+        return ret
+
+    def get_localparams(self) -> List[LocalParam]:
+        ret = []
+        for param in self.by_name.values():
+            if isinstance(param, LocalParam):
+                ret.append(param)
+        return ret
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_base.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_base.py
new file mode 100644
index 00000000..eb88b463
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_base.py
@@ -0,0 +1,45 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import List
+
+from .field import Field
+
+
+class RegBase:
+    '''An abstract class inherited by Register and MultiRegister
+
+    This represents a block of one or more registers with a base address.
+
+    '''
+    def __init__(self, offset: int):
+        self.offset = offset
+
+    def get_n_bits(self, bittype: List[str]) -> int:
+        '''Get the size of this register / these registers in bits
+
+        See Field.get_n_bits() for the precise meaning of bittype.
+
+        '''
+        raise NotImplementedError()
+
+    def get_field_list(self) -> List[Field]:
+        '''Get an ordered list of the fields in the register(s)
+
+        Registers are ordered from low to high address. Within a register,
+        fields are ordered as Register.fields: from LSB to MSB.
+
+        '''
+        raise NotImplementedError()
+
+    def is_homogeneous(self) -> bool:
+        '''True if every field in the block is identical
+
+        For a single register, this is true if it only has one field. For a
+        multireg, it is true if the generating register has just one field.
+        Note that if the compact flag is set, the generated registers might
+        have multiple (replicated) fields.
+
+        '''
+        raise NotImplementedError()
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_block.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_block.py
new file mode 100644
index 00000000..30a4f747
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_block.py
@@ -0,0 +1,431 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+'''Code representing the registers, windows etc. for a block'''
+
+import re
+from typing import Callable, Dict, List, Optional, Sequence, Union
+
+from .alert import Alert
+from .access import SWAccess, HWAccess
+from .field import Field
+from .signal import Signal
+from .lib import check_int, check_list, check_str_dict, check_str
+from .multi_register import MultiRegister
+from .params import ReggenParams
+from .register import Register
+from .window import Window
+
+
+class RegBlock:
+    def __init__(self, reg_width: int, params: ReggenParams):
+
+        self._addrsep = (reg_width + 7) // 8
+        self._reg_width = reg_width
+        self._params = params
+
+        self.offset = 0
+        self.multiregs = []  # type: List[MultiRegister]
+        self.registers = []  # type: List[Register]
+        self.windows = []  # type: List[Window]
+
+        # Boolean indication whether ANY window in regblock has data integrity passthrough
+        self.has_data_intg_passthru = False
+
+        # A list of all registers, expanding multiregs, ordered by offset
+        self.flat_regs = []  # type: List[Register]
+
+        # A list of registers and multiregisters (unexpanded)
+        self.all_regs = []  # type: List[Union[Register, MultiRegister]]
+
+        # A list with everything in order
+        self.entries = []  # type: List[object]
+
+        # A dict of named entries, mapping name to offset
+        self.name_to_offset = {}  # type: Dict[str, int]
+
+        # A dict of all registers (expanding multiregs), mapping name to the
+        # register object
+        self.name_to_flat_reg = {}  # type: Dict[str, Register]
+
+        # A list of all write enable names
+        self.wennames = []  # type: List[str]
+
+    @staticmethod
+    def build_blocks(block: 'RegBlock',
+                     raw: object) -> Dict[Optional[str], 'RegBlock']:
+        '''Build a dictionary of blocks for a 'registers' field in the hjson
+
+        There are two different syntaxes we might see here. The simple syntax
+        just consists of a list of entries (register, multireg, window,
+        skipto). If we see that, each entry gets added to init_block and then
+        we return {None: init_block}.
+
+        The more complicated syntax is a dictionary. This parses from hjson as
+        an OrderedDict which we walk in document order. Entries from the first
+        key/value pair in the dictionary will be added to init_block. Later
+        key/value pairs start empty RegBlocks. The return value is a dictionary
+        mapping the keys we saw to their respective RegBlocks.
+
+        '''
+        if isinstance(raw, list):
+            # This is the simple syntax
+            block.add_raw_registers(raw, 'registers field at top-level')
+            return {None: block}
+
+        # This is the more complicated syntax
+        if not isinstance(raw, dict):
+            raise ValueError('registers field at top-level is '
+                             'neither a list or a dictionary.')
+
+        ret = {}  # type: Dict[Optional[str], RegBlock]
+        for idx, (r_key, r_val) in enumerate(raw.items()):
+            if idx > 0:
+                block = RegBlock(block._reg_width, block._params)
+
+            rb_key = check_str(r_key,
+                               'the key for item {} of '
+                               'the registers dictionary at top-level'
+                               .format(idx + 1))
+            rb_val = check_list(r_val,
+                                'the value for item {} of '
+                                'the registers dictionary at top-level'
+                                .format(idx + 1))
+
+            block.add_raw_registers(rb_val,
+                                    'item {} of the registers '
+                                    'dictionary at top-level'
+                                    .format(idx + 1))
+            block.validate()
+
+            assert rb_key not in ret
+            ret[rb_key] = block
+
+        return ret
+
+    def add_raw_registers(self, raw: object, what: str) -> None:
+        rl = check_list(raw, 'registers field at top-level')
+        for entry_idx, entry_raw in enumerate(rl):
+            where = ('entry {} of the top-level registers field'
+                     .format(entry_idx + 1))
+            self.add_raw(where, entry_raw)
+
+    def add_raw(self, where: str, raw: object) -> None:
+        entry = check_str_dict(raw, where)
+
+        handlers = {
+            'register': self._handle_register,
+            'reserved': self._handle_reserved,
+            'skipto': self._handle_skipto,
+            'window': self._handle_window,
+            'multireg': self._handle_multireg
+        }
+
+        entry_type = 'register'
+        entry_body = entry  # type: object
+
+        for t in ['reserved', 'skipto', 'window', 'multireg']:
+            t_body = entry.get(t)
+            if t_body is not None:
+                # Special entries look like { window: { ... } }, so if we
+                # get a hit, this should be the only key in entry. Note
+                # that this also checks that nothing has more than one
+                # entry type.
+                if len(entry) != 1:
+                    other_keys = [k for k in entry if k != t]
+                    assert other_keys
+                    raise ValueError('At offset {:#x}, {} has key {}, which '
+                                     'should give its type. But it also has '
+                                     'other keys too: {}.'
+                                     .format(self.offset,
+                                             where, t, ', '.join(other_keys)))
+                entry_type = t
+                entry_body = t_body
+
+        entry_where = ('At offset {:#x}, {}, type {!r}'
+                       .format(self.offset, where, entry_type))
+
+        handlers[entry_type](entry_where, entry_body)
+
+    def _handle_register(self, where: str, body: object) -> None:
+        reg = Register.from_raw(self._reg_width,
+                                self.offset, self._params, body)
+        self.add_register(reg)
+
+    def _handle_reserved(self, where: str, body: object) -> None:
+        nreserved = check_int(body, 'body of ' + where)
+        if nreserved <= 0:
+            raise ValueError('Reserved count in {} is {}, '
+                             'which is not positive.'
+                             .format(where, nreserved))
+
+        self.offset += self._addrsep * nreserved
+
+    def _handle_skipto(self, where: str, body: object) -> None:
+        skipto = check_int(body, 'body of ' + where)
+        if skipto < self.offset:
+            raise ValueError('Destination of skipto in {} is {:#x}, '
+                             'is less than the current offset, {:#x}.'
+                             .format(where, skipto, self.offset))
+        if skipto % self._addrsep:
+            raise ValueError('Destination of skipto in {} is {:#x}, '
+                             'not a multiple of addrsep, {:#x}.'
+                             .format(where, skipto, self._addrsep))
+        self.offset = skipto
+
+    def _handle_window(self, where: str, body: object) -> None:
+        window = Window.from_raw(self.offset,
+                                 self._reg_width, self._params, body)
+        if window.name is not None:
+            lname = window.name.lower()
+            if lname in self.name_to_offset:
+                raise ValueError('Window {} (at offset {:#x}) has the '
+                                 'same name as something at offset {:#x}.'
+                                 .format(window.name, window.offset,
+                                         self.name_to_offset[lname]))
+        self.add_window(window)
+
+    def _handle_multireg(self, where: str, body: object) -> None:
+        mr = MultiRegister(self.offset,
+                           self._addrsep, self._reg_width, self._params, body)
+        for reg in mr.regs:
+            lname = reg.name.lower()
+            if lname in self.name_to_offset:
+                raise ValueError('Multiregister {} (at offset {:#x}) expands '
+                                 'to a register with name {} (at offset '
+                                 '{:#x}), but this already names something at '
+                                 'offset {:#x}.'
+                                 .format(mr.reg.name, mr.reg.offset,
+                                         reg.name, reg.offset,
+                                         self.name_to_offset[lname]))
+            self._add_flat_reg(reg)
+            self.name_to_offset[lname] = reg.offset
+
+        self.multiregs.append(mr)
+        self.all_regs.append(mr)
+        self.entries.append(mr)
+        self.offset = mr.next_offset(self._addrsep)
+
+    def add_register(self, reg: Register) -> None:
+        assert reg.offset == self.offset
+
+        lname = reg.name.lower()
+        if lname in self.name_to_offset:
+            raise ValueError('Register {} (at offset {:#x}) has the same '
+                             'name as something at offset {:#x}.'
+                             .format(reg.name, reg.offset,
+                                     self.name_to_offset[lname]))
+        self._add_flat_reg(reg)
+        self.name_to_offset[lname] = reg.offset
+
+        self.registers.append(reg)
+        self.all_regs.append(reg)
+        self.entries.append(reg)
+        self.offset = reg.next_offset(self._addrsep)
+
+        if reg.regwen is not None and reg.regwen not in self.wennames:
+            self.wennames.append(reg.regwen)
+
+    def _add_flat_reg(self, reg: Register) -> None:
+        # The first assertion is checked at the call site (where we can print
+        # out a nicer message for multiregs). The second assertion should be
+        # implied by the first.
+        assert reg.name not in self.name_to_offset
+        assert reg.name not in self.name_to_flat_reg
+
+        self.flat_regs.append(reg)
+        self.name_to_flat_reg[reg.name.lower()] = reg
+
+    def add_window(self, window: Window) -> None:
+        if window.name is not None:
+            lname = window.name.lower()
+            assert lname not in self.name_to_offset
+            self.name_to_offset[lname] = window.offset
+
+        self.windows.append(window)
+        self.entries.append(window)
+        assert self.offset <= window.offset
+        self.offset = window.next_offset(self._addrsep)
+
+        self.has_data_intg_passthru |= window.data_intg_passthru
+
+    def validate(self) -> None:
+        '''Run this to check consistency after all registers have been added'''
+
+        # Check that every write-enable register has a good name, a valid reset
+        # value, and valid access permissions.
+        for wenname in self.wennames:
+            # check the REGWEN naming convention
+            if re.fullmatch(r'(.+_)*REGWEN(_[0-9]+)?', wenname) is None:
+                raise ValueError("Regwen name {} must have the suffix '_REGWEN'"
+                                 .format(wenname))
+
+            wen_reg = self.name_to_flat_reg.get(wenname.lower())
+            if wen_reg is None:
+                raise ValueError('One or more registers use {} as a '
+                                 'write-enable, but there is no such register.'
+                                 .format(wenname))
+
+            # If the REGWEN bit is SW controlled, check that the register
+            # defaults to enabled. If this bit is read-only by SW and hence
+            # hardware controlled, we do not enforce this requirement.
+            if wen_reg.swaccess.key != "ro" and not wen_reg.resval:
+                raise ValueError('One or more registers use {} as a '
+                                 'write-enable. Since it is SW-controlled '
+                                 'it should have a nonzero reset value.'
+                                 .format(wenname))
+
+            if wen_reg.swaccess.key == "rw0c":
+                # The register is software managed: all good!
+                continue
+
+            if wen_reg.swaccess.key == "ro" and wen_reg.hwaccess.key == "hwo":
+                # The register is hardware managed: that's fine too.
+                continue
+
+            raise ValueError('One or more registers use {} as a write-enable. '
+                             'However, it has invalid access permissions '
+                             '({} / {}). It should either have swaccess=RW0C '
+                             'or have swaccess=RO and hwaccess=HWO.'
+                             .format(wenname,
+                                     wen_reg.swaccess.key,
+                                     wen_reg.hwaccess.key))
+
+    def get_n_bits(self, bittype: List[str] = ["q"]) -> int:
+        '''Returns number of bits in registers in this block.
+
+        This includes those expanded from multiregs. See Field.get_n_bits for a
+        description of the bittype argument.
+
+        '''
+        return sum(reg.get_n_bits(bittype) for reg in self.flat_regs)
+
+    def as_dicts(self) -> List[object]:
+        entries = []  # type: List[object]
+        offset = 0
+        for entry in self.entries:
+            assert (isinstance(entry, Register) or
+                    isinstance(entry, MultiRegister) or
+                    isinstance(entry, Window))
+
+            next_off = entry.offset
+            assert offset <= next_off
+            res_bytes = next_off - offset
+            if res_bytes:
+                assert res_bytes % self._addrsep == 0
+                entries.append({'reserved': res_bytes // self._addrsep})
+
+            entries.append(entry)
+            offset = entry.next_offset(self._addrsep)
+
+        return entries
+
+    _FieldFormatter = Callable[[bool, str], str]
+
+    def _add_intr_alert_reg(self,
+                            signals: Sequence[Signal],
+                            reg_name: str,
+                            reg_desc: str,
+                            field_desc_fmt: Optional[Union[str, _FieldFormatter]],
+                            swaccess: str,
+                            hwaccess: str,
+                            is_testreg: bool,
+                            reg_tags: List[str]) -> None:
+        swaccess_obj = SWAccess('RegBlock._make_intr_alert_reg()', swaccess)
+        hwaccess_obj = HWAccess('RegBlock._make_intr_alert_reg()', hwaccess)
+
+        fields = []
+        for signal in signals:
+            if field_desc_fmt is None:
+                field_desc = signal.desc
+            elif isinstance(field_desc_fmt, str):
+                field_desc = field_desc_fmt
+            else:
+                width = signal.bits.width()
+                field_desc = field_desc_fmt(width > 1, signal.name)
+
+            fields.append(Field(signal.name,
+                                field_desc or signal.desc,
+                                tags=[],
+                                swaccess=swaccess_obj,
+                                hwaccess=hwaccess_obj,
+                                hwqe=is_testreg,
+                                hwre=False,
+                                bits=signal.bits,
+                                resval=0,
+                                enum=None))
+
+        reg = Register(self.offset,
+                       reg_name,
+                       reg_desc,
+                       swaccess_obj,
+                       hwaccess_obj,
+                       hwext=is_testreg,
+                       hwqe=is_testreg,
+                       hwre=False,
+                       regwen=None,
+                       tags=reg_tags,
+                       resval=None,
+                       shadowed=False,
+                       fields=fields,
+                       update_err_alert=None,
+                       storage_err_alert=None)
+        self.add_register(reg)
+
+    def make_intr_regs(self, interrupts: Sequence[Signal]) -> None:
+        assert interrupts
+        assert interrupts[-1].bits.msb < self._reg_width
+
+        self._add_intr_alert_reg(interrupts,
+                                 'INTR_STATE',
+                                 'Interrupt State Register',
+                                 None,
+                                 'rw1c',
+                                 'hrw',
+                                 False,
+                                 # intr_state csr is affected by writes to
+                                 # other csrs - skip write-check
+                                 ["excl:CsrNonInitTests:CsrExclWriteCheck"])
+        self._add_intr_alert_reg(interrupts,
+                                 'INTR_ENABLE',
+                                 'Interrupt Enable Register',
+                                 lambda w, n: ('Enable interrupt when '
+                                               '{}!!INTR_STATE.{} is set.'
+                                               .format('corresponding bit in '
+                                                       if w else '',
+                                                       n)),
+                                 'rw',
+                                 'hro',
+                                 False,
+                                 [])
+        self._add_intr_alert_reg(interrupts,
+                                 'INTR_TEST',
+                                 'Interrupt Test Register',
+                                 lambda w, n: ('Write 1 to force '
+                                               '{}!!INTR_STATE.{} to 1.'
+                                               .format('corresponding bit in '
+                                                       if w else '',
+                                                       n)),
+                                 'wo',
+                                 'hro',
+                                 True,
+                                 # intr_test csr is WO so reads back 0s
+                                 ["excl:CsrNonInitTests:CsrExclWrite"])
+
+    def make_alert_regs(self, alerts: List[Alert]) -> None:
+        assert alerts
+        assert len(alerts) < self._reg_width
+        self._add_intr_alert_reg(alerts,
+                                 'ALERT_TEST',
+                                 'Alert Test Register',
+                                 ('Write 1 to trigger '
+                                  'one alert event of this kind.'),
+                                 'wo',
+                                 'hro',
+                                 True,
+                                 [])
+
+    def get_addr_width(self) -> int:
+        '''Calculate the number of bits to address every byte of the block'''
+        return (self.offset - 1).bit_length()
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_html.css b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_html.css
new file mode 100644
index 00000000..4cb48edb
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_html.css
@@ -0,0 +1,74 @@
+/* Stylesheet for reggen HTML register output */
+/* Copyright lowRISC contributors. */
+/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+table.regpic {
+    width: 95%;
+    border-collapse: collapse;
+    margin-left:auto; 
+    margin-right:auto;
+    table-layout:fixed;
+}
+
+table.regdef {
+    border: 1px solid black;
+    width: 80%;
+    border-collapse: collapse;
+    margin-left:auto; 
+    margin-right:auto;
+    table-layout:auto;
+}
+
+table.regdef th {
+    border: 1px solid black;
+    font-family: sans-serif;
+
+}
+
+td.bitnum {
+    font-size: 60%;
+    text-align: center;
+}
+
+td.unused {
+    border: 1px solid black;
+    background-color: gray;
+}
+
+td.fname {
+    border: 1px solid black;
+    text-align: center;
+    font-family: sans-serif;
+}
+
+
+td.regbits, td.regperm, td.regrv {
+    border: 1px solid black;
+    text-align: center;
+    font-family: sans-serif;
+}
+
+td.regde, td.regfn {
+    border: 1px solid black;
+}
+
+table.cfgtable {
+    border: 1px solid black;
+    width: 80%;
+    border-collapse: collapse;
+    margin-left:auto;
+    margin-right:auto;
+    table-layout:auto;
+}
+
+table.cfgtable th {
+    border: 1px solid black;
+    font-family: sans-serif;
+    font-weight: bold;
+}
+
+table.cfgtable td {
+    border: 1px solid black;
+    font-family: sans-serif;
+}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_pkg.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_pkg.sv.tpl
new file mode 100644
index 00000000..1c5520a5
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_pkg.sv.tpl
@@ -0,0 +1,347 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+<%
+  from topgen import lib # TODO: Split lib to common lib module
+
+  from reggen.access import HwAccess, SwRdAccess, SwWrAccess
+  from reggen.register import Register
+  from reggen.multi_register import MultiRegister
+
+  from reggen import gen_rtl
+
+  localparams = block.params.get_localparams()
+
+  addr_widths = gen_rtl.get_addr_widths(block)
+
+  lblock = block.name.lower()
+  ublock = lblock.upper()
+
+  def reg_pfx(reg):
+    return '{}_{}'.format(ublock, reg.name.upper())
+
+  def reg_resname(reg):
+    return '{}_RESVAL'.format(reg_pfx(reg))
+
+  def field_resname(reg, field):
+    return '{}_{}_RESVAL'.format(reg_pfx(reg), field.name.upper())
+
+%>\
+<%def name="typedefs_for_iface(iface_name, iface_desc, for_iface, rb)">\
+<%
+   hdr = gen_rtl.make_box_quote('Typedefs for registers' + for_iface)
+%>\
+% for r in rb.all_regs:
+  % if r.get_n_bits(["q"]):
+    % if hdr:
+
+${hdr}
+    % endif
+<%
+    r0 = gen_rtl.get_r0(r)
+    hdr = None
+%>\
+
+  typedef struct packed {
+    % if r.is_homogeneous():
+      ## If we have a homogeneous register or multireg, there is just one field
+      ## (possibly replicated many times). The typedef is for one copy of that
+      ## field.
+<%
+      field = r.get_field_list()[0]
+      field_q_width = field.get_n_bits(r0.hwext, ['q'])
+      field_q_bits = lib.bitarray(field_q_width, 2)
+%>\
+    logic ${field_q_bits} q;
+      % if field.hwqe:
+    logic        qe;
+      % endif
+      % if field.hwre or (r0.shadowed and r0.hwext):
+    logic        re;
+      % endif
+      % if r0.shadowed and not r0.hwext:
+    logic        err_update;
+    logic        err_storage;
+      % endif
+    % else:
+      ## We are inhomogeneous, which means there is more than one different
+      ## field. Generate a reg2hw typedef that packs together all the fields of
+      ## the register.
+      % for f in r0.fields:
+        % if f.get_n_bits(r0.hwext, ["q"]) >= 1:
+<%
+          field_q_width = f.get_n_bits(r0.hwext, ['q'])
+          field_q_bits = lib.bitarray(field_q_width, 2)
+
+          struct_name = f.name.lower()
+%>\
+    struct packed {
+      logic ${field_q_bits} q;
+          % if f.hwqe:
+      logic        qe;
+          % endif
+          % if f.hwre or (r0.shadowed and r0.hwext):
+      logic        re;
+          % endif
+          % if r0.shadowed and not r0.hwext:
+      logic        err_update;
+      logic        err_storage;
+          % endif
+    } ${struct_name};
+        %endif
+      %endfor
+    %endif
+  } ${gen_rtl.get_reg_tx_type(block, r, False)};
+  %endif
+% endfor
+% for r in rb.all_regs:
+  % if r.get_n_bits(["d"]):
+    % if hdr:
+
+${hdr}
+    % endif
+<%
+    r0 = gen_rtl.get_r0(r)
+    hdr = None
+%>\
+
+  typedef struct packed {
+    % if r.is_homogeneous():
+      ## If we have a homogeneous register or multireg, there is just one field
+      ## (possibly replicated many times). The typedef is for one copy of that
+      ## field.
+<%
+      field = r.get_field_list()[0]
+      field_d_width = field.get_n_bits(r0.hwext, ['d'])
+      field_d_bits = lib.bitarray(field_d_width, 2)
+%>\
+    logic ${field_d_bits} d;
+      % if not r0.hwext:
+    logic        de;
+      % endif
+    % else:
+      ## We are inhomogeneous, which means there is more than one different
+      ## field. Generate a hw2reg typedef that packs together all the fields of
+      ## the register.
+      % for f in r0.fields:
+        % if f.get_n_bits(r0.hwext, ["d"]) >= 1:
+<%
+          field_d_width = f.get_n_bits(r0.hwext, ['d'])
+          field_d_bits = lib.bitarray(field_d_width, 2)
+
+          struct_name = f.name.lower()
+%>\
+    struct packed {
+      logic ${field_d_bits} d;
+          % if not r0.hwext:
+      logic        de;
+          % endif
+    } ${struct_name};
+        %endif
+      %endfor
+    %endif
+  } ${gen_rtl.get_reg_tx_type(block, r, True)};
+  % endif
+% endfor
+</%def>\
+<%def name="reg2hw_for_iface(iface_name, iface_desc, for_iface, rb)">\
+<%
+nbits = rb.get_n_bits(["q", "qe", "re"])
+packbit = 0
+%>\
+% if nbits > 0:
+
+  // Register -> HW type${for_iface}
+  typedef struct packed {
+% for r in rb.all_regs:
+  % if r.get_n_bits(["q"]):
+<%
+    r0 = gen_rtl.get_r0(r)
+    struct_type = gen_rtl.get_reg_tx_type(block, r, False)
+    struct_width = r0.get_n_bits(['q', 'qe', 're'])
+
+    if isinstance(r, MultiRegister):
+      struct_type += " [{}:0]".format(r.count - 1)
+      struct_width *= r.count
+
+    msb = nbits - packbit - 1
+    lsb = msb - struct_width + 1
+    packbit += struct_width
+%>\
+    ${struct_type} ${r0.name.lower()}; // [${msb}:${lsb}]
+  % endif
+% endfor
+  } ${gen_rtl.get_iface_tx_type(block, iface_name, False)};
+% endif
+</%def>\
+<%def name="hw2reg_for_iface(iface_name, iface_desc, for_iface, rb)">\
+<%
+nbits = rb.get_n_bits(["d", "de"])
+packbit = 0
+%>\
+% if nbits > 0:
+
+  // HW -> register type${for_iface}
+  typedef struct packed {
+% for r in rb.all_regs:
+  % if r.get_n_bits(["d"]):
+<%
+    r0 = gen_rtl.get_r0(r)
+    struct_type = gen_rtl.get_reg_tx_type(block, r, True)
+    struct_width = r0.get_n_bits(['d', 'de'])
+
+    if isinstance(r, MultiRegister):
+      struct_type += " [{}:0]".format(r.count - 1)
+      struct_width *= r.count
+
+    msb = nbits - packbit - 1
+    lsb = msb - struct_width + 1
+    packbit += struct_width
+%>\
+    ${struct_type} ${r0.name.lower()}; // [${msb}:${lsb}]
+  % endif
+% endfor
+  } ${gen_rtl.get_iface_tx_type(block, iface_name, True)};
+% endif
+</%def>\
+<%def name="offsets_for_iface(iface_name, iface_desc, for_iface, rb)">\
+% if not rb.flat_regs:
+<% return STOP_RENDERING %>
+% endif
+
+  // Register offsets${for_iface}
+<%
+aw_name, aw = addr_widths[iface_name]
+%>\
+% for r in rb.flat_regs:
+<%
+value = "{}'h {:x}".format(aw, r.offset)
+%>\
+  parameter logic [${aw_name}-1:0] ${reg_pfx(r)}_OFFSET = ${value};
+% endfor
+</%def>\
+<%def name="hwext_resvals_for_iface(iface_name, iface_desc, for_iface, rb)">\
+<%
+  hwext_regs = [r for r in rb.flat_regs if r.hwext]
+%>\
+% if hwext_regs:
+
+  // Reset values for hwext registers and their fields${for_iface}
+  % for reg in hwext_regs:
+<%
+    reg_width = reg.get_width()
+    reg_msb = reg_width - 1
+    reg_resval = "{}'h {:x}".format(reg_width, reg.resval)
+%>\
+  parameter logic [${reg_msb}:0] ${reg_resname(reg)} = ${reg_resval};
+    % for field in reg.fields:
+      % if field.resval is not None:
+<%
+    field_width = field.bits.width()
+    field_msb = field_width - 1
+    field_resval = "{}'h {:x}".format(field_width, field.resval)
+%>\
+  parameter logic [${field_msb}:0] ${field_resname(reg, field)} = ${field_resval};
+      % endif
+    % endfor
+  % endfor
+% endif
+</%def>\
+<%def name="windows_for_iface(iface_name, iface_desc, for_iface, rb)">\
+% if rb.windows:
+<%
+  aw_name, aw = addr_widths[iface_name]
+%>\
+
+  // Window parameters${for_iface}
+% for i,w in enumerate(rb.windows):
+<%
+    win_pfx = '{}_{}'.format(ublock, w.name.upper())
+    base_txt_val = "{}'h {:x}".format(aw, w.offset)
+    size_txt_val = "'h {:x}".format(w.size_in_bytes)
+
+    offset_type = 'logic [{}-1:0]'.format(aw_name)
+    size_type = 'int unsigned'
+    max_type_len = max(len(offset_type), len(size_type))
+
+    offset_type += ' ' * (max_type_len - len(offset_type))
+    size_type += ' ' * (max_type_len - len(size_type))
+
+%>\
+  parameter ${offset_type} ${win_pfx}_OFFSET = ${base_txt_val};
+  parameter ${size_type} ${win_pfx}_SIZE   = ${size_txt_val};
+% endfor
+% endif
+</%def>\
+<%def name="reg_data_for_iface(iface_name, iface_desc, for_iface, rb)">\
+% if rb.flat_regs:
+<%
+  lpfx = gen_rtl.get_type_name_pfx(block, iface_name)
+  upfx = lpfx.upper()
+  idx_len = len("{}".format(len(rb.flat_regs) - 1))
+%>\
+
+  // Register index${for_iface}
+  typedef enum int {
+% for r in rb.flat_regs:
+    ${ublock}_${r.name.upper()}${"" if loop.last else ","}
+% endfor
+  } ${lpfx}_id_e;
+
+  // Register width information to check illegal writes${for_iface}
+  parameter logic [3:0] ${upfx}_PERMIT [${len(rb.flat_regs)}] = '{
+  % for i, r in enumerate(rb.flat_regs):
+<%
+  index_str = "{}".format(i).rjust(idx_len)
+  width = r.get_width()
+  if width > 24:
+    mask = '1111'
+  elif width > 16:
+    mask = '0111'
+  elif width > 8:
+    mask = '0011'
+  else:
+    mask = '0001'
+
+  comma = ',' if i < len(rb.flat_regs) - 1 else ' '
+%>\
+    4'b ${mask}${comma} // index[${index_str}] ${ublock}_${r.name.upper()}
+  % endfor
+  };
+% endif
+</%def>\
+
+package ${lblock}_reg_pkg;
+% if localparams:
+
+  // Param list
+% for param in localparams:
+  parameter ${param.param_type} ${param.name} = ${param.value};
+% endfor
+% endif
+
+  // Address widths within the block
+% for param_name, width in addr_widths.values():
+  parameter int ${param_name} = ${width};
+% endfor
+<%
+  just_default = len(block.reg_blocks) == 1 and None in block.reg_blocks
+%>\
+% for iface_name, rb in block.reg_blocks.items():
+<%
+  iface_desc = iface_name or 'default'
+  for_iface = '' if just_default else ' for {} interface'.format(iface_desc)
+%>\
+${typedefs_for_iface(iface_name, iface_desc, for_iface, rb)}\
+${reg2hw_for_iface(iface_name, iface_desc, for_iface, rb)}\
+${hw2reg_for_iface(iface_name, iface_desc, for_iface, rb)}\
+${offsets_for_iface(iface_name, iface_desc, for_iface, rb)}\
+${hwext_resvals_for_iface(iface_name, iface_desc, for_iface, rb)}\
+${windows_for_iface(iface_name, iface_desc, for_iface, rb)}\
+${reg_data_for_iface(iface_name, iface_desc, for_iface, rb)}\
+% endfor
+
+endpackage
+
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_top.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_top.sv.tpl
new file mode 100644
index 00000000..4cd9036a
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/reg_top.sv.tpl
@@ -0,0 +1,712 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+<%
+  from reggen import gen_rtl
+  from reggen.access import HwAccess, SwRdAccess, SwWrAccess
+  from reggen.lib import get_basename
+  from reggen.register import Register
+  from reggen.multi_register import MultiRegister
+  from reggen.ip_block import IpBlock
+  from reggen.bus_interfaces import BusProtocol
+
+  num_wins = len(rb.windows)
+  num_wins_width = ((num_wins+1).bit_length()) - 1
+  num_reg_dsp = 1 if rb.all_regs else 0
+  num_dsp  = num_wins + num_reg_dsp
+  regs_flat = rb.flat_regs
+  max_regs_char = len("{}".format(len(regs_flat) - 1))
+  addr_width = rb.get_addr_width()
+
+  lblock = block.name.lower()
+  ublock = lblock.upper()
+
+  u_mod_base = mod_base.upper()
+
+  reg2hw_t = gen_rtl.get_iface_tx_type(block, if_name, False)
+  hw2reg_t = gen_rtl.get_iface_tx_type(block, if_name, True)
+
+  # Calculate whether we're going to need an AW parameter. We use it if there
+  # are any registers (obviously). We also use it if there are any windows that
+  # don't start at zero and end at 1 << addr_width (see the "addr_checks"
+  # calculation below for where that comes from).
+  needs_aw = (bool(regs_flat) or
+              num_wins > 1 or
+              rb.windows and (
+                rb.windows[0].offset != 0 or
+                rb.windows[0].size_in_bytes != (1 << addr_width)))
+
+  # Check if the interface protocol is reg_interface
+  use_reg_iface = any([interface['protocol'] == BusProtocol.REG_IFACE and not interface['is_host'] for interface in block.bus_interfaces.interface_list])
+  reg_intf_req = "reg_req_t"
+  reg_intf_rsp = "reg_rsp_t"
+
+  common_data_intg_gen = 0 if rb.has_data_intg_passthru else 1
+  adapt_data_intg_gen = 1 if rb.has_data_intg_passthru else 0
+  assert common_data_intg_gen != adapt_data_intg_gen
+%>
+
+% if use_reg_iface:
+`include "common_cells/assertions.svh"
+% else:
+`include "prim_assert.sv"
+% endif
+
+module ${mod_name} \
+% if use_reg_iface:
+#(
+    parameter type reg_req_t = logic,
+    parameter type reg_rsp_t = logic,
+    parameter int AW = ${addr_width}
+) \
+% else:
+    % if needs_aw:
+#(
+    parameter int AW = ${addr_width}
+) \
+    % endif
+% endif
+(
+  input clk_i,
+  input rst_ni,
+% if use_reg_iface:
+  input  ${reg_intf_req} reg_req_i,
+  output ${reg_intf_rsp} reg_rsp_o,
+% else:
+  input  tlul_pkg::tl_h2d_t tl_i,
+  output tlul_pkg::tl_d2h_t tl_o,
+% endif
+% if num_wins != 0:
+
+  // Output port for window
+% if use_reg_iface:
+  output ${reg_intf_req} [${num_wins}-1:0] reg_req_win_o,
+  input  ${reg_intf_rsp} [${num_wins}-1:0] reg_rsp_win_i,
+% else:
+  output tlul_pkg::tl_h2d_t tl_win_o  [${num_wins}],
+  input  tlul_pkg::tl_d2h_t tl_win_i  [${num_wins}],
+% endif
+
+% endif
+  // To HW
+% if rb.get_n_bits(["q","qe","re"]):
+  output ${lblock}_reg_pkg::${reg2hw_t} reg2hw, // Write
+% endif
+% if rb.get_n_bits(["d","de"]):
+  input  ${lblock}_reg_pkg::${hw2reg_t} hw2reg, // Read
+% endif
+
+% if not use_reg_iface:
+  // Integrity check errors
+  output logic intg_err_o,
+% endif
+
+  // Config
+  input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+  import ${lblock}_reg_pkg::* ;
+
+% if rb.all_regs:
+  localparam int DW = ${block.regwidth};
+  localparam int DBW = DW/8;                    // Byte Width
+
+  // register signals
+  logic           reg_we;
+  logic           reg_re;
+  logic [AW-1:0]  reg_addr;
+  logic [DW-1:0]  reg_wdata;
+  logic [DBW-1:0] reg_be;
+  logic [DW-1:0]  reg_rdata;
+  logic           reg_error;
+
+  logic          addrmiss, wr_err;
+
+  logic [DW-1:0] reg_rdata_next;
+
+% if use_reg_iface:
+  // Below register interface can be changed
+  reg_req_t  reg_intf_req;
+  reg_rsp_t  reg_intf_rsp;
+% else:
+  tlul_pkg::tl_h2d_t tl_reg_h2d;
+  tlul_pkg::tl_d2h_t tl_reg_d2h;
+% endif
+% endif
+
+% if not use_reg_iface:
+  // incoming payload check
+  logic intg_err;
+  tlul_cmd_intg_chk u_chk (
+    .tl_i,
+    .err_o(intg_err)
+  );
+
+  logic intg_err_q;
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      intg_err_q <= '0;
+    end else if (intg_err) begin
+      intg_err_q <= 1'b1;
+    end
+  end
+
+  // integrity error output is permanent and should be used for alert generation
+  // register errors are transactional
+  assign intg_err_o = intg_err_q | intg_err;
+
+  // outgoing integrity generation
+  tlul_pkg::tl_d2h_t tl_o_pre;
+  tlul_rsp_intg_gen #(
+    .EnableRspIntgGen(1),
+    .EnableDataIntgGen(${common_data_intg_gen})
+  ) u_rsp_intg_gen (
+    .tl_i(tl_o_pre),
+    .tl_o
+  );
+% endif
+
+% if num_dsp == 1:
+  ## Either no windows (and just registers) or no registers and only
+  ## one window.
+  % if num_wins == 0:
+      % if use_reg_iface:
+  assign reg_intf_req = reg_req_i;
+  assign reg_rsp_o = reg_intf_rsp;
+      % else:
+  assign tl_reg_h2d = tl_i;
+  assign tl_o_pre   = tl_reg_d2h;
+      % endif
+  % else:
+      % if use_reg_iface:
+  assign reg_req_win_o = reg_req_i;
+  assign reg_rsp_o = reg_rsp_win_i
+      % else:
+  assign tl_win_o[0] = tl_i;
+  assign tl_o_pre    = tl_win_i[0];
+      % endif
+  % endif
+% else:
+  logic [${num_wins_width-1}:0] reg_steer;
+
+  % if use_reg_iface:
+  ${reg_intf_req} [${num_dsp}-1:0] reg_intf_demux_req;
+  ${reg_intf_rsp} [${num_dsp}-1:0] reg_intf_demux_rsp;
+
+  // demux connection
+  assign reg_intf_req = reg_intf_demux_req[${num_wins}];
+  assign reg_intf_demux_rsp[${num_wins}] = reg_intf_rsp;
+
+    % for i,t in enumerate(block.wins):
+  assign reg_req_win_o[${i}] = reg_intf_demux_req[${i}];
+  assign reg_intf_demux_rsp[${i}] = reg_rsp_win_i[${i}];
+    % endfor
+
+  // Create Socket_1n
+  reg_demux #(
+    .NoPorts  (${num_dsp}),
+    .req_t    (${reg_intf_req}),
+    .rsp_t    (${reg_intf_rsp})
+  ) i_reg_demux (
+    .clk_i,
+    .rst_ni,
+    .in_req_i (reg_req_i),
+    .in_rsp_o (reg_rsp_o),
+    .out_req_o (reg_intf_demux_req),
+    .out_rsp_i (reg_intf_demux_rsp),
+    .in_select_i (reg_steer)
+  );
+
+  % else:
+  tlul_pkg::tl_h2d_t tl_socket_h2d [${num_dsp}];
+  tlul_pkg::tl_d2h_t tl_socket_d2h [${num_dsp}];
+
+  // socket_1n connection
+  % if rb.all_regs:
+  assign tl_reg_h2d = tl_socket_h2d[${num_wins}];
+  assign tl_socket_d2h[${num_wins}] = tl_reg_d2h;
+
+  % endif
+  % for i,t in enumerate(rb.windows):
+  assign tl_win_o[${i}] = tl_socket_h2d[${i}];
+    % if common_data_intg_gen == 0 and rb.windows[i].data_intg_passthru == False:
+    ## If there are multiple windows, and not every window has data integrity
+    ## passthrough, we must generate data integrity for it here.
+  tlul_rsp_intg_gen #(
+    .EnableRspIntgGen(0),
+    .EnableDataIntgGen(1)
+  ) u_win${i}_data_intg_gen (
+    .tl_i(tl_win_i[${i}]),
+    .tl_o(tl_socket_d2h[${i}])
+  );
+    % else:
+  assign tl_socket_d2h[${i}] = tl_win_i[${i}];
+    % endif
+  % endfor
+
+  // Create Socket_1n
+  tlul_socket_1n #(
+    .N          (${num_dsp}),
+    .HReqPass   (1'b1),
+    .HRspPass   (1'b1),
+    .DReqPass   ({${num_dsp}{1'b1}}),
+    .DRspPass   ({${num_dsp}{1'b1}}),
+    .HReqDepth  (4'h0),
+    .HRspDepth  (4'h0),
+    .DReqDepth  ({${num_dsp}{4'h0}}),
+    .DRspDepth  ({${num_dsp}{4'h0}})
+  ) u_socket (
+    .clk_i,
+    .rst_ni,
+    .tl_h_i (tl_i),
+    .tl_h_o (tl_o_pre),
+    .tl_d_o (tl_socket_h2d),
+    .tl_d_i (tl_socket_d2h),
+    .dev_select_i (reg_steer)
+  );
+  % endif
+
+  // Create steering logic
+  always_comb begin
+    reg_steer = ${num_dsp-1};       // Default set to register
+
+    // TODO: Can below codes be unique case () inside ?
+  % for i,w in enumerate(rb.windows):
+<%
+      base_addr = w.offset
+      limit_addr = w.offset + w.size_in_bytes
+      if use_reg_iface:
+        hi_check = 'reg_req_i.addr[AW-1:0] < {}'.format(limit_addr)
+      else:
+        hi_check = 'tl_i.a_address[AW-1:0] < {}'.format(limit_addr)
+      addr_checks = []
+      if base_addr > 0:
+        if use_reg_iface:
+          addr_checks.append('reg_req_i.addr[AW-1:0] >= {}'.format(base_addr))
+        else:
+          addr_checks.append('tl_i.a_address[AW-1:0] >= {}'.format(base_addr))
+      if limit_addr < 2**addr_width:
+        if use_reg_iface:
+          addr_checks.append('reg_req_i.addr[AW-1:0] < {}'.format(limit_addr))
+        else:
+          addr_checks.append('tl_i.a_address[AW-1:0] < {}'.format(limit_addr))
+
+      addr_test = ' && '.join(addr_checks)
+%>\
+      % if addr_test:
+    if (${addr_test}) begin
+      % endif
+      reg_steer = ${i};
+      % if addr_test:
+    end
+      % endif
+  % endfor
+  % if not use_reg_iface:
+    if (intg_err) begin
+      reg_steer = ${num_dsp-1};
+    end
+  % endif
+  end
+% endif
+% if rb.all_regs:
+
+
+% if use_reg_iface:
+  assign reg_we = reg_intf_req.valid & reg_intf_req.write;
+  assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
+  assign reg_addr = reg_intf_req.addr;
+  assign reg_wdata = reg_intf_req.wdata;
+  assign reg_be = reg_intf_req.wstrb;
+  assign reg_intf_rsp.rdata = reg_rdata;
+  assign reg_intf_rsp.error = reg_error;
+  assign reg_intf_rsp.ready = 1'b1;
+% else:
+  tlul_adapter_reg #(
+    .RegAw(AW),
+    .RegDw(DW),
+    .EnableDataIntgGen(${adapt_data_intg_gen})
+  ) u_reg_if (
+    .clk_i,
+    .rst_ni,
+
+    .tl_i (tl_reg_h2d),
+    .tl_o (tl_reg_d2h),
+
+    .we_o    (reg_we),
+    .re_o    (reg_re),
+    .addr_o  (reg_addr),
+    .wdata_o (reg_wdata),
+    .be_o    (reg_be),
+    .rdata_i (reg_rdata),
+    .error_i (reg_error)
+  );
+% endif
+
+  assign reg_rdata = reg_rdata_next ;
+% if use_reg_iface:
+  assign reg_error = (devmode_i & addrmiss) | wr_err;
+% else:
+  assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+% endif
+
+
+  // Define SW related signals
+  // Format: <reg>_<field>_{wd|we|qs}
+  //        or <reg>_{wd|we|qs} if field == 1 or 0
+  % for r in regs_flat:
+    % if len(r.fields) == 1:
+${sig_gen(r.fields[0], r.name.lower(), r.hwext, r.shadowed)}\
+    % else:
+      % for f in r.fields:
+${sig_gen(f, r.name.lower() + "_" + f.name.lower(), r.hwext, r.shadowed)}\
+      % endfor
+    % endif
+  % endfor
+
+  // Register instances
+  % for r in rb.all_regs:
+  ######################## multiregister ###########################
+    % if isinstance(r, MultiRegister):
+<%
+      k = 0
+%>
+      % for sr in r.regs:
+  // Subregister ${k} of Multireg ${r.reg.name.lower()}
+  // R[${sr.name.lower()}]: V(${str(sr.hwext)})
+        % if len(sr.fields) == 1:
+<%
+          f = sr.fields[0]
+          finst_name = sr.name.lower()
+          fsig_name = r.reg.name.lower() + "[%d]" % k
+          k = k + 1
+%>
+${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)}
+        % else:
+          % for f in sr.fields:
+<%
+            finst_name = sr.name.lower() + "_" + f.name.lower()
+            if r.is_homogeneous():
+              fsig_name = r.reg.name.lower() + "[%d]" % k
+              k = k + 1
+            else:
+              fsig_name = r.reg.name.lower() + "[%d]" % k + "." + get_basename(f.name.lower())
+%>
+  // F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb}
+${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)}
+          % endfor
+<%
+          if not r.is_homogeneous():
+            k += 1
+%>
+        % endif
+        ## for: mreg_flat
+      % endfor
+######################## register with single field ###########################
+    % elif len(r.fields) == 1:
+  // R[${r.name.lower()}]: V(${str(r.hwext)})
+<%
+        f = r.fields[0]
+        finst_name = r.name.lower()
+        fsig_name = r.name.lower()
+%>
+${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)}
+######################## register with multiple fields ###########################
+    % else:
+  // R[${r.name.lower()}]: V(${str(r.hwext)})
+      % for f in r.fields:
+<%
+        finst_name = r.name.lower() + "_" + f.name.lower()
+        fsig_name = r.name.lower() + "." + f.name.lower()
+%>
+  //   F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb}
+${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)}
+      % endfor
+    % endif
+
+  ## for: rb.all_regs
+  % endfor
+
+
+  logic [${len(regs_flat)-1}:0] addr_hit;
+  always_comb begin
+    addr_hit = '0;
+    % for i,r in enumerate(regs_flat):
+    addr_hit[${"{}".format(i).rjust(max_regs_char)}] = (reg_addr == ${ublock}_${r.name.upper()}_OFFSET);
+    % endfor
+  end
+
+  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+% if regs_flat:
+<%
+    # We want to signal wr_err if reg_be (the byte enable signal) is true for
+    # any bytes that aren't supported by a register. That's true if a
+    # addr_hit[i] and a bit is set in reg_be but not in *_PERMIT[i].
+
+    wr_err_terms = ['(addr_hit[{idx}] & (|({mod}_PERMIT[{idx}] & ~reg_be)))'
+                    .format(idx=str(i).rjust(max_regs_char),
+                            mod=u_mod_base)
+                    for i in range(len(regs_flat))]
+    wr_err_expr = (' |\n' + (' ' * 15)).join(wr_err_terms)
+%>\
+  // Check sub-word write is permitted
+  always_comb begin
+    wr_err = (reg_we &
+              (${wr_err_expr}));
+  end
+% else:
+  assign wr_error = 1'b0;
+% endif\
+
+  % for i, r in enumerate(regs_flat):
+    % if len(r.fields) == 1:
+${we_gen(r.fields[0], r.name.lower(), r.hwext, r.shadowed, i)}\
+    % else:
+      % for f in r.fields:
+${we_gen(f, r.name.lower() + "_" + f.name.lower(), r.hwext, r.shadowed, i)}\
+      % endfor
+    % endif
+  % endfor
+
+  // Read data return
+  always_comb begin
+    reg_rdata_next = '0;
+    unique case (1'b1)
+      % for i, r in enumerate(regs_flat):
+        % if len(r.fields) == 1:
+      addr_hit[${i}]: begin
+${rdata_gen(r.fields[0], r.name.lower())}\
+      end
+
+        % else:
+      addr_hit[${i}]: begin
+          % for f in r.fields:
+${rdata_gen(f, r.name.lower() + "_" + f.name.lower())}\
+          % endfor
+      end
+
+        % endif
+      % endfor
+      default: begin
+        reg_rdata_next = '1;
+      end
+    endcase
+  end
+% endif
+
+  // Unused signal tieoff
+% if rb.all_regs:
+
+  // wdata / byte enable are not always fully used
+  // add a blanket unused statement to handle lint waivers
+  logic unused_wdata;
+  logic unused_be;
+  assign unused_wdata = ^reg_wdata;
+  assign unused_be = ^reg_be;
+% else:
+  // devmode_i is not used if there are no registers
+  logic unused_devmode;
+  assign unused_devmode = ^devmode_i;
+% endif
+% if rb.all_regs:
+
+  // Assertions for Register Interface
+% if not use_reg_iface:
+  `ASSERT_PULSE(wePulse, reg_we)
+  `ASSERT_PULSE(rePulse, reg_re)
+
+  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
+
+  // this is formulated as an assumption such that the FPV testbenches do disprove this
+  // property by mistake
+  //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+% endif
+  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+
+% endif
+endmodule
+<%def name="str_bits_sv(bits)">\
+% if bits.msb != bits.lsb:
+${bits.msb}:${bits.lsb}\
+% else:
+${bits.msb}\
+% endif
+</%def>\
+<%def name="str_arr_sv(bits)">\
+% if bits.msb != bits.lsb:
+[${bits.msb-bits.lsb}:0] \
+% endif
+</%def>\
+<%def name="sig_gen(field, sig_name, hwext, shadowed)">\
+  % if field.swaccess.allows_read():
+  logic ${str_arr_sv(field.bits)}${sig_name}_qs;
+  % endif
+  % if field.swaccess.allows_write():
+  logic ${str_arr_sv(field.bits)}${sig_name}_wd;
+  logic ${sig_name}_we;
+  % endif
+  % if (field.swaccess.allows_read() and hwext) or shadowed:
+  logic ${sig_name}_re;
+  % endif
+</%def>\
+<%def name="finst_gen(field, finst_name, fsig_name, hwext, regwen, shadowed)">\
+  % if hwext:       ## if hwext, instantiate prim_subreg_ext
+  prim_subreg_ext #(
+    .DW    (${field.bits.width()})
+  ) u_${finst_name} (
+    % if field.swaccess.allows_read():
+    .re     (${finst_name}_re),
+    % else:
+    .re     (1'b0),
+    % endif
+    % if field.swaccess.allows_write():
+      % if regwen:
+    // qualified with register enable
+    .we     (${finst_name}_we & ${regwen.lower()}_qs),
+      % else:
+    .we     (${finst_name}_we),
+      % endif
+    .wd     (${finst_name}_wd),
+    % else:
+    .we     (1'b0),
+    .wd     ('0),
+    % endif
+    % if field.hwaccess.allows_write():
+    .d      (hw2reg.${fsig_name}.d),
+    % else:
+    .d      ('0),
+    % endif
+    % if field.hwre or shadowed:
+    .qre    (reg2hw.${fsig_name}.re),
+    % else:
+    .qre    (),
+    % endif
+    % if not field.hwaccess.allows_read():
+    .qe     (),
+    .q      (),
+    % else:
+      % if field.hwqe:
+    .qe     (reg2hw.${fsig_name}.qe),
+      % else:
+    .qe     (),
+      % endif
+    .q      (reg2hw.${fsig_name}.q ),
+    % endif
+    % if field.swaccess.allows_read():
+    .qs     (${finst_name}_qs)
+    % else:
+    .qs     ()
+    % endif
+  );
+  % else:       ## if not hwext, instantiate prim_subreg, prim_subreg_shadow or constant assign
+    % if ((not field.hwaccess.allows_read() and\
+           not field.hwaccess.allows_write() and\
+           field.swaccess.swrd() == SwRdAccess.RD and\
+           not field.swaccess.allows_write())):
+  // constant-only read
+  assign ${finst_name}_qs = ${field.bits.width()}'h${"%x" % (field.resval or 0)};
+    % else:     ## not hwext not constant
+      % if not shadowed:
+  prim_subreg #(
+      % else:
+  prim_subreg_shadow #(
+      % endif
+    .DW      (${field.bits.width()}),
+    .SWACCESS("${field.swaccess.value[1].name.upper()}"),
+    .RESVAL  (${field.bits.width()}'h${"%x" % (field.resval or 0)})
+  ) u_${finst_name} (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+      % if shadowed:
+    .re     (${finst_name}_re),
+      % endif
+      % if field.swaccess.allows_write(): ## non-RO types
+        % if regwen:
+    // from register interface (qualified with register enable)
+    .we     (${finst_name}_we & ${regwen.lower()}_qs),
+        % else:
+    // from register interface
+    .we     (${finst_name}_we),
+        % endif
+    .wd     (${finst_name}_wd),
+      % else:                             ## RO types
+    .we     (1'b0),
+    .wd     ('0  ),
+      % endif
+
+    // from internal hardware
+      % if field.hwaccess.allows_write():
+    .de     (hw2reg.${fsig_name}.de),
+    .d      (hw2reg.${fsig_name}.d ),
+      % else:
+    .de     (1'b0),
+    .d      ('0  ),
+      % endif
+
+    // to internal hardware
+      % if not field.hwaccess.allows_read():
+    .qe     (),
+    .q      (),
+      % else:
+        % if field.hwqe:
+    .qe     (reg2hw.${fsig_name}.qe),
+        % else:
+    .qe     (),
+        % endif
+    .q      (reg2hw.${fsig_name}.q ),
+      % endif
+
+      % if not shadowed:
+        % if field.swaccess.allows_read():
+    // to register interface (read)
+    .qs     (${finst_name}_qs)
+        % else:
+    .qs     ()
+        % endif
+      % else:
+        % if field.swaccess.allows_read():
+    // to register interface (read)
+    .qs     (${finst_name}_qs),
+        % else:
+    .qs     (),
+        % endif
+
+    // Shadow register error conditions
+    .err_update  (reg2hw.${fsig_name}.err_update ),
+    .err_storage (reg2hw.${fsig_name}.err_storage)
+      % endif
+  );
+    % endif  ## end non-constant prim_subreg
+  % endif
+</%def>\
+<%def name="we_gen(field, sig_name, hwext, shadowed, idx)">\
+<%
+    needs_we = field.swaccess.allows_write()
+    needs_re = (field.swaccess.allows_read() and hwext) or shadowed
+    space = '\n' if needs_we or needs_re else ''
+%>\
+${space}\
+% if needs_we:
+  % if field.swaccess.swrd() != SwRdAccess.RC:
+  assign ${sig_name}_we = addr_hit[${idx}] & reg_we & !reg_error;
+  assign ${sig_name}_wd = reg_wdata[${str_bits_sv(field.bits)}];
+  % else:
+  ## Generate WE based on read request, read should clear
+  assign ${sig_name}_we = addr_hit[${idx}] & reg_re & !reg_error;
+  assign ${sig_name}_wd = '1;
+  % endif
+% endif
+% if needs_re:
+  assign ${sig_name}_re = addr_hit[${idx}] & reg_re & !reg_error;
+% endif
+</%def>\
+<%def name="rdata_gen(field, sig_name)">\
+% if field.swaccess.allows_read():
+        reg_rdata_next[${str_bits_sv(field.bits)}] = ${sig_name}_qs;
+% else:
+        reg_rdata_next[${str_bits_sv(field.bits)}] = '0;
+% endif
+</%def>\
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/register.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/register.py
new file mode 100644
index 00000000..24f73d02
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/register.py
@@ -0,0 +1,375 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict, List, Optional
+
+from .access import SWAccess, HWAccess
+from .field import Field
+from .lib import (check_keys, check_str, check_name, check_bool,
+                  check_list, check_str_list, check_int)
+from .params import ReggenParams
+from .reg_base import RegBase
+
+REQUIRED_FIELDS = {
+    'name': ['s', "name of the register"],
+    'desc': ['t', "description of the register"],
+    'fields': ['l', "list of register field description groups"]
+}
+
+OPTIONAL_FIELDS = {
+    'swaccess': [
+        's',
+        "software access permission to use for "
+        "fields that don't specify swaccess"
+    ],
+    'hwaccess': [
+        's',
+        "hardware access permission to use for "
+        "fields that don't specify hwaccess"
+    ],
+    'hwext': [
+        's',
+        "'true' if the register is stored outside "
+        "of the register module"
+    ],
+    'hwqe': [
+        's',
+        "'true' if hardware uses 'q' enable signal, "
+        "which is latched signal of software write pulse."
+    ],
+    'hwre': [
+        's',
+        "'true' if hardware uses 're' signal, "
+        "which is latched signal of software read pulse."
+    ],
+    'regwen': [
+        's',
+        "if register is write-protected by another register, that "
+        "register name should be given here. empty-string for no register "
+        "write protection"
+    ],
+    'resval': [
+        'd',
+        "reset value of full register (default 0)"
+    ],
+    'tags': [
+        's',
+        "tags for the register, following the format 'tag_name:item1:item2...'"
+    ],
+    'shadowed': [
+        's',
+        "'true' if the register is shadowed"
+    ],
+    'update_err_alert': [
+        's',
+        "alert that will be triggered if "
+        "this shadowed register has update error"
+    ],
+    'storage_err_alert': [
+        's',
+        "alert that will be triggered if "
+        "this shadowed register has storage error"
+    ]
+}
+
+
+class Register(RegBase):
+    '''Code representing a register for reggen'''
+    def __init__(self,
+                 offset: int,
+                 name: str,
+                 desc: str,
+                 swaccess: SWAccess,
+                 hwaccess: HWAccess,
+                 hwext: bool,
+                 hwqe: bool,
+                 hwre: bool,
+                 regwen: Optional[str],
+                 tags: List[str],
+                 resval: Optional[int],
+                 shadowed: bool,
+                 fields: List[Field],
+                 update_err_alert: Optional[str],
+                 storage_err_alert: Optional[str]):
+        super().__init__(offset)
+        self.name = name
+        self.desc = desc
+
+        self.swaccess = swaccess
+        self.hwaccess = hwaccess
+
+        self.hwext = hwext
+        if self.hwext and self.hwaccess.key == 'hro' and self.sw_readable():
+            raise ValueError('hwext flag for {} register is set, but '
+                             'hwaccess is hro and the register value '
+                             'is readable by software mode ({}).'
+                             .format(self.name, self.swaccess.key))
+
+        self.hwqe = hwqe
+        if self.hwext and not self.hwqe and self.sw_writable():
+            raise ValueError('The {} register has hwext set and is writable '
+                             'by software (mode {}), so must also have hwqe '
+                             'enabled.'
+                             .format(self.name, self.swaccess.key))
+
+        self.hwre = hwre
+        if self.hwre and not self.hwext:
+            raise ValueError('The {} register specifies hwre but not hwext.'
+                             .format(self.name))
+
+        self.regwen = regwen
+        self.tags = tags
+
+        self.shadowed = shadowed
+        sounds_shadowy = self.name.lower().endswith('_shadowed')
+        if self.shadowed and not sounds_shadowy:
+            raise ValueError("Register {} has the shadowed flag but its name "
+                             "doesn't end with the _shadowed suffix."
+                             .format(self.name))
+        elif sounds_shadowy and not self.shadowed:
+            raise ValueError("Register {} has a name ending in _shadowed, but "
+                             "the shadowed flag is not set."
+                             .format(self.name))
+
+        # Take a copy of fields and then sort by bit index
+        assert fields
+        self.fields = fields.copy()
+        self.fields.sort(key=lambda field: field.bits.lsb)
+
+        # Index fields by name and check for duplicates
+        self.name_to_field = {}  # type: Dict[str, Field]
+        for field in self.fields:
+            if field.name in self.name_to_field:
+                raise ValueError('Register {} has duplicate fields called {}.'
+                                 .format(self.name, field.name))
+            self.name_to_field[field.name] = field
+
+        # Check that field bits are disjoint
+        bits_used = 0
+        for field in self.fields:
+            field_mask = field.bits.bitmask()
+            if bits_used & field_mask:
+                raise ValueError('Register {} has non-disjoint fields: '
+                                 '{} uses bits {:#x} used by other fields.'
+                                 .format(self.name, field.name,
+                                         bits_used & field_mask))
+
+        # Compute a reset value and mask from our constituent fields.
+        self.resval = 0
+        self.resmask = 0
+        for field in self.fields:
+            self.resval |= (field.resval or 0) << field.bits.lsb
+            self.resmask |= field.bits.bitmask()
+
+        # If the register defined a reset value, make sure it matches. We've
+        # already checked that each field matches, but we still need to make
+        # sure there weren't any bits unaccounted for.
+        if resval is not None and self.resval != resval:
+            raise ValueError('Register {} specifies a reset value of {:#x} but '
+                             'collecting reset values across its fields yields '
+                             '{:#x}.'
+                             .format(self.name, resval, self.resval))
+
+        self.update_err_alert = update_err_alert
+        self.storage_err_alert = storage_err_alert
+
+    @staticmethod
+    def from_raw(reg_width: int,
+                 offset: int,
+                 params: ReggenParams,
+                 raw: object) -> 'Register':
+        rd = check_keys(raw, 'register',
+                        list(REQUIRED_FIELDS.keys()),
+                        list(OPTIONAL_FIELDS.keys()))
+
+        name = check_name(rd['name'], 'name of register')
+        desc = check_str(rd['desc'], 'desc for {} register'.format(name))
+
+        swaccess = SWAccess('{} register'.format(name),
+                            rd.get('swaccess', 'none'))
+        hwaccess = HWAccess('{} register'.format(name),
+                            rd.get('hwaccess', 'hro'))
+
+        hwext = check_bool(rd.get('hwext', False),
+                           'hwext flag for {} register'.format(name))
+
+        hwqe = check_bool(rd.get('hwqe', False),
+                          'hwqe flag for {} register'.format(name))
+
+        hwre = check_bool(rd.get('hwre', False),
+                          'hwre flag for {} register'.format(name))
+
+        raw_regwen = rd.get('regwen', '')
+        if not raw_regwen:
+            regwen = None
+        else:
+            regwen = check_name(raw_regwen,
+                                'regwen for {} register'.format(name))
+
+        tags = check_str_list(rd.get('tags', []),
+                              'tags for {} register'.format(name))
+
+        raw_resval = rd.get('resval')
+        if raw_resval is None:
+            resval = None
+        else:
+            resval = check_int(raw_resval,
+                               'resval for {} register'.format(name))
+            if not 0 <= resval < (1 << reg_width):
+                raise ValueError('resval for {} register is {}, '
+                                 'not an unsigned {}-bit number.'
+                                 .format(name, resval, reg_width))
+
+        shadowed = check_bool(rd.get('shadowed', False),
+                              'shadowed flag for {} register'
+                              .format(name))
+
+        raw_fields = check_list(rd['fields'],
+                                'fields for {} register'.format(name))
+        if not raw_fields:
+            raise ValueError('Register {} has no fields.'.format(name))
+        fields = [Field.from_raw(name,
+                                 idx,
+                                 len(raw_fields),
+                                 swaccess,
+                                 hwaccess,
+                                 resval,
+                                 reg_width,
+                                 hwqe,
+                                 hwre,
+                                 params,
+                                 rf)
+                  for idx, rf in enumerate(raw_fields)]
+
+        raw_uea = rd.get('update_err_alert')
+        if raw_uea is None:
+            update_err_alert = None
+        else:
+            update_err_alert = check_name(raw_uea,
+                                          'update_err_alert for {} register'
+                                          .format(name))
+
+        raw_sea = rd.get('storage_err_alert')
+        if raw_sea is None:
+            storage_err_alert = None
+        else:
+            storage_err_alert = check_name(raw_sea,
+                                           'storage_err_alert for {} register'
+                                           .format(name))
+
+        return Register(offset, name, desc, swaccess, hwaccess,
+                        hwext, hwqe, hwre, regwen,
+                        tags, resval, shadowed, fields,
+                        update_err_alert, storage_err_alert)
+
+    def next_offset(self, addrsep: int) -> int:
+        return self.offset + addrsep
+
+    def sw_readable(self) -> bool:
+        return self.swaccess.key not in ['wo', 'r0w1c']
+
+    def sw_writable(self) -> bool:
+        return self.swaccess.key != 'ro'
+
+    def dv_rights(self) -> str:
+        return self.swaccess.dv_rights()
+
+    def get_n_bits(self, bittype: List[str]) -> int:
+        return sum(field.get_n_bits(self.hwext, bittype)
+                   for field in self.fields)
+
+    def get_field_list(self) -> List[Field]:
+        return self.fields
+
+    def is_homogeneous(self) -> bool:
+        return len(self.fields) == 1
+
+    def get_width(self) -> int:
+        '''Get the width of the fields in the register in bits
+
+        This counts dead space between and below fields, so it's calculated as
+        one more than the highest msb.
+
+        '''
+        # self.fields is ordered by (increasing) LSB, so we can find the MSB of
+        # the register by taking the MSB of the last field.
+        return 1 + self.fields[-1].bits.msb
+
+    def make_multi(self,
+                   reg_width: int,
+                   offset: int,
+                   creg_idx: int,
+                   creg_count: int,
+                   regwen_multi: bool,
+                   compact: bool,
+                   min_reg_idx: int,
+                   max_reg_idx: int,
+                   cname: str) -> 'Register':
+        '''Generate a numbered, packed version of the register'''
+        assert 0 <= creg_idx < creg_count
+        assert 0 <= min_reg_idx <= max_reg_idx
+        assert compact or (min_reg_idx == max_reg_idx)
+
+        new_name = ('{}_{}'.format(self.name, creg_idx)
+                    if creg_count > 1
+                    else self.name)
+
+        if self.regwen is None or not regwen_multi or creg_count == 1:
+            new_regwen = self.regwen
+        else:
+            new_regwen = '{}_{}'.format(self.regwen, creg_idx)
+
+        strip_field = creg_idx > 0
+
+        if compact:
+            # Compacting multiple registers into a single "compacted" register.
+            # This is only supported if we have exactly one field (checked at
+            # the call-site)
+            assert len(self.fields) == 1
+            new_fields = self.fields[0].make_multi(reg_width,
+                                                   min_reg_idx, max_reg_idx,
+                                                   cname, creg_idx,
+                                                   strip_field)
+        else:
+            # No compacting going on, but we still choose to rename the fields
+            # to match the registers
+            assert creg_idx == min_reg_idx
+            new_fields = [field.make_suffixed('_{}'.format(creg_idx),
+                                              cname, creg_idx, strip_field)
+                          for field in self.fields]
+
+        # Don't specify a reset value for the new register. Any reset value
+        # defined for the original register will have propagated to its fields,
+        # so when we combine them here, the Register constructor can compute a
+        # reset value for us (which might well be different from self.resval if
+        # we've replicated fields).
+        new_resval = None
+
+        return Register(offset, new_name, self.desc,
+                        self.swaccess, self.hwaccess,
+                        self.hwext, self.hwqe, self.hwre, new_regwen,
+                        self.tags, new_resval, self.shadowed, new_fields,
+                        self.update_err_alert, self.storage_err_alert)
+
+    def _asdict(self) -> Dict[str, object]:
+        rd = {
+            'name': self.name,
+            'desc': self.desc,
+            'fields': self.fields,
+            'swaccess': self.swaccess.key,
+            'hwaccess': self.hwaccess.key,
+            'hwext': str(self.hwext),
+            'hwqe': str(self.hwqe),
+            'hwre': str(self.hwre),
+            'tags': self.tags,
+            'shadowed': str(self.shadowed),
+        }
+        if self.regwen is not None:
+            rd['regwen'] = self.regwen
+        if self.update_err_alert is not None:
+            rd['update_err_alert'] = self.update_err_alert
+        if self.storage_err_alert is not None:
+            rd['storage_err_alert'] = self.storage_err_alert
+
+        return rd
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/signal.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/signal.py
new file mode 100644
index 00000000..bd4d6a33
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/signal.py
@@ -0,0 +1,63 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict, Sequence
+
+from .bits import Bits
+from .lib import check_keys, check_name, check_str, check_int, check_list
+
+
+class Signal:
+    def __init__(self, name: str, desc: str, bits: Bits):
+        self.name = name
+        self.desc = desc
+        self.bits = bits
+
+    @staticmethod
+    def from_raw(what: str, lsb: int, raw: object) -> 'Signal':
+        rd = check_keys(raw, what,
+                        ['name', 'desc'],
+                        ['width'])
+
+        name = check_name(rd['name'], 'name field of ' + what)
+        desc = check_str(rd['desc'], 'desc field of ' + what)
+        width = check_int(rd.get('width', 1), 'width field of ' + what)
+        if width <= 0:
+            raise ValueError('The width field of signal {} ({}) '
+                             'has value {}, but should be positive.'
+                             .format(name, what, width))
+
+        bits = Bits(lsb + width - 1, lsb)
+
+        return Signal(name, desc, bits)
+
+    @staticmethod
+    def from_raw_list(what: str, raw: object) -> Sequence['Signal']:
+        lsb = 0
+        ret = []
+        for idx, entry in enumerate(check_list(raw, what)):
+            entry_what = 'entry {} of {}'.format(idx, what)
+            interrupt = Signal.from_raw(entry_what, lsb, entry)
+            ret.append(interrupt)
+            lsb += interrupt.bits.width()
+        return ret
+
+    def _asdict(self) -> Dict[str, object]:
+        return {
+            'name': self.name,
+            'desc': self.desc,
+            'width': str(self.bits.width())
+        }
+
+    def as_nwt_dict(self, type_field: str) -> Dict[str, object]:
+        '''Return a view of the signal as a dictionary
+
+        The dictionary has fields "name", "width" and "type", the last
+        of which comes from the type_field argument. Used for topgen
+        integration.
+
+        '''
+        return {'name': self.name,
+                'width': self.bits.width(),
+                'type': type_field}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg.sv.tpl
new file mode 100644
index 00000000..9d8d9dc7
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg.sv.tpl
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// UVM Registers auto-generated by `reggen` containing data structure
+##
+##
+## We use functions from uvm_reg_base.sv.tpl to define
+## per-device-interface code.
+##
+<%namespace file="uvm_reg_base.sv.tpl" import="*"/>\
+##
+##
+${make_ral_pkg(dv_base_prefix, block.regwidth, reg_block_path, rb, esc_if_name)}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg_base.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg_base.sv.tpl
new file mode 100644
index 00000000..d1da4f4f
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/uvm_reg_base.sv.tpl
@@ -0,0 +1,431 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+<%!
+  from reggen import gen_dv
+  from reggen.access import HwAccess, SwRdAccess, SwWrAccess
+%>
+##
+##
+## make_ral_pkg
+## ============
+##
+## Generate the RAL package for a device interface.
+##
+##    dv_base_prefix   a string naming the base register type. If it is FOO,
+##                     then we will inherit from FOO_reg (assumed to
+##                     be a subclass of uvm_reg).
+##
+##    reg_width        an integer giving the width of registers in bits
+##
+##    reg_block_path   the hierarchical path to the relevant register block in the
+##                     design
+##
+##    rb               a RegBlock object
+##
+##    esc_if_name      a string giving the full, escaped, interface name. For
+##                     a device interface called FOO on block BAR,
+##                     this will be bar__foo. For an unnamed interface
+##                     on block BAR, this will be just bar.
+##
+<%def name="make_ral_pkg(dv_base_prefix, reg_width, reg_block_path, rb, esc_if_name)">\
+package ${esc_if_name}_ral_pkg;
+${make_ral_pkg_hdr(dv_base_prefix, [])}
+
+${make_ral_pkg_fwd_decls(esc_if_name, rb.flat_regs, rb.windows)}
+% for reg in rb.flat_regs:
+
+${make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, reg_block_path, reg)}
+% endfor
+% for window in rb.windows:
+
+${make_ral_pkg_window_class(dv_base_prefix, esc_if_name, window)}
+% endfor
+
+<%
+  reg_block_name = gen_dv.bcname(esc_if_name)
+%>\
+  class ${reg_block_name} extends ${dv_base_prefix}_reg_block;
+% if rb.flat_regs:
+    // registers
+%   for r in rb.flat_regs:
+    rand ${gen_dv.rcname(esc_if_name, r)} ${r.name.lower()};
+%   endfor
+% endif
+% if rb.windows:
+    // memories
+% for window in rb.windows:
+    rand ${gen_dv.mcname(esc_if_name, window)} ${gen_dv.miname(window)};
+% endfor
+% endif
+
+    `uvm_object_utils(${reg_block_name})
+
+    function new(string name = "${reg_block_name}",
+                 int    has_coverage = UVM_NO_COVERAGE);
+      super.new(name, has_coverage);
+    endfunction : new
+
+    virtual function void build(uvm_reg_addr_t base_addr,
+                                csr_excl_item csr_excl = null);
+      // create default map
+      this.default_map = create_map(.name("default_map"),
+                                    .base_addr(base_addr),
+                                    .n_bytes(${reg_width//8}),
+                                    .endian(UVM_LITTLE_ENDIAN));
+      if (csr_excl == null) begin
+        csr_excl = csr_excl_item::type_id::create("csr_excl");
+        this.csr_excl = csr_excl;
+      end
+% if rb.flat_regs:
+      set_hdl_path_root("tb.dut", "BkdrRegPathRtl");
+      set_hdl_path_root("tb.dut", "BkdrRegPathRtlCommitted");
+      set_hdl_path_root("tb.dut", "BkdrRegPathRtlShadow");
+      // create registers
+%   for r in rb.flat_regs:
+<%
+      reg_name = r.name.lower()
+      reg_right = r.dv_rights()
+      reg_offset = "{}'h{:x}".format(reg_width, r.offset)
+      reg_tags = r.tags
+      reg_shadowed = r.shadowed
+
+      type_id_indent = ' ' * (len(reg_name) + 4)
+%>\
+      ${reg_name} = (${gen_dv.rcname(esc_if_name, r)}::
+      ${type_id_indent}type_id::create("${reg_name}"));
+      ${reg_name}.configure(.blk_parent(this));
+      ${reg_name}.build(csr_excl);
+      default_map.add_reg(.rg(${reg_name}),
+                          .offset(${reg_offset}),
+                          .rights("${reg_right}"));
+%     if reg_shadowed:
+      ${reg_name}.set_is_shadowed();
+%     endif
+%     if reg_tags:
+      // create register tags
+%       for reg_tag in reg_tags:
+<%
+        tag = reg_tag.split(":")
+%>\
+%         if tag[0] == "excl":
+      csr_excl.add_excl(${reg_name}.get_full_name(), ${tag[2]}, ${tag[1]});
+%         endif
+%       endfor
+%     endif
+%   endfor
+<%
+  any_regwen = False
+  for r in rb.flat_regs:
+    if r.regwen:
+      any_regwen = True
+      break
+%>\
+% if any_regwen:
+      // assign locked reg to its regwen reg
+%     for r in rb.flat_regs:
+%       if r.regwen:
+%         for reg in rb.flat_regs:
+%           if r.regwen.lower() == reg.name.lower():
+      ${r.regwen.lower()}.add_lockable_reg_or_fld(${r.name.lower()});
+<% break %>\
+%           elif reg.name.lower() in r.regwen.lower():
+%             for field in reg.get_field_list():
+%               if r.regwen.lower() == (reg.name.lower() + "_" + field.name.lower()):
+      ${r.regwen.lower()}.${field.name.lower()}.add_lockable_reg_or_fld(${r.name.lower()});
+<% break %>\
+%               endif
+%             endfor
+%           endif
+%         endfor
+%       endif
+%     endfor
+%   endif
+% endif
+${make_ral_pkg_window_instances(reg_width, esc_if_name, rb)}
+    endfunction : build
+  endclass : ${reg_block_name}
+
+endpackage
+</%def>\
+##
+##
+## make_ral_pkg_hdr
+## ================
+##
+## Generate the header for a RAL package
+##
+##    dv_base_prefix   as for make_ral_pkg
+##
+##    deps             a list of names for packages that should be explicitly
+##                     imported
+##
+<%def name="make_ral_pkg_hdr(dv_base_prefix, deps)">\
+  // dep packages
+  import uvm_pkg::*;
+  import dv_base_reg_pkg::*;
+% if dv_base_prefix != "dv_base":
+  import ${dv_base_prefix}_reg_pkg::*;
+% endif
+% for dep in deps:
+  import ${dep}::*;
+% endfor
+
+  // macro includes
+  `include "uvm_macros.svh"\
+</%def>\
+##
+##
+## make_ral_pkg_fwd_decls
+## ======================
+##
+## Generate the forward declarations for a RAL package
+##
+##    esc_if_name      as for make_ral_pkg
+##
+##    flat_regs        a list of Register objects (expanding multiregs)
+##
+##    windows          a list of Window objects
+##
+<%def name="make_ral_pkg_fwd_decls(esc_if_name, flat_regs, windows)">\
+  // Forward declare all register/memory/block classes
+% for r in flat_regs:
+  typedef class ${gen_dv.rcname(esc_if_name, r)};
+% endfor
+% for w in windows:
+  typedef class ${gen_dv.mcname(esc_if_name, w)};
+% endfor
+  typedef class ${gen_dv.bcname(esc_if_name)};\
+</%def>\
+##
+##
+## make_ral_pkg_reg_class
+## ======================
+##
+## Generate the classes for a register inside a RAL package
+##
+##    dv_base_prefix   as for make_ral_pkg
+##
+##    reg_width        as for make_ral_pkg
+##
+##    esc_if_name      as for make_ral_pkg
+##
+##    reg_block_path   as for make_ral_pkg
+##
+##    reg              a Register object
+<%def name="make_ral_pkg_reg_class(dv_base_prefix, reg_width, esc_if_name, reg_block_path, reg)">\
+<%
+  reg_name = reg.name.lower()
+
+  is_ext = reg.hwext
+  for field in reg.fields:
+    if (field.hwaccess.value[1] == HwAccess.NONE and
+        field.swaccess.swrd() == SwRdAccess.RD and
+        not field.swaccess.allows_write()):
+      is_ext = 1
+
+  class_name = gen_dv.rcname(esc_if_name, reg)
+%>\
+  class ${class_name} extends ${dv_base_prefix}_reg;
+    // fields
+% for f in reg.fields:
+    rand ${dv_base_prefix}_reg_field ${f.name.lower()};
+% endfor
+
+    `uvm_object_utils(${class_name})
+
+    function new(string       name = "${class_name}",
+                 int unsigned n_bits = ${reg_width},
+                 int          has_coverage = UVM_NO_COVERAGE);
+      super.new(name, n_bits, has_coverage);
+    endfunction : new
+
+    virtual function void build(csr_excl_item csr_excl = null);
+      // create fields
+% for field in reg.fields:
+<%
+    if len(reg.fields) == 1:
+      reg_field_name = reg_name
+    else:
+      reg_field_name = reg_name + "_" + field.name.lower()
+%>\
+${_create_reg_field(dv_base_prefix, reg_width, reg_block_path, reg.shadowed, reg.hwext, reg_field_name, field)}
+% endfor
+% if reg.shadowed and reg.hwext:
+<%
+    shadowed_reg_path = ''
+    for tag in reg.tags:
+      parts = tag.split(':')
+      if parts[0] == 'shadowed_reg_path':
+        shadowed_reg_path = parts[1]
+
+    if not shadowed_reg_path:
+      print("ERROR: ext shadow_reg does not have tags for shadowed_reg_path!")
+      assert 0
+
+    bit_idx = reg.fields[-1].bits.msb + 1
+
+%>\
+      add_update_err_alert("${reg.update_err_alert}");
+      add_storage_err_alert("${reg.storage_err_alert}");
+      add_hdl_path_slice("${shadowed_reg_path}.committed_reg.q",
+                         0, ${bit_idx}, 0, "BkdrRegPathRtlCommitted");
+      add_hdl_path_slice("${shadowed_reg_path}.shadow_reg.q",
+                         0, ${bit_idx}, 0, "BkdrRegPathRtlShadow");
+% endif
+% if is_ext:
+      set_is_ext_reg(1);
+% endif
+    endfunction : build
+  endclass : ${class_name}\
+</%def>\
+##
+##
+## _create_reg_field
+## =================
+##
+## Generate the code that creates a uvm_reg_field object for a field
+## in a register.
+##
+##    dv_base_prefix   as for make_ral_pkg
+##
+##    reg_width        as for make_ral_pkg
+##
+##    reg_block_path   as for make_ral_pkg
+##
+##    shadowed         true if the field's register is shadowed
+##
+##    hwext            true if the field's register is hwext
+##
+##    reg_field_name   a string with the name to give the field in the HDL
+##
+##    field            a Field object
+<%def name="_create_reg_field(dv_base_prefix, reg_width, reg_block_path, shadowed, hwext, reg_field_name, field)">\
+<%
+  field_size = field.bits.width()
+  if field.swaccess.key == "r0w1c":
+    field_access = "W1C"
+  else:
+    field_access = field.swaccess.value[1].name
+
+  if not field.hwaccess.allows_write():
+    field_volatile = 0
+  else:
+    field_volatile = 1
+  field_tags = field.tags
+
+  fname = field.name.lower()
+  type_id_indent = ' ' * (len(fname) + 4)
+%>\
+      ${fname} = (${dv_base_prefix}_reg_field::
+      ${type_id_indent}type_id::create("${fname}"));
+      ${fname}.configure(
+        .parent(this),
+        .size(${field_size}),
+        .lsb_pos(${field.bits.lsb}),
+        .access("${field_access}"),
+        .volatile(${field_volatile}),
+        .reset(${reg_width}'h${format(field.resval or 0, 'x')}),
+        .has_reset(1),
+        .is_rand(1),
+        .individually_accessible(1));
+      ${fname}.set_original_access("${field_access}");
+% if ((field.hwaccess.value[1] == HwAccess.NONE and\
+       field.swaccess.swrd() == SwRdAccess.RD and\
+       not field.swaccess.allows_write())):
+      // constant reg
+      add_hdl_path_slice("${reg_block_path}.${reg_field_name}_qs",
+                         ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl");
+% else:
+      add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.q${"s" if hwext else ""}",
+                         ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtl");
+% endif
+% if shadowed and not hwext:
+      add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.committed_reg.q",
+                         ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlCommitted");
+      add_hdl_path_slice("${reg_block_path}.u_${reg_field_name}.shadow_reg.q",
+                         ${field.bits.lsb}, ${field_size}, 0, "BkdrRegPathRtlShadow");
+% endif
+% if field_tags:
+      // create field tags
+%     for field_tag in field_tags:
+<%
+  tag = field_tag.split(":")
+%>\
+%       if tag[0] == "excl":
+      csr_excl.add_excl(${field.name.lower()}.get_full_name(), ${tag[2]}, ${tag[1]});
+%       endif
+%     endfor
+%   endif
+</%def>\
+##
+##
+## make_ral_pkg_window_class
+## =========================
+##
+## Generate the classes for a window inside a RAL package
+##
+##    dv_base_prefix   as for make_ral_pkg
+##
+##    esc_if_name      as for make_ral_pkg
+##
+##    window           a Window object
+<%def name="make_ral_pkg_window_class(dv_base_prefix, esc_if_name, window)">\
+<%
+  mem_name = window.name.lower()
+  mem_right = window.swaccess.dv_rights()
+  mem_n_bits = window.validbits
+  mem_size = window.items
+
+  class_name = gen_dv.mcname(esc_if_name, window)
+%>\
+  class ${class_name} extends ${dv_base_prefix}_mem;
+
+    `uvm_object_utils(${class_name})
+
+    function new(string           name = "${class_name}",
+                 longint unsigned size = ${mem_size},
+                 int unsigned     n_bits = ${mem_n_bits},
+                 string           access = "${mem_right}",
+                 int              has_coverage = UVM_NO_COVERAGE);
+      super.new(name, size, n_bits, access, has_coverage);
+%     if window.byte_write:
+      set_mem_partial_write_support(1);
+%     endif
+    endfunction : new
+
+  endclass : ${class_name}
+</%def>\
+##
+##
+## make_ral_pkg_window_instances
+## =============================
+##
+## Generate the classes for a window inside a RAL package
+##
+##    reg_width        as for make_ral_pkg
+##
+##    esc_if_name      as for make_ral_pkg
+##
+##    rb               a RegBlock object
+##
+<%def name="make_ral_pkg_window_instances(reg_width, esc_if_name, rb)">\
+% if rb.windows:
+
+      // create memories
+%  for w in rb.windows:
+<%
+      mem_name = w.name.lower()
+      mem_right = w.swaccess.dv_rights()
+      mem_offset = "{}'h{:x}".format(reg_width, w.offset)
+      mem_n_bits = w.validbits
+      mem_size = w.items
+%>\
+      ${mem_name} = ${gen_dv.mcname(esc_if_name, w)}::type_id::create("${mem_name}");
+      ${mem_name}.configure(.parent(this));
+      default_map.add_mem(.mem(${mem_name}),
+                          .offset(${mem_offset}),
+                          .rights("${mem_right}"));
+%   endfor
+% endif
+</%def>\
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/validate.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/validate.py
new file mode 100644
index 00000000..e1cea7fa
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/validate.py
@@ -0,0 +1,155 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""
+Register JSON validation
+"""
+
+import logging as log
+
+
+# validating version of int(x, 0)
+# returns int value, error flag
+# if error flag is True value will be zero
+def check_int(x, err_prefix, suppress_err_msg=False):
+    if isinstance(x, int):
+        return x, False
+    if x[0] == '0' and len(x) > 2:
+        if x[1] in 'bB':
+            validch = '01'
+        elif x[1] in 'oO':
+            validch = '01234567'
+        elif x[1] in 'xX':
+            validch = '0123456789abcdefABCDEF'
+        else:
+            if not suppress_err_msg:
+                log.error(err_prefix +
+                          ": int must start digit, 0b, 0B, 0o, 0O, 0x or 0X")
+            return 0, True
+        for c in x[2:]:
+            if c not in validch:
+                if not suppress_err_msg:
+                    log.error(err_prefix + ": Bad character " + c + " in " + x)
+                return 0, True
+    else:
+        if not x.isdecimal():
+            if not suppress_err_msg:
+                log.error(err_prefix + ": Number not valid int " + x)
+            return 0, True
+    return int(x, 0), False
+
+
+def check_bool(x, err_prefix):
+    """check_bool checks if input 'x' is one of the list:
+        "true", "false"
+
+        It returns value as Bool type and Error condition.
+    """
+    if isinstance(x, bool):
+        # if Bool returns as it is
+        return x, False
+    if not x.lower() in ["true", "false"]:
+        log.error(err_prefix + ": Bad field value " + x)
+        return False, True
+    else:
+        return (x.lower() == "true"), False
+
+
+def check_ln(obj, x, withwidth, err_prefix):
+    error = 0
+    if not isinstance(obj[x], list):
+        log.error(err_prefix + ' element ' + x + ' not a list')
+        return 1
+    for y in obj[x]:
+        error += check_keys(y, ln_required, ln_optional if withwidth else {},
+                            {}, err_prefix + ' element ' + x)
+        if withwidth:
+            if 'width' in y:
+                w, err = check_int(y['width'], err_prefix + ' width in ' + x)
+                if err:
+                    error += 1
+                    w = 1
+            else:
+                w = 1
+            y['width'] = str(w)
+
+    return error
+
+
+def check_keys(obj, required_keys, optional_keys, added_keys, err_prefix):
+    error = 0
+    for x in required_keys:
+        if x not in obj:
+            error += 1
+            log.error(err_prefix + " missing required key " + x)
+    for x in obj:
+        type = None
+        if x in required_keys:
+            type = required_keys[x][0]
+        elif x in optional_keys:
+            type = optional_keys[x][0]
+        elif x not in added_keys:
+            log.warning(err_prefix + " contains extra key " + x)
+        if type is not None:
+            if type[:2] == 'ln':
+                error += check_ln(obj, x, type == 'lnw', err_prefix)
+
+    return error
+
+
+val_types = {
+    'd': ["int", "integer (binary 0b, octal 0o, decimal, hex 0x)"],
+    'x': ["xint", "x for undefined otherwise int"],
+    'b': [
+        "bitrange", "bit number as decimal integer, "
+        "or bit-range as decimal integers msb:lsb"
+    ],
+    'l': ["list", "comma separated list enclosed in `[]`"],
+    'ln': [
+        "name list", 'comma separated list enclosed in `[]` of '
+        'one or more groups that have just name and dscr keys.'
+        ' e.g. `{ name: "name", desc: "description"}`'
+    ],
+    'lnw': ["name list+", 'name list that optionally contains a width'],
+    'lp': ["parameter list", 'parameter list having default value optionally'],
+    'g': ["group", "comma separated group of key:value enclosed in `{}`"],
+    'lg': [
+        "list of group", "comma separated group of key:value enclosed in `{}`"
+        " the second entry of the list is the sub group format"
+    ],
+    's': ["string", "string, typically short"],
+    't': [
+        "text", "string, may be multi-line enclosed in `'''` "
+        "may use `**bold**`, `*italic*` or `!!Reg` markup"
+    ],
+    'T': ["tuple", "tuple enclosed in ()"],
+    'pi': ["python int", "Native Python type int (generated)"],
+    'pb': ["python Bool", "Native Python type Bool (generated)"],
+    'pl': ["python list", "Native Python type list (generated)"],
+    'pe': ["python enum", "Native Python type enum (generated)"]
+}
+
+# ln type has list of groups with only name and description
+# (was called "subunit" in cfg_validate)
+ln_required = {
+    'name': ['s', "name of the item"],
+    'desc': ['s', "description of the item"],
+}
+ln_optional = {
+    'width': ['d', "bit width of the item (if not 1)"],
+}
+
+# Registers list may have embedded keys
+list_optone = {
+    'reserved': ['d', "number of registers to reserve space for"],
+    'skipto': ['d', "set next register offset to value"],
+    'window': [
+        'g', "group defining an address range "
+        "for something other than standard registers"
+    ],
+    'multireg':
+    ['g', "group defining registers generated "
+     "from a base instance."]
+}
+
+key_use = {'r': "required", 'o': "optional", 'a': "added by tool"}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/version.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/version.py
new file mode 100644
index 00000000..3539c460
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/version.py
@@ -0,0 +1,24 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+r"""Standard version printing
+"""
+import os
+import subprocess
+import sys
+
+import pkg_resources  # part of setuptools
+
+
+def show_and_exit(clitool, packages):
+    util_path = os.path.dirname(os.path.realpath(clitool))
+    os.chdir(util_path)
+    ver = subprocess.run(
+        ["git", "describe", "--always", "--dirty", "--broken"],
+        stdout=subprocess.PIPE).stdout.strip().decode('ascii')
+    if (ver == ''):
+        ver = 'not found (not in Git repository?)'
+    sys.stderr.write(clitool + " Git version " + ver + '\n')
+    for p in packages:
+        sys.stderr.write(p + ' ' + pkg_resources.require(p)[0].version + '\n')
+    exit(0)
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/window.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/window.py
new file mode 100644
index 00000000..d4355c88
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/reggen/window.py
@@ -0,0 +1,169 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from typing import Dict
+
+from .access import SWAccess
+from .lib import check_keys, check_str, check_bool, check_int
+from .params import ReggenParams
+
+
+REQUIRED_FIELDS = {
+    'name': ['s', "name of the window"],
+    'desc': ['t', "description of the window"],
+    'items': ['d', "size in fieldaccess width words of the window"],
+    'swaccess': ['s', "software access permitted"],
+}
+
+# TODO potential for additional optional to give more type info?
+# eg sram-hw-port: "none", "sync", "async"
+OPTIONAL_FIELDS = {
+    'data-intg-passthru': [
+        's', "True if the window has data integrity pass through. "
+        "Defaults to false if not present."
+    ],
+    'byte-write': [
+        's', "True if byte writes are supported. "
+        "Defaults to false if not present."
+    ],
+    'validbits': [
+        'd', "Number of valid data bits within "
+        "regwidth sized word. "
+        "Defaults to regwidth. If "
+        "smaller than the regwidth then in each "
+        "word of the window bits "
+        "[regwidth-1:validbits] are unused and "
+        "bits [validbits-1:0] are valid."
+    ],
+    'unusual': [
+        's', "True if window has unusual parameters "
+        "(set to prevent Unusual: errors)."
+        "Defaults to false if not present."
+    ]
+}
+
+
+class Window:
+    '''A class representing a memory window'''
+    def __init__(self,
+                 name: str,
+                 desc: str,
+                 unusual: bool,
+                 byte_write: bool,
+                 data_intg_passthru: bool,
+                 validbits: int,
+                 items: int,
+                 size_in_bytes: int,
+                 offset: int,
+                 swaccess: SWAccess):
+        assert 0 < validbits
+        assert 0 < items <= size_in_bytes
+
+        self.name = name
+        self.desc = desc
+        self.unusual = unusual
+        self.byte_write = byte_write
+        self.data_intg_passthru = data_intg_passthru
+        self.validbits = validbits
+        self.items = items
+        self.size_in_bytes = size_in_bytes
+        self.offset = offset
+        self.swaccess = swaccess
+
+        # Check that offset has been adjusted so that the first item in the
+        # window has all zeros in the low bits.
+        po2_size = 1 << (self.size_in_bytes - 1).bit_length()
+        assert not (offset & (po2_size - 1))
+
+    @staticmethod
+    def from_raw(offset: int,
+                 reg_width: int,
+                 params: ReggenParams,
+                 raw: object) -> 'Window':
+        rd = check_keys(raw, 'window',
+                        list(REQUIRED_FIELDS.keys()),
+                        list(OPTIONAL_FIELDS.keys()))
+
+        wind_desc = 'window at offset {:#x}'.format(offset)
+        name = check_str(rd['name'], wind_desc)
+        wind_desc = '{!r} {}'.format(name, wind_desc)
+
+        desc = check_str(rd['desc'], 'desc field for ' + wind_desc)
+
+        unusual = check_bool(rd.get('unusual', False),
+                             'unusual field for ' + wind_desc)
+        byte_write = check_bool(rd.get('byte-write', False),
+                                'byte-write field for ' + wind_desc)
+        data_intg_passthru = check_bool(rd.get('data-intg-passthru', False),
+                                        'data-intg-passthru field for ' + wind_desc)
+
+        validbits = check_int(rd.get('validbits', reg_width),
+                              'validbits field for ' + wind_desc)
+        if validbits <= 0:
+            raise ValueError('validbits field for {} is not positive.'
+                             .format(wind_desc))
+        if validbits > reg_width:
+            raise ValueError('validbits field for {} is {}, '
+                             'which is greater than {}, the register width.'
+                             .format(wind_desc, validbits, reg_width))
+
+        r_items = check_str(rd['items'], 'items field for ' + wind_desc)
+        items = params.expand(r_items, 'items field for ' + wind_desc)
+        if items <= 0:
+            raise ValueError("Items field for {} is {}, "
+                             "which isn't positive."
+                             .format(wind_desc, items))
+
+        assert reg_width % 8 == 0
+        size_in_bytes = items * (reg_width // 8)
+
+        # Round size_in_bytes up to the next power of 2. The calculation is
+        # like clog2 calculations in SystemVerilog, where we start with the
+        # last index, rather than the number of elements.
+        assert size_in_bytes > 0
+        po2_size = 1 << (size_in_bytes - 1).bit_length()
+
+        # A size that isn't a power of 2 is not allowed unless the unusual flag
+        # is set.
+        if po2_size != size_in_bytes and not unusual:
+            raise ValueError('Items field for {} is {}, which gives a size of '
+                             '{} bytes. This is not a power of 2 (next power '
+                             'of 2 is {}). If you want to do this even so, '
+                             'set the "unusual" flag.'
+                             .format(wind_desc, items,
+                                     size_in_bytes, po2_size))
+
+        # Adjust offset if necessary to make sure the base address of the first
+        # item in the window has all zeros in the low bits.
+        addr_mask = po2_size - 1
+        if offset & addr_mask:
+            offset = (offset | addr_mask) + 1
+        offset = offset
+
+        swaccess = SWAccess(wind_desc, rd['swaccess'])
+        if not (swaccess.value[4] or unusual):
+            raise ValueError('swaccess field for {} is {}, which is an '
+                             'unusual access type for a window. If you want '
+                             'to do this, set the "unusual" flag.'
+                             .format(wind_desc, swaccess.key))
+
+        return Window(name, desc, unusual, byte_write, data_intg_passthru,
+                      validbits, items, size_in_bytes, offset, swaccess)
+
+    def next_offset(self, addrsep: int) -> int:
+        return self.offset + self.size_in_bytes
+
+    def _asdict(self) -> Dict[str, object]:
+        rd = {
+            'desc': self.desc,
+            'items': self.items,
+            'swaccess': self.swaccess.key,
+            'byte-write': self.byte_write,
+            'validbits': self.validbits,
+            'unusual': self.unusual
+        }
+        if self.name is not None:
+            rd['name'] = self.name
+
+        return {'window': rd}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/regtool.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/regtool.py
new file mode 100644
index 00000000..f1501bd0
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/regtool.py
@@ -0,0 +1,235 @@
+#!/usr/bin/env python3
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""Command-line tool to validate and convert register hjson
+
+"""
+import argparse
+import logging as log
+import re
+import sys
+from pathlib import PurePath
+
+from reggen import (gen_cheader, gen_dv, gen_fpv, gen_html,
+                    gen_json, gen_rtl, gen_selfdoc, version)
+from reggen.ip_block import IpBlock
+
+DESC = """regtool, generate register info from Hjson source"""
+
+USAGE = '''
+  regtool [options]
+  regtool [options] <input>
+  regtool (-h | --help)
+  regtool (-V | --version)
+'''
+
+
+def main():
+    verbose = 0
+
+    parser = argparse.ArgumentParser(
+        prog="regtool",
+        formatter_class=argparse.RawDescriptionHelpFormatter,
+        usage=USAGE,
+        description=DESC)
+    parser.add_argument('input',
+                        nargs='?',
+                        metavar='file',
+                        type=argparse.FileType('r'),
+                        default=sys.stdin,
+                        help='input file in Hjson type')
+    parser.add_argument('-d',
+                        action='store_true',
+                        help='Output register documentation (html)')
+    parser.add_argument('--cdefines',
+                        '-D',
+                        action='store_true',
+                        help='Output C defines header')
+    parser.add_argument('--doc',
+                        action='store_true',
+                        help='Output source file documentation (gfm)')
+    parser.add_argument('-j',
+                        action='store_true',
+                        help='Output as formatted JSON')
+    parser.add_argument('-c', action='store_true', help='Output as JSON')
+    parser.add_argument('-r',
+                        action='store_true',
+                        help='Output as SystemVerilog RTL')
+    parser.add_argument('-s',
+                        action='store_true',
+                        help='Output as UVM Register class')
+    parser.add_argument('-f',
+                        action='store_true',
+                        help='Output as FPV CSR rw assertion module')
+    parser.add_argument('--outdir',
+                        '-t',
+                        help='Target directory for generated RTL; '
+                        'tool uses ../rtl if blank.')
+    parser.add_argument('--dv-base-prefix',
+                        default='dv_base',
+                        help='Prefix for the DV register classes from which '
+                        'the register models are derived.')
+    parser.add_argument('--outfile',
+                        '-o',
+                        type=argparse.FileType('w'),
+                        default=sys.stdout,
+                        help='Target filename for json, html, gfm.')
+    parser.add_argument('--verbose',
+                        '-v',
+                        action='store_true',
+                        help='Verbose and run validate twice')
+    parser.add_argument('--param',
+                        '-p',
+                        type=str,
+                        default="",
+                        help='''Change the Parameter values.
+                                Only integer value is supported.
+                                You can add multiple param arguments.
+
+                                  Format: ParamA=ValA;ParamB=ValB
+                                  ''')
+    parser.add_argument('--version',
+                        '-V',
+                        action='store_true',
+                        help='Show version')
+    parser.add_argument('--novalidate',
+                        action='store_true',
+                        help='Skip validate, just output json')
+
+    args = parser.parse_args()
+
+    if args.version:
+        version.show_and_exit(__file__, ["Hjson", "Mako"])
+
+    verbose = args.verbose
+    if (verbose):
+        log.basicConfig(format="%(levelname)s: %(message)s", level=log.DEBUG)
+    else:
+        log.basicConfig(format="%(levelname)s: %(message)s")
+
+    # Entries are triples of the form (arg, (format, dirspec)).
+    #
+    # arg is the name of the argument that selects the format. format is the
+    # name of the format. dirspec is None if the output is a single file; if
+    # the output needs a directory, it is a default path relative to the source
+    # file (used when --outdir is not given).
+    arg_to_format = [('j', ('json', None)), ('c', ('compact', None)),
+                     ('d', ('html', None)), ('doc', ('doc', None)),
+                     ('r', ('rtl', 'rtl')), ('s', ('dv', 'dv')),
+                     ('f', ('fpv', 'fpv/vip')), ('cdefines', ('cdh', None))]
+    format = None
+    dirspec = None
+    for arg_name, spec in arg_to_format:
+        if getattr(args, arg_name):
+            if format is not None:
+                log.error('Multiple output formats specified on '
+                          'command line ({} and {}).'.format(format, spec[0]))
+                sys.exit(1)
+            format, dirspec = spec
+    if format is None:
+        format = 'hjson'
+
+    infile = args.input
+
+    # Split parameters into key=value pairs.
+    raw_params = args.param.split(';') if args.param else []
+    params = []
+    for idx, raw_param in enumerate(raw_params):
+        tokens = raw_param.split('=')
+        if len(tokens) != 2:
+            raise ValueError('Entry {} in list of parameter defaults to '
+                             'apply is {!r}, which is not of the form '
+                             'param=value.'
+                             .format(idx, raw_param))
+        params.append((tokens[0], tokens[1]))
+
+    # Define either outfile or outdir (but not both), depending on the output
+    # format.
+    outfile = None
+    outdir = None
+    if dirspec is None:
+        if args.outdir is not None:
+            log.error('The {} format expects an output file, '
+                      'not an output directory.'.format(format))
+            sys.exit(1)
+
+        outfile = args.outfile
+    else:
+        if args.outfile is not sys.stdout:
+            log.error('The {} format expects an output directory, '
+                      'not an output file.'.format(format))
+            sys.exit(1)
+
+        if args.outdir is not None:
+            outdir = args.outdir
+        elif infile is not sys.stdin:
+            outdir = str(PurePath(infile.name).parents[1].joinpath(dirspec))
+        else:
+            # We're using sys.stdin, so can't infer an output directory name
+            log.error(
+                'The {} format writes to an output directory, which '
+                'cannot be inferred automatically if the input comes '
+                'from stdin. Use --outdir to specify it manually.'.format(
+                    format))
+            sys.exit(1)
+
+    if format == 'doc':
+        with outfile:
+            gen_selfdoc.document(outfile)
+        exit(0)
+
+    srcfull = infile.read()
+
+    try:
+        obj = IpBlock.from_text(srcfull, params, infile.name)
+    except ValueError as err:
+        log.error(str(err))
+        exit(1)
+
+    if args.novalidate:
+        with outfile:
+            gen_json.gen_json(obj, outfile, format)
+            outfile.write('\n')
+    else:
+        if format == 'rtl':
+            return gen_rtl.gen_rtl(obj, outdir)
+        if format == 'dv':
+            return gen_dv.gen_dv(obj, args.dv_base_prefix, outdir)
+        if format == 'fpv':
+            return gen_fpv.gen_fpv(obj, outdir)
+        src_lic = None
+        src_copy = ''
+        found_spdx = None
+        found_lunder = None
+        copy = re.compile(r'.*(copyright.*)|(.*\(c\).*)', re.IGNORECASE)
+        spdx = re.compile(r'.*(SPDX-License-Identifier:.+)')
+        lunder = re.compile(r'.*(Licensed under.+)', re.IGNORECASE)
+        for line in srcfull.splitlines():
+            mat = copy.match(line)
+            if mat is not None:
+                src_copy += mat.group(1)
+            mat = spdx.match(line)
+            if mat is not None:
+                found_spdx = mat.group(1)
+            mat = lunder.match(line)
+            if mat is not None:
+                found_lunder = mat.group(1)
+        if found_lunder:
+            src_lic = found_lunder
+        if found_spdx:
+            src_lic += '\n' + found_spdx
+
+        with outfile:
+            if format == 'html':
+                return gen_html.gen_html(obj, outfile)
+            elif format == 'cdh':
+                return gen_cheader.gen_cdefines(obj, outfile, src_lic, src_copy)
+            else:
+                return gen_json.gen_json(obj, outfile, format)
+
+            outfile.write('\n')
+
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/__init__.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/__init__.py
new file mode 100644
index 00000000..d8a34008
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/__init__.py
@@ -0,0 +1,8 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+from .lib import get_hjsonobj_xbars, search_ips  # noqa: F401
+# noqa: F401 These functions are used in topgen.py
+from .merge import amend_clocks, merge_top  # noqa: F401
+from .validate import validate_top, check_flash  # noqa: F401
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/c.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/c.py
new file mode 100644
index 00000000..58760a37
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/c.py
@@ -0,0 +1,444 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""This contains a class which is used to help generate `top_{name}.h` and
+`top_{name}.h`.
+"""
+from collections import OrderedDict
+from typing import Dict, List, Optional, Tuple
+
+from mako.template import Template
+
+from .lib import get_base_and_size, Name
+
+from reggen.ip_block import IpBlock
+
+
+class MemoryRegion(object):
+    def __init__(self, name: Name, base_addr: int, size_bytes: int):
+        assert isinstance(base_addr, int)
+        self.name = name
+        self.base_addr = base_addr
+        self.size_bytes = size_bytes
+        self.size_words = (size_bytes + 3) // 4
+
+    def base_addr_name(self):
+        return self.name + Name(["base", "addr"])
+
+    def offset_name(self):
+        return self.name + Name(["offset"])
+
+    def size_bytes_name(self):
+        return self.name + Name(["size", "bytes"])
+
+    def size_words_name(self):
+        return self.name + Name(["size", "words"])
+
+
+class CEnum(object):
+    def __init__(self, name):
+        self.name = name
+        self.enum_counter = 0
+        self.finalized = False
+
+        self.constants = []
+
+    def add_constant(self, constant_name, docstring=""):
+        assert not self.finalized
+
+        full_name = self.name + constant_name
+
+        value = self.enum_counter
+        self.enum_counter += 1
+
+        self.constants.append((full_name, value, docstring))
+
+        return full_name
+
+    def add_last_constant(self, docstring=""):
+        assert not self.finalized
+
+        full_name = self.name + Name(["last"])
+
+        _, last_val, _ = self.constants[-1]
+
+        self.constants.append((full_name, last_val, r"\internal " + docstring))
+        self.finalized = True
+
+    def render(self):
+        template = ("typedef enum ${enum.name.as_snake_case()} {\n"
+                    "% for name, value, docstring in enum.constants:\n"
+                    "  ${name.as_c_enum()} = ${value}, /**< ${docstring} */\n"
+                    "% endfor\n"
+                    "} ${enum.name.as_c_type()};")
+        return Template(template).render(enum=self)
+
+
+class CArrayMapping(object):
+    def __init__(self, name, output_type_name):
+        self.name = name
+        self.output_type_name = output_type_name
+
+        self.mapping = OrderedDict()
+
+    def add_entry(self, in_name, out_name):
+        self.mapping[in_name] = out_name
+
+    def render_declaration(self):
+        template = (
+            "extern const ${mapping.output_type_name.as_c_type()}\n"
+            "    ${mapping.name.as_snake_case()}[${len(mapping.mapping)}];")
+        return Template(template).render(mapping=self)
+
+    def render_definition(self):
+        template = (
+            "const ${mapping.output_type_name.as_c_type()}\n"
+            "    ${mapping.name.as_snake_case()}[${len(mapping.mapping)}] = {\n"
+            "% for in_name, out_name in mapping.mapping.items():\n"
+            "  [${in_name.as_c_enum()}] = ${out_name.as_c_enum()},\n"
+            "% endfor\n"
+            "};\n")
+        return Template(template).render(mapping=self)
+
+
+class TopGenC:
+    def __init__(self, top_info, name_to_block: Dict[str, IpBlock]):
+        self.top = top_info
+        self._top_name = Name(["top"]) + Name.from_snake_case(top_info["name"])
+        self._name_to_block = name_to_block
+
+        # The .c file needs the .h file's relative path, store it here
+        self.header_path = None
+
+        self._init_plic_targets()
+        self._init_plic_mapping()
+        self._init_alert_mapping()
+        self._init_pinmux_mapping()
+        self._init_pwrmgr_wakeups()
+        self._init_rstmgr_sw_rsts()
+        self._init_pwrmgr_reset_requests()
+        self._init_clkmgr_clocks()
+
+    def devices(self) -> List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]:
+        '''Return a list of MemoryRegion objects for devices on the bus
+
+        The list returned is pairs (full_if, region) where full_if is itself a
+        pair (inst_name, if_name). inst_name is the name of some IP block
+        instantiation. if_name is the name of the interface (may be None).
+        region is a MemoryRegion object representing the device.
+
+        '''
+        ret = []  # type: List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]
+        for inst in self.top['module']:
+            block = self._name_to_block[inst['type']]
+            for if_name, rb in block.reg_blocks.items():
+                full_if = (inst['name'], if_name)
+                full_if_name = Name.from_snake_case(full_if[0])
+                if if_name is not None:
+                    full_if_name += Name.from_snake_case(if_name)
+
+                name = self._top_name + full_if_name
+                base, size = get_base_and_size(self._name_to_block,
+                                               inst, if_name)
+
+                region = MemoryRegion(name, base, size)
+                ret.append((full_if, region))
+
+        return ret
+
+    def memories(self):
+        return [(m["name"],
+                 MemoryRegion(self._top_name + Name.from_snake_case(m["name"]),
+                              int(m["base_addr"], 0),
+                              int(m["size"], 0)))
+                for m in self.top["memory"]]
+
+    def _init_plic_targets(self):
+        enum = CEnum(self._top_name + Name(["plic", "target"]))
+
+        for core_id in range(int(self.top["num_cores"])):
+            enum.add_constant(Name(["ibex", str(core_id)]),
+                              docstring="Ibex Core {}".format(core_id))
+
+        enum.add_last_constant("Final PLIC target")
+
+        self.plic_targets = enum
+
+    def _init_plic_mapping(self):
+        """We eventually want to generate a mapping from interrupt id to the
+        source peripheral.
+
+        In order to do so, we generate two enums (one for interrupts, one for
+        sources), and store the generated names in a dictionary that represents
+        the mapping.
+
+        PLIC Interrupt ID 0 corresponds to no interrupt, and so no peripheral,
+        so we encode that in the enum as "unknown".
+
+        The interrupts have to be added in order, with "none" first, to ensure
+        that they get the correct mapping to their PLIC id, which is used for
+        addressing the right registers and bits.
+        """
+        sources = CEnum(self._top_name + Name(["plic", "peripheral"]))
+        interrupts = CEnum(self._top_name + Name(["plic", "irq", "id"]))
+        plic_mapping = CArrayMapping(
+            self._top_name + Name(["plic", "interrupt", "for", "peripheral"]),
+            sources.name)
+
+        unknown_source = sources.add_constant(Name(["unknown"]),
+                                              docstring="Unknown Peripheral")
+        none_irq_id = interrupts.add_constant(Name(["none"]),
+                                              docstring="No Interrupt")
+        plic_mapping.add_entry(none_irq_id, unknown_source)
+
+        # When we generate the `interrupts` enum, the only info we have about
+        # the source is the module name. We'll use `source_name_map` to map a
+        # short module name to the full name object used for the enum constant.
+        source_name_map = {}
+
+        for name in self.top["interrupt_module"]:
+            source_name = sources.add_constant(Name.from_snake_case(name),
+                                               docstring=name)
+            source_name_map[name] = source_name
+
+        sources.add_last_constant("Final PLIC peripheral")
+
+        for intr in self.top["interrupt"]:
+            # Some interrupts are multiple bits wide. Here we deal with that by
+            # adding a bit-index suffix
+            if "width" in intr and int(intr["width"]) != 1:
+                for i in range(int(intr["width"])):
+                    name = Name.from_snake_case(intr["name"]) + Name([str(i)])
+                    irq_id = interrupts.add_constant(name,
+                                                     docstring="{} {}".format(
+                                                         intr["name"], i))
+                    source_name = source_name_map[intr["module_name"]]
+                    plic_mapping.add_entry(irq_id, source_name)
+            else:
+                name = Name.from_snake_case(intr["name"])
+                irq_id = interrupts.add_constant(name, docstring=intr["name"])
+                source_name = source_name_map[intr["module_name"]]
+                plic_mapping.add_entry(irq_id, source_name)
+
+        interrupts.add_last_constant("The Last Valid Interrupt ID.")
+
+        self.plic_sources = sources
+        self.plic_interrupts = interrupts
+        self.plic_mapping = plic_mapping
+
+    def _init_alert_mapping(self):
+        """We eventually want to generate a mapping from alert id to the source
+        peripheral.
+
+        In order to do so, we generate two enums (one for alerts, one for
+        sources), and store the generated names in a dictionary that represents
+        the mapping.
+
+        Alert Handler has no concept of "no alert", unlike the PLIC.
+
+        The alerts have to be added in order, to ensure that they get the
+        correct mapping to their alert id, which is used for addressing the
+        right registers and bits.
+        """
+        sources = CEnum(self._top_name + Name(["alert", "peripheral"]))
+        alerts = CEnum(self._top_name + Name(["alert", "id"]))
+        alert_mapping = CArrayMapping(
+            self._top_name + Name(["alert", "for", "peripheral"]),
+            sources.name)
+
+        # When we generate the `alerts` enum, the only info we have about the
+        # source is the module name. We'll use `source_name_map` to map a short
+        # module name to the full name object used for the enum constant.
+        source_name_map = {}
+
+        for name in self.top["alert_module"]:
+            source_name = sources.add_constant(Name.from_snake_case(name),
+                                               docstring=name)
+            source_name_map[name] = source_name
+
+        sources.add_last_constant("Final Alert peripheral")
+
+        for alert in self.top["alert"]:
+            if "width" in alert and int(alert["width"]) != 1:
+                for i in range(int(alert["width"])):
+                    name = Name.from_snake_case(alert["name"]) + Name([str(i)])
+                    irq_id = alerts.add_constant(name,
+                                                 docstring="{} {}".format(
+                                                     alert["name"], i))
+                    source_name = source_name_map[alert["module_name"]]
+                    alert_mapping.add_entry(irq_id, source_name)
+            else:
+                name = Name.from_snake_case(alert["name"])
+                alert_id = alerts.add_constant(name, docstring=alert["name"])
+                source_name = source_name_map[alert["module_name"]]
+                alert_mapping.add_entry(alert_id, source_name)
+
+        alerts.add_last_constant("The Last Valid Alert ID.")
+
+        self.alert_sources = sources
+        self.alert_alerts = alerts
+        self.alert_mapping = alert_mapping
+
+    def _init_pinmux_mapping(self):
+        """Generate C enums for addressing pinmux registers and in/out selects.
+
+        Inputs/outputs are connected in the order the modules are listed in
+        the hjson under the "mio_modules" key. For each module, the corresponding
+        inouts are connected first, followed by either the inputs or the outputs.
+
+        Inputs:
+        - Peripheral chooses register field (pinmux_peripheral_in)
+        - Insel chooses MIO input (pinmux_insel)
+
+        Outputs:
+        - MIO chooses register field (pinmux_mio_out)
+        - Outsel chooses peripheral output (pinmux_outsel)
+
+        Insel and outsel have some special values which are captured here too.
+        """
+        pinmux_info = self.top['pinmux']
+        pinout_info = self.top['pinout']
+
+        # Peripheral Inputs
+        peripheral_in = CEnum(self._top_name +
+                              Name(['pinmux', 'peripheral', 'in']))
+        i = 0
+        for sig in pinmux_info['ios']:
+            if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'input']:
+                index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([])
+                name = Name.from_snake_case(sig['name']) + index
+                peripheral_in.add_constant(name, docstring='Peripheral Input {}'.format(i))
+                i += 1
+
+        peripheral_in.add_last_constant('Last valid peripheral input')
+
+        # Pinmux Input Selects
+        insel = CEnum(self._top_name + Name(['pinmux', 'insel']))
+        insel.add_constant(Name(['constant', 'zero']),
+                           docstring='Tie constantly to zero')
+        insel.add_constant(Name(['constant', 'one']),
+                           docstring='Tie constantly to one')
+        i = 0
+        for pad in pinout_info['pads']:
+            if pad['connection'] == 'muxed':
+                insel.add_constant(Name([pad['name']]),
+                                   docstring='MIO Pad {}'.format(i))
+                i += 1
+        insel.add_last_constant('Last valid insel value')
+
+        # MIO Outputs
+        mio_out = CEnum(self._top_name + Name(['pinmux', 'mio', 'out']))
+        i = 0
+        for pad in pinout_info['pads']:
+            if pad['connection'] == 'muxed':
+                mio_out.add_constant(Name.from_snake_case(pad['name']),
+                                     docstring='MIO Pad {}'.format(i))
+                i += 1
+        mio_out.add_last_constant('Last valid mio output')
+
+        # Pinmux Output Selects
+        outsel = CEnum(self._top_name + Name(['pinmux', 'outsel']))
+        outsel.add_constant(Name(['constant', 'zero']),
+                            docstring='Tie constantly to zero')
+        outsel.add_constant(Name(['constant', 'one']),
+                            docstring='Tie constantly to one')
+        outsel.add_constant(Name(['constant', 'high', 'z']),
+                            docstring='Tie constantly to high-Z')
+        i = 0
+        for sig in pinmux_info['ios']:
+            if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'output']:
+                index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([])
+                name = Name.from_snake_case(sig['name']) + index
+                outsel.add_constant(name, docstring='Peripheral Output {}'.format(i))
+                i += 1
+
+        outsel.add_last_constant('Last valid outsel value')
+
+        self.pinmux_peripheral_in = peripheral_in
+        self.pinmux_insel = insel
+        self.pinmux_mio_out = mio_out
+        self.pinmux_outsel = outsel
+
+    def _init_pwrmgr_wakeups(self):
+        enum = CEnum(self._top_name +
+                     Name(["power", "manager", "wake", "ups"]))
+
+        for signal in self.top["wakeups"]:
+            enum.add_constant(
+                Name.from_snake_case(signal["module"]) +
+                Name.from_snake_case(signal["name"]))
+
+        enum.add_last_constant("Last valid pwrmgr wakeup signal")
+
+        self.pwrmgr_wakeups = enum
+
+    # Enumerates the positions of all software controllable resets
+    def _init_rstmgr_sw_rsts(self):
+        sw_rsts = [
+            rst for rst in self.top["resets"]["nodes"]
+            if 'sw' in rst and rst['sw'] == 1
+        ]
+
+        enum = CEnum(self._top_name +
+                     Name(["reset", "manager", "sw", "resets"]))
+
+        for rst in sw_rsts:
+            enum.add_constant(Name.from_snake_case(rst["name"]))
+
+        enum.add_last_constant("Last valid rstmgr software reset request")
+
+        self.rstmgr_sw_rsts = enum
+
+    def _init_pwrmgr_reset_requests(self):
+        enum = CEnum(self._top_name +
+                     Name(["power", "manager", "reset", "requests"]))
+
+        for signal in self.top["reset_requests"]:
+            enum.add_constant(
+                Name.from_snake_case(signal["module"]) +
+                Name.from_snake_case(signal["name"]))
+
+        enum.add_last_constant("Last valid pwrmgr reset_request signal")
+
+        self.pwrmgr_reset_requests = enum
+
+    def _init_clkmgr_clocks(self):
+        """
+        Creates CEnums for accessing the software-controlled clocks in the
+        design.
+
+        The logic here matches the logic in topgen.py in how it instantiates the
+        clock manager with the described clocks.
+
+        We differentiate "gateable" clocks and "hintable" clocks because the
+        clock manager has separate register interfaces for each group.
+        """
+
+        aon_clocks = set()
+        for src in self.top['clocks']['srcs'] + self.top['clocks'][
+                'derived_srcs']:
+            if src['aon'] == 'yes':
+                aon_clocks.add(src['name'])
+
+        gateable_clocks = CEnum(self._top_name + Name(["gateable", "clocks"]))
+        hintable_clocks = CEnum(self._top_name + Name(["hintable", "clocks"]))
+
+        # This replicates the behaviour in `topgen.py` in deriving `hints` and
+        # `sw_clocks`.
+        for group in self.top['clocks']['groups']:
+            for (name, source) in group['clocks'].items():
+                if source not in aon_clocks:
+                    # All these clocks start with `clk_` which is redundant.
+                    clock_name = Name.from_snake_case(name).remove_part("clk")
+                    docstring = "Clock {} in group {}".format(
+                        name, group['name'])
+                    if group["sw_cg"] == "yes":
+                        gateable_clocks.add_constant(clock_name, docstring)
+                    elif group["sw_cg"] == "hint":
+                        hintable_clocks.add_constant(clock_name, docstring)
+
+        gateable_clocks.add_last_constant("Last Valid Gateable Clock")
+        hintable_clocks.add_last_constant("Last Valid Hintable Clock")
+
+        self.clkmgr_gateable_clocks = gateable_clocks
+        self.clkmgr_hintable_clocks = hintable_clocks
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/gen_dv.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/gen_dv.py
new file mode 100644
index 00000000..5e2beaa1
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/gen_dv.py
@@ -0,0 +1,46 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import logging as log
+from typing import Optional, Tuple
+
+from mako import exceptions  # type: ignore
+from mako.lookup import TemplateLookup  # type: ignore
+from pkg_resources import resource_filename
+
+from reggen.gen_dv import gen_core_file
+
+from .top import Top
+
+
+def sv_base_addr(top: Top, if_name: Tuple[str, Optional[str]]) -> str:
+    '''Get the base address of a device interface in SV syntax'''
+    return "{}'h{:x}".format(top.regwidth, top.if_addrs[if_name])
+
+
+def gen_dv(top: Top,
+           dv_base_prefix: str,
+           outdir: str) -> int:
+    '''Generate DV RAL model for a Top'''
+    # Read template
+    lookup = TemplateLookup(directories=[resource_filename('topgen', '.'),
+                                         resource_filename('reggen', '.')])
+    uvm_reg_tpl = lookup.get_template('top_uvm_reg.sv.tpl')
+
+    # Expand template
+    try:
+        to_write = uvm_reg_tpl.render(top=top,
+                                      dv_base_prefix=dv_base_prefix)
+    except:  # noqa: E722
+        log.error(exceptions.text_error_template().render())
+        return 1
+
+    # Dump to output file
+    dest_path = '{}/chip_ral_pkg.sv'.format(outdir)
+    with open(dest_path, 'w') as fout:
+        fout.write(to_write)
+
+    gen_core_file(outdir, 'chip', dv_base_prefix, ['chip_ral_pkg.sv'])
+
+    return 0
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/intermodule.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/intermodule.py
new file mode 100644
index 00000000..d1048c12
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/intermodule.py
@@ -0,0 +1,1005 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import logging as log
+import re
+from collections import OrderedDict
+from enum import Enum
+from typing import Dict, List, Tuple
+
+from reggen.ip_block import IpBlock
+from reggen.inter_signal import InterSignal
+from reggen.validate import check_int
+from topgen import lib
+
+IM_TYPES = ['uni', 'req_rsp']
+IM_ACTS = ['req', 'rsp', 'rcv']
+IM_VALID_TYPEACT = {'uni': ['req', 'rcv'], 'req_rsp': ['req', 'rsp']}
+IM_CONN_TYPE = ['1-to-1', '1-to-N', 'broadcast']
+
+
+class ImType(Enum):
+    Uni = 1
+    ReqRsp = 2
+
+
+class ImAct(Enum):
+    Req = 1
+    Rsp = 2
+    Rcv = 3
+
+
+class ImConn(Enum):
+    OneToOne = 1  # req <-> {rsp,rcv} with same width
+    OneToN = 2  # req width N <-> N x {rsp,rcv}s width 1
+    Broadcast = 3  # req width 1 <-> N x rcvs width 1
+
+
+def intersignal_format(req: Dict) -> str:
+    """Determine the signal format of the inter-module connections
+
+    @param[req] Request struct. It has instance name, package format
+                and etc.
+    """
+
+    # TODO: Handle array signal
+    result = "{req}_{struct}".format(req=req["inst_name"], struct=req["name"])
+
+    # check signal length if exceeds 100
+
+    # 7 : space + .
+    # 3 : _{i|o}(
+    # 6 : _{req|rsp}),
+    req_length = 7 + len(req["name"]) + 3 + len(result) + 6
+
+    if req_length > 100:
+        logmsg = "signal {0} length cannot be greater than 100"
+        log.warning(logmsg.format(result))
+        log.warning("Please consider shorten the instance name")
+    return result
+
+
+def get_suffixes(ims: OrderedDict) -> Tuple[str, str]:
+    """Get suffixes of the struct.
+
+    TL-UL struct uses `h2d`, `d2h` suffixes for req, rsp pair.
+    """
+    if ims["package"] == "tlul_pkg" and ims["struct"] == "tl":
+        return ("_h2d", "_d2h")
+
+    return ("_req", "_rsp")
+
+
+def add_intermodule_connection(obj: OrderedDict, req_m: str, req_s: str,
+                               rsp_m: str, rsp_s: str):
+    """Add if doesn't exist the connection
+
+    Add a connection into obj['inter_module']['connect'] dictionary if doesn't exist.
+
+    Parameters:
+        obj:   Top dictionary object
+        req_m: Requester module name
+        req_s: Requester signal name
+        rsp_m: Responder module name
+        rsp_s: Responder signal name
+
+    Returns:
+        No return type for this function
+    """
+    req_key = "{}.{}".format(req_m, req_s)
+    rsp_key = "{}.{}".format(rsp_m, rsp_s)
+
+    connect = obj["inter_module"]["connect"]
+    if req_key in connect:
+        # check if rsp has data
+        if rsp_key in connect[req_key]:
+            return
+        req_key.append(rsp_key)
+        return
+
+    # req_key is not in connect:
+    # check if rsp_key
+    if rsp_key in connect:
+        # check if rsp has data
+        if req_key in connect[rsp_key]:
+            return
+        rsp_key.append(req_key)
+        return
+
+    # Add new key and connect
+    connect[req_key] = [rsp_key]
+
+
+def autoconnect_xbar(topcfg: OrderedDict,
+                     name_to_block: Dict[str, IpBlock],
+                     xbar: OrderedDict) -> None:
+    # The crossbar is connecting to modules and memories in topcfg, plus
+    # possible external connections. Make indices for the modules and memories
+    # for quick lookup and add some assertions to make sure no name appears in
+    # multiple places.
+    name_to_module = {}
+    for mod in topcfg['module']:
+        assert mod['name'] not in name_to_module
+        if lib.is_inst(mod):
+            name_to_module[mod['name']] = mod
+
+    name_to_memory = {}
+    for mem in topcfg['memory']:
+        assert mem['name'] not in name_to_memory
+        if lib.is_inst(mem):
+            name_to_memory[mem['name']] = mem
+
+    # The names of modules and memories should be disjoint
+    assert not (set(name_to_module.keys()) & set(name_to_memory.keys()))
+
+    external_names = (set(topcfg['inter_module']['top']) |
+                      set(topcfg["inter_module"]["external"].keys()))
+
+    ports = [x for x in xbar["nodes"] if x["type"] in ["host", "device"]]
+    for port in ports:
+        # Here, we expect port_name to either be a single identifier (in which
+        # case, it's taken as the name of some module or memory) to be a dotted
+        # pair MOD.INAME where MOD is the name of some module and INAME is the
+        # associated interface name.
+        name_parts = port['name'].split('.', 1)
+        port_base = name_parts[0]
+        port_iname = name_parts[1] if len(name_parts) > 1 else None
+        esc_name = port['name'].replace('.', '__')
+
+        if port["xbar"]:
+            if port_iname is not None:
+                log.error('A crossbar connection may not '
+                          'have a target of the form MOD.INAME (saw {!r})'
+                          .format(port['name']))
+                continue
+
+            if port["type"] == "host":
+                # Skip as device will add connection
+                continue
+
+            # Device port adds signal
+            add_intermodule_connection(obj=topcfg,
+                                       req_m=xbar["name"],
+                                       req_s="tl_" + esc_name,
+                                       rsp_m=esc_name,
+                                       rsp_s="tl_" + xbar["name"])
+            continue  # xbar port case
+
+        port_mod = name_to_module.get(port_base)
+        port_mem = name_to_memory.get(port_base)
+        assert port_mod is None or port_mem is None
+
+        if not (port_mod or port_mem):
+            # if not in module, memory, should be existed in top or ext field
+            module_key = "{}.tl_{}".format(xbar["name"], esc_name)
+            if module_key not in external_names:
+                log.error("Inter-module key {} cannot be found in module, "
+                          "memory, top, or external lists.".format(module_key))
+
+            continue
+
+        if port_iname is not None and port_mem is not None:
+            log.error('Cannot make connection for {!r}: the base of the name '
+                      'points to a memory but memories do not support '
+                      'interface names.'
+                      .format(port['name']))
+
+        is_host = port['type'] == 'host'
+
+        # If the hit is a module, it originally came from reggen (via
+        # merge.py's amend_ip() function). In this case, we should have a
+        # BusInterfaces object as well as a list of InterSignal objects.
+        #
+        # If not, this is a memory that will just have a dictionary of inter
+        # signals.
+        if port_mod is not None:
+            block = name_to_block[port_mod['type']]
+            try:
+                sig_name = block.bus_interfaces.find_port_name(is_host,
+                                                               port_iname)
+            except KeyError:
+                log.error('Cannot make {} connection for {!r}: the base of '
+                          'the target module has no matching bus interface.'
+                          .format('host' if is_host else 'device',
+                                  port['name']))
+                continue
+        else:
+            inter_signal_list = port_mem['inter_signal_list']
+            act = 'req' if is_host else 'rsp'
+            matches = [
+                x for x in inter_signal_list
+                if (x.get('package') == 'tlul_pkg' and
+                    x['struct'] == 'tl' and
+                    x['act'] == act)
+            ]
+            if not matches:
+                log.error('Cannot make {} connection for {!r}: the memory '
+                          'has no signal with an action of {}.'
+                          .format('host' if is_host else 'device',
+                                  port['name'],
+                                  act))
+                continue
+
+            assert len(matches) == 1
+            sig_name = matches[0]['name']
+
+        add_intermodule_connection(obj=topcfg,
+                                   req_m=port_base,
+                                   req_s=sig_name,
+                                   rsp_m=xbar["name"],
+                                   rsp_s="tl_" + esc_name)
+
+
+def autoconnect(topcfg: OrderedDict, name_to_block: Dict[str, IpBlock]):
+    """Matching the connection based on the naming rule
+    between {memory, module} <-> Xbar.
+    """
+
+    # Add xbar connection to the modules, memories
+    for xbar in topcfg["xbar"]:
+        autoconnect_xbar(topcfg, name_to_block, xbar)
+
+
+def _get_default_name(sig, suffix):
+    """Generate default for a net if one does not already exist.
+    """
+
+    # The else case covers the scenario where neither package nor default is provided.
+    # Specifically, the interface is 'logic' and has no default value.
+    # In this situation, just return 0's
+    if sig['default']:
+        return sig['default']
+    elif sig['package']:
+        return "{}::{}_DEFAULT".format(sig['package'], (sig["struct"] + suffix).upper())
+    else:
+        return "'0"
+
+
+def elab_intermodule(topcfg: OrderedDict):
+    """Check the connection of inter-module and categorize them
+
+    In the top template, it uses updated inter_module fields to create
+    connections between the modules (incl. memories). This function is to
+    create and check the validity of the connections `inter_module` using IPs'
+    `inter_signal_list`.
+    """
+
+    list_of_intersignals = []
+
+    if "inter_signal" not in topcfg:
+        topcfg["inter_signal"] = OrderedDict()
+
+    # Gather the inter_signal_list
+    instances = topcfg["module"] + topcfg["memory"] + topcfg["xbar"] + \
+        topcfg["host"] + topcfg["port"]
+
+    for x in instances:
+        old_isl = x.get('inter_signal_list')
+        if old_isl is None:
+            continue
+
+        new_isl = []
+        for entry in old_isl:
+            # Convert any InterSignal objects to the expected dictionary format.
+            sig = (entry.as_dict()
+                   if isinstance(entry, InterSignal)
+                   else entry.copy())
+
+            # Add instance name to the entry and add to list_of_intersignals
+            sig["inst_name"] = x["name"]
+            list_of_intersignals.append(sig)
+            new_isl.append(sig)
+
+        x['inter_signal_list'] = new_isl
+
+    # Add field to the topcfg
+    topcfg["inter_signal"]["signals"] = list_of_intersignals
+
+    # TODO: Cross check Can be done here not in validate as ipobj is not
+    # available in validate
+    error = check_intermodule(topcfg, "Inter-module Check")
+    assert error == 0, "Inter-module validation is failed cannot move forward."
+
+    # intermodule
+    definitions = []
+
+    # Check the originator
+    # As inter-module connection allow only 1:1, 1:N, or N:1, pick the most
+    # common signals. If a requester connects to multiple responders/receivers,
+    # the requester is main connector so that the definition becomes array.
+    #
+    # For example:
+    #  inter_module: {
+    #    'connect': {
+    #      'pwr_mgr.pwrup': ['lc.pwrup', 'otp.pwrup']
+    #    }
+    #  }
+    # The tool adds `struct [1:0] pwr_mgr_pwrup`
+    # It doesn't matter whether `pwr_mgr.pwrup` is requester or responder.
+    # If the key is responder type, then the connection is made in reverse,
+    # such that `lc.pwrup --> pwr_mgr.pwrup[0]` and
+    # `otp.pwrup --> pwr_mgr.pwrup[1]`
+
+    uid = 0  # Unique connection ID across the top
+
+    for req, rsps in topcfg["inter_module"]["connect"].items():
+        log.info("{req} --> {rsps}".format(req=req, rsps=rsps))
+
+        # Split index
+        req_module, req_signal, req_index = filter_index(req)
+
+        # get the module signal
+        req_struct = find_intermodule_signal(list_of_intersignals, req_module,
+                                             req_signal)
+
+        # decide signal format based on the `key`
+        sig_name = intersignal_format(req_struct)
+        req_struct["top_signame"] = sig_name
+
+        # Find package in req, rsps
+        if "package" in req_struct:
+            package = req_struct["package"]
+        else:
+            for rsp in rsps:
+                rsp_module, rsp_signal, rsp_index = filter_index(rsp)
+                rsp_struct = find_intermodule_signal(list_of_intersignals,
+                                                     rsp_module, rsp_signal)
+                if "package" in rsp_struct:
+                    package = rsp_struct["package"]
+                    break
+            if not package:
+                package = ""
+
+        # Add to definition
+        if req_struct["type"] == "req_rsp":
+            req_suffix, rsp_suffix = get_suffixes(req_struct)
+            req_default = _get_default_name(req_struct, req_suffix)
+            rsp_default = _get_default_name(req_struct, rsp_suffix)
+
+            # based on the active direction of the req_struct, one of the directions does not
+            # need a default since it will be an output
+            if (req_struct["act"] == 'req'):
+                req_default = ''
+            else:
+                rsp_default = ''
+
+            # Add two definitions
+            definitions.append(
+                OrderedDict([('package', package),
+                             ('struct', req_struct["struct"] + req_suffix),
+                             ('signame', sig_name + "_req"),
+                             ('width', req_struct["width"]),
+                             ('type', req_struct["type"]),
+                             ('end_idx', req_struct["end_idx"]),
+                             ('act', req_struct["act"]),
+                             ('suffix', "req"),
+                             ('default', req_default)]))
+            definitions.append(
+                OrderedDict([('package', package),
+                             ('struct', req_struct["struct"] + rsp_suffix),
+                             ('signame', sig_name + "_rsp"),
+                             ('width', req_struct["width"]),
+                             ('type', req_struct["type"]),
+                             ('end_idx', req_struct["end_idx"]),
+                             ('act', req_struct["act"]),
+                             ('suffix', "rsp"),
+                             ('default', rsp_default)]))
+        else:
+            # unidirection
+            default = _get_default_name(req_struct, "")
+            definitions.append(
+                OrderedDict([('package', package),
+                             ('struct', req_struct["struct"]),
+                             ('signame', sig_name),
+                             ('width', req_struct["width"]),
+                             ('type', req_struct["type"]),
+                             ('end_idx', req_struct["end_idx"]),
+                             ('act', req_struct["act"]),
+                             ('suffix', ""),
+                             ('default', default)]))
+
+        req_struct["index"] = -1
+
+        for i, rsp in enumerate(rsps):
+            # Split index
+            rsp_module, rsp_signal, rsp_index = filter_index(rsp)
+
+            rsp_struct = find_intermodule_signal(list_of_intersignals,
+                                                 rsp_module, rsp_signal)
+
+            # determine the signal name
+
+            rsp_struct["top_signame"] = sig_name
+            if req_struct["type"] == "uni" and req_struct[
+                    "top_type"] == "broadcast":
+                rsp_struct["index"] = -1
+            elif rsp_struct["width"] == req_struct["width"] and len(rsps) == 1:
+                rsp_struct["index"] = -1
+            else:
+                rsp_struct["index"] = -1 if req_struct["width"] == 1 else i
+
+            # Assume it is logic
+            # req_rsp doesn't allow logic
+            if req_struct["struct"] == "logic":
+                assert req_struct[
+                    "type"] != "req_rsp", "logic signal cannot have req_rsp type"
+
+            # increase Unique ID
+            uid += 1
+
+    # TODO: Check unconnected port
+    if "top" not in topcfg["inter_module"]:
+        topcfg["inter_module"]["top"] = []
+
+    for s in topcfg["inter_module"]["top"]:
+        sig_m, sig_s, sig_i = filter_index(s)
+        assert sig_i == -1, 'top net connection should not use bit index'
+        sig = find_intermodule_signal(list_of_intersignals, sig_m, sig_s)
+        sig_name = intersignal_format(sig)
+        sig["top_signame"] = sig_name
+        if "index" not in sig:
+            sig["index"] = -1
+
+        if sig["type"] == "req_rsp":
+            req_suffix, rsp_suffix = get_suffixes(sig)
+            # Add two definitions
+            definitions.append(
+                OrderedDict([('package', sig["package"]),
+                             ('struct', sig["struct"] + req_suffix),
+                             ('signame', sig_name + "_req"),
+                             ('width', sig["width"]), ('type', sig["type"]),
+                             ('end_idx', -1),
+                             ('default', sig["default"])]))
+            definitions.append(
+                OrderedDict([('package', sig["package"]),
+                             ('struct', sig["struct"] + rsp_suffix),
+                             ('signame', sig_name + "_rsp"),
+                             ('width', sig["width"]), ('type', sig["type"]),
+                             ('end_idx', -1),
+                             ('default', sig["default"])]))
+        else:  # if sig["type"] == "uni":
+            definitions.append(
+                OrderedDict([('package', sig["package"]),
+                             ('struct', sig["struct"]), ('signame', sig_name),
+                             ('width', sig["width"]), ('type', sig["type"]),
+                             ('end_idx', -1),
+                             ('default', sig["default"])]))
+
+    topcfg["inter_module"].setdefault('external', [])
+    topcfg["inter_signal"].setdefault('external', [])
+
+    for s, port in topcfg["inter_module"]["external"].items():
+        sig_m, sig_s, sig_i = filter_index(s)
+        assert sig_i == -1, 'top net connection should not use bit index'
+        sig = find_intermodule_signal(list_of_intersignals, sig_m, sig_s)
+
+        # To make netname `_o` or `_i`
+        sig['external'] = True
+
+        sig_name = port if port != "" else intersignal_format(sig)
+
+        # if top signame already defined, then a previous connection category
+        # is already connected to external pin.  Sig name is only used for
+        # port definition
+        conn_type = False
+        if "top_signame" not in sig:
+            sig["top_signame"] = sig_name
+        else:
+            conn_type = True
+
+        if "index" not in sig:
+            sig["index"] = -1
+
+        # Add the port definition to top external ports
+        index = sig["index"]
+        netname = sig["top_signame"]
+        if sig["type"] == "req_rsp":
+            req_suffix, rsp_suffix = get_suffixes(sig)
+            if sig["act"] == "req":
+                req_sigsuffix, rsp_sigsuffix = ("_o", "_i")
+
+            else:
+                req_sigsuffix, rsp_sigsuffix = ("_i", "_o")
+
+            topcfg["inter_signal"]["external"].append(
+                OrderedDict([('package', sig["package"]),
+                             ('struct', sig["struct"] + req_suffix),
+                             ('signame', sig_name + "_req" + req_sigsuffix),
+                             ('width', sig["width"]), ('type', sig["type"]),
+                             ('default', sig["default"]),
+                             ('direction',
+                              'out' if sig['act'] == "req" else 'in'),
+                             ('conn_type', conn_type),
+                             ('index', index),
+                             ('netname', netname + req_suffix)]))
+            topcfg["inter_signal"]["external"].append(
+                OrderedDict([('package', sig["package"]),
+                             ('struct', sig["struct"] + rsp_suffix),
+                             ('signame', sig_name + "_rsp" + rsp_sigsuffix),
+                             ('width', sig["width"]), ('type', sig["type"]),
+                             ('default', sig["default"]),
+                             ('direction',
+                              'in' if sig['act'] == "req" else 'out'),
+                             ('conn_type', conn_type),
+                             ('index', index),
+                             ('netname', netname + rsp_suffix)]))
+        else:  # uni
+            if sig["act"] == "req":
+                sigsuffix = "_o"
+            else:
+                sigsuffix = "_i"
+            topcfg["inter_signal"]["external"].append(
+                OrderedDict([('package', sig.get("package", "")),
+                             ('struct', sig["struct"]),
+                             ('signame', sig_name + sigsuffix),
+                             ('width', sig["width"]), ('type', sig["type"]),
+                             ('default', sig["default"]),
+                             ('direction',
+                              'out' if sig['act'] == "req" else 'in'),
+                             ('conn_type', conn_type),
+                             ('index', index),
+                             ('netname', netname)]))
+
+    for sig in topcfg["inter_signal"]["signals"]:
+        # Check if it exist in definitions
+        if "top_signame" in sig:
+            continue
+
+        # Set index to -1
+        sig["index"] = -1
+
+        # TODO: Handle the unconnected port rule
+
+    if "definitions" not in topcfg["inter_signal"]:
+        topcfg["inter_signal"]["definitions"] = definitions
+
+
+def filter_index(signame: str) -> Tuple[str, str, int]:
+    """If the signal has array indicator `[N]` then split and return name and
+    array index. If not, array index is -1.
+
+    param signame module.sig{[N]}
+
+    result (module_name, signal_name, array_index)
+    """
+    m = re.match(r'(\w+)\.(\w+)(\[(\d+)\])*', signame)
+
+    if not m:
+        # Cannot match the pattern
+        return "", "", -1
+
+    if m.group(3):
+        # array index is not None
+        return m.group(1), m.group(2), m.group(4)
+
+    return m.group(1), m.group(2), -1
+
+
+def find_intermodule_signal(sig_list, m_name, s_name) -> Dict:
+    """Return the intermodule signal structure
+    """
+
+    filtered = [
+        x for x in sig_list if x["name"] == s_name and x["inst_name"] == m_name
+    ]
+
+    if len(filtered) == 1:
+        return filtered[0]
+
+    log.error("Found {num} entry/entries for {m_name}.{s_name}:".format(
+        num=len(filtered), m_name=m_name, s_name=s_name))
+    return None
+
+
+# Validation
+def check_intermodule_field(sig: OrderedDict,
+                            prefix: str = "") -> Tuple[int, OrderedDict]:
+    error = 0
+
+    # type check
+    if sig["type"] not in IM_TYPES:
+        log.error("{prefix} Inter_signal {name} "
+                  "type {type} is incorrect.".format(prefix=prefix,
+                                                     name=sig["name"],
+                                                     type=sig["type"]))
+        error += 1
+
+    if sig["act"] not in IM_ACTS:
+        log.error("{prefix} Inter_signal {name} "
+                  "act {act} is incorrect.".format(prefix=prefix,
+                                                   name=sig["name"],
+                                                   act=sig["act"]))
+        error += 1
+
+    # Check if type and act are matched
+    if error == 0:
+        if sig["act"] not in IM_VALID_TYPEACT[sig['type']]:
+            log.error("{type} and {act} of {name} are not a valid pair."
+                      "".format(type=sig['type'],
+                                act=sig['act'],
+                                name=sig['name']))
+            error += 1
+    # Check 'width' field
+    width = 1
+    if "width" not in sig:
+        sig["width"] = 1
+    elif not isinstance(sig["width"], int):
+        width, err = check_int(sig["width"], sig["name"])
+        if err:
+            log.error("{prefix} Inter-module {inst}.{sig} 'width' "
+                      "should be int type.".format(prefix=prefix,
+                                                   inst=sig["inst_name"],
+                                                   sig=sig["name"]))
+            error += 1
+        else:
+            # convert to int value
+            sig["width"] = width
+
+    # Add empty string if no explicit default for dangling pins is given.
+    # In that case, dangling pins of type struct will be tied to the default
+    # parameter in the corresponding package, and dangling pins of type logic
+    # will be tied off to '0.
+    if "default" not in sig:
+        sig["default"] = ""
+
+    if "package" not in sig:
+        sig["package"] = ""
+
+    return error, sig
+
+
+def find_otherside_modules(topcfg: OrderedDict, m,
+                           s) -> List[Tuple[str, str, str]]:
+    """Find far-end port based on given module and signal name
+    """
+    # TODO: handle special cases
+    special_inst_names = {
+        ('main', 'tl_rom'): ('tl_adapter_rom', 'tl'),
+        ('main', 'tl_ram_main'): ('tl_adapter_ram_main', 'tl'),
+        ('main', 'tl_eflash'): ('tl_adapter_eflash', 'tl'),
+        ('peri', 'tl_ram_ret_aon'): ('tl_adapter_ram_ret_aon', 'tl'),
+        ('main', 'tl_corei'): ('rv_core_ibex', 'tl_i'),
+        ('main', 'tl_cored'): ('rv_core_ibex', 'tl_d'),
+        ('main', 'tl_dm_sba'): ('dm_top', 'tl_h'),
+        ('main', 'tl_debug_mem'): ('dm_top', 'tl_d'),
+        ('peri', 'tl_ast'): ('ast', 'tl')
+    }
+    special_result = special_inst_names.get((m, s))
+    if special_result is not None:
+        return [('top', special_result[0], special_result[1])]
+
+    signame = "{}.{}".format(m, s)
+    for req, rsps in topcfg["inter_module"]["connect"].items():
+        if req.startswith(signame):
+            # return rsps after splitting module instance name and the port
+            result = []
+            for rsp in rsps:
+                rsp_m, rsp_s, rsp_i = filter_index(rsp)
+                result.append(('connect', rsp_m, rsp_s))
+            return result
+
+        for rsp in rsps:
+            if signame == rsp:
+                req_m, req_s, req_i = filter_index(req)
+                return [('connect', req_m, req_s)]
+
+    # if reaches here, it means either the format is wrong, or floating port.
+    log.error("`find_otherside_modules()`: "
+              "No such signal {}.{} exists.".format(m, s))
+    return []
+
+
+def check_intermodule(topcfg: Dict, prefix: str) -> int:
+    if "inter_module" not in topcfg:
+        return 0
+
+    total_error = 0
+
+    for req, rsps in topcfg["inter_module"]["connect"].items():
+        error = 0
+        # checking the key, value are in correct format
+        # Allowed format
+        #   1. module.signal
+        #   2. module.signal[index] // Remember array is not yet supported
+        #                           // But allow in format checker
+        #
+        # Example:
+        #   inter_module: {
+        #     'connect': {
+        #       'flash_ctrl.flash': ['eflash.flash_ctrl'],
+        #       'life_cycle.provision': ['debug_tap.dbg_en', 'dft_ctrl.en'],
+        #       'otp.pwr_hold': ['pwrmgr.peri[0]'],
+        #       'flash_ctrl.pwr_hold': ['pwrmgr.peri[1]'],
+        #     }
+        #   }
+        #
+        # If length of value list is > 1, then key should be array (width need to match)
+        # If key is format #2, then length of value list shall be 1
+        # If one of the value is format #2, then the key should be 1 bit width and
+        # entries of value list should be 1
+        req_m, req_s, req_i = filter_index(req)
+
+        if req_s == "":
+            log.error(
+                "Cannot parse the inter-module signal key '{req}'".format(
+                    req=req))
+            error += 1
+
+        # Check rsps signal format is list
+        if not isinstance(rsps, list):
+            log.error("Value of key '{req}' should be a list".format(req=req))
+            error += 1
+            continue
+
+        req_struct = find_intermodule_signal(topcfg["inter_signal"]["signals"],
+                                             req_m, req_s)
+
+        err, req_struct = check_intermodule_field(req_struct)
+        error += err
+
+        if req_i != -1 and len(rsps) != 1:
+            # Array format should have one entry
+            log.error(
+                "If key {req} has index, only one entry is allowed.".format(
+                    req=req))
+            error += 1
+
+        total_width = 0
+        widths = []
+
+        # Check rsp format
+        for i, rsp in enumerate(rsps):
+            rsp_m, rsp_s, rsp_i = filter_index(rsp)
+            if rsp_s == "":
+                log.error(
+                    "Cannot parse the inter-module signal key '{req}->{rsp}'".
+                    format(req=req, rsp=rsp))
+                error += 1
+
+            rsp_struct = find_intermodule_signal(
+                topcfg["inter_signal"]["signals"], rsp_m, rsp_s)
+
+            err, rsp_struct = check_intermodule_field(rsp_struct)
+            error += err
+
+            total_width += rsp_struct["width"]
+            widths.append(rsp_struct["width"])
+
+            # Type check
+            # If no package was declared, it is declared with an empty string
+            if not rsp_struct["package"]:
+                rsp_struct["package"] = req_struct.get("package", "")
+            elif req_struct["package"] != rsp_struct["package"]:
+                log.error(
+                    "Inter-module package should be matched: "
+                    "{req}->{rsp} exp({expected}), actual({actual})".format(
+                        req=req_struct["name"],
+                        rsp=rsp_struct["name"],
+                        expected=req_struct["package"],
+                        actual=rsp_struct["package"]))
+                error += 1
+            if req_struct["type"] != rsp_struct["type"]:
+                log.error(
+                    "Inter-module type should be matched: "
+                    "{req}->{rsp} exp({expected}), actual({actual})".format(
+                        req=req_struct["name"],
+                        rsp=rsp_struct["name"],
+                        expected=req_struct["type"],
+                        actual=rsp_struct["type"]))
+                error += 1
+
+            # If len(rsps) is 1, then the width should be matched to req
+            if req_struct["width"] != 1:
+                if rsp_struct["width"] not in [1, req_struct["width"]]:
+                    log.error(
+                        "If req {req} is an array, "
+                        "rsp {rsp} shall be non-array or array with same width"
+                        .format(req=req, rsp=rsp))
+                    error += 1
+
+                elif rsp_i != -1:
+                    # If rsp has index, req should be width 1
+                    log.error(
+                        "If rsp {rsp} has an array index, only one-to-one map is allowed."
+                        .format(rsp=rsp))
+                    error += 1
+
+        # Determine if broadcast or one-to-N
+        log.debug("Handling inter-sig {} {}".format(req_struct['name'], total_width))
+        req_struct["end_idx"] = -1
+        if req_struct["width"] > 1 or len(rsps) != 1:
+            # If req width is same to the every width of rsps ==> broadcast
+            if len(rsps) * [req_struct["width"]] == widths:
+                log.debug("broadcast type")
+                req_struct["top_type"] = "broadcast"
+
+            # If req width is same as total width of rsps ==> one-to-N
+            elif req_struct["width"] == total_width:
+                log.debug("one-to-N type")
+                req_struct["top_type"] = "one-to-N"
+
+            # one-to-N connection is not fully populated
+            elif req_struct["width"] > total_width:
+                log.debug("partial one-to-N type")
+                req_struct["top_type"] = "partial-one-to-N"
+                req_struct["end_idx"] = len(rsps)
+
+            # If not, error
+            else:
+                log.error("'uni' type connection {req} should be either "
+                          "OneToN or Broadcast".format(req=req))
+                error += 1
+
+        elif req_struct["type"] == "uni":
+            # one-to-one connection
+            req_struct["top_type"] = "broadcast"
+
+        # If req is array, it is not allowed to have partial connections.
+        # Doing for loop again here: Make code separate from other checker
+        # for easier maintenance
+        total_error += error
+
+        if error != 0:
+            # Skip the check
+            continue
+
+    for item in topcfg["inter_module"]["top"] + list(
+            topcfg["inter_module"]["external"].keys()):
+        sig_m, sig_s, sig_i = filter_index(item)
+        if sig_i != -1:
+            log.error("{item} cannot have index".format(item=item))
+            total_error += 1
+
+        sig_struct = find_intermodule_signal(topcfg["inter_signal"]["signals"],
+                                             sig_m, sig_s)
+        err, sig_struct = check_intermodule_field(sig_struct)
+        total_error += err
+
+    return total_error
+
+
+# Template functions
+def im_defname(obj: OrderedDict) -> str:
+    """return definition struct name
+
+    e.g. flash_ctrl::flash_req_t
+    """
+    if obj["package"] == "":
+        # should be logic
+        return "logic"
+
+    return "{package}::{struct}_t".format(package=obj["package"],
+                                          struct=obj["struct"])
+
+
+def im_netname(sig: OrderedDict,
+               suffix: str = "", default_name=False) -> str:
+    """return top signal name with index
+
+    It also adds suffix for external signal.
+
+    The default name input forces function to return default name, even if object
+    has a connection.
+    """
+
+    # Basic check and add missing fields
+    err, obj = check_intermodule_field(sig)
+    assert not err
+
+    # Floating signals
+    # TODO: Find smarter way to assign default?
+    if "top_signame" not in obj or default_name:
+        if obj["act"] == "req" and suffix == "req":
+            return ""
+        if obj["act"] == "rsp" and suffix == "rsp":
+            return ""
+        if obj["act"] == "req" and suffix == "rsp":
+            # custom default has been specified
+            if obj["default"]:
+                return obj["default"]
+            if obj["package"] == "tlul_pkg" and obj["struct"] == "tl":
+                return "{package}::{struct}_D2H_DEFAULT".format(
+                    package=obj["package"], struct=obj["struct"].upper())
+            return "{package}::{struct}_RSP_DEFAULT".format(
+                package=obj["package"], struct=obj["struct"].upper())
+        if obj["act"] == "rsp" and suffix == "req":
+            # custom default has been specified
+            if obj["default"]:
+                return obj["default"]
+            if obj.get("package") == "tlul_pkg" and obj["struct"] == "tl":
+                return "{package}::{struct}_H2D_DEFAULT".format(
+                    package=obj["package"], struct=obj["struct"].upper())
+            # default is used for dangling ports in definitions.
+            # the struct name already has `_req` suffix
+            return "{package}::{struct}_REQ_DEFAULT".format(
+                package=obj.get("package", ''), struct=obj["struct"].upper())
+        if obj["act"] == "rcv" and suffix == "" and obj["struct"] == "logic":
+            # custom default has been specified
+            if obj["default"]:
+                return obj["default"]
+            return "'0"
+        if obj["act"] == "rcv" and suffix == "":
+            # custom default has been specified
+            if obj["default"]:
+                return obj["default"]
+            return "{package}::{struct}_DEFAULT".format(
+                package=obj["package"], struct=obj["struct"].upper())
+
+        return ""
+
+    # Connected signals
+    assert suffix in ["", "req", "rsp"]
+
+    suffix_s = "_{suffix}".format(suffix=suffix) if suffix != "" else suffix
+
+    # External signal handling
+    if "external" in obj and obj["external"]:
+        pairs = {
+            # act , suffix: additional suffix
+            ("req", "req"): "_o",
+            ("req", "rsp"): "_i",
+            ("rsp", "req"): "_i",
+            ("rsp", "rsp"): "_o",
+            ("req", ""): "_o",
+            ("rcv", ""): "_i"
+        }
+        suffix_s += pairs[(obj['act'], suffix)]
+
+    return "{top_signame}{suffix}{index}".format(
+        top_signame=obj["top_signame"],
+        suffix=suffix_s,
+        index=lib.index(obj["index"]))
+
+
+def im_portname(obj: OrderedDict, suffix: str = "") -> str:
+    """return IP's port name
+
+    e.g signame_o for requester req signal
+    """
+    act = obj['act']
+    name = obj['name']
+
+    if suffix == "":
+        suffix_s = "_o" if act == "req" else "_i"
+    elif suffix == "req":
+        suffix_s = "_o" if act == "req" else "_i"
+    else:
+        suffix_s = "_o" if act == "rsp" else "_i"
+
+    return name + suffix_s
+
+
+def get_dangling_im_def(objs: OrderedDict) -> str:
+    """return partial inter-module definitions
+
+    Dangling intermodule connections happen when a one-to-N assignment
+    is not fully populated.
+
+    This can result in two types of dangling:
+    - outgoing requests not used
+    - incoming responses not driven
+
+    The determination of which category we fall into follows similar rules
+    as those used by im_netname.
+
+    When the direction of the net is the same as the active direction of the
+    the connecting module, it is "unused".
+
+    When the direction of the net is opposite of the active direction of the
+    the connecting module, it is "undriven".
+
+    As an example, edn is defined as "rsp" of a "req_rsp" pair. It is also used
+    as the "active" module in inter-module connection. If there are not enough
+    connecting modules, the 'req' line is undriven, while the 'rsp' line is
+    unused.
+
+    """
+    unused_def = [obj for obj in objs if obj['end_idx'] > 0 and
+                  obj['act'] == obj['suffix']]
+
+    undriven_def = [obj for obj in objs if obj['end_idx'] > 0 and
+                    (obj['act'] == 'req' and obj['suffix'] == 'rsp' or
+                     obj['act'] == 'rsp' and obj['suffix'] == 'req')]
+
+    return unused_def, undriven_def
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/lib.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/lib.py
new file mode 100644
index 00000000..a1354fdf
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/lib.py
@@ -0,0 +1,497 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import logging as log
+import re
+import sys
+from collections import OrderedDict
+from copy import deepcopy
+from pathlib import Path
+from typing import Dict, List, Optional, Tuple
+
+import hjson
+
+from reggen.ip_block import IpBlock
+
+# Ignore flake8 warning as the function is used in the template
+# disable isort formating, as conflicting with flake8
+from .intermodule import find_otherside_modules  # noqa : F401 # isort:skip
+from .intermodule import im_portname, im_defname, im_netname  # noqa : F401 # isort:skip
+from .intermodule import get_dangling_im_def # noqa : F401 # isort:skip
+
+
+class Name:
+    """
+    We often need to format names in specific ways; this class does so.
+
+    To simplify parsing and reassembling of name strings, this class
+    stores the name parts as a canonical list of strings internally
+    (in self.parts).
+
+    The "from_*" functions parse and split a name string into the canonical
+    list, whereas the "as_*" functions reassemble the canonical list in the
+    format specified.
+
+    For example, ex = Name.from_snake_case("example_name") gets split into
+    ["example", "name"] internally, and ex.as_camel_case() reassembles this
+    internal representation into "ExampleName".
+    """
+    def __add__(self, other):
+        return Name(self.parts + other.parts)
+
+    @staticmethod
+    def from_snake_case(input: str) -> 'Name':
+        return Name(input.split("_"))
+
+    def __init__(self, parts: List[str]):
+        self.parts = parts
+        for p in parts:
+            assert len(p) > 0, "cannot add zero-length name piece"
+
+    def as_snake_case(self) -> str:
+        return "_".join([p.lower() for p in self.parts])
+
+    def as_camel_case(self) -> str:
+        out = ""
+        for p in self.parts:
+            # If we're about to join two parts which would introduce adjacent
+            # numbers, put an underscore between them.
+            if out[-1:].isnumeric() and p[:1].isnumeric():
+                out += "_" + p
+            else:
+                out += p.capitalize()
+        return out
+
+    def as_c_define(self) -> str:
+        return "_".join([p.upper() for p in self.parts])
+
+    def as_c_enum(self) -> str:
+        return "k" + self.as_camel_case()
+
+    def as_c_type(self) -> str:
+        return self.as_snake_case() + "_t"
+
+    def remove_part(self, part_to_remove: str) -> "Name":
+        return Name([p for p in self.parts if p != part_to_remove])
+
+
+def is_ipcfg(ip: Path) -> bool:  # return bool
+    log.info("IP Path: %s" % repr(ip))
+    ip_name = ip.parents[1].name
+    hjson_name = ip.name
+
+    log.info("IP Name(%s) and HJSON name (%s)" % (ip_name, hjson_name))
+
+    if ip_name + ".hjson" == hjson_name or ip_name + "_reg.hjson" == hjson_name:
+        return True
+    return False
+
+
+def search_ips(ip_path):  # return list of config files
+    # list the every Hjson file
+    p = ip_path.glob('*/data/*.hjson')
+
+    # filter only ip_name/data/ip_name{_reg|''}.hjson
+    ips = [x for x in p if is_ipcfg(x)]
+
+    log.info("Filtered-in IP files: %s" % repr(ips))
+    return ips
+
+
+def is_xbarcfg(xbar_obj):
+    if "type" in xbar_obj and xbar_obj["type"] == "xbar":
+        return True
+
+    return False
+
+
+def get_hjsonobj_xbars(xbar_path):
+    """ Search crossbars Hjson files from given path.
+
+    Search every Hjson in the directory and check Hjson type.
+    It could be type: "top" or type: "xbar"
+    returns [(name, obj), ... ]
+    """
+    p = xbar_path.glob('*.hjson')
+    try:
+        xbar_objs = [
+            hjson.load(x.open('r'),
+                       use_decimal=True,
+                       object_pairs_hook=OrderedDict) for x in p
+        ]
+    except ValueError:
+        raise SystemExit(sys.exc_info()[1])
+
+    xbar_objs = [x for x in xbar_objs if is_xbarcfg(x)]
+
+    return xbar_objs
+
+
+def get_module_by_name(top, name):
+    """Search in top["module"] by name
+    """
+    module = None
+    for m in top["module"]:
+        if m["name"] == name:
+            module = m
+            break
+
+    return module
+
+
+def intersignal_to_signalname(top, m_name, s_name) -> str:
+
+    # TODO: Find the signal in the `inter_module_list` and get the correct signal name
+
+    return "{m_name}_{s_name}".format(m_name=m_name, s_name=s_name)
+
+
+def get_package_name_by_intermodule_signal(top, struct) -> str:
+    """Search inter-module signal package with the struct name
+
+    For instance, if `flash_ctrl` has inter-module signal package,
+    this function returns the package name
+    """
+    instances = top["module"] + top["memory"]
+
+    intermodule_instances = [
+        x["inter_signal_list"] for x in instances if "inter_signal_list" in x
+    ]
+
+    for m in intermodule_instances:
+        if m["name"] == struct and "package" in m:
+            return m["package"]
+    return ""
+
+
+def get_signal_by_name(module, name):
+    """Return the signal struct with the type input/output/inout
+    """
+    result = None
+    for s in module["available_input_list"] + module[
+            "available_output_list"] + module["available_inout_list"]:
+        if s["name"] == name:
+            result = s
+            break
+
+    return result
+
+
+def add_module_prefix_to_signal(signal, module):
+    """Add module prefix to module signal format { name: "sig_name", width: NN }
+    """
+    result = deepcopy(signal)
+
+    if "name" not in signal:
+        raise SystemExit("signal {} doesn't have name field".format(signal))
+
+    result["name"] = module + "_" + signal["name"]
+    result["module_name"] = module
+
+    return result
+
+
+def get_ms_name(name):
+    """Split module_name.signal_name to module_name , signal_name
+    """
+
+    tokens = name.split('.')
+
+    if len(tokens) == 0:
+        raise SystemExit("This to be catched in validate.py")
+
+    module = tokens[0]
+    signal = None
+    if len(tokens) == 2:
+        signal = tokens[1]
+
+    return module, signal
+
+
+def parse_pad_field(padstr):
+    """Parse PadName[NN...NN] or PadName[NN] or just PadName
+    """
+    match = re.match(r'^([A-Za-z0-9_]+)(\[([0-9]+)(\.\.([0-9]+))?\]|)', padstr)
+    return match.group(1), match.group(3), match.group(5)
+
+
+def get_pad_list(padstr):
+    pads = []
+
+    pad, first, last = parse_pad_field(padstr)
+    if first is None:
+        first = 0
+        last = 0
+    elif last is None:
+        last = first
+    first = int(first, 0)
+    last = int(last, 0)
+    # width = first - last + 1
+
+    for p in range(first, last + 1):
+        pads.append(OrderedDict([("name", pad), ("index", p)]))
+
+    return pads
+
+
+# Template functions
+def ljust(x, width):
+    return "{:<{width}}".format(x, width=width)
+
+
+def bitarray(d, width):
+    """Print Systemverilog bit array
+
+    @param d the bit width of the signal
+    @param width max character width of the signal group
+
+    For instance, if width is 4, the max d value in the signal group could be
+    9999. If d is 2, then this function pads 3 spaces at the end of the bit
+    slice.
+
+    "[1:0]   " <- d:=2, width=4
+    "[9999:0]" <- max d-1 value
+
+    If d is 1, it means array slice isn't necessary. So it returns empty spaces
+    """
+
+    if d <= 0:
+        log.error("lib.bitarray: Given value {} is smaller than 1".format(d))
+        raise ValueError
+    if d == 1:
+        return " " * (width + 4)  # [x:0] needs 4 more space than char_width
+
+    out = "[{}:0]".format(d - 1)
+    return out + (" " * (width - len(str(d))))
+
+
+def parameterize(text):
+    """Return the value wrapping with quote if not integer nor bits
+    """
+    if re.match(r'(\d+\'[hdb]\s*[0-9a-f_A-F]+|[0-9]+)', text) is None:
+        return "\"{}\"".format(text)
+
+    return text
+
+
+def index(i: int) -> str:
+    """Return index if it is not -1
+    """
+    return "[{}]".format(i) if i != -1 else ""
+
+
+def get_clk_name(clk):
+    """Return the appropriate clk name
+    """
+    if clk == 'main':
+        return 'clk_i'
+    else:
+        return "clk_{}_i".format(clk)
+
+
+def get_reset_path(reset, domain, reset_cfg):
+    """Return the appropriate reset path given name
+    """
+    # find matching node for reset
+    node_match = [node for node in reset_cfg['nodes'] if node['name'] == reset]
+    assert len(node_match) == 1
+    reset_type = node_match[0]['type']
+
+    # find matching path
+    hier_path = ""
+    if reset_type == "int":
+        log.debug("{} used as internal reset".format(reset["name"]))
+    else:
+        hier_path = reset_cfg['hier_paths'][reset_type]
+
+    # find domain selection
+    domain_sel = ''
+    if reset_type not in ["ext", "int"]:
+        domain_sel = "[rstmgr_pkg::Domain{}Sel]".format(domain)
+
+    reset_path = ""
+    if reset_type == "ext":
+        reset_path = reset
+    else:
+        reset_path = "{}rst_{}_n{}".format(hier_path, reset, domain_sel)
+
+    return reset_path
+
+
+def get_unused_resets(top):
+    """Return dict of unused resets and associated domain
+    """
+    unused_resets = OrderedDict()
+    unused_resets = {
+        reset['name']: domain
+        for reset in top['resets']['nodes']
+        for domain in top['power']['domains']
+        if reset['type'] == 'top' and domain not in reset['domains']
+    }
+
+    log.debug("Unused resets are {}".format(unused_resets))
+    return unused_resets
+
+
+def is_templated(module):
+    """Returns an indication where a particular module is templated
+    """
+    if "attr" not in module:
+        return False
+    elif module["attr"] in ["templated"]:
+        return True
+    else:
+        return False
+
+
+def is_top_reggen(module):
+    """Returns an indication where a particular module is NOT templated
+       and requires top level specific reggen
+    """
+    if "attr" not in module:
+        return False
+    elif module["attr"] in ["reggen_top", "reggen_only"]:
+        return True
+    else:
+        return False
+
+
+def is_inst(module):
+    """Returns an indication where a particular module should be instantiated
+       in the top level
+    """
+    top_level_module = False
+    top_level_mem = False
+
+    if "attr" not in module:
+        top_level_module = True
+    elif module["attr"] in ["normal", "templated", "reggen_top"]:
+        top_level_module = True
+    elif module["attr"] in ["reggen_only"]:
+        top_level_module = False
+    else:
+        raise ValueError('Attribute {} in {} is not valid'
+                         .format(module['attr'], module['name']))
+
+    if module['type'] in ['rom', 'ram_1p_scr', 'eflash']:
+        top_level_mem = True
+
+    return top_level_mem or top_level_module
+
+
+def get_base_and_size(name_to_block: Dict[str, IpBlock],
+                      inst: Dict[str, object],
+                      ifname: Optional[str]) -> Tuple[int, int]:
+    min_device_spacing = 0x1000
+
+    block = name_to_block.get(inst['type'])
+    if block is None:
+        # If inst isn't the instantiation of a block, it came from some memory.
+        # Memories have their sizes defined, so we can just look it up there.
+        bytes_used = int(inst['size'], 0)
+
+        # Memories don't have multiple or named interfaces, so this will only
+        # work if ifname is None.
+        assert ifname is None
+        base_addr = inst['base_addr']
+
+    else:
+        # If inst is the instantiation of some block, find the register block
+        # that corresponds to ifname
+        rb = block.reg_blocks.get(ifname)
+        if rb is None:
+            log.error('Cannot connect to non-existent {} device interface '
+                      'on {!r} (an instance of the {!r} block)'
+                      .format('default' if ifname is None else repr(ifname),
+                              inst['name'], block.name))
+            bytes_used = 0
+        else:
+            bytes_used = 1 << rb.get_addr_width()
+
+        base_addr = inst['base_addrs'][ifname]
+
+    # Round up to min_device_spacing if necessary
+    size_byte = max(bytes_used, min_device_spacing)
+
+    if isinstance(base_addr, str):
+        base_addr = int(base_addr, 0)
+    else:
+        assert isinstance(base_addr, int)
+
+    return (base_addr, size_byte)
+
+
+def get_io_enum_literal(sig: Dict, prefix: str) -> str:
+    """Returns the DIO pin enum literal with value assignment"""
+    name = Name.from_snake_case(prefix) + Name.from_snake_case(sig["name"])
+    # In this case, the signal is a multibit signal, and hence
+    # we have to make the signal index part of the parameter
+    # name to uniquify it.
+    if sig['width'] > 1:
+        name += Name([str(sig['idx'])])
+    return name.as_camel_case()
+
+
+def make_bit_concatenation(sig_name: str,
+                           indices: List[int],
+                           end_indent: int) -> str:
+    '''Return SV code for concatenating certain indices from a signal
+
+    sig_name is the name of the signal and indices is a non-empty list of the
+    indices to use, MSB first. So
+
+      make_bit_concatenation("foo", [0, 100, 20])
+
+    should give
+
+      {foo[0], foo[100], foo[20]}
+
+    Adjacent bits turn into a range select. For example:
+
+      make_bit_concatenation("foo", [0, 1, 2])
+
+    should give
+
+      foo[0:2]
+
+    If there are multiple ranges, they are printed one to a line. end_indent
+    gives the indentation of the closing brace and the range selects in between
+    get indented to end_indent + 2.
+
+    '''
+    assert 0 <= end_indent
+
+    ranges = []
+    cur_range_start = indices[0]
+    cur_range_end = indices[0]
+    for idx in indices[1:]:
+        if idx == cur_range_end + 1 and cur_range_start <= cur_range_end:
+            cur_range_end += 1
+            continue
+        if idx == cur_range_end - 1 and cur_range_start >= cur_range_end:
+            cur_range_end -= 1
+            continue
+        ranges.append((cur_range_start, cur_range_end))
+        cur_range_start = idx
+        cur_range_end = idx
+    ranges.append((cur_range_start, cur_range_end))
+
+    items = []
+    for range_start, range_end in ranges:
+        if range_start == range_end:
+            select = str(range_start)
+        else:
+            select = '{}:{}'.format(range_start, range_end)
+        items.append('{}[{}]'.format(sig_name, select))
+
+    if len(items) == 1:
+        return items[0]
+
+    item_indent = '\n' + (' ' * (end_indent + 2))
+
+    acc = ['{', item_indent, items[0]]
+    for item in items[1:]:
+        acc += [',', item_indent, item]
+    acc += ['\n', ' ' * end_indent, '}']
+    return ''.join(acc)
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/merge.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/merge.py
new file mode 100644
index 00000000..6c0a9cd4
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/merge.py
@@ -0,0 +1,1081 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+import logging as log
+import random
+from collections import OrderedDict
+from copy import deepcopy
+from math import ceil, log2
+from typing import Dict, List
+
+from topgen import c, lib
+from reggen.ip_block import IpBlock
+from reggen.params import LocalParam, Parameter, RandParameter
+
+
+def _get_random_data_hex_literal(width):
+    """ Fetch 'width' random bits and return them as hex literal"""
+    width = int(width)
+    literal_str = hex(random.getrandbits(width))
+    return literal_str
+
+
+def _get_random_perm_hex_literal(numel):
+    """ Compute a random permutation of 'numel' elements and
+    return as packed hex literal"""
+    num_elements = int(numel)
+    width = int(ceil(log2(num_elements)))
+    idx = [x for x in range(num_elements)]
+    random.shuffle(idx)
+    literal_str = ""
+    for k in idx:
+        literal_str += format(k, '0' + str(width) + 'b')
+    # convert to hex for space efficiency
+    literal_str = hex(int(literal_str, 2))
+    return literal_str
+
+
+def elaborate_instances(top, name_to_block: Dict[str, IpBlock]):
+    '''Add additional fields to the elements of top['module']
+
+    These elements represent instantiations of IP blocks. This function adds
+    extra fields to them to carry across information from the IpBlock objects
+    that represent the blocks being instantiated. See elaborate_instance for
+    more details of what gets added.
+
+    '''
+    # Initialize RNG for compile-time netlist constants.
+    random.seed(int(top['rnd_cnst_seed']))
+
+    for instance in top['module']:
+        block = name_to_block[instance['type']]
+        elaborate_instance(instance, block)
+
+
+def elaborate_instance(instance, block: IpBlock):
+    """Add additional fields to a single instance of a module.
+
+    instance is the instance to be filled in. block is the block that it's
+    instantiating.
+
+    Altered fields:
+        - param_list (list of parameters for the instance)
+        - inter_signal_list (list of inter-module signals)
+        - base_addrs (a map from interface name to its base address)
+
+    Removed fields:
+        - base_addr (this is reflected in base_addrs)
+
+    """
+    mod_name = instance["name"]
+
+    # param_list
+    new_params = []
+    for param in block.params.by_name.values():
+        if isinstance(param, LocalParam):
+            # Remove local parameters.
+            continue
+
+        new_param = param.as_dict()
+
+        param_expose = param.expose if isinstance(param, Parameter) else False
+
+        # Check for security-relevant parameters that are not exposed,
+        # adding a top-level name.
+        if param.name.lower().startswith("sec") and not param_expose:
+            log.warning("{} has security-critical parameter {} "
+                        "not exposed to top".format(
+                            mod_name, param.name))
+
+        # Move special prefixes to the beginnining of the parameter name.
+        param_prefixes = ["Sec", "RndCnst"]
+        cc_mod_name = c.Name.from_snake_case(mod_name).as_camel_case()
+        name_top = cc_mod_name + param.name
+        for prefix in param_prefixes:
+            if param.name.lower().startswith(prefix.lower()):
+                name_top = (prefix + cc_mod_name +
+                            param.name[len(prefix):])
+                break
+
+        new_param['name_top'] = name_top
+
+        # Generate random bits or permutation, if needed
+        if isinstance(param, RandParameter):
+            if param.randtype == 'data':
+                new_default = _get_random_data_hex_literal(param.randcount)
+                # Effective width of the random vector
+                randwidth = param.randcount
+            else:
+                assert param.randtype == 'perm'
+                new_default = _get_random_perm_hex_literal(param.randcount)
+                # Effective width of the random vector
+                randwidth = param.randcount * ceil(log2(param.randcount))
+
+            new_param['default'] = new_default
+            new_param['randwidth'] = randwidth
+
+        new_params.append(new_param)
+
+    instance["param_list"] = new_params
+
+    # These objects get added-to in place by code in intermodule.py, so we have
+    # to convert and copy them here.
+    instance["inter_signal_list"] = [s.as_dict() for s in block.inter_signals]
+
+    # An instance must either have a 'base_addr' address or a 'base_addrs'
+    # address, but can't have both.
+    base_addrs = instance.get('base_addrs')
+    if base_addrs is None:
+        if 'base_addr' not in instance:
+            log.error('Instance {!r} has neither a base_addr '
+                      'nor a base_addrs field.'
+                      .format(instance['name']))
+        else:
+            # If the instance has a base_addr field, make sure that the block
+            # has just one device interface.
+            if len(block.reg_blocks) != 1:
+                log.error('Instance {!r} has a base_addr field but it '
+                          'instantiates the block {!r}, which has {} '
+                          'device interfaces.'
+                          .format(instance['name'],
+                                  block.name, len(block.reg_blocks)))
+            else:
+                if_name = next(iter(block.reg_blocks))
+                base_addrs = {if_name: instance['base_addr']}
+
+        # Fill in a bogus base address (we don't have proper error handling, so
+        # have to do *something*)
+        if base_addrs is None:
+            base_addrs = {None: 0}
+
+        instance['base_addrs'] = base_addrs
+    else:
+        if 'base_addr' in instance:
+            log.error('Instance {!r} has both a base_addr '
+                      'and a base_addrs field.'
+                      .format(instance['name']))
+
+        # Since the instance already has a base_addrs field, make sure that
+        # it's got the same set of keys as the name of the interfaces in the
+        # block.
+        inst_if_names = set(base_addrs.keys())
+        block_if_names = set(block.reg_blocks.keys())
+        if block_if_names != inst_if_names:
+            log.error('Instance {!r} has a base_addrs field with keys {} '
+                      'but the block it instantiates ({!r}) has device '
+                      'interfaces {}.'
+                      .format(instance['name'], inst_if_names,
+                              block.name, block_if_names))
+
+    if 'base_addr' in instance:
+        del instance['base_addr']
+
+
+# TODO: Replace this part to be configurable from Hjson or template
+predefined_modules = {
+    "corei": "rv_core_ibex",
+    "cored": "rv_core_ibex",
+    "dm_sba": "rv_dm",
+    "debug_mem": "rv_dm"
+}
+
+
+def is_xbar(top, name):
+    """Check if the given name is crossbar
+    """
+    xbars = list(filter(lambda node: node["name"] == name, top["xbar"]))
+    if len(xbars) == 0:
+        return False, None
+
+    if len(xbars) > 1:
+        log.error("Matching crossbar {} is more than one.".format(name))
+        raise SystemExit()
+
+    return True, xbars[0]
+
+
+def xbar_addhost(top, xbar, host):
+    """Add host nodes information
+
+    - xbar: bool, true if the host port is from another Xbar
+    """
+    # Check and fetch host if exists in nodes
+    obj = list(filter(lambda node: node["name"] == host, xbar["nodes"]))
+    if len(obj) == 0:
+        log.warning(
+            "host %s doesn't exist in the node list. Using default values" %
+            host)
+        obj = OrderedDict([
+            ("name", host),
+            ("clock", xbar['clock']),
+            ("reset", xbar['reset']),
+            ("type", "host"),
+            ("inst_type", ""),
+            ("stub", False),
+            # The default matches RTL default
+            # pipeline_byp is don't care if pipeline is false
+            ("pipeline", "true"),
+            ("pipeline_byp", "true")
+        ])
+        xbar["nodes"].append(obj)
+        return
+
+    xbar_bool, xbar_h = is_xbar(top, host)
+    if xbar_bool:
+        log.info("host {} is a crossbar. Nothing to deal with.".format(host))
+
+    obj[0]["xbar"] = xbar_bool
+
+    if 'clock' not in obj[0]:
+        obj[0]["clock"] = xbar['clock']
+
+    if 'reset' not in obj[0]:
+        obj[0]["reset"] = xbar["reset"]
+
+    obj[0]["stub"] = False
+    obj[0]["inst_type"] = predefined_modules[
+        host] if host in predefined_modules else ""
+    obj[0]["pipeline"] = obj[0]["pipeline"] if "pipeline" in obj[0] else "true"
+    obj[0]["pipeline_byp"] = obj[0]["pipeline_byp"] if obj[0][
+        "pipeline"] == "true" and "pipeline_byp" in obj[0] else "true"
+
+
+def process_pipeline_var(node):
+    """Add device nodes pipeline / pipeline_byp information
+
+    - Supply a default of true / true if not defined by xbar
+    """
+    node["pipeline"] = node["pipeline"] if "pipeline" in node else "true"
+    node["pipeline_byp"] = node[
+        "pipeline_byp"] if "pipeline_byp" in node else "true"
+
+
+def xbar_adddevice(top: Dict[str, object],
+                   name_to_block: Dict[str, IpBlock],
+                   xbar: Dict[str, object],
+                   other_xbars: List[str],
+                   device: str) -> None:
+    """Add or amend an entry in xbar['nodes'] to represent the device interface
+
+    - clock: comes from module if exist, use xbar default otherwise
+    - reset: comes from module if exist, use xbar default otherwise
+    - inst_type: comes from module or memory if exist.
+    - base_addr: comes from module or memory, or assume rv_plic?
+    - size_byte: comes from module or memory
+    - xbar: bool, true if the device port is another xbar
+    - stub: There is no backing module / memory, instead a tlul port
+            is created and forwarded above the current hierarchy
+    """
+    device_parts = device.split('.', 1)
+    device_base = device_parts[0]
+    device_ifname = device_parts[1] if len(device_parts) > 1 else None
+
+    # Try to find a block or memory instance with name device_base. Object
+    # names should be unique, so there should never be more than one hit.
+    instances = [
+        node for node in top["module"] + top["memory"]
+        if node['name'] == device_base
+    ]
+    assert len(instances) <= 1
+    inst = instances[0] if instances else None
+
+    # Try to find a node in the crossbar called device. Node names should be
+    # unique, so there should never be more than one hit.
+    nodes = [
+        node for node in xbar['nodes']
+        if node['name'] == device
+    ]
+    assert len(nodes) <= 1
+    node = nodes[0] if nodes else None
+
+    log.info("Handling xbar device {} (matches instance? {}; matches node? {})"
+             .format(device, inst is not None, node is not None))
+
+    # case 1: another xbar --> check in xbar list
+    if node is None and device in other_xbars:
+        log.error(
+            "Another crossbar %s needs to be specified in the 'nodes' list" %
+            device)
+        return
+
+    # If there is no module or memory with the right name, this might still be
+    # ok: we might be connecting to another crossbar or to a predefined module.
+    if inst is None:
+        # case 1: Crossbar handling
+        if device in other_xbars:
+            log.info(
+                "device {} in Xbar {} is connected to another Xbar".format(
+                    device, xbar["name"]))
+            assert node is not None
+            node["xbar"] = True
+            node["stub"] = False
+            process_pipeline_var(node)
+            return
+
+        # case 2: predefined_modules (debug_mem, rv_plic)
+        # TODO: Find configurable solution not from predefined but from object?
+        if device in predefined_modules:
+            if device == "debug_mem":
+                if node is None:
+                    # Add new debug_mem
+                    xbar["nodes"].append({
+                        "name": "debug_mem",
+                        "type": "device",
+                        "clock": xbar['clock'],
+                        "reset": xbar['reset'],
+                        "inst_type": predefined_modules["debug_mem"],
+                        "addr_range": [OrderedDict([
+                            ("base_addr", top["debug_mem_base_addr"]),
+                            ("size_byte", "0x1000"),
+                        ])],
+                        "xbar": False,
+                        "stub": False,
+                        "pipeline": "true",
+                        "pipeline_byp": "true"
+                    })  # yapf: disable
+                else:
+                    # Update if exists
+                    node["inst_type"] = predefined_modules["debug_mem"]
+                    node["addr_range"] = [
+                        OrderedDict([("base_addr", top["debug_mem_base_addr"]),
+                                     ("size_byte", "0x1000")])
+                    ]
+                    node["xbar"] = False
+                    node["stub"] = False
+                    process_pipeline_var(node)
+            else:
+                log.error("device %s shouldn't be host type" % device)
+
+            return
+
+        # case 3: not defined
+        # Crossbar check
+        log.error("Device %s doesn't exist in 'module', 'memory', predefined, "
+                  "or as a node object" % device)
+        return
+
+    # If we get here, inst points an instance of some block or memory. It
+    # shouldn't point at a crossbar (because that would imply a naming clash)
+    assert device_base not in other_xbars
+    base_addr, size_byte = lib.get_base_and_size(name_to_block,
+                                                 inst, device_ifname)
+    addr_range = {"base_addr": hex(base_addr), "size_byte": hex(size_byte)}
+
+    stub = not lib.is_inst(inst)
+
+    if node is None:
+        log.error('Cannot connect to {!r} because '
+                  'the crossbar defines no node for {!r}.'
+                  .format(device, device_base))
+        return
+
+    node["inst_type"] = inst["type"]
+    node["addr_range"] = [addr_range]
+    node["xbar"] = False
+    node["stub"] = stub
+    process_pipeline_var(node)
+
+
+def amend_xbar(top: Dict[str, object],
+               name_to_block: Dict[str, IpBlock],
+               xbar: Dict[str, object]):
+    """Amend crossbar informations to the top list
+
+    Amended fields
+    - clock: Adopt from module clock if exists
+    - inst_type: Module instance some module will be hard-coded
+                 the tool searches module list and memory list then put here
+    - base_addr: from top["module"]
+    - size: from top["module"]
+    """
+    xbar_list = [x["name"] for x in top["xbar"]]
+    if not xbar["name"] in xbar_list:
+        log.info(
+            "Xbar %s doesn't belong to the top %s. Check if the xbar doesn't need"
+            % (xbar["name"], top["name"]))
+        return
+
+    topxbar = list(
+        filter(lambda node: node["name"] == xbar["name"], top["xbar"]))[0]
+
+    topxbar["connections"] = deepcopy(xbar["connections"])
+    if "nodes" in xbar:
+        topxbar["nodes"] = deepcopy(xbar["nodes"])
+    else:
+        topxbar["nodes"] = []
+
+    # xbar primary clock and reset
+    topxbar["clock"] = xbar["clock_primary"]
+    topxbar["reset"] = xbar["reset_primary"]
+
+    # Build nodes from 'connections'
+    device_nodes = set()
+    for host, devices in xbar["connections"].items():
+        # add host first
+        xbar_addhost(top, topxbar, host)
+
+        # add device if doesn't exist
+        device_nodes.update(devices)
+
+    other_xbars = [x["name"]
+                   for x in top["xbar"]
+                   if x["name"] != xbar["name"]]
+
+    log.info(device_nodes)
+    for device in device_nodes:
+        xbar_adddevice(top, name_to_block, topxbar, other_xbars, device)
+
+
+def xbar_cross(xbar, xbars):
+    """Check if cyclic dependency among xbars
+
+    And gather the address range for device port (to another Xbar)
+
+    @param node_name if not "", the function only search downstream
+                     devices starting from the node_name
+    @param visited   The nodes it visited to reach this port. If any
+                     downstream port from node_name in visited, it means
+                     circular path exists. It should be fatal error.
+    """
+    # Step 1: Visit devices (gather the address range)
+    log.info("Processing circular path check for {}".format(xbar["name"]))
+    addr = []
+    for node in [
+            x for x in xbar["nodes"]
+            if x["type"] == "device" and "xbar" in x and x["xbar"] is False
+    ]:
+        addr.extend(node["addr_range"])
+
+    # Step 2: visit xbar device ports
+    xbar_nodes = [
+        x for x in xbar["nodes"]
+        if x["type"] == "device" and "xbar" in x and x["xbar"] is True
+    ]
+
+    # Now call function to get the device range
+    # the node["name"] is used to find the host_xbar and its connection. The
+    # assumption here is that there's only one connection from crossbar A to
+    # crossbar B.
+    #
+    # device_xbar is the crossbar has a device port with name as node["name"].
+    # host_xbar is the crossbar has a host port with name as node["name"].
+    for node in xbar_nodes:
+        xbar_addr = xbar_cross_node(node["name"], xbar, xbars, visited=[])
+        node["addr_range"] = xbar_addr
+
+
+def xbar_cross_node(node_name, device_xbar, xbars, visited=[]):
+    # 1. Get the connected xbar
+    host_xbars = [x for x in xbars if x["name"] == node_name]
+    assert len(host_xbars) == 1
+    host_xbar = host_xbars[0]
+
+    log.info("Processing node {} in Xbar {}.".format(node_name,
+                                                     device_xbar["name"]))
+    result = []  # [(base_addr, size), .. ]
+    # Sweep the devices using connections and gather the address.
+    # If the device is another xbar, call recursive
+    visited.append(host_xbar["name"])
+    devices = host_xbar["connections"][device_xbar["name"]]
+
+    for node in host_xbar["nodes"]:
+        if not node["name"] in devices:
+            continue
+        if "xbar" in node and node["xbar"] is True:
+            if "addr_range" not in node:
+                # Deeper dive into another crossbar
+                xbar_addr = xbar_cross_node(node["name"], host_xbar, xbars,
+                                            visited)
+                node["addr_range"] = xbar_addr
+
+        result.extend(deepcopy(node["addr_range"]))
+
+    visited.pop()
+
+    return result
+
+
+# find the first instance name of a given type
+def _find_module_name(modules, module_type):
+    for m in modules:
+        if m['type'] == module_type:
+            return m['name']
+
+    return None
+
+
+def amend_clocks(top: OrderedDict):
+    """Add a list of clocks to each clock group
+       Amend the clock connections of each entry to reflect the actual gated clock
+    """
+    clks_attr = top['clocks']
+    clk_paths = clks_attr['hier_paths']
+    clkmgr_name = _find_module_name(top['module'], 'clkmgr')
+    groups_in_top = [x["name"].lower() for x in clks_attr['groups']]
+    exported_clks = OrderedDict()
+    trans_eps = []
+
+    # Assign default parameters to source clocks
+    for src in clks_attr['srcs']:
+        if 'derived' not in src:
+            src['derived'] = "no"
+            src['params'] = OrderedDict()
+
+    # Default assignments
+    for group in clks_attr['groups']:
+
+        # if unique not defined, it defaults to 'no'
+        if 'unique' not in group:
+            group['unique'] = "no"
+
+        # if no hardwired clocks, define an empty set
+        group['clocks'] = OrderedDict(
+        ) if 'clocks' not in group else group['clocks']
+
+    for ep in top['module'] + top['memory'] + top['xbar']:
+
+        clock_connections = OrderedDict()
+
+        # Ensure each module has a default case
+        export_if = ep.get('clock_reset_export', [])
+
+        # if no clock group assigned, default is unique
+        ep['clock_group'] = 'secure' if 'clock_group' not in ep else ep[
+            'clock_group']
+        ep_grp = ep['clock_group']
+
+        # if ep is in the transactional group, collect into list below
+        if ep['clock_group'] == 'trans':
+            trans_eps.append(ep['name'])
+
+        # end point names and clocks
+        ep_name = ep['name']
+        ep_clks = []
+
+        # clock group index
+        cg_idx = groups_in_top.index(ep_grp)
+
+        # unique property of each group
+        unique = clks_attr['groups'][cg_idx]['unique']
+
+        # src property of each group
+        src = clks_attr['groups'][cg_idx]['src']
+
+        for port, clk in ep['clock_srcs'].items():
+            ep_clks.append(clk)
+
+            name = ''
+            hier_name = clk_paths[src]
+
+            if src == 'ext':
+                # clock comes from top ports
+                if clk == 'main':
+                    name = "i"
+                else:
+                    name = "{}_i".format(clk)
+
+            elif unique == "yes":
+                # new unqiue clock name
+                name = "{}_{}".format(clk, ep_name)
+
+            else:
+                # new group clock name
+                name = "{}_{}".format(clk, ep_grp)
+
+            clk_name = "clk_" + name
+
+            # add clock to a particular group
+            clks_attr['groups'][cg_idx]['clocks'][clk_name] = clk
+
+            # add clock connections
+            clock_connections[port] = hier_name + clk_name
+
+            # clocks for this module are exported
+            for intf in export_if:
+                log.info("{} export clock name is {}".format(ep_name, name))
+
+                # create dict entry if it does not exit
+                if intf not in exported_clks:
+                    exported_clks[intf] = OrderedDict()
+
+                # if first time encounter end point, declare
+                if ep_name not in exported_clks[intf]:
+                    exported_clks[intf][ep_name] = []
+
+                # append clocks
+                exported_clks[intf][ep_name].append(name)
+
+        # Add to endpoint structure
+        ep['clock_connections'] = clock_connections
+
+    # add entry to top level json
+    top['exported_clks'] = exported_clks
+
+    # add entry to inter_module automatically
+    for intf in top['exported_clks']:
+        top['inter_module']['external']['{}.clocks_{}'.format(
+            clkmgr_name, intf)] = "clks_{}".format(intf)
+
+    # add to intermodule connections
+    for ep in trans_eps:
+        entry = ep + ".idle"
+        top['inter_module']['connect']['{}.idle'.format(clkmgr_name)].append(entry)
+
+
+def amend_resets(top):
+    """Generate exported reset structure and automatically connect to
+       intermodule.
+    """
+
+    rstmgr_name = _find_module_name(top['module'], 'rstmgr')
+
+    # Generate exported reset list
+    exported_rsts = OrderedDict()
+    for module in top["module"]:
+
+        # This code is here to ensure if amend_clocks/resets switched order
+        # everything would still work
+        export_if = module.get('clock_reset_export', [])
+
+        # There may be multiple export interfaces
+        for intf in export_if:
+            # create dict entry if it does not exit
+            if intf not in exported_rsts:
+                exported_rsts[intf] = OrderedDict()
+
+            # grab directly from reset_connections definition
+            rsts = [rst for rst in module['reset_connections'].values()]
+            exported_rsts[intf][module['name']] = rsts
+
+    # add entry to top level json
+    top['exported_rsts'] = exported_rsts
+
+    # add entry to inter_module automatically
+    for intf in top['exported_rsts']:
+        top['inter_module']['external']['{}.resets_{}'.format(
+            rstmgr_name, intf)] = "rsts_{}".format(intf)
+    """Discover the full path and selection to each reset connection.
+       This is done by modifying the reset connection of each end point.
+    """
+    for end_point in top['module'] + top['memory'] + top['xbar']:
+        for port, net in end_point['reset_connections'].items():
+            reset_path = lib.get_reset_path(net, end_point['domain'],
+                                            top['resets'])
+            end_point['reset_connections'][port] = reset_path
+
+    # reset paths are still needed temporarily until host only modules are properly automated
+    reset_paths = OrderedDict()
+    reset_hiers = top["resets"]['hier_paths']
+
+    for reset in top["resets"]["nodes"]:
+        if "type" not in reset:
+            log.error("{} missing type field".format(reset["name"]))
+            return
+
+        if reset["type"] == "top":
+            reset_paths[reset["name"]] = "{}rst_{}_n".format(
+                reset_hiers["top"], reset["name"])
+
+        elif reset["type"] == "ext":
+            reset_paths[reset["name"]] = reset_hiers["ext"] + reset['name']
+        elif reset["type"] == "int":
+            log.info("{} used as internal reset".format(reset["name"]))
+        else:
+            log.error("{} type is invalid".format(reset["type"]))
+
+    top["reset_paths"] = reset_paths
+
+    return
+
+
+def ensure_interrupt_modules(top: OrderedDict, name_to_block: Dict[str, IpBlock]):
+    '''Populate top['interrupt_module'] if necessary
+
+    Do this by adding each module in top['modules'] that defines at least one
+    interrupt.
+
+    '''
+    if 'interrupt_module' in top:
+        return
+
+    modules = []
+    for module in top['module']:
+        block = name_to_block[module['type']]
+        if block.interrupts:
+            modules.append(module['name'])
+
+    top['interrupt_module'] = modules
+
+
+def amend_interrupt(top: OrderedDict, name_to_block: Dict[str, IpBlock]):
+    """Check interrupt_module if exists, or just use all modules
+    """
+    ensure_interrupt_modules(top, name_to_block)
+
+    if "interrupt" not in top or top["interrupt"] == "":
+        top["interrupt"] = []
+
+    for m in top["interrupt_module"]:
+        ips = list(filter(lambda module: module["name"] == m, top["module"]))
+        if len(ips) == 0:
+            log.warning(
+                "Cannot find IP %s which is used in the interrupt_module" % m)
+            continue
+
+        ip = ips[0]
+        block = name_to_block[ip['type']]
+
+        log.info("Adding interrupts from module %s" % ip["name"])
+        for signal in block.interrupts:
+            sig_dict = signal.as_nwt_dict('interrupt')
+            qual = lib.add_module_prefix_to_signal(sig_dict,
+                                                   module=m.lower())
+            top["interrupt"].append(qual)
+
+
+def ensure_alert_modules(top: OrderedDict, name_to_block: Dict[str, IpBlock]):
+    '''Populate top['alert_module'] if necessary
+
+    Do this by adding each module in top['modules'] that defines at least one
+    alert.
+
+    '''
+    if 'alert_module' in top:
+        return
+
+    modules = []
+    for module in top['module']:
+        block = name_to_block[module['type']]
+        if block.alerts:
+            modules.append(module['name'])
+
+    top['alert_module'] = modules
+
+
+def amend_alert(top: OrderedDict, name_to_block: Dict[str, IpBlock]):
+    """Check interrupt_module if exists, or just use all modules
+    """
+    ensure_alert_modules(top, name_to_block)
+
+    if "alert" not in top or top["alert"] == "":
+        top["alert"] = []
+
+    # Find the alert handler and extract the name of its clock
+    alert_clock = None
+    for instance in top['module']:
+        if instance['type'].lower() == 'alert_handler':
+            alert_clock = instance['clock_srcs']['clk_i']
+            break
+    assert alert_clock is not None
+
+    for m in top["alert_module"]:
+        ips = list(filter(lambda module: module["name"] == m, top["module"]))
+        if len(ips) == 0:
+            log.warning("Cannot find IP %s which is used in the alert_module" %
+                        m)
+            continue
+
+        ip = ips[0]
+        block = name_to_block[ip['type']]
+
+        log.info("Adding alert from module %s" % ip["name"])
+        has_async_alerts = ip['clock_srcs']['clk_i'] != alert_clock
+        for alert in block.alerts:
+            alert_dict = alert.as_nwt_dict('alert')
+            alert_dict['async'] = '1' if has_async_alerts else '0'
+            qual_sig = lib.add_module_prefix_to_signal(alert_dict,
+                                                       module=m.lower())
+            top["alert"].append(qual_sig)
+
+
+def amend_wkup(topcfg: OrderedDict, name_to_block: Dict[str, IpBlock]):
+
+    pwrmgr_name = _find_module_name(topcfg['module'], 'pwrmgr')
+
+    if "wakeups" not in topcfg or topcfg["wakeups"] == "":
+        topcfg["wakeups"] = []
+
+    # create list of wakeup signals
+    for m in topcfg["module"]:
+        log.info("Adding wakeup from module %s" % m["name"])
+        block = name_to_block[m['type']]
+        for signal in block.wakeups:
+            log.info("Adding signal %s" % signal.name)
+            topcfg["wakeups"].append({
+                'name': signal.name,
+                'width': str(signal.bits.width()),
+                'module': m["name"]
+            })
+
+    # add wakeup signals to pwrmgr connections
+    signal_names = [
+        "{}.{}".format(s["module"].lower(), s["name"].lower())
+        for s in topcfg["wakeups"]
+    ]
+
+    topcfg["inter_module"]["connect"]["{}.wakeups".format(pwrmgr_name)] = signal_names
+    log.info("Intermodule signals: {}".format(
+        topcfg["inter_module"]["connect"]))
+
+
+# Handle reset requests from modules
+def amend_reset_request(topcfg: OrderedDict,
+                        name_to_block: Dict[str, IpBlock]):
+
+    pwrmgr_name = _find_module_name(topcfg['module'], 'pwrmgr')
+
+    if "reset_requests" not in topcfg or topcfg["reset_requests"] == "":
+        topcfg["reset_requests"] = []
+
+    # create list of reset signals
+    for m in topcfg["module"]:
+        log.info("Adding reset requests from module %s" % m["name"])
+        block = name_to_block[m['type']]
+        for signal in block.reset_requests:
+            log.info("Adding signal %s" % signal.name)
+            topcfg["reset_requests"].append({
+                'name': signal.name,
+                'width': str(signal.bits.width()),
+                'module': m["name"]
+            })
+
+    # add reset requests to pwrmgr connections
+    signal_names = [
+        "{}.{}".format(s["module"].lower(), s["name"].lower())
+        for s in topcfg["reset_requests"]
+    ]
+
+    topcfg["inter_module"]["connect"]["{}.rstreqs".format(pwrmgr_name)] = signal_names
+    log.info("Intermodule signals: {}".format(
+        topcfg["inter_module"]["connect"]))
+
+
+def append_io_signal(temp: Dict, sig_inst: Dict) -> None:
+    '''Appends the signal to the correct list'''
+    if sig_inst['type'] == 'inout':
+        temp['inouts'].append(sig_inst)
+    if sig_inst['type'] == 'input':
+        temp['inputs'].append(sig_inst)
+    if sig_inst['type'] == 'output':
+        temp['outputs'].append(sig_inst)
+
+
+def get_index_and_incr(ctrs: Dict, connection: str, io_dir: str) -> Dict:
+    '''Get correct index counter and increment'''
+
+    if connection != 'muxed':
+        connection = 'dedicated'
+
+    if io_dir in 'inout':
+        result = ctrs[connection]['inouts']
+        ctrs[connection]['inouts'] += 1
+    elif connection == 'muxed':
+        # For MIOs, the input/output arrays differ in RTL
+        # I.e., the input array contains {inputs, inouts}, whereas
+        # the output array contains {outputs, inouts}.
+        if io_dir == 'input':
+            result = ctrs[connection]['inputs'] + ctrs[connection]['inouts']
+            ctrs[connection]['inputs'] += 1
+        elif io_dir == 'output':
+            result = ctrs[connection]['outputs'] + ctrs[connection]['inouts']
+            ctrs[connection]['outputs'] += 1
+        else:
+            assert(0)  # should not happen
+    else:
+        # For DIOs, the input/output arrays are identical in terms of index layout.
+        # Unused inputs are left unconnected and unused outputs are tied off.
+        if io_dir == 'input':
+            result = ctrs[connection]['inputs'] + ctrs[connection]['inouts']
+            ctrs[connection]['inputs'] += 1
+        elif io_dir == 'output':
+            result = (ctrs[connection]['outputs'] +
+                      ctrs[connection]['inouts'] +
+                      ctrs[connection]['inputs'])
+            ctrs[connection]['outputs'] += 1
+        else:
+            assert(0)  # should not happen
+
+    return result
+
+
+def amend_pinmux_io(top: Dict, name_to_block: Dict[str, IpBlock]):
+    """ Process pinmux/pinout configuration and assign available IOs
+    """
+    pinmux = top['pinmux']
+    pinout = top['pinout']
+    targets = top['targets']
+
+    temp = {}
+    temp['inouts'] = []
+    temp['inputs'] = []
+    temp['outputs'] = []
+
+    for sig in pinmux['signals']:
+        # Get the signal information from the IP block type of this instance/
+        mod_name = sig['instance']
+        m = lib.get_module_by_name(top, mod_name)
+
+        if m is None:
+            raise SystemExit("Module {} is not searchable.".format(mod_name))
+
+        block = name_to_block[m['type']]
+
+        # If the signal is explicitly named.
+        if sig['port'] != '':
+
+            # If this is a bus signal with explicit indexes.
+            if '[' in sig['port']:
+                name_split = sig['port'].split('[')
+                sig_name = name_split[0]
+                idx = int(name_split[1][:-1])
+            else:
+                idx = -1
+                sig_name = sig['port']
+
+            sig_inst = deepcopy(block.get_signal_by_name_as_dict(sig_name))
+
+            if idx >= 0 and idx >= sig_inst['width']:
+                raise SystemExit("Index {} is out of bounds for signal {}"
+                                 " with width {}.".format(idx, sig_name, sig_inst['width']))
+            if idx == -1 and sig_inst['width'] != 1:
+                raise SystemExit("Bus signal {} requires an index.".format(sig_name))
+
+            # If we got this far we know that the signal is valid and exists.
+            # Augment this signal instance with additional information.
+            sig_inst.update({'idx': idx,
+                             'pad': sig['pad'],
+                             'attr': sig['attr'],
+                             'connection': sig['connection']})
+            sig_inst['name'] = mod_name + '_' + sig_inst['name']
+            append_io_signal(temp, sig_inst)
+
+        # Otherwise the name is a wildcard for selecting all available IO signals
+        # of this block and we need to extract them here one by one signals here.
+        else:
+            sig_list = deepcopy(block.get_signals_as_list_of_dicts())
+
+            for sig_inst in sig_list:
+                # If this is a multibit signal, unroll the bus and
+                # generate a single bit IO signal entry for each one.
+                if sig_inst['width'] > 1:
+                    for idx in range(sig_inst['width']):
+                        sig_inst_copy = deepcopy(sig_inst)
+                        sig_inst_copy.update({'idx': idx,
+                                              'pad': sig['pad'],
+                                              'attr': sig['attr'],
+                                              'connection': sig['connection']})
+                        sig_inst_copy['name'] = sig['instance'] + '_' + sig_inst_copy['name']
+                        append_io_signal(temp, sig_inst_copy)
+                else:
+                    sig_inst.update({'idx': -1,
+                                     'pad': sig['pad'],
+                                     'attr': sig['attr'],
+                                     'connection': sig['connection']})
+                    sig_inst['name'] = sig['instance'] + '_' + sig_inst['name']
+                    append_io_signal(temp, sig_inst)
+
+    # Now that we've collected all input and output signals,
+    # we can go through once again and stack them into one unified
+    # list, and calculate MIO/DIO global indices.
+    pinmux['ios'] = (temp['inouts'] +
+                     temp['inputs'] +
+                     temp['outputs'])
+
+    # Remember these counts to facilitate the RTL generation
+    pinmux['io_counts'] = {'dedicated': {'inouts': 0, 'inputs': 0, 'outputs': 0, 'pads': 0},
+                           'muxed': {'inouts': 0, 'inputs': 0, 'outputs': 0, 'pads': 0}}
+
+    for sig in pinmux['ios']:
+        glob_idx = get_index_and_incr(pinmux['io_counts'], sig['connection'], sig['type'])
+        sig['glob_idx'] = glob_idx
+
+    # Calculate global indices for pads.
+    j = k = 0
+    for pad in pinout['pads']:
+        if pad['connection'] == 'muxed':
+            pad['idx'] = j
+            j += 1
+        else:
+            pad['idx'] = k
+            k += 1
+    pinmux['io_counts']['muxed']['pads'] = j
+    pinmux['io_counts']['dedicated']['pads'] = k
+
+    # For each target configuration, calculate the special signal indices.
+    known_muxed_pads = {}
+    for pad in pinout['pads']:
+        if pad['connection'] == 'muxed':
+            known_muxed_pads[pad['name']] = pad
+
+    known_mapped_dio_pads = {}
+    for sig in pinmux['ios']:
+        if sig['connection'] in ['muxed', 'manual']:
+            continue
+        if sig['pad'] in known_mapped_dio_pads:
+            raise SystemExit('Cannot have multiple IOs mapped to the same DIO pad {}'
+                             .format(sig['pad']))
+        known_mapped_dio_pads[sig['pad']] = sig
+
+    for target in targets:
+        for entry in target['pinmux']['special_signals']:
+            # If this is a muxed pad, the resolution is
+            # straightforward. I.e., we just assign the MIO index.
+            if entry['pad'] in known_muxed_pads:
+                entry['idx'] = known_muxed_pads[entry['pad']]['idx']
+            # Otherwise we need to find out which DIO this pad is mapped to.
+            # Note that we can't have special_signals that are manual, since
+            # there needs to exist a DIO connection.
+            elif entry['pad'] in known_mapped_dio_pads:
+                # This index refers to the stacked {dio, mio} array
+                # on the chip-level, hence we have to add the amount of MIO pads.
+                idx = (known_mapped_dio_pads[entry['pad']]['glob_idx'] +
+                       pinmux['io_counts']['muxed']['pads'])
+                entry['idx'] = idx
+            else:
+                assert(0)  # Entry should be guaranteed to exist at this point
+
+
+def merge_top(topcfg: OrderedDict,
+              name_to_block: Dict[str, IpBlock],
+              xbarobjs: OrderedDict) -> OrderedDict:
+
+    # Combine ip cfg into topcfg
+    elaborate_instances(topcfg, name_to_block)
+
+    # Create clock connections for each block
+    # Assign clocks into appropriate groups
+    # Note, elaborate_instances references clock information to establish async handling
+    # as part of alerts.
+    # amend_clocks(topcfg)
+
+    # Combine the wakeups
+    amend_wkup(topcfg, name_to_block)
+    amend_reset_request(topcfg, name_to_block)
+
+    # Combine the interrupt (should be processed prior to xbar)
+    amend_interrupt(topcfg, name_to_block)
+
+    # Combine the alert (should be processed prior to xbar)
+    amend_alert(topcfg, name_to_block)
+
+    # Creates input/output list in the pinmux
+    log.info("Processing PINMUX")
+    amend_pinmux_io(topcfg, name_to_block)
+
+    # Combine xbar into topcfg
+    for xbar in xbarobjs:
+        amend_xbar(topcfg, name_to_block, xbar)
+
+    # 2nd phase of xbar (gathering the devices address range)
+    for xbar in topcfg["xbar"]:
+        xbar_cross(xbar, topcfg["xbar"])
+
+    # Add path names to declared resets.
+    # Declare structure for exported resets.
+    amend_resets(topcfg)
+
+    # remove unwanted fields 'debug_mem_base_addr'
+    topcfg.pop('debug_mem_base_addr', None)
+
+    return topcfg
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/README.md b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/README.md
new file mode 100644
index 00000000..afd488ac
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/README.md
@@ -0,0 +1,4 @@
+# OpenTitan topgen templates
+
+This directory contains templates used by topgen to assembly a chip toplevel.
+
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chip_env_pkg__params.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chip_env_pkg__params.sv.tpl
new file mode 100644
index 00000000..34079006
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chip_env_pkg__params.sv.tpl
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Generated by topgen.py
+
+parameter string LIST_OF_ALERTS[] = {
+% for alert in top["alert"]:
+  % if loop.last:
+  "${alert["name"]}"
+  % else:
+  "${alert["name"]}",
+  % endif
+% endfor
+};
+
+parameter uint NUM_ALERTS = ${len(top["alert"])};
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chiplevel.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chiplevel.sv.tpl
new file mode 100644
index 00000000..aafec5bf
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/chiplevel.sv.tpl
@@ -0,0 +1,1218 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+${gencmd}
+<%
+import re
+import topgen.lib as lib
+from copy import deepcopy
+
+# Provide shortcuts for some commonly used variables
+pinmux = top['pinmux']
+pinout = top['pinout']
+
+num_mio_inputs = pinmux['io_counts']['muxed']['inouts'] + \
+                 pinmux['io_counts']['muxed']['inputs']
+num_mio_outputs = pinmux['io_counts']['muxed']['inouts'] + \
+                  pinmux['io_counts']['muxed']['outputs']
+num_mio_pads = pinmux['io_counts']['muxed']['pads']
+
+num_dio_inputs = pinmux['io_counts']['dedicated']['inouts'] + \
+                 pinmux['io_counts']['dedicated']['inputs']
+num_dio_outputs = pinmux['io_counts']['dedicated']['inouts'] + \
+                  pinmux['io_counts']['dedicated']['outputs']
+num_dio_total = pinmux['io_counts']['dedicated']['inouts'] + \
+                pinmux['io_counts']['dedicated']['inputs'] + \
+                pinmux['io_counts']['dedicated']['outputs']
+
+def get_dio_sig(pinmux: {}, pad: {}):
+  '''Get DIO signal associated with this pad or return None'''
+  for sig in pinmux["ios"]:
+    if sig["connection"] == "direct" and pad["name"] == sig["pad"]:
+      return sig
+  else:
+    return None
+
+# Modify the pad lists on the fly, based on target config
+maxwidth = 0
+muxed_pads = []
+dedicated_pads = []
+k = 0
+for pad in pinout["pads"]:
+  if pad["connection"] == "muxed":
+    if pad["name"] not in target["pinout"]["remove_pads"]:
+      maxwidth = max(maxwidth, len(pad["name"]))
+      muxed_pads.append(pad)
+  else:
+    k = pad["idx"]
+    if pad["name"] not in target["pinout"]["remove_pads"]:
+      maxwidth = max(maxwidth, len(pad["name"]))
+      dedicated_pads.append(pad)
+
+for pad in target["pinout"]["add_pads"]:
+  # Since these additional pads have not been elaborated in the merge phase,
+  # we need to add their global index here.
+  amended_pad = deepcopy(pad)
+  amended_pad.update({"idx" : k})
+  dedicated_pads.append(pad)
+  k += 1
+
+num_im = sum([x["width"] if "width" in x else 1 for x in top["inter_signal"]["external"]])
+
+max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["ios"]])
+max_sigwidth = len("{}".format(max_sigwidth))
+
+clks_attr = top['clocks']
+cpu_clk = top['clocks']['hier_paths']['top'] + "clk_proc_main"
+cpu_rst = top["reset_paths"]["sys"]
+dm_rst = top["reset_paths"]["lc"]
+esc_clk = top['clocks']['hier_paths']['top'] + "clk_io_div4_timers"
+esc_rst = top["reset_paths"]["sys_io_div4"]
+
+unused_resets = lib.get_unused_resets(top)
+unused_im_defs, undriven_im_defs = lib.get_dangling_im_def(top["inter_signal"]["definitions"])
+
+%>\
+% if target["name"] != "asic":
+module chip_${top["name"]}_${target["name"]} #(
+  // Path to a VMEM file containing the contents of the boot ROM, which will be
+  // baked into the FPGA bitstream.
+  parameter BootRomInitFile = "boot_rom_fpga_${target["name"]}.32.vmem",
+  // Path to a VMEM file containing the contents of the emulated OTP, which will be
+  // baked into the FPGA bitstream.
+  parameter OtpCtrlMemInitFile = "otp_img_fpga_${target["name"]}.vmem",
+  // TODO: Remove this 0 once infra is ready
+  parameter bit RomCtrlSkipCheck = 1
+) (
+% else:
+module chip_${top["name"]}_${target["name"]} #(
+  // TODO: Remove this 0 once infra is ready
+  parameter bit RomCtrlSkipCheck = 1
+) (
+% endif
+<%
+
+%>\
+  // Dedicated Pads
+% for pad in dedicated_pads:
+<%
+  sig = get_dio_sig(pinmux, pad)
+  if sig is not None:
+    comment = "// Dedicated Pad for {}".format(sig["name"])
+  else:
+    comment = "// Manual Pad"
+%>\
+  inout ${pad["name"]}, ${comment}
+% endfor
+
+  // Muxed Pads
+% for pad in muxed_pads:
+  inout ${pad["name"]}${" " if loop.last else ","} // MIO Pad ${pad["idx"]}
+% endfor
+);
+
+  import top_${top["name"]}_pkg::*;
+  import prim_pad_wrapper_pkg::*;
+
+% if target["pinmux"]["special_signals"]:
+  ////////////////////////////
+  // Special Signal Indices //
+  ////////////////////////////
+
+  % for entry in target["pinmux"]["special_signals"]:
+<% param_name = (lib.Name.from_snake_case(entry["name"]) +
+                 lib.Name(["pad", "idx"])).as_camel_case()
+%>\
+  parameter int ${param_name} = ${entry["idx"]};
+  % endfor
+% endif
+
+  // DFT and Debug signal positions in the pinout.
+  localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+    tck_idx:           TckPadIdx,
+    tms_idx:           TmsPadIdx,
+    trst_idx:          TrstNPadIdx,
+    tdi_idx:           TdiPadIdx,
+    tdo_idx:           TdoPadIdx,
+    tap_strap0_idx:    Tap0PadIdx,
+    tap_strap1_idx:    Tap1PadIdx,
+    dft_strap0_idx:    Dft0PadIdx,
+    dft_strap1_idx:    Dft1PadIdx,
+    // TODO: check whether there is a better way to pass these USB-specific params
+    usb_dp_idx:        DioUsbdevDp,
+    usb_dn_idx:        DioUsbdevDn,
+    usb_dp_pullup_idx: DioUsbdevDpPullup,
+    usb_dn_pullup_idx: DioUsbdevDnPullup,
+    // Pad types for attribute WARL behavior
+    dio_pad_type: {
+<%
+  pad_attr = []
+  for sig in list(reversed(top["pinmux"]["ios"])):
+    if sig["connection"] != "muxed":
+      pad_attr.append((sig['name'], sig["attr"]))
+%>\
+% for name, attr in pad_attr:
+      ${attr}${" " if loop.last else ","} // DIO ${name}
+% endfor
+    },
+    mio_pad_type: {
+<%
+  pad_attr = []
+  for pad in list(reversed(pinout["pads"])):
+    if pad["connection"] == "muxed":
+      pad_attr.append(pad["type"])
+%>\
+% for attr in pad_attr:
+      ${attr}${" " if loop.last else ","} // MIO Pad ${len(pad_attr) - loop.index - 1}
+% endfor
+    }
+  };
+
+  ////////////////////////
+  // Signal definitions //
+  ////////////////////////
+
+  pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
+  pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
+  logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
+  logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
+  logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
+  logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw;
+  logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
+  logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
+  logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
+
+  logic unused_mio_in_raw;
+  assign unused_mio_in_raw = ^mio_in_raw;
+
+  // Manual pads
+% for pad in dedicated_pads:
+<%
+  pad_prefix = pad["name"].lower()
+%>\
+% if not get_dio_sig(pinmux, pad):
+  logic manual_in_${pad_prefix}, manual_out_${pad_prefix}, manual_oe_${pad_prefix};
+% endif
+% endfor
+
+% for pad in dedicated_pads:
+<%
+  pad_prefix = pad["name"].lower()
+%>\
+% if not get_dio_sig(pinmux, pad):
+  pad_attr_t manual_attr_${pad_prefix};
+% endif
+% endfor
+
+% if target["pinout"]["remove_pads"]:
+  /////////////////////////
+  // Stubbed pad tie-off //
+  /////////////////////////
+
+  // Only signals going to non-custom pads need to be tied off.
+  logic [${len(pinout["pads"])-1}:0] unused_sig;
+% for pad in pinout["pads"]:
+  % if pad["connection"] == 'muxed':
+    % if pad["name"] in target["pinout"]["remove_pads"]:
+  assign mio_in[${pad["idx"]}] = 1'b0;
+  assign unused_sig[${loop.index}] = mio_out[${pad["idx"]}] ^ mio_oe[${pad["idx"]}];
+    % endif
+  % else:
+    % if pad["name"] in target["pinout"]["remove_pads"]:
+<%
+    ## Only need to tie off if this is not a custom pad.
+    sig = get_dio_sig(pinmux, pad)
+    if sig is not None:
+      sig_index = lib.get_io_enum_literal(sig, 'dio')
+%>\
+      % if sig is not None:
+  assign dio_in[${lib.get_io_enum_literal(sig, 'dio')}] = 1'b0;
+  assign unused_sig[${loop.index}] = dio_out[${sig_index}] ^ dio_oe[${sig_index}];
+      % endif
+    % endif
+  % endif
+% endfor
+%endif
+
+  //////////////////////
+  // Padring Instance //
+  //////////////////////
+
+% if target["name"] == "asic":
+  // AST signals needed in padring
+  ast_pkg::ast_clks_t ast_base_clks;
+  logic scan_rst_n;
+  lc_ctrl_pkg::lc_tx_t scanmode;
+% endif
+
+  padring #(
+    // Padring specific counts may differ from pinmux config due
+    // to custom, stubbed or added pads.
+    .NDioPads(${len(dedicated_pads)}),
+    .NMioPads(${len(muxed_pads)}),
+% if target["name"] == "asic":
+    .PhysicalPads(1),
+    .NIoBanks(int'(IoBankCount)),
+    .DioScanRole ({
+% for pad in list(reversed(dedicated_pads)):
+      scan_role_pkg::${lib.Name.from_snake_case('dio_pad_' + pad["name"] + '_scan_role').as_camel_case()}${"" if loop.last else ","}
+% endfor
+    }),
+    .MioScanRole ({
+% for pad in list(reversed(muxed_pads)):
+      scan_role_pkg::${lib.Name.from_snake_case('mio_pad_' + pad["name"] + '_scan_role').as_camel_case()}${"" if loop.last else ","}
+% endfor
+    }),
+    .DioPadBank ({
+% for pad in list(reversed(dedicated_pads)):
+      ${lib.Name.from_snake_case('io_bank_' + pad["bank"]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+    }),
+    .MioPadBank ({
+% for pad in list(reversed(muxed_pads)):
+      ${lib.Name.from_snake_case('io_bank_' + pad["bank"]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+    }),
+% endif
+\
+\
+    .DioPadType ({
+% for pad in list(reversed(dedicated_pads)):
+      ${pad["type"]}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+    }),
+    .MioPadType ({
+% for pad in list(reversed(muxed_pads)):
+      ${pad["type"]}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+    })
+  ) u_padring (
+  // This is only used for scan and DFT purposes
+% if target["name"] == "asic":
+    .clk_scan_i   ( ast_base_clks.clk_sys ),
+    .scanmode_i   ( scanmode              ),
+% else:
+    .clk_scan_i   ( 1'b0                  ),
+    .scanmode_i   ( lc_ctrl_pkg::Off      ),
+  % endif
+    .dio_in_raw_o ( ),
+    .mio_in_raw_o ( mio_in_raw            ),
+    // Chip IOs
+    .dio_pad_io ({
+% for pad in list(reversed(dedicated_pads)):
+      ${pad["name"]}${"" if loop.last else ","}
+% endfor
+    }),
+
+    .mio_pad_io ({
+% for pad in list(reversed(muxed_pads)):
+      ${pad["name"]}${"" if loop.last else ","}
+% endfor
+    }),
+
+    // Core-facing
+% for port in ["in_o", "out_i", "oe_i", "attr_i"]:
+    .dio_${port} ({
+  % for pad in list(reversed(dedicated_pads)):
+  <%
+    sig = get_dio_sig(pinmux, pad)
+  %>\
+    % if sig is None:
+      manual_${port[:-2]}_${pad["name"].lower()}${"" if loop.last else ","}
+    % else:
+      dio_${port[:-2]}[${lib.get_io_enum_literal(sig, 'dio')}]${"" if loop.last else ","}
+    % endif
+  % endfor
+      }),
+% endfor
+
+% for port in ["in_o", "out_i", "oe_i", "attr_i"]:
+<%
+    sig_name = 'mio_' + port[:-2]
+    indices = list(reversed(list(pad['idx'] for pad in muxed_pads)))
+%>\
+    .mio_${port} (${lib.make_bit_concatenation(sig_name, indices, 6)})${"" if loop.last else ","}
+% endfor
+  );
+
+
+###################################################################
+## USB for CW305                                                 ##
+###################################################################
+% if target["name"] == "cw305":
+  // Connect the DP pad
+  assign dio_in[DioUsbdevDp] = manual_in_usb_p;
+  assign manual_out_usb_p = dio_out[DioUsbdevDp];
+  assign manual_oe_usb_p = dio_oe[DioUsbdevDp];
+  assign manual_attr_usb_p = dio_attr[DioUsbdevDp];
+
+  // Connect the DN pad
+  assign dio_in[DioUsbdevDn] = manual_in_usb_n;
+  assign manual_out_usb_n = dio_out[DioUsbdevDn];
+  assign manual_oe_usb_n = dio_oe[DioUsbdevDn];
+  assign manual_attr_usb_n = dio_attr[DioUsbdevDn];
+
+  // Connect sense pad
+  assign dio_in[DioUsbdevSense] = manual_in_io_usb_sense0;
+  assign manual_out_io_usb_sense0 = dio_out[DioUsbdevSense];
+  assign manual_oe_io_usb_sense0 = dio_oe[DioUsbdevSense];
+  assign manual_attr_io_sense0 = dio_attr[DioUsbdevSense];
+
+  // Connect DN pullup
+  assign dio_in[DioUsbdevDnPullup] = manual_in_io_usb_dnpullup0;
+  assign manual_out_io_usb_dnpullup0 = dio_out[DioUsbdevDnPullup];
+  assign manual_oe_io_usb_dnpullup0 = dio_oe[DioUsbdevDnPullup];
+  assign manual_attr_io_dnpullup0 = dio_attr[DioUsbdevDnPullup];
+
+  // Connect DP pullup
+  assign dio_in[DioUsbdevDpPullup] = manual_in_io_usb_dppullup0;
+  assign manual_out_io_usb_dppullup0 = dio_out[DioUsbdevDpPullup];
+  assign manual_oe_io_usb_dppullup0 = dio_oe[DioUsbdevDpPullup];
+  assign manual_attr_io_dppullup0 = dio_attr[DioUsbdevDpPullup];
+
+  // Tie-off unused signals
+  assign dio_in[DioUsbdevSe0] = 1'b0;
+  assign dio_in[DioUsbdevTxModeSe] = 1'b0;
+  assign dio_in[DioUsbdevSuspend] = 1'b0;
+
+  logic unused_usb_sigs;
+  assign unused_usb_sigs = ^{
+    // SE0
+    dio_out[DioUsbdevSe0],
+    dio_oe[DioUsbdevSe0],
+    dio_attr[DioUsbdevSe0],
+    // TX Mode
+    dio_out[DioUsbdevTxModeSe],
+    dio_oe[DioUsbdevTxModeSe],
+    dio_attr[DioUsbdevTxModeSe],
+    // Suspend
+    dio_out[DioUsbdevSuspend],
+    dio_oe[DioUsbdevSuspend],
+    dio_attr[DioUsbdevSuspend],
+    // D is used as an input only
+    dio_out[DioUsbdevD],
+    dio_oe[DioUsbdevD],
+    dio_attr[DioUsbdevD]
+  };
+
+% endif
+
+###################################################################
+## USB for Nexysvideo                                            ##
+###################################################################
+% if target["name"] == "nexysvideo":
+
+  /////////////////////
+  // USB Overlay Mux //
+  /////////////////////
+
+  // TODO: generalize this USB mux code and align with other tops.
+
+  // Software can enable the pinflip feature inside usbdev.
+  // The example hello_usbdev does this based on GPIO0 (a switch on the board)
+  //
+  // Here, we use the state of the DN pullup to effectively undo the
+  // swapping such that the PCB always sees the unflipped D+/D-. We
+  // could do the same inside the .xdc file but then two FPGA
+  // bitstreams would be needed for testing.
+  //
+  // dio_in/out/oe map is: PADS <- _padring <- JTAG mux -> _umux -> USB mux -> _core
+
+  // Split out for differential PHY testing
+
+  // Outputs always drive and just copy the value
+  // Let them go to the normal place too because it won't do any harm
+  // and it simplifies the changes needed
+
+  // The output enable for IO_USB_DNPULLUP0 is used to decide whether we need to undo the swapping.
+  logic undo_swap;
+  assign undo_swap = dio_oe[DioUsbdevDnPullup];
+
+  // GPIO[2] = Switch 2 on board is used to select using the UPHY
+  // Keep GPIO[1] for selecting differential in sw
+  logic use_uphy;
+  assign use_uphy = mio_in[MioPadIoa2];
+
+  // DioUsbdevDn
+  assign manual_attr_usb_n = '0;
+  assign manual_attr_io_uphy_dn_tx = '0;
+
+  assign manual_out_io_uphy_dn_tx = manual_out_usb_n;
+  assign manual_out_usb_n = undo_swap ? dio_out[DioUsbdevDp] :
+                                        dio_out[DioUsbdevDn];
+
+  assign manual_oe_io_uphy_dn_tx = manual_oe_usb_n;
+  assign manual_oe_usb_n = undo_swap ? dio_oe[DioUsbdevDp] :
+                                       dio_oe[DioUsbdevDn];
+
+  assign dio_in[DioUsbdevDn] = use_uphy ?
+                               (undo_swap ? manual_in_io_uphy_dp_rx :
+                                            manual_in_io_uphy_dn_rx) :
+                               (undo_swap ? manual_in_usb_p :
+                                            manual_in_usb_n);
+  // DioUsbdevDp
+  assign manual_attr_usb_p = '0;
+  assign manual_attr_io_uphy_dp_tx = '0;
+
+  assign manual_out_io_uphy_dp_tx = manual_out_usb_p;
+  assign manual_out_usb_p = undo_swap ? dio_out[DioUsbdevDn] :
+                                       dio_out[DioUsbdevDp];
+
+  assign manual_oe_io_uphy_dp_tx = manual_oe_usb_p;
+  assign manual_oe_usb_p = undo_swap ? dio_oe[DioUsbdevDn] :
+                                       dio_oe[DioUsbdevDp];
+  assign dio_in[DioUsbdevDp] = use_uphy ?
+                               (undo_swap ? manual_in_io_uphy_dn_rx :
+                                            manual_in_io_uphy_dp_rx) :
+                               (undo_swap ? manual_in_usb_n :
+                                            manual_in_usb_p);
+  // DioUsbdevD
+  // This is not connected at the moment
+  logic unused_out_usb_d;
+  assign unused_out_usb_d = dio_out[DioUsbdevD] ^
+                            dio_oe[DioUsbdevD];
+  assign dio_in[DioUsbdevD] = use_uphy ?
+                              (undo_swap ? ~manual_in_io_uphy_d_rx :
+                                            manual_in_io_uphy_d_rx) :
+                              // This is not connected at the moment
+                              (undo_swap ? 1'b1 : 1'b0);
+  assign manual_out_io_uphy_d_rx = 1'b0;
+  assign manual_oe_io_uphy_d_rx = 1'b0;
+
+  // DioUsbdevDnPullup
+  assign manual_attr_io_usb_dnpullup0 = '0;
+  assign manual_out_io_usb_dnpullup0 = undo_swap ? dio_out[DioUsbdevDpPullup] :
+                                                   dio_out[DioUsbdevDnPullup];
+  assign manual_oe_io_usb_dnpullup0 = undo_swap ? dio_oe[DioUsbdevDpPullup] :
+                                                  dio_oe[DioUsbdevDnPullup];
+  assign dio_in[DioUsbdevDnPullup] = manual_in_io_usb_dnpullup0;
+
+  // DioUsbdevDpPullup
+  assign manual_attr_io_usb_dppullup0 = '0;
+  assign manual_out_io_usb_dppullup0 = undo_swap ? dio_out[DioUsbdevDnPullup] :
+                                                   dio_out[DioUsbdevDpPullup];
+  assign manual_oe_io_usb_dppullup0 = undo_swap ? dio_oe[DioUsbdevDnPullup] :
+                                                  dio_oe[DioUsbdevDpPullup];
+  assign dio_in[DioUsbdevDpPullup] = manual_in_io_usb_dppullup0;
+
+  // DioUsbdevSense
+  assign manual_out_io_usb_sense0 = dio_out[DioUsbdevSense];
+  assign manual_oe_io_usb_sense0  = dio_oe[DioUsbdevSense];
+  assign dio_in[DioUsbdevSense] = use_uphy ? manual_in_io_uphy_sense :
+                                             manual_in_io_usb_sense0;
+  assign manual_out_io_uphy_sense = 1'b0;
+  assign manual_oe_io_uphy_sense = 1'b0;
+
+  // DioUsbdevRxEnable
+  assign dio_in[DioUsbdevRxEnable] = 1'b0;
+
+  // Additional outputs for uphy
+  assign manual_oe_io_uphy_dppullup = 1'b1;
+  assign manual_out_io_uphy_dppullup = manual_out_io_usb_dppullup0 &
+                                       manual_oe_io_usb_dppullup0;
+
+  logic unused_in_io_uphy_dppullup;
+  assign unused_in_io_uphy_dppullup = manual_in_io_uphy_dppullup;
+
+  assign manual_oe_io_uphy_oe_n = 1'b1;
+  assign manual_out_io_uphy_oe_n = ~manual_oe_usb_p;
+
+  logic unused_in_io_uphy_oe_n;
+  assign unused_in_io_uphy_oe_n = manual_in_io_uphy_oe_n;
+
+% endif
+
+###################################################################
+## ASIC                                                          ##
+###################################################################
+% if target["name"] == "asic":
+
+  //////////////////////////////////
+  // Manual Pad / Signal Tie-offs //
+  //////////////////////////////////
+
+  assign manual_out_por_n = 1'b0;
+  assign manual_oe_por_n = 1'b0;
+
+  assign manual_out_cc1 = 1'b0;
+  assign manual_oe_cc1 = 1'b0;
+  assign manual_out_cc2 = 1'b0;
+  assign manual_oe_cc2 = 1'b0;
+
+  assign manual_out_flash_test_mode0 = 1'b0;
+  assign manual_oe_flash_test_mode0 = 1'b0;
+  assign manual_out_flash_test_mode1 = 1'b0;
+  assign manual_oe_flash_test_mode1 = 1'b0;
+  assign manual_out_flash_test_volt = 1'b0;
+  assign manual_oe_flash_test_volt = 1'b0;
+  assign manual_out_otp_ext_volt = 1'b0;
+  assign manual_oe_otp_ext_volt = 1'b0;
+
+  // These pad attributes currently tied off permanently (these are all input-only pads).
+  assign manual_attr_por_n = '0;
+  assign manual_attr_cc1 = '0;
+  assign manual_attr_cc2 = '0;
+  assign manual_attr_flash_test_mode0 = '0;
+  assign manual_attr_flash_test_mode1 = '0;
+  assign manual_attr_flash_test_volt = '0;
+  assign manual_attr_otp_ext_volt = '0;
+
+  logic unused_manual_sigs;
+  assign unused_manual_sigs = ^{
+    manual_in_cc2,
+    manual_in_cc1,
+    manual_in_flash_test_volt,
+    manual_in_flash_test_mode0,
+    manual_in_flash_test_mode1,
+    manual_in_otp_ext_volt
+  };
+
+  ///////////////////////////////
+  // Differential USB Receiver //
+  ///////////////////////////////
+
+  // TODO: generalize this USB mux code and align with other tops.
+
+  // Connect the DP pad
+  assign dio_in[DioUsbdevDp] = manual_in_usb_p;
+  assign manual_out_usb_p = dio_out[DioUsbdevDp];
+  assign manual_oe_usb_p = dio_oe[DioUsbdevDp];
+  assign manual_attr_usb_p = dio_attr[DioUsbdevDp];
+
+  // Connect the DN pad
+  assign dio_in[DioUsbdevDn] = manual_in_usb_n;
+  assign manual_out_usb_n = dio_out[DioUsbdevDn];
+  assign manual_oe_usb_n = dio_oe[DioUsbdevDn];
+  assign manual_attr_usb_n = dio_attr[DioUsbdevDn];
+
+  // Pullups
+  logic usb_pullup_p_en, usb_pullup_n_en;
+  assign usb_pullup_p_en = dio_out[DioUsbdevDpPullup] & dio_oe[DioUsbdevDpPullup];
+  assign usb_pullup_n_en = dio_out[DioUsbdevDnPullup] & dio_oe[DioUsbdevDnPullup];
+
+  logic usb_rx_enable;
+  assign usb_rx_enable = dio_out[DioUsbdevRxEnable] & dio_oe[DioUsbdevRxEnable];
+
+  logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
+
+  // pwrmgr interface
+  pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
+  pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+
+  prim_usb_diff_rx #(
+    .CalibW(ast_pkg::UsbCalibWidth)
+  ) u_prim_usb_diff_rx (
+    .input_pi      ( USB_P                 ),
+    .input_ni      ( USB_N                 ),
+    .input_en_i    ( usb_rx_enable         ),
+    .core_pok_i    ( ast_base_pwr.main_pok ),
+    .pullup_p_en_i ( usb_pullup_p_en       ),
+    .pullup_n_en_i ( usb_pullup_n_en       ),
+    .calibration_i ( usb_io_pu_cal         ),
+    .input_o       ( dio_in[DioUsbdevD]    )
+  );
+
+  // Tie-off unused signals
+  assign dio_in[DioUsbdevSense] = 1'b0;
+  assign dio_in[DioUsbdevSe0] = 1'b0;
+  assign dio_in[DioUsbdevDpPullup] = 1'b0;
+  assign dio_in[DioUsbdevDnPullup] = 1'b0;
+  assign dio_in[DioUsbdevTxModeSe] = 1'b0;
+  assign dio_in[DioUsbdevSuspend] = 1'b0;
+  assign dio_in[DioUsbdevRxEnable] = 1'b0;
+
+  logic unused_usb_sigs;
+  assign unused_usb_sigs = ^{
+    // Sense
+    dio_out[DioUsbdevSense],
+    dio_oe[DioUsbdevSense],
+    dio_attr[DioUsbdevSense],
+    // SE0
+    dio_out[DioUsbdevSe0],
+    dio_oe[DioUsbdevSe0],
+    dio_attr[DioUsbdevSe0],
+    // TX Mode
+    dio_out[DioUsbdevTxModeSe],
+    dio_oe[DioUsbdevTxModeSe],
+    dio_attr[DioUsbdevTxModeSe],
+    // Suspend
+    dio_out[DioUsbdevSuspend],
+    dio_oe[DioUsbdevSuspend],
+    dio_attr[DioUsbdevSuspend],
+    // Rx enable
+    dio_attr[DioUsbdevRxEnable],
+    // D is used as an input only
+    dio_out[DioUsbdevD],
+    dio_oe[DioUsbdevD],
+    dio_attr[DioUsbdevD],
+    // Pullup/down
+    dio_attr[DioUsbdevDpPullup],
+    dio_attr[DioUsbdevDnPullup]
+  };
+
+  //////////////////////
+  // AST              //
+  //////////////////////
+  // TLUL interface
+  tlul_pkg::tl_h2d_t base_ast_bus;
+  tlul_pkg::tl_d2h_t ast_base_bus;
+
+  // assorted ast status
+  ast_pkg::ast_status_t ast_status;
+
+  // ast clocks and resets
+  logic aon_pok;
+
+  // synchronization clocks / rests
+  clkmgr_pkg::clkmgr_ast_out_t clks_ast;
+  rstmgr_pkg::rstmgr_ast_out_t rsts_ast;
+
+  // otp power sequence
+  otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
+  otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
+
+  logic usb_ref_pulse;
+  logic usb_ref_val;
+
+  // adc
+  ast_pkg::adc_ast_req_t adc_req;
+  ast_pkg::adc_ast_rsp_t adc_rsp;
+
+  // entropy source interface
+  // The entropy source pacakge definition should eventually be moved to es
+  entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
+  entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
+  logic es_rng_fips;
+
+  // entropy distribution network
+  edn_pkg::edn_req_t ast_edn_edn_req;
+  edn_pkg::edn_rsp_t ast_edn_edn_rsp;
+
+  // alerts interface
+  ast_pkg::ast_alert_rsp_t ast_alert_rsp;
+  ast_pkg::ast_alert_req_t ast_alert_req;
+
+  // Flash connections
+  lc_ctrl_pkg::lc_tx_t flash_bist_enable;
+  logic flash_power_down_h;
+  logic flash_power_ready_h;
+
+  // Life cycle clock bypass req/ack
+  lc_ctrl_pkg::lc_tx_t ast_clk_byp_req;
+  lc_ctrl_pkg::lc_tx_t ast_clk_byp_ack;
+
+  // DFT connections
+  logic scan_en;
+  lc_ctrl_pkg::lc_tx_t dft_en;
+  pinmux_pkg::dft_strap_test_req_t dft_strap_test;
+
+  // Debug connections
+  logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
+  logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast;
+
+  assign pad2ast = {
+                     mio_in_raw[MioPadIoc3],
+                     mio_in_raw[MioPadIob8],
+                     mio_in_raw[MioPadIob7],
+                     mio_in_raw[MioPadIob2],
+                     mio_in_raw[MioPadIob1],
+                     mio_in_raw[MioPadIob0]
+                   };
+
+
+  // Jitter enable
+  logic jen;
+
+  // reset domain connections
+  import rstmgr_pkg::PowerDomains;
+  import rstmgr_pkg::DomainAonSel;
+  import rstmgr_pkg::Domain0Sel;
+
+  // external clock comes in at a fixed position
+  logic ext_clk;
+  assign ext_clk = mio_in_raw[MioPadIoc6];
+
+  // Memory configuration connections
+  ast_pkg::spm_rm_t ast_ram_1p_cfg;
+  ast_pkg::spm_rm_t ast_rf_cfg;
+  ast_pkg::spm_rm_t ast_rom_cfg;
+  ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
+  ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
+
+  prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
+  prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg;
+  prim_rom_pkg::rom_cfg_t rom_cfg;
+
+  // conversion from ast structure to memory centric structures
+  assign ram_1p_cfg = '{
+    ram_cfg: '{
+                cfg_en: ast_ram_1p_cfg.marg_en,
+                cfg:    ast_ram_1p_cfg.marg
+              },
+    rf_cfg:  '{
+                cfg_en: ast_rf_cfg.marg_en,
+                cfg:    ast_rf_cfg.marg
+              }
+  };
+
+  assign ram_2p_cfg = '{
+    a_ram_fcfg: '{
+                   cfg_en: ast_ram_2p_fcfg.marg_en_a,
+                   cfg:    ast_ram_2p_fcfg.marg_a
+                 },
+    a_ram_lcfg: '{
+                   cfg_en: ast_ram_2p_lcfg.marg_en_a,
+                   cfg:    ast_ram_2p_lcfg.marg_a
+                 },
+    b_ram_fcfg: '{
+                   cfg_en: ast_ram_2p_fcfg.marg_en_b,
+                   cfg:    ast_ram_2p_fcfg.marg_b
+                 },
+    b_ram_lcfg: '{
+                   cfg_en: ast_ram_2p_lcfg.marg_en_b,
+                   cfg:    ast_ram_2p_lcfg.marg_b
+                 }
+  };
+
+  assign rom_cfg = '{
+    cfg_en: ast_rom_cfg.marg_en,
+    cfg: ast_rom_cfg.marg
+  };
+
+
+  // AST does not use all clocks / resets forwarded to it
+  logic unused_slow_clk_en;
+  logic unused_usb_clk_aon;
+  logic unused_usb_clk_io_div4;
+  assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
+  assign unused_usb_clk_aon = clks_ast.clk_ast_usbdev_aon_peri;
+  assign unused_usb_clk_io_div4 = clks_ast.clk_ast_usbdev_io_div4_peri;
+
+  logic unused_usb_usb_rst;
+  logic [PowerDomains-1:0] unused_usb_sys_io_div4_rst;
+  logic [PowerDomains-1:0] unused_usb_sys_aon_rst;
+  logic unused_ast_sys_io_div4_rst;
+  logic unused_sensor_ctrl_sys_io_div4_rst;
+  logic unused_adc_ctrl_sys_io_div4_rst;
+  logic unused_entropy_sys_rst;
+  logic unused_edn_sys_rst;
+  assign unused_usb_usb_rst = rsts_ast.rst_ast_usbdev_usb_n[DomainAonSel];
+  assign unused_usb_sys_io_div4_rst = rsts_ast.rst_ast_usbdev_sys_io_div4_n;
+  assign unused_usb_sys_aon_rst = rsts_ast.rst_ast_usbdev_sys_aon_n;
+  assign unused_ast_sys_io_div4_rst =
+    rsts_ast.rst_ast_ast_sys_io_div4_n[Domain0Sel];
+  assign unused_sensor_ctrl_sys_io_div4_rst =
+    rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[Domain0Sel];
+  assign unused_adc_ctrl_sys_io_div4_rst =
+    rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[Domain0Sel];
+  assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel];
+  assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel];
+
+  ast_pkg::ast_dif_t flash_alert;
+  ast_pkg::ast_dif_t otp_alert;
+  logic ast_init_done;
+
+  ast #(
+    .EntropyStreams(ast_pkg::EntropyStreams),
+    .AdcChannels(ast_pkg::AdcChannels),
+    .AdcDataWidth(ast_pkg::AdcDataWidth),
+    .UsbCalibWidth(ast_pkg::UsbCalibWidth),
+    .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
+    .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
+  ) u_ast (
+    // tlul
+    .tl_i                  ( base_ast_bus ),
+    .tl_o                  ( ast_base_bus ),
+    // init done indication
+    .ast_init_done_o       ( ast_init_done ),
+    // buffered clocks & resets
+    // Reset domain connection is manual at the moment
+    .clk_ast_adc_i         ( clks_ast.clk_ast_adc_ctrl_aon_io_div4_peri ),
+    .rst_ast_adc_ni        ( rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+    .clk_ast_alert_i       ( clks_ast.clk_ast_sensor_ctrl_aon_io_div4_secure ),
+    .rst_ast_alert_ni      ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+    .clk_ast_es_i          ( clks_ast.clk_ast_edn0_main_secure ),
+    .rst_ast_es_ni         ( rsts_ast.rst_ast_edn0_sys_n[Domain0Sel] ),
+    .clk_ast_rng_i         ( clks_ast.clk_ast_entropy_src_main_secure ),
+    .rst_ast_rng_ni        ( rsts_ast.rst_ast_entropy_src_sys_n[Domain0Sel] ),
+    .clk_ast_tlul_i        ( clks_ast.clk_ast_ast_io_div4_secure ),
+    .rst_ast_tlul_ni       ( rsts_ast.rst_ast_ast_sys_io_div4_n[DomainAonSel] ),
+    .clk_ast_usb_i         ( clks_ast.clk_ast_usbdev_usb_peri ),
+    .rst_ast_usb_ni        ( rsts_ast.rst_ast_usbdev_usb_n[Domain0Sel] ),
+    .clk_ast_ext_i         ( ext_clk ),
+    .por_ni                ( manual_in_por_n ),
+    // pok test for FPGA
+    .vcc_supp_i            ( 1'b1 ),
+    .vcaon_supp_i          ( 1'b1 ),
+    .vcmain_supp_i         ( 1'b1 ),
+    .vioa_supp_i           ( 1'b1 ),
+    .viob_supp_i           ( 1'b1 ),
+    // pok
+    .vcaon_pok_o           ( aon_pok ),
+    .vcmain_pok_o          ( ast_base_pwr.main_pok ),
+    .vioa_pok_o            ( ast_status.io_pok[0] ),
+    .viob_pok_o            ( ast_status.io_pok[1] ),
+    // main regulator
+    .main_env_iso_en_i     ( base_ast_pwr.pwr_clamp_env ),
+    .main_pd_ni            ( base_ast_pwr.main_pd_n ),
+    // pdm control (flash)/otp
+    .flash_power_down_h_o  ( flash_power_down_h ),
+    .flash_power_ready_h_o ( flash_power_ready_h ),
+    .otp_power_seq_i       ( otp_ctrl_otp_ast_pwr_seq ),
+    .otp_power_seq_h_o     ( otp_ctrl_otp_ast_pwr_seq_h ),
+    // system source clock
+    .clk_src_sys_en_i      ( base_ast_pwr.core_clk_en ),
+    // need to add function in clkmgr
+    .clk_src_sys_jen_i     ( jen ),
+    .clk_src_sys_o         ( ast_base_clks.clk_sys  ),
+    .clk_src_sys_val_o     ( ast_base_pwr.core_clk_val ),
+    // aon source clock
+    .clk_src_aon_o         ( ast_base_clks.clk_aon ),
+    .clk_src_aon_val_o     ( ast_base_pwr.slow_clk_val ),
+    // io source clock
+    .clk_src_io_en_i       ( base_ast_pwr.io_clk_en ),
+    .clk_src_io_o          ( ast_base_clks.clk_io ),
+    .clk_src_io_val_o      ( ast_base_pwr.io_clk_val ),
+    // usb source clock
+    .usb_ref_pulse_i       ( usb_ref_pulse ),
+    .usb_ref_val_i         ( usb_ref_val ),
+    .clk_src_usb_en_i      ( base_ast_pwr.usb_clk_en ),
+    .clk_src_usb_o         ( ast_base_clks.clk_usb ),
+    .clk_src_usb_val_o     ( ast_base_pwr.usb_clk_val ),
+    // USB IO Pull-up Calibration Setting
+    .usb_io_pu_cal_o       ( usb_io_pu_cal ),
+    // adc
+    .adc_a0_ai             ( CC1 ),
+    .adc_a1_ai             ( CC2 ),
+    .adc_pd_i              ( adc_req.pd ),
+    .adc_chnsel_i          ( adc_req.channel_sel ),
+    .adc_d_o               ( adc_rsp.data ),
+    .adc_d_val_o           ( adc_rsp.data_valid ),
+    // rng
+    .rng_en_i              ( es_rng_req.rng_enable ),
+    .rng_fips_i            ( es_rng_fips ),
+    .rng_val_o             ( es_rng_rsp.rng_valid ),
+    .rng_b_o               ( es_rng_rsp.rng_b ),
+    // entropy
+    .entropy_rsp_i         ( ast_edn_edn_rsp ),
+    .entropy_req_o         ( ast_edn_edn_req ),
+    // alerts
+    .fla_alert_in_i        ( flash_alert    ),
+    .otp_alert_in_i        ( otp_alert      ),
+    .alert_rsp_i           ( ast_alert_rsp  ),
+    .alert_req_o           ( ast_alert_req  ),
+    // dft
+    .dft_strap_test_i      ( dft_strap_test   ),
+    .lc_dft_en_i           ( dft_en           ),
+    // pinmux related
+    .padmux2ast_i          ( pad2ast    ),
+    .ast2padmux_o          ( ast2pinmux ),
+    // Direct short to PAD
+    .pad2ast_t0_ai         ( IOA4 ),
+    .pad2ast_t1_ai         ( IOA5 ),
+    .ast2pad_t0_ao         ( IOA2 ),
+    .ast2pad_t1_ao         ( IOA3 ),
+    .lc_clk_byp_req_i      ( ast_clk_byp_req   ),
+    .lc_clk_byp_ack_o      ( ast_clk_byp_ack   ),
+    .flash_bist_en_o       ( flash_bist_enable ),
+    // Memory configuration connections
+    .dpram_rmf_o           ( ast_ram_2p_fcfg ),
+    .dpram_rml_o           ( ast_ram_2p_lcfg ),
+    .spram_rm_o            ( ast_ram_1p_cfg  ),
+    .sprgf_rm_o            ( ast_rf_cfg      ),
+    .sprom_rm_o            ( ast_rom_cfg     ),
+    // scan
+    .dft_scan_md_o         ( scanmode ),
+    .scan_shift_en_o       ( scan_en ),
+    .scan_reset_no         ( scan_rst_n )
+  );
+
+  //////////////////////
+  // Top-level design //
+  //////////////////////
+
+  top_${top["name"]} #(
+    .AesMasking(1'b1),
+    .AesSBoxImpl(aes_pkg::SBoxImplDom),
+    .SecAesStartTriggerDelay(0),
+    .SecAesAllowForcingMasks(1'b0),
+    .KmacEnMasking(1),  // DOM AND + Masking scheme
+    .KmacReuseShare(0),
+    .SramCtrlRetAonInstrExec(0),
+    .SramCtrlMainInstrExec(1),
+    .PinmuxAonTargetCfg(PinmuxTargetCfg),
+    .RomCtrlSkipCheck(RomCtrlSkipCheck)
+  ) top_${top["name"]} (
+    .rst_ni                       ( aon_pok                    ),
+    // ast connections
+    .clk_main_i                   ( ast_base_clks.clk_sys      ),
+    .clk_io_i                     ( ast_base_clks.clk_io       ),
+    .clk_usb_i                    ( ast_base_clks.clk_usb      ),
+    .clk_aon_i                    ( ast_base_clks.clk_aon      ),
+    .clks_ast_o                   ( clks_ast                   ),
+    .clk_main_jitter_en_o         ( jen                        ),
+    .rsts_ast_o                   ( rsts_ast                   ),
+    .pwrmgr_ast_req_o             ( base_ast_pwr               ),
+    .pwrmgr_ast_rsp_i             ( ast_base_pwr               ),
+    .sensor_ctrl_ast_alert_req_i  ( ast_alert_req              ),
+    .sensor_ctrl_ast_alert_rsp_o  ( ast_alert_rsp              ),
+    .sensor_ctrl_ast_status_i     ( ast_status                 ),
+    .usbdev_usb_ref_val_o         ( usb_ref_pulse              ),
+    .usbdev_usb_ref_pulse_o       ( usb_ref_val                ),
+    .ast_tl_req_o                 ( base_ast_bus               ),
+    .ast_tl_rsp_i                 ( ast_base_bus               ),
+    .adc_req_o                    ( adc_req                    ),
+    .adc_rsp_i                    ( adc_rsp                    ),
+    .ast_edn_req_i                ( ast_edn_edn_req            ),
+    .ast_edn_rsp_o                ( ast_edn_edn_rsp            ),
+    .otp_ctrl_otp_ast_pwr_seq_o   ( otp_ctrl_otp_ast_pwr_seq   ),
+    .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
+    .otp_alert_o                  ( otp_alert                  ),
+    .flash_bist_enable_i          ( flash_bist_enable          ),
+    .flash_power_down_h_i         ( flash_power_down_h         ),
+    .flash_power_ready_h_i        ( flash_power_ready_h        ),
+    .flash_alert_o                ( flash_alert                ),
+    .es_rng_req_o                 ( es_rng_req                 ),
+    .es_rng_rsp_i                 ( es_rng_rsp                 ),
+    .es_rng_fips_o                ( es_rng_fips                ),
+    .ast_clk_byp_req_o            ( ast_clk_byp_req            ),
+    .ast_clk_byp_ack_i            ( ast_clk_byp_ack            ),
+    .ast2pinmux_i                 ( ast2pinmux                 ),
+    .ast_init_done_i              ( ast_init_done              ),
+
+    // Flash test mode voltages
+    .flash_test_mode_a_io         ( {FLASH_TEST_MODE1,
+                                     FLASH_TEST_MODE0}         ),
+    .flash_test_voltage_h_io      ( FLASH_TEST_VOLT            ),
+
+    // OTP external voltage
+    .otp_ext_voltage_h_io         ( OTP_EXT_VOLT               ),
+
+    // Multiplexed I/O
+    .mio_in_i                     ( mio_in                     ),
+    .mio_out_o                    ( mio_out                    ),
+    .mio_oe_o                     ( mio_oe                     ),
+
+    // Dedicated I/O
+    .dio_in_i                     ( dio_in                     ),
+    .dio_out_o                    ( dio_out                    ),
+    .dio_oe_o                     ( dio_oe                     ),
+
+    // Pad attributes
+    .mio_attr_o                   ( mio_attr                   ),
+    .dio_attr_o                   ( dio_attr                   ),
+
+    // Memory attributes
+    .ram_1p_cfg_i                 ( ram_1p_cfg                 ),
+    .ram_2p_cfg_i                 ( ram_2p_cfg                 ),
+    .rom_cfg_i                    ( rom_cfg                    ),
+
+    // DFT signals
+    .ast_lc_dft_en_o              ( dft_en                     ),
+    .dft_strap_test_o             ( dft_strap_test             ),
+    .dft_hold_tap_sel_i           ( '0                         ),
+    .scan_rst_ni                  ( scan_rst_n                 ),
+    .scan_en_i                    ( scan_en                    ),
+    .scanmode_i                   ( scanmode                   )
+  );
+% endif
+
+###################################################################
+## FPGA shared                                                   ##
+###################################################################
+% if target["name"] in ["cw305", "nexysvideo"]:
+  //////////////////
+  // PLL for FPGA //
+  //////////////////
+
+  assign manual_out_io_clk = 1'b0;
+  assign manual_oe_io_clk = 1'b0;
+  assign manual_out_por_n = 1'b0;
+  assign manual_oe_por_n = 1'b0;
+  assign manual_out_io_jsrst_n = 1'b0;
+  assign manual_oe_io_jsrst_n = 1'b0;
+
+  logic clk_main, clk_usb_48mhz, clk_aon, rst_n;
+  clkgen_xil7series # (
+    .AddClkBuf(0)
+  ) clkgen (
+    .clk_i(manual_in_io_clk),
+    .rst_ni(manual_in_por_n),
+    .jtag_srst_ni(manual_in_io_jsrst_n),
+    .clk_main_o(clk_main),
+    .clk_48MHz_o(clk_usb_48mhz),
+    .clk_aon_o(clk_aon),
+    .rst_no(rst_n)
+  );
+
+  //////////////////////
+  // Top-level design //
+  //////////////////////
+  pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+  ast_pkg::ast_alert_req_t ast_base_alerts;
+  ast_pkg::ast_status_t ast_base_status;
+
+  assign ast_base_pwr.slow_clk_val = 1'b1;
+  assign ast_base_pwr.core_clk_val = 1'b1;
+  assign ast_base_pwr.io_clk_val   = 1'b1;
+  assign ast_base_pwr.usb_clk_val  = 1'b1;
+  assign ast_base_pwr.main_pok     = 1'b1;
+
+  ast_pkg::ast_dif_t silent_alert = '{
+                                       p: 1'b0,
+                                       n: 1'b1
+                                     };
+
+  assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
+  assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
+
+  // the rst_ni pin only goes to AST
+  // the rest of the logic generates reset based on the 'pok' signal.
+  // for verilator purposes, make these two the same.
+  lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
+
+% if target["name"] == "cw305":
+  // This is used for outputting the capture trigger
+  logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_pre;
+% endif
+
+// TODO: align this with ASIC version to minimize the duplication.
+// Also need to add AST simulation and FPGA emulation models for things like entropy source -
+// otherwise Verilator / FPGA will hang.
+  top_${top["name"]} #(
+% if target["name"] == "cw305":
+    .AesMasking(1'b1),
+    .AesSBoxImpl(aes_pkg::SBoxImplDom),
+    .SecAesStartTriggerDelay(40),
+    .SecAesAllowForcingMasks(1'b1),
+    .SecAesSkipPRNGReseeding(1'b1),
+    .IbexICache(0),
+    .BootRomInitFile(BootRomInitFile),
+% else:
+    .AesMasking(1'b0),
+    .AesSBoxImpl(aes_pkg::SBoxImplLut),
+    .SecAesStartTriggerDelay(0),
+    .SecAesAllowForcingMasks(1'b0),
+    .SecAesSkipPRNGReseeding(1'b0),
+    .EntropySrcStub(1'b1),
+    .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
+    .OtbnRegFile(otbn_pkg::RegFileFPGA),
+    .OtbnStub(1'b1),
+    .OtpCtrlMemInitFile(OtpCtrlMemInitFile),
+    .RomCtrlBootRomInitFile(BootRomInitFile),
+% endif
+    .IbexRegFile(ibex_pkg::RegFileFPGA),
+    .IbexPipeLine(1),
+    .SecureIbex(0),
+    .SramCtrlRetAonInstrExec(0),
+    .SramCtrlMainInstrExec(1),
+    .PinmuxAonTargetCfg(PinmuxTargetCfg)
+  ) top_${top["name"]} (
+    .rst_ni                       ( rst_n            ),
+    .clk_main_i                   ( clk_main         ),
+    .clk_io_i                     ( clk_main         ),
+    .clk_usb_i                    ( clk_usb_48mhz    ),
+    .clk_aon_i                    ( clk_aon          ),
+    .clks_ast_o                   (                  ),
+    .clk_main_jitter_en_o         (                  ),
+    .rsts_ast_o                   (                  ),
+    .pwrmgr_ast_req_o             (                  ),
+    .pwrmgr_ast_rsp_i             ( ast_base_pwr     ),
+    .sensor_ctrl_ast_alert_req_i  ( ast_base_alerts  ),
+    .sensor_ctrl_ast_alert_rsp_o  (                  ),
+    .sensor_ctrl_ast_status_i     ( ast_base_status  ),
+    .usbdev_usb_ref_val_o         (                  ),
+    .usbdev_usb_ref_pulse_o       (                  ),
+    .ast_edn_req_i                ( '0               ),
+    .ast_edn_rsp_o                (                  ),
+    .flash_bist_enable_i          ( lc_ctrl_pkg::Off ),
+    .flash_power_down_h_i         ( 1'b0             ),
+    .flash_power_ready_h_i        ( 1'b1             ),
+    .ast_clk_byp_req_o            ( lc_clk_bypass    ),
+    .ast_clk_byp_ack_i            ( lc_clk_bypass    ),
+
+% if target["name"] != "cw305":
+    .ast_tl_req_o                 (                  ),
+    .ast_tl_rsp_i                 ( '0               ),
+    .otp_ctrl_otp_ast_pwr_seq_o   (                  ),
+    .otp_ctrl_otp_ast_pwr_seq_h_i ( '0               ),
+    .otp_alert_o                  (                  ),
+    .es_rng_req_o                 (                  ),
+    .es_rng_rsp_i                 ( '0               ),
+    .es_rng_fips_o                (                  ),
+    .ast2pinmux_i                 ( '0               ),
+% endif
+
+    // Multiplexed I/O
+    .mio_in_i        ( mio_in   ),
+% if target["name"] == "cw305":
+    .mio_out_o       ( mio_out_pre  ),
+% else:
+    .mio_out_o       ( mio_out  ),
+% endif
+    .mio_oe_o        ( mio_oe   ),
+
+    // Dedicated I/O
+    .dio_in_i        ( dio_in   ),
+    .dio_out_o       ( dio_out  ),
+    .dio_oe_o        ( dio_oe   ),
+
+    // Pad attributes
+    .mio_attr_o      ( mio_attr      ),
+    .dio_attr_o      ( dio_attr      ),
+
+    // Memory attributes
+    .ram_1p_cfg_i    ( '0 ),
+    .ram_2p_cfg_i    ( '0 ),
+    .rom_cfg_i       ( '0 ),
+
+    // DFT signals
+    .dft_hold_tap_sel_i ( '0               ),
+    .scan_rst_ni        ( 1'b1             ),
+    .scan_en_i          ( 1'b0             ),
+    .scanmode_i         ( lc_ctrl_pkg::Off )
+  );
+% endif
+
+
+###################################################################
+## CW305 capture trigger                                         ##
+###################################################################
+% if target["name"] == "cw305":
+
+  //////////////////////////////////////
+  // Generate precise capture trigger //
+  //////////////////////////////////////
+
+  // TODO: make this a "manual" IO specific to the CW305 target
+  // such that we can decouple this from the MIO signals.
+  localparam int MioIdxTrigger = 15;
+
+  // To obtain a more precise capture trigger for side-channel analysis, we only forward the
+  // software-controlled capture trigger when the AES module is actually busy (performing
+  // either encryption/decryption or clearing internal registers).
+  // GPIO15 is used as capture trigger (mapped to IOB9 at the moment in pinmux.c).
+  always_comb begin : p_trigger
+    mio_out = mio_out_pre;
+    mio_out[MioIdxTrigger] = mio_out_pre[MioIdxTrigger] &
+                             ~top_englishbreakfast.clkmgr_aon_idle[clkmgr_pkg::Aes];
+  end
+
+  //////////////////////
+  // ChipWhisperer IO //
+  //////////////////////
+
+  logic unused_inputs;
+  assign unused_inputs = manual_in_tio_clkout ^ manual_in_io_utx_debug;
+
+  // Clock ouput to capture board.
+  assign manual_out_tio_clkout = manual_in_io_clk;
+  assign manual_oe_tio_clkout = 1'b1;
+
+  // UART Tx for debugging. The UART itself is connected to the capture board.
+  assign manual_out_io_utx_debug = top_${top["name"]}.cio_uart0_tx_d2p;
+  assign manual_oe_io_utx_debug = 1'b1;
+
+% endif
+
+endmodule : chip_${top["name"]}_${target["name"]}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/clang-format b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/clang-format
new file mode 100644
index 00000000..7cb47a7a
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/clang-format
@@ -0,0 +1,4 @@
+# This disables clang-format on all files in the sw/autogen directory.
+# This is needed so that git-clang-format and similar scripts work.
+DisableFormat: true
+SortIncludes: false
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__alert_handler_connect.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__alert_handler_connect.sv.tpl
new file mode 100644
index 00000000..559926a7
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__alert_handler_connect.sv.tpl
@@ -0,0 +1,21 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool
+
+<%
+  index = 0
+  module_name = ""
+%>\
+% for alert in top["alert"]:
+  % if alert["module_name"] == module_name:
+<% index = index + 1 %>\
+  % else:
+<%
+  module_name = alert["module_name"]
+  index = 0
+%>\
+  % endif
+assign alert_if[${loop.index}].alert_tx = `CHIP_HIER.u_${module_name}.alert_tx_o[${index}];
+% endfor
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__xbar_connect.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__xbar_connect.sv.tpl
new file mode 100644
index 00000000..d4910958
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/tb__xbar_connect.sv.tpl
@@ -0,0 +1,124 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tb__xbar_connect generated by `topgen.py` tool
+<%
+from collections import OrderedDict
+import topgen.lib as lib
+
+top_hier = 'tb.dut.top_' + top["name"] + '.'
+clk_hier = top_hier + top["clocks"]["hier_paths"]["top"]
+
+clk_src = OrderedDict()
+for xbar in top["xbar"]:
+  for clk, src in xbar["clock_srcs"].items():
+    clk_src[clk] = src
+
+clk_freq = OrderedDict()
+for clock in top["clocks"]["srcs"] + top["clocks"]["derived_srcs"]:
+  if clock["name"] in clk_src.values():
+    clk_freq[clock["name"]] = clock["freq"]
+
+hosts = OrderedDict()
+devices = OrderedDict()
+for xbar in top["xbar"]:
+  for node in xbar["nodes"]:
+    if node["type"] == "host" and not node["xbar"]:
+      hosts[node["name"]] = "clk_" + clk_src[node["clock"]]
+    elif node["type"] == "device" and not node["xbar"]:
+      devices[node["name"]] = "clk_" + clk_src[node["clock"]]
+
+def escape_if_name(qual_if_name):
+    return qual_if_name.replace('.', '__')
+
+%>\
+<%text>
+`define DRIVE_CHIP_TL_HOST_IF(tl_name, inst_name, sig_name) \
+     force ``tl_name``_tl_if.d2h = dut.top_earlgrey.u_``inst_name``.``sig_name``_i; \
+     force dut.top_earlgrey.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.h2d; \
+     force dut.top_earlgrey.u_``inst_name``.clk_i = 0; \
+     uvm_config_db#(virtual tl_if)::set(null, $sformatf("*%0s*", `"tl_name`"), "vif", \
+                                        ``tl_name``_tl_if);
+
+`define DRIVE_CHIP_TL_DEVICE_IF(tl_name, inst_name, sig_name) \
+     force ``tl_name``_tl_if.h2d = dut.top_earlgrey.u_``inst_name``.``sig_name``_i; \
+     force dut.top_earlgrey.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.d2h; \
+     force dut.top_earlgrey.u_``inst_name``.clk_i = 0; \
+     uvm_config_db#(virtual tl_if)::set(null, $sformatf("*%0s*", `"tl_name`"), "vif", \
+                                        ``tl_name``_tl_if);
+
+`define DRIVE_CHIP_TL_EXT_DEVICE_IF(tl_name, port_name) \
+     force ``tl_name``_tl_if.h2d = dut.top_earlgrey.``port_name``_req_o; \
+     force dut.top_earlgrey.``port_name``_rsp_i = ``tl_name``_tl_if.d2h; \
+     uvm_config_db#(virtual tl_if)::set(null, $sformatf("*%0s*", `"tl_name`"), "vif", \
+                                        ``tl_name``_tl_if);
+</%text>\
+
+% for c in clk_freq.keys():
+wire clk_${c};
+clk_rst_if clk_rst_if_${c}(.clk(clk_${c}), .rst_n(rst_n));
+% endfor
+
+% for i, clk in hosts.items():
+tl_if ${escape_if_name(i)}_tl_if(${clk}, rst_n);
+% endfor
+
+% for i, clk in devices.items():
+tl_if ${escape_if_name(i)}_tl_if(${clk}, rst_n);
+% endfor
+
+initial begin
+  bit xbar_mode;
+  void'($value$plusargs("xbar_mode=%0b", xbar_mode));
+  if (xbar_mode) begin
+    // only enable assertions in xbar as many pins are unconnected
+    $assertoff(0, tb);
+% for xbar in top["xbar"]:
+    $asserton(0, tb.dut.top_${top["name"]}.u_xbar_${xbar["name"]});
+% endfor
+
+% for c in clk_freq.keys():
+    clk_rst_if_${c}.set_active(.drive_rst_n_val(0));
+    clk_rst_if_${c}.set_freq_khz(${clk_freq[c]} / 1000);
+% endfor
+
+    // bypass clkmgr, force clocks directly
+% for xbar in top["xbar"]:
+  % for clk, src in xbar["clock_srcs"].items():
+    force ${top_hier}u_xbar_${xbar["name"]}.${clk} = clk_${src};
+  % endfor
+% endfor
+
+    // bypass rstmgr, force resets directly
+% for xbar in top["xbar"]:
+  % for rst in xbar["reset_connections"]:
+    force ${top_hier}u_xbar_${xbar["name"]}.${rst} = rst_n;
+  % endfor
+% endfor
+
+% for xbar in top["xbar"]:
+  % for node in xbar["nodes"]:
+<%
+clk = 'clk_' + clk_src[node["clock"]]
+esc_name = node['name'].replace('.', '__')
+inst_sig_list = lib.find_otherside_modules(top, xbar["name"], 'tl_' + esc_name)
+inst_name = inst_sig_list[0][1]
+sig_name = inst_sig_list[0][2]
+
+%>\
+    % if node["type"] == "host" and not node["xbar"]:
+    `DRIVE_CHIP_TL_HOST_IF(${esc_name}, ${inst_name}, ${sig_name})
+    % elif node["type"] == "device" and not node["xbar"] and node["stub"]:
+    `DRIVE_CHIP_TL_EXT_DEVICE_IF(${esc_name}, ${inst_name}_${sig_name})
+    % elif node["type"] == "device" and not node["xbar"]:
+    `DRIVE_CHIP_TL_DEVICE_IF(${esc_name}, ${inst_name}, ${sig_name})
+    % endif
+  % endfor
+% endfor
+  end
+end
+
+`undef DRIVE_CHIP_TL_HOST_IF
+`undef DRIVE_CHIP_TL_DEVICE_IF
+`undef DRIVE_CHIP_TL_EXT_DEVICE_IF
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.c.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.c.tpl
new file mode 100644
index 00000000..4cfbabe2
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.c.tpl
@@ -0,0 +1,21 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "${helper.header_path}"
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `${helper.plic_interrupts.name.as_c_type()}` to
+ * `${helper.plic_sources.name.as_c_type()}`.
+ */
+${helper.plic_mapping.render_definition()}
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `${helper.alert_alerts.name.as_c_type()}` to
+ * `${helper.alert_sources.name.as_c_type()}`.
+ */
+${helper.alert_mapping.render_definition()}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.h.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.h.tpl
new file mode 100644
index 00000000..24ba4100
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.h.tpl
@@ -0,0 +1,201 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _TOP_${top["name"].upper()}_H_
+#define _TOP_${top["name"].upper()}_H_
+
+/**
+ * @file
+ * @brief Top-specific Definitions
+ *
+ * This file contains preprocessor and type definitions for use within the
+ * device C/C++ codebase.
+ *
+ * These definitions are for information that depends on the top-specific chip
+ * configuration, which includes:
+ * - Device Memory Information (for Peripherals and Memory)
+ * - PLIC Interrupt ID Names and Source Mappings
+ * - Alert ID Names and Source Mappings
+ * - Pinmux Pin/Select Names
+ * - Power Manager Wakeups
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+% for (inst_name, if_name), region in helper.devices():
+<%
+    if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name)
+    hex_base_addr = "0x{:X}u".format(region.base_addr)
+    hex_size_bytes = "0x{:X}u".format(region.size_bytes)
+
+    base_addr_name = region.base_addr_name().as_c_define()
+    size_bytes_name = region.size_bytes_name().as_c_define()
+
+%>\
+/**
+ * Peripheral base address for ${if_desc} in top ${top["name"]}.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define ${base_addr_name} ${hex_base_addr}
+
+/**
+ * Peripheral size for ${if_desc} in top ${top["name"]}.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #${base_addr_name} and
+ * `${base_addr_name} + ${size_bytes_name}`.
+ */
+#define ${size_bytes_name} ${hex_size_bytes}
+
+% endfor
+
+% for name, region in helper.memories():
+<%
+    hex_base_addr = "0x{:X}u".format(region.base_addr)
+    hex_size_bytes = "0x{:X}u".format(region.size_bytes)
+
+    base_addr_name = region.base_addr_name().as_c_define()
+    size_bytes_name = region.size_bytes_name().as_c_define()
+
+%>\
+/**
+ * Memory base address for ${name} in top ${top["name"]}.
+ */
+#define ${base_addr_name} ${hex_base_addr}
+
+/**
+ * Memory size for ${name} in top ${top["name"]}.
+ */
+#define ${size_bytes_name} ${hex_size_bytes}
+
+% endfor
+
+/**
+ * PLIC Interrupt Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * interrupt.
+ */
+${helper.plic_sources.render()}
+
+/**
+ * PLIC Interrupt Source.
+ *
+ * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+${helper.plic_interrupts.render()}
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `${helper.plic_interrupts.name.as_c_type()}` to
+ * `${helper.plic_sources.name.as_c_type()}`.
+ */
+${helper.plic_mapping.render_declaration()}
+
+/**
+ * PLIC Interrupt Target.
+ *
+ * Enumeration used to determine which set of IE, CC, threshold registers to
+ * access for a given interrupt target.
+ */
+${helper.plic_targets.render()}
+
+/**
+ * Alert Handler Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * alert.
+ */
+${helper.alert_sources.render()}
+
+/**
+ * Alert Handler Alert Source.
+ *
+ * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+${helper.alert_alerts.render()}
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `${helper.alert_alerts.name.as_c_type()}` to
+ * `${helper.alert_sources.name.as_c_type()}`.
+ */
+${helper.alert_mapping.render_declaration()}
+
+#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
+
+// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
+//  0 and 1 are tied to value 0 and 1
+#define NUM_MIO_PADS ${top["pinmux"]["io_counts"]["muxed"]["pads"]}
+#define NUM_DIO_PADS ${top["pinmux"]["io_counts"]["dedicated"]["inouts"] + \
+                       top["pinmux"]["io_counts"]["dedicated"]["inputs"] + \
+                       top["pinmux"]["io_counts"]["dedicated"]["outputs"] }
+
+#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
+
+/**
+ * Pinmux Peripheral Input.
+ */
+${helper.pinmux_peripheral_in.render()}
+
+/**
+ * Pinmux MIO Input Selector.
+ */
+${helper.pinmux_insel.render()}
+
+/**
+ * Pinmux MIO Output.
+ */
+${helper.pinmux_mio_out.render()}
+
+/**
+ * Pinmux Peripheral Output Selector.
+ */
+${helper.pinmux_outsel.render()}
+
+/**
+ * Power Manager Wakeup Signals
+ */
+${helper.pwrmgr_wakeups.render()}
+
+/**
+ * Reset Manager Software Controlled Resets
+ */
+${helper.rstmgr_sw_rsts.render()}
+
+/**
+ * Power Manager Reset Request Signals
+ */
+${helper.pwrmgr_reset_requests.render()}
+
+/**
+ * Clock Manager Software-Controlled ("Gated") Clocks.
+ *
+ * The Software has full control over these clocks.
+ */
+${helper.clkmgr_gateable_clocks.render()}
+
+/**
+ * Clock Manager Software-Hinted Clocks.
+ *
+ * The Software has partial control over these clocks. It can ask them to stop,
+ * but the clock manager is in control of whether the clock actually is stopped.
+ */
+${helper.clkmgr_hintable_clocks.render()}
+
+// Header Extern Guard
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+
+#endif  // _TOP_${top["name"].upper()}_H_
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.sv.tpl
new file mode 100644
index 00000000..f0248b3c
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel.sv.tpl
@@ -0,0 +1,832 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+${gencmd}
+<%
+import re
+import topgen.lib as lib
+
+num_mio_inputs = top['pinmux']['io_counts']['muxed']['inouts'] + \
+                 top['pinmux']['io_counts']['muxed']['inputs']
+num_mio_outputs = top['pinmux']['io_counts']['muxed']['inouts'] + \
+                  top['pinmux']['io_counts']['muxed']['outputs']
+num_mio_pads = top['pinmux']['io_counts']['muxed']['pads']
+
+num_dio_inputs = top['pinmux']['io_counts']['dedicated']['inouts'] + \
+                 top['pinmux']['io_counts']['dedicated']['inputs']
+num_dio_outputs = top['pinmux']['io_counts']['dedicated']['inouts'] + \
+                  top['pinmux']['io_counts']['dedicated']['outputs']
+num_dio_total = top['pinmux']['io_counts']['dedicated']['inouts'] + \
+                top['pinmux']['io_counts']['dedicated']['inputs'] + \
+                top['pinmux']['io_counts']['dedicated']['outputs']
+
+num_im = sum([x["width"] if "width" in x else 1 for x in top["inter_signal"]["external"]])
+
+max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["ios"]])
+max_sigwidth = len("{}".format(max_sigwidth))
+
+clks_attr = top['clocks']
+cpu_clk = top['clocks']['hier_paths']['top'] + "clk_proc_main"
+cpu_rst = top["reset_paths"]["sys"]
+dm_rst = top["reset_paths"]["lc"]
+esc_clk = top['clocks']['hier_paths']['top'] + "clk_io_div4_timers"
+esc_rst = top["reset_paths"]["sys_io_div4"]
+
+unused_resets = lib.get_unused_resets(top)
+unused_im_defs, undriven_im_defs = lib.get_dangling_im_def(top["inter_signal"]["definitions"])
+
+has_toplevel_rom = False
+for m in top['memory']:
+  if m['type'] == 'rom':
+    has_toplevel_rom = True
+
+%>\
+module top_${top["name"]} #(
+  // Auto-inferred parameters
+% for m in top["module"]:
+  % if not lib.is_inst(m):
+<% continue %>
+  % endif
+  % for p_exp in filter(lambda p: p.get("expose") == "true", m["param_list"]):
+  parameter ${p_exp["type"]} ${p_exp["name_top"]} = ${p_exp["default"]},
+  % endfor
+% endfor
+
+  // Manually defined parameters
+% if has_toplevel_rom:
+  parameter     BootRomInitFile = "",
+% endif
+  parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
+  parameter bit IbexICache = 1,
+  parameter bit IbexPipeLine = 0,
+  parameter bit SecureIbex = 1
+) (
+  // Reset, clocks defined as part of intermodule
+  input               rst_ni,
+
+% if num_mio_pads != 0:
+  // Multiplexed I/O
+  input        ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_in_i,
+  output logic ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_out_o,
+  output logic ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_oe_o,
+% endif
+% if num_dio_total != 0:
+  // Dedicated I/O
+  input        ${lib.bitarray(num_dio_total, max_sigwidth)} dio_in_i,
+  output logic ${lib.bitarray(num_dio_total, max_sigwidth)} dio_out_o,
+  output logic ${lib.bitarray(num_dio_total, max_sigwidth)} dio_oe_o,
+% endif
+
+% if "pinmux" in top:
+  // pad attributes to padring
+  output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o,
+  output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o,
+% endif
+
+% if num_im != 0:
+
+  // Inter-module Signal External type
+  % for sig in top["inter_signal"]["external"]:
+  ${"input " if sig["direction"] == "in" else "output"} ${lib.im_defname(sig)} ${lib.bitarray(sig["width"],1)} ${sig["signame"]},
+  % endfor
+
+  // Flash specific voltages
+  inout [1:0] flash_test_mode_a_io,
+  inout flash_test_voltage_h_io,
+
+  // OTP specific voltages
+  inout otp_ext_voltage_h_io,
+
+% endif
+  input                      scan_rst_ni, // reset used for test mode
+  input                      scan_en_i,
+  input lc_ctrl_pkg::lc_tx_t scanmode_i   // lc_ctrl_pkg::On for Scan
+);
+
+  // JTAG IDCODE for development versions of this code.
+  // Manufacturers of OpenTitan chips must replace this code with one of their
+  // own IDs.
+  // Field structure as defined in the IEEE 1149.1 (JTAG) specification,
+  // section 12.1.1.
+  localparam logic [31:0] JTAG_IDCODE = {
+    4'h0,     // Version
+    16'h4F54, // Part Number: "OT"
+    11'h426,  // Manufacturer Identity: Google
+    1'b1      // (fixed)
+  };
+
+  import tlul_pkg::*;
+  import top_pkg::*;
+  import tl_main_pkg::*;
+  import top_${top["name"]}_pkg::*;
+  // Compile-time random constants
+  import top_${top["name"]}_rnd_cnst_pkg::*;
+
+  // Signals
+  logic [${num_mio_inputs - 1}:0] mio_p2d;
+  logic [${num_mio_outputs - 1}:0] mio_d2p;
+  logic [${num_mio_outputs - 1}:0] mio_en_d2p;
+  logic [${num_dio_total - 1}:0] dio_p2d;
+  logic [${num_dio_total - 1}:0] dio_d2p;
+  logic [${num_dio_total - 1}:0] dio_en_d2p;
+% for m in top["module"]:
+  % if not lib.is_inst(m):
+<% continue %>
+  % endif
+<%
+  block = name_to_block[m['type']]
+  inouts, inputs, outputs = block.xputs
+%>\
+  // ${m["name"]}
+  % for p_in in inputs + inouts:
+  logic ${lib.bitarray(p_in.bits.width(), max_sigwidth)} cio_${m["name"]}_${p_in.name}_p2d;
+  % endfor
+  % for p_out in outputs + inouts:
+  logic ${lib.bitarray(p_out.bits.width(), max_sigwidth)} cio_${m["name"]}_${p_out.name}_d2p;
+  logic ${lib.bitarray(p_out.bits.width(), max_sigwidth)} cio_${m["name"]}_${p_out.name}_en_d2p;
+  % endfor
+% endfor
+
+
+<%
+  # Interrupt source 0 is tied to 0 to conform RISC-V PLIC spec.
+  # So, total number of interrupts are the number of entries in the list + 1
+  interrupt_num = sum([x["width"] if "width" in x else 1 for x in top["interrupt"]]) + 1
+%>\
+  logic [${interrupt_num-1}:0]  intr_vector;
+  // Interrupt source list
+% for m in top["module"]:
+<%
+  block = name_to_block[m['type']]
+%>\
+    % if not lib.is_inst(m):
+<% continue %>
+    % endif
+    % for intr in block.interrupts:
+        % if intr.bits.width() != 1:
+  logic [${intr.bits.width()-1}:0] intr_${m["name"]}_${intr.name};
+        % else:
+  logic intr_${m["name"]}_${intr.name};
+        % endif
+    % endfor
+% endfor
+
+
+<% add_spaces = " " * len(str((interrupt_num-1).bit_length()-1)) %>
+  logic [0:0]${add_spaces}irq_plic;
+  logic [0:0]${add_spaces}msip;
+  logic [${(interrupt_num-1).bit_length()-1}:0] irq_id[1];
+  logic [${(interrupt_num-1).bit_length()-1}:0] unused_irq_id[1];
+
+  // this avoids lint errors
+  assign unused_irq_id = irq_id;
+
+  // Alert list
+  prim_alert_pkg::alert_tx_t [alert_pkg::NAlerts-1:0]  alert_tx;
+  prim_alert_pkg::alert_rx_t [alert_pkg::NAlerts-1:0]  alert_rx;
+
+% if not top["alert"]:
+  for (genvar k = 0; k < alert_pkg::NAlerts; k++) begin : gen_alert_tie_off
+    // tie off if no alerts present in the system
+    assign alert_tx[k].alert_p = 1'b0;
+    assign alert_tx[k].alert_n = 1'b1;
+  end
+% endif
+
+## Inter-module Definitions
+% if len(top["inter_signal"]["definitions"]) >= 1:
+  // define inter-module signals
+% endif
+% for sig in top["inter_signal"]["definitions"]:
+  ${lib.im_defname(sig)} ${lib.bitarray(sig["width"],1)} ${sig["signame"]};
+% endfor
+
+## Mixed connection to port
+## Index greater than 0 means a port is assigned to an inter-module array
+## whereas an index of 0 means a port is directly driven by a module
+  // define mixed connection to port
+% for port in top['inter_signal']['external']:
+  % if port['conn_type'] and port['index'] > 0:
+    % if port['direction'] == 'in':
+  assign ${port['netname']}[${port['index']}] = ${port['signame']};
+    % else:
+  assign ${port['signame']} = ${port['netname']}[${port['index']}];
+    % endif
+  % elif port['conn_type']:
+    % if port['direction'] == 'in':
+  assign ${port['netname']} = ${port['signame']};
+    % else:
+  assign ${port['signame']} = ${port['netname']};
+    % endif
+  % endif
+% endfor
+
+## Partial inter-module definition tie-off
+  // define partial inter-module tie-off
+% for sig in unused_im_defs:
+  % for idx in range(sig['end_idx'], sig['width']):
+  ${lib.im_defname(sig)} unused_${sig["signame"]}${idx};
+  % endfor
+% endfor
+
+  // assign partial inter-module tie-off
+% for sig in unused_im_defs:
+  % for idx in range(sig['end_idx'], sig['width']):
+  assign unused_${sig["signame"]}${idx} = ${sig["signame"]}[${idx}];
+  % endfor
+% endfor
+% for sig in undriven_im_defs:
+  % for idx in range(sig['end_idx'], sig['width']):
+  assign ${sig["signame"]}[${idx}] = ${sig["default"]};
+  % endfor
+% endfor
+
+## Inter-module signal collection
+
+  // Unused reset signals
+% for k, v in unused_resets.items():
+  logic unused_d${v.lower()}_rst_${k};
+% endfor
+% for k, v in unused_resets.items():
+  assign unused_d${v.lower()}_rst_${k} = ${lib.get_reset_path(k, v, top['resets'])};
+% endfor
+
+  // Non-debug module reset == reset for everything except for the debug module
+  logic ndmreset_req;
+
+  // debug request from rv_dm to core
+  logic debug_req;
+
+  // processor core
+  rv_core_ibex #(
+    .PMPEnable                (1),
+    .PMPGranularity           (0), // 2^(PMPGranularity+2) == 4 byte granularity
+    .PMPNumRegions            (16),
+    .MHPMCounterNum           (10),
+    .MHPMCounterWidth         (32),
+    .RV32E                    (0),
+    .RV32M                    (ibex_pkg::RV32MSingleCycle),
+    .RV32B                    (ibex_pkg::RV32BNone),
+    .RegFile                  (IbexRegFile),
+    .BranchTargetALU          (1),
+    .WritebackStage           (1),
+    .ICache                   (IbexICache),
+    .ICacheECC                (1),
+    .BranchPredictor          (0),
+    .DbgTriggerEn             (1),
+    .SecureIbex               (SecureIbex),
+    .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress[31:0]),
+    .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress[31:0]),
+    .PipeLine                 (IbexPipeLine)
+  ) u_rv_core_ibex (
+    // clock and reset
+    .clk_i                (${cpu_clk}),
+    .rst_ni               (${cpu_rst}[rstmgr_pkg::Domain0Sel]),
+    .clk_esc_i            (${esc_clk}),
+    .rst_esc_ni           (${esc_rst}[rstmgr_pkg::Domain0Sel]),
+    .ram_cfg_i            (ast_ram_1p_cfg),
+    // static pinning
+    .hart_id_i            (32'b0),
+    .boot_addr_i          (ADDR_SPACE_ROM_CTRL__ROM),
+    // TL-UL buses
+    .tl_i_o               (main_tl_corei_req),
+    .tl_i_i               (main_tl_corei_rsp),
+    .tl_d_o               (main_tl_cored_req),
+    .tl_d_i               (main_tl_cored_rsp),
+    // interrupts
+    .irq_software_i       (msip),
+    .irq_timer_i          (intr_rv_timer_timer_expired_0_0),
+    .irq_external_i       (irq_plic),
+    // escalation input from alert handler (NMI)
+    .esc_tx_i             (alert_handler_esc_tx[0]),
+    .esc_rx_o             (alert_handler_esc_rx[0]),
+    // debug interface
+    .debug_req_i          (debug_req),
+    // crash dump interface
+    .crash_dump_o         (rv_core_ibex_crash_dump),
+    // CPU control signals
+    .lc_cpu_en_i          (lc_ctrl_lc_cpu_en),
+    .pwrmgr_cpu_en_i      (pwrmgr_aon_fetch_en),
+    .core_sleep_o         (pwrmgr_aon_pwr_cpu.core_sleeping),
+
+    // dft bypass
+    .scan_rst_ni,
+    .scanmode_i
+  );
+
+  // Debug Module (RISC-V Debug Spec 0.13)
+  //
+
+  rv_dm #(
+    .NrHarts     (1),
+    .IdcodeValue (JTAG_IDCODE)
+  ) u_dm_top (
+    .clk_i         (${cpu_clk}),
+    .rst_ni        (${dm_rst}[rstmgr_pkg::Domain0Sel]),
+    .hw_debug_en_i (lc_ctrl_lc_hw_debug_en),
+    .scanmode_i,
+    .scan_rst_ni,
+    .ndmreset_o    (ndmreset_req),
+    .dmactive_o    (),
+    .debug_req_o   (debug_req),
+    .unavailable_i (1'b0),
+
+    // bus device with debug memory (for execution-based debug)
+    .tl_d_i        (main_tl_debug_mem_req),
+    .tl_d_o        (main_tl_debug_mem_rsp),
+
+    // bus host (for system bus accesses, SBA)
+    .tl_h_o        (main_tl_dm_sba_req),
+    .tl_h_i        (main_tl_dm_sba_rsp),
+
+    //JTAG
+    .jtag_req_i    (pinmux_aon_rv_jtag_req),
+    .jtag_rsp_o    (pinmux_aon_rv_jtag_rsp)
+  );
+
+  assign rstmgr_aon_cpu.ndmreset_req = ndmreset_req;
+  assign rstmgr_aon_cpu.rst_cpu_n = ${top["reset_paths"]["sys"]}[rstmgr_pkg::Domain0Sel];
+
+## Memory Instantiation
+% for m in top["memory"]:
+<%
+  resets = m['reset_connections']
+  clocks = m['clock_connections']
+%>\
+  % if m["type"] == "ram_1p_scr":
+<%
+     data_width = int(top["datawidth"])
+     full_data_width = data_width + int(m["integ_width"])
+     dw_byte = data_width // 8
+     addr_width = ((int(m["size"], 0) // dw_byte) -1).bit_length()
+     sram_depth = (int(m["size"], 0) // dw_byte)
+     max_char = len(str(max(data_width, addr_width)))
+%>\
+  // sram device
+  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_req;
+  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_gnt;
+  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_we;
+  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_intg_err;
+  logic ${lib.bitarray(addr_width, max_char)} ${m["name"]}_addr;
+  logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_wdata;
+  logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_wmask;
+  logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_rdata;
+  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_rvalid;
+  logic ${lib.bitarray(2,          max_char)} ${m["name"]}_rerror;
+
+  tlul_adapter_sram #(
+    .SramAw(${addr_width}),
+    .SramDw(${data_width}),
+    .Outstanding(2),
+    .CmdIntgCheck(1),
+    .EnableRspIntgGen(1),
+    .EnableDataIntgGen(0),
+    .EnableDataIntgPt(1)
+  ) u_tl_adapter_${m["name"]} (
+    % for key in clocks:
+    .${key}   (${clocks[key]}),
+    % endfor
+    % for key, value in resets.items():
+    .${key}   (${value}),
+    % endfor
+    .tl_i        (${m["name"]}_tl_req),
+    .tl_o        (${m["name"]}_tl_rsp),
+    .en_ifetch_i (${m["inter_signal_list"][3]["top_signame"]}),
+    .req_o       (${m["name"]}_req),
+    .req_type_o  (),
+    .gnt_i       (${m["name"]}_gnt),
+    .we_o        (${m["name"]}_we),
+    .addr_o      (${m["name"]}_addr),
+    .wdata_o     (${m["name"]}_wdata),
+    .wmask_o     (${m["name"]}_wmask),
+    .intg_error_o(${m["name"]}_intg_err),
+    .rdata_i     (${m["name"]}_rdata),
+    .rvalid_i    (${m["name"]}_rvalid),
+    .rerror_i    (${m["name"]}_rerror)
+  );
+
+<%
+mem_name = m["name"].split("_")
+mem_name = lib.Name(mem_name[1:])
+%>\
+  prim_ram_1p_scr #(
+    .Width(${full_data_width}),
+    .Depth(${sram_depth}),
+    .EnableParity(0),
+    .LfsrWidth(${data_width}),
+    .StatePerm(RndCnstSramCtrl${mem_name.as_camel_case()}SramLfsrPerm),
+    .DataBitsPerMask(1), // TODO: Temporary change to ensure byte updates can still be done
+    .DiffWidth(8)
+  ) u_ram1p_${m["name"]} (
+    % for key in clocks:
+    .${key}   (${clocks[key]}),
+    % endfor
+    % for key, value in resets.items():
+    .${key}   (${value}),
+    % endfor
+
+    .key_valid_i (${m["inter_signal_list"][1]["top_signame"]}_req.valid),
+    .key_i       (${m["inter_signal_list"][1]["top_signame"]}_req.key),
+    .nonce_i     (${m["inter_signal_list"][1]["top_signame"]}_req.nonce),
+    .init_req_i  (${m["inter_signal_list"][2]["top_signame"]}_req.req),
+    .init_seed_i (${m["inter_signal_list"][2]["top_signame"]}_req.seed),
+    .init_ack_o  (${m["inter_signal_list"][2]["top_signame"]}_rsp.ack),
+
+    .req_i       (${m["name"]}_req),
+    .intg_error_i(${m["name"]}_intg_err),
+    .gnt_o       (${m["name"]}_gnt),
+    .write_i     (${m["name"]}_we),
+    .addr_i      (${m["name"]}_addr),
+    .wdata_i     (${m["name"]}_wdata),
+    .wmask_i     (${m["name"]}_wmask),
+    .rdata_o     (${m["name"]}_rdata),
+    .rvalid_o    (${m["name"]}_rvalid),
+    .rerror_o    (${m["name"]}_rerror),
+    .raddr_o     (${m["inter_signal_list"][1]["top_signame"]}_rsp.raddr),
+    .intg_error_o(${m["inter_signal_list"][4]["top_signame"]}),
+    .cfg_i       (ram_1p_cfg_i)
+  );
+
+  assign ${m["inter_signal_list"][1]["top_signame"]}_rsp.rerror = ${m["name"]}_rerror;
+
+  % elif m["type"] == "rom":
+<%
+     data_width = int(top["datawidth"])
+     full_data_width = data_width + int(m['integ_width'])
+     dw_byte = data_width // 8
+     addr_width = ((int(m["size"], 0) // dw_byte) -1).bit_length()
+     rom_depth = (int(m["size"], 0) // dw_byte)
+     max_char = len(str(max(data_width, addr_width)))
+%>\
+  // ROM device
+  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_req;
+  logic ${lib.bitarray(addr_width, max_char)} ${m["name"]}_addr;
+  logic ${lib.bitarray(full_data_width, max_char)} ${m["name"]}_rdata;
+  logic ${lib.bitarray(1,          max_char)} ${m["name"]}_rvalid;
+
+  tlul_adapter_sram #(
+    .SramAw(${addr_width}),
+    .SramDw(${data_width}),
+    .Outstanding(2),
+    .ErrOnWrite(1),
+    .CmdIntgCheck(1),
+    .EnableRspIntgGen(1),
+    .EnableDataIntgGen(1) // TODO: Needs to be updated for intgerity passthrough
+  ) u_tl_adapter_${m["name"]} (
+    % for key in clocks:
+    .${key}   (${clocks[key]}),
+    % endfor
+    % for key, value in resets.items():
+    .${key}   (${value}),
+    % endfor
+
+    .tl_i        (${m["name"]}_tl_req),
+    .tl_o        (${m["name"]}_tl_rsp),
+    .en_ifetch_i (tlul_pkg::InstrEn),
+    .req_o       (${m["name"]}_req),
+    .req_type_o  (),
+    .gnt_i       (1'b1), // Always grant as only one requester exists
+    .we_o        (),
+    .addr_o      (${m["name"]}_addr),
+    .wdata_o     (),
+    .wmask_o     (),
+    .intg_error_o(), // Connect to ROM checker and ROM scramble later
+    .rdata_i     (${m["name"]}_rdata[${data_width-1}:0]),
+    .rvalid_i    (${m["name"]}_rvalid),
+    .rerror_i    (2'b00)
+  );
+
+  prim_rom_adv #(
+    .Width(${full_data_width}),
+    .Depth(${rom_depth}),
+    .MemInitFile(BootRomInitFile)
+  ) u_rom_${m["name"]} (
+    % for key in clocks:
+    .${key}   (${clocks[key]}),
+    % endfor
+    % for key, value in resets.items():
+    .${key}   (${value}),
+    % endfor
+    .req_i    (${m["name"]}_req),
+    .addr_i   (${m["name"]}_addr),
+    .rdata_o  (${m["name"]}_rdata),
+    .rvalid_o (${m["name"]}_rvalid),
+    .cfg_i    (rom_cfg_i)
+  );
+
+  % elif m["type"] == "eflash":
+
+  // host to flash communication
+  logic flash_host_req;
+  tlul_pkg::tl_type_e flash_host_req_type;
+  logic flash_host_req_rdy;
+  logic flash_host_req_done;
+  logic flash_host_rderr;
+  logic [flash_ctrl_pkg::BusWidth-1:0] flash_host_rdata;
+  logic [flash_ctrl_pkg::BusAddrW-1:0] flash_host_addr;
+  logic flash_host_intg_err;
+
+  tlul_adapter_sram #(
+    .SramAw(flash_ctrl_pkg::BusAddrW),
+    .SramDw(flash_ctrl_pkg::BusWidth),
+    .Outstanding(2),
+    .ByteAccess(0),
+    .ErrOnWrite(1),
+    .CmdIntgCheck(1),
+    .EnableRspIntgGen(1),
+    .EnableDataIntgGen(1)
+  ) u_tl_adapter_${m["name"]} (
+    % for key in clocks:
+    .${key}   (${clocks[key]}),
+    % endfor
+    % for key, value in resets.items():
+    .${key}   (${value}),
+    % endfor
+
+    .tl_i        (${m["name"]}_tl_req),
+    .tl_o        (${m["name"]}_tl_rsp),
+    .en_ifetch_i (tlul_pkg::InstrEn), // tie this to secure boot somehow
+    .req_o       (flash_host_req),
+    .req_type_o  (flash_host_req_type),
+    .gnt_i       (flash_host_req_rdy),
+    .we_o        (),
+    .addr_o      (flash_host_addr),
+    .wdata_o     (),
+    .wmask_o     (),
+    .intg_error_o(flash_host_intg_err),
+    .rdata_i     (flash_host_rdata),
+    .rvalid_i    (flash_host_req_done),
+    .rerror_i    ({flash_host_rderr,1'b0})
+  );
+
+  flash_phy u_flash_${m["name"]} (
+    % for key in clocks:
+    .${key}   (${clocks[key]}),
+    % endfor
+    % for key, value in resets.items():
+    .${key}   (${value}),
+    % endfor
+    .host_req_i        (flash_host_req),
+    .host_intg_err_i   (flash_host_intg_err),
+    .host_req_type_i   (flash_host_req_type),
+    .host_addr_i       (flash_host_addr),
+    .host_req_rdy_o    (flash_host_req_rdy),
+    .host_req_done_o   (flash_host_req_done),
+    .host_rderr_o      (flash_host_rderr),
+    .host_rdata_o      (flash_host_rdata),
+    .flash_ctrl_i      (${m["inter_signal_list"][0]["top_signame"]}_req),
+    .flash_ctrl_o      (${m["inter_signal_list"][0]["top_signame"]}_rsp),
+    .lc_nvm_debug_en_i (${m["inter_signal_list"][2]["top_signame"]}),
+    .flash_bist_enable_i,
+    .flash_power_down_h_i,
+    .flash_power_ready_h_i,
+    .flash_test_mode_a_io,
+    .flash_test_voltage_h_io,
+    .flash_alert_o,
+    .scanmode_i,
+    .scan_en_i,
+    .scan_rst_ni
+  );
+
+  % else:
+    // flash memory is embedded within controller
+  % endif
+% endfor
+## Peripheral Instantiation
+
+<% alert_idx = 0 %>
+% for m in top["module"]:
+<%
+if not lib.is_inst(m):
+     continue
+
+block = name_to_block[m['type']]
+inouts, inputs, outputs = block.xputs
+
+port_list = inputs + outputs + inouts
+max_sigwidth = max(len(x.name) for x in port_list) if port_list else 0
+max_intrwidth = (max(len(x.name) for x in block.interrupts)
+                 if block.interrupts else 0)
+%>\
+  % if m["param_list"] or block.alerts:
+  ${m["type"]} #(
+  % if block.alerts:
+<%
+w = len(block.alerts)
+slice = str(alert_idx+w-1) + ":" + str(alert_idx)
+%>\
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[${slice}])${"," if m["param_list"] else ""}
+  % endif
+    % for i in m["param_list"]:
+    .${i["name"]}(${i["name_top" if i.get("expose") == "true" or i.get("randtype", "none") != "none" else "default"]})${"," if not loop.last else ""}
+    % endfor
+  ) u_${m["name"]} (
+  % else:
+  ${m["type"]} u_${m["name"]} (
+  % endif
+    % for p_in in inputs + inouts:
+      % if loop.first:
+
+      // Input
+      % endif
+      .${lib.ljust("cio_"+p_in.name+"_i",max_sigwidth+9)} (cio_${m["name"]}_${p_in.name}_p2d),
+    % endfor
+    % for p_out in outputs + inouts:
+      % if loop.first:
+
+      // Output
+      % endif
+      .${lib.ljust("cio_"+p_out.name+"_o",   max_sigwidth+9)} (cio_${m["name"]}_${p_out.name}_d2p),
+      .${lib.ljust("cio_"+p_out.name+"_en_o",max_sigwidth+9)} (cio_${m["name"]}_${p_out.name}_en_d2p),
+    % endfor
+    % for intr in block.interrupts:
+      % if loop.first:
+
+      // Interrupt
+      % endif
+      .${lib.ljust("intr_"+intr.name+"_o",max_intrwidth+7)} (intr_${m["name"]}_${intr.name}),
+    % endfor
+    % if block.alerts:
+      % for alert in block.alerts:
+      // [${alert_idx}]: ${alert.name}<% alert_idx += 1 %>
+      % endfor
+      .alert_tx_o  ( alert_tx[${slice}] ),
+      .alert_rx_i  ( alert_rx[${slice}] ),
+    % endif
+    ## TODO: Inter-module Connection
+    % if m.get('inter_signal_list'):
+
+      // Inter-module signals
+      % for sig in m['inter_signal_list']:
+        ## TODO: handle below condition in lib.py
+        % if sig['type'] == "req_rsp":
+      .${lib.im_portname(sig,"req")}(${lib.im_netname(sig, "req")}),
+      .${lib.im_portname(sig,"rsp")}(${lib.im_netname(sig, "rsp")}),
+        % elif sig['type'] == "uni":
+          ## TODO: Broadcast type
+          ## TODO: default for logic type
+      .${lib.im_portname(sig)}(${lib.im_netname(sig)}),
+        % endif
+      % endfor
+    % endif
+    % if m["type"] == "rv_plic":
+
+      .intr_src_i (intr_vector),
+      .irq_o      (irq_plic),
+      .irq_id_o   (irq_id),
+      .msip_o     (msip),
+    % endif
+    % if m["type"] == "pinmux":
+
+      .periph_to_mio_i      (mio_d2p    ),
+      .periph_to_mio_oe_i   (mio_en_d2p ),
+      .mio_to_periph_o      (mio_p2d    ),
+
+      .mio_attr_o,
+      .mio_out_o,
+      .mio_oe_o,
+      .mio_in_i,
+
+      .periph_to_dio_i      (dio_d2p    ),
+      .periph_to_dio_oe_i   (dio_en_d2p ),
+      .dio_to_periph_o      (dio_p2d    ),
+
+      .dio_attr_o,
+      .dio_out_o,
+      .dio_oe_o,
+      .dio_in_i,
+
+    % endif
+    % if m["type"] == "alert_handler":
+      // alert signals
+      .alert_rx_o  ( alert_rx ),
+      .alert_tx_i  ( alert_tx ),
+    % endif
+    % if m["type"] == "otp_ctrl":
+      .otp_ext_voltage_h_io,
+    % endif
+    % if block.scan:
+      .scanmode_i,
+    % endif
+    % if block.scan_reset:
+      .scan_rst_ni,
+    % endif
+    % if block.scan_en:
+      .scan_en_i,
+    % endif
+
+      // Clock and reset connections
+    % for k, v in m["clock_connections"].items():
+      .${k} (${v}),
+    % endfor
+    % for k, v in m["reset_connections"].items():
+      .${k} (${v})${"," if not loop.last else ""}
+    % endfor
+  );
+
+% endfor
+  // interrupt assignments
+<% base = interrupt_num %>\
+  assign intr_vector = {
+  % for intr in top["interrupt"][::-1]:
+<% base -= intr["width"] %>\
+      intr_${intr["name"]}, // IDs [${base} +: ${intr['width']}]
+  % endfor
+      1'b 0 // ID [0 +: 1] is a special case and tied to zero.
+  };
+
+  // TL-UL Crossbar
+% for xbar in top["xbar"]:
+<%
+  name_len = max([len(x["name"]) for x in xbar["nodes"]]);
+%>\
+  xbar_${xbar["name"]} u_xbar_${xbar["name"]} (
+  % for k, v in xbar["clock_connections"].items():
+    .${k} (${v}),
+  % endfor
+  % for k, v in xbar["reset_connections"].items():
+    .${k} (${v}),
+  % endfor
+
+  ## Inter-module signal
+  % for sig in xbar["inter_signal_list"]:
+<% assert sig['type'] == "req_rsp" %>\
+    // port: ${sig['name']}
+    .${lib.im_portname(sig,"req")}(${lib.im_netname(sig, "req")}),
+    .${lib.im_portname(sig,"rsp")}(${lib.im_netname(sig, "rsp")}),
+
+  % endfor
+
+    .scanmode_i
+  );
+% endfor
+
+% if "pinmux" in top:
+  // Pinmux connections
+  // All muxed inputs
+  % for sig in top["pinmux"]["ios"]:
+    % if sig["connection"] == "muxed" and sig["type"] in ["inout", "input"]:
+<% literal = lib.get_io_enum_literal(sig, 'mio_in') %>\
+  assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""} = mio_p2d[${literal}];
+    % endif
+  % endfor
+
+  // All muxed outputs
+  % for sig in top["pinmux"]["ios"]:
+    % if sig["connection"] == "muxed" and sig["type"] in ["inout", "output"]:
+<% literal = lib.get_io_enum_literal(sig, 'mio_out') %>\
+  assign mio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""};
+    % endif
+  % endfor
+
+  // All muxed output enables
+  % for sig in top["pinmux"]["ios"]:
+    % if sig["connection"] == "muxed" and sig["type"] in ["inout", "output"]:
+<% literal = lib.get_io_enum_literal(sig, 'mio_out') %>\
+  assign mio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""};
+    % endif
+  % endfor
+
+  // All dedicated inputs
+<% idx = 0 %>\
+  logic [${num_dio_total-1}:0] unused_dio_p2d;
+  assign unused_dio_p2d = dio_p2d;
+  % for sig in top["pinmux"]["ios"]:
+<% literal = lib.get_io_enum_literal(sig, 'dio') %>\
+    % if sig["connection"] != "muxed" and sig["type"] in ["inout"]:
+  assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""} = dio_p2d[${literal}];
+    % elif sig["connection"] != "muxed" and sig["type"] in ["input"]:
+  assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""} = dio_p2d[${literal}];
+    % endif
+  % endfor
+
+    // All dedicated outputs
+  % for sig in top["pinmux"]["ios"]:
+<% literal = lib.get_io_enum_literal(sig, 'dio') %>\
+    % if sig["connection"] != "muxed" and sig["type"] in ["inout"]:
+  assign dio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""};
+    % elif sig["connection"] != "muxed" and sig["type"] in ["input"]:
+  assign dio_d2p[${literal}] = 1'b0;
+    % elif sig["connection"] != "muxed" and sig["type"] in ["output"]:
+  assign dio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""};
+    % endif
+  % endfor
+
+  // All dedicated output enables
+  % for sig in top["pinmux"]["ios"]:
+<% literal = lib.get_io_enum_literal(sig, 'dio') %>\
+    % if sig["connection"] != "muxed" and sig["type"] in ["inout"]:
+  assign dio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""};
+    % elif sig["connection"] != "muxed" and sig["type"] in ["input"]:
+  assign dio_en_d2p[${literal}] = 1'b0;
+    % elif sig["connection"] != "muxed" and sig["type"] in ["output"]:
+  assign dio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1  else ""};
+    % endif
+  % endfor
+
+% endif
+
+  // make sure scanmode_i is never X (including during reset)
+  `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_main_i, 0)
+
+endmodule
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.h.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.h.tpl
new file mode 100644
index 00000000..bfb0274a
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.h.tpl
@@ -0,0 +1,62 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _TOP_${top["name"].upper()}_MEMORY_H_
+#define _TOP_${top["name"].upper()}_MEMORY_H_
+
+/**
+ * @file
+ * @brief Assembler-only Top-Specific Definitions.
+ *
+ * This file contains preprocessor definitions for use within assembly code.
+ *
+ * These are not shared with C/C++ code because these are only allowed to be
+ * preprocessor definitions, no data or type declarations are allowed. The
+ * assembler is also stricter about literals (not allowing suffixes for
+ * signed/unsigned which are sensible to use for unsigned values in C/C++).
+ */
+
+// Include guard for assembler
+#ifdef __ASSEMBLER__
+
+/**
+ * Memory base address for rom in top earlgrey.
+ */
+#define TOP_EARLGREY_ROM_BASE_ADDR 0x00008000
+
+/**
+ * Memory size for rom in top earlgrey.
+ */
+#define TOP_EARLGREY_ROM_SIZE_BYTES 0x4000
+
+% for m in top["memory"]:
+/**
+ * Memory base address for ${m["name"]} in top ${top["name"]}.
+ */
+#define TOP_${top["name"].upper()}_${m["name"].upper()}_BASE_ADDR ${m["base_addr"]}
+
+/**
+ * Memory size for ${m["name"]} in top ${top["name"]}.
+ */
+#define TOP_${top["name"].upper()}_${m["name"].upper()}_SIZE_BYTES ${m["size"]}
+
+% endfor
+
+% for (inst_name, if_name), region in helper.devices():
+<%
+    if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name)
+    hex_base_addr = "0x{:X}".format(region.base_addr)
+    base_addr_name = region.base_addr_name().as_c_define()
+%>\
+/**
+ * Peripheral base address for ${if_desc} in top ${top["name"]}.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define ${base_addr_name} ${hex_base_addr}
+% endfor
+#endif  // __ASSEMBLER__
+
+#endif  // _TOP_${top["name"].upper()}_MEMORY_H_
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.ld.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.ld.tpl
new file mode 100644
index 00000000..42c41989
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_memory.ld.tpl
@@ -0,0 +1,30 @@
+/* Copyright lowRISC contributors. */
+/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
+/* SPDX-License-Identifier: Apache-2.0 */
+<%!
+def memory_to_flags(memory):
+    memory_type = memory["type"]
+    memory_access = memory.get("swaccess", "rw")
+    assert memory_access in ["ro", "rw"]
+
+    flags_str = ""
+    if memory_access == "ro":
+        flags_str += "r"
+    else:
+        flags_str += "rw"
+
+    if memory_type in ["rom", "eflash"]:
+        flags_str += "x"
+
+    return flags_str
+%>\
+
+/**
+ * Partial linker script for chip memory configuration.
+ */
+MEMORY {
+  rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x4000
+% for m in top["memory"]:
+  ${m["name"]}(${memory_to_flags(m)}) : ORIGIN = ${m["base_addr"]}, LENGTH = ${m["size"]}
+% endfor
+}
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_pkg.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_pkg.sv.tpl
new file mode 100644
index 00000000..a25d4fd7
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_pkg.sv.tpl
@@ -0,0 +1,112 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+${gencmd}
+<%
+import topgen.lib as lib
+%>\
+package top_${top["name"]}_pkg;
+% for (inst_name, if_name), region in helper.devices():
+<%
+    if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name)
+    hex_base_addr = "32'h{:X}".format(region.base_addr)
+    hex_size_bytes = "32'h{:X}".format(region.size_bytes)
+%>\
+  /**
+   * Peripheral base address for ${if_desc} in top ${top["name"]}.
+   */
+  parameter int unsigned ${region.base_addr_name().as_c_define()} = ${hex_base_addr};
+
+  /**
+   * Peripheral size in bytes for ${if_desc} in top ${top["name"]}.
+   */
+  parameter int unsigned ${region.size_bytes_name().as_c_define()} = ${hex_size_bytes};
+
+% endfor
+% for name, region in helper.memories():
+<%
+    hex_base_addr = "32'h{:x}".format(region.base_addr)
+    hex_size_bytes = "32'h{:x}".format(region.size_bytes)
+%>\
+  /**
+   * Memory base address for ${name} in top ${top["name"]}.
+   */
+  parameter int unsigned ${region.base_addr_name().as_c_define()} = ${hex_base_addr};
+
+  /**
+   * Memory size for ${name} in top ${top["name"]}.
+   */
+  parameter int unsigned ${region.size_bytes_name().as_c_define()} = ${hex_size_bytes};
+
+% endfor
+
+  // Enumeration of IO power domains.
+  // Only used in ASIC target.
+  typedef enum logic [${len(top["pinout"]["banks"]).bit_length()-1}:0] {
+% for bank in top["pinout"]["banks"]:
+    ${lib.Name(['io', 'bank', bank]).as_camel_case()} = ${loop.index},
+% endfor
+    IoBankCount = ${len(top["pinout"]["banks"])}
+  } pwr_dom_e;
+
+  // Enumeration for MIO signals on the top-level.
+  typedef enum int unsigned {
+% for sig in top["pinmux"]["ios"]:
+  % if sig['type'] in ['inout', 'input'] and sig['connection'] == 'muxed':
+    ${lib.get_io_enum_literal(sig, 'mio_in')} = ${sig['glob_idx']},
+  % endif
+% endfor
+<% total = top["pinmux"]['io_counts']['muxed']['inouts'] + \
+           top["pinmux"]['io_counts']['muxed']['inputs'] %>\
+    ${lib.Name.from_snake_case("mio_in_count").as_camel_case()} = ${total}
+  } mio_in_e;
+
+  typedef enum {
+% for sig in top["pinmux"]["ios"]:
+  % if sig['type'] in ['inout', 'output'] and sig['connection'] == 'muxed':
+    ${lib.get_io_enum_literal(sig, 'mio_out')} = ${sig['glob_idx']},
+  % endif
+% endfor
+<% total = top["pinmux"]['io_counts']['muxed']['inouts'] + \
+           top["pinmux"]['io_counts']['muxed']['outputs'] %>\
+    ${lib.Name.from_snake_case("mio_out_count").as_camel_case()} = ${total}
+  } mio_out_e;
+
+  // Enumeration for DIO signals, used on both the top and chip-levels.
+  typedef enum int unsigned {
+% for sig in top["pinmux"]["ios"]:
+  % if sig['connection'] != 'muxed':
+    ${lib.get_io_enum_literal(sig, 'dio')} = ${sig['glob_idx']},
+  % endif
+% endfor
+<% total = top["pinmux"]['io_counts']['dedicated']['inouts'] + \
+           top["pinmux"]['io_counts']['dedicated']['inputs'] + \
+           top["pinmux"]['io_counts']['dedicated']['outputs'] %>\
+    ${lib.Name.from_snake_case("dio_count").as_camel_case()} = ${total}
+  } dio_e;
+
+  // Raw MIO/DIO input array indices on chip-level.
+  // TODO: Does not account for target specific stubbed/added pads.
+  // Need to make a target-specific package for those.
+  typedef enum int unsigned {
+% for pad in top["pinout"]["pads"]:
+  % if pad["connection"] == "muxed":
+    ${lib.Name.from_snake_case("mio_pad_" + pad["name"]).as_camel_case()} = ${pad["idx"]},
+  % endif
+% endfor
+    ${lib.Name.from_snake_case("mio_pad_count").as_camel_case()}
+  } mio_pad_e;
+
+  typedef enum int unsigned {
+% for pad in top["pinout"]["pads"]:
+  % if pad["connection"] != "muxed":
+    ${lib.Name.from_snake_case("dio_pad_" + pad["name"]).as_camel_case()} = ${pad["idx"]},
+  % endif
+% endfor
+    ${lib.Name.from_snake_case("dio_pad_count").as_camel_case()}
+  } dio_pad_e;
+
+  // TODO: Enumeration for PLIC Interrupt source peripheral.
+  // TODO: Enumeration for PLIC Interrupt Ids.
+
+endpackage
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl
new file mode 100644
index 00000000..9700c3d5
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/toplevel_rnd_cnst_pkg.sv.tpl
@@ -0,0 +1,44 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+${gencmd}
+<%
+  def make_blocked_sv_literal(hexstr, randwidth):
+    """This chops the random hexstring into manageable blocks of 64 chars such that the
+    lines do not get too long.
+    """
+    # Make all-caps and drop '0x' preamble
+    hexstr = str(hexstr[2:]).upper()
+    # Block width in hex chars
+    blockwidth = 64
+    remainder = randwidth % (4*blockwidth)
+    numbits = remainder if remainder else 4*blockwidth
+    idx = 0
+    hexblocks = []
+    while randwidth > 0:
+      hexstr = hexstr[idx:]
+      randwidth -= numbits
+      idx = (numbits + 3) // 4
+      hexblocks.append(str(numbits) + "'h" + hexstr[0:idx])
+      numbits = 4*blockwidth
+    return hexblocks
+%>
+package top_${top["name"]}_rnd_cnst_pkg;
+
+% for m in top["module"]:
+  % for p in filter(lambda p: p.get("randtype") in ["data", "perm"], m["param_list"]):
+    % if loop.first:
+  ////////////////////////////////////////////
+  // ${m['name']}
+  ////////////////////////////////////////////
+    % endif
+  // ${p['desc']}
+  parameter ${p["type"]} ${p["name_top"]} = {
+    % for block in make_blocked_sv_literal(p["default"], p["randwidth"]):
+    ${block}${"" if loop.last else ","}
+    % endfor
+  };
+
+  % endfor
+% endfor
+endpackage : top_${top["name"]}_rnd_cnst_pkg
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/xbar_env_pkg__params.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/xbar_env_pkg__params.sv.tpl
new file mode 100644
index 00000000..63c59fe1
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/templates/xbar_env_pkg__params.sv.tpl
@@ -0,0 +1,88 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_env_pkg__params generated by `topgen.py` tool
+
+<%
+  from collections import OrderedDict
+
+  def is_device_a_xbar(dev_name):
+    for xbar in top["xbar"]:
+      if xbar["name"] == dev_name:
+        return 1
+    return 0
+
+  # recursively find all non-xbar devices under this xbar
+  def get_xbar_edge_nodes(xbar_name):
+    edge_devices = []
+    for xbar in top["xbar"]:
+      if xbar["name"] == xbar_name:
+        for host, devices in xbar["connections"].items():
+          for dev_name in devices:
+            if is_device_a_xbar(dev_name):
+              edge_devices.extend(get_xbar_edge_nodes())
+            else:
+              edge_devices.append(dev_name)
+
+    return edge_devices
+
+  # find device xbar and assign all its device nodes to it: "peri" -> "uart, gpio, ..."
+  xbar_device_dict = OrderedDict()
+
+  for xbar in top["xbar"]:
+    for n in xbar["nodes"]:
+      if n["type"] == "device" and n["xbar"]:
+        xbar_device_dict[n["name"]] = get_xbar_edge_nodes(n["name"])
+
+  # create the mapping: host with the corresponding devices map
+  host_dev_map = OrderedDict()
+  for host, devices in top["xbar"][0]["connections"].items():
+    dev_list = []
+    for dev in devices:
+      if dev not in xbar_device_dict.keys():
+        dev_list.append(dev)
+      else:
+        dev_list.extend(xbar_device_dict[dev])
+      host_dev_map[host] = dev_list
+
+%>\
+
+// List of Xbar device memory map
+tl_device_t xbar_devices[$] = '{
+% for xbar in top["xbar"]:
+  % for device in xbar["nodes"]:
+    % if device["type"] == "device" and not device["xbar"]:
+    '{"${device["name"].replace('.', '__')}", '{
+      % for addr in device["addr_range"]:
+<%
+         start_addr = int(addr["base_addr"], 0)
+         end_addr = start_addr + int(addr["size_byte"], 0) - 1
+%>\
+        '{32'h${"%08x" % start_addr}, 32'h${"%08x" % end_addr}}${"," if not loop.last else ""}
+      % endfor
+    }}${"," if not loop.last or xbar != top["xbar"][-1] else "};"}
+    % endif
+  % endfor
+% endfor
+
+  // List of Xbar hosts
+tl_host_t xbar_hosts[$] = '{
+% for host in host_dev_map.keys():
+    '{"${host}", ${loop.index}, '{
+<%
+  host_devices = host_dev_map[host];
+%>\
+  % for device in host_devices:
+    % if loop.last:
+        "${device}"}}
+    % else:
+        "${device}",
+    % endif
+  % endfor
+  % if loop.last:
+};
+  % else:
+    ,
+  % endif
+% endfor
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top.py
new file mode 100644
index 00000000..dcdf1cae
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top.py
@@ -0,0 +1,122 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+'''Code representing the entire chip for reggen'''
+
+from typing import Dict, List, Optional, Tuple, Union
+
+from reggen.ip_block import IpBlock
+from reggen.params import ReggenParams
+from reggen.reg_block import RegBlock
+from reggen.window import Window
+
+_IFName = Tuple[str, Optional[str]]
+_Triple = Tuple[int, str, IpBlock]
+
+
+class Top:
+    '''An object representing the entire chip, as seen by reggen.
+
+    This contains instances of some blocks (possibly multiple instances of each
+    block), starting at well-defined base addresses. It may also contain some
+    windows. These are memories that don't have their own comportable IP (so
+    aren't defined in a block), but still take up address space.
+
+    '''
+
+    def __init__(self,
+                 regwidth: int,
+                 blocks: Dict[str, IpBlock],
+                 instances: Dict[str, str],
+                 if_addrs: Dict[Tuple[str, Optional[str]], int],
+                 windows: List[Window],
+                 attrs: Dict[str, str]):
+        '''Class initializer.
+
+        regwidth is the width of the registers (which must match for all the
+        blocks) in bits.
+
+        blocks is a map from block name to IpBlock object.
+
+        instances is a map from instance name to the name of the block it
+        instantiates. Every block name that appears in instances must be a key
+        of blocks.
+
+        if_addrs is a dictionary that maps the name of a device interface on
+        some instance of some block to its base address. A key of the form (n,
+        i) means "the device interface called i on an instance called n". If i
+        is None, this is an unnamed device interface. Every instance name (n)
+        that appears in connections must be a key of instances.
+
+        windows is a list of windows (these contain base addresses already).
+
+        attrs is a map from instance name to attr field of the block
+
+        '''
+
+        self.regwidth = regwidth
+        self.blocks = blocks
+        self.instances = instances
+        self.if_addrs = if_addrs
+        self.attrs = attrs
+
+        self.window_block = RegBlock(regwidth, ReggenParams())
+
+        # Generate one list of base addresses and objects (with each object
+        # either a block name and interface name or a window). While we're at
+        # it, construct inst_to_block_name and if_addrs.
+        merged = []  # type: List[Tuple[int, Union[_IFName, Window]]]
+        for full_if_name, addr in if_addrs.items():
+            merged.append((addr, full_if_name))
+
+            inst_name, if_name = full_if_name
+
+            # The instance name must match some key in instances, whose value
+            # should in turn match some key in blocks.
+            assert inst_name in instances
+            block_name = instances[inst_name]
+            assert block_name in blocks
+
+            # Check that if_name is indeed the name of a device interface for
+            # that block.
+            block = blocks[block_name]
+            assert block.bus_interfaces.has_interface(False, if_name)
+
+        for window in sorted(windows, key=lambda w: w.offset):
+            merged.append((window.offset, window))
+            self.window_block.add_window(window)
+
+        # A map from block name to the list of its instances. These instances
+        # are listed in increasing order of the lowest base address of one of
+        # their interfaces. The entries are added into the dict in the same
+        # order, so an iteration over items() will give blocks ordered by their
+        # first occurrence in the address map.
+        self.block_instances = {}  # type: Dict[str, List[str]]
+
+        # Walk the merged list in order of increasing base address. Check for
+        # overlaps and construct block_instances.
+        offset = 0
+        for base_addr, item in sorted(merged, key=lambda pr: pr[0]):
+            # Make sure that this item doesn't overlap with the previous one
+            assert offset <= base_addr, item
+
+            if isinstance(item, Window):
+                addrsep = (regwidth + 7) // 8
+                offset = item.next_offset(addrsep)
+                continue
+
+            inst_name, if_name = item
+            block_name = instances[inst_name]
+            block = blocks[block_name]
+
+            lst = self.block_instances.setdefault(block_name, [])
+            if inst_name not in lst:
+                lst.append(inst_name)
+
+            # This should be guaranteed by the fact that we've already checked
+            # the existence of a device interface.
+            assert if_name in block.reg_blocks
+            reg_block = block.reg_blocks[if_name]
+
+            offset = base_addr + reg_block.offset
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top_uvm_reg.sv.tpl b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top_uvm_reg.sv.tpl
new file mode 100644
index 00000000..1486a926
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/top_uvm_reg.sv.tpl
@@ -0,0 +1,151 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// UVM registers auto-generated by `reggen` containing UVM definitions for the entire top-level
+<%!
+  from topgen.gen_dv import sv_base_addr
+  from reggen.gen_dv import bcname, mcname, miname
+%>
+##
+## This template is used for chip-wide tests. It expects to be run with the
+## following arguments
+##
+##    top              a Top object
+##
+##    dv_base_prefix   a string for the base register type. If it is FOO, then
+##                     we will inherit from FOO_reg (assumed to be a subclass
+##                     of uvm_reg).
+##
+## Like uvm_reg.sv.tpl, we use functions from uvm_reg_base.sv.tpl to define
+## per-device-interface code.
+##
+<%namespace file="uvm_reg_base.sv.tpl" import="*"/>\
+##
+##
+## Waive the package-filename check: we're going to be defining all sorts of
+## packages in a single file.
+
+// verilog_lint: waive-start package-filename
+##
+## Iterate over the device interfaces of blocks in Top, constructing a package
+## for each. Sorting items like this guarantees we'll work alphabetically in
+## block name.
+% for block_name, block in sorted(top.blocks.items()):
+%   for if_name, rb in block.reg_blocks.items():
+<%
+      if_suffix = '' if if_name is None else '_' + if_name
+      esc_if_name = block_name.lower() + if_suffix
+      if_desc = '' if if_name is None else '; interface {}'.format(if_name)
+      reg_block_path = 'u_reg' + if_suffix
+      reg_block_path = reg_block_path if block.hier_path is None else block.hier_path + "." + reg_block_path
+%>\
+// Block: ${block_name.lower()}${if_desc}
+${make_ral_pkg(dv_base_prefix, top.regwidth, reg_block_path, rb, esc_if_name)}
+%   endfor
+% endfor
+##
+##
+## Now that we've made the block-level packages, re-instate the
+## package-filename check. The only package left is chip_ral_pkg, which should
+## match the generated filename.
+
+// verilog_lint: waive-start package-filename
+
+// Block: chip
+package chip_ral_pkg;
+<%
+  if_packages = []
+  for block_name, block in sorted(top.blocks.items()):
+    for if_name in block.reg_blocks:
+      if_suffix = '' if if_name is None else '_' + if_name
+      if_packages.append('{}{}_ral_pkg'.format(block_name.lower(), if_suffix))
+
+  windows = top.window_block.windows
+%>\
+${make_ral_pkg_hdr(dv_base_prefix, if_packages)}
+${make_ral_pkg_fwd_decls('chip', [], windows)}
+% for window in windows:
+
+${make_ral_pkg_window_class(dv_base_prefix, 'chip', window)}
+% endfor
+
+  class chip_reg_block extends ${dv_base_prefix}_reg_block;
+    // sub blocks
+% for block_name, block in sorted(top.blocks.items()):
+%   for inst_name in top.block_instances[block_name.lower()]:
+%     for if_name, rb in block.reg_blocks.items():
+<%
+        if_suffix = '' if if_name is None else '_' + if_name
+        esc_if_name = block_name.lower() + if_suffix
+        if_inst = inst_name + if_suffix
+%>\
+    rand ${bcname(esc_if_name)} ${if_inst};
+%     endfor
+%   endfor
+% endfor
+% if windows:
+    // memories
+%   for window in windows:
+    rand ${mcname('chip', window)} ${miname(window)};
+%   endfor
+% endif
+
+    `uvm_object_utils(chip_reg_block)
+
+    function new(string name = "chip_reg_block",
+                 int    has_coverage = UVM_NO_COVERAGE);
+      super.new(name, has_coverage);
+    endfunction : new
+
+    virtual function void build(uvm_reg_addr_t base_addr,
+                                csr_excl_item csr_excl = null);
+      // create default map
+      this.default_map = create_map(.name("default_map"),
+                                    .base_addr(base_addr),
+                                    .n_bytes(${top.regwidth//8}),
+                                    .endian(UVM_LITTLE_ENDIAN));
+      if (csr_excl == null) begin
+        csr_excl = csr_excl_item::type_id::create("csr_excl");
+        this.csr_excl = csr_excl;
+      end
+
+      // create sub blocks and add their maps
+% for block_name, block in sorted(top.blocks.items()):
+%   for inst_name in top.block_instances[block_name.lower()]:
+%     for if_name, rb in block.reg_blocks.items():
+<%
+        if_suffix = '' if if_name is None else '_' + if_name
+        esc_if_name = block_name.lower() + if_suffix
+        if_inst = inst_name + if_suffix
+
+        if top.attrs.get(inst_name) == 'reggen_only':
+          hdl_path = 'tb.dut.u_' + inst_name
+        else:
+          hdl_path = 'tb.dut.top_earlgrey.u_' + inst_name
+        qual_if_name = (inst_name, if_name)
+        base_addr = top.if_addrs[qual_if_name]
+        base_addr_txt = sv_base_addr(top, qual_if_name)
+
+        hpr_indent = (len(if_inst) + len('.set_hdl_path_root(')) * ' '
+%>\
+      ${if_inst} = ${bcname(esc_if_name)}::type_id::create("${if_inst}");
+      ${if_inst}.configure(.parent(this));
+      ${if_inst}.build(.base_addr(base_addr + ${base_addr_txt}), .csr_excl(csr_excl));
+      ${if_inst}.set_hdl_path_root("${hdl_path}",
+      ${hpr_indent}"BkdrRegPathRtl");
+      ${if_inst}.set_hdl_path_root("${hdl_path}",
+      ${hpr_indent}"BkdrRegPathRtlCommitted");
+      ${if_inst}.set_hdl_path_root("${hdl_path}",
+      ${hpr_indent}"BkdrRegPathRtlShadow");
+      default_map.add_submap(.child_map(${if_inst}.default_map),
+                             .offset(base_addr + ${base_addr_txt}));
+%     endfor
+%   endfor
+% endfor
+${make_ral_pkg_window_instances(top.regwidth, 'chip', top.window_block)}
+
+    endfunction : build
+  endclass : chip_reg_block
+
+endpackage
diff --git a/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/validate.py b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/validate.py
new file mode 100644
index 00000000..bfb42987
--- /dev/null
+++ b/hw/vendor/esl_epfl_cgra/util/lowrisc_opentitan/topgen/validate.py
@@ -0,0 +1,878 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+import re
+import logging as log
+from collections import OrderedDict
+from enum import Enum
+from typing import Dict, List
+
+from reggen.validate import check_keys
+from reggen.ip_block import IpBlock
+
+# For the reference
+# val_types = {
+#     'd': ["int", "integer (binary 0b, octal 0o, decimal, hex 0x)"],
+#     'x': ["xint", "x for undefined otherwise int"],
+#     'b': [
+#         "bitrange", "bit number as decimal integer, \
+#                     or bit-range as decimal integers msb:lsb"
+#     ],
+#     'l': ["list", "comma separated list enclosed in `[]`"],
+#     'ln': ["name list", 'comma separated list enclosed in `[]` of '\
+#            'one or more groups that have just name and dscr keys.'\
+#            ' e.g. `{ name: "name", desc: "description"}`'],
+#     'lnw': ["name list+", 'name list that optionally contains a width'],
+#     'lp': ["parameter list", 'parameter list having default value optionally'],
+#     'g': ["group", "comma separated group of key:value enclosed in `{}`"],
+#     's': ["string", "string, typically short"],
+#     't': ["text", "string, may be multi-line enclosed in `'''` "\
+#           "may use `**bold**`, `*italic*` or `!!Reg` markup"],
+#     'T': ["tuple", "tuple enclosed in ()"],
+#     'pi': ["python int", "Native Python type int (generated)"],
+#     'pb': ["python Bool", "Native Python type Bool (generated)"],
+#     'pl': ["python list", "Native Python type list (generated)"],
+#     'pe': ["python enum", "Native Python type enum (generated)"]
+# }
+
+# Required/optional field in top hjson
+top_required = {
+    'name': ['s', 'Top name'],
+    'type': ['s', 'type of hjson. Shall be "top" always'],
+    'clocks': ['g', 'group of clock properties'],
+    'resets': ['l', 'list of resets'],
+    'module': ['l', 'list of modules to instantiate'],
+    'memory': ['l', 'list of memories. At least one memory '
+                    'is needed to run the software'],
+    'debug_mem_base_addr': ['d', 'Base address of RV_DM. '
+                                 'Planned to move to module'],
+    'xbar': ['l', 'List of the xbar used in the top'],
+    'rnd_cnst_seed': ['int', "Seed for random netlist constant computation"],
+    'pinout': ['g', 'Pinout configuration'],
+    'targets': ['l', ' Target configurations'],
+    'pinmux': ['g', 'pinmux configuration'],
+}
+
+top_optional = {
+    'alert_async': ['l', 'async alerts (generated)'],
+    'alert': ['lnw', 'alerts (generated)'],
+    'alert_module': [
+        'l',
+        'list of the modules that connects to alert_handler'
+    ],
+    'datawidth': ['pn', "default data width"],
+    'exported_clks': ['g', 'clock signal routing rules'],
+    'host': ['g', 'list of host-only components in the system'],
+    'inter_module': ['g', 'define the signal connections between the modules'],
+    'interrupt': ['lnw', 'interrupts (generated)'],
+    'interrupt_module': ['l', 'list of the modules that connects to rv_plic'],
+    'num_cores': ['pn', "number of computing units"],
+    'power': ['g', 'power domains supported by the design'],
+    'port': ['g', 'assign special attributes to specific ports']
+}
+
+top_added = {}
+
+pinmux_required = {}
+pinmux_optional = {
+    'num_wkup_detect': [
+        'd', 'Number of wakeup detectors'
+    ],
+    'wkup_cnt_width': [
+        'd', 'Number of bits in wakeup detector counters'
+    ],
+    'signals': ['l', 'List of Dedicated IOs.'],
+}
+pinmux_added = {
+    'ios': ['l', 'Full list of IO'],
+}
+
+pinmux_sig_required = {
+    'instance': ['s', 'Module instance name'],
+    'connection': ['s', 'Specification of connection type, '
+                        'can be direct, manual or muxed'],
+}
+pinmux_sig_optional = {
+    'port': ['s', 'Port name of module'],
+    'pad': ['s', 'Pad name for direct connections'],
+    'desc': ['s', 'Signal description'],
+    'attr': ['s', 'Pad type for generating the correct attribute CSR']
+}
+pinmux_sig_added = {}
+
+pinout_required = {
+    'banks': ['l', 'List of IO power banks'],
+    'pads': ['l', 'List of pads']
+}
+pinout_optional = {
+}
+pinout_added = {}
+
+pad_required = {
+    'name': ['l', 'Pad name'],
+    'type': ['s', 'Pad type'],
+    'bank': ['s', 'IO power bank for the pad'],
+    'connection': ['s', 'Specification of connection type, '
+                        'can be direct, manual or muxed'],
+}
+pad_optional = {
+    'desc': ['s', 'Pad description'],
+}
+pad_added = {}
+
+target_required = {
+    'name': ['s', 'Name of target'],
+    'pinout': ['g', 'Target-specific pinout configuration'],
+    'pinmux': ['g', 'Target-specific pinmux configuration']
+}
+target_optional = {
+}
+target_added = {}
+
+target_pinmux_required = {
+    'special_signals': ['l', 'List of special signals and the pad they are mapped to.'],
+}
+target_pinmux_optional = {}
+target_pinmux_added = {}
+
+target_pinout_required = {
+    'remove_pads': ['l', 'List of pad names to remove and stub out'],
+    'add_pads': ['l', 'List of manual pads to add'],
+}
+target_pinout_optional = {}
+target_pinout_added = {}
+
+straps_required = {
+    'tap0': ['s', 'Name of tap0 pad'],
+    'tap1': ['s', 'Name of tap1 pad'],
+    'dft0': ['s', 'Name of dft0 pad'],
+    'dft1': ['s', 'Name of dft1 pad'],
+}
+straps_optional = {}
+straps_added = {}
+
+straps_required = {
+    'tap0': ['s', 'Name of tap0 pad'],
+    'tap1': ['s', 'Name of tap1 pad'],
+    'dft0': ['s', 'Name of dft0 pad'],
+    'dft1': ['s', 'Name of dft1 pad'],
+}
+straps_optional = {}
+straps_added = {}
+
+special_sig_required = {
+    'name': ['s', 'DIO name'],
+    'pad': ['s', 'Pad name'],
+}
+special_sig_optional = {
+    'desc': ['s', 'Description of signal connection'],
+}
+special_sig_added = {}
+
+clock_srcs_required = {
+    'name': ['s', 'name of clock group'],
+    'aon': ['s', 'yes, no. aon attribute of a clock'],
+    'freq': ['s', 'frequency of clock in Hz'],
+}
+
+clock_srcs_optional = {
+    'derived': ['s', 'whether clock is derived'],
+    'params': ['s', 'extra clock parameters']
+}
+
+derived_clock_srcs_required = {
+    'name': ['s', 'name of clock group'],
+    'aon': ['s', 'yes, no. aon attribute of a clock'],
+    'freq': ['s', 'frequency of clock in Hz'],
+    'src': ['s', 'source clock'],
+    'div': ['d', 'ratio between source clock and derived clock'],
+}
+
+clock_groups_required = {
+    'name': ['s', 'name of clock group'],
+    'src': ['s', 'yes, no. This clock group is directly from source'],
+    'sw_cg': ['s', 'yes, no, hint. Software clock gate attributes'],
+}
+clock_groups_optional = {
+    'unique': ['s', 'whether clocks in the group are unique'],
+    'clocks': ['g', 'groups of clock name to source'],
+}
+clock_groups_added = {}
+
+eflash_required = {
+    'banks': ['d', 'number of flash banks'],
+    'base_addr': ['s', 'strarting hex address of memory'],
+    'clock_connections': ['g', 'generated, elaborated version of clock_srcs'],
+    'clock_group': ['s', 'associated clock attribute group'],
+    'clock_srcs': ['g', 'clock connections'],
+    'inter_signal_list': ['lg', 'intersignal list'],
+    'name': ['s', 'name of flash memory'],
+    'pages_per_bank': ['d', 'number of data pages per flash bank'],
+    'program_resolution': ['d', 'maximum number of flash words allowed to program'],
+    'reset_connections': ['g', 'reset connections'],
+    'swaccess': ['s', 'software accessibility'],
+    'type': ['s', 'type of memory']
+}
+
+eflash_optional = {}
+
+eflash_added = {}
+
+
+# Supported PAD types.
+# Needs to coincide with enum definition in prim_pad_wrapper_pkg.sv
+class PadType(Enum):
+    INPUT_STD = 'InputStd'
+    BIDIR_STD = 'BidirStd'
+    BIDIR_TOL = 'BidirTol'
+    BIDIR_OD = 'BidirOd'
+    ANALOG_IN0 = 'AnalogIn0'
+
+
+def is_valid_pad_type(obj):
+    try:
+        PadType(obj)
+    except ValueError:
+        return False
+    return True
+
+
+class TargetType(Enum):
+    MODULE = "module"
+    XBAR = "xbar"
+
+
+class Target:
+    """Target class informs the checkers if we are validating a module or xbar
+    """
+    def __init__(self, target_type):
+        # The type of this target
+        self.target_type = target_type
+        # The key to search against
+        if target_type == TargetType.MODULE:
+            self.key = "type"
+        else:
+            self.key = "name"
+
+
+class Flash:
+    """Flash class contains information regarding parameter defaults.
+       For now, only expose banks / pages_per_bank for user configuration.
+       For now, also enforce power of 2 requiremnt.
+    """
+    max_banks = 4
+    max_pages_per_bank = 1024
+
+    def __init__(self, mem):
+        self.banks = mem['banks']
+        self.pages_per_bank = mem['pages_per_bank']
+        self.program_resolution = mem['program_resolution']
+        self.words_per_page = 256
+        self.data_width = 64
+        self.metadata_width = 12
+        self.info_types = 3
+        self.infos_per_bank = [10, 1, 2]
+
+    def is_pow2(self, n):
+        return (n != 0) and (n & (n - 1) == 0)
+
+    def check_values(self):
+        pow2_check = (self.is_pow2(self.banks) and
+                      self.is_pow2(self.pages_per_bank) and
+                      self.is_pow2(self.program_resolution))
+        limit_check = ((self.banks <= Flash.max_banks) and
+                       (self.pages_per_bank <= Flash.max_pages_per_bank))
+
+        return pow2_check and limit_check
+
+    def calc_size(self):
+        word_bytes = self.data_width / 8
+        bytes_per_page = word_bytes * self.words_per_page
+        bytes_per_bank = bytes_per_page * self.pages_per_bank
+        return bytes_per_bank * self.banks
+
+    def populate(self, mem):
+        mem['words_per_page'] = self.words_per_page
+        mem['data_width'] = self.data_width
+        mem['metadata_width'] = self.metadata_width
+        mem['info_types'] = self.info_types
+        mem['infos_per_bank'] = self.infos_per_bank
+        mem['size'] = hex(int(self.calc_size()))
+
+        word_bytes = self.data_width / 8
+        mem['pgm_resolution_bytes'] = int(self.program_resolution * word_bytes)
+
+
+# Check to see if each module/xbar defined in top.hjson exists as ip/xbar.hjson
+# Also check to make sure there are not multiple definitions of ip/xbar.hjson for each
+# top level definition
+# If it does, return a dictionary of instance names to index in ip/xbarobjs
+def check_target(top, objs, tgtobj):
+    error = 0
+    idxs = OrderedDict()
+
+    # Collect up counts of object names. We support entries of objs that are
+    # either dicts (for top-levels) or IpBlock objects.
+    name_indices = {}
+    for idx, obj in enumerate(objs):
+        if isinstance(obj, IpBlock):
+            name = obj.name.lower()
+        else:
+            name = obj['name'].lower()
+
+        log.info("%d Order is %s" % (idx, name))
+        name_indices.setdefault(name, []).append(idx)
+
+    tgt_type = tgtobj.target_type.value
+    inst_key = tgtobj.key
+
+    for cfg in top[tgt_type]:
+        cfg_name = cfg['name'].lower()
+        log.info("Checking target %s %s" % (tgt_type, cfg_name))
+
+        indices = name_indices.get(cfg[inst_key], [])
+        if not indices:
+            log.error("Could not find %s.hjson" % cfg_name)
+            error += 1
+        elif len(indices) > 1:
+            log.error("Duplicate %s.hjson" % cfg_name)
+            error += 1
+        else:
+            idxs[cfg_name] = indices[0]
+
+    log.info("Current state %s" % idxs)
+    return error, idxs
+
+
+def check_pad(top: Dict,
+              pad: Dict,
+              known_pad_names: Dict,
+              valid_connections: List[str],
+              prefix: str) -> int:
+    error = 0
+    error += check_keys(pad, pad_required, pad_optional,
+                        pad_added, prefix)
+
+    # check name uniqueness
+    if pad['name'] in known_pad_names:
+        log.warning('Pad name {} is not unique'.format(pad['name']))
+        error += 1
+    known_pad_names[pad['name']] = 1
+
+    if not is_valid_pad_type(pad['type']):
+        log.warning('Unkown pad type {}'.format(pad['type']))
+        error += 1
+
+    if pad['bank'] not in top['pinout']['banks']:
+        log.warning('Unkown io power bank {}'.format(pad['bank']))
+        error += 1
+
+    if pad['connection'] not in valid_connections:
+        log.warning('Connection type {} of pad {} is invalid'
+                    .format(pad['connection'], pad['name']))
+        error += 1
+
+    return error
+
+
+def check_pinout(top: Dict, prefix: str) -> int:
+    error = check_keys(top['pinout'], pinout_required, pinout_optional,
+                       pinout_added, prefix + ' Pinout')
+
+    known_names = {}
+    for pad in top['pinout']['pads']:
+        error += check_keys(pad, pad_required, pad_optional,
+                            pad_added, prefix + ' Pinout')
+
+        error += check_pad(top, pad, known_names,
+                           ['direct', 'manual', 'muxed'],
+                           prefix + ' Pad')
+
+    return error
+
+
+def check_pinmux(top: Dict, prefix: str) -> int:
+    error = check_keys(top['pinmux'], pinmux_required, pinmux_optional,
+                       pinmux_added, prefix + ' Pinmux')
+
+    # This is used for the direct connection accounting below,
+    # where we tick off already connected direct pads.
+    known_direct_pads = {}
+    direct_pad_attr = {}
+    for pad in top['pinout']['pads']:
+        if pad['connection'] == 'direct':
+            known_direct_pads[pad['name']] = 1
+            direct_pad_attr[pad['name']] = pad['type']
+
+    # Note: the actual signal crosscheck is deferred until the merge stage,
+    # since we have no idea at this point which IOs comportable IPs expose.
+    for sig in top['pinmux']['signals']:
+        error += check_keys(sig, pinmux_sig_required, pinmux_sig_optional,
+                            pinmux_sig_added, prefix + ' Pinmux signal')
+
+        if sig['connection'] not in ['direct', 'manual', 'muxed']:
+            log.warning('Invalid connection type {}'.format(sig['connection']))
+            error += 1
+
+        # The pad needs to refer to a valid pad name in the pinout that is of
+        # connection type "direct". We tick off all direct pads that have been
+        # referenced in order to make sure there are no double connections
+        # and unconnected direct pads.
+        padname = sig.setdefault('pad', '')
+        if padname != '':
+            if padname in known_direct_pads:
+                if known_direct_pads[padname] == 1:
+                    known_direct_pads[padname] = 0
+                    padattr = direct_pad_attr[padname]
+                else:
+                    log.warning('Warning, direct pad {} is already connected'
+                                .format(padname))
+                    error += 1
+            else:
+                log.warning('Unknown direct pad {}'.format(padname))
+                error += 1
+
+        # Check port naming scheme.
+        port = sig.setdefault('port', '')
+        pattern = r'^[a-zA-Z0-9_]*(\[[0-9]*\]){0,1}'
+        matches = re.match(pattern, port)
+        if matches is None:
+            log.warning('Port name {} has wrong format'
+                        .format(port))
+            error += 1
+
+        # Check that only direct connections have pad keys
+        if sig['connection'] == 'direct':
+            if sig.setdefault('attr', '') != '':
+                log.warning('Direct connection of instance {} port {} '
+                            'must not have an associated pad attribute field'
+                            .format(sig['instance'],
+                                    sig['port']))
+                error += 1
+            # Since the signal is directly connected, we can automatically infer
+            # the pad type needed to instantiate the correct attribute CSR WARL
+            # module inside the pinmux.
+            sig['attr'] = padattr
+
+            if padname == '':
+                log.warning('Instance {} port {} connection is of direct type '
+                            'and therefore must have an associated pad name.'
+                            .format(sig['instance'],
+                                    sig['port']))
+                error += 1
+            if port == '':
+                log.warning('Instance {} port {} connection is of direct type '
+                            'and therefore must have an associated port name.'
+                            .format(sig['instance'],
+                                    sig['port']))
+                error += 1
+        elif sig['connection'] == 'muxed':
+            # Muxed signals do not have a corresponding pad and attribute CSR,
+            # since they first go through the pinmux matrix.
+            if sig.setdefault('attr', '') != '':
+                log.warning('Muxed connection of instance {} port {} '
+                            'must not have an associated pad attribute field'
+                            .format(sig['instance'],
+                                    sig['port']))
+                error += 1
+            if padname != '':
+                log.warning('Muxed connection of instance {} port {} '
+                            'must not have an associated pad'
+                            .format(sig['instance'],
+                                    sig['port']))
+                error += 1
+        elif sig['connection'] == 'manual':
+            # This pad attr key is only allowed in the manual case,
+            # as there is no way to infer the pad type automatically.
+            sig.setdefault('attr', 'BidirStd')
+            if padname != '':
+                log.warning('Manual connection of instance {} port {} '
+                            'must not have an associated pad'
+                            .format(sig['instance'],
+                                    sig['port']))
+                error += 1
+
+    # At this point, all direct pads should have been ticked off.
+    for key, val in known_direct_pads.items():
+        if val == 1:
+            log.warning('Direct pad {} has not been connected'
+                        .format(key))
+            error += 1
+
+    return error
+
+
+def check_implementation_targets(top: Dict, prefix: str) -> int:
+    error = 0
+    known_names = {}
+    for target in top['targets']:
+        error += check_keys(target, target_required, target_optional,
+                            target_added, prefix + ' Targets')
+
+        # check name uniqueness
+        if target['name'] in known_names:
+            log.warning('Target name {} is not unique'.format(target['name']))
+            error += 1
+        known_names[target['name']] = 1
+
+        error += check_keys(target['pinmux'], target_pinmux_required, target_pinmux_optional,
+                            target_pinmux_added, prefix + ' Target pinmux')
+
+        error += check_keys(target['pinout'], target_pinout_required, target_pinout_optional,
+                            target_pinout_added, prefix + ' Target pinout')
+
+        # Check special pad signals
+        known_entry_names = {}
+        for entry in target['pinmux']['special_signals']:
+            error += check_keys(entry, special_sig_required, special_sig_optional,
+                                special_sig_added, prefix + ' Special signal')
+
+            # check name uniqueness
+            if entry['name'] in known_entry_names:
+                log.warning('Special pad name {} is not unique'.format(entry['name']))
+                error += 1
+            known_entry_names[entry['name']] = 1
+
+            # The pad key needs to refer to a valid pad name.
+            is_muxed = False
+            for pad in top['pinout']['pads']:
+                if entry['pad'] == pad['name']:
+                    is_muxed = pad['connection'] == 'muxed'
+                    break
+            else:
+                log.warning('Unknown pad {}'.format(entry['pad']))
+                error += 1
+
+            if not is_muxed:
+                # If this is not a muxed pad, we need to make sure this refers to
+                # DIO that is NOT a manual pad.
+                for sig in top['pinmux']['signals']:
+                    if entry['pad'] == sig['pad']:
+                        break
+                else:
+                    log.warning('Special pad {} cannot refer to a manual pad'.format(entry['pad']))
+                    error += 1
+
+        # Check pads to remove and stub out
+        for entry in target['pinout']['remove_pads']:
+            # The pad key needs to refer to a valid pad name.
+            for pad in top['pinout']['pads']:
+                if entry == pad['name']:
+                    break
+            else:
+                log.warning('Unknown pad {}'.format(entry))
+                error += 1
+
+        # Check pads to add
+        known_pad_names = {}
+        for pad in top['pinout']['pads']:
+            known_pad_names.update({pad['name']: 1})
+
+        for pad in target['pinout']['add_pads']:
+            error += check_pad(top, pad, known_pad_names, ['manual'],
+                               prefix + ' Additional Pad')
+
+    return error
+
+
+# check for inconsistent clock group definitions
+def check_clock_groups(top):
+
+    # default empty assignment
+    if "groups" not in top['clocks']:
+        top['clocks']['groups'] = []
+
+    error = 0
+    for group in top['clocks']['groups']:
+        error = check_keys(group, clock_groups_required, clock_groups_optional,
+                           clock_groups_added, "Clock Groups")
+
+        # Check sw_cg values are valid
+        if group['sw_cg'] not in ['yes', 'no', 'hint']:
+            log.error("Incorrect attribute for sw_cg: {}".format(
+                group['sw_cg']))
+            error += 1
+
+        # Check combination of src and sw are valid
+        if group['src'] == 'yes' and group['sw_cg'] != 'no':
+            log.error("Invalid combination of src and sw_cg: {} and {}".format(
+                group['src'], group['sw_cg']))
+            error += 1
+
+        # Check combination of sw_cg and unique are valid
+        unique = group['unique'] if 'unique' in group else 'no'
+        if group['sw_cg'] == 'no' and unique != 'no':
+            log.error(
+                "Incorrect attribute combination.  When sw_cg is no, unique must be no"
+            )
+            error += 1
+
+        if error:
+            break
+
+    return error
+
+
+def check_clocks_resets(top, ipobjs, ip_idxs, xbarobjs, xbar_idxs):
+
+    error = 0
+
+    # there should only be one each of pwrmgr/clkmgr/rstmgr
+    pwrmgrs = [m for m in top['module'] if m['type'] == 'pwrmgr']
+    clkmgrs = [m for m in top['module'] if m['type'] == 'clkmgr']
+    rstmgrs = [m for m in top['module'] if m['type'] == 'rstmgr']
+
+    if len(pwrmgrs) == 1 * len(clkmgrs) == 1 * len(rstmgrs) != 1:
+        log.error("Incorrect number of pwrmgr/clkmgr/rstmgr")
+        error += 1
+
+    # check clock fields are all there
+    ext_srcs = []
+    for src in top['clocks']['srcs']:
+        check_keys(src, clock_srcs_required, clock_srcs_optional, {},
+                   "Clock source")
+        ext_srcs.append(src['name'])
+
+    # check derived clock sources
+    log.info("Collected clocks are {}".format(ext_srcs))
+    for src in top['clocks']['derived_srcs']:
+        check_keys(src, derived_clock_srcs_required, {}, {}, "Derived clocks")
+        try:
+            ext_srcs.index(src['src'])
+        except Exception:
+            error += 1
+            log.error("{} is not a valid src for {}".format(
+                src['src'], src['name']))
+
+    # all defined clock/reset nets
+    reset_nets = [reset['name'] for reset in top['resets']['nodes']]
+    clock_srcs = [
+        clock['name']
+        for clock in top['clocks']['srcs'] + top['clocks']['derived_srcs']
+    ]
+
+    # Check clock/reset port connection for all IPs
+    for ipcfg in top['module']:
+        ipcfg_name = ipcfg['name'].lower()
+        log.info("Checking clock/resets for %s" % ipcfg_name)
+        error += validate_reset(ipcfg, ipobjs[ip_idxs[ipcfg_name]], reset_nets)
+        error += validate_clock(ipcfg, ipobjs[ip_idxs[ipcfg_name]], clock_srcs)
+
+        if error:
+            log.error("module clock/reset checking failed")
+            break
+
+    # Check clock/reset port connection for all xbars
+    for xbarcfg in top['xbar']:
+        xbarcfg_name = xbarcfg['name'].lower()
+        log.info("Checking clock/resets for xbar %s" % xbarcfg_name)
+        error += validate_reset(xbarcfg, xbarobjs[xbar_idxs[xbarcfg_name]],
+                                reset_nets, "xbar")
+        error += validate_clock(xbarcfg, xbarobjs[xbar_idxs[xbarcfg_name]],
+                                clock_srcs, "xbar")
+
+        if error:
+            log.error("xbar clock/reset checking failed")
+            break
+
+    return error
+
+
+# Checks the following
+# For each defined reset connection in top*.hjson, there exists a defined port at the destination
+# and defined reset net
+# There are the same number of defined connections as there are ports
+def validate_reset(top, inst, reset_nets, prefix=""):
+    # Gather inst port list
+    error = 0
+
+    # Handle either an IpBlock (generated by reggen) or an OrderedDict
+    # (generated by topgen for a crossbar)
+    if isinstance(inst, IpBlock):
+        name = inst.name
+        reset_signals = inst.reset_signals
+    else:
+        name = inst['name']
+        reset_signals = ([inst.get('reset_primary', 'rst_ni')] +
+                         inst.get('other_reset_list', []))
+
+    log.info("%s %s resets are %s" %
+             (prefix, name, reset_signals))
+
+    if len(top['reset_connections']) != len(reset_signals):
+        error += 1
+        log.error("%s %s mismatched number of reset ports and nets" %
+                  (prefix, name))
+
+    missing_port = [
+        port for port in top['reset_connections'].keys()
+        if port not in reset_signals
+    ]
+
+    if missing_port:
+        error += 1
+        log.error("%s %s Following reset ports do not exist:" %
+                  (prefix, name))
+        [log.error("%s" % port) for port in missing_port]
+
+    missing_net = [
+        net for port, net in top['reset_connections'].items()
+        if net not in reset_nets
+    ]
+
+    if missing_net:
+        error += 1
+        log.error("%s %s Following reset nets do not exist:" %
+                  (prefix, name))
+        [log.error("%s" % net) for net in missing_net]
+
+    return error
+
+
+# Checks the following
+# For each defined clock_src in top*.hjson, there exists a defined port at the destination
+# and defined clock source
+# There are the same number of defined connections as there are ports
+def validate_clock(top, inst, clock_srcs, prefix=""):
+    # Gather inst port list
+    error = 0
+
+    # Handle either an IpBlock (generated by reggen) or an OrderedDict
+    # (generated by topgen for a crossbar)
+    if isinstance(inst, IpBlock):
+        name = inst.name
+        clock_signals = inst.clock_signals
+    else:
+        name = inst['name']
+        clock_signals = ([inst.get('clock_primary', 'rst_ni')] +
+                         inst.get('other_clock_list', []))
+
+    if len(top['clock_srcs']) != len(clock_signals):
+        error += 1
+        log.error("%s %s mismatched number of clock ports and nets" %
+                  (prefix, name))
+
+    missing_port = [
+        port for port in top['clock_srcs'].keys()
+        if port not in clock_signals
+    ]
+
+    if missing_port:
+        error += 1
+        log.error("%s %s Following clock ports do not exist:" %
+                  (prefix, name))
+        [log.error("%s" % port) for port in missing_port]
+
+    missing_net = [
+        net for port, net in top['clock_srcs'].items() if net not in clock_srcs
+    ]
+
+    if missing_net:
+        error += 1
+        log.error("%s %s Following clock nets do not exist:" %
+                  (prefix, name))
+        [log.error("%s" % net) for net in missing_net]
+
+    return error
+
+
+def check_flash(top):
+    error = 0
+
+    for mem in top['memory']:
+        if mem['type'] == "eflash":
+            error = check_keys(mem, eflash_required, eflash_optional,
+                               eflash_added, "Eflash")
+
+    flash = Flash(mem)
+    error += 1 if not flash.check_values() else 0
+
+    if error:
+        log.error("Flash check failed")
+    else:
+        flash.populate(mem)
+
+    return error
+
+
+def check_power_domains(top):
+    error = 0
+
+    # check that the default domain is valid
+    if top['power']['default'] not in top['power']['domains']:
+        error += 1
+        return error
+
+    # check that power domain definition is consistent with reset and module definition
+    for reset in top['resets']['nodes']:
+        if reset['gen']:
+            if 'domains' not in reset:
+                log.error("{} missing domain definition".format(reset['name']))
+                error += 1
+                return error
+            else:
+                for domain in reset['domains']:
+                    if domain not in top['power']['domains']:
+                        log.error("{} defined invalid domain {}".format(
+                            reset['name'], domain))
+                        error += 1
+                        return error
+
+    # Check that each module, xbar, memory has a power domain defined.
+    # If not, give it a default.
+    # If there is one defined, check that it is a valid definition
+    for end_point in top['module'] + top['memory'] + top['xbar']:
+        if 'domain' not in end_point:
+            end_point['domain'] = top['power']['default']
+
+        if end_point['domain'] not in top['power']['domains']:
+            log.error("{} defined invalid domain {}"
+                      .format(end_point['name'],
+                              end_point['domain']))
+            error += 1
+            return error
+
+    # arrived without incident, return
+    return error
+
+
+def validate_top(top, ipobjs, xbarobjs):
+    # return as it is for now
+    error = check_keys(top, top_required, top_optional, top_added, "top")
+
+    if error != 0:
+        log.error("Top HJSON has top level errors. Aborting")
+        return top, error
+
+    component = top['name']
+
+    # MODULE check
+    err, ip_idxs = check_target(top, ipobjs, Target(TargetType.MODULE))
+    error += err
+
+    # XBAR check
+    err, xbar_idxs = check_target(top, xbarobjs, Target(TargetType.XBAR))
+    error += err
+
+    # MEMORY check
+    error += check_flash(top)
+
+    # Power domain check
+    error += check_power_domains(top)
+
+    # Clock / Reset check
+    error += check_clocks_resets(top, ipobjs, ip_idxs, xbarobjs, xbar_idxs)
+
+    # Clock group check
+    error += check_clock_groups(top)
+
+    # RV_PLIC check
+
+    # Pinout, pinmux and target checks
+    # Note that these checks must happen in this order, as
+    # the pinmux and target configs depend on the pinout.
+    error += check_pinout(top, component)
+    error += check_pinmux(top, component)
+    error += check_implementation_targets(top, component)
+
+    return top, error
diff --git a/hw/vendor/esl_epfl_cgra/utilities/instructions_fft_bitrev.py b/hw/vendor/esl_epfl_cgra/utilities/instructions_fft_bitrev.py
deleted file mode 100644
index b40736a3..00000000
--- a/hw/vendor/esl_epfl_cgra/utilities/instructions_fft_bitrev.py
+++ /dev/null
@@ -1,209 +0,0 @@
-#
-# FFT input bit reversal reordering instructions (manual mapping)
-#
-
-ker_col_needed = 1
-ker_num_instr  = 11
-
-ker_conf_words[ker_next_id] = get_bin(int(pow(2,ker_col_needed))-1,CGRA_N_COL) +\
-                              get_bin(ker_start_add, CGRA_IMEM_NL_LOG2) +\
-                              get_bin(ker_num_instr-1, RCS_NUM_CREG_LOG2)
-
-# Save current start address
-start_add     = ker_start_add
-# Update start address and ID for next kernel
-ker_start_add = ker_start_add + ker_num_instr*ker_col_needed
-ker_next_id   = ker_next_id+1
-
-# Used for multi-column kernels
-k = ker_num_instr
-
-#################################################################################################
-############################################## RC0 ##############################################
-#################################################################################################
-
-# COLUMN-0
-# PROLOGUE
-rcs_instructions[0][start_add+ 0] = [   "-",    "-",  "LWD", "R0",    "-", "-"]
-rcs_instructions[0][start_add+ 1] = [   "-",    "-",  "LWD", "R1",    "-", "-"]
-rcs_instructions[0][start_add+ 2] = rcs_nop_instr
-rcs_instructions[0][start_add+ 3] = [  "R0",  "RCB", "SADD", "R0",    "-", "-"]
-
-# ITERATION LOOP
-rcs_instructions[0][start_add+ 4] = [   "-",   "R0",  "LWI", "R2",    "-", "-"]
-rcs_instructions[0][start_add+ 5] = [  "R0",  "IMM", "SADD", "R0",    "-", "8"]
-rcs_instructions[0][start_add+ 6] = rcs_nop_instr
-rcs_instructions[0][start_add+ 7] = rcs_nop_instr
-
-rcs_instructions[0][start_add+ 8] = [ "RCB",  "IMM",  "SLT",  "-",    "-", "2"]
-rcs_instructions[0][start_add+ 9] = [  "R1", "SELF", "SADD",  "-",    "-", "-"]
-rcs_instructions[0][start_add+10] = [  "R2", "SELF",  "SWI",  "-",    "-", "-"]
-
-#################################################################################################
-############################################## RC1 ##############################################
-#################################################################################################
-
-# COLUMN-0
-# PROLOGUE
-rcs_instructions[1][start_add+ 0] = [   "-",    "-",  "LWD", "R0",    "-", "-"]
-rcs_instructions[1][start_add+ 1] = [   "-",    "-",  "LWD", "R1",    "-", "-"]
-rcs_instructions[1][start_add+ 2] = [ "RCB",  "IMM",  "SLT",  "-",    "-", "2"]
-rcs_instructions[1][start_add+ 3] = [  "R0", "SELF", "SADD", "R0",    "-", "-"]
-
-# ITERATION LOOP
-rcs_instructions[1][start_add+ 4] = [   "-",   "R0",  "LWI", "R2",    "-", "-"]
-rcs_instructions[1][start_add+ 5] = [  "R0",  "IMM", "SADD", "R0",    "-", "8"]
-rcs_instructions[1][start_add+ 6] = [  "R3",  "IMM",  "SLT",  "-",    "-", "1"]
-rcs_instructions[1][start_add+ 7] = ["SELF",  "RCB",  "LOR", "R3",    "-", "-"]
-
-rcs_instructions[1][start_add+ 8] = ["ZERO", "ZERO", "SADD", "R3",    "-", "-"] # R3=0
-rcs_instructions[1][start_add+ 9] = [ "RCT",   "R1", "SADD",  "-",    "-", "-"]
-rcs_instructions[1][start_add+10] = [  "R2", "SELF",  "SWI",  "-",    "-", "-"]
-
-#################################################################################################
-############################################## RC2 ##############################################
-#################################################################################################
-
-# COLUMN-0
-# PROLOGUE
-rcs_instructions[2][start_add+ 0] = [   "-",    "-",  "LWD", "R1",    "-", "-"]
-rcs_instructions[2][start_add+ 1] = [   "-",    "-",  "LWD", "R0",    "-", "-"]
-rcs_instructions[2][start_add+ 2] = rcs_nop_instr
-rcs_instructions[2][start_add+ 3] = rcs_nop_instr
-
-# ITERATION LOOP
-rcs_instructions[2][start_add+ 4] = ["ZERO",   "R0", "SADD", "R2",    "-", "-"] # R2=R0
-rcs_instructions[2][start_add+ 5] = rcs_nop_instr
-rcs_instructions[2][start_add+ 6] = [  "R2",  "IMM", "LAND",  "-",    "-", "1"]
-rcs_instructions[2][start_add+ 7] = [  "R2",  "IMM",  "SRT", "R2",    "-", "1"]
-
-rcs_instructions[2][start_add+ 8] = [  "R0",  "IMM", "SADD", "R0",    "-", "1"]
-rcs_instructions[2][start_add+ 9] = rcs_nop_instr
-rcs_instructions[2][start_add+10] = [  "R0",   "R1",  "BLT",  "-",    "-", "4"]
-
-#################################################################################################
-############################################## RC3 ##############################################
-#################################################################################################
-
-# COLUMN-0
-# PROLOGUE
-rcs_instructions[3][start_add+ 0] = [   "-",    "-",  "LWD", "R0",    "-", "-"]
-rcs_instructions[3][start_add+ 1] = rcs_nop_instr
-rcs_instructions[3][start_add+ 2] = rcs_nop_instr
-rcs_instructions[3][start_add+ 3] = rcs_nop_instr
-
-# ITERATION LOOP
-rcs_instructions[3][start_add+ 4] = ["ZERO", "ZERO", "SADD", "R1",    "-", "-"] # R1=0
-rcs_instructions[3][start_add+ 5] = rcs_nop_instr
-rcs_instructions[3][start_add+ 6] = [  "R1",  "IMM", "SADD", "R1",    "-", "1"]
-rcs_instructions[3][start_add+ 7] = [  "R1",   "R0",  "BLT",  "-",    "-", "6"]
-
-rcs_instructions[3][start_add+ 8] = rcs_nop_instr
-rcs_instructions[3][start_add+ 9] = rcs_nop_instr
-rcs_instructions[3][start_add+10] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
-
-#######################################################################################
-
-# instructions.append(["NEXT RC"])
-
-# # RC1_0
-# # PROLOGUE
-# instructions.append(["DATA", "OUT_D", "IN1", "RF1", "ON", "OUT_F", "0"])
-# instructions.append(["DATA", "OUT_D", "IN1", "RF2", "ON", "OUT_F", "0"])
-# instructions.append(["RF1", "CONST", "SLT", "RF1", "OFF", "OUT_F", "2"])
-# instructions.append(["RF2", "OUT_D", "SADD", "RF1", "ON", "OUT_F", "0"])
-# instructions.append(["RF1", "CONST", "SSUB", "RF1", "ON", "OUT_F", "4"])
-# instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-
-# # ITERATION LOOP
-# instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "8"])
-# instructions.append(["DATA", "RF1", "LWI", "RF3", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["RF2", "RCB", "SADD", "RF4", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["RF3", "RF4", "SWI", "RF1", "OFF", "OUT_F", "0"])
-
-# #################################################################################################
-# #################################################################################################
-# #################################################################################################
-
-# instructions.append(["NEXT RC"])
-
-# # RC2_0
-# # PROLOGUE
-# instructions.append(["DATA", "OUT_D", "IN1", "RF1", "ON", "OUT_F", "0"])
-# instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-# instructions.append(["RF1", "CONST", "SLT", "RF1", "OFF", "OUT_F", "2"])
-# instructions.append(["RF2", "OUT_D", "SADD", "RF1", "ON", "OUT_F", "0"])
-# instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# # ITERATION LOOP
-# instructions.append(["DATA", "RF1", "LWI", "RF3", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "IN1", "RF4", "ON", "OUT_F", "0"])
-# instructions.append(["RF4", "CONST", "SLT", "RF1", "OFF", "OUT_F", "1"])
-# instructions.append(["RCB", "OUT_D", "LOR", "RF4", "ON", "OUT_F", "0"])
-# instructions.append(["RF4", "CONST", "SLT", "RF1", "OFF", "OUT_F", "2"])
-# instructions.append(["RF2", "OUT_D", "SADD", "RF4", "ON", "OUT_F", "0"])
-# instructions.append(["RF3", "RF4", "SWI", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "8"])
-
-# #################################################################################################
-# #################################################################################################
-# #################################################################################################
-
-# instructions.append(["NEXT RC"])
-
-# # RC3_0
-# # PROLOGUE
-# instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# # ITERATION LOOP
-# instructions.append(["RF1", "OUT_D", "IN1", "RF3", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["RF3", "CONST", "LAND", "RF1", "OFF", "OUT_F", "1"])
-# instructions.append(["RF3", "CONST", "SRT", "RF3", "ON", "OUT_F", "1"])
-# instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "1"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["RF1", "RF2", "BLT", "RF1", "OFF", "OUT_F", "6"])
-
-# #################################################################################################
-# #################################################################################################
-# #################################################################################################
-
-# instructions.append(["NEXT RC"])
-
-# # RC4_0
-# # PROLOGUE
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# # ITERATION LOOP
-# instructions.append(["ZEROS", "OUT_D", "IN1", "RF2", "ON", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["RF2", "CONST", "SADD", "RF2", "ON", "OUT_F", "1"])
-# instructions.append(["RF2", "RF1", "BLT", "RF1", "OFF", "OUT_F", "8"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-# instructions.append(["ZEROS", "OUT_D", "EXIT", "RF1", "OFF", "OUT_F", "0"])
-
-# #################################################################################################
-# #################################################################################################
-# #################################################################################################
-
-# kernel_col_needed = "0001"
-# row_st_add = 44
-# n_instructions = 14
diff --git a/hw/vendor/eslepfl_cgra.lock.hjson b/hw/vendor/eslepfl_cgra.lock.hjson
index 3b7520c1..b4a34e3f 100644
--- a/hw/vendor/eslepfl_cgra.lock.hjson
+++ b/hw/vendor/eslepfl_cgra.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/OpenEdgeCGRA.git
-    rev: d53dd7a98ec59754ed21a5411dc985ebbdc39d3e
+    rev: 618b45d2c5deb0ae3741b8dfdd472354ed073126
   }
 }
diff --git a/hw/vendor/eslepfl_cgra.vendor.hjson b/hw/vendor/eslepfl_cgra.vendor.hjson
index 61b8090c..0b95a6dd 100644
--- a/hw/vendor/eslepfl_cgra.vendor.hjson
+++ b/hw/vendor/eslepfl_cgra.vendor.hjson
@@ -8,7 +8,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/OpenEdgeCGRA.git",
-    rev: "d53dd7a98ec59754ed21a5411dc985ebbdc39d3e",
+    rev: "618b45d2c5deb0ae3741b8dfdd472354ed073126",
   },
 
   patch_dir: "patches/esl_epfl_cgra",

From a20abefbc076e7db5c47ce661f821aa78f7238cc Mon Sep 17 00:00:00 2001
From: jmiranda <mirandacalero.joseangel@gmail.com>
Date: Wed, 25 Sep 2024 20:37:45 +0200
Subject: [PATCH 16/27] revendorizing x-heep

---
 hw/vendor/esl_epfl_x_heep/.gitignore          |   14 +-
 hw/vendor/esl_epfl_x_heep/Makefile            |   97 +-
 hw/vendor/esl_epfl_x_heep/README.md           |  651 +--
 .../block_diagrams/core_v_mini_mcu.svg        | 3553 -----------------
 .../esl_epfl_x_heep/block_diagrams/x-heep.svg | 2461 ------------
 hw/vendor/esl_epfl_x_heep/configs/ci.hjson    |   23 +
 hw/vendor/esl_epfl_x_heep/configs/example.py  |   18 +
 .../configs/example_interleaved.hjson         |   40 +
 .../esl_epfl_x_heep/configs/general.hjson     |   24 +
 .../esl_epfl_x_heep/configs/testall.hjson     |   23 +
 .../esl_epfl_x_heep/core-v-mini-mcu-fpga.core |   72 +
 .../esl_epfl_x_heep/core-v-mini-mcu.core      |   78 +-
 .../core-v-mini-mcu.dc.upf.tpl                |  159 +
 .../esl_epfl_x_heep/core-v-mini-mcu.upf.tpl   |   38 +-
 .../esl_epfl_x_heep/docs/requirements.txt     |    3 +-
 .../source/Configuration/Configuration.rst    |  172 +
 .../docs/source/How_to/AnalogMixedSignal.md   |    4 +-
 .../docs/source/How_to/CompileMakefile        |  350 --
 .../docs/source/How_to/CompileMakefile.md     |  145 +
 .../docs/source/How_to/Debug.md               |    6 +-
 .../docs/source/How_to/ExecuteFromFlash.md    |    2 +-
 .../docs/source/How_to/ExternalDevices.md     |  151 -
 .../docs/source/How_to/GettingStarted.md      |   50 +-
 .../{ => docs/source/How_to}/IDEs.md          |   18 +-
 .../docs/source/How_to/ImplementASIC.md       |    2 +-
 .../docs/source/How_to/IntegratePeripheral.md |    2 +-
 .../docs/source/How_to/ProgramFlash.md        |    2 +-
 .../docs/source/How_to/RunOnFPGA.md           |   81 +
 .../docs/source/How_to/Simulate.md            |  160 +
 .../docs/source/How_to/UpdateDocumentation.md |   27 +
 .../docs/source/How_to/eXtendingHEEP.md       |   69 +-
 .../docs/source/Peripherals/DMA.md            |  645 +--
 .../docs/source/Peripherals/SPI.md            | 1246 ++++++
 .../docs/source/Peripherals/Timer.md          |  107 +
 .../source/_static/ides}/build_screenshot.png |  Bin
 .../source/_static/ides}/debug_screenshot.png |  Bin
 hw/vendor/esl_epfl_x_heep/docs/source/conf.py |   11 +
 .../source/images}/example_adc.svg            |    0
 .../docs/source/images/x-heep-outline.png     |  Bin 0 -> 42485 bytes
 .../docs/source/images/xheep_diagram.png      |  Bin 0 -> 483438 bytes
 .../esl_epfl_x_heep/docs/source/index.rst     |   17 +-
 .../hw/asic/sky130/sram_wrapper.sv            |    4 +
 .../ao_peripheral_subsystem.sv                |  153 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv     |  357 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl |  155 +-
 .../hw/core-v-mini-mcu/debug_subsystem.sv     |   31 +-
 .../include/addr_map_rule_pkg.sv              |    6 +
 .../include/core_v_mini_mcu_pkg.sv.tpl        |   75 +-
 .../include/power_manager_pkg.sv              |   17 +
 .../include/x-heep_packages.core              |    1 +
 .../core-v-mini-mcu/memory_subsystem.sv.tpl   |   73 +-
 .../core-v-mini-mcu/peripheral_subsystem.sv   |  173 +-
 .../peripheral_subsystem.sv.tpl               |   59 +-
 .../hw/core-v-mini-mcu/system_bus.sv.tpl      |    8 +-
 .../hw/core-v-mini-mcu/system_xbar.sv.tpl     |   24 +-
 .../hw/fpga/constraints/nexys/pin_assign.xdc  |   24 +-
 .../fpga/constraints/pynq-z2/constraints.xdc  |    2 +-
 .../hw/fpga/constraints/zcu104/pin_assign.xdc |   99 +
 .../hw/fpga/pad_cell_inout_xilinx.sv          |    3 +-
 .../hw/fpga/pad_cell_input_xilinx.sv          |    3 +-
 .../hw/fpga/pad_cell_output_xilinx.sv         |    3 +-
 .../hw/fpga/prim_xilinx_clk.sv                |   15 +-
 .../hw/fpga/scripts/generate_sram.tcl         |   27 -
 .../hw/fpga/scripts/generate_sram.tcl.tpl     |   50 +
 .../hw/fpga/scripts/nexys/set_board.tcl       |    3 -
 .../hw/fpga/scripts/pynq-z2/set_board.tcl     |    3 -
 .../hw/fpga/scripts/zcu104/set_board.tcl      |    3 -
 .../{sram_wrapper.sv => sram_wrapper.sv.tpl}  |   33 +-
 .../esl_epfl_x_heep/hw/ip/dma/data/dma.hjson  |  191 +-
 hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core  |    2 +-
 .../esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv      |  798 +++-
 .../hw/ip/dma/rtl/dma_reg_pkg.sv              |  216 +-
 .../hw/ip/dma/rtl/dma_reg_top.sv              |  670 +++-
 .../hw/ip/dma_subsystem/dma_subsystem.core    |   21 +
 .../hw/ip/dma_subsystem/dma_subsystem.vlt     |   10 +
 .../hw/ip/dma_subsystem/rtl/dma_subsystem.sv  |  198 +
 .../hw/ip/i2s/rtl/i2s_rx_channel.sv           |    2 +-
 .../esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/fir.sv  |    4 +-
 .../hw/ip/pdm2pcm/rtl/halfband.sv             |    6 +-
 .../data/power_manager.hjson.tpl              |   60 +-
 .../power_manager/data/power_manager.sv.tpl   |  152 +-
 .../hw/ip/power_manager/power_manager.vlt     |    2 +-
 .../hw/simulation/pad_cell_inout.sv           |    1 +
 .../hw/simulation/pad_cell_input.sv           |    1 +
 .../hw/simulation/pad_cell_output.sv          |    1 +
 .../hw/simulation/simulation.vlt              |    2 +
 .../hw/simulation/sram_wrapper.sv             |    3 +
 .../pad_control/data/pad_control.hjson.tpl    |    2 +-
 .../hw/system/x_heep_system.sv.tpl            |   32 +-
 .../hw/vendor/esl_epfl_cv32e40px.lock.hjson   |    2 +-
 .../hw/vendor/esl_epfl_cv32e40px.vendor.hjson |    2 +-
 .../hw/vendor/esl_epfl_cv32e40px/.gitignore   |    8 +
 .../bhv/cv32e40px_instr_trace.svh             |  466 ++-
 .../esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv  |  397 +-
 .../bhv/cv32e40px_rvfi_trace.sv               |  123 +-
 .../bhv/cv32e40px_tb_wrapper.sv               |   83 +-
 .../bhv/cv32e40px_tracer.sv                   |   47 +-
 .../bhv/include/cv32e40px_rvfi_pkg.sv         |   28 +-
 .../bhv/include/cv32e40px_tracer_pkg.sv       |   30 +-
 .../esl_epfl_cv32e40px/bhv/insn_trace.sv      |  111 +-
 .../bhv/pipe_freeze_trace.sv                  |   41 +-
 .../rtl/cv32e40px_controller.sv               |   42 +-
 .../esl_epfl_cv32e40px/rtl/cv32e40px_core.sv  |   18 +-
 .../rtl/cv32e40px_cs_registers.sv             |    2 +-
 .../rtl/cv32e40px_decoder.sv                  |   86 +-
 .../rtl/cv32e40px_ex_stage.sv                 |    2 +-
 .../rtl/cv32e40px_fp_wrapper.sv               |    2 +-
 .../rtl/cv32e40px_id_stage.sv                 |   10 +-
 .../rtl/cv32e40px_load_store_unit.sv          |   32 +-
 .../rtl/cv32e40px_register_file_latch.sv      |    8 +-
 .../esl_epfl_cv32e40px/rtl/cv32e40px_top.sv   |   50 +-
 .../rtl/cv32e40px_x_disp.sv                   |   26 +-
 .../openhwgroup_cv32e20/rtl/cve2_core.sv      |   15 +-
 .../rtl/cve2_cs_registers.sv                  |   81 +-
 .../rtl/cve2_fetch_fifo.sv                    |    2 -
 .../openhwgroup_cv32e20/rtl/cve2_id_stage.sv  |    1 +
 .../openhwgroup_cv32e20/rtl/cve2_pkg.sv       |   80 +
 .../rtl/cve2_top_tracing.sv                   |    2 -
 .../hw/vendor/openhwgroup_cv32e40p.lock.hjson |    2 +-
 .../vendor/openhwgroup_cv32e40p.vendor.hjson  |    2 +-
 .../hw/vendor/openhwgroup_cv32e40p/.gitignore |    2 +
 .../bhv/cv32e40p_instr_trace.svh              |  466 ++-
 .../openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv |  319 +-
 .../bhv/cv32e40p_rvfi_trace.sv                |  123 +-
 .../bhv/cv32e40p_tb_wrapper.sv                |   40 +-
 .../bhv/cv32e40p_tracer.sv                    |   47 +-
 .../bhv/include/cv32e40p_rvfi_pkg.sv          |   28 +-
 .../bhv/include/cv32e40p_tracer_pkg.sv        |   30 +-
 .../openhwgroup_cv32e40p/bhv/insn_trace.sv    |  107 +-
 .../bhv/pipe_freeze_trace.sv                  |   41 +-
 .../rtl/cv32e40p_controller.sv                |   40 +-
 .../openhwgroup_cv32e40p/rtl/cv32e40p_core.sv |   12 +-
 .../rtl/cv32e40p_decoder.sv                   |   86 +-
 .../rtl/cv32e40p_fp_wrapper.sv                |    2 +-
 .../rtl/cv32e40p_id_stage.sv                  |   10 +-
 .../rtl/cv32e40p_load_store_unit.sv           |   32 +-
 .../rtl/cv32e40p_register_file_latch.sv       |    8 +-
 .../openhwgroup_cv32e40p/rtl/cv32e40p_top.sv  |   50 +-
 .../hw/vendor/openhwgroup_cve2.lock.hjson     |    2 +-
 .../hw/vendor/openhwgroup_cve2.vendor.hjson   |    2 +-
 .../pulp_platform_riscv_dbg/fix_nrharts.patch |   28 +
 .../pulp_platform_riscv_dbg.vendor.hjson      |    2 +
 .../pulp_platform_riscv_dbg/src/dm_csrs.sv    |    2 +-
 .../pulp_platform_riscv_dbg/src/dm_mem.sv     |    4 +-
 .../hw/vendor/waiver/lint/cv32e40px.vlt       |    3 +
 .../hw/vendor/waiver/lint/riscv_dbg.vlt       |    1 +
 hw/vendor/esl_epfl_x_heep/logo/x-heep.png     |  Bin 30569 -> 0 bytes
 hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson       |   47 +-
 .../esl_epfl_x_heep/mcu_cfg_minimal.hjson     |   50 +-
 hw/vendor/esl_epfl_x_heep/pad_cfg.hjson       |   18 +-
 .../scripts/synthesis/dc_shell/dc_script.tcl  |    4 +
 hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt   |  105 +-
 hw/vendor/esl_epfl_x_heep/sw/Makefile         |    2 +-
 .../sw/applications/coremark/coremark.h       |    2 +-
 .../example_ams_peripheral/main.c             |    2 +-
 .../sw/applications/example_asm/add.s         |    6 +
 .../sw/applications/example_asm/constants.h   |    1 +
 .../sw/applications/example_asm/main.c        |   31 +
 .../sw/applications/example_asm/multiply.S    |    9 +
 .../applications/example_clock_gating/main.c  |   63 -
 .../sw/applications/example_cpp/MyClass.cpp   |   21 +
 .../sw/applications/example_cpp/MyClass.hpp   |   15 +
 .../sw/applications/example_cpp/main.c        |   27 -
 .../sw/applications/example_cpp/main.cpp      |   50 +
 .../sw/applications/example_cpp/test_cpp.cpp  |   43 -
 .../sw/applications/example_cpp/test_cpp.h    |    4 -
 .../gen_stimuly.py                            |   65 +
 .../example_data_processing_from_flash/main.c |   87 +
 .../example_data_processing_from_flash/main.h |   42 +
 .../matrices.h                                |  206 +
 .../sw/applications/example_dma/main.c        |  519 ++-
 .../sw/applications/example_dma_2d/main.c     |  890 +++++
 .../applications/example_dma_2d/test_data.h   |   40 +
 .../applications/example_dma_external/main.c  |    8 +-
 .../example_dma_multichannel/main.c           | 1261 ++++++
 .../example_dma_multichannel/test_data.h      |   34 +
 .../sw/applications/example_dma_sdk/main.c    |  112 +
 .../example_freertos_blinky/main.c            |    4 +-
 .../sw/applications/example_gpio_intr/main.c  |    5 +-
 .../applications/example_gpio_toggle/main.c   |    2 +-
 .../sw/applications/example_i2s/main.c        |   61 +-
 .../sw/applications/example_iffifo/main.c     |    8 +-
 .../example_im2col/im2colGolden.c             |   72 +
 .../example_im2col/im2colGolden.h             |   31 +
 .../applications/example_im2col/im2col_lib.c  |  211 +
 .../applications/example_im2col/im2col_lib.h  |   74 +
 .../sw/applications/example_im2col/main.c     |   81 +
 .../sw/applications/example_matadd/main.c     |    2 +-
 .../example_matadd_interleaved/main.c         |    2 +-
 .../sw/applications/example_matfadd/main.c    |  110 +-
 .../sw/applications/example_matmul/main.c     |    2 +-
 .../sw/applications/example_pdm2pcm/main.c    |    2 +-
 .../example_power_gating_core/main.c          |  189 -
 .../example_power_gating_external/main.c      |   68 -
 .../example_power_gating_periph/main.c        |   66 -
 .../example_power_gating_ram_blocks/main.c    |   74 -
 .../applications/example_power_manager/main.c |  471 +++
 .../applications/example_sdk_spi_flash/main.c |  353 ++
 .../example_set_retentive_ram_blocks/main.c   |   70 -
 .../main.c                                    |   63 -
 .../example_simple_accelerator/main.c         |    2 +-
 .../example_spi_host_dma_power_gate/main.c    |  341 --
 .../sw/applications/example_spi_read/main.c   |   12 +-
 .../sw/applications/example_spi_write/main.c  |   15 +-
 .../example_spidma_powergate/main.c           |  192 +
 .../sw/applications/example_timer_sdk/main.c  |  126 +
 .../sw/applications/hello_world/main.c        |    1 -
 .../sw/applications/minver/chipsupport.c      |    2 +-
 .../esl_epfl_x_heep/sw/cmake/riscv.cmake      |    2 +-
 .../esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c |  541 ++-
 .../sw/device/bsp/w25q/w25q128jw.h            |   14 +-
 .../sw/device/lib/base/freestanding/assert.h  |   17 +-
 .../device/lib/base/freestanding/stdalign.h   |    6 +
 .../sw/device/lib/base/freestanding/stdbool.h |    4 +
 .../sw/device/lib/base/memory.c               |   12 +-
 .../sw/device/lib/base/memory.h               |    2 +-
 .../esl_epfl_x_heep/sw/device/lib/base/mmio.c |   10 +
 .../sw/device/lib/crt/{crt0.S => crt0.S.tpl}  |  317 +-
 .../sw/device/lib/crt/vectors.S               |   30 +-
 .../sw/device/lib/crt/vectors_freertos.S      |   27 -
 .../sw/device/lib/drivers/dma/dma.c           |  681 +++-
 .../sw/device/lib/drivers/dma/dma.h           |  145 +-
 .../sw/device/lib/drivers/dma/dma_regs.h      |  153 +-
 .../drivers/fast_intr_ctrl/fast_intr_ctrl.c   |    6 +
 .../drivers/fast_intr_ctrl/fast_intr_ctrl.h   |    8 +-
 .../sw/device/lib/drivers/gpio/gpio.c         |   11 +-
 .../power_manager/data/power_manager.h.tpl    |   18 +-
 .../lib/drivers/power_manager/power_manager.c |  208 +-
 .../power_manager/power_manager_cpu_restore.S |   88 +
 .../power_manager/power_manager_cpu_store.S   |   88 +
 .../sw/device/lib/drivers/rv_plic/rv_plic.c   |   13 +-
 .../sw/device/lib/drivers/rv_timer/rv_timer.h |    6 +
 .../sw/device/lib/drivers/soc_ctrl/soc_ctrl.h |    2 +-
 .../sw/device/lib/drivers/spi_host/spi_host.c |  526 ++-
 .../sw/device/lib/drivers/spi_host/spi_host.h |  916 ++++-
 .../sw/device/lib/drivers/uart/uart.c         |   20 +-
 .../device/lib/runtime/core_v_mini_mcu.h.tpl  |   15 +-
 .../lib/runtime/core_v_mini_mcu_memory.h.tpl  |   29 +
 .../sw/device/lib/runtime/handler.c           |    8 +
 .../sw/device/lib/runtime/handler.h           |    9 +
 .../sw/device/lib/runtime/hart.h              |   10 +
 .../sw/device/lib/runtime/heap.cpp            |   60 +
 .../sw/device/lib/runtime/init.c              |   11 +-
 .../sw/device/lib/runtime/syscalls.c          |   42 +-
 .../sw/device/lib/runtime/syscalls_cpp.cpp    |   39 +
 .../sw/device/lib/sdk/dma/dma_sdk.c           |  100 +
 .../sw/device/lib/sdk/dma/dma_sdk.h           |  108 +
 .../sw/device/lib/sdk/spi/spi_sdk.c           | 1127 ++++++
 .../sw/device/lib/sdk/spi/spi_sdk.h           |  576 +++
 .../sw/device/lib/sdk/timer/timer_sdk.c       |  142 +
 .../sw/device/lib/sdk/timer/timer_sdk.h       |  121 +
 .../sw/device/target/nexys-a7-100t/x-heep.h   |    1 +
 .../sw/device/target/pynq-z2/x-heep.h         |    1 +
 .../sw/device/target/zcu104/x-heep.h          |    1 +
 .../esl_epfl_x_heep/sw/linker/link.ld.tpl     |   18 +-
 .../sw/linker/link_flash_exec.ld.tpl          |    2 +-
 .../sw/linker/link_flash_load.ld.tpl          |   36 +-
 hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl  |   43 +-
 hw/vendor/esl_epfl_x_heep/tb/testharness.sv   |   24 +-
 hw/vendor/esl_epfl_x_heep/util/MakefileHelp   |   12 +-
 .../util/generate-makefile-help               |    2 -
 hw/vendor/esl_epfl_x_heep/util/mcu_gen.py     |  162 +-
 .../util/structs_periph_gen.py                |   28 +-
 hw/vendor/esl_epfl_x_heep/util/test_all.sh    |   10 +-
 .../util/x_heep_gen/__init__.py               |    4 +
 .../util/x_heep_gen/linker_section.py         |   80 +
 .../util/x_heep_gen/load_config.py            |  293 ++
 .../util/x_heep_gen/ram_bank.py               |  133 +
 .../esl_epfl_x_heep/util/x_heep_gen/system.py |  430 ++
 hw/vendor/eslepfl_x_heep.lock.hjson           |    2 +-
 hw/vendor/eslepfl_x_heep.vendor.hjson         |    2 +-
 271 files changed, 19587 insertions(+), 12028 deletions(-)
 delete mode 100644 hw/vendor/esl_epfl_x_heep/block_diagrams/core_v_mini_mcu.svg
 delete mode 100644 hw/vendor/esl_epfl_x_heep/block_diagrams/x-heep.svg
 create mode 100644 hw/vendor/esl_epfl_x_heep/configs/ci.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/configs/example.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/configs/general.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/configs/testall.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/core-v-mini-mcu-fpga.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.dc.upf.tpl
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/Configuration/Configuration.rst
 delete mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile.md
 delete mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md
 rename hw/vendor/esl_epfl_x_heep/{ => docs/source/How_to}/IDEs.md (92%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/How_to/RunOnFPGA.md
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/How_to/Simulate.md
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/How_to/UpdateDocumentation.md
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/SPI.md
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/Timer.md
 rename hw/vendor/esl_epfl_x_heep/{ides/img => docs/source/_static/ides}/build_screenshot.png (100%)
 rename hw/vendor/esl_epfl_x_heep/{ides/img => docs/source/_static/ides}/debug_screenshot.png (100%)
 rename hw/vendor/esl_epfl_x_heep/{block_diagrams => docs/source/images}/example_adc.svg (100%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/images/x-heep-outline.png
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/images/xheep_diagram.png
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/power_manager_pkg.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl.tpl
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl
 delete mode 100644 hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl
 rename hw/vendor/esl_epfl_x_heep/hw/fpga/{sram_wrapper.sv => sram_wrapper.sv.tpl} (66%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.vlt
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_riscv_dbg/fix_nrharts.patch
 delete mode 100644 hw/vendor/esl_epfl_x_heep/logo/x-heep.png
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/add.s
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/constants.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/multiply.S
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_clock_gating/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.cpp
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.hpp
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.cpp
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.cpp
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/test_data.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_sdk/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_core/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_external/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_periph/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_ram_blocks/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_sdk_spi_flash/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks_external/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_spidma_powergate/main.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_timer_sdk/main.c
 rename hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/{crt0.S => crt0.S.tpl} (83%)
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_restore.S
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_store.S
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/heap.cpp
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls_cpp.cpp
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.h
 delete mode 100755 hw/vendor/esl_epfl_x_heep/util/generate-makefile-help
 create mode 100644 hw/vendor/esl_epfl_x_heep/util/x_heep_gen/__init__.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/util/x_heep_gen/linker_section.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/util/x_heep_gen/load_config.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/util/x_heep_gen/ram_bank.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/util/x_heep_gen/system.py

diff --git a/hw/vendor/esl_epfl_x_heep/.gitignore b/hw/vendor/esl_epfl_x_heep/.gitignore
index f2b85af8..d369ddf8 100644
--- a/hw/vendor/esl_epfl_x_heep/.gitignore
+++ b/hw/vendor/esl_epfl_x_heep/.gitignore
@@ -7,8 +7,10 @@ build/
 *.dis
 *.map
 *.do
+*.jou
+*.str
 .venv/
-util/__pycache__/*
+__pycache__/
 
 # ignore apps output file
 run_verif_rtl_log.txt
@@ -16,6 +18,7 @@ run_verif_rtl_log.txt
 # ignore the following hw automatically generated files
 environment.yml
 core-v-mini-mcu.upf
+core-v-mini-mcu.dc.upf
 tb/tb_util.svh
 hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv
 hw/core-v-mini-mcu/system_bus.sv
@@ -32,9 +35,13 @@ hw/system/pad_control/data/pad_control.hjson
 hw/system/pad_control/rtl/pad_control.sv
 hw/system/pad_control/rtl/pad_control_reg_pkg.sv
 hw/system/pad_control/rtl/pad_control_reg_top.sv
+hw/fpga/sram_wrapper.sv
+hw/fpga/scripts/generate_sram.tcl
 
-# same for the C header file and linker scripts
+# same for the C header file and linker scripts and assembly files
+sw/device/lib/crt/crt0.S
 sw/device/lib/runtime/core_v_mini_mcu.h
+sw/device/lib/runtime/core_v_mini_mcu_memory.h
 sw/linker/link.ld
 sw/linker/link_flash_exec.ld
 sw/linker/link_flash_load.ld
@@ -46,6 +53,9 @@ sw/device/lib/drivers/**/*_structs.h
 # openroad
 flow/OpenROAD-flow-scripts
 
+# automatically generated docs
+/docs/source/Configuration/generated
+
 # User-dependent configuration files
 .vscode
 private/
diff --git a/hw/vendor/esl_epfl_x_heep/Makefile b/hw/vendor/esl_epfl_x_heep/Makefile
index 2d67386a..ca1a02b0 100644
--- a/hw/vendor/esl_epfl_x_heep/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/Makefile
@@ -9,8 +9,10 @@ mkfile_path := $(shell dirname "$(realpath $(firstword $(MAKEFILE_LIST)))")
 $(info $$You are executing from: $(mkfile_path))
 
 # Include the self-documenting tool
-FILE=$(mkfile_path)/Makefile
-include $(mkfile_path)/util/generate-makefile-help
+export FILE_FOR_HELP=$(mkfile_path)/Makefile
+
+help:
+	${mkfile_path}/util/MakefileHelp
 
 # Setup to autogenerate python virtual environment
 VENVDIR?=$(WORKDIR)/.venv
@@ -31,12 +33,15 @@ endif
 # Project options are based on the app to be build (default - hello_world)
 PROJECT  ?= hello_world
 
+LINK_FOLDER ?= $(mkfile_path)/sw/linker
+
 # Linker options are 'on_chip' (default),'flash_load','flash_exec','freertos'
 LINKER   ?= on_chip
 
 # Target options are 'sim' (default) and 'pynq-z2' and 'nexys-a7-100t'
 TARGET   	?= sim
-MCU_CFG  	?= mcu_cfg.hjson
+MCU_CFG_PERIPHERALS  	?= mcu_cfg.hjson
+X_HEEP_CFG  ?= configs/general.hjson
 PAD_CFG  	?= pad_cfg.hjson
 EXT_PAD_CFG ?=
 
@@ -63,23 +68,23 @@ FLASHREAD_ADDR ?= 0x0
 FLASHREAD_FILE ?= $(mkfile_path)/flashcontent.hex
 FLASHREAD_BYTES ?= 256
 
+
+#binary to store in flash memory
+FLASHWRITE_FILE ?= $(mkfile_path)/sw/build/main.hex
+
 #max address in the hex file, used to program the flash
-ifeq ($(wildcard sw/build/main.hex),)
-	MAX_HEX_ADDRESS  = 0
-	MAX_HEX_ADDRESS_DEC = 0
-	BYTES_AFTER_MAX_HEX_ADDRESS = 0
-	FLASHRWITE_BYTES = 0
+ifeq ($(wildcard $(FLASHWRITE_FILE)),)
+	MAX_HEX_ADDRESS  := 0
+	MAX_HEX_ADDRESS_DEC := 0
+	BYTES_AFTER_MAX_HEX_ADDRESS := 0
+	FLASHWRITE_BYTES := 0
 else
-	MAX_HEX_ADDRESS  = $(shell cat sw/build/main.hex | grep "@" | tail -1 | cut -c2-)
-	MAX_HEX_ADDRESS_DEC = $(shell printf "%d" 0x$(MAX_HEX_ADDRESS))
-	BYTES_AFTER_MAX_HEX_ADDRESS = $(shell tac sw/build/main.hex | awk 'BEGIN {count=0} /@/ {print count; exit} {count++}')
-	FLASHRWITE_BYTES = $(shell echo $(MAX_HEX_ADDRESS_DEC) + $(BYTES_AFTER_MAX_HEX_ADDRESS)*16 | bc)
+	MAX_HEX_ADDRESS  := $(shell cat $(FLASHWRITE_FILE) | grep "@" | tail -1 | cut -c2-)
+	MAX_HEX_ADDRESS_DEC := $(shell printf "%d" 0x$(MAX_HEX_ADDRESS))
+	BYTES_AFTER_MAX_HEX_ADDRESS := $(shell tac $(FLASHWRITE_FILE) | awk 'BEGIN {count=0} /@/ {print count; exit} {count++}')
+	FLASHWRITE_BYTES := $(shell echo $(MAX_HEX_ADDRESS_DEC) + $(BYTES_AFTER_MAX_HEX_ADDRESS)*16 | bc)
 endif
 
-
-#binary to store in flash memory
-FLASHWRITE_FILE = $(mkfile_path)/sw/build/main.hex
-
 # Export variables to sub-makefiles
 export
 
@@ -98,28 +103,33 @@ environment.yml: python-requirements.txt
 ## @param MEMORY_BANKS=[2(default) to (16 - MEMORY_BANKS_IL)]
 ## @param MEMORY_BANKS_IL=[0(default),2,4,8]
 mcu-gen:
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/include --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/system_bus.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/system_xbar.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/memory_subsystem.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir tb/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv tb/tb_util.svh.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/pad_ring.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/x_heep_system.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link.ld.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.upf.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/ip/power_manager/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/ip/power_manager/data/power_manager.sv.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/ip/power_manager/data --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/ip/power_manager/data/power_manager.hjson.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/include --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/system_bus.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/system_xbar.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/memory_subsystem.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir tb/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv tb/tb_util.svh.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/pad_ring.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/core-v-mini-mcu/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/system/x_heep_system.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/runtime --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --header-c sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir $(LINK_FOLDER) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script $(LINK_FOLDER)/link.ld.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.upf.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir . --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --pkg-sv ./core-v-mini-mcu.dc.upf.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/ip/power_manager/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/ip/power_manager/data/power_manager.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/ip/power_manager/data --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/ip/power_manager/data/power_manager.hjson.tpl
 	bash -c "cd hw/ip/power_manager; source power_manager_gen.sh; cd ../../../"
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/drivers/power_manager --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv sw/device/lib/drivers/power_manager/data/power_manager.h.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/data --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/data/pad_control.hjson.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/rtl/pad_control.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/drivers/power_manager --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv sw/device/lib/drivers/power_manager/data/power_manager.h.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/data --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/data/pad_control.hjson.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/system/pad_control/rtl --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --external_pads $(EXT_PAD_CFG) --pkg-sv hw/system/pad_control/rtl/pad_control.sv.tpl
 	bash -c "cd hw/system/pad_control; source pad_control_gen.sh; cd ../../../"
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link_flash_exec.ld.tpl
-	$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir sw/linker --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script sw/linker/link_flash_load.ld.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir $(LINK_FOLDER) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script $(LINK_FOLDER)/link_flash_exec.ld.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir $(LINK_FOLDER) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --linker_script $(LINK_FOLDER)/link_flash_load.ld.tpl
 	$(PYTHON) ./util/structs_periph_gen.py
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/fpga/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/fpga/sram_wrapper.sv.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir hw/fpga/scripts/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv hw/fpga/scripts/generate_sram.tcl.tpl
+	$(PYTHON) util/mcu_gen.py --config $(X_HEEP_CFG) --cfg_peripherals $(MCU_CFG_PERIPHERALS) --pads_cfg $(PAD_CFG) --outdir sw/device/lib/crt/ --bus $(BUS) --memorybanks $(MEMORY_BANKS) --memorybanks_il $(MEMORY_BANKS_IL) --tpl-sv sw/device/lib/crt/crt0.S.tpl
 	$(MAKE) verible
 
 ## Display mcu_gen.py help
@@ -140,7 +150,15 @@ verible:
 ## @param COMPILER_PREFIX=riscv32-unknown-(default)
 ## @param ARCH=rv32imc(default), <any RISC-V ISA string supported by the CPU>
 app: clean-app
-	$(MAKE) -C sw PROJECT=$(PROJECT) TARGET=$(TARGET) LINKER=$(LINKER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH) SOURCE=$(SOURCE)
+	$(MAKE) -C sw PROJECT=$(PROJECT) TARGET=$(TARGET) LINKER=$(LINKER) LINK_FOLDER=$(LINK_FOLDER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH) SOURCE=$(SOURCE) \
+	|| { \
+	echo "\033[0;31mHmmm... seems like the compilation failed...\033[0m"; \
+	echo "\033[0;31mIf you do not understand why, it is likely that you either:\033[0m"; \
+	echo "\033[0;31m  a) offended the Leprechaun of Electronics\033[0m"; \
+	echo "\033[0;31m  b) forgot to run make mcu-gen\033[0m"; \
+	echo "\033[0;31mI would start by checking b) if I were you!\033[0m"; \
+	exit 1; \
+	}
 
 ## Just list the different application names available
 app-list:
@@ -256,13 +274,18 @@ flash-readid:
 ## Loads the obtained binary to the EPFL_Programmer flash
 flash-prog:
 	cd sw/vendor/yosyshq_icestorm/iceprog; make; \
-	./iceprog -a $(FLASHRWITE_BYTES) -d i:0x0403:0x6011 -I B $(FLASHWRITE_FILE);
+	./iceprog -a $(FLASHWRITE_BYTES) -d i:0x0403:0x6011 -I B $(FLASHWRITE_FILE);
 
 ## Read the EPFL_Programmer flash
 flash-read:
 	cd sw/vendor/yosyshq_icestorm/iceprog; make; \
 	./iceprog -d i:0x0403:0x6011 -I B -o $(shell printf "%d" $(FLASHREAD_ADDR)) -R $(FLASHREAD_BYTES) $(FLASHREAD_FILE);
 
+## Erase the EPFL_Programmer flash
+flash-erase:
+	cd sw/vendor/yosyshq_icestorm/iceprog; make; \
+	./iceprog -d i:0x0403:0x6011 -I B -b;
+
 ## Run openOCD w/ EPFL_Programmer
 openOCD_epflp:
 	xterm -e openocd -f ./tb/core-v-mini-mcu-pynq-z2-esl-programmer.cfg;
diff --git a/hw/vendor/esl_epfl_x_heep/README.md b/hw/vendor/esl_epfl_x_heep/README.md
index c9705474..1a539464 100644
--- a/hw/vendor/esl_epfl_x_heep/README.md
+++ b/hw/vendor/esl_epfl_x_heep/README.md
@@ -1,3 +1,22 @@
+<br />
+<p align="center"><img src="docs/source/images/x-heep-outline.png" width="500"></p>
+
+`X-HEEP` (eXtendable Heterogeneous Energy-Efficient Platform) is a `RISC-V` microcontroller described in `SystemVerilog`
+that can be configured to target small and tiny platforms as well as extended to support accelerators.
+The cool thing about `X-HEEP` is that we provide a simple customizable MCU, so CPUs, common peripherals, memories, etc.
+so that you can extend it with your own accelerator without modifying the MCU, but just instantiating it in your design.
+By doing so, you inherit an IP capable of booting RTOS (such as `freeRTOS`) with the whole FW stack, including `HAL` drivers and `SDK`,
+and you can focus on building your special HW supported by the microcontroller.
+
+`X-HEEP` supports simulation with Verilator, Questasim, etc. Morever, FW can be built and linked by using `CMake` either with gcc or with clang. It can be implemented on FPGA, and it supports implementation in Silicon, which is its main (but not only) target. See below for more details.
+
+The block diagram below shows the `X-HEEP` MCU
+
+<p align="center"><img src="docs/source/images/xheep_diagram.png" width="1000"></p>
+
+
+> :bookmark_tabs: Please refer to the documentation in [Read the Docs](https://x-heep.readthedocs.io/en/latest/index.html)
+
 # Repository folder structure
 
     .
@@ -23,22 +42,6 @@
     ├── util
     └── README.md
 
-<br />
-<p align="left"><img src="logo/x-heep.png" width="250"></p>
-
-`X-HEEP` (eXtendable Heterogeneous Energy-Efficient Platform) is a `RISC-V` microcontroller described in `SystemVerilog`
-that can be configured to target small and tiny platforms as well as extended to support accelerators.
-The cool thing about `X-HEEP` is that we provide a simple customizable MCU, so CPUs, common peripherals, memories, etc.
-so that you can extend it with your own accelerator without modifying the MCU, but just instantiating it in your design.
-By doing so, you inherit an IP capable of booting RTOS (such as `freeRTOS`) with the whole FW stack, including `HAL` drivers and `SDK`,
-and you can focus on building your special HW supported by the microcontroller.
-
-`X-HEEP` supports simulation with Verilator, Questasim, etc. Morever, FW can be built and linked by using `CMake` either with gcc or with clang. It can be implemented on FPGA, and it supports implementation in Silicon, which is its main (but not only) target. See below for more details.
-
-The block diagram below shows the `X-HEEP` MCU
-
-<p align="center"><img src="block_diagrams/core_v_mini_mcu.svg" width="650"></p>
-
 # Reference
 
 If you use X-HEEP in your academic work you can cite us: [X-HEEP Paper](https://arxiv.org/abs/2401.05548)
@@ -52,618 +55,4 @@ If you use X-HEEP in your academic work you can cite us: [X-HEEP Paper](https://
       archivePrefix={arXiv},
       primaryClass={cs.AR}
 }
-```
-
-# Self-documented Makefile
-
-Note that under `util` folder, the file `generate-makefile-help` is employed to generate a self-documented helping output. In case of including any other target or command under the main `Makefile`, follow the same general and parameter descriptions as already provided for every target. Check the `help` output by doing `make` or `make help`. Moreover, **note that some of the parameters required for some of the targets are initiated with _default values_**
-
-# Prerequisite
-
-## 1. OS requirements
-
-To use `X-HEEP`, first make sure you have the following apt packages, or install them as:
-
-```bash
-sudo apt install lcov libelf1 libelf-dev libftdi1-2 libftdi1-dev libncurses5 libssl-dev libudev-dev libusb-1.0-0 lsb-release texinfo autoconf cmake flex bison libexpat-dev gawk tree xterm python3-venv python3-dev
-```
-
-In general, have a look at the [Install required software](https://opentitan.org/guides/getting_started/index.html) section of the OpenTitan documentation.
-
-It has been tested only on `Ubuntu 20`, and we know it does NOT WORK on `Ubuntu 22`.
-
-## 2. Python
-
-We rely on either (a) `miniconda`, or (b) `virtual environment` enviroment.
-
-Choose between `2.a` or `2.b` to setup your enviroment.
-
-### 2.a Miniconda
-
-Install [Miniconda](https://docs.conda.io/en/latest/miniconda.html#linux-installers) python 3.8 version as described in the link,
-and create the Conda enviroment:
-
-```bash
-make conda
-```
-
-You need to do it only the first time, then just activate the environment everytime you work with `X-HEEP` as
-
-```bash
-conda activate core-v-mini-mcu
-```
-
-### 2.b Virtual Environment
-
-Install the python virtual environment just as:
-
-```bash
-make venv
-```
-
-You need to do it only the first time, then just activate the environment everytime you work with `X-HEEP` as
-
-```bash
-source .venv/bin/activate
-```
-
-## 3. Install the RISC-V Compiler:
-
-```
-git clone --branch 2022.01.17 --recursive https://github.com/riscv/riscv-gnu-toolchain
-cd riscv-gnu-toolchain
-./configure --prefix=/home/$USER/tools/riscv --with-abi=ilp32 --with-arch=rv32imc --with-cmodel=medlow
-make
-```
-
-Then, set the `RISCV` env variable as:
-
-```
-export RISCV=/home/$USER/tools/riscv
-```
-
-Optionally you can also compile with clang/LLVM instead of gcc. For that you must install the clang compiler into the same `RISCV` path. The binaries of gcc and clang do not collide so you can have both residing in the same `RISCV` directory. For this you can set the `-DCMAKE_INSTALL_PREFIX` cmake variable to `$RISCV` when building LLVM. This can be accomplished by doing the following:
-
-```
-git clone https://github.com/llvm/llvm-project.git
-cd llvm-project
-git checkout llvmorg-14.0.0
-mkdir build && cd build
-cmake -G "Unix Makefiles" -DLLVM_ENABLE_PROJECTS=clang -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$RISCV -DLLVM_TARGETS_TO_BUILD="RISCV" ../llvm
-cmake --build . --target install
-```
-
-## 4. Install Verilator:
-
-```
-export VERILATOR_VERSION=4.210
-
-git clone https://github.com/verilator/verilator.git
-cd verilator
-git checkout v$VERILATOR_VERSION
-
-autoconf
-./configure --prefix=/home/$USER/tools/verilator/$VERILATOR_VERSION
-make
-make install
-```
-Then, set the `PATH` env variable to as:
-
-```
-export PATH=/home/$USER/tools/verilator/$VERILATOR_VERSION/bin:$PATH
-```
-
-In general, have a look at the [Install Verilator](https://opentitan.org/guides/getting_started/setup_verilator.html) section of the OpenTitan documentation.
-
-If you want to see the vcd waveforms generated by the Verilator simulation, install GTKWAVE:
-
-```
-sudo apt install libcanberra-gtk-module libcanberra-gtk3-module
-sudo apt-get install -y gtkwave
-```
-
-## Files are formatted with Verible
-
-We use version v0.0-1824-ga3b5bedf
-
-See: [Install Verible](https://opentitan.org/guides/getting_started/index.html#step-7a-install-verible-optional)
-
-To format your RTL code type:
-
-```
-make verible
-```
-
-## Docker alternative
-
-A docker image containing all the required software dependancies is available on [github-packages](https://github.com/orgs/esl-epfl/packages/container/package/x-heep-toolchain).
-
-It is only required to install [`docker`](https://docs.docker.com/get-docker/) and pull the image.
-
-```bash
-docker pull ghcr.io/esl-epfl/x-heep-toolchain:latest
-```
-
-Assuming that X-HEEP has been cloned to `X-HEEP-DIR=\absolute\path\to\x-HEEP\folder`, it is possible to directly run the docker mounting `X-HEEP-DIR` to the path `\workspace\x-heep` in the docker.
-
-```bash
-docker run -it -v ${X-HEEP-DIR}:/workspace/x-heep ghcr.io/esl-epfl/x-heep-toolchain
-```
-
-Take care to indicate the absolute path to the local clone of X-HEEP, otherwise `docker` will not be able to properly nount the local folder in the container.
-
-All the command listed in the README can be execute in the docker container, except for:
-- Simulation with Questasim and VCS, synthesis with Design Compiler (licenses are required to use these tools, so they are not installed in the container)
-- OpenRoad flow is not installed in the container, so it is not possible to run the related make commands
-
-## Compilation Flow and Package Manager
-
-We use [FuseSoC](https://github.com/olofk/fusesoc) for all the tools we use.
-
-The `fusesoc` commands are inside the Makefile.
-
-# Adding external IPs
-
-This repository relies on [Vendor](https://opentitan.org/book/util/doc/vendor.html) to add new IPs. The `vendor.py` script in the [`./util`](./util/) folder implements what is described above, while [this](./docs/source/How_to/ExternalDevices.md) file contains additional information on how to connect external devices to the system.
-
-# Compiling with Makefile
-
-You can compile the example applications and the platform using the Makefile. Type 'make help' or 'make' for more information. Moreover, please, check the different 'clean' commands to verify that you are using the corret one.
-
-## Generate core-v-mini-mcu package
-
-First, you have to generate the SystemVerilog package and C header file of the core-v-mini-mcu:
-
-```
-make mcu-gen
-```
-
-By default, `X-HEEP` deploys the [cv32e20](https://github.com/openhwgroup/cve2) RISC-V CPU.
-Other supported CPUs are: the [cv32e40p](https://github.com/openhwgroup/cv32e40p), [cv32e40x](https://github.com/openhwgroup/cv32e40x), and the [cv32e40px](https://github.com/esl-epfl/cv32e40px).
-The default bus type of `X-HEEP` is a single-master-at-a-time architecture, (called `onetoM`), but the cross-bar architecture is also supported by setting
-the bus to `NtoM`. Also, the user can select the number of 32kB banks addressed in continuous mode and/or the interleaved mode.
-By default, `X-HEEP` is generated with 2 continuous banks and 0 interleaved banks.
-
-Below an example that changes the default configuration:
-
-```
-make mcu-gen CPU=cv32e40p BUS=NtoM MEMORY_BANKS=12 MEMORY_BANKS_IL=4
-```
-
-The last command generates x-heep with the cv32e40p core, with a parallel bus, and 16 memory banks (12 continuous and 4 interleaved),
-each 32KB, for a total memory of 512KB.
-
-If you are using `X-HEEP` just as a controller for your own system and you do not need any peripheral, you can use the `minimal` configuration file
-when generating the MCU as:
-
-```
-make mcu-gen MCU_CFG=mcu_cfg_minimal.hjson
-```
-
-The `minimal` configuration is a work-in-progress, thus not all the APPs have been tested.
-
-## Compiling Software
-
-Don't forget to set the `RISCV` env variable to the compiler folder (without the `/bin` included).
-To run 'hello world' application, just type 'make app'.
-
-```
-make app
-```
-
-To run any other application, please use the following command with appropiate parameters:
-
-```
-app PROJECT=<folder_name_of_the_project_to_be_built> TARGET=sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104 LINKER=on_chip(default),flash_load,flash_exec COMPILER=gcc(default),clang COMPILER_PREFIX=riscv32-unknown-(default) ARCH=rv32imc(default),<any RISC-V ISA string supported by the CPU>
-
-Params:
-- PROJECT (ex: <folder_name_of_the_project_to_be_built>, hello_world(default))
-- TARGET (ex: sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104)
-- LINKER (ex: on_chip(default),flash_load,flash_exec)
-- COMPILER (ex: gcc(default),clang)
-- COMPILER_PREFIX (ex: riscv32-unknown-(default))
-- ARCH (ex: rv32imc(default),<any RISC-V ISA string supported by the CPU>)
-```
-
-For instance, to run 'hello world' app for the pynq-z2 FPGA targets, just run:
-
-```
-make app TARGET=pynq-z2
-```
-
-Or, if you use the OpenHW Group [GCC](https://www.embecosm.com/resources/tool-chain-downloads/#corev) compiler with CORE_PULP extensions, make sure to point the `RISCV` env variable to the OpenHW Group compiler, then just run:
-
-```
-make app COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_xcvhwlp_xcvmem_xcvmac_xcvbi_xcvalu_xcvsimd_xcvbitmanip
-```
-
-This will create the executable file to be loaded into your target system (ASIC, FPGA, Simulation).
-Remember that, `X-HEEP` is using CMake to compile and link. Thus, the generated files after having
-compiled and linked are under `sw\build`
-
-Alternatively, in case you are doing pure FW development and you are used to developing using Integrated Development Evironments (IDEs), please check [the IDE readme](./IDEs.md).
-
-## FreeROTS based applications
-
-'X-HEEP' supports 'FreeRTOS' based applications. Please see `sw\applications\blinky_freertos`.
-
-After that, you can run the command to compile and link the FreeRTOS based application. Please also set 'LINKER' and 'TARGET' parameters if needed.
-
-```
-make app PROJECT=blinky_freertos
-```
-
-The main FreeRTOS configuration is allocated under `sw\freertos`, in `FreeRTOSConfig.h`. Please, change this file based on your application requirements.
-Moreover, FreeRTOS is being fetch from 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git' by CMake. Specifically, 'V10.5.1' is used. Finally, the fetch repository is located under `sw\build\_deps` after building.
-
-## Simulating
-
-This project supports simulation with Verilator, Synopsys VCS, Siemens Questasim and Cadence Xcelium.
-It relies on `fusesoc` to handle multiple EDA tools and parameters.
-For example, if you want to set the `FPU` and `COREV_PULP` parameters of the `cv32e40p` CPU,
-you need to add next to your compilation command `FUSESOC_PARAM="--COREV_PULP=1 --FPU=1"`
-Below the different EDA examples commands.
-
-### Compiling for Verilator (C++ testbench)
-
-To simulate your application with Verilator, first compile the HDL:
-
-```
-make verilator-sim
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
-```
-
-and type to run your compiled software:
-
-```
-./Vtestharness +firmware=../../../sw/build/main.hex
-```
-
-or to execute all these three steps type:
-
-```
-make run-helloworld
-```
-
-### Compiling for Verilator (SystemC testbench)
-
-To simulate your application with Verilator using `SystemC`,
-
-make sure you have `SystemC 2.3.3` installed, if not, find it [here](https://www.accellera.org/downloads/standards/systemc).
-
-Make sure to have the following env variables set:
-
-```
-export SYSTEMC_INCLUDE=/your_path_to_systemc/systemc/include/
-export SYSTEMC_LIBDIR=/your_path_to_systemc/systemc/lib-linux64/
-```
-
-Compile the HDL:
-
-```
-make verilator-sim-sc
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim_sc-verilator
-```
-
-and type to run your compiled software:
-
-```
-./Vtestharness +firmware=../../../sw/build/main.hex
-```
-
-If you want to know what is special about the SystemC testbench, have a look [here](./docs/source/How_to/SystemC.md)
-
-### Compiling for VCS
-
-To simulate your application with VCS, first compile the HDL:
-
-```
-make vcs-sim
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-vcs
-```
-
-and type to run your compiled software:
-
-```
-./openhwgroup.org_systems_core-v-mini-mcu_0 +firmware=../../../sw/build/main.hex
-```
-
-Waveforms can be viewed with Verdi. Make sure you have the env variable `VERDI_HOME` set to your Verdi install folder, then run your compiled software as above, but with the `-gui` flag:
-
-```
-./openhwgroup.org_systems_core-v-mini-mcu_0 +firmware=../../../sw/build/main.hex -gui
-```
-
-An Analog / Mixed-Signal simulation of X-HEEP, combining both the RTL system verilog files for the digital part and a SPICE file connected through a `control.init` file for the analog / mixed-signal part, can be ran by typing
-
-```
-make vcs-ams-sim
-```
-
-then going to the target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-vcs
-```
-
-and running the same executable as for the digital simulation. Note that with Verdi you can view both the digital and the analog waveforms.
-
-Additional instructions on how to run an analog / mixed-signal simulation of X-HEEP can be found [here](./docs/source/How_to/AnalogMixedSignal.md). To try out the simulation, we provide an example SPICE netlist of an simple 1-bit ADC created by us and exported from [xschem](https://xschem.sourceforge.io/stefan/index.html) and which uses the PTM 65nm bulk CMOS model from [https://ptm.asu.edu](https://ptm.asu.edu/).
-
-### Compiling for Questasim
-
-To simulate your application with Questasim, first set the env variable `MODEL_TECH` to your Questasim bin folder, then compile the HDL:
-
-```
-make questasim-sim
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim/
-```
-
-and type to run your compiled software:
-
-```
-make run PLUSARGS="c firmware=../../../sw/build/main.hex"
-```
-
-You can also use vopt for HDL optimized compilation:
-
-```
-make questasim-sim-opt
-```
-
-then go to
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim_opt-modelsim/
-```
-and
-
-```
-make run RUN_OPT=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
-```
-
-You can also compile with the UPF power domain description as:
-
-```
-make questasim-sim-opt-upf FUSESOC_PARAM="--USE_UPF"
-```
-
-and then execute software as:
-
-```
-make run RUN_OPT=1 RUN_UPF=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
-```
-
-Questasim version must be >= Questasim 2020.4
-
-### Compiling for Xcelium
-
-To simulate your application with Xcelium, first compile the HDL:
-
-```
-make xcelium-sim
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-xcelium/
-```
-
-and type to run your compiled software:
-
-```
-make run PLUSARGS="c firmware=../../../sw/build/main.hex"
-```
-
-### UART DPI
-
-To simulate the UART, we use the LowRISC OpenTitan [UART DPI](https://github.com/lowRISC/opentitan/tree/master/hw/dv/dpi/uartdpi).
-Read how to interact with it in the Section "Running Software on a Verilator Simulation with Bazel" [here](https://opentitan.org/guides/getting_started/setup_verilator.html#running-software-on-a-verilator-simulation-with-bazel).
-The output of the UART DPI module is printed in the `uart0.log` file in the simulation folder.
-
-For example, to see the "hello world!" output of the Verilator simulation:
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
-./Vtestharness +firmware=../../../sw/build/main.hex
-cat uart0.log
-```
-
-## Automatic testing
-
-X-HEEP includes two tools to perform automatic tests over your modifications.
-
-### Github CIs
-
-Upon push, tests are run on Github runners, these include:
-* The generated `.sv` files pushed are equal to those generated in the runner (the code does not depend on the modification of generated files)
-* Vendor is up to date (the code does not depend on the modification of vendorized files)
-* All applications can be built successfully using both gcc and clang
-
-All test must be successful before PRs can be merged.
-
-### Simulation script
-
-Additionally, a `test_all.sh` script is provided. Apart from compiling all apps with both gcc and clang, it will simulate them and check the result.
-
-The available parameters are:
-* COMPILER: `gcc` (default) or `clang` (can provide more than one)
-* SIMULATOR: `verilator` (default), `questasim` or disable simulation with `nosim` (only one, the last provided is used).
-* LINKER: `on_chip`(default), `flash_load` or `flash_exec` (can provide more than one)
-* TIMEOUT: Integer number of seconds (default 120)
-
-#### Usage
-
-##### Comands
-You can use two different commands to compile or simulate all the existing APPs:
-```
-make app-compile-all
-```
-```
-make app-simulate-all
-```
-Note that both commands allow the previous parameters to specify compiling or simulation options. E.g.:
-```
-make app-simulate-all LINKER=on_chip SIMULATOR=questasim COMPILER=clang TIMEOUT=150
-```
-
-##### Manually
-You can also **SOURCE** the script as
-```bash
-. util/test_all.sh on_chip questasim clang 150
-```
-
-*Pay special attention to the first period in the command!*
-You will be killing simulations that take too long, if you **EXECUTE** (`./test_all.sh`) this action kills the script.
-
-For both usages (commands or manual), the order of the arguments is irrelevant.
-
-> Note: Be sure to commit all your changes before running the script!
-
-* Applications that fail being built with gcc will not be simulated (skipped).
-* Some applications are skipped by default for not being suitable for simulation.
-* If a simulation takes too long (>timeout), it is killed.
-
-* Upon starting, the script will modify the `mcu_cfg.hjson` file to include all peripherals (so the largest number of apps can be run), re-generates the mcu and re-builds the simulation model for the chosen tool.
-These changes can be reverted at the end of the execution (default). If changes were not commited, accepting this operation will revert them!
-
-The success of the script is not required for merging of a PR.
-
-## Debug
-
-Follow the [Debug](./docs/source/How_to/Debug.md) guide to debug core-v-mini-mcu.
-
-Alternatively, in case you are used to developing using Integrated Development Environments (IDEs), please check [the IDE readme](./IDEs.md).
-
-## Execute From Flash
-
-Follow the [ExecuteFromFlash](./docs/source/How_to/ExecuteFromFlash.md) guide to exxecute code directly from the FLASH with modelsim, FPGA, or ASIC.
-
-## Emulation on Xilinx FPGAs
-
-This project offers two different X-HEEP implementetions on Xilinx FPGAs, called Standalone and FEMU.
-
-### Standalone
-
-In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the FPGA, and its input/output are connected to the available headers on the FPGA board.
-
-Three FPGA boards are supported: the Xilinx Pynq-z2, Nexys-A7-100t, Zynq Ultrascale+ ZCU104.
-
-Make sure you have the FPGA board files installed in your Vivado.
-
-For example, for the Pynq-Z2 board, use the documentation provided at the following [link](https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html) to download and install them:
-
-To build and program the bitstream for your FPGA with vivado, type:
-
-```
-make vivado-fpga FPGA_BOARD=pynq-z2
-```
-
-or
-
-```
-make vivado-fpga FPGA_BOARD=nexys-a7-100t
-```
-
-or
-
-```
-make vivado-fpga FPGA_BOARD=zcu104
-```
-
-or add the flag `use_bscane_xilinx` to use the native Xilinx scanchain:
-
-```
-make vivado-fpga FPGA_BOARD=pynq-z2 FUSESOC_FLAGS=--flag=use_bscane_xilinx
-```
-
-Only Vivado 2021.2 has been tried.
-
-To program the bitstream, open Vivado,
-
-```
-open --> Hardware Manager --> Open Target --> Autoconnect --> Program Device
-```
-
-and choose the file `openhwgroup.org_systems_core-v-mini-mcu_0.bit`.
-
-Or simply type:
-
-```
-bash vivado-fpga-pgm FPGA_BOARD=pynq-z2
-```
-
-or
-
-```
-make vivado-fpga-pgm FPGA_BOARD=nexys-a7-100t
-```
-
-To run SW, follow the [Debug](./docs/source/How_to/Debug.md) guide
-to load the binaries with the HS2 cable over JTAG,
-or follow the [ExecuteFromFlash](./docs/source/How_to/ExecuteFromFlash.md)
-guide if you have a FLASH attached to the FPGA.
-
-Do not forget that the `pynq-z2` board requires you to have the ethernet cable attached to the board while running.
-
-For example, if you want to run your application using flash_exec, do as follow:
-
-compile your application, e.g. `make app PROJECT=example_matfadd TARGET=pynq-z2 ARCH=rv32imfc LINKER=flash_exec`
-
-and then follow the [ExecuteFromFlash](./docs/source/How_to/ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly.
-
-To look at the output of your printf, run in another terminal:
-
-`picocom -b 9600 -r -l --imap lfcrlf /dev/ttyUSB2`
-
-Please be sure to use the right `ttyUSB` number (you can discover it with `dmesg --time-format iso | grep FTDI` for example).
-
-### FPGA EMUlation Platform (FEMU)
-
-In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the Xilinx Zynq-7020 chip on the Pynq-Z2 board and Linux is run on the ARM-based processing system (PS) side of the same chip.
-
-NOTE: This platform is not part of this repository, but you can access it with the following link: [FEMU](https://github.com/esl-epfl/x-heep-femu-sdk).
-
-# ASIC Implementation
-
-This project can be implemented using standard cells based ASIC flow.
-
-## Synthesis with Synopsys Design Compiler
-
-First, you need to provide technology-dependent implementations of some of the cells which require specific instantiation.
-
-Then, please provide a set_libs.tcl and set_constraints.tcl scripts to set link and target libraries, and constraints as the clock.
-
-To generate the `analyze` script for the synthesis scripts with DC, execute:
-
-```
-make asic
-```
-
-## OpenRoad support for SkyWater 130nm
-
-We are working on supporting OpenRoad and SkyWater 130nm PDK, please refer to the
-[Implement on ASIC](./docs/source/How_to/ImplementASIC.md) page. This is not ready yet, it has not been tested.
-
-This relies on a fork of [edalize](https://github.com/davideschiavone/edalize) that contains templates for Design Compiler and OpenRoad.
+```
\ No newline at end of file
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deleted file mode 100644
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diff --git a/hw/vendor/esl_epfl_x_heep/configs/ci.hjson b/hw/vendor/esl_epfl_x_heep/configs/ci.hjson
new file mode 100644
index 00000000..51a278b7
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/configs/ci.hjson
@@ -0,0 +1,23 @@
+{
+    bus_type: "onetoM",
+    ram_banks: {
+        code_and_data: {
+            num: 6
+            sizes: 32
+        }
+    }
+
+    linker_sections: 
+    [
+        {
+            name: code
+            start: 0
+            #minimum size for freeRTOS and clang
+            size: 0x00000D800
+        },
+        {
+            name: data
+            start: 0x00000D800
+        }
+    ]
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/configs/example.py b/hw/vendor/esl_epfl_x_heep/configs/example.py
new file mode 100644
index 00000000..b9e3faf2
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/configs/example.py
@@ -0,0 +1,18 @@
+from x_heep_gen.linker_section import LinkerSection
+from x_heep_gen.system import XHeep, BusType
+
+def config():
+    system = XHeep(BusType.NtoM)
+    system.add_ram_banks([32] * 2)
+    system.add_ram_banks_il(2, 64, "data_interleaved")
+
+    system.add_linker_section(LinkerSection.by_size("code", 0, 0x00000C800))
+    system.add_linker_section(LinkerSection("data", 0x00000C800, None))
+
+    # Here the system is build,
+    # The missing gaps are filled, like the missing end address of the data section.
+    system.build()
+    if not system.validate():
+        raise RuntimeError("there are errors")
+
+    return system
diff --git a/hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson b/hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson
new file mode 100644
index 00000000..aac0801e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson
@@ -0,0 +1,40 @@
+{
+    bus_type: "NtoM",
+    ram_banks: {
+        code_and_data: {
+            sizes: 64
+        }
+        more_data: {
+            type: continuous
+            num: 2
+            sizes: 32
+        }
+        data_interleaved: {
+            auto_section: auto
+            // the name is used by example_matadd_interleaved as .xheep_data_interleaved
+            type: interleaved
+            num: 4
+            size: 16
+        }
+        data_interleaved_2: {
+            auto_section: auto
+            type: interleaved
+            num: 2
+            size: 16
+        }
+    }
+
+    linker_sections: 
+    [
+        {
+            name: code
+            start: 0
+            // minimum size for freeRTOS and clang
+            size: 0x00000D800
+        },
+        {
+            name: data
+            start: 0x00000D800
+        }
+    ]
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/configs/general.hjson b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
new file mode 100644
index 00000000..f7040640
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
@@ -0,0 +1,24 @@
+{
+    ram_address: 0
+    bus_type: "onetoM",
+    ram_banks: {
+        code_and_data: {
+            num: 2
+            sizes: [32]
+        }
+    }
+
+    linker_sections:
+    [
+        {
+            name: code
+            start: 0
+            #minimum size for freeRTOS and clang
+            size: 0x00000D800
+        },
+        {
+            name: data
+            start: 0x00000D800
+        }
+    ]
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/configs/testall.hjson b/hw/vendor/esl_epfl_x_heep/configs/testall.hjson
new file mode 100644
index 00000000..36828dc8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/configs/testall.hjson
@@ -0,0 +1,23 @@
+{
+    bus_type: "onetoM",
+    ram_banks: {
+        code_and_data: {
+            num: 3
+            sizes: 32
+        }
+    }
+
+    linker_sections: 
+    [
+        {
+            name: code
+            start: 0
+            #minimum size for freeRTOS and clang
+            size: 0x00000D800
+        },
+        {
+            name: data
+            start: 0x00000D800
+        }
+    ]
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu-fpga.core b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu-fpga.core
new file mode 100644
index 00000000..38663aea
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu-fpga.core
@@ -0,0 +1,72 @@
+CAPI=2:
+
+# Copyright 2024 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+name: openhwgroup.org:systems:core-v-mini-mcu-fpga
+description: CORE-V MINI-MCU FPGA related files.
+
+filesets:
+  rtl-fpga:
+    depend:
+    - x-heep::packages
+    files:
+    - hw/fpga/sram_wrapper.sv
+    file_type: systemVerilogSource
+
+  ip-fpga:
+    files:
+    - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
+    - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/cv32e40p_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/cv32e40x_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/cv32e40px_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/pad_cell_input_xilinx.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/pad_cell_output_xilinx.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/pad_cell_inout_xilinx.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
+    - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }
+
+  ip-fpga-pynq-z2:
+    files:
+    - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+
+  ip-fpga-nexys:
+    files:
+    - hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+
+  ip-fpga-zcu104:
+    files:
+    - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+
+  xdc-fpga-nexys:
+    files:
+    - hw/fpga/constraints/nexys/pin_assign.xdc
+    - hw/fpga/constraints/nexys/constraints.xdc
+    file_type: xdc
+
+  xdc-fpga-pynq-z2:
+    files:
+    - hw/fpga/constraints/pynq-z2/pin_assign.xdc
+    - hw/fpga/constraints/pynq-z2/constraints.xdc
+    file_type: xdc
+
+  xdc-fpga-zcu104:
+    files:
+    - hw/fpga/constraints/zcu104/pin_assign.xdc
+    file_type: xdc
+
+
+targets:
+  default: &default_target
+    filesets:
+    - rtl-fpga
+    - ip-fpga
+    - target_pynq-z2 ? (ip-fpga-pynq-z2)
+    - target_pynq-z2 ? (xdc-fpga-pynq-z2)
+    - target_nexys-a7-100t ? (ip-fpga-nexys)
+    - target_nexys-a7-100t ? (xdc-fpga-nexys)
+    - target_zcu104 ? (ip-fpga-zcu104)
+    - target_zcu104 ? (xdc-fpga-zcu104)
diff --git a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core
index dd439888..aef1f20e 100644
--- a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core
+++ b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.core
@@ -30,6 +30,7 @@ filesets:
     - x-heep:obi_spimemio:0.1.0
     - x-heep:ip:boot_rom
     - x-heep:ip:dma
+    - x-heep:ip:dma_subsystem
     - x-heep:ip:i2s
     - x-heep:ip:power_manager
     - x-heep:ip:fast_intr_ctrl
@@ -84,6 +85,7 @@ filesets:
     - hw/ip/boot_rom/boot_rom.vlt
     - hw/ip/obi_spimemio/obi_spimemio.vlt
     - hw/ip/dma/dma.vlt
+    - hw/ip/dma_subsystem/dma_subsystem.vlt
     - hw/ip/pdm2pcm/pdm2pcm.vlt
     - hw/ip_examples/pdm2pcm_dummy/pdm2pcm_dummy.vlt
     - hw/ip/power_manager/power_manager.vlt
@@ -95,40 +97,12 @@ filesets:
     file_type: vlt
 
   rtl-fpga:
+    depend:
+    - openhwgroup.org:systems:core-v-mini-mcu-fpga
     files:
     - hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
-    - hw/fpga/sram_wrapper.sv
     file_type: systemVerilogSource
 
-  ip-fpga:
-    files:
-    - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
-    - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/cv32e40p_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/cv32e40x_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/cv32e40px_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_output_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_inout_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }
-
-  ip-fpga-pynq-z2:
-    files:
-    - hw/fpga/scripts/pynq-z2/set_board.tcl: { file_type: tclSource }
-    - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
-
-  ip-fpga-nexys:
-    files:
-    - hw/fpga/scripts/nexys/set_board.tcl: { file_type: tclSource }
-    - hw/fpga/scripts/nexys/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
-
-  ip-fpga-zcu104:
-    files:
-    - hw/fpga/scripts/zcu104/set_board.tcl: { file_type: tclSource }
-    - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
-
   ip-asic:
     depend:
     - technology::prim_mytech
@@ -147,28 +121,6 @@ filesets:
     files:
       - hw/asic/sky130/sky130_sram_4kbyte_1rw_32x1024_8_TT_1p8V_25C.lib : { copyto: lib/sky130_sram_4kbyte_1rw_32x1024_8_TT_1p8V_25C.lib }
 
-  xdc-fpga-nexys:
-    files:
-    - hw/fpga/constraints/nexys/pin_assign.xdc
-    - hw/fpga/constraints/nexys/constraints.xdc
-    file_type: xdc
-
-  xdc-fpga-pynq-z2:
-    files:
-    - hw/fpga/constraints/pynq-z2/pin_assign.xdc
-    - hw/fpga/constraints/pynq-z2/constraints.xdc
-    file_type: xdc
-
-  xdc-fpga-zcu104:
-    files:
-    - hw/fpga/constraints/zcu104/pin_assign.xdc
-    file_type: xdc
-
-  netlist-fpga:
-    files:
-    - build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
-    file_type: verilogSource
-
   # Scripts for hooks
   post_build_modelsim_scripts:
     files:
@@ -285,6 +237,10 @@ parameters:
     datatype: bool
     paramtype: vlogdefine
     default: false
+  FPGA_SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
   FPGA_NEXYS:
     datatype: bool
     paramtype: vlogdefine
@@ -463,19 +419,19 @@ targets:
     filesets_append:
     - x_heep_system
     - rtl-fpga
-    - ip-fpga-nexys
-    - ip-fpga
-    - xdc-fpga-nexys
     parameters:
     - COREV_PULP
     - FPU
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
     - FPGA_NEXYS=true
     tools:
       vivado:
         part: xc7a100tcsg324-1
+        board_part: digilentinc.com:nexys-a7-100t:part0:1.3
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_nexys_a7_100t_board_files]
     toplevel: [xilinx_core_v_mini_mcu_wrapper]
 
   pynq-z2:
@@ -485,18 +441,18 @@ targets:
     filesets_append:
     - x_heep_system
     - rtl-fpga
-    - ip-fpga-pynq-z2
-    - ip-fpga
-    - xdc-fpga-pynq-z2
     parameters:
     - COREV_PULP
     - FPU
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
     tools:
       vivado:
         part: xc7z020clg400-1
+        board_part: tul.com.tw:pynq-z2:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_pynq_z2_board_files]
     toplevel: [xilinx_core_v_mini_mcu_wrapper]
 
   zcu104:
@@ -506,19 +462,19 @@ targets:
     filesets_append:
     - x_heep_system
     - rtl-fpga
-    - ip-fpga-zcu104
-    - ip-fpga
-    - xdc-fpga-zcu104
     parameters:
     - COREV_PULP
     - FPU
     - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
     - FPGA_ZCU104=true
     tools:
       vivado:
         part: xczu7ev-ffvc1156-2-e
+        board_part: xilinx.com:zcu104:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files]
     toplevel: [xilinx_core_v_mini_mcu_wrapper]
     
   asic_synthesis:
diff --git a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.dc.upf.tpl b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.dc.upf.tpl
new file mode 100644
index 00000000..b08abad8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.dc.upf.tpl
@@ -0,0 +1,159 @@
+upf_version 2.1
+
+set_design_top core_v_mini_mcu
+set_scope .
+
+
+<%text>
+#####################
+##  POWER DOMAINS  ##
+#####################
+</%text>\
+
+create_power_domain PD_TOP -include_scope
+create_power_domain PD_CPU -elements {cpu_subsystem_i}
+create_power_domain PD_PERIP_SUBS -elements {peripheral_subsystem_i}
+% for bank in xheep.iter_ram_banks():
+create_power_domain PD_MEM_BANK_${bank.name()} -elements {memory_subsystem_i/ram${bank.name()}_i}
+% endfor
+
+
+<%text>
+####################
+##  POWER STATES  ##
+####################
+</%text>\
+
+add_power_state PD_TOP.primary -state TOP_ON <%text>\</%text>
+    {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}}
+
+add_power_state PD_CPU.primary -state CPU_ON <%text>\</%text>
+    {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}}
+
+add_power_state PD_CPU.primary -state CPU_OFF <%text>\</%text>
+    {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT
+
+add_power_state PD_PERIP_SUBS.primary -state PERIP_SUBS_ON <%text>\</%text>
+    {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}}
+
+add_power_state PD_PERIP_SUBS.primary -state PERIP_SUBS_OFF <%text>\</%text>
+    {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT
+
+% for bank in xheep.iter_ram_banks():
+add_power_state PD_MEM_BANK_${bank.name()}.primary -state MEM_BANK_${bank.name()}_ON <%text>\</%text>
+    {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}}
+
+add_power_state PD_MEM_BANK_${bank.name()}.primary -state MEM_BANK_${bank.name()}_OFF <%text>\</%text>
+    {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT
+
+% endfor
+
+<%text>
+###################
+##  SUPPLY NETS  ##
+###################
+</%text>\
+
+create_supply_port VDD -direction in
+create_supply_port VSS -direction in
+
+create_supply_net VDD
+create_supply_net VSS
+
+connect_supply_net VDD -ports VDD
+connect_supply_net VSS -ports VSS
+
+create_supply_set PD_TOP.primary -function {power VDD} -function {ground VSS} -update
+
+create_supply_net VDD_CPU
+create_supply_set PD_CPU.primary -function {power VDD_CPU} -function {ground VSS} -update
+
+create_supply_net VDD_PERIP_SUBS
+create_supply_set PD_PERIP_SUBS.primary -function {power VDD_PERIP_SUBS} -function {ground VSS} -update
+
+% for bank in xheep.iter_ram_banks():
+create_supply_net VDD_MEM_BANK_${bank.name()}
+create_supply_set PD_MEM_BANK_${bank.name()}.primary -function {power VDD_MEM_BANK_${bank.name()}} -function {ground VSS} -update
+
+% endfor
+
+<%text>
+################
+##  SWITCHES  ##
+################
+</%text>\
+
+create_power_switch switch_PD_CPU <%text>\</%text>
+    -supply_set         PD_TOP.primary <%text>\</%text>
+    -domain             PD_CPU <%text>\</%text>
+    -input_supply_port  {sw_in     VDD} <%text>\</%text>
+    -output_supply_port {sw_out    VDD_CPU} <%text>\</%text>
+    -control_port       {sw_ctrl   ao_peripheral_subsystem_i/cpu_subsystem_pwr_ctrl_o<%text>\</%text>[pwrgate_en_n<%text>\</%text>]} <%text>\</%text>
+    -ack_port           {sw_ack    ao_peripheral_subsystem_i/cpu_subsystem_pwr_ctrl_i<%text>\</%text>[pwrgate_ack_n<%text>\</%text>]}  <%text>\</%text>
+    -on_state           {on_state  sw_in {sw_ctrl}} <%text>\</%text>
+    -off_state          {off_state {!sw_ctrl}}
+
+create_power_switch switch_PD_PERIP_SUBS <%text>\</%text>
+    -supply_set         PD_TOP.primary <%text>\</%text>
+    -domain             PD_PERIP_SUBS <%text>\</%text>
+    -input_supply_port  {sw_in     VDD} <%text>\</%text>
+    -output_supply_port {sw_out    VDD_PERIP_SUBS} <%text>\</%text>
+    -control_port       {sw_ctrl   ao_peripheral_subsystem_i/peripheral_subsystem_pwr_ctrl_o<%text>\</%text>[pwrgate_en_n<%text>\</%text>]} <%text>\</%text>
+    -ack_port           {sw_ack    ao_peripheral_subsystem_i/peripheral_subsystem_pwr_ctrl_i<%text>\</%text>[pwrgate_ack_n<%text>\</%text>]}  <%text>\</%text>
+    -on_state           {on_state  sw_in {sw_ctrl}} <%text>\</%text>
+    -off_state          {off_state {!sw_ctrl}}
+
+% for bank in xheep.iter_ram_banks():
+create_power_switch switch_PD_MEM_BANK_${bank.name()} <%text>\</%text>
+    -supply_set         PD_TOP.primary <%text>\</%text>
+    -domain             PD_MEM_BANK_${bank.name()} <%text>\</%text>
+    -input_supply_port  {sw_in     VDD} <%text>\</%text>
+    -output_supply_port {sw_out    VDD_MEM_BANK_${bank.name()}} <%text>\</%text>
+    -control_port       {sw_ctrl   ao_peripheral_subsystem_i/memory_subsystem_pwr_ctrl_o[${bank.name()}]<%text>\</%text>[pwrgate_en_n<%text>\</%text>]} <%text>\</%text>
+    -ack_port           {sw_ack    ao_peripheral_subsystem_i/memory_subsystem_pwr_ctrl_i[${bank.name()}]<%text>\</%text>[pwrgate_ack_n<%text>\</%text>]}  <%text>\</%text>
+    -on_state           {on_state  sw_in {sw_ctrl}} <%text>\</%text>
+    -off_state          {off_state {!sw_ctrl}}
+
+% endfor
+
+<%text>
+#################
+##  ISOLATION  ##
+#################
+</%text>\
+
+set_isolation cpu_iso <%text>\</%text>
+    -domain PD_CPU <%text>\</%text>
+    -isolation_power_net VDD <%text>\</%text>
+    -isolation_ground_net VSS <%text>\</%text>
+    -isolation_signal ao_peripheral_subsystem_i/cpu_subsystem_pwr_ctrl_o<%text>\</%text>[isogate_en_n<%text>\</%text>]  <%text>\</%text>
+    -isolation_sense low <%text>\</%text>
+    -clamp_value 0 <%text>\</%text>
+    -applies_to outputs <%text>\</%text>
+    -name_prefix cpu_iso_cell <%text>\</%text>
+    -location parent
+
+set_isolation perip_subs_iso <%text>\</%text>
+    -domain PD_PERIP_SUBS <%text>\</%text>
+    -isolation_power_net VDD <%text>\</%text>
+    -isolation_ground_net VSS <%text>\</%text>
+    -isolation_signal ao_peripheral_subsystem_i/peripheral_subsystem_pwr_ctrl_o<%text>\</%text>[isogate_en_n<%text>\</%text>]  <%text>\</%text>
+    -isolation_sense low <%text>\</%text>
+    -clamp_value 0 <%text>\</%text>
+    -applies_to outputs <%text>\</%text>
+    -name_prefix cpu_iso_cell <%text>\</%text>
+    -location parent
+
+% for bank in xheep.iter_ram_banks():
+set_isolation mem_bank_${bank.name()}_iso <%text>\</%text>
+    -domain PD_MEM_BANK_${bank.name()} <%text>\</%text>
+    -isolation_power_net VDD <%text>\</%text>
+    -isolation_ground_net VSS <%text>\</%text>
+    -isolation_signal ao_peripheral_subsystem_i/memory_subsystem_pwr_ctrl_o[${bank.name()}]<%text>\</%text>[isogate_en_n<%text>\</%text>]  <%text>\</%text>
+    -isolation_sense low <%text>\</%text>
+    -clamp_value 0 <%text>\</%text>
+    -elements {memory_subsystem_i/ram${bank.name()}_i/rdata_o} <%text>\</%text>
+    -name_prefix cpu_iso_cell <%text>\</%text>
+    -location parent
+
+% endfor
diff --git a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.upf.tpl b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.upf.tpl
index 5d687f9a..d7e0f6f1 100644
--- a/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.upf.tpl
+++ b/hw/vendor/esl_epfl_x_heep/core-v-mini-mcu.upf.tpl
@@ -13,8 +13,8 @@ set_scope .
 create_power_domain PD_TOP -include_scope
 create_power_domain PD_CPU -elements {cpu_subsystem_i}
 create_power_domain PD_PERIP_SUBS -elements {peripheral_subsystem_i}
-% for bank in range(ram_numbanks):
-create_power_domain PD_MEM_BANK_${bank} -elements {memory_subsystem_i/gen_sram[${bank}].ram_i}
+% for bank in xheep.iter_ram_banks():
+create_power_domain PD_MEM_BANK_${bank.name()} -elements {memory_subsystem_i/ram${bank.name()}_i}
 % endfor
 
 
@@ -39,11 +39,11 @@ add_power_state PD_PERIP_SUBS.primary -state PERIP_SUBS_ON <%text>\</%text>
 add_power_state PD_PERIP_SUBS.primary -state PERIP_SUBS_OFF <%text>\</%text>
     {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT
 
-% for bank in range(ram_numbanks):
-add_power_state PD_MEM_BANK_${bank}.primary -state MEM_BANK_${bank}_ON <%text>\</%text>
+% for bank in xheep.iter_ram_banks():
+add_power_state PD_MEM_BANK_${bank.name()}.primary -state MEM_BANK_${bank.name()}_ON <%text>\</%text>
     {-supply_expr {power == `{FULL_ON, 1.2} && ground == `{FULL_ON, 0.0}}}
 
-add_power_state PD_MEM_BANK_${bank}.primary -state MEM_BANK_${bank}_OFF <%text>\</%text>
+add_power_state PD_MEM_BANK_${bank.name()}.primary -state MEM_BANK_${bank.name()}_OFF <%text>\</%text>
     {-supply_expr {power == `{OFF} && ground == `{FULL_ON, 0.0}}} -simstate CORRUPT
 
 % endfor
@@ -71,9 +71,9 @@ create_supply_set PD_CPU.primary -function {power VDD_CPU} -function {ground VSS
 create_supply_net VDD_PERIP_SUBS
 create_supply_set PD_PERIP_SUBS.primary -function {power VDD_PERIP_SUBS} -function {ground VSS} -update
 
-% for bank in range(ram_numbanks):
-create_supply_net VDD_MEM_BANK_${bank}
-create_supply_set PD_MEM_BANK_${bank}.primary -function {power VDD_MEM_BANK_${bank}} -function {ground VSS} -update
+% for bank in xheep.iter_ram_banks():
+create_supply_net VDD_MEM_BANK_${bank.name()}
+create_supply_set PD_MEM_BANK_${bank.name()}.primary -function {power VDD_MEM_BANK_${bank.name()}} -function {ground VSS} -update
 
 % endfor
 
@@ -103,14 +103,14 @@ create_power_switch switch_PD_PERIP_SUBS <%text>\</%text>
     -on_state           {on_state  sw_in {sw_ctrl}} <%text>\</%text>
     -off_state          {off_state {!sw_ctrl}}
 
-% for bank in range(ram_numbanks):
-create_power_switch switch_PD_MEM_BANK_${bank} <%text>\</%text>
+% for bank in xheep.iter_ram_banks():
+create_power_switch switch_PD_MEM_BANK_${bank.name()} <%text>\</%text>
     -supply_set         PD_TOP.primary <%text>\</%text>
-    -domain             PD_MEM_BANK_${bank} <%text>\</%text>
+    -domain             PD_MEM_BANK_${bank.name()} <%text>\</%text>
     -input_supply_port  {sw_in     VDD} <%text>\</%text>
-    -output_supply_port {sw_out    VDD_MEM_BANK_${bank}} <%text>\</%text>
-    -control_port       {sw_ctrl   memory_subsystem_banks_powergate_switch_no[${bank}]} <%text>\</%text>
-    -ack_port           {sw_ack    memory_subsystem_banks_powergate_switch_ack_ni[${bank}]} <%text>\</%text>
+    -output_supply_port {sw_out    VDD_MEM_BANK_${bank.name()}} <%text>\</%text>
+    -control_port       {sw_ctrl   memory_subsystem_banks_powergate_switch_n[${bank.name()}]} <%text>\</%text>
+    -ack_port           {sw_ack    memory_subsystem_i.ram${bank.name()}_i.pwrgate_ack_no} <%text>\</%text>
     -on_state           {on_state  sw_in {sw_ctrl}} <%text>\</%text>
     -off_state          {off_state {!sw_ctrl}}
 
@@ -144,15 +144,15 @@ set_isolation perip_subs_iso <%text>\</%text>
     -name_prefix cpu_iso_cell <%text>\</%text>
     -location parent
 
-% for bank in range(ram_numbanks):
-set_isolation mem_bank_${bank}_iso <%text>\</%text>
-    -domain PD_MEM_BANK_${bank} <%text>\</%text>
+% for bank in xheep.iter_ram_banks():
+set_isolation mem_bank_${bank.name()}_iso <%text>\</%text>
+    -domain PD_MEM_BANK_${bank.name()} <%text>\</%text>
     -isolation_power_net VDD <%text>\</%text>
     -isolation_ground_net VSS <%text>\</%text>
-    -isolation_signal memory_subsystem_banks_powergate_iso_n[${bank}] <%text>\</%text>
+    -isolation_signal memory_subsystem_banks_powergate_iso_n[${bank.name()}] <%text>\</%text>
     -isolation_sense low <%text>\</%text>
     -clamp_value 0 <%text>\</%text>
-    -applies_to outputs <%text>\</%text>
+    -elements {memory_subsystem_i/ram${bank.name()}_i/rdata_o} <%text>\</%text>
     -name_prefix cpu_iso_cell <%text>\</%text>
     -location parent
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/requirements.txt b/hw/vendor/esl_epfl_x_heep/docs/requirements.txt
index cf9a675b..a4cd7e7b 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/requirements.txt
+++ b/hw/vendor/esl_epfl_x_heep/docs/requirements.txt
@@ -1,2 +1,3 @@
 sphinx-rtd-theme
-myst-parser
\ No newline at end of file
+myst-parser
+sphinxcontrib-apidoc
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/Configuration/Configuration.rst b/hw/vendor/esl_epfl_x_heep/docs/source/Configuration/Configuration.rst
new file mode 100644
index 00000000..c18a4e26
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/Configuration/Configuration.rst
@@ -0,0 +1,172 @@
+Configuration
+=============
+
+Project Configuration
+---------------------
+The project can be configured either by a hjson file or a python script.
+The default configurations and examples are located in the `config` directory.
+
+Hjson Configuration File
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. literalinclude:: ../../../configs/example_interleaved.hjson
+    :language: js
+
+Bus Type Configuration
+^^^^^^^^^^^^^^^^^^^^^^
+The bus type can either be configured to `NtoM` or `onetoM`.
+
+Ram Bank Configuration
+^^^^^^^^^^^^^^^^^^^^^^
+
+The system can be configured with banks of different sizes. The sizes should be a power of two in kiB.
+All banks are configured in one continuous address region.
+
+
+To configure interleaved banks the number and the size of the banks have to be provided.
+The following restrictions apply: All banks must have the same size and a power of two banks must be configured.
+
+
+For continuous banks the default mode, only the `sizes` filed is required.
+It can be either the size in kiB of a single bank,
+a dictionary of the same format containing more banks, or a list of multiple entries.
+If the `num` field is also provided the configuration in the `sizes` field is repeated `num` times.
+
+.. code:: js
+
+    ram_banks: {
+        code: {sizes: 64} // configure just one bank
+        
+        data: {
+            type: continuous // the default, can be omitted
+            num: 2
+            sizes: 32
+        }
+        
+        alt_data: {sizes: [32, 32]} // the same as data but with a list
+
+        more_complex: {
+        // This also works recursively so we can easily have different sizes of banks
+        // and in bigger numbers without listing them all one by one.
+            sizes: [
+                {
+                    num: 4
+                    sizes: 8
+                },
+                {
+                    num: 16
+                    sizes: 4
+                },
+            ]
+        }
+
+    }
+
+
+Linker Section Configuration
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+The linker script sections can be configured in two ways.
+Either a section can be matched with a group of ram banks
+or it can be manually defined.
+
+To automatically add a section the entry `auto_section: auto` should be added to the banks.
+It will add a section that matches the banks exactly, it can only be used in the non recursive part.
+The name of the section is set with the name of the group of banks.
+
+When manually setting the the linker section the name and the start address have to be provided.
+Additionally the end is either provided by it's address or by the size of the section.
+If no end is provided the end is inferred by the start of the next linker section.
+Or if no section follows, the end address of the last ram bank.
+
+Both configuration types can be freely combined as long as no section overlap.
+All sections will e sorted by the configuration system.
+
+The first two sections should always be code and data.
+The other name can be used in code with a `.xheep_` prefix, like in `example_matadd_interleaved`
+
+.. code:: c
+
+    int32_t __attribute__((section(".xheep_data_interleaved"))) m_c[16*16];
+
+.. code:: js
+
+    {
+        ram_address: 0
+        bus_type: "onetoM",
+        ram_banks: {
+            code_and_data: {
+                num: 2
+                sizes: [32]
+            }
+            i_am_a_section_name: {
+                auto_section: auto
+                sizes: 16
+            }
+        }
+
+        linker_sections: 
+        [
+            {
+                name: code
+                start: 0
+
+                // Alternatively the end tag can be used to provide the end.
+                size: 0x00000C800
+            },
+            {
+                name: data
+                start: 0x00000C800
+                // The end of this section will be at the beginning of the next.
+                // In this example the next section is i_am_a_section_name
+            }
+        ]
+    }
+
+
+
+
+Python Configuration
+~~~~~~~~~~~~~~~~~~~~
+
+The same can be done by using a python script
+
+.. literalinclude:: ../../../configs/example.py
+    :language: python
+
+
+The script should include a config function that return an :py:class:`x_heep_gen.system.XHeep` instance.
+The configuration is simmilar to the hjson one. The order in which sections are added is also the one used in hardware.
+The script writer is responsible to call :py:meth:`x_heep_gen.system.XHeep.build` and :py:meth:`x_heep_gen.system.XHeep.validate` and to raise an error in case of failure.
+The first does make the system ready to be used and the second does check for errors in the configuration.
+
+
+
+Select Configuration File
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To configure the system call
+
+.. code:: bash
+
+    make mcu-gen X_HEEP_CFG=configs/name_of_file.hjson
+
+
+
+Other configurations
+~~~~~~~~~~~~~~~~~~~~
+
+The pads are configured in `pad_cfg.hjson`.
+
+One part of the configuration is in `mcu_cfg.hjson`.
+
+Additionally if a `hjson` file is ussed for configuration the following parameters can be set to the make command to override the configuration:
+
+- `BUS=NtoM,onetoM`
+- `MEMORY_BANKS=integer`
+- `MEMORY_BANKS_IL=integer` 
+
+They will replace the configuration used in the configuration file.
+When one parameter is not provided the configuration files value is used.
+The memory banks configured this way will only be of size 32kiB.
+For compatibility reasons `MEMORY_BANKS` does not create linker sections while `MEMORY_BANKS_IL` does create a linker section.
+
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/AnalogMixedSignal.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/AnalogMixedSignal.md
index 8ba4ed5c..5e2d0bb4 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/AnalogMixedSignal.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/AnalogMixedSignal.md
@@ -1,4 +1,4 @@
-#  integrate Analog / Mixed-Signal simulations
+#  Integrate Analog / Mixed-Signal simulations
 
 ## About
 
@@ -68,7 +68,7 @@ The example AMS peripheral used by simulations of X-HEEP is located in `hw/ip_ex
 
 ### The repository's example SPICE files
 
-<p align="center"><img src="block_diagrams/example_adc.svg" width="500"></p>
+<p align="center"><img src="../images/example_adc.svg" width="500"></p>
 
 An example `adc.sp` file can be found in `hw/ip_examples/ams/analog`. This is a 1-bit ADC with a threshold that is configured through the 2-bit wide SEL input: an input of 00, 01, 10 and 11 will provide a threshold of 20%, 40%, 60% and 80% of VDD (1.2V) respectively. The input signal of the ADC is a sine wave with a peak-to-peak amplitude of 1.2V directly placed inside the SPICE netlist.
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile
deleted file mode 100644
index 2db8a17d..00000000
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile
+++ /dev/null
@@ -1,350 +0,0 @@
-# compile with Makefile
-
-You can compile the example applications and the platform using the Makefile. Type 'make help' or 'make' for more information. Moreover, please, check the different 'clean' commands to verify that you are using the corret one.
-
-## Generate core-v-mini-mcu package
-
-First, you have to generate the SystemVerilog package and C header file of the core-v-mini-mcu:
-
-```
-make mcu-gen
-```
-
-To change the default cpu type (i.e., cv32e20), the default bus type (i.e., onetoM),
-the default continuous memory size (i.e., 2 continuous banks) or the default interleaved memory size (i.e., 0 interleaved banks):
-
-```
-make mcu-gen CPU=cv32e40p BUS=NtoM MEMORY_BANKS=12 MEMORY_BANKS_IL=4
-```
-
-The last command generates x-heep with the cv32e40p core, with a parallel bus, and 16 memory banks (12 continuous and 4 interleaved),
-each 32KB, for a total memory of 512KB.
-
-## Compiling Software
-
-Don't forget to set the `RISCV` env variable to the compiler folder (without the `/bin` included).
-To run 'hello world' application, just type 'make app'.
-
-```
-make app
-```
-
-To run any other application, please use the following command with appropiate parameters:
-
-```
-app PROJECT=<folder_name_of_the_project_to_be_built> TARGET=sim(default),pynq-z2 LINKER=on_chip(default),flash_load,flash_exec COMPILER=gcc(default),clang COMPILER_PREFIX=riscv32-unknown-(default) ARCH=rv32imc(default),<any RISC-V ISA string supported by the CPU>
-
-Params:
-- PROJECT (ex: <folder_name_of_the_project_to_be_built>, hello_world(default))
-- TARGET (ex: sim(default),pynq-z2)
-- LINKER (ex: on_chip(default),flash_load,flash_exec)
-- COMPILER (ex: gcc(default),clang)
-- COMPILER_PREFIX (ex: riscv32-unknown-(default))
-- ARCH (ex: rv32imc(default),<any RISC-V ISA string supported by the CPU>)
-```
-
-For instance, to run 'hello world' app for the pynq-z2 FPGA targets, just run:
-
-```
-make app TARGET=pynq-z2
-```
-
-Or, if you use the OpenHW Group [GCC](https://www.embecosm.com/resources/tool-chain-downloads/#corev) compiler with CORE_PULP extensions, make sure to point the `RISCV` env variable to the OpenHW Group compiler, then just run:
-
-
-```
-make app COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_xcvhwlp1p0_xcvmem1p0_xcvmac1p0_xcvbi1p0_xcvalu1p0_xcvsimd1p0_xcvbitmanip1p0
-```
-
-This will create the executable file to be loaded in your target system (ASIC, FPGA, Simulation).
-Remember that, `X-HEEP` is using CMake to compile and link. Thus, the generated files after having
-compiled and linked are under `sw\build`
-
-## FreeROTS based applications
-
-'X-HEEP' supports 'FreeRTOS' based applications. Please see `sw\applications\blinky_freertos`.
-
-After that, you can run the command to compile and link the FreeRTOS based application. Please also set 'LINKER' and 'TARGET' parameters if needed.
-
-```
-make app PROJECT=blinky_freertos
-```
-
-The main FreeRTOS configuration is allocated under `sw\freertos`, in `FreeRTOSConfig.h`. Please, change this file based on your application requirements.
-Moreover, FreeRTOS is being fetch from 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git' by CMake. Specifically, 'V10.5.1' is used. Finally, the fetch repository is located under `sw\build\_deps` after building.
-
-## Simulating
-
-This project supports simulation with Verilator, Synopsys VCS, and Siemens Questasim.
-It relies on `fusesoc` to handle multiple EDA tools and parameters.
-For example, if you want to set the `FPU` and `COREV_PULP` parameters of the `cv32e40p` CPU,
-you need to add next to your compilation command `FUSESOC_PARAM="--COREV_PULP=1 --FPU=1"`
-Below the different EDA examples commands.
-
-### Compiling for Verilator
-
-To simulate your application with Verilator, first compile the HDL:
-
-```
-make verilator-sim
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
-```
-
-and type to run your compiled software:
-
-```
-./Vtestharness +firmware=../../../sw/build/main.hex
-```
-
-or to execute all these three steps type:
-
-```
-make run-helloworld
-```
-
-### Compiling for VCS
-
-To simulate your application with VCS, first compile the HDL:
-
-```
-make vcs-sim
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-vcs
-```
-
-and type to run your compiled software:
-
-```
-./openhwgroup.org_systems_core-v-mini-mcu_0 +firmware=../../../sw/build/main.hex
-```
-
-Waveforms can be viewed with Verdi. Make sure you have the env variable `VERDI_HOME` set to your Verdi install folder, then run your compiled software as above, but with the `-gui` flag:
-
-```
-./openhwgroup.org_systems_core-v-mini-mcu_0 +firmware=../../../sw/build/main.hex -gui
-```
-
-An Analog / Mixed-Signal simulation of X-HEEP, combining both the RTL system verilog files for the digital part and a SPICE file connected through a `control.init` file for the analog / mixed-signal part, can be ran by typing
-
-```
-make vcs-ams-sim
-```
-
-then going to the target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-vcs
-```
-
-and running the same executable as for the digital simulation. Note that with Verdi you can view both the digital and the analog waveforms.
-
-Additional instructions on how to run an analog / mixed-signal simulation of X-HEEP can be found [here](AnalogMixedSignal.md). To try out the simulation, we provide an example SPICE netlist of an simple 1-bit ADC created by us and exported from [xschem](https://xschem.sourceforge.io/stefan/index.html) and which uses the PTM 65nm bulk CMOS model from [https://ptm.asu.edu](https://ptm.asu.edu/).
-
-### Compiling for Questasim
-
-To simulate your application with Questasim, first set the env variable `MODEL_TECH` to your Questasim bin folder, then compile the HDL:
-
-```
-make questasim-sim
-```
-
-then, go to your target system built folder
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim/
-```
-
-and type to run your compiled software:
-
-```
-make run PLUSARGS="c firmware=../../../sw/build/main.hex"
-```
-
-You can also use vopt for HDL optimized compilation:
-
-```
-make questasim-sim-opt
-```
-
-then go to
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim_opt-modelsim/
-```
-and
-
-```
-make run RUN_OPT=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
-```
-
-You can also compile with the UPF power domain description as:
-
-```
-make questasim-sim-opt-upf FUSESOC_PARAM="--USE_UPF"
-```
-
-and then execute software as:
-
-```
-make run RUN_OPT=1 RUN_UPF=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
-```
-
-Questasim version must be >= Questasim 2020.4
-
-### UART DPI
-
-To simulate the UART, we use the LowRISC OpenTitan [UART DPI](https://github.com/lowRISC/opentitan/tree/master/hw/dv/dpi/uartdpi).
-Read how to interact with it in the Section "Running Software on a Verilator Simulation with Bazel" [here](https://opentitan.org/guides/getting_started/setup_verilator.html#running-software-on-a-verilator-simulation-with-bazel).
-The output of the UART DPI module is printed in the `uart0.log` file in the simulation folder.
-
-For example, to see the "hello world!" output of the Verilator simulation:
-
-```
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
-./Vtestharness +firmware=../../../sw/build/main.hex
-cat uart0.log
-```
-
-## Automatic testing
-
-X-HEEP includes two tools to perform automatic tests over your modifications.
-
-### Github CIs
-
-Upon push, tests are run on Github runners, these include:
-* The generated `.sv` files pushed are equal to those generated in the runner (the code does not depend on the modification of generated files)
-* Vendor is up to date (the code does not depend on the modification of vendorized files)
-* All applications can be built successfully using both gcc and clang
-
-All test must be successful before PRs can be merged.
-
-### Simulation script
-
-Additionally, a `test_all.sh` script is provided. Apart from compiling all apps with both gcc and clang, it will simulate them and check the result.
-
-The available parameters are:
-* COMPILER: `gcc` (default) or `clang` (can provide more than one)
-* SIMULATOR: `verilator` (default), `questasim` or disable simulation with `nosim` (only one, the last provided is used).
-* LINKER: `on_chip`(default), `flash_load` or `flash_exec` (can provide more than one)
-* TIMEOUT: Integer number of seconds (default 120)
-
-#### Usage
-
-##### Comands
-You can use two different commands to compile or simulate all the existing APPs:
-```
-make app-compile-all
-```
-```
-make app-simulate-all
-```
-Note that both commands allow the previous parameters to specify compiling or simulation options. E.g.:
-```
-make app-simulate-all LINKER=on_chip SIMULATOR=questasim COMPILER=clang TIMEOUT=150
-```
-
-##### Manually
-You can also **SOURCE** the script as
-```bash
-. util/test_all.sh on_chip questasim clang 150
-```
-
-*Pay special attention to the first period in the command!*
-You will be killing simulations that take too long, if you **EXECUTE** (`./test_all.sh`) this action kills the script.
-
-For both usages (commands or manual), the order of the arguments is irrelevant.
-
-> Note: Be sure to commit all your changes before running the script!
-
-* Applications that fail being built with gcc will not be simulated (skipped).
-* Some applications are skipped by default for not being suitable for simulation.
-* If a simulation takes too long (>timeout), it is killed.
-
-* Upon starting, the script will modify the `mcu_cfg.hjson` file to include all peripherals (so the largest number of apps can be run), re-generates the mcu and re-builds the simulation model for the chosen tool.
-These changes can be reverted at the end of the execution (default). If changes were not commited, accepting this operation will revert them!
-
-The success of the script is not required for merging of a PR.
-
-## Debug
-
-Follow the [Debug](./Debug.md) guide to debug core-v-mini-mcu.
-
-## Execute From Flash
-
-Follow the [ExecuteFromFlash](./ExecuteFromFlash.md) guide to exxecute code directly from the FLASH with modelsim, FPGA, or ASIC.
-
-## Emulation on Xilinx FPGAs
-
-This project offers two different X-HEEP implementetions on Xilinx FPGAs, called Standalone and FEMU.
-
-### Standalone
-
-In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the FPGA, and its input/output are connected to the available headers on the FPGA board.
-
-Two FPGA boards are supported: the Xilinx Pynq-z2 and Nexys-A7-100t.
-
-Make sure you have the FPGA board files installed in your Vivado.
-
-For example, for the Pynq-Z2 board, use the documentation provided at the following [link](https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html) to download and install them:
-
-To build and program the bitstream for your FPGA with vivado, type:
-
-```
-make vivado-fpga FPGA_BOARD=pynq-z2
-```
-
-or
-
-```
-make vivado-fpga FPGA_BOARD=nexys-a7-100t
-```
-
-or add the flag `use_bscane_xilinx` to use the native Xilinx scanchain:
-
-```
-make vivado-fpga FPGA_BOARD=pynq-z2 FUSESOC_FLAGS=--flag=use_bscane_xilinx
-```
-
-Only Vivado 2021.2 has been tried.
-
-To program the bitstream, open Vivado,
-
-```
-open --> Hardware Manager --> Open Target --> Autoconnect --> Program Device
-```
-
-and choose the file `openhwgroup.org_systems_core-v-mini-mcu_0.bit`
-
-To run SW, follow the [Debug](./Debug.md) guide
-to load the binaries with the HS2 cable over JTAG,
-or follow the [ExecuteFromFlash](./ExecuteFromFlash.md)
-guide if you have a FLASH attached to the FPGA.
-
-Do not forget that the `pynq-z2` board requires you to have the ethernet cable attached to the board while running.
-
-For example, if you want to run your application using flash_exec, do as follow:
-
-compile your application, e.g. `make app PROJECT=example_matfadd TARGET=pynq-z2 ARCH=rv32imfc LINKER=flash_exec`
-
-and then follow the [ExecuteFromFlash](./ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly.
-
-To look at the output of your printf, run in another terminal:
-
-`picocom -b 9600 -r -l --imap lfcrlf /dev/ttyUSB2`
-
-Please be sure to use the right `ttyUSB` number (you can discover it with `dmesg --time-format iso | grep FTDI` for example).
-
-### FPGA EMUlation Platform (FEMU)
-
-In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the Xilinx Zynq-7020 chip on the Pynq-Z2 board and Linux is run on the ARM-based processing system (PS) side of the same chip.
-
-NOTE: This platform is not part of this repository, but you can access it with the following link: [FEMU](https://github.com/esl-epfl/x-heep-femu-sdk).
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile.md
new file mode 100644
index 00000000..774f8ae3
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/CompileMakefile.md
@@ -0,0 +1,145 @@
+# Compile with Makefile
+
+You can compile the example applications and the platform using the Makefile. Type 'make help' or 'make' for more information. Moreover, please, check the different 'clean' commands to verify that you are using the corret one.
+
+## Generate core-v-mini-mcu package
+
+First, you have to generate the SystemVerilog package and C header file of the core-v-mini-mcu:
+
+```
+make mcu-gen
+```
+
+To change the default cpu type (i.e., cv32e20), the default bus type (i.e., onetoM),
+the default continuous memory size (i.e., 2 continuous banks) or the default interleaved memory size (i.e., 0 interleaved banks):
+
+```
+make mcu-gen CPU=cv32e40p BUS=NtoM MEMORY_BANKS=12 MEMORY_BANKS_IL=4
+```
+
+The last command generates x-heep with the cv32e40p core, with a parallel bus, and 16 memory banks (12 continuous and 4 interleaved),
+each 32KB, for a total memory of 512KB.
+This method is limmited to 32KB banks.
+
+To configure the ram banks with more flexibility, edit `configs/general.hjson` or provided your own one.
+Both method work together the first one overrides the second.
+
+```
+make mcu-gen X_HEEP_CFG=configs/my_config.hjson
+```
+
+For more information see Configuration section.
+
+## Compiling Software
+
+Don't forget to set the `RISCV` env variable to the compiler folder (without the `/bin` included).
+To run 'hello world' application, just type 'make app'.
+
+```
+make app
+```
+
+To run any other application, please use the following command with appropiate parameters:
+
+```
+app PROJECT=<folder_name_of_the_project_to_be_built> TARGET=sim(default),pynq-z2 LINKER=on_chip(default),flash_load,flash_exec COMPILER=gcc(default),clang COMPILER_PREFIX=riscv32-unknown-(default) ARCH=rv32imc(default),<any RISC-V ISA string supported by the CPU>
+
+Params:
+- PROJECT (ex: <folder_name_of_the_project_to_be_built>, hello_world(default))
+- TARGET (ex: sim(default),pynq-z2)
+- LINKER (ex: on_chip(default),flash_load,flash_exec)
+- COMPILER (ex: gcc(default),clang)
+- COMPILER_PREFIX (ex: riscv32-unknown-(default))
+- ARCH (ex: rv32imc(default),<any RISC-V ISA string supported by the CPU>)
+```
+
+For instance, to run 'hello world' app for the pynq-z2 FPGA targets, just run:
+
+```
+make app TARGET=pynq-z2
+```
+
+Or, if you use the OpenHW Group [GCC](https://www.embecosm.com/resources/tool-chain-downloads/#corev) compiler with CORE_PULP extensions, make sure to point the `RISCV` env variable to the OpenHW Group compiler, then just run:
+
+
+```
+make app COMPILER_PREFIX=riscv32-corev- ARCH=rv32imc_zicsr_zifencei_xcvhwlp_xcvmem_xcvmac_xcvbi_xcvalu_xcvsimd_xcvbitmanip
+```
+
+This will create the executable file to be loaded in your target system (ASIC, FPGA, Simulation).
+Remember that, `X-HEEP` is using CMake to compile and link. Thus, the generated files after having
+compiled and linked are under `sw\build`
+
+## FreeROTS based applications
+
+'X-HEEP' supports 'FreeRTOS' based applications. Please see `sw\applications\blinky_freertos`.
+
+After that, you can run the command to compile and link the FreeRTOS based application. Please also set 'LINKER' and 'TARGET' parameters if needed.
+
+```
+make app PROJECT=blinky_freertos
+```
+
+The main FreeRTOS configuration is allocated under `sw\freertos`, in `FreeRTOSConfig.h`. Please, change this file based on your application requirements.
+Moreover, FreeRTOS is being fetch from 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git' by CMake. Specifically, 'V10.5.1' is used. Finally, the fetch repository is located under `sw\build\_deps` after building.
+
+
+## Automatic testing
+
+X-HEEP includes two tools to perform automatic tests over your modifications.
+
+### Github CIs
+
+Upon push, tests are run on Github runners, these include:
+* The generated `.sv` files pushed are equal to those generated in the runner (the code does not depend on the modification of generated files)
+* Vendor is up to date (the code does not depend on the modification of vendorized files)
+* All applications can be built successfully using both gcc and clang
+
+All test must be successful before PRs can be merged.
+
+### Simulation script
+
+Additionally, a `test_all.sh` script is provided. Apart from compiling all apps with both gcc and clang, it will simulate them and check the result.
+
+The available parameters are:
+* COMPILER: `gcc` (default) or `clang` (can provide more than one)
+* SIMULATOR: `verilator` (default), `questasim` or disable simulation with `nosim` (only one, the last provided is used).
+* LINKER: `on_chip`(default), `flash_load` or `flash_exec` (can provide more than one)
+* TIMEOUT: Integer number of seconds (default 120)
+
+#### Usage
+
+##### Comands
+You can use two different commands to compile or simulate all the existing APPs:
+```
+make app-compile-all
+```
+```
+make app-simulate-all
+```
+Note that both commands allow the previous parameters to specify compiling or simulation options. E.g.:
+```
+make app-simulate-all LINKER=on_chip SIMULATOR=questasim COMPILER=clang TIMEOUT=150
+```
+
+##### Manually
+You can also **SOURCE** the script as
+```bash
+. util/test_all.sh on_chip questasim clang 150
+```
+
+*Pay special attention to the first period in the command!*
+You will be killing simulations that take too long, if you **EXECUTE** (`./test_all.sh`) this action kills the script.
+
+For both usages (commands or manual), the order of the arguments is irrelevant.
+
+> Note: Be sure to commit all your changes before running the script!
+
+* Applications that fail being built with gcc will not be simulated (skipped).
+* Some applications are skipped by default for not being suitable for simulation.
+* If a simulation takes too long (>timeout), it is killed.
+
+* Upon starting, the script will modify the `mcu_cfg.hjson` file to include all peripherals (so the largest number of apps can be run), re-generates the mcu and re-builds the simulation model for the chosen tool.
+These changes can be reverted at the end of the execution (default). If changes were not commited, accepting this operation will revert them!
+
+The success of the script is not required for merging of a PR.
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md
index 2a5882f6..9bcc76fb 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Debug.md
@@ -1,11 +1,11 @@
-#  debug
+#  Debug
 
 ## Prerequisite
 
 1. Install the required linux tools:
 
 ```
-sudo apt install pkg-config libftdi1-2 libusb-1.0-4
+sudo apt install pkg-config libftdi1-2
 ```
 
 You need at least gcc>10, so in case you do not have it:
@@ -42,7 +42,7 @@ The remote bitbang server is simplemented in the folder ./hw/vendor/pulp_platfor
 
 ### Verilator (C++ only)
 
-To simulate your application with Questasim using the remote_bitbang server, you need to compile you system adding the `JTAG DPI` functions:
+To simulate your application with Verilator using the remote_bitbang server, you need to compile you system adding the `JTAG DPI` functions:
 
 ```
 make verilator-sim FUSESOC_PARAM="--JTAG_DPI=1"
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExecuteFromFlash.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExecuteFromFlash.md
index 8413a129..ce7b9a9c 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExecuteFromFlash.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExecuteFromFlash.md
@@ -1,4 +1,4 @@
-#  execute Code from FLASH
+#  Execute Code from FLASH
 
 ## Boot Procedure
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md
deleted file mode 100644
index bbc89bd3..00000000
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ExternalDevices.md
+++ /dev/null
@@ -1,151 +0,0 @@
-# interface with external devices
-
-The top module [`core_v_mini_mcu`]((./../../../hw/core-v-mini-mcu/corecore_v_mini_mcu.sv) exposes several external interfaces:
-
-- `ext_xbar_master`: N ports to connect external masters to the internal system bus.
-
-- Five external ports to connect internal masters (e.g., CPU instruction and data ports) to external slaves. Every internal master is exposed to the external subsystem:
-   1. `ext_core_instr`: CPU instruction interface.
-   2. `ext_core_data`: CPU data interface.
-   3. `ext_debug_master`: debug interface.
-   4. `ext_dma_read_ch0`: DMA read master, channel 0.
-   5. `ext_dma_write_ch0`: DMA write master, channel 0.
-   6. `ext_dma_addr_ch0`: DMA address (read) master, channel 0.
-
-- `ext_peripheral_slave`: 1 peripheral slave port connected to the system bus (through the peripheral interface).
-
-The number of external master ports is set by the [`EXT_XBAR_NMASTER`](./../../../tb/testharness_pkg.sv#L10) parameter from `testharness_pkg`.
-Multiple OBI slaves can be connected to the exposed internal masters using an external bus, as demonstrated in [`testharness.sv`](./../../../tb/testharness.sv#L232).
-
-> NOTE: the internal bus has no master port connected to the external subsystem. Therefore, an external master cannot send a request to an external slave through one of the exposed master ports. All the address decoding must be done by the external bus: the request must be forwarded to one of the `ext_xbar_master` ports only if the target address falls into the space where internal slaves are mapped. This can be achieved using a 1-to-2 crossbar for each external master as done [here](./../../../tb/ext_bus.sv#L131).
-
-Finally, only one peripheral slave port is available to the external subsystem.
-
-## External device example
-
-One example using the external ports is provided where:
-
-- hw/ip_examples/slow_sram is a memory slave device
-- hw/ip_examples/memcopy is a slave peripheral with a master port. It implements a simple memcopy feature (i.e., DMA).
-- hw/ip_examples/ams is an example AMS peripheral which can interface with SPICE netlists to run mixed-signal simulations (in this repository, the example analog peripheral is a 1-bit ADC)
-    - For more information, see [here](AnalogMixedSignal.md)
-
-## Run the external device example
-
-To run the external device example, first compile the software example:
-
-```bash
-make app PROJECT=example_external_dma
-```
-
-By default, the external device example RTL code is disabled. This example is available for the sim and sim_opt targets.
-
-For example, compile for Verilator with:
-
-```
-make verilator-sim
-```
-
-then, go to your target system built folder
-
-```bash
-cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
-```
-
-and type to run your compiled software:
-
-```bash
-./Vtestharness +firmware=../../../sw/build/main.hex
-```
-
-If you don't compile the platform with the correct fusesoc flag, the simulation will hang forever because the external peripheral is disabled and never replies.
-
-You can display the UART output with:
-
-```bash
-cat uart0.log
-```
-
-It should print:
-
-```
---- MEMCOPY EXAMPLE - external peripheral ---
-Init the PLIC...success
-Set MEMCOPY interrupt priority to 1...success
-Enable MEMCOPY interrupt...Success
-Memcopy launched...finished
-Complete interrupt...success
-MEMCOPY SUCCESS
-```
-
-## Add an external master/slave or peripheral
-
-1. Master(s): use the obi_pkg (import obi_pkg::\*;) to create your master_req output port (obi_req_t) and master_resp input port (obi_resp_t). Adjust the EXT_XBAR_NMASTER parameter accordingly.
-
-2. Slave(s): similar to adding a master but you have a slave_req input port (obi_req_t) and slave_resp output port (obi_resp_t). Remember to connect external masters with external slaves through an external bus. The same bus can be used to connect multiple external slaves to the internal `core_v_mini_mcu` masters.
-
-3. Peripheral slave(s): use the reg_pkg (import obi_pkg::\*;) to create your slave_periph_req input port (reg_req_t) and slave_resp output port (reg_rsp_t). If multiple peripheral slaves are used, add a decoding stage for addresses dispatching.
-
-To create and maintain a peripheral unit efficiently, use the `reggen` tool:
-
-1. Define the registers of your peripheral in a `.hjson` file (read the documentation [here](https://docs.opentitan.org/doc/rm/register_tool/)).
-
-2. Launch the `regtool.py` script to generate SystemVerilog RTL code and a C header file.
-
-For example, launching the script [`memcopy_periph_gen.sh`](./../../../hw/ip_examples/memcopy_periph/memcopy_periph_gen.sh) generates 2 SystemVerilog files and one C header file:
-
-1. `memcopy_periph_reg_top.sv`: the register file module. It can be directly instantiated inside your peripheral RTL code (e.g., [`memcopy_periph.sv`](./../../../hw/ip_examples/memcopy_periph/rtl/memcopy_periph.sv)) and connected to the peripheral device controller(s).
-2. `memcopy_periph_reg_pkg.sv`: SystemVerilog package containing the definitions used in the SystemVerilog module above.
-3. `memcopy_periph_regs.h`: C/C++ header file defining the address offset of the peripheral configuration registers. Take a look at the C code [here](./../../../sw/applications/example_external_peripheral/memcopy_periph.c) for a usage example.
-
-## External Interrupts
-
-X-HEEP includes several empty external interrupts slots that can be assigned both in HW and SW.
-
-Firstly, connect your external device's interrupt to one of the slots of the `external_interrupt_vector` of X-HEEP:
-
-```systemverilog
-
-logic [core_v_mini_mcu_pkg::NEXT_INT-1:0] ext_intr_vector;
-
-always_comb begin
-for (int i = 0; i < core_v_mini_mcu_pkg::NEXT_INT; i++) begin
-    ext_intr_vector[i] = 1'b0;    // All interrupt lines set to zero by default
-end
-ext_intr_vector[0] = my_device_int;  // Re-assign the interrupt lines used here
-end
-
-x_heep_system #(
-    . . .
-) x_heep_system_i (
-    .intr_vector_ext_i(ext_intr_vector),
-    . . .
-)
-
-```
-
-Then, when initializing the PLIC system in software, do not forget to assign the corresponding interrupt ID to your custom handler.
-
-```C
-#define MY_DEVICE_INTR EXT_INTR_0
-
-void handler_irq_my_device(uint32_t id) {
-    my_device_intr_flag = 1;
-    // Do whatever you need here
-}
-
-void main() {
-    plic_Init(); // Init the PLIC, this will clear all external interrupts assigned previously.
-    plic_irq_set_priority(MY_DEVICE_INTR, 1); // Set the priority of the external device's interrupt.
-    plic_irq_set_enabled(MY_DEVICE_INTR, kPlicToggleEnabled); // Enable the external device's interrupt.
-    plic_assign_external_irq_handler( MY_DEVICE_INTR, (void *) &handler_irq_my_device); // Assign a handler taht will be called when this interrupt is triggered.
-
-    // Enable global interrupt for machine-level interrupts
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    // Set mie.MEIE bit to one to enable machine-level external interrupts
-    const uint32_t mask = 1 << 11;//IRQ_EXT_ENABLE_OFFSET;
-    CSR_SET_BITS(CSR_REG_MIE, mask);
-
-    . . .
-}
-```
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/GettingStarted.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/GettingStarted.md
index e5b877dd..4b7b6685 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/GettingStarted.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/GettingStarted.md
@@ -1,6 +1,34 @@
-# get started
+# Get started
 
-## 1. OS requirements
+## Docker setup
+
+A docker image containing all the required software dependancies is available on [github-packages](https://github.com/orgs/esl-epfl/packages/container/package/x-heep-toolchain).
+
+It is only required to install docker and pull the image.
+
+```bash
+docker pull ghcr.io/esl-epfl/x-heep-toolchain:latest
+```
+
+Assuming that X-HEEP has been cloned to `X-HEEP-DIR=\absolute\path\to\x-HEEP\folder`, it is possible to directly run the docker mounting `X-HEEP-DIR` to the path `\workspace\x-heep` in the docker.
+
+```bash
+docker run -it -v ${X-HEEP-DIR}:/workspace/x-heep ghcr.io/esl-epfl/x-heep-toolchain
+```
+
+:warning: Take care to indicate the absolute path to the local clone of X-HEEP, otherwise docker will not be able to properly mount the local folder in the container.
+
+All the command listed in the README can be execute in the docker container, except for:
+
+- Simulation with Questasim and VCS, synthesis with Design Compiler (licenses are required to use these tools, so they are not installed in the container)
+
+- OpenRoad flow is not installed in the container, so it is not possible to run the related make commands
+
+- Synthesis with Vivado could be possible, but currently is untested
+
+## Manual setup
+
+### 1. OS requirements
 
 To use `X-HEEP`, first make sure you have the following apt packages, or install them as:
 
@@ -10,16 +38,14 @@ sudo apt install lcov libelf1 libelf-dev libftdi1-2 libftdi1-dev libncurses5 lib
 
 In general, have a look at the [Install required software](https://opentitan.org/guides/getting_started/index.html) section of the OpenTitan documentation.
 
-It has been tested only on `Ubuntu 20`, and we know it does NOT WORK on `Ubuntu 22`.
-
-## 2. Python
+### 2. Python
 
 
 We rely on either (a) `miniconda`, or (b) `virtual environment` enviroment.
 
 Choose between `2.a` or `2.b` to setup your enviroment.
 
-### 2.a Miniconda
+#### 2.a Miniconda
 
 Install [Miniconda](https://docs.conda.io/en/latest/miniconda.html#linux-installers) python 3.8 version as described in the link,
 and create the Conda enviroment:
@@ -35,7 +61,7 @@ conda activate core-v-mini-mcu
 ```
 
 
-### 2.b Virtual Environment
+#### 2.b Virtual Environment
 
 Install the python virtual environment just as:
 
@@ -49,7 +75,7 @@ You need to do it only the first time, then just activate the environment everyt
 source .venv/bin/activate
 ```
 
-## 3. Install the RISC-V Compiler:
+### 3. Install the RISC-V Compiler:
 
 ```
 git clone --branch 2022.01.17 --recursive https://github.com/riscv/riscv-gnu-toolchain
@@ -75,7 +101,7 @@ cmake -G "Unix Makefiles" -DLLVM_ENABLE_PROJECTS=clang -DCMAKE_BUILD_TYPE=Releas
 cmake --build . --target install
 ```
 
-## 4. Install Verilator:
+### 4. Install Verilator:
 
 ```
 export VERILATOR_VERSION=4.210
@@ -104,18 +130,18 @@ sudo apt install libcanberra-gtk-module libcanberra-gtk3-module
 sudo apt-get install -y gtkwave
 ```
 
-## Files are formatted with Verible
+### Files are formatted with Verible
 
 We use version v0.0-1824-ga3b5bedf
 
-See: [Install Verible](https://opentitan.org/guides/getting_started/index.html#step-6a-install-verible-optional)
+See: [Install Verible](https://opentitan.org/guides/getting_started/index.html#step-7a-install-verible-optional)
 
 To format your RTL code type:
 
 ```
 make verible
 ```
-## Compilation Flow and Package Manager
+### Compilation Flow and Package Manager
 
 We use [FuseSoC](https://github.com/olofk/fusesoc) for all the tools we use.
 
diff --git a/hw/vendor/esl_epfl_x_heep/IDEs.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/IDEs.md
similarity index 92%
rename from hw/vendor/esl_epfl_x_heep/IDEs.md
rename to hw/vendor/esl_epfl_x_heep/docs/source/How_to/IDEs.md
index e1fce194..ee932dc3 100644
--- a/hw/vendor/esl_epfl_x_heep/IDEs.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/IDEs.md
@@ -1,14 +1,14 @@
+# Set up an IDE
 
 For FW development, `X-HEEP` can be used together with different Integrated Development Environments (IDEs) flavours. Up to now, full support is just provided by [Segger Embedded Studio (SES)](https://www.segger.com/products/development-tools/embedded-studio/editions/risc-v/). This readme guides you through all the needed steps to get SES working and debugging when prototyping `X-HEEP` into the pynq-z2 board.
 
-# Prerequisite
 
-## 1. SES installation. 
+## SES installation.
 The platform was only tested under Linux and version 7.32 of the Embedded Studio for RISC-V. Please, go to the Segger [download center](https://www.segger.com/downloads/embedded-studio/) to get that version. It is assumed that you have already installed the RISC-V compiler and openOCD. If the latter is not true, check the main [Readme](https://github.com/esl-epfl/x-heep) please.
 
-# Configuration
+## Configuration
 
-After installing SES, you need to indicate to Segger your Toolchain directory (RISC-V Compiler) as well as your openOCD installation folder. Those need to be specified into `xheep.emProject` file. 
+After installing SES, you need to indicate to Segger your Toolchain directory (RISC-V Compiler) as well as your openOCD installation folder. Those need to be specified into `xheep.emProject` file.
 
 For the RISC-V Compiler path, **line 71**:
 ```
@@ -22,23 +22,23 @@ gdb_server_command_line="/home/< user >/tools/openocd/bin/openocd -f &quot;$(Pro
 ```
 Please, substitute that path to your current path where openOCD was installed. Do not forget to target the `openocd` file inside the `bin` installation folder of openocd.
 
-# Building
+## Building
 
 Once the paths are set properly, you can open `xheep.emProject` with SES. That will launch SES with one solution already configured, `xheep_ses`, and one project into that solution `helloworld`. Note that this project has already everything configured to run the `helloworld` application of the main repo, i.e. all the source files are linked to the project as well as the `c user include directories` already set up. Moreover, this project is configured to be running (compile, linking, and debug) by using the on-chip linker `sw/linker/link.ld`. If you want to change any of these options, you will need to change the options of the project or the options of the solution. Note that the project is currently set-up to be working on the `Debug_External` configuration. Please, do not move to other configuration when building and/or debugging. Finally, to build the whole project just press `F7` or `Build > Build helloworld`.
 
 The output should be like this:
 
-<p align="left"><img src="ides/img/build_screenshot.png" width="450"></p>
+<p align="left"><img src="../_static/ides/build_screenshot.png" width="600"></p>
 
 Note that on the right part, you have the memory usage based on the linker we have configured. If you do not see this, you can activate that view in `View > Memory Usage`.
 
-# Debugging
+## Debugging
 
-Finally, after building (compile and linking), you can directly start debugging by pressing `F5` or also `Target > Connect GDB Server` and `Debug > Go`. You also have the possibility to activate the terminal to see directly into the SES window the printing characters. 
+Finally, after building (compile and linking), you can directly start debugging by pressing `F5` or also `Target > Connect GDB Server` and `Debug > Go`. You also have the possibility to activate the terminal to see directly into the SES window the printing characters.
 
 The output should be something like this:
 
-<p align="left"><img src="ides/img/debug_screenshot.png" width="450"></p>
+<p align="left"><img src="../_static/ides/debug_screenshot.png" width="600"></p>
 
 Note that when debugging and setting breakpoints, please, go one-by-one (one breakpoint at a time). Several breakpoints support will be supported in the following releases.
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ImplementASIC.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ImplementASIC.md
index bacb7050..2ddf20c8 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ImplementASIC.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ImplementASIC.md
@@ -1,4 +1,4 @@
-# implement on ASIC
+# Implement on ASIC
 
 This project can be implemented using standard cells based ASIC flow.
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/IntegratePeripheral.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/IntegratePeripheral.md
index ae8b3b3f..f39bdbd1 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/IntegratePeripheral.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/IntegratePeripheral.md
@@ -206,7 +206,7 @@ module <peripheral> #(
 
 b. The corresponding package must be imported:
 
-```systemverilog
+```
 import <peripheral>_reg_pkg::*;
 ```
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md
index 7ed89d24..efbe78a9 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/ProgramFlash.md
@@ -1,4 +1,4 @@
-# program the FLASH on the EPFL Programmer
+# Program the FLASH on the EPFL Programmer
 
 Install the required linux tools:
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/RunOnFPGA.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/RunOnFPGA.md
new file mode 100644
index 00000000..79790a91
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/RunOnFPGA.md
@@ -0,0 +1,81 @@
+# Run on FPGA
+
+This project offers two different X-HEEP implementetions on Xilinx FPGAs, called Standalone and FEMU.
+
+## Standalone
+
+### Set-up
+In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the FPGA, and its input/output are connected to the available headers on the FPGA board.
+
+Two FPGA boards are supported: the Xilinx Pynq-z2 and Nexys-A7-100t.
+
+1. Make sure you have the FPGA board files installed in your Vivado.
+> For example, for the Pynq-Z2 board, use the documentation provided at the following [link](https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html) to download and install them.
+
+2. Make sure you set up the Vivado environments by running
+   ```
+   source <vivado-installation-path>/settings64.sh
+   ```
+   > We recommend adding this command to your `.bashrc`
+
+3. Install the Xilinx cable drivers.
+* Follow the [instructions for Linux](https://docs.amd.com/api/khub/documents/6EIhov6ruoilhq8zq7bXBA/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=4.3.26#G4.262534)
+* Restart your PC
+
+### Running
+
+To build and program the bitstream for your FPGA with vivado, type:
+
+```
+make vivado-fpga FPGA_BOARD=pynq-z2
+```
+
+or
+
+```
+make vivado-fpga FPGA_BOARD=nexys-a7-100t
+```
+
+or add the flag `use_bscane_xilinx` to use the native Xilinx scanchain:
+
+```
+make vivado-fpga FPGA_BOARD=pynq-z2 FUSESOC_FLAGS=--flag=use_bscane_xilinx
+```
+
+To program the bitstream, open Vivado,
+
+```
+open --> Hardware Manager --> Open Target --> Autoconnect --> Program Device
+```
+
+and choose the file `openhwgroup.org_systems_core-v-mini-mcu_0.bit`.
+
+Or simply type:
+
+```
+bash vivado-fpga-pgm FPGA_BOARD=pynq-z2
+```
+
+or
+
+```
+make vivado-fpga-pgm FPGA_BOARD=nexys-a7-100t
+```
+
+To run SW, follow the [Debug](./Debug.md) guide to load the binaries with the HS2 cable over JTAG,
+or follow the [ExecuteFromFlash](./ExecuteFromFlash.md) guide if you have a FLASH attached to the FPGA.
+
+Do not forget that the `pynq-z2` board requires you to have the ethernet cable attached to the board while running.
+
+For example, if you want to run your application using flash_exec, do as follow:
+compile your application, e.g. `make app PROJECT=example_matfadd TARGET=pynq-z2 ARCH=rv32imfc LINKER=flash_exec`
+and then follow the [ExecuteFromFlash](./ExecuteFromFlash.md) to program the flash and set the boot buttons on the FPGA correctly.
+To look at the output of your printf, run in another terminal:
+`picocom -b 9600 -r -l --imap lfcrlf /dev/ttyUSB2`
+Please be sure to use the right `ttyUSB` number (you can discover it with `dmesg --time-format iso | grep FTDI` for example).
+
+## FPGA EMUlation Platform (FEMU)
+
+In this version, the X-HEEP architecture is implemented on the programmable logic (PL) side of the Xilinx Zynq-7020 chip on the Pynq-Z2 board and Linux is run on the ARM-based processing system (PS) side of the same chip.
+
+NOTE: This platform is not part of this repository, but you can access it with the following link: [FEMU](https://github.com/esl-epfl/x-heep-femu-sdk).
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Simulate.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Simulate.md
new file mode 100644
index 00000000..6147648c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/Simulate.md
@@ -0,0 +1,160 @@
+# Simulate
+
+This project supports simulation with Verilator, Synopsys VCS, Siemens Questasim and Cadence Xcelium.
+It relies on `fusesoc` to handle multiple EDA tools and parameters.
+For example, if you want to set the `FPU` and `COREV_PULP` parameters of the `cv32e40p` CPU,
+you need to add next to your compilation command `FUSESOC_PARAM="--COREV_PULP=1 --FPU=1"`
+Below the different EDA examples commands.
+
+## Compiling for Verilator
+
+To simulate your application with Verilator, first compile the HDL:
+
+```
+make verilator-sim
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
+```
+
+and type to run your compiled software:
+
+```
+./Vtestharness +firmware=../../../sw/build/main.hex
+```
+
+or to execute all these three steps type:
+
+```
+make run-helloworld
+```
+
+## Compiling for VCS
+
+To simulate your application with VCS, first compile the HDL:
+
+```
+make vcs-sim
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-vcs
+```
+
+and type to run your compiled software:
+
+```
+./openhwgroup.org_systems_core-v-mini-mcu_0 +firmware=../../../sw/build/main.hex
+```
+
+Waveforms can be viewed with Verdi. Make sure you have the env variable `VERDI_HOME` set to your Verdi install folder, then run your compiled software as above, but with the `-gui` flag:
+
+```
+./openhwgroup.org_systems_core-v-mini-mcu_0 +firmware=../../../sw/build/main.hex -gui
+```
+
+An Analog / Mixed-Signal simulation of X-HEEP, combining both the RTL system verilog files for the digital part and a SPICE file connected through a `control.init` file for the analog / mixed-signal part, can be ran by typing
+
+```
+make vcs-ams-sim
+```
+
+then going to the target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-vcs
+```
+
+and running the same executable as for the digital simulation. Note that with Verdi you can view both the digital and the analog waveforms.
+
+Additional instructions on how to run an analog / mixed-signal simulation of X-HEEP can be found [here](./AnalogMixedSignal.md). To try out the simulation, we provide an example SPICE netlist of an simple 1-bit ADC created by us and exported from [xschem](https://xschem.sourceforge.io/stefan/index.html) and which uses the PTM 65nm bulk CMOS model from [https://ptm.asu.edu](https://ptm.asu.edu/).
+
+## Compiling for Questasim
+
+To simulate your application with Questasim, first set the env variable `MODEL_TECH` to your Questasim bin folder, then compile the HDL:
+
+```
+make questasim-sim
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim/
+```
+
+and type to run your compiled software:
+
+```
+make run PLUSARGS="c firmware=../../../sw/build/main.hex"
+```
+
+You can also use vopt for HDL optimized compilation:
+
+```
+make questasim-sim-opt
+```
+
+then go to
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim_opt-modelsim/
+```
+and
+
+```
+make run RUN_OPT=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
+```
+
+You can also compile with the UPF power domain description as:
+
+```
+make questasim-sim-opt-upf FUSESOC_PARAM="--USE_UPF"
+```
+
+and then execute software as:
+
+```
+make run RUN_OPT=1 RUN_UPF=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
+```
+
+Questasim version must be >= Questasim 2020.4
+
+## Compiling for Xcelium
+
+To simulate your application with Xcelium, first compile the HDL:
+
+```
+make xcelium-sim
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-xcelium/
+```
+
+and type to run your compiled software:
+
+```
+make run PLUSARGS="c firmware=../../../sw/build/main.hex"
+```
+
+## UART DPI
+
+To simulate the UART, we use the LowRISC OpenTitan [UART DPI](https://github.com/lowRISC/opentitan/tree/master/hw/dv/dpi/uartdpi).
+Read how to interact with it in the Section "Running Software on a Verilator Simulation with Bazel" [here](https://opentitan.org/guides/getting_started/setup_verilator.html#running-software-on-a-verilator-simulation-with-bazel).
+The output of the UART DPI module is printed in the `uart0.log` file in the simulation folder.
+
+For example, to see the "hello world!" output of the Verilator simulation:
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator
+./Vtestharness +firmware=../../../sw/build/main.hex
+cat uart0.log
+```
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/UpdateDocumentation.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/UpdateDocumentation.md
new file mode 100644
index 00000000..c27a8776
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/UpdateDocumentation.md
@@ -0,0 +1,27 @@
+# Update the documentation
+
+All documentation is found in the `/docs` directory.
+
+1. If you need to create a new entry, add the new document in markdown (`.md` extension) to the corresponding folder. Otherwise, just edit the corresponding file.
+
+> Make sure the document has one single `# header`, otherwise they will be considered different documents.
+
+2. If a new folder is added, add it to the `toctree` inside `docs/source/index.rst` (as the `peripherals` folder is)
+3. Commit and push
+
+## Refresh the web documentation
+
+After each change to the documentation, once the branch is merged into the main branch of X-HEEP, anyone must do the following:
+
+1. Open a terminal in the `docs` folder and make sure the conda environment is activated.
+2. If it is your first time updating the web docs, run:
+```bash
+pip install -r requirements.txt
+```
+3. Run
+```bash
+make clean html
+```
+4. Wait a few minutes and enjoy your brand new documentation in [Read the Docs](https://x-heep.readthedocs.io/en/latest/).
+
+Thank you for helping keep X-HEEP accurately and extensively documented!
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md
index ad8805b1..59c1b1e9 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md
@@ -10,6 +10,7 @@ Here you can find a list of `X-HEEP` based open-source examples. If you want to
 
 * [CGRA-X-HEEP](https://github.com/esl-epfl/cgra_x_heep): A CGRA loosely coupled with X-HEEP.
 * [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40x.
+* [KALIPSO](https://github.com/vlsi-lab/ntt_intt_kyber) and [KRONOS](https://github.com/vlsi-lab/keccak_integration/tree/keccak_xheep): Loosely-coupled, post-quantum cryptography accelerators for NTT/INTT and Keccak hash function integrated into X-HEEP.
 
 
 In addition, the `X-HEEP` testbench has been extended with a `DMA`, dummy `PERIPHERALs` (including the `FLASH`), and a CORE-V-XIF compatible co-processor
@@ -304,7 +305,7 @@ To do so, it MUST include the `external.mk` AFTER all your custom rules.
 <details>
     <summary>Example of BASE/Makefile</summary>
 
-```
+```Makefile
 MAKE     = make
 .PHONY: test
 test:
@@ -326,12 +327,69 @@ include $(XHEEP_MAKE)
 * The `app` rule will perform actions before calling `X-HEEP` Makefile's `app` rule. In this case, the project and where the source files are to be extracted from is being specified. The `SOURCE=.` argument will set `X-HEEP`'s own `sw/` folder as the directory from which to fetch source files. This is an example of building inner sources from an external directory.
 * The `verilator-sim` rule will override the `X-HEEP` Makefile's one.
 * Any other target will be passed straight to `X-HEEP`'s Makefile. For example
-```
+```sh
 make mcu-gen CPU=cv32e40x
 ```
 </details>
 
 
+### Excluding files from compilation
+If you have files that need to be excluded from the gcc compilation flow, you can add them to a directory containing the keyword `exclude`, and/or rename the file to include the keyword `exclude`. 
+In the following example, the files marked with ✅ will be compiled, and the ones marked with ❌ will not.  
+
+    BASE
+    ├── sw
+    │   ├── applications
+    │   │   └── your_app
+    │   │       ├── ✅ main.c      
+    │   │       ├── ✅ your_app.c
+    │   │       ├──    your_app.h
+    │   │       ├── ❌ my_kernel_exclude.c
+    │   │       ├──    my_kernel.h
+    │   │       └── exclude_files
+    │   │           └── ❌ kernel_asm.S
+
+
+
+### Makefile help
+If you want that the commands `make` or `make help` show the help for your external Makefile, add the following lines before the first `include` directive or target.
+
+<details>
+    <summary>Addition to print the target's help</summary>
+
+```Makefile
+# HEEP_DIR might already be defined, you may want to move it to the top
+export HEEP_DIR = hw/vendor/esl_epfl_x_heep/
+
+# Get the path of this Makefile to pass to the Makefile help generator
+MKFILE_PATH = $(shell dirname "$(realpath $(firstword $(MAKEFILE_LIST)))")
+export FILE_FOR_HELP = $(MKFILE_PATH)/Makefile
+
+
+## Call the help generator. Calling simply
+## $ make
+## or
+## $ make help
+## Will print the help of this project.
+## With the parameter WHICH you can select to print
+## either the help of X-HEEP (WHICH=xheep)
+## or both this project's and X-HEEP's (WHICH=all)
+help:
+ifndef WHICH
+	${HEEP_DIR}/util/MakefileHelp
+else ifeq ($(filter $(WHICH),xheep x-heep),)
+	${HEEP_DIR}/util/MakefileHelp
+	$(MAKE) -C $(HEEP_DIR) help
+else
+	$(MAKE) -C $(HEEP_DIR) help
+endif
+```
+
+</details>
+
+> Remeber to add double hashes `##` on any comment you want printed on the help.
+> Use `## @section SectionName` to divide the documentation in sections
+
 ### Different use cases
 If you plan to vendorize `X-HEEP` in a different directory than the one proposed, just update in your `BASE/Makefile`:
 ```
@@ -343,3 +401,10 @@ If you plan to store source files in a different location that the one proposed,
 make app PROJECT=your_app SOURCE=<path_to_your_sw_relative_to_x_heep_sw>
 ```
 Consider that inside this `sw` folder the same structure than the one proposed is required.
+
+
+## Inter-process communication using Verilator's DPI
+
+The following [repository](https://github.com/specs-feup/x-heep) uses X-HEEP and the Verilator simulator to model a CPU-CGRA hybrid system. This architecture simulates the CPU integrated into the X-HEEP system, and an external Java process simulates the accelerator. Both components require a communication channel to exchange instructions and data. Using the existing infrastructure to to interact with an external OS process is not feasible at first sight, given that the X-HEEP ecosystem's pipeline encapsulates most of the simulation build and execution, with all modules supplied directly to Verilator. 
+
+To circumvent this issue, this project uses [Direct Programming Interface (DPI)](https://verilator.org/guide/latest/connecting.html) calls (defined in `hw/ip_examples/cgraitf/cgraitfdpi.c`) to establish a connection and communicate with an external process through a Unix Domain Socket. This behavior mirrors the UART module (used as the skeleton code) that connects and outputs _printf_ information to the pseudo-terminal. These calls are embedded in a mock CGRA peripheral/interface, located in `hw/ip_examples/cgraitf/cgraitf.sv`. The module overrides reads and writes to the specified peripheral address, with the proper socket-based mechanism (_send_ or _recv_). The _simple_accelerator_ module could also be similarly customized to perform the same operations, using X-HEEP's  interfaces and memory access protocols. A given user program executed in the CPU (such as `sw/applications/cgra_itf/main.c`) must then select assignments to or from the address to trigger the appropriate action.
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md
index e955df91..6b57642f 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md
@@ -1,327 +1,376 @@
+
 # DMA
 The **Direct Memory Access (DMA)** peripheral allows data transfers with reduced CPU interaction.
 It can perform *transactions* of data between peripherals and memory, or memory-to-memory (as a `memcpy` would).
 The CPU is required to configure the transaction, but once launched it is free to go to sleep, process the incoming data or do anything else.
-
+  
 The DMA **Hardware Abstraction Layer (HAL)** facilitates the configuration of transactions from the users application. Furthermore, it adds an additional layer of safety checks to reduce the risk of faulty memory accesses, data override or infinite loops.
-
-
+  
+  
 ## Previous Definitions
 The implementation of this software layer introduced some concepts that need to be understood in order to make proper use of the DMA's functionalities .
-
+  
 ### Transaction
-A transaction is an operation to be performed by the DMA. It implies copying bytes from a source pointer into a destination pointer. The transaction configuration can be loaded into the DMA registers once it has been cross-checked and it only starts when the size of the transaction is written in its corresponding register. The transaction is finished once the DMA has sent all its bytes (which not necessarily means they have been received by the final destination).
+A transaction is an operation to be performed by the DMA. It implies copying bytes from a source pointer into a destination pointer. The transaction configuration can be loaded into the DMA registers once it has been cross-checked and it only starts when the size along the *first dimension* of the transaction is written in its corresponding register. The transaction is finished once the DMA has sent all its bytes (which not necessarily means they have been received by the final destination).
 Transactions cannot be stopped once they were launched.
 While a transaction is running, new transactions can be validated, but not launched or loaded into the DMA.
 Transactions can be re-launched automatically in `circular mode`.
 Once the transaction has finished, a status bit is changed (that can be monitored through polling) and a fast interrupt is triggered.
-
+  
 ### Source and destination
 Sources and destinations are the two pointers that will exchange data. Bytes will be copied from the source and into the destination address.
-
+  
 ### Data type
 The DMA allows transactions in chunks of 1, 2 or 4 Bytes (`Byte`, `Half-Word` and `Word` respectively). The size in bytes of the chosen data type is called _data unit_ (usually abbreviated as `du`).
 For example, 16 bytes can be 16 data units if the data type is `Byte`, but 8 data units if the data type is `Half Word`.
-
+Source and destination can have different data types, if the destination type is wider than the source type, data can be sign extended.
+### Sign extension
+If specified (setting the bit in the corresponding register) and if the destination data type is wider than the source type, sign of the source data is extended to fill the size of the destination data type.
+
+### Dimensionality
+The DMA can perform both **1D transactions** and **2D transactions**. 
+When set to perform 1D transactions, the DMA copies the defined number of elements from the source pointer to the destination pointer using a 1D increment.
+When set to perform 2D transactions, the DMA copies data from the source pointer to the destination pointer using both a 1D increment and an additional 2D increment. 
+In this way, two-dimensional data manipulations (e.g. matrix manipulations) can be performed in a single DMA transaction, greatly reducing the CPU time.
 ### Increment
-In the case that source and/or destination data are not to be consecutively read/written, a certain increment can be defined.
+In the 1D configuration, if source and/or destination data are not to be consecutively read/written, a certain increment can be defined.
 For instance, if you have an array of 4-bytes-words, but only want to copy the first 2 bytes of each word, you could define the transaction with a data type of half word, an increment of 2 data units in the source, and 1 data unit in the destination. This way, after each read operation the DMA will increment the read pointer in 4 bytes (2 data units), but the write pointer by only 2 bytes.
+In the 2D configuration, a second increment has to be set in order to enable the 2D transaction.
+In the context of matrix manipulation, the 2D increment is the number of words that the DMA has to "skip" to move to the next row.
+For instance, let's examine the extraction of a continuous 2x2 matrix from a 4x4 matrix, stored in a continuous 2x2 matrix.
+```
+| 3 | 5 | 7 | 9 |    
+| 2 | 4 | 6 | 8 | 	->  | 3 | 5 |
+| 1 | 3 | 5 | 7 | 	    | 2 | 4 |
+| 0 | 2 | 4 | 6 |
+```
+The total number of elements copied from the source is 4 elements. The increments are:
+ - For the source:
+	- 1D increment set to 1 word 
+	- 2D increment set to 3 words
+ - For the destination:
+	- 1D increment set to 1 word
+	- 2D increment set to 1 word
+By exploiting the 2D increment, it's possible to implement a non-continuous read and/or write by computing the correct 2D increment. Detailed formulas for the computation of 2D increments are reported in the *example_dma_2d* folder.
+  
+### Zero padding
+
+The DMA is capable of performing zero padding on the extracted data, both in 1D and 2D transactions.
+This is done by by setting four padding parameters:
+- **T**op				    
+- **B**ottom				     				
+- **L**eft				
+- **R**ight		
+
+e.g.
+
+```		
+| T | T | T | T | T |	
+| L | x | x | x | R |	
+| L | x | x | x | R |	
+| B | B | B | B | B |	
+```
+It's important to highlight the fact that the padding is performed (conceptually) only *after* the matrix has been extracted.
+Let's examine the previous 2x2 extraction example, adding a left and top padding of 1 word:
+
+```
+| 3 | 5 | 7 | 9 |      | 0 | 0 | 0 |
+| 2 | 4 | 6 | 8 |  ->  | 0 | 3 | 5 |
+| 1 | 3 | 5 | 7 |      | 0 | 2 | 4 |
+| 0 | 2 | 4 | 6 |
+```
 
 ### Alignment
 When doing transactions with bytes, the DMA can read/write from any pointer. However, if the data type is larger, words should be aligned so the DMA can perform a read/write operation and affect only the chosen bytes. If a word or half-word's pointer is not a multiple of 4 or 2 (respectively), the pointer is _misaligned_. In some cases the DMA HAL can overcome this problem reducing the data type (which will reflect on an efficiency loss).
-
+  
 ### Environment
 An environment is a region of memory that can optionally be defined by the user to let the HAL know that it is allowed to read/write on that region. It is useful to make sure the DMA will not affect reserved memory regions.
 Right now, read and write permissions are not supported by environments, meaning that if it is defined, the DMA will be able to read AND write on it.
-
+  
 ### Triggers and Slots
 If the source or destination pointer is a peripheral, there are lines connecting the peripheral and the DMA that can be used to control the data flow (they behave as _triggers_). These lines are connected to _slots_ on the DMA and they allow/stop the DMA from reading/writing data.
-
+  
 ### Target
 A target is either a region of memory or a peripheral to which the DMA will be able to read/write. When targets are pointing to memory, they can be assigned an environment to make sure that they will comply with memory restrictions.
 Targets include a pointer (a point in the memory, or the Rx/Tx buffer in case of peripherals), a size to be copied (if its going to be used as a source), a data type and an increment.
-
+  
 ### Configuration flags
 During the creation or configuration of environments, targets or transactions, there could be inconsistencies or threatening situations (like writing outside the boundaries of a defined region). To provide the user with information about this potentially harmful situations, configuration flags are set while creating each of these entities. They can be unmasked and checked.
 In some cases, when the threat is too risky, a _crucial error_ might be raised and the operation of the configuration is halted.
 If senseless configurations are input to functions, assertions may halt the whole program. This is reserved for extreme situations that mean the program was not properly coded (e.g. a slot value is provided and is not among the available ones).
-
+  
 ### Transaction modes
 There are three different transaction modes:
 **Single Mode:** The default mode, where the DMA will perform the copy from the source target to the destination, and trigger an interrupt once done.
 **Circular mode:** To take full advantage of the speed and transparency of the DMA, a _circular_ mode was implemented. When selected, the DMA will relaunch the exactly same transaction upon finishing. This cycle only stops if by the end of a transaction the _transaction mode_ was changed to _single_. The CPU receives a fast interrupt on every transaction finished.
-**Address Mode:** Instead of using the destination pointer and increment to decide where to copy information, an _address list_ must be provided, containing addresses for each data unit being copied. It is only carried out in _single_ mode.
-
+**Address Mode:** Instead of using the destination pointer and increment to decide where to copy information, an _address list_ must be provided, containing addresses for each data unit being copied. It is only carried out in _single_ mode. 
+In this mode it's possible to perform only 1D transactions.
+  
 ### Windows
 In order to process information as it arrives, the application can define a _window size_ (smaller than the _transaction size_. Every time the DMA has finished sending that given amount of information will trigger an interrupt through the PLIC.
 > :warning: If the window size is a multiple of the transaction size, upon finishing the transaction there will be first an interrupt for the whole transaction (through the FIC), and then an interrupt for the window (through the PLIC, which is slower).
-
-
+  
+  
 ### Checks and Validations
 The DMA HAL's interface functions perform two types of checks:
-* **Sanity checks**: Make sure that each individual value passed as an argument is reasonable and belongs to the proper domain. This errors will raise an _assertion_ and, depending on how assertions are managed in the application, may result in the program crashing.
-* **Integrity checks**: Arguments are cross-checked to make sure that they abide by the rules of the DMA. If configurations are incompatible, contradictory, or a risk for the programs integrity, warnings are raised through the _configuration flags_. In some special cases, a _critical error_ can be raised, which blocks the deployment of the configuration into the DMA registers.
-
+*  **Sanity checks**: Make sure that each individual value passed as an argument is reasonable and belongs to the proper domain. This errors will raise an _assertion_ and, depending on how assertions are managed in the application, may result in the program crashing.
+*  **Integrity checks**: Arguments are cross-checked to make sure that they abide by the rules of the DMA. If configurations are incompatible, contradictory, or a risk for the programs integrity, warnings are raised through the _configuration flags_. In some special cases, a _critical error_ can be raised, which blocks the deployment of the configuration into the DMA registers.
+  
 > :warning: Integrity checks can be disabled to speed up configuration time. Do this only if you have previously checked the configuration and are sure it will not cause any trouble.
-
+  
 Checks and validations are performed during the transactions creation, loading and launching.
-
+  
 A transaction is validated if it went through the creation-checks without raising critical errors.
-
+  
 ### End events
 The DMA considers a certain amount of bytes to have been transferred once it has sent them. It does not wait for a confirmation from the recipient. When a transaction/window is finished the DMA performs a series of event. These may include:
 * Changing its status register.
 * Raising a _transaction done_ interrupt.
 * Raising a _window done_ interrupt.
-
+  
 The DMA HAL can follow up on these changes or let the application be in charge. For this purpose, three different types of _end events_ are defined:
-* **Polling**: The HAL will disable interrupts from the DMA. The application will need to frequently query the status of the DMA to know when a transaction has finished.
-* **Interrupt**: Interrupts will be enabled. The _window done interrupt_ is enabled if a window size is provided.
-* **Interrupt wait**: The DMA HAL will block the program in a `wfi()` state until the _transaction done interrupt_ is triggered.
-
-
+*  **Polling**: The HAL will disable interrupts from the DMA. The application will need to frequently query the status of the DMA to know when a transaction has finished.
+*  **Interrupt**: Interrupts will be enabled. The _window done interrupt_ is enabled if a window size is provided.
+*  **Interrupt wait**: The DMA HAL will block the program in a `wfi()` state until the _transaction done interrupt_ is triggered.
+  
+  
 ## Operation
 This section will explain the operation of the DMA through the DMA HAL.
 There is a DMA instance inside X-HEEP, but others can be connected outside through the bus (see the `example_external_peripheral` application in `sw/aplications/example_external_peripheral/main.c`). As long as the DMA instance is the same and the registers are memory mapped with the same structure, the DMA HAL can be used.
-
+  
 The DMA HAL adds an extra computational overhead to transactions in order to check the consistency of the transaction configurations. By-passing this layer (and the steps here described) is disadvised. For the efficiency-hungry applications, doing at least one pass with the whole validation process is recommended. The HAL allows to load and launch transactions with minimum overhead afterwards.
-
+  
 The following explanation makes use of Figure 1.
-
+  
 ![DMA HAL-HW + addresses](https://github.com/esl-epfl/x-heep/assets/54960111/3092faa5-c72c-4cd9-a4d4-4c87de63d1c7)
-<p align="center">Figure 1: Example operation of the DMA and its HAL</p>
-
+<p  align="center">Figure 1: Example operation of the DMA and its HAL</p>
+  
 ---
-
-The use of the DMA starts with the application creating a set of targets (<span style="color:red">**a**</span>) . In the figure, the source target is a peripheral connected to an SPI and to the DMA. The address of the reception FIFO (_Rx FIFO_) of this SPI is `0x70` (<span style="color:red">**b**</span>) . The destination target is a region of memory of address `0x16` (<span style="color:red">**c**</span>). It is located inside an environment that spans from `0x12` to `0x35`. Any number of environments and targets can be created, and not used.
-
+  
+The use of the DMA starts with the application creating a set of targets (<span  style="color:red">**a**</span>) . In the figure, the source target is a peripheral connected to an SPI and to the DMA. The address of the reception FIFO (_Rx FIFO_) of this SPI is `0x70` (<span  style="color:red">**b**</span>) . The destination target is a region of memory of address `0x16` (<span  style="color:red">**c**</span>). It is located inside an environment that spans from `0x12` to `0x35`. Any number of environments and targets can be created, and not used.
+  
 Additionally, in the application the transaction is created. The _operation mode_ and _window size_ are selected.
-
-The application calls the validation function of the HAL. If the configurations do not raise a critical flag, it then calls the loading function. By doing so, the desired values are written into their corresponding registers (<span style="color:red">**d**</span>). The only register that is not immediately written is the _transaction size_, as it is the one responsible for launching the transaction when changed from zero to a non-zero value. It is only written once the application calls the launching function (<span style="color:red">**e**</span>).
-
+  
+The application calls the validation function of the HAL. If the configurations do not raise a critical flag, it then calls the loading function. By doing so, the desired values are written into their corresponding registers (<span  style="color:red">**d**</span>). The only register that is not immediately written is the _transaction size_, as it is the one responsible for launching the transaction when changed from zero to a non-zero value. It is only written once the application calls the launching function (<span  style="color:red">**e**</span>).
+  
 Note that there could be some changes between the configuration input in the application and the values written in the registers. For example, a _window size_ of 2 refers to _2 data units_ (i.e. 2 half-words, as such is the data type of the source in Figure 1); however, when writing on the register, this is translated to bytes, so 4 is written instead.
-
-Once launched, the transaction will execute completely (it cannot be stopped). Upon finishing, it will check the _operation mode_ and _transaction size_ registers. If any of both is non-zero, it will relaunch. Note that the selecting _circular mode_ during the configuration loading does not launch the transaction (despite what step (<span style="color:red">**f**</span>) might suggest, which is only illustrative).
-
-
-Once the transaction is launched, the DMA will take care of copying as many data units as were requested from the source target (<span style="color:red">**g**</span>), and pasting them into the destination target (<span style="color:red">**h**</span>). The data width of the transaction is determined by the _data type_ of the source target (<span style="color:red">**i**</span>). However, this might be changed (for a smaller width) in case of misalignment. It is possible to reject changes by the DMA HAL and raise an error in case of misalignments instead.
-
-The selected slot will query the state of a trigger from the peripheral (<span style="color:red">**j**</span>). In case the peripheral's FIFO is empty/full (for reception/transmission respectively), the transaction is paused until the trigger enables it again.
-
+  
+Once launched, the transaction will execute completely (it cannot be stopped). Upon finishing, it will check the _operation mode_ and _transaction size_ registers. If any of both is non-zero, it will relaunch. Note that the selecting _circular mode_ during the configuration loading does not launch the transaction (despite what step (<span  style="color:red">**f**</span>) might suggest, which is only illustrative).
+  
+  
+Once the transaction is launched, the DMA will take care of copying as many data units as were requested from the source target (<span  style="color:red">**g**</span>), and pasting them into the destination target (<span  style="color:red">**h**</span>). The data width of the transaction is determined by the _data type_ of the source target (<span  style="color:red">**i**</span>). However, this might be changed (for a smaller width) in case of misalignment. It is possible to reject changes by the DMA HAL and raise an error in case of misalignments instead.
+  
+The selected slot will query the state of a trigger from the peripheral (<span  style="color:red">**j**</span>). In case the peripheral's FIFO is empty/full (for reception/transmission respectively), the transaction is paused until the trigger enables it again.
+  
 The source and destination increments will determine the amount of steps the pointer should jump after every read and write, respectively. For peripherals it should always be zero (as it should always take the first element of the FIFO).
-
-The DMA will consider a data unit was transferred once it is sent (<span style="color:red">**k**</span>). It does not wait for an acknowledge by the destination target.
-
-The _interrupts_ register controls whether the events triggered by the DMA upon finishing a window or a whole transaction should be propagated as interrupts (<span style="color:red">**l**</span>).
-
-Every time  _window size_ data units have been transferred the window count is incremented and a PLIC interrupt is triggered (if enabled) (<span style="color:red">**m**</span>).
-
-Every time a transaction is finished a FIC interrupt is triggered and the restart condition is evaluated (<span style="color:red">**f**</span>).
-
+  
+The DMA will consider a data unit was transferred once it is sent (<span  style="color:red">**k**</span>). It does not wait for an acknowledge by the destination target.
+  
+The _interrupts_ register controls whether the events triggered by the DMA upon finishing a window or a whole transaction should be propagated as interrupts (<span  style="color:red">**l**</span>).
+  
+Every time _window size_ data units have been transferred the window count is incremented and a PLIC interrupt is triggered (if enabled) (<span  style="color:red">**m**</span>).
+  
+Every time a transaction is finished a FIC interrupt is triggered and the restart condition is evaluated (<span  style="color:red">**f**</span>).
+  
 If the window size is a multiple of the transaction size, upon finishing the transaction there will be first an interrupt for the whole transaction (through the FIC), and then an interrupt for the window (through the PLIC, which is slower).
-
-
-The DMA HAL has weak implementations to handle each interrupt. It is up to the application to do something useful with this. the HAL will only forward the interrupt (<span style="color:red">**n**</span>).
-
+  
+  
+The DMA HAL has weak implementations to handle each interrupt. It is up to the application to do something useful with this. the HAL will only forward the interrupt (<span  style="color:red">**n**</span>).
+  
 > :warning: If the window size is too small (i.e. the time the DMA requires to make the copy is smaller than the time required to attend the interrupt handling), data might be lost. The HAL implements a warning in case the transaction-window size ratio is to small. The warning can be re-configured to an appropriate threshold by overriding a weak implementation. The user should do its own testing and choose this threshold accordingly. The same type of issue might be found on circular mode. The user should be sure it can attend an interrupt before the next one occurs. There is no warning from the HAL in this case.
-
-The same result from this example could have been achieved by setting the transaction mode to _address_. It requires an array of destination addresses (<span style="color:red">**p**</span>) that must be provided as the destination target pointer. Instead of copying information to that pointer, the DMA will read from there and copy the information into the addresses stored in each word (<span style="color:red">**o**</span>).
+  
+The same result from this example could have been achieved by setting the transaction mode to _address_. It requires an array of destination addresses (<span  style="color:red">**p**</span>) that must be provided as the destination target pointer. Instead of copying information to that pointer, the DMA will read from there and copy the information into the addresses stored in each word (<span  style="color:red">**o**</span>).
 This use case is very impractical as it doubles the memory usage. It is intended to be used along In-Memory-Computing architectures and algorithms.
-
+  
 ## Usage
 This section will explain a basic usage of the DMA as a `memcpy`, and a slightly more complex situation involving a peripheral connected via an SPI.
-
+  
 ### Basic application
 This example will provide a simplified code for copying data from one region of memory to another. For a real implementation please refer to the `dma_example` application in `sw/applications/dma_example/main.c`.
-
+  
 The objective of this app would be to copy the content of an array into another.
-
+  
 ---
-
+  
 Start the application by calling
 ```C
 dma_init( NULL );
 ```
-
+  
 This will reset the DMA registers. The `NULL` parameter tells the HAL that the devices internal DMA is to be used.
-
+  
 The most basic implementation requires the creation of **two targets** and a **transaction** relating them both.
-
+  
 A target will include the information of the source or destination pointer and the characteristics of the expected transaction.
-
+  
 Theoretically, there is no required difference between a _source_ and _destination_ target. They will only be differentiated once the transaction is created. Eventually, they could be interchanged from one transaction to the next. In this example they will be given explicit names and will take different arguments for the sake of clarity.
-
+  
 ```C
 static dma_target_t tgt_src = {
-                                .ptr        = copy_buffer,
-                                .inc_du     = 1,
-                                .size_du    = sizeof(copy_buffer),
-                                };
+				.ptr        = copy_buffer,
+				.inc_du     = 1,
+				.size_du    = sizeof(copy_buffer),
+				.type       = DMA_DATA_TYPE_WORD
+				};
 ```
-
+  
 Here, `ptr = copy_buffer` is a `uint32_t` pointer from where the information will be extracted. `inc_du = 1` is telling the DMA that for each word copied, the pointer should be incremented by 1 unit, therefore words will be copied consecutively without gaps.
-
+  
 This configuration is implicitly initializing the rest of the target configurations as zero (as of [C99](https://gcc.gnu.org/onlinedocs/gcc/Designated-Inits.html)). This means that:
 * No environment is set.
 * Data type is set to _word_ (32-bits).
 * The trigger is set to _memory_ (vs. a peripheral).
-
-The destination target can also dispense of a size, as the source size will be used.
-
 ```C
 static dma_target_t tgt_dst = {
                                 .ptr        = copy_buffer,
                                 .inc_du     = 1,
+                                .size_du    = sizeof(copy_buffer),
+                                .type       = DMA_DATA_TYPE_WORD
                                 };
 ```
-
+Both destination and source targets have to contain a data type (they can be different) and size in data units (they should be the same).
 Finally, a transaction is created to relate both targets:
-
+  
 ```C
-static dma_trans_t trans = {
-                            .src        = &tgt_src,
-                            .dst        = &tgt_dst,
-                            };
+static  dma_trans_t trans = {
+				.src = &tgt_src,
+				.dst = &tgt_dst,
+				};
 ```
-
+  
 This will also imply some configurations set to zero:
 * Mode is set to singular (only one transaction will be executed).
 * There will be no window interrupts.
 * The application will have to do polling to know when the transaction has finished.
-
+  
 The transaction can now be created (some extra configurations are computed from the targets), loaded into the DMA and launched.
-
+  
 ```C
 dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
 dma_load_transaction( &trans );
 dma_launch( &trans );
-
+  
 ```
-
+  
 When creating the transaction, the two last parameters are allowing the DMA to perform integrity checks and try some fixes (at the expense of efficiency) if misalignments are found.
-
+  
 As there will be no interrupts set, the application has to check by itself the status of the transaction.
-
+  
 ```C
 while( ! dma_is_ready() ){}
 // The transaction has finished!
 ```
-
-
+  
+  
 ### Complete Application
 The objective of this example is to show various special cases, precautions and considerations that can be taken. For a real example refer to the `spi_flash_write` application in `sw/applications/spi_flash_write/main.c`.
-
+  
 This example will copy every other byte from a buffer in RAM to a FLASH connected via an SPI to the DMA. Then, it will copy information from an SPI peripheral continuously into a small buffer.
-
+  
 This explanation assumes you have read the previous example.
-
+  
 ---
-
+  
 Start the application by calling
 ```C
 dma_init( NULL );
 ```
-
+  
 The first source target will be pointing to a `uint16_t` buffer in memory. Data will be copied in chunks of 1 byte. For every half-word (16 bits), the only the second half (second 8 bits) will be copied.
-
+  
 ```C
-static dma_target_t tgt1= {
-                            .ptr        = (uint8_t*)(copy_buffer + 1),
-                            .inc_du     = 2,
-                            .size_du    = sizeof(copy_buffer),
-                            .type       = DMA_DATA_TYPE_BYTE,
-};
-
+static  dma_target_t tgt1= {
+				.ptr = (uint8_t*)(copy_buffer + 1),
+				.inc_du = 2,
+				.size_du = sizeof(copy_buffer),
+				.type = DMA_DATA_TYPE_BYTE,
+				};
 ```
-
+  
 To start copying information from the second byte of `copy_buffer`, the source pointer is set to the address of `copy_buffer` plus one byte.
 In order to copy one byte and skip another, the data type is set to byte, and the increment is set to two data units (i.e. two bytes). As for every half-word of the buffer a data unit will be copied, the transaction size is the same as the size of the `copy_buffer`.
-
-
+  
+  
 The second target will point to the address of the SPI FLASH transmission FIFO. On this example, this value was already computed and stored in a constant `ADDRESS_SPI_FLASH_TX_FIFO`.
-
-
+  
+  
 ```C
-static uint32_t *spi_flash_fifo_tx = ADDRESS_SPI_FLASH_TX_FIFO;
-
-
-static dma_target_t tgt2= {
-                            .inc_du     = 0,
-                            .trig       = DMA_TRIG_SLOT_SPI_FLASH_TX,
-};
-
+static  uint32_t *spi_flash_fifo_tx = ADDRESS_SPI_FLASH_TX_FIFO;
+  
+  
+static  dma_target_t tgt2= {
+				.inc_du = 0,
+				.trig = DMA_TRIG_SLOT_SPI_FLASH_TX,
+				};
 tgt2.ptr = spi_flash_fifo_tx;
-
 ```
-
+  
 Because structure initializers need to be constants, the pointer value (which is a non-constant variable) needs to be initialized outside the designated initializer.
-
-
+  
+  
 There is no need to assign a value of transaction size or data type. By default, the DMA will use the source's values. The data type could eventually be modified by the HAL if there is a misalignment and `DMA_ENABLE_REALIGN` is set when creating the transaction.
-
+  
 The increment needs to be set to zero as the pointer should always be set to the FIFO address.
-
+  
 Because the SPI FLASH transmission FIFO has a line connected to slot number 4 (codified as a `1` in the fourth bit of the `trig` element) to let the DMA know if the FIFO is full, a trigger is set in that position by passing `.trig = DMA_TRIG_SLOT_SPI_FLASH_TX`.
-
-
+  
+  
 The transaction is formed by selecting the source and destination targets
-
+  
 ```C
-static dma_trans_t trans = {
-                            .src = &tgt1,
-                            .dst = &tgt2,
-                            .end = DMA_TRANS_END_INTR,
-                            };
+static  dma_trans_t trans = {
+				.src = &tgt1,
+				.dst = &tgt2,
+				.end = DMA_TRANS_END_INTR,
+				};
 ```
-
+  
 To enable interrupts, the end event is set to `DMA_TRANS_END_INTR`.
-
-
+  
+  
 To create the transaction allowing the DMA to perform necessary realignments and integrity checks such arguments are passed to the creation function along with a pointer to the transaction.
-
+  
 ```C
 dma_config_flags_t res;
 res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
 ```
-
+  
 The result variable `res` contains configuration flags that can be used to check that no errors or warnings were raised. These are codified as bits in the 16-bit `res` variable.
 If only one flag was raised, the value of `res` will be equal to it. Otherwise, they can be checked by selecting individual bits, with inequalities, or comparing the result to a bitwise-or of flags.
-
+  
 ```C
 if( res == DMA_CONFIG_OK ) // Everything was ok.
 if( res & DMA_CONFIG_CRITICAL_ERROR ) // A critical error was found. It has to be fixed or the transaction will not be loaded.
 if( res >= DMA_CONFIG_OVERLAP && res =< DMA_CONFIG_TRANS_OVERRIDE ) // One or more warning flags were raised between those two.
 if( res & ( DMA_CONFIG_SRC | DMA_CONFIG_DST) ) // Either one of the flags was raised.
 ```
-
+  
 The transaction can then be loaded into the DMA registers by calling the load function
 ```C
 res = dma_load_transaction( &trans );
 ```
-
+  
 and launched
 ```C
 res = dma_load_transaction( &trans );
 ```
-
+  
 Because the DMA will raise an interrupt as soon as it has sent all of its information, it is recommended to wait for the SPI interrupt.
 ```C
-while( spi_intr_flag == 0 )
-{
-    wait_for_interrupt();
+while( spi_intr_flag == 0 ) {
+	wait_for_interrupt();
 }
 ```
-
+  
 If something is to be done as soon as the DMA finishes (like preparing a new transaction) it can be triggered by the interrupt attention routine:
 ```C
-void dma_intr_handler_trans_done()
-{
-    // Raise a flag to trigger an action
+void  dma_intr_handler_trans_done() {
+// Raise a flag to trigger an action
 }
 ```
 This function is a strong implementation defined in the application of the weak one in `dma.c`.
-
-
+  
+  
 During this transaction
 * The DMA grabbed the first byte of from the pointer (i.e. the second of the buffer, letter `B` in the chart below).
 * Sent it to the SPI, where it will be treated as a 32-bit word.
@@ -329,162 +378,212 @@ During this transaction
 * The source pointer was increased by two data units (i.e. two bytes) to point letter `D` from the chart.
 * The DMA grabbed that byte and sent it to the SPI.
 * The process went on until the the last byte (letter `L`) is sent to the SPI.
-
-
-<style type="text/css">
-.tg  {border-collapse:collapse;border-spacing:0;}
-.tg td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;
-  overflow:hidden;padding:10px 5px;word-break:normal;}
-.tg th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;
-  font-weight:normal;overflow:hidden;padding:10px 5px;word-break:normal;}
-.tg .tg-wp8o{border-color:#000000;text-align:center;vertical-align:top}
+  
+  
+<style  type="text/css">
+.tg {border-collapse:collapse;border-spacing:0;}
+.tg  td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;
+overflow:hidden;padding:10px  5px;word-break:normal;}
+.tg  th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;
+font-weight:normal;overflow:hidden;padding:10px  5px;word-break:normal;}
+.tg  .tg-wp8o{border-color:#000000;text-align:center;vertical-align:top}
 </style>
-<table class="tg">
+<table  class="tg">
 <thead>
-  <tr>
-    <td class="tg-wp8o" colspan="4">RAM</td>
-    <td class="tg-wp8o" rowspan="5"></td>
-    <td class="tg-wp8o" colspan="4">FLASH</td>
-  </tr>
-  <tr>
-    <td class="tg-wp8o">A</td>
-    <td class="tg-wp8o">B</td>
-    <td class="tg-wp8o">C</td>
-    <td class="tg-wp8o">D</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">B</td>
-  </tr>
-  <tr>
-    <td class="tg-wp8o">E</td>
-    <td class="tg-wp8o">F</td>
-    <td class="tg-wp8o">G</td>
-    <td class="tg-wp8o">H</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">D</td>
-  </tr>
-  <tr>
-    <td class="tg-wp8o">I</td>
-    <td class="tg-wp8o">J</td>
-    <td class="tg-wp8o">K</td>
-    <td class="tg-wp8o">L</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">0</td>
-    <td class="tg-wp8o">F</td>
-  </tr>
-  <tr>
-    <td class="tg-wp8o">.</td>
-    <td class="tg-wp8o">.</td>
-    <td class="tg-wp8o">.</td>
-    <td class="tg-wp8o">.</td>
-    <td class="tg-wp8o">.</td>
-    <td class="tg-wp8o">.</td>
-    <td class="tg-wp8o">.</td>
-    <td class="tg-wp8o">.</td>
-  </tr>
+<tr>
+<td  class="tg-wp8o"  colspan="4">RAM</td>
+<td  class="tg-wp8o"  rowspan="5"></td>
+<td  class="tg-wp8o"  colspan="4">FLASH</td>
+</tr>
+<tr>
+<td  class="tg-wp8o">A</td>
+<td  class="tg-wp8o">B</td>
+<td  class="tg-wp8o">C</td>
+<td  class="tg-wp8o">D</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">B</td>
+</tr>
+<tr>
+<td  class="tg-wp8o">E</td>
+<td  class="tg-wp8o">F</td>
+<td  class="tg-wp8o">G</td>
+<td  class="tg-wp8o">H</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">D</td>
+</tr>
+<tr>
+<td  class="tg-wp8o">I</td>
+<td  class="tg-wp8o">J</td>
+<td  class="tg-wp8o">K</td>
+<td  class="tg-wp8o">L</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">0</td>
+<td  class="tg-wp8o">F</td>
+</tr>
+<tr>
+<td  class="tg-wp8o">.</td>
+<td  class="tg-wp8o">.</td>
+<td  class="tg-wp8o">.</td>
+<td  class="tg-wp8o">.</td>
+<td  class="tg-wp8o">.</td>
+<td  class="tg-wp8o">.</td>
+<td  class="tg-wp8o">.</td>
+<td  class="tg-wp8o">.</td>
+</tr>
 </thead>
 </table>
-
-
+  
+  
 ---
-
-
+  
+  
 For the second part of this example, the targets will be modified and their role switched.
-
+  
 The source of the data will be a peripheral connected to the SPI, which will be continuously sending information in half-word format, in streams of 4096 bytes (2048 half-words). Every 1024 half-words there should be a `MILESTONE-CHARACTER`, if there is not, the data flow should be stopped.
-
+  
 ```C
-tgt2.ptr        = spi_peripheral_fifo_rx;
-tgt2.size_du    = 2048;
-tgt2.type       = DMA_DATA_TYPE_HALF_WORD;
-tgt2.trig       = DMA_TRIG_SLOT_SPI_RX;
+tgt2.ptr = spi_peripheral_fifo_rx;
+tgt2.size_du = 2048;
+tgt2.type = DMA_DATA_TYPE_HALF_WORD;
+tgt2.trig = DMA_TRIG_SLOT_SPI_RX;
 ```
-
+  
 The source pointer is set to the reception FIFO of the SPI, and the appropriate slot is chosen.
 The increment is kept in zero.
-
+  
 The destination pointer will be given by a function.
-
+  
 ```C
-tgt1.ptr        = (uint8_t*) myApp_getDestination();
+tgt1.ptr = (uint8_t*) myApp_getDestination();
 ```
-
+  
 To guarantee that the result of this function will not cause the DMA to write in undesired regions of memory, an environment can be created.
 It requires two pointers to the first and last byte where the DMA will be authorized to make any action.
 ```C
-static dma_env_t safe_zone = {
-                                .start  = ADDRESS_START_OF_SAFE_ZONE,
-                                .end    = ADDRESS_END_OF_SAFE_ZONE,
+static  dma_env_t safe_zone = {
+				.start = ADDRESS_START_OF_SAFE_ZONE,
+				.end = ADDRESS_END_OF_SAFE_ZONE,
 };
 ```
-
+  
 The environment can be assigned to the target.
 ```C
-tgt1.env    = &safe_zone;
+tgt1.env = &safe_zone;
 tgt1.inc_du = 1;
 ```
-
+  
 Size and data type is up to the source, and the rest of the configurations are inherited from the last transaction.
-
+  
 The transaction is conformed as:
 ```C
-window_size_du  = 1024;
-
-trans.src       = &tgt2;
-trans.dst       = &tgt1;
-trans.mode      = DMA_TRANS_MODE_CIRCULAR;
-trans.win_du    = window_size_du;
-
+window_size_du = 1024;
+  
+trans.src = &tgt2;
+trans.dst = &tgt1;
+trans.mode = DMA_TRANS_MODE_CIRCULAR;
+trans.win_du = window_size_du;
+  
 ```
-
+  
 Meaning that the information will start to flow into the target 1 from target 2, and every 1024 half-words transferred the application will get an interrupt to check if the `MILESTONE_SYMBOL` is present. Upon finishing the transaction, it shall start again to refill the buffer as it was set in `CIRCULAR_MODE`.
-
+  
 The amount of times the buffer was filled will be updated on every _transaction done_ interrupt.
 ```C
-void dma_intr_handler_trans_done()
-{
-    transaction_count++;
+void  dma_intr_handler_trans_done() {
+	transaction_count++;
 }
 ```
-
+  
 The search for the `MILESTONE_SYMBOL` can be done inside the _window done_ interrupt handling.
 ```C
-void dma_intr_handler_window_done()
-{
-    /* The current window is obtained. The count is zero when no windows have yet been written. When it is set to one, the window zero is ready. */
-    window_count    = dma_get_window_count() -1;
-    /* The pointer to the symbol is obtained from the destination pointer + the amount of half-words that have been written. this assumes the symbol is on the first element of each chunk.*/
-    address         = (uint16_t *)trans.dst->ptr + window_count*window_size_du;
-    symbol          = *address;
-    if( symbol != MILESTONE_SYMBOL )
-    {
-        /* If the symbol was not the expected one, future transactions should not be carried out.*/
-        dma_stop_circular();
-        /* The number of the first window with error is saved to analyze it later.*/
-        error_window = error_window == 0 ? window_count : error_window;
-    }
+void  dma_intr_handler_window_done() {
+	/* The current window is obtained. The count is zero when no windows have yet been written. When it is set to one, the window zero is ready. */
+	window_count = dma_get_window_count() -1;
+	/* The pointer to the symbol is obtained from the destination pointer + the amount of half-words that have been written. this assumes the symbol is on the first element of each chunk.*/
+	address = (uint16_t *)trans.dst->ptr + window_count*window_size_du;
+	symbol = *address;
+	if( symbol != MILESTONE_SYMBOL ){
+		/* If the symbol was not the expected one, future transactions should not be carried out.*/
+		dma_stop_circular();
+		/* The number of the first window with error is saved to analyze it later.*/
+		error_window = error_window == 0 ? window_count : error_window;
+	}
 }
 ```
 > :warning: Interrupt attention routines are advised to be kept as short as possible. This example is merely illustrative.
-
+  
 Once the `dma_stop_circular()` function is called, the DMA will still finish the transaction it is currently executing (which could be a whole transaction if the faulty window was the last one). It is important to save valuable information that might be overridden by the ongoing transaction (like the faulty window number).
-
-
+  
+  
 ## Testing
 This section will describe the available example application in X-HEEP using the DMA, and will outline the testing that needs to be performed in order to validate its proper operation.
-
-
+  
+  
 ### Available Applications
-
+  
 There are 6 applications using the DMA:
-* `dma_example`: Tests memory-to-memory transfer, the blocking of transactions while another one is in progress, and window interrupts.
-* `example_external_peripheral`: Tests the use of the DMA HAL one a DMA instance external to X-HEEP. Only available for simulation.
-* `example_virtual_flash`: Tests the transfer to/from an external flash through the DMA.
-* `spi_flash_write`: Tests the transfer to/from the flash. Tests circular mode. Not available on FPGA if linker is `flash-exec`. Should be used with `mcu gen BUS=NtoM CPU=cv32e40p` to test circular mode.
-* `spi_host_dma_exampe`: Test the transfer of data through the SPI host. Not available on Verilator.
-* `spi_host_dma_power_gate_example`: Test the transfer of data through the SPI host. Not available on Verilator.
-
+*  `dma_example`: Tests memory-to-memory transfer, the blocking of transactions while another one is in progress, and window interrupts.
+*  `example_external_peripheral`: Tests the use of the DMA HAL one a DMA instance external to X-HEEP. Only available for simulation.
+*  `example_virtual_flash`: Tests the transfer to/from an external flash through the DMA.
+*  `spi_flash_write`: Tests the transfer to/from the flash. Tests circular mode. Not available on FPGA if linker is `flash-exec`. Should be used with `mcu gen BUS=NtoM CPU=cv32e40p` to test circular mode.
+*  `spi_host_dma_exampe`: Test the transfer of data through the SPI host. Not available on Verilator.
+*  `spi_host_dma_power_gate_example`: Test the transfer of data through the SPI host. Not available on Verilator.
+  
+  
+## 😎 X-pert Zone:
+  
+If you know what you are doing and want to minimize the overhead of using the DMA, you can try by-passing the HAL and writing directly on the configuration registers.
+  
+```c
+/* We will copy a set of 25 half-words of 16 bits into a buffer of 32-bit words.
+Each word in the destination buffer will have its 16 MSB set to 0, and the 16 LSB with the corresponding value from the source.*/
+#define HALF_WORDS_TO_COPY 25
+static  uint16_t  src_buffer[HALF_WORDS_TO_COPY]; // The source buffer
+static  uint32_t  dst_buffer[HALF_WORDS_TO_COPY]; // The destination buffer
+  
+/* Set the DMA's control block's peripheral structure to point to the address defined in core_v_mini_mcu.h */
+dma_cb.peri = dma_peri;
+/* Activate interrupts*/
+dma_cb.peri->INTERRUPT_EN |= INTR_EN_TRANS_DONE;
+/* Set the source and destination pointers*/
+dma_cb.peri->SRC_PTR = (uint16_t*) source_buffer;
+dma_cb.peri->DST_PTR = (uint32_t*) dst_buffer;
+  
+/* Set the source increment as 2 bytes (because the source buffer is uint16_t).
+Set the destination increment as 4 bytes (because the destination buffer is uint32_t).
+We write 1026 = 0000 0100 0000 0010,
+as the first 8 LSB refer to the source, and the next 8 bits for the destination. */
+dma_cb.peri->PTR_INC = (uint32_t) 1026;
+  
+/* Make sure that the DMA will point to memory.*/
+dma_cb.peri->SLOT = DMA_TRIG_MEMORY;
+  
+/* Set the data transfer type as half-words.*/
+dma_cb.peri->TYPE = DMA_DATA_TYPE_HALF_WORD;
+  
+/* Set the transaction size, this will launch the transaction.
+If you want to restart the same transaction again, just run from here.*/
+dma_cb.peri->SIZE = HALF_WORDS_TO_COPY;
+  
+/* Go to sleep until the DMA finishes.*/
+while( dma_cb.peri->STATUS == 0 ) {
+	/* Disable the interrupts MSTATUS to avoid going to sleep AFTER the interrupt
+	was triggered.*/
+	CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+	/* If the transaction has not yet finished, go to sleep*/
+	if (dma_cb.peri->STATUS == 0) {
+		/* If a interrupt happened before, the core would still wake-up,
+		but will not jump to the interrupt handler MSTATUS is not re-set. */
+		{ asm  volatile("wfi"); }
+	}
+	/* Restore the interrupts. */
+	CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+}
+  
+  
+```
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/SPI.md b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/SPI.md
new file mode 100644
index 00000000..72315f6c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/SPI.md
@@ -0,0 +1,1246 @@
+# SPI Host
+
+```{contents} Table of Contents
+:depth: 2
+```
+
+There are three instances of the _SPI Host IP_ in the X-HEEP platform. These will
+be defined throughout the documentation as:
+
+- SPI Host 1
+- SPI Host 2
+- SPI Flash
+
+## Preliminary Definitions
+
+### Transaction
+
+A transaction is defined by one or multiple command segments.
+
+### Command Segment
+
+A command segment is a single instruction provided to the _SPI Host IP_ specifying 
+speed, direction, and additional parameters discussed later.
+
+### SPI Host
+
+SPI Host refers to the particular hardware device for which this SDK and HAL have 
+been developed. _SPI Host_, _SPI Host IP_, and _SPI Host device_ are used 
+interchangeably.
+
+### TX and RX
+
+- TX: Transmission-related data or operations.
+
+- RX: Reception-related data or operations.
+
+### Slave and Target
+
+_Slave_ and _target_ are used interchangeably, referring to the SPI device that 
+responds to the SPI Host.
+
+### Word
+
+A word, when used as a unit of digital information, always refers to 32 bits
+throughout the entire documentation.
+
+
+## SDK Usage
+
+The SDK facilitates communication with external SPI devices through the `spi_t` 
+structure, which holds necessary information, including the specific _SPI Host IP_ 
+and external _SPI slave_ data.
+
+```c
+typedef struct {
+    spi_idx_e   idx;   // The identifier for the desired SPI devide
+    uint32_t    id;    // spi_t instance ID
+    bool        init;  // Indicates if initialization was successful
+    spi_slave_t slave; // The slave with whom to communicate configuration 
+} spi_t;
+```
+
+- `idx` can be `SPI_IDX_FLASH`, `SPI_IDX_HOST` or `SPI_IDX_HOST_2`,
+each referring to a specific _SPI Host IP_.
+
+- `id` is the identifier of the specific `spi_t` instance.
+
+- `init` is a boolean used to verify if the `spi_t` variable is properly initialized.
+
+- `slave` is the structure containing all information about the external SPI slave.
+
+
+### The Slave
+
+The `spi_slave_t` structure is defined as:
+
+```c
+typedef struct {
+    // The Chip Select line where device connected
+    uint8_t        csid       : 2;
+    // The data sampling and transmitting mode (polarity and phase)
+    spi_datamode_e data_mode  : 2;
+    // If 1 data is sampled a full cycle after shifting data out, instead of half cycle
+    bool           full_cycle : 1;
+    // The minimum number of sck half-cycles to hold cs_n high between commands
+    uint8_t        csn_idle   : 4;
+    // The number of half sck cycles, CSNTRAIL+1, to leave between last edge of sck 
+    // and the rising edge of cs_n
+    uint8_t        csn_trail  : 4;
+    // The number of half sck cycles, CSNLEAD+1, to leave between the falling edge 
+    // of cs_n and the first edge of sck
+    uint8_t        csn_lead   : 4;
+    // The maximum frequency in hertz of the slave
+    uint32_t       freq       : 32;
+} spi_slave_t;
+```
+
+These fields depend on the external SPI slave you intend to communicate with.
+
+- `csid` is the _Chip Select_ ID (i.e. the line to which your slave is connected).
+It can only be __0__ or __1__.
+
+- `data_mode` specifies the phase and polarity the slave uses. Possible values are:
+
+    - `SPI_DATA_MODE_0`: Clock polarity 0, phase 0. (__active-high__
+    SCK, sampling data on the __leading__ edge, and asserting data on the __trailing__ edge)
+    - `SPI_DATA_MODE_1`: Clock polarity 0, phase 1. (__active-high__
+    SCK, sampling data on the __trailing__ edge, and asserting data on the __leading__ edge)
+    - `SPI_DATA_MODE_2`: Clock polarity 1, phase 0. (__active-low__
+    SCK, sampling data on the __leading__ edge, and asserting data on the __trailing__ edge)
+    - `SPI_DATA_MODE_3`: Clock polarity 1, phase 1. (__active-low__
+    SCK, sampling data on the __trailing__ edge, and asserting data on the __leading__ edge)
+
+- `full_cycle` determines if data should be sampled _half SCK_ cycle or a _full SCK_ cycle 
+after shifting out data. 
+
+- `csn_idle`, `csn_trail`, and `csn_lead` indicate the number of _half SCK_ cycles to keep
+the _CS_ line active between command segments, after segments, and before segments,
+respectively. The actual number of cycles will be the specified number + 1. For instance, if
+`csn_lead` is 5, the _CS_ line will go active 6 _half SCK_ cycles before executing the 
+command segment.
+
+- `freq` is the maximum desired frequency for the communication. The true frequency
+will be an integer division of half the MCU core frequency. The integer divisor will
+be computed by the SDK based on the maximum desired frequency provided, and will take
+a value between 1 and 65536 (16 bits). This implies that the true frequency will never
+be larger than half the MCU core frequency. The SDK will also return an invalid `spi_t` 
+if the desired maximum frequency provided is lower than half the MCU core frequency 
+divided by 65536.
+
+````{tip}
+It is possible to change the frequency of a particular slave after initialization if
+you wish to decrease or increase the communication speed with:
+
+```c
+spi_codes_e spi_set_slave_freq(spi_t* spi, uint32_t freq);
+```
+````
+
+
+### Initialization
+
+To start using the SDK, you must create an `spi_slave_t` and an `spi_t`. However, 
+the `spi_t` __can't__ be created directly; it must be created through the `spi_init` 
+function of the SDK to avoid unexpected behaviour.
+
+The function is defined as:
+```c
+spi_t spi_init(spi_idx_e idx, spi_slave_t slave);
+```
+
+This function checks the provided parameters and validates the slave configuration. 
+If there is any error it will return an invalid `spi_t` structure. This can be verified 
+by reading the `init` field of the structure.
+
+Example:
+```c
+spi_slave_t slave = {
+    .csid = 0,
+    .csn_idle = 15,
+    .csn_lead = 15,
+    .csn_trail = 15,
+    .data_mode = SPI_DATA_MODE_0,
+    .full_cycle = false,
+    .freq = FLASH_MAX_FREQ
+};
+
+spi_t spi = spi_init(SPI_IDX_FLASH, slave);
+
+if (spi.init) {
+    // Properly initialized
+}
+else {
+    // Initialization error
+}
+```
+
+````{tip}
+A slave with predefined standard values can be created using the macro:
+```c
+#define SPI_SLAVE(csid, freq) (spi_slave_t) { \
+    .csid       = csid, \
+    .data_mode  = SPI_DATA_MODE_0, \
+    .full_cycle = false, \
+    .csn_lead   = 10, \
+    .csn_trail  = 10, \
+    .csn_idle   = 10, \
+    .freq       = freq \
+}
+```
+````
+
+```{note}
+After initialization, the `freq` field of the `spi_slave_t` structure of the 
+`slave` field of the obtained `spi_t` structure, will provide the value of the 
+_true_ frequency, no longer the maximum desired frequency provided!
+```
+
+### Transactions
+
+Once the `spi_t` has been successfully initialized, communication with its slave 
+device can be performed via transactions, which are lists of command segments executed 
+by the _SPI Host IP_.
+
+#### Command Segments
+
+Each command segment consists of a simple instruction dermining the direction of 
+data transfer (TX, RX or Bidirectional), its speed (Standard, Dual, or Quad), and
+the length of the data.
+
+The command segment structure `spi_segment_t` is as:
+
+```c
+typedef struct {
+    uint32_t   len  : 24;  // Length of data in bytes for the particular segment
+    spi_mode_e mode : 4;   // Communication mode (TX, BIDIR, RX_QUAD, ...)
+} spi_segment_t;
+```
+
+- `len` specifies the length in **bytes** of the data managed by this segment. 
+For instance, to send 4 32-bit words, the length would be 16.
+
+- `mode` indicates the data transfer direction and speed. Possible values are:
+
+    - `SPI_MODE_DUMMY`  
+    - `SPI_MODE_RX_STD` 
+    - `SPI_MODE_TX_STD` 
+    - `SPI_MODE_BIDIR`  
+    - `SPI_MODE_RX_DUAL`
+    - `SPI_MODE_TX_DUAL`
+    - `SPI_MODE_RX_QUAD`
+    - `SPI_MODE_TX_QUAD`
+
+_DUMMY_ mode refers to a period where the _SPI Host IP_ sends _SCK_ pulses without 
+reading or sending any data. The number of _SCK_ pulses is determined by the `len` 
+field. For example, to send 10 _SCK_ pulses, `len` must be set to 10 (seems evident,
+but I rather put it explicitly).
+
+```{note}
+There are no _Dual_ or _Quad_ speeds for _Bidirectional_ mode because the _SPI Host IP_ 
+doesn't support it.
+```
+
+```{tip}
+There are macros for each segment _mode_ simplifying command segment creation.
+
+The macros are: `SPI_SEG_DUMMY`, `SPI_SEG_TX`, `SPI_SEG_RX`, `SPI_SEG_BIDIR`,
+`SPI_SEG_TX_DUAL`, `SPI_SEG_RX_DUAL`, `SPI_SEG_TX_QUAD`, and `SPI_SEG_RX_QUAD`
+
+Each macro takes one argument which sets the `len` field.
+```
+
+As mentioned above, a transaction comprises various command segments, so an array 
+of segments is required.
+
+For example:
+```c
+spi_segment_t segments[2] = { SPI_SEG_TX(4), SPI_SEG_RX(256) };
+```
+
+#### TX/RX Buffers
+
+Since these segments transmit/receive data, appropriate TX and RX buffers are needed. 
+These buffers must be large enough to contain the data being transmitted/received to 
+avoid memory overwrites.
+
+For our example with 4 bytes of TX and 256 bytes of RX, the buffers would be:
+
+```c
+uint32_t src_buffer      = 0;
+uint32_t dest_buffer[64] = {0};
+```
+
+```{caution}
+:name: caution-seglen-bufflen
+
+While segments with lengths not multiple of 4 are allowed, buffers **must** be multiples 
+of 4 bytes because the _SPI Host IP_ only allows reads from the RX _FIFO_ one word at
+a time.
+
+It is the _segment length_ that will ultimately determine the amount of bytes effectively
+transmitted/received, not the buffer size.
+
+For example, an RX segment of length 3 is fine, but the _dest\_buffer_ should be at least 
+4 bytes to avoid unexpected behavior.
+
+This design choice was made to avoid having various alignment computations, thus favoring 
+computational speed at expense of minimal amount of superfluous bytes.
+```
+
+#### Execution
+
+With the buffers and segments ready, the transaction can be issued using:
+
+```c
+spi_codes_e spi_execute(spi_t* spi, const spi_segment_t* segments, 
+                        uint32_t segments_len, const uint32_t* src_buffer, 
+                        uint32_t* dest_buffer);
+```
+
+This function returns `SPI_CODE_OK` if the transaction is successfully issued. Otherwise, 
+it returns an error code.
+
+And, after a transaction has completed, the result can be checked using:
+
+```c
+spi_state_e spi_get_state(spi_t* spi);
+```
+
+Which returns `SPI_STATE_DONE` if the transaction completed successfully
+(i.e. all segments were completed), `SPI_STATE_ERROR` if a hardware error occured
+during the transaction, or `SPI_STATE_TIMEOUT` if the transaction has timed-out.
+
+````{important}
+The SDK completely relies on _SPI Host IP_ interrupts in order to execute any
+transaction. Therefore, it is crucial to **enable _SPI Host_ interrupts** at machine-
+level before any transaction is initiated.
+
+Example
+
+```c
+// Enable global interrupt for machine-level interrupts
+CSR_SET_BITS(CSR_REG_MSTATUS, CSR_INTR_EN);
+// Set mie.MEIE bit to one to enable machine-level fast spi_flash interrupt
+const uint32_t mask = 1 << FIC_FLASH_MEIE;
+CSR_SET_BITS(CSR_REG_MIE, mask);
+```
+````
+
+#### Example
+
+A complete example of executing a transaction:
+
+```c
+// Assuming spi variable is properly initialized and machine-level interrupts have
+// been enabled.
+
+// Define transaction command segments
+spi_segment_t segments[2] = { SPI_SEG_TX(4), SPI_SEG_RX(256) };
+// Initialize data buffers
+uint32_t src_buffer      = 0;
+uint32_t dest_buffer[64] = {0};
+// Execute the transaction
+if (spi_execute(&spi, segments, 2, &src_buffer, dest_buffer) == SPI_CODE_OK)
+{
+    if (spi_get_state(&spi) == SPI_STATE_DONE)
+    {
+        // Transaction successful
+    }
+    else {
+        // Transaction error
+    }
+}
+else {
+    // Configuration error
+}
+```
+
+#### Simplified Transaction Functions
+
+This method is the most configurable. However, there are simpler methods for common 
+transactions:
+
+```c
+spi_codes_e spi_transmit  (spi_t* spi, const uint32_t* src_buffer, uint32_t len);
+spi_codes_e spi_receive   (spi_t* spi, uint32_t* dest_buffer, uint32_t len);
+spi_codes_e spi_transceive(spi_t* spi, const uint32_t* src_buffer, 
+                           uint32_t* dest_buffer, uint32_t len);
+```
+
+```{caution}
+The `len` parameter specifies the number of **bytes**, not words.
+```
+
+These functions execute basic standard transactions: `spi_transmit` performs a _TX Standard_ 
+transaction, `spi_receive` performs an _RX Standard_ transaction, and `spi_transceive` 
+performs a _Bidirectional Standard_ transaction. They work like `spi_execute` but do not 
+require command segments to be provided.
+
+#### Timeout
+
+All blocking functions have a maximum allowed time from the start of a transaction 
+to its complete execution. This duration can be easily configured and retrieved 
+using the following functions:
+
+```c
+spi_codes_e spi_set_timeout(spi_t* spi, uint32_t timeout);
+
+spi_codes_e spi_get_timeout(spi_t* spi, uint32_t* timeout);
+```
+
+This timeout is entirely independent for each _SPI Host_ device. It specifies the
+maximum number of **milliseconds** permitted to elapse from the issuance of the 
+first command segment to the hardware until the last 32-bit word is read from the 
+RX FIFO.
+
+The maximum allowed value for the timeout is {math}`2^{32}-1` (unless the core 
+clock frequency exceeds 4 THz, which is unlikely to occur in the near future :) ). 
+And the default timeout value is set to 100ms.
+
+
+### Non-Blocking Transactions
+
+To allow the main program to continue processing while a transaction executes, each 
+transaction function has also a _non-blocking_ variant:
+
+```c
+spi_codes_e spi_transmit_nb(spi_t* spi, const uint32_t* src_buffer, uint32_t len,
+                            spi_callbacks_t callbacks);
+
+spi_codes_e spi_receive_nb(spi_t* spi, uint32_t* dest_buffer, uint32_t len, 
+                           spi_callbacks_t callbacks);
+
+spi_codes_e spi_transceive_nb(spi_t* spi, const uint32_t* src_buffer, 
+                              uint32_t* dest_buffer, uint32_t len, 
+                              spi_callbacks_t callbacks);
+
+spi_codes_e spi_execute_nb(spi_t* spi, const spi_segment_t* segments, 
+                           uint32_t segments_len, const uint32_t* src_buffer, 
+                           uint32_t* dest_buffer, spi_callbacks_t callbacks);
+```
+
+These functions differ in two aspects from their _blocking_ counterpart. First, these 
+functions return immediately after launching the transaction, allowing other data 
+processing while the transaction completes. Secondly, they take an additional parameter 
+of type `spi_callbacks_t`.
+
+#### Callbacks
+
+```c
+// Callback type
+typedef void (*spi_cb_t)(const uint32_t*, uint32_t, uint32_t*, uint32_t);
+
+// Callbacks structure
+typedef struct {
+    spi_cb_t done_cb;   // Called once transaction is done
+    spi_cb_t txwm_cb;   // Called each time TX watermark event is triggered
+    spi_cb_t rxwm_cb;   // Called each time RX watermark event is triggered
+    spi_cb_t error_cb;  // Called when there was an error during transaction
+} spi_callbacks_t;
+```
+
+The _callback_ type (`spi_cb_t`) is invoked with four arguments whenever the corresponding 
+event occurs:
+
+1. The _TX buffer_ associated to the transaction.
+1. The current number of words in the _TX buffer_.
+1. The _RX buffer_ associated to the transaction.
+1. The current number of words in the _RX buffer_.
+
+Callbacks in `spi_callbacks_t` can be `NULL` if not needed.
+
+```{note}
+In this context, the function `spi_get_state` previously explained, can be used to 
+check if the transaction is still ongoing (`SPI_STATE_BUSY`) or has finished. Once
+finished the state will also become `SPI_STATE_DONE` or `SPI_STATE_ERROR` depending 
+on the result of the transaction.
+```
+
+```{tip}
+It is possible to get or set the watermark values with the functions `spi_set_txwm`,
+`spi_set_rxwm`, `spi_get_txwm`, and `spi_get_rxwm`.
+```
+
+#### Example
+
+```c
+void done_cb(const uint32_t* txbuff, uint32_t txlen, uint32_t* rxbuff, uint32_t rxlen)
+{
+    // Do stuff with the data once the transaction is done
+}
+
+int main(int argc, char *argv[])
+{
+    // ...
+
+    // We assume an spi variable has been created by properly initializing it and
+    // that machine-level interrupts have been appropriately enabled.
+
+    uint32_t src_buffer = 0x1234    // For example a command to send to slave
+    uint32_t dest_buffer[12] = {0}  // Slave's response
+
+    // Notice that the segments' length are not multiples of 4.
+    spi_segment_t segments[2] = { SPI_SEG_TX(2), SPI_SEG_RX(45) };
+
+    // Define the callbacks. Notice we can assign NULL when we do not want any
+    // callback to be called
+    spi_callbacks_t callbacks = {
+        .done_cb  = &done_cb,
+        .error_cb = NULL,
+        .rxwm_cb  = NULL,
+        .txwm_cb  = NULL
+    };
+
+    if (!spi_execute_nb(&spi, segments, 2, &src_buffer, dest_buffer, callbacks))
+    {
+        while(spi_get_state(spi) == SPI_STATE_BUSY)
+        {
+            // Do stuff while SPI is busy
+        }
+    }
+    else {
+        // There was an error in the transaction configuration
+    }
+
+    // ...
+}
+```
+
+```{note}
+In this example, the _TX segment length_ is 2 while _src\_buffer_ is 4 bytes long, 
+and the _RX segment length_ is 45 while _dest\_buffer_ is 48 bytes long.
+For explanation, please refer to [this directive](#caution-seglen-bufflen).
+```
+
+
+## HAL Usage
+
+### Overview
+
+The three instances of the _SPI Host IP_ of the X-HEEP platform can be referenced 
+in the HAL with the macros:
+
+- `spi_host1` for _SPI Host 1_.
+- `spi_host2` for _SPI Host 2_.
+- `spi_flash` for _SPI Flash_.
+
+These macros expand to variables of type `spi_host_t*`. They must be passed to any 
+HAL function requiring to reference the specific peripheral.
+
+
+#### Return Flags
+
+Most functions in the HAL return an enum value of type `spi_return_flags_e`, indicating 
+the outcome of the operation. Below is the complete list of return flags:
+
+```c
+typedef enum {
+    // Everithing went well
+    SPI_FLAG_OK                 = 0x0000,
+    // The SPI variabled passed was a null pointer
+    SPI_FLAG_NULL_PTR           = 0x0001,
+    // The Watermark exceeded SPI_HOST_PARAM_TX_DEPTH or SPI_HOST_PARAM_RX_DEPTH 
+    // and was therefore not set
+    SPI_FLAG_WATERMARK_EXCEEDS  = 0x0002,
+    // The CSID was out of the bounds specified inSPI_HOST_PARAM_NUM_C_S 
+    SPI_FLAG_CSID_INVALID       = 0x0004,
+    // The CMD FIFO is currently full so couldn't write command
+    SPI_FLAG_COMMAND_FULL       = 0x0008,
+    // The specified speed is not valid so couldn't write command
+    SPI_FLAG_SPEED_INVALID      = 0x0010,
+    // The TX Queue is full, thus could not write to TX register
+    SPI_FLAG_TX_QUEUE_FULL      = 0x0020,
+    // The RX Queue is empty, thus could not read from RX register
+    SPI_FLAG_RX_QUEUE_EMPTY     = 0x0040,
+    // The SPI is not ready
+    SPI_FLAG_NOT_READY          = 0x0080,
+    // The event to enable is not a valid event
+    SPI_FLAG_EVENT_INVALID      = 0x0100,
+    // The error irq to enable is not a valid error irq
+    SPI_FLAG_ERROR_INVALID      = 0x0200 
+} spi_return_flags_e;
+```
+
+
+**Note**: All functions in the HAL returning a `spi_return_flags_e` will **always** 
+return `SPI_FLAG_NULL_PTR` when the argument `spi_host_t* spi` is a `NULL` pointer 
+and `SPI_FLAG_OK` if the operation has suceeded. To avoid repetition, `SPI_FLAG_NULL_PTR` 
+and `SPI_FLAG_OK` will be omitted from discussions of function return values. Only
+`spi_return_flags_e` different from these two will be mentioned. If there is any
+doubt please refer to the functions documentation.
+
+
+### Target Device Configuration
+
+Using the HAL begins by configuring the slave device(s) you intend to communicate 
+with. For this purpose, a configuration options structure, `spi_configopts_t`, is 
+provided, along with functions to write the slave configuration options to the 
+_SPI Host IP_.
+
+#### Configuration Options Structure
+
+```c
+typedef struct spi_configopts_s {
+    // The clock divider to use with a paricular slave
+    uint16_t clkdiv     : 16;
+    // Indicates the minimum number of sck half-cycles to hold cs_n high between 
+    // commands
+    uint8_t  csnidle    : 4; 
+    // Indicates the number of half sck cycles, CSNTRAIL+1, to leave between last 
+    // edge of sck and the rising edge of cs_n
+    uint8_t  csntrail   : 4;
+    // Indicates the number of half sck cycles, CSNLEAD+1, to leave between the 
+    // falling edge of cs_n and the first edge of sck
+    uint8_t  csnlead    : 4;
+    // Will be ignored by hardware
+    bool     __rsvd0    : 1;
+    // If 1 data is sampled a full cycle after shifting data out, instead of half cycle
+    bool     fullcyc    : 1;
+    // If 0 data lines change on trailing edge and sample done on leading edge, 
+    // if 1 it is the opposite
+    bool     cpha       : 1;
+    // If 0 sck is low when idle, and emits high pulses. If 1 sck is high when idle, 
+    // and emits of low pulses
+    bool     cpol       : 1;
+} spi_configopts_t;
+```
+
+#### Configuration Functions
+
+```c
+uint32_t spi_create_configopts(const spi_configopts_t configopts);
+
+spi_return_flags_e spi_set_configopts(spi_host_t* spi, uint32_t csid, 
+                                      const uint32_t conf_reg);
+```
+
+#### Configuration Steps
+
+To create and write the configuration options to the hardware:
+
+1. **Define Configuration**: Create a `spi_configopts_t` structure with the desired 
+settings.
+1. **Create Configuration Word**: Call `spi_create_configopts` with the structure 
+to generate a 32-bit configuration word.
+1. **Apply Configuration**: Call `spi_set_configopts` with the SPI instance, _Chip Select_ 
+ID (`csid`), and the configuration word.
+1. **Verify Configuration**: Ensure the function returns `SPI_FLAG_OK` to confirm 
+successful configuration.
+
+The configuration options persist until overwritten or the _SPI Host IP_ is reset.
+
+
+### Enabling the SPI Host
+
+After configuring the slave, enable the _SPI Host IP_ and its output buffers:
+
+```c
+spi_return_flags_e spi_set_enable(spi_host_t* spi, bool enable);
+spi_return_flags_e spi_output_enable(spi_host_t* spi, bool enable);
+```
+
+Both functions must be called to start communication:
+
+- `spi_set_enable`: Enables the _SPI Host IP_.
+- `spi_output_enable`: Enables the output buffers for _SCK_, _CSB_, and _SD_ lines.
+
+
+
+### Communication Commands
+
+Communication with SPI slaves involves creating and inputting commands to the 
+_SPI Host IP_. Each command instructs the _SPI Host IP_ to execute a transfer 
+(transmit/receive) for a certain amount of bytes, in a specific direction and speed.
+
+
+#### Command Structure
+
+```c
+typedef struct spi_command_s {
+    // Length-1 in bytes for the command to transmit/receive
+    uint32_t    len         : 24;
+    // Keep CS line active after command has finished (allows to instruct series 
+    // of commands)
+    bool        csaat       : 1;
+    // Speed of communication
+    spi_speed_e speed       : 2;
+    // Direction of communication
+    spi_dir_e   direction   : 2;
+} spi_command_t;
+```
+
+- `len`: Length of bytes - 1 to transmit/receive.
+In the case of `SPI_DIR_DUMMY` direction, it represents the number of _SCK_ impulses 
+to send without transmitting or receiving any data.
+- `csaat`: Keeps CS line active after the command (see [Advanced Commands](#hal-advanced-commands)).
+- `speed`: Communication speed (`SPI_SPEED_STANDARD`, `SPI_SPEED_DUAL`, `SPI_SPEED_QUAD`).
+- `direction`:Communication direction (`SPI_DIR_DUMMY`, `SPI_DIR_RX_ONLY`, `SPI_DIR_TX_ONLY`,
+`SPI_DIR_BIDIR`).
+
+```{note}
+The direction `SPI_DIR_BIDIR` can only use the speed `SPI_SPEED_STANDARD`. Configuring 
+`SPI_DIR_BIDIR` with any other speed will return `SPI_FLAG_SPEED_INVALID` when issuing
+the command.
+```
+
+#### Setting Chip Select ID
+
+Specify the target device by setting the Chip Select line:
+
+```c
+spi_return_flags_e spi_set_csid(spi_host_t* spi, uint32_t csid);
+```
+
+- `csid`: _Chip Select_ line (0 or 1).
+
+This function returns `SPI_FLAG_CSID_INVALID` if the `csid` is out of range.
+
+
+#### Loading TX FIFO
+
+If the command transmits data (`SPI_DIR_TX_ONLY` or `SPI_DIR_BIDIR`), load the 
+TX _FIFO_ with data:
+
+```c
+spi_return_flags_e spi_write_word(spi_host_t* spi, uint32_t wdata);
+
+spi_return_flags_e spi_write_byte(spi_host_t* spi, uint8_t bdata);
+```
+
+You can load only one 32-bit word or one byte at a time. Therefore, iterate over 
+all the data you want to transmit until either the _FIFO_ is full or all the data 
+is loaded.
+
+Both write functions will return either `SPI_FLAG_TX_QUEUE_FULL` if the TX _FIFO_ is 
+full or `SPI_FLAG_OK` if the data has been loaded into the _FIFO_.
+
+
+#### Verifying Readiness
+
+Ensure the _SPI Host IP_ is ready to receive commands:
+
+```c
+spi_tristate_e spi_get_ready(spi_host_t* spi);
+```
+
+- Returns `SPI_TRISTATE_TRUE` if ready, `SPI_TRISTATE_FALSE` if not, and 
+`SPI_TRISTATE_ERROR` if the spi pointer is `NULL`.
+
+Alternatively, you may wait for readiness:
+
+```c
+spi_return_flags_e spi_wait_for_ready(spi_host_t* spi);
+```
+
+#### Issuing Commands
+
+```c
+uint32_t spi_create_command(const spi_command_t command);
+
+spi_return_flags_e spi_set_command(spi_host_t* spi, uint32_t cmd_reg);
+```
+
+Issue commands by following these steps:
+
+1. **Create Command Word**: Call `spi_create_command` with the command structure.
+1. **Send Command**: Call `spi_set_command` with the generated command word.
+1. **Check for Errors**: `spi_set_command` returns `SPI_FLAG_SPEED_INVALID` for 
+invalid speed or `SPI_FLAG_NOT_READY` if not ready.
+
+
+#### Reading Received Data
+
+For RX or Bidirectional commands, read received data with:
+
+```c
+spi_return_flags_e spi_read_word(spi_host_t* spi, uint32_t* dst);
+```
+
+This function returns `SPI_FLAG_RX_QUEUE_EMPTY` if no words are available. Otherwise, 
+stores the read word in `uint32_t* dst`.
+
+```{note}
+There is no function to read single bytes from the RX _FIFO_ because the _SPI Host IP_ 
+only offers entire words to be read. The unused bytes (when the RX command length 
+parameter does not describe full words) will be zero-padded.
+```
+
+
+(hal-advanced-commands)=
+#### Advanced Commands
+
+For complex commands (e.g. TX followed by RX without deactivating the CS line, etc.), 
+use the `csaat` field to keep the _CS_ line active:
+
+- Set `csaat` to `true` to keep the _CS_ line active.
+- Repeat the command steps until the last _segment_, where `csaat` should be `false`.
+
+
+
+### SPI Host Status
+
+To retrieve the current status of the _SPI Host IP_, a structure and a function 
+are provided:
+
+```c
+typedef struct spi_status_s {
+    // TX queue depth (how many unsent words are in the FIFO)
+    uint8_t txqd        : 8;
+    // RX queue depth (how many unread words are in the FIFO)
+    uint8_t rxqd        : 8;
+    // CMD queue depth (how many unprocessed commands are in the FIFO)
+    uint8_t cmdqd       : 4;
+    // Indicates wether rxqd is above the RX Watermark
+    bool    rxwm        : 1;
+    // Not used
+    bool    __rsvd0     : 1;
+    // The endianness of the SPI Peripheral
+    bool    byteorder   : 1;
+    // Indicates if the SPI still still has more data to read but the RX FIFO is full
+    bool    rxstall     : 1;
+    // Indicates RX FIFO is empty
+    bool    rxempty     : 1;
+    // Indicates RX FIFO is full
+    bool    rxfull      : 1;
+    // Indicates wether txqd is below the TX Watermark
+    bool    txwm        : 1;
+    // Indicates if the SPI still has more data to send but the TX FIFO is empty
+    bool    txstall     : 1;
+    // Indicates TX FIFO is empty
+    bool    txempty     : 1;
+    // Indicates TX FIFO is full
+    bool    txfull      : 1;
+    // Indicates if the SPI peripheral is currently processing a command
+    bool    active      : 1;
+    // Indicates if the SPI peripheral is ready to receive more commands
+    bool    ready       : 1;
+} spi_status_t;
+
+const volatile spi_status_t* spi_get_status(spi_host_t* spi);
+```
+
+Calling this function provides read access to all the fields in `spi_status_t`, 
+mapped to the `STATUS` register of the _SPI Host_ device.
+
+If `spi_host_t* spi` is `NULL`, this function returns a `NULL` pointer.
+Check for `NULL` before accessing fields.
+
+
+### Interrupts
+
+#### Overview of Interrupts
+
+The SPI Host features two types of interrupts:
+
+- **Error Interrupts**: Triggered by specific error conditions.
+- **Event Interrupts**: Triggered by specific event conditions.
+
+To manage these interrupts, you can select which conditions trigger them and 
+then check the specific error/event in the interrupt handler.
+
+#### Interrupt Handling
+
+To use interrupts, first implement the _non-weak_ functions of the _weak_ functions 
+defined in the HAL. Each _SPI Host IP_ instance has its own _weak_ error handling 
+and event handling functions:
+
+For error interrupts:
+
+```c
+void spi_intr_handler_error_host(spi_error_e errors);   // For SPI Host 1
+void spi_intr_handler_error_host2(spi_error_e errors);  // For SPI Host 2
+void spi_intr_handler_error_flash(spi_error_e errors);  // For SPI Flash
+```
+
+For event interrupts:
+
+```c
+void spi_intr_handler_event_host(spi_event_e events);   // For SPI Host 1
+void spi_intr_handler_event_host2(spi_event_e events);  // For SPI Host 2
+void spi_intr_handler_event_flash(spi_event_e events);  // For SPI Flash
+```
+
+These handlers receive an `enum` value indicating the specific error or event 
+condition that triggered the interrupt.
+
+For error interrupts:
+
+```c
+typedef enum {
+    SPI_ERROR_NONE          = 0,
+    // Triggers error interrupt whenever a command is issued while busy.
+    SPI_ERROR_CMDBUSY       = (1 << SPI_HOST_ERROR_ENABLE_CMDBUSY_BIT),
+    // Triggers error interrupt whenever the TX FIFO overflows.
+    SPI_ERROR_OVERFLOW      = (1 << SPI_HOST_ERROR_ENABLE_OVERFLOW_BIT),
+    // Triggers error interrupt whenever there is a read from RXDATA but the RX 
+    // FIFO is empty. 
+    SPI_ERROR_UNDERFLOW     = (1 << SPI_HOST_ERROR_ENABLE_UNDERFLOW_BIT),
+    // Triggers error interrupt whenever a command is sent with invalid values for 
+    // COMMAND.SPEED or COMMAND.DIRECTION.
+    SPI_ERROR_CMDINVAL      = (1 << SPI_HOST_ERROR_ENABLE_CMDINVAL_BIT),
+    // Triggers error interrupt whenever a command is submitted, but CSID exceeds 
+    // NumCS.
+    SPI_ERROR_CSIDINVAL     = (1 << SPI_HOST_ERROR_ENABLE_CSIDINVAL_BIT),
+    // INDICATES that TLUL attempted to write to TXDATA with no bytes enabled.
+    // This error cannot be set (enabled or disabled).
+    // This error should never happen since it is the hardware that controls this.
+    SPI_ERROR_ACCESSINVAL   = (1 << SPI_HOST_ERROR_STATUS_ACCESSINVAL_BIT),
+    // All the above mentioned errors that can be set.
+    SPI_ERROR_IRQALL        = (1 << SPI_HOST_ERROR_ENABLE_CSIDINVAL_BIT+1) - 1,
+    // All the above mentioned errors.
+    SPI_ERROR_ALL           = (1 << SPI_HOST_ERROR_STATUS_ACCESSINVAL_BIT+1) - 1
+} spi_error_e;
+```
+
+For event interrupts:
+
+```c
+typedef enum {
+    SPI_EVENT_NONE      = 0,
+    // Triggers event when RX becomes full
+    SPI_EVENT_RXFULL    = (1 << SPI_HOST_EVENT_ENABLE_RXFULL_BIT),
+    // Triggers event when TX becomes empty
+    SPI_EVENT_TXEMPTY   = (1 << SPI_HOST_EVENT_ENABLE_TXEMPTY_BIT),
+    // Triggers event when RX goes above watermark
+    SPI_EVENT_RXWM      = (1 << SPI_HOST_EVENT_ENABLE_RXWM_BIT),
+    // Triggers event when TX falls below watermark
+    SPI_EVENT_TXWM      = (1 << SPI_HOST_EVENT_ENABLE_TXWM_BIT),
+    // Triggers event as soon as SPI Host IP is ready to receive more commands
+    SPI_EVENT_READY     = (1 << SPI_HOST_EVENT_ENABLE_READY_BIT),
+    // Triggers event as soon as SPI Host IP is not processing any command
+    SPI_EVENT_IDLE      = (1 << SPI_HOST_EVENT_ENABLE_IDLE_BIT),
+    // All the above mentioned events
+    SPI_EVENT_ALL       = (1 << SPI_HOST_EVENT_ENABLE_IDLE_BIT+1) - 1
+} spi_event_e;
+```
+
+```{attention}
+The `spi_event_e events` passed to the event handler does not represent the event 
+that _triggered_ the interrupt. Since the _SPI Host IP_ has no manner of determining
+the specific event that triggered the interrupt, the implemented workaround consists
+in reading the `STATUS` register to map the corresponding status to the related 
+event. Therefore, the `events` variable received by the handler functions is 
+actually the statuses mapped to `spi_event_e`.
+```
+
+##### Interrupt Acknowledgment
+
+After handling an interrupt, it must be acknowledged to the _SPI Host_.
+
+For event interrupts, the HAL handles acknowledgment automatically.
+
+For error interrupts, the user must acknowledge the error once resolved. The 
+_SPI Host_ will remain idle until the error is acknowledged. Use the following 
+function to acknowledge errors:
+
+```c
+spi_return_flags_e spi_acknowledge_errors(spi_host_t* spi);
+```
+
+#### Enabling Interrupts
+
+To enable or disable interrupts, use the following functions:
+
+```c
+// For Error Interrupts
+spi_return_flags_e spi_enable_error_intr(spi_host_t* spi, bool enable);
+
+// For Event Interrupts
+spi_return_flags_e spi_enable_evt_intr(spi_host_t* spi, bool enable);
+```
+
+These functions enable/disable the interrupts but do not specify the conditions 
+that trigger them. To set the conditions, use these functions:
+
+```c
+// For Error Conditions
+spi_return_flags_e spi_set_errors_enabled(spi_host_t* spi, spi_error_e errors, bool enable);
+
+// For Event Conditions
+spi_return_flags_e spi_set_events_enabled(spi_host_t* spi, spi_event_e events, bool enable);
+```
+
+- `spi_set_errors_enabled` returns `SPI_FLAG_ERROR_INVALID` if the provided `errors` 
+are not valid (note that `SPI_ERROR_ACCESSINVAL` and `SPI_ERROR_ALL` are
+**not valid**).
+
+- `spi_set_events_enabled` returns `SPI_FLAG_EVENT_INVALID` if the provided `events` 
+are not valid.
+
+When setting an error or event condition, the other conditions remain unaffected. 
+For instance, if `SPI_EVENT_RXWM` and `SPI_EVENT_TXWM` are enabled and you call 
+`spi_set_events_enabled` to enable `SPI_EVENT_IDLE`, both `SPI_EVENT_RXWM` and 
+`SPI_EVENT_TXWM` will remain enabled.
+
+```{tip}
+It is possible to enable/disable multiple `events` or `errors` simultaneously by 
+OR-ing the different `spi_error_e` or `spi_event_e` values.
+```
+
+
+
+## Using HAL Together With SDK
+
+While it is possible to use the HAL together with the SDK, there are important 
+considerations to be aware of. Also, consistency is key: do not mix SDK usage with HAL 
+usage within the same context. If you need to use both, clearly separate the 
+contexts in which each is used.
+
+### Interrupt Handling
+
+#### Event and Error Interrupts
+
+Since the SDK already implements the weak interrupt handlers of the HAL, it is 
+not possible to redefine handlers. This means that it is not possible to use any 
+interrupt from the HAL when using the SDK.
+
+Because the SDK uses interrupts to operate, it is **crucial not to change any 
+interrupt triggering configuration**. In any case, it would be pointless to modify 
+it since there is no way to use the interrupts.
+
+### Configuration Management
+
+#### Watermarks
+
+It is possible to modify the TX and RX watermarks using the HAL, but they will 
+not be implicitly reset by the SDK. Hence, if you modify any watermarks, they 
+should be reset if you want to use different watermarks when using the SDK.
+
+The SDK also provides functions to modify the watermarks. If setting the watermarks 
+for SDK usage, it is advised to set them with the SDK's functions rather than with 
+the HAL's functions because the SDK will also internally keep an instance of these 
+watermarks.
+
+#### Slave Configuration Options
+
+It is possible to change the configuration options for a particular _CSID_ using 
+the HAL, but, subsequently, the SDK will not reset the configuration if the same 
+SDK `spi_t` instance was used in the previous SDK transaction.
+
+For example, if you execute a transaction with an `spi_t` instance and then use HAL 
+functions to change the configuration options of the same _CSID_, the SDK will not 
+reset these options in subsequent transactions with the same `spi_t` instance. 
+Therefore, it is important to maintain consistency with configuration changes.
+
+### Transaction Management
+
+#### SPI Host Activeness
+
+Since the tracking of busyness by the SDK is managed internally, the `spi_get_state` 
+function of the SDK will not return `SPI_STATE_BUSY` if the _SPI Host IP_ is 
+processing a transaction that was executed through HAL functions.
+
+It is, anyway, impossible to issue transactions through SDK functions while the _SPI 
+Host IP_ is processing a transaction (whether issued by HAL or SDK), but it would 
+be useless to check the state of the device using the `spi_get_state` function of 
+the SDK.
+
+### Summary of Key Points
+
+- **Consistency**: Do not mix SDK and HAL usage in the same context. Clearly 
+separate their usage.
+
+- **Interrupts**: Do not alter interrupt triggering conditions; SDK relies on 
+its interrupt handlers.
+
+- **Watermarks**: Use SDK functions to modify watermarks when using SDK to 
+maintain consistency.
+
+- **Configuration**: Be consistent with configuration changes, especially when 
+switching between HAL and SDK.
+
+- **Activeness**: The `spi_get_state` function of the SDK will not reflect 
+transactions initiated by HAL functions.
+
+
+## 😎 X-pert Zone
+
+Another option for speeding up transaction processing is to use the registers of 
+the _SPI Host_ directly. However, this is not recommended unless you have a strong 
+understanding of the process. For detailed information on the operation of the 
+device, please refer to the following documentation on the _SPI Host_:
+[SPI Host: Theory of Operation](https://opentitan.org/book/hw/ip/spi_host/doc/theory_of_operation.html).
+
+To access the registers of the _SPI Host_ directly, the `spi_host` structure is 
+defined in `spi_host_structs.h`, along with a pointer variable for each 
+_SPI Host IP_, defined as follows:
+
+- `spi_host1_peri ((volatile spi_host *) SPI_HOST_START_ADDRESS)`
+- `spi_host2_peri ((volatile spi_host *) SPI2_START_ADDRESS)`
+- `spi_flash_peri ((volatile spi_host *) SPI_FLASH_START_ADDRESS)`
+
+Below is an example of implementing an SPI _Standard_ speed transaction with a 
+_W25Q128JW_ Flash slave device using this method:
+
+```c
+#include "bitfield.h"
+#include "soc_ctrl_structs.h"
+#include "spi_host_regs.h"
+#include "spi_host_structs.h"
+
+// MCU frequency
+#define SYS_FREQ (soc_ctrl_peri->SYSTEM_FREQUENCY_HZ)
+
+// Flash paramters
+#define FLASH_MAX_FREQ  (133*1000*1000)
+#define FLASH_CSN_TIMES 0x0F
+#define FLASH_POL       0
+#define FLASH_PHA       0
+#define FC_RD           0x03 /* Flash Read Data Command */
+
+// SPI transaction parameters
+#define SPI_TX  0x02
+#define SPI_RX  0x01
+#define SPI_STD 0x00
+
+#define LEN_B = 4096 /* Amount of bytes of data to read from flash */
+
+#define ADDRESS = 0x00800000 /* Flash address where to read */
+
+int main(int argc, char *argv[])
+{
+    // Initialize RX buffer
+    uint8_t dest_buff[LEN_B] = {0};
+
+    // Compute frequency of SPI communication based on slave and MCU frequency
+    uint16_t clk_div = 0;
+    if (FLASH_MAX_FREQ < SYS_FREQ / 2) {
+        clk_div = (SYS_FREQ / FLASH_MAX_FREQ - 2) / 2;
+        if (SYS_FREQ / (2 * clk_div + 2) > FLASH_MAX_FREQ) clk_div++;
+    }
+    // Set slave configuration options
+    spi_flash_peri->CONFIGOPTS0 = (FLASH_CSN_TIMES << SPI_HOST_CONFIGOPTS_0_CSNIDLE_0_OFFSET) |
+                                  (FLASH_CSN_TIMES << SPI_HOST_CONFIGOPTS_0_CSNLEAD_0_OFFSET) |
+                                  (FLASH_CSN_TIMES << SPI_HOST_CONFIGOPTS_0_CSNTRAIL_0_OFFSET) |
+                                  (FLASH_PHA       << SPI_HOST_CONFIGOPTS_0_CPHA_0_BIT) |
+                                  (FLASH_POL       << SPI_HOST_CONFIGOPTS_0_CPOL_0_BIT) |
+                                  (clk_div         << SPI_HOST_CONFIGOPTS_0_CLKDIV_0_OFFSET);
+
+    // Enable SPI Host device and output
+    bitfield_write(spi_flash_peri->CONTROL, BIT_MASK_1, SPI_HOST_CONTROL_SPIEN_BIT,     true);
+    bitfield_write(spi_flash_peri->CONTROL, BIT_MASK_1, SPI_HOST_CONTROL_OUTPUT_EN_BIT, true);
+
+    // Set command to send to slave
+    spi_flash_peri->TXDATA = ((bitfield_byteswap32(ADDRESS & 0x00ffffff)) | FC_RD);
+    // Set CSID line where slave is connected
+    spi_flash_peri->CSID = 0;
+    // Wait for SPI Host to be ready before setting command
+    while (!bitfield_read(spi_flash_peri->STATUS, BIT_MASK_1, SPI_HOST_STATUS_READY_BIT));
+    // Set command
+    spi_flash_peri->COMMAND = (SPI_TX   << SPI_HOST_COMMAND_DIRECTION_OFFSET) |
+                              (SPI_STD  << SPI_HOST_COMMAND_SPEED_OFFSET) |
+                              (0x01     << SPI_HOST_COMMAND_CSAAT_BIT) |
+                              (0x03     << SPI_HOST_COMMAND_LEN_OFFSET);
+    // Wait for SPI Host to be ready before setting command
+    while (!bitfield_read(spi_flash_peri->STATUS, BIT_MASK_1, SPI_HOST_STATUS_READY_BIT));
+    // Set command
+    spi_flash_peri->COMMAND = (SPI_RX   << SPI_HOST_COMMAND_DIRECTION_OFFSET) |
+                              (SPI_STD  << SPI_HOST_COMMAND_SPEED_OFFSET) |
+                              (0x00     << SPI_HOST_COMMAND_CSAAT_BIT) |
+                              (LEN_B-1  << SPI_HOST_COMMAND_LEN_OFFSET);
+
+    // Setup RX word counter and set watermark
+    uint32_t rxcnt = 0;
+    const uint8_t watermark = 48;
+    bitfield_write(spi_flash_peri->CONTROL, SPI_HOST_CONTROL_RX_WATERMARK_MASK, 
+                   SPI_HOST_CONTROL_RX_WATERMARK_OFFSET, watermark);
+
+    // While the SPI Host is active (i.e. still processing transaction)
+    while (bitfield_read(spi_flash_peri->STATUS, BIT_MASK_1, SPI_HOST_STATUS_ACTIVE_BIT))
+    {
+        // If there are still more words to be read than watermark, then wait
+        // for RX watermark to go high
+        if ((LEN_B/4) - rxcnt > watermark)
+            while (!bitfield_read(spi_flash_peri->STATUS, BIT_MASK_1, 
+                                                          SPI_HOST_STATUS_RXWM_BIT))
+        // Needed because too fast otherwise
+        asm volatile ("nop");
+        // Just read as much as possible (but no more than watermark words)
+        for (int i = 0; i < watermark; i++)
+        {
+            // If there are words in the RX FIFO read them
+            if (bitfield_read(spi_flash_peri->STATUS, SPI_HOST_STATUS_RXQD_MASK, 
+                                                      SPI_HOST_STATUS_RXQD_OFFSET))
+            {
+                dest_buff[rxcnt] = spi_flash_peri->RXDATA;
+                rxcnt++;
+            }
+        }
+    }
+    // Read the remaining words if there are any
+    while (bitfield_read(spi_flash_peri->STATUS, SPI_HOST_STATUS_RXQD_MASK, 
+                                                 SPI_HOST_STATUS_RXQD_OFFSET))
+    {
+        dest_buff[rxcnt] = spi_flash_peri->RXDATA;
+        rxcnt++;
+    }
+}
+```
+
+```{note}
+There are practically no sanity checks performed in this example in order to keep it
+as simple as possible. In a practical application there should of course be sanity
+checks wherever needed.
+```
+
+
+## Performance Analysis
+
+A performance testing was carried out utilizing the _EPFL Programmer_, which includes
+a _W25Q128JW_ flash memory, and the _PYNQ-Z2_ FPGA. The 
+[SPI Flash Loading Boot Procedure](/How_to/ExecuteFromFlash.html#spi-flash-loading-boot-procedure)
+was employed for all tests.
+
+The test application used the 
+[Clock Cycle Counter `mcycle(h)`](https://ibex-core.readthedocs.io/en/latest/03_reference/performance_counters.html) 
+of X-HEEP, recording time via the `CSR_REG_MCYCLE` register. The test tracked the 
+duration to create and execute a transaction of various command segments with the 
+SDK, where each transaction involved reading 4KiB from the _W25Q128JW_ flash device. 
+This read operation was repeated 500 times to obtain an average.
+
+The exact same procedure was applied to the HAL and the _direct register_ method, 
+which involves direct manipulation of _SPI Host_ registers without using the HAL or 
+SDK. The tests were conducted at both _Standard_ SPI and _Quad_ SPI speeds. For 
+accurate comparison, only essential steps for transaction execution were implemented, 
+avoiding as many sanity checks as possible to maximize performance.
+
+Results indicate that at _Standard_ SPI speed, _direct register_ manipulation was 
+slightly faster than the HAL by approximately 0.8%. At _Quad_ SPI speed, _direct register_ 
+manipulation showed a significant performance gain, being about 18.6% faster than 
+the HAL. Comparing the HAL to the SDK, the HAL was about 1% faster at _Quad_ speed 
+and 0.8% faster at _Standard_ speed.
+
+Exact numbers are provided in the following tables.
+
+```{table}
+:widths: auto
+:align: center
+
+|          | SDK        | HAL        | Register   |
+| :------: | :--------: | :--------: | :--------: |
+| **Standard** | 4472.00 μs | 4437.40 μs | 4402.07 μs |
+| **Quad**     | 1970.00 μs | 1951.40 μs | 1588.00 μs |
+```
+
+To illustrate these numbers rather in percentage of change, the following table 
+shows the speed gain(-) and the speed loss(+) when changing method for a Quad speed 
+read. For example, when switching from the _direct register_ method to the SDK, 
+there is a
+
+```{math}
+\frac{SDK - Register}{Register}\ =\ 24.055\%
+```
+
+change, which means 24.055% slower.
+
+```{table}
+:widths: auto
+:align: center
+
+|          | SDK      | HAL      | Register |
+| :------: | :------: | :------: | :------: |
+| **SDK**      | 0%       | 0.953%   | 24.055%  |
+| **HAL**      | -0.944%  | 0%       | 22.884%  |
+| **Register** | -19.391% | -18.623% | 0%       |
+```
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/Timer.md b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/Timer.md
new file mode 100644
index 00000000..052faf0d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/Timer.md
@@ -0,0 +1,107 @@
+
+# Timer SDK
+
+This SDK provides utilities for execution time measurements using HW timers. It includes functions to start, stop, reset, and configure timers, as well as to enable timer interrupts and measure elapsed time.
+
+## Usage
+
+The SDK provides a set of functions to interact with the HW Timer for various timing operations.
+
+### Initialize Timer for Counting Cycles
+
+This function configures the counter at the running clock frequency to count the number of clock cycles. Call this function before any of the other timer SDK functions.
+
+```c
+void timer_cycles_init();
+```
+
+### Start Timer
+
+Start the HW timer.
+
+```c
+void timer_start();
+```
+
+### Get Current Timer Value
+
+Retrieve the current value of the HW timer without stopping it.
+
+```c
+uint32_t timer_get_cycles();
+```
+
+### Complete timer reset
+
+Completely resets the HW counter, disabling all IRQs, counters, and comparators.
+```c
+void timer_reset();
+```
+ 
+### Stop and Reset Timer
+
+Retrieve the current value of the HW timer and stop it.
+
+```c
+uint32_t timer_stop();
+```
+
+### Set Timer Threshold
+
+Set the timer to go off once the counter value reaches the specified threshold. If the timer interrupts and the timer IRQ have been enabled, when the timer reaches that value an interrupt will be called.
+
+```c
+void timer_arm_set(uint32_t threshold);
+```
+
+### Set Timer Threshold and Start
+
+Set the timer to go off once the counter value reaches the specified threshold, and start the timer. If the timer interrupts and the timer IRQ have been enabled, when the timer reaches that value an interrupt will be called.
+
+```c
+void timer_arm_start(uint32_t threshold);
+```
+
+### Enable Timer IRQ
+
+Enable the timer interrupt request.
+
+```c
+void timer_irq_enable();
+```
+
+### Clear Timer IRQ
+
+Clear the timer interrupt request.
+
+```c
+void timer_irq_clear();
+```
+
+### Enable Timer Machine-level Interrupts
+
+Enable the timer machine-level interrupts for the X-Heep platform.
+
+```c
+void enable_timer_interrupt();
+```
+
+### Wait for Microseconds
+
+Block execution for a specified number of microseconds. This function is not precise for small numbers of microseconds. Enable timer interrupts with `enable_timer_interrupt()` before using this function.
+
+```c
+void timer_wait_us(uint32_t ms);
+```
+
+### Get Execution Time in Microseconds
+
+Get the time taken to execute a certain number of cycles, returned as a float representing the time in microseconds.
+
+```c
+float get_time_from_cycles(uint32_t cycles);
+```
+
+## Example Usage
+
+An example of utilization of the timer SDK can be found in `sw/applications/example_timer_sdk/main.c`.
diff --git a/hw/vendor/esl_epfl_x_heep/ides/img/build_screenshot.png b/hw/vendor/esl_epfl_x_heep/docs/source/_static/ides/build_screenshot.png
similarity index 100%
rename from hw/vendor/esl_epfl_x_heep/ides/img/build_screenshot.png
rename to hw/vendor/esl_epfl_x_heep/docs/source/_static/ides/build_screenshot.png
diff --git a/hw/vendor/esl_epfl_x_heep/ides/img/debug_screenshot.png b/hw/vendor/esl_epfl_x_heep/docs/source/_static/ides/debug_screenshot.png
similarity index 100%
rename from hw/vendor/esl_epfl_x_heep/ides/img/debug_screenshot.png
rename to hw/vendor/esl_epfl_x_heep/docs/source/_static/ides/debug_screenshot.png
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/conf.py b/hw/vendor/esl_epfl_x_heep/docs/source/conf.py
index c9f6eaab..44ce6b68 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/conf.py
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/conf.py
@@ -4,6 +4,10 @@
 #
 # Author: Embedded Systems Laboratory (EPFL)
 
+import os
+import sys
+sys.path.insert(0, os.path.abspath("../../util"))
+
 project = 'X-HEEP'
 copyright = '2023, EPFL'
 author = 'ESL'
@@ -17,9 +21,12 @@
     'sphinx.ext.autodoc',
     'sphinx.ext.autosummary',
     'sphinx.ext.intersphinx',
+    'sphinxcontrib.apidoc',
     'myst_parser',
 ]
 
+html_static_path = ['_static']
+
 source_suffix = ['.rst', '.md']
 
 intersphinx_mapping = {
@@ -33,3 +40,7 @@
 html_theme = 'sphinx_rtd_theme'
 
 epub_show_urls = 'footnote'
+
+apidoc_module_dir = '../../util/x_heep_gen'
+apidoc_output_dir = 'Configuration/generated'
+apidoc_separate_modules = True
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/block_diagrams/example_adc.svg b/hw/vendor/esl_epfl_x_heep/docs/source/images/example_adc.svg
similarity index 100%
rename from hw/vendor/esl_epfl_x_heep/block_diagrams/example_adc.svg
rename to hw/vendor/esl_epfl_x_heep/docs/source/images/example_adc.svg
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/images/x-heep-outline.png b/hw/vendor/esl_epfl_x_heep/docs/source/images/x-heep-outline.png
new file mode 100644
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diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/images/xheep_diagram.png b/hw/vendor/esl_epfl_x_heep/docs/source/images/xheep_diagram.png
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diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/index.rst b/hw/vendor/esl_epfl_x_heep/docs/source/index.rst
index e3968a3f..a0d4c746 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/index.rst
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/index.rst
@@ -1,6 +1,11 @@
 X-HEEP
 ======
 
+.. image:: images/x-heep-outline.png
+   :width: 600
+
+
+
 ``X-HEEP`` (eXtendable Heterogeneous Energy-Efficient Platform) is a RISC-V microcontroller described in SystemVerilog that can be configured to target small and tiny platforms as well as extended to support accelerators.
 The cool thing about X-HEEP is that we provide a simple customizable MCU, so CPUs, common peripherals, memories, etc. so that you can extend it with your own accelerator without modifying the MCU, but just instantiating it in your design.
 By doing so, you inherit an IP capable of booting RTOS (such as FreeRTOS) with the whole FW stack, including HAL drivers and SDK, and you can focus on building your special HW or APP supported by the microcontroller.
@@ -23,7 +28,7 @@ The CPU subsystem is based on the `RISC-V lowRISC Ibex <https://github.com/lowRI
 Memory banks domains
 ^^^^^^^^^^^^^^^^^^^^
 
-The memory subsystem is divided into 4 32KB banks of memory used to both program instructions and data. Banks are connected to the bus with dedicated interfaces and this allows you to access multiple banks at the same time without conflicts. Each bank can be individually clock-gated or set in retention to save dynamic and leakage power, respectively. Moreover, the memory subsystem is thought to be fine-grained power-gated, switching off each bank that is not needed.
+The memory subsystem is divided into multiple banks that can have different sizes of memory used to both program instructions and data. Banks are connected to the bus with dedicated interfaces and this allows you to access multiple banks at the same time without conflicts. Each bank can be individually clock-gated or set in retention to save dynamic and leakage power, respectively. Moreover, the memory subsystem is thought to be fine-grained power-gated, switching off each bank that is not needed.
 
 Peripheral subsystem domain
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -76,4 +81,12 @@ Index
    :glob:
    :caption: Peripherals
 
-   ./Peripherals/*
\ No newline at end of file
+   ./Peripherals/*
+
+.. toctree::
+   :maxdepth: 5
+   :glob:
+   :caption: Configuration
+
+   ./Configuration/*
+   ./Configuration/generated/modules.rst
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/hw/asic/sky130/sram_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/asic/sky130/sram_wrapper.sv
index 68e030f4..722cf5f3 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/asic/sky130/sram_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/asic/sky130/sram_wrapper.sv
@@ -21,6 +21,10 @@ module sram_wrapper #(
     output logic [         31:0] rdata_o   // read data
 );
 
+  if (NumWords != 8192) begin
+    $error("Bank size not implemented.");
+  end
+
   logic [8-1:0] unused;
   logic [8-1:0] cs;
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
index 504fed22..dd9246df 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
@@ -5,6 +5,7 @@
 module ao_peripheral_subsystem
   import obi_pkg::*;
   import reg_pkg::*;
+  import power_manager_pkg::*;
 #(
     //do not touch these parameters
     parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
@@ -36,42 +37,25 @@ module ao_peripheral_subsystem
     input  logic [                        3:0] spi_flash_sd_i,
 
     // OpenTitan SPI interface to external spi slaves
-    output logic                               spi_sck_o,
-    output logic                               spi_sck_en_o,
-    output logic [spi_host_reg_pkg::NumCS-1:0] spi_csb_o,
-    output logic [spi_host_reg_pkg::NumCS-1:0] spi_csb_en_o,
-    output logic [                        3:0] spi_sd_o,
-    output logic [                        3:0] spi_sd_en_o,
-    input  logic [                        3:0] spi_sd_i,
-    output logic                               spi_intr_event_o,
-    output logic                               spi_flash_intr_event_o,
+    input logic spi_rx_valid_i,
+    input logic spi_tx_ready_i,
+
+    output logic spi_flash_intr_event_o,
 
     // POWER MANAGER
     input logic [31:0] intr_i,
     input logic [NEXT_INT_RND-1:0] intr_vector_ext_i,
     input logic core_sleep_i,
-    output logic cpu_subsystem_powergate_switch_no,
-    input logic cpu_subsystem_powergate_switch_ack_ni,
-    output logic cpu_subsystem_powergate_iso_no,
-    output logic cpu_subsystem_rst_no,
-    output logic peripheral_subsystem_powergate_switch_no,
-    input logic peripheral_subsystem_powergate_switch_ack_ni,
-    output logic peripheral_subsystem_powergate_iso_no,
-    output logic peripheral_subsystem_rst_no,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_no,
-    input  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack_ni,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso_no,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_set_retentive_no,
-    output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_no,
-    input logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_ack_ni,
-    output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_iso_no,
-    output logic [EXT_DOMAINS_RND-1:0] external_subsystem_rst_no,
-    output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no,
-
-    // Clock gating signals
-    output logic peripheral_subsystem_clkgate_en_no,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_clkgate_en_no,
-    output logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_no,
+
+    output power_manager_out_t cpu_subsystem_pwr_ctrl_o,
+    output power_manager_out_t peripheral_subsystem_pwr_ctrl_o,
+    output power_manager_out_t memory_subsystem_pwr_ctrl_o[core_v_mini_mcu_pkg::NUM_BANKS-1:0],
+    output power_manager_out_t external_subsystem_pwr_ctrl_o[EXT_DOMAINS_RND-1:0],
+
+    input power_manager_in_t cpu_subsystem_pwr_ctrl_i,
+    input power_manager_in_t peripheral_subsystem_pwr_ctrl_i,
+    input power_manager_in_t memory_subsystem_pwr_ctrl_i[core_v_mini_mcu_pkg::NUM_BANKS-1:0],
+    input power_manager_in_t external_subsystem_pwr_ctrl_i[EXT_DOMAINS_RND-1:0],
 
     // RV TIMER
     output logic rv_timer_0_intr_o,
@@ -120,8 +104,10 @@ module ao_peripheral_subsystem
     output reg_req_t ext_peripheral_slave_req_o,
     input  reg_rsp_t ext_peripheral_slave_resp_i,
 
-    input logic ext_dma_slot_tx_i,
-    input logic ext_dma_slot_rx_i
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i,
+
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -144,8 +130,6 @@ module ao_peripheral_subsystem
 
   logic use_spimemio;
 
-  logic spi_rx_valid;
-  logic spi_tx_ready;
   logic spi_flash_rx_valid;
   logic spi_flash_tx_ready;
 
@@ -283,31 +267,6 @@ module ao_peripheral_subsystem
       .spi_flash_tx_ready_o(spi_flash_tx_ready)
   );
 
-  spi_host #(
-      .reg_req_t(reg_pkg::reg_req_t),
-      .reg_rsp_t(reg_pkg::reg_rsp_t)
-  ) spi_host_dma_i (
-      .clk_i,
-      .rst_ni,
-      .reg_req_i(ao_peripheral_slv_req[core_v_mini_mcu_pkg::SPI_HOST_IDX]),
-      .reg_rsp_o(ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI_HOST_IDX]),
-      .alert_rx_i(),
-      .alert_tx_o(),
-      .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
-      .passthrough_o(),
-      .cio_sck_o(spi_sck_o),
-      .cio_sck_en_o(spi_sck_en_o),
-      .cio_csb_o(spi_csb_o),
-      .cio_csb_en_o(spi_csb_en_o),
-      .cio_sd_o(spi_sd_o),
-      .cio_sd_en_o(spi_sd_en_o),
-      .cio_sd_i(spi_sd_i),
-      .rx_valid_o(spi_rx_valid),
-      .tx_ready_o(spi_tx_ready),
-      .intr_error_o(),
-      .intr_spi_event_o(spi_intr_event_o)
-  );
-
   power_manager #(
       .reg_req_t(reg_pkg::reg_req_t),
       .reg_rsp_t(reg_pkg::reg_rsp_t)
@@ -319,26 +278,14 @@ module ao_peripheral_subsystem
       .intr_i,
       .ext_irq_i(intr_vector_ext_i),
       .core_sleep_i,
-      .cpu_subsystem_powergate_switch_no,
-      .cpu_subsystem_powergate_switch_ack_ni,
-      .cpu_subsystem_powergate_iso_no,
-      .cpu_subsystem_rst_no,
-      .peripheral_subsystem_powergate_switch_no,
-      .peripheral_subsystem_powergate_switch_ack_ni,
-      .peripheral_subsystem_powergate_iso_no,
-      .peripheral_subsystem_rst_no,
-      .memory_subsystem_banks_powergate_switch_no,
-      .memory_subsystem_banks_powergate_switch_ack_ni,
-      .memory_subsystem_banks_powergate_iso_no,
-      .memory_subsystem_banks_set_retentive_no,
-      .external_subsystem_powergate_switch_no,
-      .external_subsystem_powergate_switch_ack_ni,
-      .external_subsystem_powergate_iso_no,
-      .external_subsystem_rst_no,
-      .external_ram_banks_set_retentive_no,
-      .peripheral_subsystem_clkgate_en_no,
-      .memory_subsystem_clkgate_en_no,
-      .external_subsystem_clkgate_en_no
+      .cpu_subsystem_pwr_ctrl_o,
+      .peripheral_subsystem_pwr_ctrl_o,
+      .memory_subsystem_pwr_ctrl_o,
+      .external_subsystem_pwr_ctrl_o,
+      .cpu_subsystem_pwr_ctrl_i,
+      .peripheral_subsystem_pwr_ctrl_i,
+      .memory_subsystem_pwr_ctrl_i,
+      .external_subsystem_pwr_ctrl_i
   );
 
   reg_to_tlul #(
@@ -367,23 +314,33 @@ module ao_peripheral_subsystem
       .intr_timer_expired_1_0_o(rv_timer_1_intr_o)
   );
 
-  parameter DMA_TRIGGER_SLOT_NUM = 7;
-  logic [DMA_TRIGGER_SLOT_NUM-1:0] dma_trigger_slots;
-  assign dma_trigger_slots[0] = spi_rx_valid;
-  assign dma_trigger_slots[1] = spi_tx_ready;
-  assign dma_trigger_slots[2] = spi_flash_rx_valid;
-  assign dma_trigger_slots[3] = spi_flash_tx_ready;
-  assign dma_trigger_slots[4] = i2s_rx_valid_i;
-  assign dma_trigger_slots[5] = ext_dma_slot_tx_i;
-  assign dma_trigger_slots[6] = ext_dma_slot_rx_i;
-
-  dma #(
-      .reg_req_t (reg_pkg::reg_req_t),
-      .reg_rsp_t (reg_pkg::reg_rsp_t),
-      .obi_req_t (obi_pkg::obi_req_t),
+  parameter DMA_GLOBAL_TRIGGER_SLOT_NUM = 5;
+  parameter DMA_EXT_TRIGGER_SLOT_NUM = core_v_mini_mcu_pkg::DMA_CH_NUM * 2;
+
+  logic [DMA_GLOBAL_TRIGGER_SLOT_NUM-1:0] dma_global_trigger_slots;
+  logic [DMA_EXT_TRIGGER_SLOT_NUM-1:0] dma_ext_trigger_slots;
+
+  assign dma_global_trigger_slots[0] = spi_rx_valid_i;
+  assign dma_global_trigger_slots[1] = spi_tx_ready_i;
+  assign dma_global_trigger_slots[2] = spi_flash_rx_valid;
+  assign dma_global_trigger_slots[3] = spi_flash_tx_ready;
+  assign dma_global_trigger_slots[4] = i2s_rx_valid_i;
+
+  generate
+    for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_CH_NUM; i++) begin : dma_trigger_slots_gen
+      assign dma_ext_trigger_slots[2*i]   = ext_dma_slot_tx_i[i];
+      assign dma_ext_trigger_slots[2*i+1] = ext_dma_slot_rx_i[i];
+    end
+  endgenerate
+
+  dma_subsystem #(
+      .reg_req_t(reg_pkg::reg_req_t),
+      .reg_rsp_t(reg_pkg::reg_rsp_t),
+      .obi_req_t(obi_pkg::obi_req_t),
       .obi_resp_t(obi_pkg::obi_resp_t),
-      .SLOT_NUM  (DMA_TRIGGER_SLOT_NUM)
-  ) dma_i (
+      .GLOBAL_SLOT_NUM(DMA_GLOBAL_TRIGGER_SLOT_NUM),
+      .EXT_SLOT_NUM(DMA_EXT_TRIGGER_SLOT_NUM)
+  ) dma_subsystem_i (
       .clk_i,
       .rst_ni,
       .reg_req_i(ao_peripheral_slv_req[core_v_mini_mcu_pkg::DMA_IDX]),
@@ -394,7 +351,9 @@ module ao_peripheral_subsystem
       .dma_write_ch0_resp_i,
       .dma_addr_ch0_req_o,
       .dma_addr_ch0_resp_i,
-      .trigger_slot_i(dma_trigger_slots),
+      .global_trigger_slot_i(dma_global_trigger_slots),
+      .ext_trigger_slot_i(dma_ext_trigger_slots),
+      .ext_dma_stop_i(ext_dma_stop_i),
       .dma_done_intr_o(dma_done_intr_o),
       .dma_window_intr_o(dma_window_intr_o)
   );
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
index 45f21d2c..4cfb3d9d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
@@ -11,10 +11,12 @@ module core_v_mini_mcu
     parameter ZFINX = 0,
     parameter EXT_XBAR_NMASTER = 0,
     parameter X_EXT = 0,  // eXtension interface in cv32e40x
+    parameter EXT_HARTS = 0,
     //do not touch these parameters
     parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
     parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
-    parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT
+    parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT,
+    parameter EXT_HARTS_RND = EXT_HARTS == 0 ? 1 : EXT_HARTS
 ) (
 
     input logic rst_ni,
@@ -297,37 +299,45 @@ module core_v_mini_mcu
     output obi_req_t  ext_dma_addr_ch0_req_o,
     input  obi_resp_t ext_dma_addr_ch0_resp_i,
 
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
+
     output reg_req_t ext_peripheral_slave_req_o,
     input  reg_rsp_t ext_peripheral_slave_resp_i,
 
+    output logic [EXT_HARTS_RND-1:0] ext_debug_req_o,
+    output logic ext_debug_reset_no,
+
     input logic [NEXT_INT_RND-1:0] intr_vector_ext_i,
 
+    //power manager exposed to top level
+    //signals are unrolled to easy EDA tools
     output logic cpu_subsystem_powergate_switch_no,
     input logic cpu_subsystem_powergate_switch_ack_ni,
     output logic peripheral_subsystem_powergate_switch_no,
     input logic peripheral_subsystem_powergate_switch_ack_ni,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_no,
-    input  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack_ni,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_no,
     input logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_ack_ni,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_iso_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_rst_no,
+    output logic ext_cpu_subsystem_rst_no,
     output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_no,
 
     output logic [31:0] exit_value_o,
 
-    input logic ext_dma_slot_tx_i,
-    input logic ext_dma_slot_rx_i
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
   import cv32e40p_apu_core_pkg::*;
+  import power_manager_pkg::*;
 
   localparam NUM_BYTES = core_v_mini_mcu_pkg::MEM_SIZE;
   localparam DM_HALTADDRESS = core_v_mini_mcu_pkg::DEBUG_START_ADDRESS + 32'h00000800; //debug rom code (section .text in linker) starts at 0x800
 
   localparam JTAG_IDCODE = 32'h10001c05;
+  localparam NRHARTS = EXT_HARTS + 1;  //external harts + single hart core-v-mini-mcu
   localparam BOOT_ADDR = core_v_mini_mcu_pkg::BOOTROM_START_ADDRESS;
   localparam NUM_MHPMCOUNTERS = 1;
 
@@ -369,7 +379,7 @@ module core_v_mini_mcu
   // signals to debug unit
   logic debug_core_req;
   logic debug_reset_n;
-
+  logic [NRHARTS-1:0] debug_req;
   // core
   logic core_sleep;
 
@@ -391,24 +401,73 @@ module core_v_mini_mcu
   logic [31:0] intr;
   logic [14:0] fast_intr;
 
-  // Power manager
-  logic cpu_subsystem_powergate_iso_n;
+  //Power manager signals
+  power_manager_out_t cpu_subsystem_pwr_ctrl_out;
+  power_manager_out_t peripheral_subsystem_pwr_ctrl_out;
+  power_manager_out_t memory_subsystem_pwr_ctrl_out[core_v_mini_mcu_pkg::NUM_BANKS-1:0];
+  power_manager_out_t external_subsystem_pwr_ctrl_out[EXT_DOMAINS_RND-1:0];
+
+  power_manager_in_t cpu_subsystem_pwr_ctrl_in;
+  power_manager_in_t peripheral_subsystem_pwr_ctrl_in;
+  power_manager_in_t memory_subsystem_pwr_ctrl_in[core_v_mini_mcu_pkg::NUM_BANKS-1:0];
+  power_manager_in_t external_subsystem_pwr_ctrl_in[EXT_DOMAINS_RND-1:0];
+
   logic cpu_subsystem_rst_n;
-  logic peripheral_subsystem_powergate_iso_n;
-  logic peripheral_subsystem_rst_n;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso_n;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_set_retentive_n;
+  logic cpu_subsystem_powergate_iso_n;
 
-  // Clock gating signals
+  logic peripheral_subsystem_rst_n;
+  logic peripheral_subsystem_powergate_iso_n;
   logic peripheral_subsystem_clkgate_en_n;
+
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_n;
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack_n;
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_set_retentive_n;
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso_n;
   logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_clkgate_en_n;
 
+  //pwrgate exposed outside for UPF sim flow and switch cells
+  assign cpu_subsystem_powergate_switch_no = cpu_subsystem_pwr_ctrl_out.pwrgate_en_n;
+  assign cpu_subsystem_pwr_ctrl_in.pwrgate_ack_n = cpu_subsystem_powergate_switch_ack_ni;
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign cpu_subsystem_powergate_iso_n = cpu_subsystem_pwr_ctrl_out.isogate_en_n;
+  assign cpu_subsystem_rst_n = cpu_subsystem_pwr_ctrl_out.rst_n;
+
+  //pwrgate exposed both outside for UPF sim flow
+  assign peripheral_subsystem_powergate_switch_no = peripheral_subsystem_pwr_ctrl_out.pwrgate_en_n;
+  assign peripheral_subsystem_pwr_ctrl_in.pwrgate_ack_n  = peripheral_subsystem_powergate_switch_ack_ni;
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign peripheral_subsystem_powergate_iso_n = peripheral_subsystem_pwr_ctrl_out.isogate_en_n;
+  assign peripheral_subsystem_rst_n = peripheral_subsystem_pwr_ctrl_out.rst_n;
+  assign peripheral_subsystem_clkgate_en_n = peripheral_subsystem_pwr_ctrl_out.clkgate_en_n;
+
+  assign memory_subsystem_banks_powergate_switch_n[0] = memory_subsystem_pwr_ctrl_out[0].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[0].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[0];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[0] = memory_subsystem_pwr_ctrl_out[0].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[0] = memory_subsystem_pwr_ctrl_out[0].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[0] = memory_subsystem_pwr_ctrl_out[0].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[1] = memory_subsystem_pwr_ctrl_out[1].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[1].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[1];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[1] = memory_subsystem_pwr_ctrl_out[1].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[1] = memory_subsystem_pwr_ctrl_out[1].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[1] = memory_subsystem_pwr_ctrl_out[1].clkgate_en_n;
+
+  for (genvar i = 0; i < EXT_DOMAINS_RND; i = i + 1) begin
+    assign external_subsystem_powergate_switch_no[i]        = external_subsystem_pwr_ctrl_out[i].pwrgate_en_n;
+    assign external_subsystem_powergate_iso_no[i] = external_subsystem_pwr_ctrl_out[i].isogate_en_n;
+    assign external_subsystem_rst_no[i] = external_subsystem_pwr_ctrl_out[i].rst_n;
+    assign external_ram_banks_set_retentive_no[i]           = external_subsystem_pwr_ctrl_out[i].retentive_en_n;
+    assign external_subsystem_clkgate_en_no[i] = external_subsystem_pwr_ctrl_out[i].clkgate_en_n;
+    assign external_subsystem_pwr_ctrl_in[i].pwrgate_ack_n = external_subsystem_powergate_switch_ack_ni[i];
+  end
+
   // DMA
   logic dma_done_intr;
   logic dma_window_intr;
 
   // SPI
-  logic spi_flash_intr, spi_intr;
+  logic spi_flash_intr, spi_intr, spi_rx_valid, spi_tx_ready;
 
   // GPIO
   logic [31:8] gpio_in;
@@ -479,6 +538,7 @@ module core_v_mini_mcu
   );
 
   debug_subsystem #(
+      .NRHARTS    (NRHARTS),
       .JTAG_IDCODE(JTAG_IDCODE)
   ) debug_subsystem_i (
       .clk_i,
@@ -488,7 +548,7 @@ module core_v_mini_mcu
       .jtag_trst_ni,
       .jtag_tdi_i,
       .jtag_tdo_o,
-      .debug_core_req_o(debug_core_req),
+      .debug_core_req_o(debug_req),
       .debug_ndmreset_no(debug_reset_n),
       .debug_slave_req_i(debug_slave_req),
       .debug_slave_resp_o(debug_slave_resp),
@@ -548,6 +608,8 @@ module core_v_mini_mcu
       .clk_gate_en_ni(memory_subsystem_clkgate_en_n),
       .ram_req_i(ram_slave_req),
       .ram_resp_o(ram_slave_resp),
+      .pwrgate_ni(memory_subsystem_banks_powergate_switch_n),
+      .pwrgate_ack_no(memory_subsystem_banks_powergate_switch_ack_n),
       .set_retentive_ni(memory_subsystem_banks_set_retentive_n)
   );
 
@@ -571,36 +633,17 @@ module core_v_mini_mcu
         spi_flash_sd_3_oe_o, spi_flash_sd_2_oe_o, spi_flash_sd_1_oe_o, spi_flash_sd_0_oe_o
       }),
       .spi_flash_sd_i({spi_flash_sd_3_i, spi_flash_sd_2_i, spi_flash_sd_1_i, spi_flash_sd_0_i}),
-      .spi_sck_o,
-      .spi_sck_en_o(spi_sck_oe_o),
-      .spi_csb_o({spi_cs_1_o, spi_cs_0_o}),
-      .spi_csb_en_o({spi_cs_1_oe_o, spi_cs_0_oe_o}),
-      .spi_sd_o({spi_sd_3_o, spi_sd_2_o, spi_sd_1_o, spi_sd_0_o}),
-      .spi_sd_en_o({spi_sd_3_oe_o, spi_sd_2_oe_o, spi_sd_1_oe_o, spi_sd_0_oe_o}),
-      .spi_sd_i({spi_sd_3_i, spi_sd_2_i, spi_sd_1_i, spi_sd_0_i}),
       .intr_i(intr),
       .intr_vector_ext_i,
       .core_sleep_i(core_sleep),
-      .cpu_subsystem_powergate_switch_no,
-      .cpu_subsystem_powergate_switch_ack_ni,
-      .cpu_subsystem_powergate_iso_no(cpu_subsystem_powergate_iso_n),
-      .cpu_subsystem_rst_no(cpu_subsystem_rst_n),
-      .peripheral_subsystem_powergate_switch_no,
-      .peripheral_subsystem_powergate_switch_ack_ni,
-      .peripheral_subsystem_powergate_iso_no(peripheral_subsystem_powergate_iso_n),
-      .peripheral_subsystem_rst_no(peripheral_subsystem_rst_n),
-      .memory_subsystem_banks_powergate_switch_no,
-      .memory_subsystem_banks_powergate_switch_ack_ni,
-      .memory_subsystem_banks_powergate_iso_no(memory_subsystem_banks_powergate_iso_n),
-      .memory_subsystem_banks_set_retentive_no(memory_subsystem_banks_set_retentive_n),
-      .external_subsystem_powergate_switch_no,
-      .external_subsystem_powergate_switch_ack_ni,
-      .external_subsystem_powergate_iso_no,
-      .external_subsystem_rst_no,
-      .external_ram_banks_set_retentive_no,
-      .peripheral_subsystem_clkgate_en_no(peripheral_subsystem_clkgate_en_n),
-      .memory_subsystem_clkgate_en_no(memory_subsystem_clkgate_en_n),
-      .external_subsystem_clkgate_en_no,
+      .cpu_subsystem_pwr_ctrl_o(cpu_subsystem_pwr_ctrl_out),
+      .peripheral_subsystem_pwr_ctrl_o(peripheral_subsystem_pwr_ctrl_out),
+      .memory_subsystem_pwr_ctrl_o(memory_subsystem_pwr_ctrl_out),
+      .external_subsystem_pwr_ctrl_o(external_subsystem_pwr_ctrl_out),
+      .cpu_subsystem_pwr_ctrl_i(cpu_subsystem_pwr_ctrl_in),
+      .peripheral_subsystem_pwr_ctrl_i(peripheral_subsystem_pwr_ctrl_in),
+      .memory_subsystem_pwr_ctrl_i(memory_subsystem_pwr_ctrl_in),
+      .external_subsystem_pwr_ctrl_i(external_subsystem_pwr_ctrl_in),
       .rv_timer_0_intr_o(rv_timer_intr[0]),
       .rv_timer_1_intr_o(rv_timer_intr[1]),
       .dma_read_ch0_req_o(dma_read_ch0_req),
@@ -611,7 +654,6 @@ module core_v_mini_mcu
       .dma_addr_ch0_resp_i(dma_addr_ch0_resp),
       .dma_done_intr_o(dma_done_intr),
       .dma_window_intr_o(dma_window_intr),
-      .spi_intr_event_o(spi_intr),
       .spi_flash_intr_event_o(spi_flash_intr),
       .pad_req_o,
       .pad_resp_i,
@@ -631,11 +673,14 @@ module core_v_mini_mcu
       .uart_intr_rx_break_err_o(uart_intr_rx_break_err),
       .uart_intr_rx_timeout_o(uart_intr_rx_timeout),
       .uart_intr_rx_parity_err_o(uart_intr_rx_parity_err),
+      .spi_rx_valid_i(spi_rx_valid),
+      .spi_tx_ready_i(spi_tx_ready),
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
       .ext_peripheral_slave_resp_i,
       .ext_dma_slot_tx_i,
-      .ext_dma_slot_rx_i
+      .ext_dma_slot_rx_i,
+      .ext_dma_stop_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (
@@ -665,6 +710,16 @@ module core_v_mini_mcu
       .cio_sda_i(i2c_sda_i),
       .cio_sda_o(i2c_sda_o),
       .cio_sda_en_o(i2c_sda_oe_o),
+      .spi_sck_o,
+      .spi_sck_en_o(spi_sck_oe_o),
+      .spi_csb_o({spi_cs_1_o, spi_cs_0_o}),
+      .spi_csb_en_o({spi_cs_1_oe_o, spi_cs_0_oe_o}),
+      .spi_sd_o({spi_sd_3_o, spi_sd_2_o, spi_sd_1_o, spi_sd_0_o}),
+      .spi_sd_en_o({spi_sd_3_oe_o, spi_sd_2_oe_o, spi_sd_1_oe_o, spi_sd_0_oe_o}),
+      .spi_sd_i({spi_sd_3_i, spi_sd_2_i, spi_sd_1_i, spi_sd_0_i}),
+      .spi_intr_event_o(spi_intr),
+      .spi_rx_valid_o(spi_rx_valid),
+      .spi_tx_ready_o(spi_tx_ready),
       .spi2_sck_o,
       .spi2_sck_en_o(spi2_sck_oe_o),
       .spi2_csb_o({spi2_cs_1_o, spi2_cs_0_o}),
@@ -689,104 +744,120 @@ module core_v_mini_mcu
       .i2s_rx_valid_o(i2s_rx_valid)
   );
 
-  assign pdm2pcm_pdm_o    = 0;
-  assign pdm2pcm_pdm_oe_o = 0;
-
-  assign gpio_ao_in[0]    = gpio_0_i;
-  assign gpio_0_o         = gpio_ao_out[0];
-  assign gpio_0_oe_o      = gpio_ao_oe[0];
-  assign gpio_ao_in[1]    = gpio_1_i;
-  assign gpio_1_o         = gpio_ao_out[1];
-  assign gpio_1_oe_o      = gpio_ao_oe[1];
-  assign gpio_ao_in[2]    = gpio_2_i;
-  assign gpio_2_o         = gpio_ao_out[2];
-  assign gpio_2_oe_o      = gpio_ao_oe[2];
-  assign gpio_ao_in[3]    = gpio_3_i;
-  assign gpio_3_o         = gpio_ao_out[3];
-  assign gpio_3_oe_o      = gpio_ao_oe[3];
-  assign gpio_ao_in[4]    = gpio_4_i;
-  assign gpio_4_o         = gpio_ao_out[4];
-  assign gpio_4_oe_o      = gpio_ao_oe[4];
-  assign gpio_ao_in[5]    = gpio_5_i;
-  assign gpio_5_o         = gpio_ao_out[5];
-  assign gpio_5_oe_o      = gpio_ao_oe[5];
-  assign gpio_ao_in[6]    = gpio_6_i;
-  assign gpio_6_o         = gpio_ao_out[6];
-  assign gpio_6_oe_o      = gpio_ao_oe[6];
-  assign gpio_ao_in[7]    = gpio_7_i;
-  assign gpio_7_o         = gpio_ao_out[7];
-  assign gpio_7_oe_o      = gpio_ao_oe[7];
-  assign gpio_in[8]       = gpio_8_i;
-  assign gpio_8_o         = gpio_out[8];
-  assign gpio_8_oe_o      = gpio_oe[8];
-  assign gpio_in[9]       = gpio_9_i;
-  assign gpio_9_o         = gpio_out[9];
-  assign gpio_9_oe_o      = gpio_oe[9];
-  assign gpio_in[10]      = gpio_10_i;
-  assign gpio_10_o        = gpio_out[10];
-  assign gpio_10_oe_o     = gpio_oe[10];
-  assign gpio_in[11]      = gpio_11_i;
-  assign gpio_11_o        = gpio_out[11];
-  assign gpio_11_oe_o     = gpio_oe[11];
-  assign gpio_in[12]      = gpio_12_i;
-  assign gpio_12_o        = gpio_out[12];
-  assign gpio_12_oe_o     = gpio_oe[12];
-  assign gpio_in[13]      = gpio_13_i;
-  assign gpio_13_o        = gpio_out[13];
-  assign gpio_13_oe_o     = gpio_oe[13];
-  assign gpio_in[14]      = gpio_14_i;
-  assign gpio_14_o        = gpio_out[14];
-  assign gpio_14_oe_o     = gpio_oe[14];
-  assign gpio_in[15]      = gpio_15_i;
-  assign gpio_15_o        = gpio_out[15];
-  assign gpio_15_oe_o     = gpio_oe[15];
-  assign gpio_in[16]      = gpio_16_i;
-  assign gpio_16_o        = gpio_out[16];
-  assign gpio_16_oe_o     = gpio_oe[16];
-  assign gpio_in[17]      = gpio_17_i;
-  assign gpio_17_o        = gpio_out[17];
-  assign gpio_17_oe_o     = gpio_oe[17];
-  assign gpio_in[18]      = gpio_18_i;
-  assign gpio_18_o        = gpio_out[18];
-  assign gpio_18_oe_o     = gpio_oe[18];
-  assign gpio_in[19]      = gpio_19_i;
-  assign gpio_19_o        = gpio_out[19];
-  assign gpio_19_oe_o     = gpio_oe[19];
-  assign gpio_in[20]      = gpio_20_i;
-  assign gpio_20_o        = gpio_out[20];
-  assign gpio_20_oe_o     = gpio_oe[20];
-  assign gpio_in[21]      = gpio_21_i;
-  assign gpio_21_o        = gpio_out[21];
-  assign gpio_21_oe_o     = gpio_oe[21];
-  assign gpio_in[22]      = gpio_22_i;
-  assign gpio_22_o        = gpio_out[22];
-  assign gpio_22_oe_o     = gpio_oe[22];
-  assign gpio_in[23]      = gpio_23_i;
-  assign gpio_23_o        = gpio_out[23];
-  assign gpio_23_oe_o     = gpio_oe[23];
-  assign gpio_in[24]      = gpio_24_i;
-  assign gpio_24_o        = gpio_out[24];
-  assign gpio_24_oe_o     = gpio_oe[24];
-  assign gpio_in[25]      = gpio_25_i;
-  assign gpio_25_o        = gpio_out[25];
-  assign gpio_25_oe_o     = gpio_oe[25];
-  assign gpio_in[26]      = gpio_26_i;
-  assign gpio_26_o        = gpio_out[26];
-  assign gpio_26_oe_o     = gpio_oe[26];
-  assign gpio_in[27]      = gpio_27_i;
-  assign gpio_27_o        = gpio_out[27];
-  assign gpio_27_oe_o     = gpio_oe[27];
-  assign gpio_in[28]      = gpio_28_i;
-  assign gpio_28_o        = gpio_out[28];
-  assign gpio_28_oe_o     = gpio_oe[28];
-  assign gpio_in[29]      = gpio_29_i;
-  assign gpio_29_o        = gpio_out[29];
-  assign gpio_29_oe_o     = gpio_oe[29];
-  assign gpio_in[30]      = gpio_30_i;
-  assign gpio_30_o        = gpio_out[30];
-  assign gpio_30_oe_o     = gpio_oe[30];
-  assign gpio_in[31]      = gpio_31_i;
-  assign gpio_31_o        = gpio_out[31];
-  assign gpio_31_oe_o     = gpio_oe[31];
+  // Debug_req assign
+  if (NRHARTS == 1) begin
+    assign debug_core_req  = debug_req;
+    assign ext_debug_req_o = 1'b0;
+  end else begin
+    always @(*) begin
+      for (int i = 0; i < NRHARTS; i++) begin
+        if (i == 0) debug_core_req = debug_req[i];
+        else ext_debug_req_o[i-1] = debug_req[i];
+      end
+    end
+  end
+
+  assign ext_cpu_subsystem_rst_no = cpu_subsystem_rst_n;
+  assign ext_debug_reset_no       = debug_reset_n;
+
+  assign pdm2pcm_pdm_o            = 0;
+  assign pdm2pcm_pdm_oe_o         = 0;
+
+  assign gpio_ao_in[0]            = gpio_0_i;
+  assign gpio_0_o                 = gpio_ao_out[0];
+  assign gpio_0_oe_o              = gpio_ao_oe[0];
+  assign gpio_ao_in[1]            = gpio_1_i;
+  assign gpio_1_o                 = gpio_ao_out[1];
+  assign gpio_1_oe_o              = gpio_ao_oe[1];
+  assign gpio_ao_in[2]            = gpio_2_i;
+  assign gpio_2_o                 = gpio_ao_out[2];
+  assign gpio_2_oe_o              = gpio_ao_oe[2];
+  assign gpio_ao_in[3]            = gpio_3_i;
+  assign gpio_3_o                 = gpio_ao_out[3];
+  assign gpio_3_oe_o              = gpio_ao_oe[3];
+  assign gpio_ao_in[4]            = gpio_4_i;
+  assign gpio_4_o                 = gpio_ao_out[4];
+  assign gpio_4_oe_o              = gpio_ao_oe[4];
+  assign gpio_ao_in[5]            = gpio_5_i;
+  assign gpio_5_o                 = gpio_ao_out[5];
+  assign gpio_5_oe_o              = gpio_ao_oe[5];
+  assign gpio_ao_in[6]            = gpio_6_i;
+  assign gpio_6_o                 = gpio_ao_out[6];
+  assign gpio_6_oe_o              = gpio_ao_oe[6];
+  assign gpio_ao_in[7]            = gpio_7_i;
+  assign gpio_7_o                 = gpio_ao_out[7];
+  assign gpio_7_oe_o              = gpio_ao_oe[7];
+  assign gpio_in[8]               = gpio_8_i;
+  assign gpio_8_o                 = gpio_out[8];
+  assign gpio_8_oe_o              = gpio_oe[8];
+  assign gpio_in[9]               = gpio_9_i;
+  assign gpio_9_o                 = gpio_out[9];
+  assign gpio_9_oe_o              = gpio_oe[9];
+  assign gpio_in[10]              = gpio_10_i;
+  assign gpio_10_o                = gpio_out[10];
+  assign gpio_10_oe_o             = gpio_oe[10];
+  assign gpio_in[11]              = gpio_11_i;
+  assign gpio_11_o                = gpio_out[11];
+  assign gpio_11_oe_o             = gpio_oe[11];
+  assign gpio_in[12]              = gpio_12_i;
+  assign gpio_12_o                = gpio_out[12];
+  assign gpio_12_oe_o             = gpio_oe[12];
+  assign gpio_in[13]              = gpio_13_i;
+  assign gpio_13_o                = gpio_out[13];
+  assign gpio_13_oe_o             = gpio_oe[13];
+  assign gpio_in[14]              = gpio_14_i;
+  assign gpio_14_o                = gpio_out[14];
+  assign gpio_14_oe_o             = gpio_oe[14];
+  assign gpio_in[15]              = gpio_15_i;
+  assign gpio_15_o                = gpio_out[15];
+  assign gpio_15_oe_o             = gpio_oe[15];
+  assign gpio_in[16]              = gpio_16_i;
+  assign gpio_16_o                = gpio_out[16];
+  assign gpio_16_oe_o             = gpio_oe[16];
+  assign gpio_in[17]              = gpio_17_i;
+  assign gpio_17_o                = gpio_out[17];
+  assign gpio_17_oe_o             = gpio_oe[17];
+  assign gpio_in[18]              = gpio_18_i;
+  assign gpio_18_o                = gpio_out[18];
+  assign gpio_18_oe_o             = gpio_oe[18];
+  assign gpio_in[19]              = gpio_19_i;
+  assign gpio_19_o                = gpio_out[19];
+  assign gpio_19_oe_o             = gpio_oe[19];
+  assign gpio_in[20]              = gpio_20_i;
+  assign gpio_20_o                = gpio_out[20];
+  assign gpio_20_oe_o             = gpio_oe[20];
+  assign gpio_in[21]              = gpio_21_i;
+  assign gpio_21_o                = gpio_out[21];
+  assign gpio_21_oe_o             = gpio_oe[21];
+  assign gpio_in[22]              = gpio_22_i;
+  assign gpio_22_o                = gpio_out[22];
+  assign gpio_22_oe_o             = gpio_oe[22];
+  assign gpio_in[23]              = gpio_23_i;
+  assign gpio_23_o                = gpio_out[23];
+  assign gpio_23_oe_o             = gpio_oe[23];
+  assign gpio_in[24]              = gpio_24_i;
+  assign gpio_24_o                = gpio_out[24];
+  assign gpio_24_oe_o             = gpio_oe[24];
+  assign gpio_in[25]              = gpio_25_i;
+  assign gpio_25_o                = gpio_out[25];
+  assign gpio_25_oe_o             = gpio_oe[25];
+  assign gpio_in[26]              = gpio_26_i;
+  assign gpio_26_o                = gpio_out[26];
+  assign gpio_26_oe_o             = gpio_oe[26];
+  assign gpio_in[27]              = gpio_27_i;
+  assign gpio_27_o                = gpio_out[27];
+  assign gpio_27_oe_o             = gpio_oe[27];
+  assign gpio_in[28]              = gpio_28_i;
+  assign gpio_28_o                = gpio_out[28];
+  assign gpio_28_oe_o             = gpio_oe[28];
+  assign gpio_in[29]              = gpio_29_i;
+  assign gpio_29_o                = gpio_out[29];
+  assign gpio_29_oe_o             = gpio_oe[29];
+  assign gpio_in[30]              = gpio_30_i;
+  assign gpio_30_o                = gpio_out[30];
+  assign gpio_30_oe_o             = gpio_oe[30];
+  assign gpio_in[31]              = gpio_31_i;
+  assign gpio_31_o                = gpio_out[31];
+  assign gpio_31_oe_o             = gpio_oe[31];
 
 endmodule  // core_v_mini_mcu
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
index 84255ec1..cb571752 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
@@ -11,10 +11,12 @@ module core_v_mini_mcu
     parameter ZFINX = 0,
     parameter EXT_XBAR_NMASTER = 0,
     parameter X_EXT = 0,  // eXtension interface in cv32e40x
+    parameter EXT_HARTS = 0,
     //do not touch these parameters
     parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
     parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
-    parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT
+    parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT,
+    parameter EXT_HARTS_RND = EXT_HARTS == 0 ? 1 : EXT_HARTS
 ) (
 
     input logic rst_ni,
@@ -51,37 +53,45 @@ ${pad.core_v_mini_mcu_interface}
     output obi_req_t  ext_dma_addr_ch0_req_o,
     input  obi_resp_t ext_dma_addr_ch0_resp_i,
 
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
+
     output reg_req_t ext_peripheral_slave_req_o,
     input  reg_rsp_t ext_peripheral_slave_resp_i,
 
+    output logic  [EXT_HARTS_RND-1:0] ext_debug_req_o,
+    output logic  ext_debug_reset_no,
+
     input logic [NEXT_INT_RND-1:0] intr_vector_ext_i,
 
+    //power manager exposed to top level
+    //signals are unrolled to easy EDA tools
     output logic cpu_subsystem_powergate_switch_no,
     input  logic cpu_subsystem_powergate_switch_ack_ni,
     output logic peripheral_subsystem_powergate_switch_no,
     input  logic peripheral_subsystem_powergate_switch_ack_ni,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_no,
-    input  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack_ni,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_no,
     input  logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_ack_ni,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_iso_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_rst_no,
+    output logic ext_cpu_subsystem_rst_no,
     output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no,
     output logic [EXT_DOMAINS_RND-1:0] external_subsystem_clkgate_en_no,
 
     output logic [31:0] exit_value_o,
 
-    input logic ext_dma_slot_tx_i,
-    input logic ext_dma_slot_rx_i
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i
 );
 
   import core_v_mini_mcu_pkg::*;
   import cv32e40p_apu_core_pkg::*;
+  import power_manager_pkg::*;
 
   localparam NUM_BYTES = core_v_mini_mcu_pkg::MEM_SIZE;
   localparam DM_HALTADDRESS = core_v_mini_mcu_pkg::DEBUG_START_ADDRESS + 32'h00000800; //debug rom code (section .text in linker) starts at 0x800
 
   localparam JTAG_IDCODE = 32'h10001c05;
+  localparam NRHARTS = EXT_HARTS + 1; //external harts + single hart core-v-mini-mcu
   localparam BOOT_ADDR = core_v_mini_mcu_pkg::BOOTROM_START_ADDRESS;
   localparam NUM_MHPMCOUNTERS = 1;
 
@@ -123,7 +133,7 @@ ${pad.core_v_mini_mcu_interface}
   // signals to debug unit
   logic debug_core_req;
   logic debug_reset_n;
-
+  logic [NRHARTS-1:0] debug_req;
   // core
   logic core_sleep;
 
@@ -145,24 +155,69 @@ ${pad.core_v_mini_mcu_interface}
   logic [31:0] intr;
   logic [14:0] fast_intr;
 
-  // Power manager
-  logic cpu_subsystem_powergate_iso_n;
+  //Power manager signals
+  power_manager_out_t cpu_subsystem_pwr_ctrl_out;
+  power_manager_out_t peripheral_subsystem_pwr_ctrl_out;
+  power_manager_out_t memory_subsystem_pwr_ctrl_out[core_v_mini_mcu_pkg::NUM_BANKS-1:0];
+  power_manager_out_t external_subsystem_pwr_ctrl_out[EXT_DOMAINS_RND-1:0];
+
+  power_manager_in_t  cpu_subsystem_pwr_ctrl_in;
+  power_manager_in_t  peripheral_subsystem_pwr_ctrl_in;
+  power_manager_in_t  memory_subsystem_pwr_ctrl_in[core_v_mini_mcu_pkg::NUM_BANKS-1:0];
+  power_manager_in_t  external_subsystem_pwr_ctrl_in[EXT_DOMAINS_RND-1:0];
+
   logic cpu_subsystem_rst_n;
-  logic peripheral_subsystem_powergate_iso_n;
+  logic cpu_subsystem_powergate_iso_n;
+
   logic peripheral_subsystem_rst_n;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso_n;
+  logic peripheral_subsystem_powergate_iso_n;
+  logic peripheral_subsystem_clkgate_en_n;
+
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_n;
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack_n;
   logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_set_retentive_n;
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso_n;
+  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_clkgate_en_n;
+
+  //pwrgate exposed outside for UPF sim flow and switch cells
+  assign cpu_subsystem_powergate_switch_no    = cpu_subsystem_pwr_ctrl_out.pwrgate_en_n;
+  assign cpu_subsystem_pwr_ctrl_in.pwrgate_ack_n = cpu_subsystem_powergate_switch_ack_ni;
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign cpu_subsystem_powergate_iso_n                 = cpu_subsystem_pwr_ctrl_out.isogate_en_n;
+  assign cpu_subsystem_rst_n                  = cpu_subsystem_pwr_ctrl_out.rst_n;
+
+  //pwrgate exposed both outside for UPF sim flow
+  assign peripheral_subsystem_powergate_switch_no = peripheral_subsystem_pwr_ctrl_out.pwrgate_en_n;
+  assign peripheral_subsystem_pwr_ctrl_in.pwrgate_ack_n  = peripheral_subsystem_powergate_switch_ack_ni;
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign peripheral_subsystem_powergate_iso_n = peripheral_subsystem_pwr_ctrl_out.isogate_en_n;
+  assign peripheral_subsystem_rst_n           = peripheral_subsystem_pwr_ctrl_out.rst_n;
+  assign peripheral_subsystem_clkgate_en_n    = peripheral_subsystem_pwr_ctrl_out.clkgate_en_n;
+
+% for bank in xheep.iter_ram_banks():
+  assign memory_subsystem_banks_powergate_switch_n[${bank.name()}] = memory_subsystem_pwr_ctrl_out[${bank.name()}].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[${bank.name()}].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[${bank.name()}];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[${bank.name()}] = memory_subsystem_pwr_ctrl_out[${bank.name()}].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[${bank.name()}] = memory_subsystem_pwr_ctrl_out[${bank.name()}].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[${bank.name()}] = memory_subsystem_pwr_ctrl_out[${bank.name()}].clkgate_en_n;
+% endfor
 
-   // Clock gating signals
-   logic peripheral_subsystem_clkgate_en_n;
-   logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0]memory_subsystem_clkgate_en_n;
+  for (genvar i = 0; i < EXT_DOMAINS_RND; i = i + 1) begin
+    assign external_subsystem_powergate_switch_no[i]        = external_subsystem_pwr_ctrl_out[i].pwrgate_en_n;
+    assign external_subsystem_powergate_iso_no[i] = external_subsystem_pwr_ctrl_out[i].isogate_en_n;
+    assign external_subsystem_rst_no[i] = external_subsystem_pwr_ctrl_out[i].rst_n;
+    assign external_ram_banks_set_retentive_no[i]           = external_subsystem_pwr_ctrl_out[i].retentive_en_n;
+    assign external_subsystem_clkgate_en_no[i] = external_subsystem_pwr_ctrl_out[i].clkgate_en_n;
+    assign external_subsystem_pwr_ctrl_in[i].pwrgate_ack_n = external_subsystem_powergate_switch_ack_ni[i];
+  end
 
   // DMA
   logic dma_done_intr;
   logic dma_window_intr;
 
   // SPI
-  logic spi_flash_intr, spi_intr;
+  logic spi_flash_intr, spi_intr, spi_rx_valid, spi_tx_ready;
 
   // GPIO
   logic [31:8] gpio_in;
@@ -233,6 +288,7 @@ ${pad.core_v_mini_mcu_interface}
   );
 
   debug_subsystem #(
+      .NRHARTS    (NRHARTS),
       .JTAG_IDCODE(JTAG_IDCODE)
   ) debug_subsystem_i (
       .clk_i,
@@ -242,7 +298,7 @@ ${pad.core_v_mini_mcu_interface}
       .jtag_trst_ni,
       .jtag_tdi_i,
       .jtag_tdo_o,
-      .debug_core_req_o(debug_core_req),
+      .debug_core_req_o(debug_req),
       .debug_ndmreset_no(debug_reset_n),
       .debug_slave_req_i(debug_slave_req),
       .debug_slave_resp_o(debug_slave_resp),
@@ -302,6 +358,8 @@ ${pad.core_v_mini_mcu_interface}
       .clk_gate_en_ni(memory_subsystem_clkgate_en_n),
       .ram_req_i(ram_slave_req),
       .ram_resp_o(ram_slave_resp),
+      .pwrgate_ni(memory_subsystem_banks_powergate_switch_n),
+      .pwrgate_ack_no(memory_subsystem_banks_powergate_switch_ack_n),
       .set_retentive_ni(memory_subsystem_banks_set_retentive_n)
   );
 
@@ -323,36 +381,17 @@ ${pad.core_v_mini_mcu_interface}
       .spi_flash_sd_o({spi_flash_sd_3_o,spi_flash_sd_2_o, spi_flash_sd_1_o, spi_flash_sd_0_o}),
       .spi_flash_sd_en_o({spi_flash_sd_3_oe_o,spi_flash_sd_2_oe_o, spi_flash_sd_1_oe_o, spi_flash_sd_0_oe_o}),
       .spi_flash_sd_i({spi_flash_sd_3_i,spi_flash_sd_2_i, spi_flash_sd_1_i, spi_flash_sd_0_i}),
-      .spi_sck_o,
-      .spi_sck_en_o(spi_sck_oe_o),
-      .spi_csb_o({spi_cs_1_o,spi_cs_0_o}),
-      .spi_csb_en_o({spi_cs_1_oe_o, spi_cs_0_oe_o}),
-      .spi_sd_o({spi_sd_3_o,spi_sd_2_o, spi_sd_1_o, spi_sd_0_o}),
-      .spi_sd_en_o({spi_sd_3_oe_o,spi_sd_2_oe_o, spi_sd_1_oe_o, spi_sd_0_oe_o}),
-      .spi_sd_i({spi_sd_3_i,spi_sd_2_i, spi_sd_1_i, spi_sd_0_i}),
       .intr_i(intr),
       .intr_vector_ext_i,
       .core_sleep_i(core_sleep),
-      .cpu_subsystem_powergate_switch_no,
-      .cpu_subsystem_powergate_switch_ack_ni,
-      .cpu_subsystem_powergate_iso_no(cpu_subsystem_powergate_iso_n),
-      .cpu_subsystem_rst_no(cpu_subsystem_rst_n),
-      .peripheral_subsystem_powergate_switch_no,
-      .peripheral_subsystem_powergate_switch_ack_ni,
-      .peripheral_subsystem_powergate_iso_no(peripheral_subsystem_powergate_iso_n),
-      .peripheral_subsystem_rst_no(peripheral_subsystem_rst_n),
-      .memory_subsystem_banks_powergate_switch_no,
-      .memory_subsystem_banks_powergate_switch_ack_ni,
-      .memory_subsystem_banks_powergate_iso_no(memory_subsystem_banks_powergate_iso_n),
-      .memory_subsystem_banks_set_retentive_no(memory_subsystem_banks_set_retentive_n),
-      .external_subsystem_powergate_switch_no,
-      .external_subsystem_powergate_switch_ack_ni,
-      .external_subsystem_powergate_iso_no,
-      .external_subsystem_rst_no,
-      .external_ram_banks_set_retentive_no,
-      .peripheral_subsystem_clkgate_en_no(peripheral_subsystem_clkgate_en_n),
-      .memory_subsystem_clkgate_en_no(memory_subsystem_clkgate_en_n),
-      .external_subsystem_clkgate_en_no,
+      .cpu_subsystem_pwr_ctrl_o(cpu_subsystem_pwr_ctrl_out),
+      .peripheral_subsystem_pwr_ctrl_o(peripheral_subsystem_pwr_ctrl_out),
+      .memory_subsystem_pwr_ctrl_o(memory_subsystem_pwr_ctrl_out),
+      .external_subsystem_pwr_ctrl_o(external_subsystem_pwr_ctrl_out),
+      .cpu_subsystem_pwr_ctrl_i(cpu_subsystem_pwr_ctrl_in),
+      .peripheral_subsystem_pwr_ctrl_i(peripheral_subsystem_pwr_ctrl_in),
+      .memory_subsystem_pwr_ctrl_i(memory_subsystem_pwr_ctrl_in),
+      .external_subsystem_pwr_ctrl_i(external_subsystem_pwr_ctrl_in),
       .rv_timer_0_intr_o(rv_timer_intr[0]),
       .rv_timer_1_intr_o(rv_timer_intr[1]),
       .dma_read_ch0_req_o(dma_read_ch0_req),
@@ -363,7 +402,6 @@ ${pad.core_v_mini_mcu_interface}
       .dma_addr_ch0_resp_i(dma_addr_ch0_resp),
       .dma_done_intr_o(dma_done_intr),
       .dma_window_intr_o(dma_window_intr),
-      .spi_intr_event_o(spi_intr),
       .spi_flash_intr_event_o(spi_flash_intr),
       .pad_req_o,
       .pad_resp_i,
@@ -383,11 +421,14 @@ ${pad.core_v_mini_mcu_interface}
       .uart_intr_rx_break_err_o(uart_intr_rx_break_err),
       .uart_intr_rx_timeout_o(uart_intr_rx_timeout),
       .uart_intr_rx_parity_err_o(uart_intr_rx_parity_err),
+      .spi_rx_valid_i(spi_rx_valid),
+      .spi_tx_ready_i(spi_tx_ready),
       .i2s_rx_valid_i(i2s_rx_valid),
       .ext_peripheral_slave_req_o,
       .ext_peripheral_slave_resp_i,
       .ext_dma_slot_tx_i,
-      .ext_dma_slot_rx_i
+      .ext_dma_slot_rx_i,
+      .ext_dma_stop_i
   );
 
   peripheral_subsystem peripheral_subsystem_i (
@@ -417,6 +458,16 @@ ${pad.core_v_mini_mcu_interface}
       .cio_sda_i(i2c_sda_i),
       .cio_sda_o(i2c_sda_o),
       .cio_sda_en_o(i2c_sda_oe_o),
+      .spi_sck_o,
+      .spi_sck_en_o(spi_sck_oe_o),
+      .spi_csb_o({spi_cs_1_o,spi_cs_0_o}),
+      .spi_csb_en_o({spi_cs_1_oe_o, spi_cs_0_oe_o}),
+      .spi_sd_o({spi_sd_3_o,spi_sd_2_o, spi_sd_1_o, spi_sd_0_o}),
+      .spi_sd_en_o({spi_sd_3_oe_o,spi_sd_2_oe_o, spi_sd_1_oe_o, spi_sd_0_oe_o}),
+      .spi_sd_i({spi_sd_3_i,spi_sd_2_i, spi_sd_1_i, spi_sd_0_i}),
+      .spi_intr_event_o(spi_intr),
+      .spi_rx_valid_o(spi_rx_valid),
+      .spi_tx_ready_o(spi_tx_ready),
       .spi2_sck_o,
       .spi2_sck_en_o(spi2_sck_oe_o),
       .spi2_csb_o({spi2_cs_1_o, spi2_cs_0_o}),
@@ -441,6 +492,22 @@ ${pad.core_v_mini_mcu_interface}
       .i2s_rx_valid_o(i2s_rx_valid)
   );
 
+  // Debug_req assign
+  if (NRHARTS == 1) begin
+    assign debug_core_req = debug_req;
+    assign ext_debug_req_o  = 1'b0;
+  end else begin
+    always @(*) begin
+      for (int i = 0; i < NRHARTS; i++) begin
+        if (i == 0) debug_core_req = debug_req[i];
+        else ext_debug_req_o[i-1] = debug_req[i];
+      end
+    end
+  end
+
+  assign ext_cpu_subsystem_rst_no = cpu_subsystem_rst_n;
+  assign ext_debug_reset_no = debug_reset_n;
+
   assign pdm2pcm_pdm_o = 0;
   assign pdm2pcm_pdm_oe_o = 0;
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv
index 673c1b31..0718c8f1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/debug_subsystem.sv
@@ -5,6 +5,7 @@
 module debug_subsystem
   import obi_pkg::*;
 #(
+    parameter NRHARTS = 1,
     parameter JTAG_IDCODE = 32'h10001c05
 ) (
     input logic clk_i,
@@ -17,7 +18,7 @@ module debug_subsystem
     output logic jtag_tdo_o,
 
     output logic debug_ndmreset_no,
-    output logic debug_core_req_o,
+    output logic [NRHARTS-1:0] debug_core_req_o,
 
     input  obi_req_t  debug_slave_req_i,
     output obi_resp_t debug_slave_resp_o,
@@ -28,14 +29,20 @@ module debug_subsystem
 
   import dm::*;
 
-  localparam dm::hartinfo_t hartinfo = '{
-      zero1: '0,
-      nscratch: 2,  // Debug module needs at least two scratch regs
-      zero0: '0,
-      dataaccess: 1'b1,  // data registers are memory mapped in the debugger
-      datasize: dm::DataCount,
-      dataaddr: dm::DataAddr
-  };
+  logic [NRHARTS-1:0]    unavailable;
+  dm::hartinfo_t [NRHARTS-1:0] hartinfo;
+
+  always @(*) begin
+    for (int i = 0; i < NRHARTS; i++) begin
+      hartinfo[i].zero1 = '0;
+      hartinfo[i].nscratch = 2;  // Debug module needs at least two scratch regs
+      hartinfo[i].zero0 = '0;
+      hartinfo[i].dataaccess = 1'b1;  // data registers are memory mapped in the debugger
+      hartinfo[i].datasize = dm::DataCount;
+      hartinfo[i].dataaddr = dm::DataAddr;
+      unavailable[i] = ~(1'b1);
+    end
+  end
 
   dm::dmi_req_t  dmi_req;
   logic          dmi_req_valid;
@@ -68,14 +75,16 @@ module debug_subsystem
       .tdo_oe_o        ()
   );
 
-  dm_obi_top dm_obi_top_i (
+  dm_obi_top #(
+      .NrHarts(NRHARTS)
+  ) dm_obi_top_i (
       .clk_i        (clk_i),
       .rst_ni       (rst_ni),
       .testmode_i   (1'b0),
       .ndmreset_o   (ndmreset),
       .dmactive_o   (),
       .debug_req_o  (debug_core_req_o),
-      .unavailable_i(~(1'b1)),
+      .unavailable_i(unavailable),
       .hartinfo_i   (hartinfo),
 
       .slave_req_i   (debug_slave_req_i.req),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/addr_map_rule_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/addr_map_rule_pkg.sv
index 4e0a9a27..712164af 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/addr_map_rule_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/addr_map_rule_pkg.sv
@@ -10,4 +10,10 @@ package addr_map_rule_pkg;
     logic [31:0] end_addr;
   } addr_map_rule_t;
 
+  typedef struct packed {
+    logic [7:0] idx;
+    logic [7:0] start_addr;
+    logic [7:0] end_addr;
+  } addr_map_rule_8bit_t;
+
 endpackage
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
index 660022e1..ba99d50f 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
@@ -16,6 +16,7 @@
 package core_v_mini_mcu_pkg;
 
   import addr_map_rule_pkg::*;
+  import power_manager_pkg::*;
 
   typedef enum logic [1:0] {
     cv32e40p,
@@ -31,7 +32,7 @@ package core_v_mini_mcu_pkg;
     onetoM
   } bus_type_e;
 
-  localparam bus_type_e BusType = ${bus_type};
+  localparam bus_type_e BusType = ${xheep.bus_type().value};
 
   //master idx
   localparam logic [31:0] CORE_INSTR_IDX = 0;
@@ -46,15 +47,15 @@ package core_v_mini_mcu_pkg;
   // Internal slave memory map and index
   // -----------------------------------
   //must be power of two
-  localparam int unsigned MEM_SIZE = 32'h${ram_size_address};
+  localparam int unsigned MEM_SIZE = 32'h${f'{xheep.ram_size_address():08X}'};
 
-  localparam SYSTEM_XBAR_NSLAVE = ${int(ram_numbanks) + 5};
+  localparam SYSTEM_XBAR_NSLAVE = ${xheep.ram_numbanks() + 5};
 
   localparam int unsigned LOG_SYSTEM_XBAR_NMASTER = SYSTEM_XBAR_NMASTER > 1 ? $clog2(SYSTEM_XBAR_NMASTER) : 32'd1;
   localparam int unsigned LOG_SYSTEM_XBAR_NSLAVE = SYSTEM_XBAR_NSLAVE > 1 ? $clog2(SYSTEM_XBAR_NSLAVE) : 32'd1;
 
-  localparam int unsigned NUM_BANKS = ${ram_numbanks};
-  localparam int unsigned NUM_BANKS_IL = ${ram_numbanks_il};
+  localparam int unsigned NUM_BANKS = ${xheep.ram_numbanks()};
+  localparam int unsigned NUM_BANKS_IL = ${xheep.ram_numbanks_il()};
   localparam int unsigned EXTERNAL_DOMAINS = ${external_domains};
 
   localparam logic[31:0] ERROR_START_ADDRESS = 32'hBADACCE5;
@@ -62,49 +63,44 @@ package core_v_mini_mcu_pkg;
   localparam logic[31:0] ERROR_END_ADDRESS = ERROR_START_ADDRESS + ERROR_SIZE;
   localparam logic[31:0] ERROR_IDX = 32'd0;
 
-% for bank in range(ram_numbanks_cont):
-  localparam logic [31:0] RAM${bank}_START_ADDRESS = 32'h${'{:08X}'.format(int(ram_start_address) + bank*32*1024)};
-  localparam logic [31:0] RAM${bank}_SIZE = 32'h${hex(32*1024)[2:]};
-  localparam logic [31:0] RAM${bank}_END_ADDRESS = RAM${bank}_START_ADDRESS + RAM${bank}_SIZE;
-  localparam logic [31:0] RAM${bank}_IDX = 32'd${bank + 1};
+% for bank in xheep.iter_ram_banks():
+  localparam logic [31:0] RAM${bank.name()}_IDX = 32'd${bank.map_idx()};
+  localparam logic [31:0] RAM${bank.name()}_SIZE = 32'h${f'{bank.size():08X}'};
+  localparam logic [31:0] RAM${bank.name()}_START_ADDRESS = 32'h${f'{bank.start_address():08X}'};
+  localparam logic [31:0] RAM${bank.name()}_END_ADDRESS = 32'h${f'{bank.end_address():08X}'};
 % endfor
-% if ram_numbanks_il != 0:
-  localparam logic [31:0] RAM${ram_numbanks_cont}_START_ADDRESS = 32'h${'{:08X}'.format(int(ram_start_address) + int(ram_numbanks_cont)*32*1024)};
-  localparam logic [31:0] RAM${ram_numbanks_cont}_SIZE = 32'h${hex(int(ram_numbanks_il)*32*1024)[2:]};
-  localparam logic [31:0] RAM${ram_numbanks_cont}_END_ADDRESS = RAM${ram_numbanks_cont}_START_ADDRESS + RAM${ram_numbanks_cont}_SIZE;
-  localparam logic [31:0] RAM${ram_numbanks_cont}_IDX = 32'd${ram_numbanks_cont + 1};
-% for bank in range(ram_numbanks_il - 1):
-  localparam logic [31:0] RAM${int(ram_numbanks_cont) + bank + 1}_IDX = 32'd${int(ram_numbanks_cont) + bank + 2};
+
+% for i, group in enumerate(xheep.iter_il_groups()):
+  localparam logic [31:0] RAM_IL${i}_START_ADDRESS = 32'h${f'{group.start:08X}'};
+  localparam logic [31:0] RAM_IL${i}_SIZE = 32'h${f'{group.size:08X}'};
+  localparam logic [31:0] RAM_IL${i}_END_ADDRESS = RAM_IL${i}_START_ADDRESS + RAM_IL${i}_SIZE;
+  localparam logic [31:0] RAM_IL${i}_IDX = RAM${group.first_name}_IDX;
 % endfor
-% endif
 
   localparam logic[31:0] DEBUG_START_ADDRESS = 32'h${debug_start_address};
   localparam logic[31:0] DEBUG_SIZE = 32'h${debug_size_address};
   localparam logic[31:0] DEBUG_END_ADDRESS = DEBUG_START_ADDRESS + DEBUG_SIZE;
-  localparam logic[31:0] DEBUG_IDX = 32'd${int(ram_numbanks) + 1};
+  localparam logic[31:0] DEBUG_IDX = 32'd${xheep.ram_numbanks() + 1};
 
   localparam logic[31:0] AO_PERIPHERAL_START_ADDRESS = 32'h${ao_peripheral_start_address};
   localparam logic[31:0] AO_PERIPHERAL_SIZE = 32'h${ao_peripheral_size_address};
   localparam logic[31:0] AO_PERIPHERAL_END_ADDRESS = AO_PERIPHERAL_START_ADDRESS + AO_PERIPHERAL_SIZE;
-  localparam logic[31:0] AO_PERIPHERAL_IDX = 32'd${int(ram_numbanks) + 2};
+  localparam logic[31:0] AO_PERIPHERAL_IDX = 32'd${xheep.ram_numbanks() + 2};
 
   localparam logic[31:0] PERIPHERAL_START_ADDRESS = 32'h${peripheral_start_address};
   localparam logic[31:0] PERIPHERAL_SIZE = 32'h${peripheral_size_address};
   localparam logic[31:0] PERIPHERAL_END_ADDRESS = PERIPHERAL_START_ADDRESS + PERIPHERAL_SIZE;
-  localparam logic[31:0] PERIPHERAL_IDX = 32'd${int(ram_numbanks) + 3};
+  localparam logic[31:0] PERIPHERAL_IDX = 32'd${xheep.ram_numbanks() + 3};
 
   localparam logic[31:0] FLASH_MEM_START_ADDRESS = 32'h${flash_mem_start_address};
   localparam logic[31:0] FLASH_MEM_SIZE = 32'h${flash_mem_size_address};
   localparam logic[31:0] FLASH_MEM_END_ADDRESS = FLASH_MEM_START_ADDRESS + FLASH_MEM_SIZE;
-  localparam logic[31:0] FLASH_MEM_IDX = 32'd${int(ram_numbanks) + 4};
+  localparam logic[31:0] FLASH_MEM_IDX = 32'd${xheep.ram_numbanks() + 4};
 
   localparam addr_map_rule_t [SYSTEM_XBAR_NSLAVE-1:0] XBAR_ADDR_RULES = '{
       '{ idx: ERROR_IDX, start_addr: ERROR_START_ADDRESS, end_addr: ERROR_END_ADDRESS },
-% for bank in range(ram_numbanks_cont):
-      '{ idx: RAM${bank}_IDX, start_addr: RAM${bank}_START_ADDRESS, end_addr: RAM${bank}_END_ADDRESS },
-% endfor
-% for bank in range(ram_numbanks_il):
-      '{ idx: RAM${int(ram_numbanks_cont) + bank}_IDX, start_addr: RAM${ram_numbanks_cont}_START_ADDRESS, end_addr: RAM${ram_numbanks_cont}_END_ADDRESS },
+% for bank in xheep.iter_ram_banks():
+      '{ idx: RAM${bank.name()}_IDX, start_addr: RAM${bank.name()}_START_ADDRESS, end_addr: RAM${bank.name()}_END_ADDRESS },
 % endfor
       '{ idx: DEBUG_IDX, start_addr: DEBUG_START_ADDRESS, end_addr: DEBUG_END_ADDRESS },
       '{ idx: AO_PERIPHERAL_IDX, start_addr: AO_PERIPHERAL_START_ADDRESS, end_addr: AO_PERIPHERAL_END_ADDRESS },
@@ -142,6 +138,7 @@ package core_v_mini_mcu_pkg;
   // always-on peripherals
   // ---------------------
   localparam AO_PERIPHERALS = ${ao_peripherals_count};
+  localparam DMA_CH_NUM = ${dma_ch_count};
 
 % for peripheral, addr in ao_peripherals.items():
   localparam logic [31:0] ${peripheral.upper()}_START_ADDRESS = AO_PERIPHERAL_START_ADDRESS + 32'h${addr["offset"]};
@@ -150,6 +147,7 @@ package core_v_mini_mcu_pkg;
   localparam logic [31:0] ${peripheral.upper()}_IDX = 32'd${loop.index};
   
 % endfor
+
   localparam addr_map_rule_t [AO_PERIPHERALS-1:0] AO_PERIPHERALS_ADDR_RULES = '{
 % for peripheral, addr in ao_peripherals.items():
       '{ idx: ${peripheral.upper()}_IDX, start_addr: ${peripheral.upper()}_START_ADDRESS, end_addr: ${peripheral.upper()}_END_ADDRESS }${"," if not loop.last else ""}
@@ -158,6 +156,23 @@ package core_v_mini_mcu_pkg;
 
   localparam int unsigned AO_PERIPHERALS_PORT_SEL_WIDTH = AO_PERIPHERALS > 1 ? $clog2(AO_PERIPHERALS) : 32'd1;
 
+  // Relative DMA channels addresses
+% for i in range(int(dma_ch_count)):
+  localparam logic [7:0] DMA_CH${i}_START_ADDRESS = 8'h${hex(int(ao_peripherals["dma"]["ch_length"], 16)*(i) >> 8)[2:]};
+  localparam logic [7:0] DMA_CH${i}_SIZE = 8'h${hex(int(ao_peripherals["dma"]["ch_length"], 16) >> 8)[2:]};
+  localparam logic [7:0] DMA_CH${i}_END_ADDRESS = DMA_CH${i}_START_ADDRESS + DMA_CH${i}_SIZE;
+  localparam logic [7:0] DMA_CH${i}_IDX = 8'd${i};
+
+% endfor
+
+  localparam addr_map_rule_8bit_t [DMA_CH_NUM-1:0] DMA_ADDR_RULES = '{
+  % for i in range(int(dma_ch_count)):
+      '{ idx: DMA_CH${i}_IDX, start_addr: DMA_CH${i}_START_ADDRESS, end_addr: DMA_CH${i}_END_ADDRESS }${"," if not loop.last else ""}
+% endfor
+  };
+  
+  localparam int unsigned DMA_CH_PORT_SEL_WIDTH = DMA_CH_NUM > 1 ? $clog2(DMA_CH_NUM) : 32'd1;
+
 ######################################################################
 ## Automatically add all peripherals listed
 ######################################################################
@@ -195,5 +210,11 @@ package core_v_mini_mcu_pkg;
 
   localparam int unsigned NUM_PAD_PORT_SEL_WIDTH = NUM_PAD > 1 ? $clog2(NUM_PAD) : 32'd1;
 
+  typedef enum logic [1:0] {
+    TOP,
+    RIGHT,
+    BOTTOM,
+    LEFT
+  } pad_side_e;
 
 endpackage
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/power_manager_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/power_manager_pkg.sv
new file mode 100644
index 00000000..613d2c7d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/power_manager_pkg.sv
@@ -0,0 +1,17 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+package power_manager_pkg;
+
+  typedef struct packed {logic pwrgate_ack_n;} power_manager_in_t;
+
+  typedef struct packed {
+    logic clkgate_en_n;
+    logic pwrgate_en_n;
+    logic isogate_en_n;
+    logic retentive_en_n;
+    logic rst_n;
+  } power_manager_out_t;
+
+endpackage
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/x-heep_packages.core b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/x-heep_packages.core
index 8a1a838d..6cbf61b0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/x-heep_packages.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/x-heep_packages.core
@@ -13,6 +13,7 @@ filesets:
     - addr_map_rule_pkg.sv
     - obi_pkg.sv
     - reg_pkg.sv
+    - power_manager_pkg.sv
     - core_v_mini_mcu_pkg.sv
     file_type: systemVerilogSource
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/memory_subsystem.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/memory_subsystem.sv.tpl
index 9e89348c..660b1b6a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/memory_subsystem.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/memory_subsystem.sv.tpl
@@ -19,33 +19,27 @@ module memory_subsystem
     input  obi_req_t  [NUM_BANKS-1:0] ram_req_i,
     output obi_resp_t [NUM_BANKS-1:0] ram_resp_o,
 
+    // power manager signals that goes to the ASIC macros
+    input logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] pwrgate_ni,
+    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] pwrgate_ack_no,
     input logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] set_retentive_ni
 );
 
-  localparam int NumWords = 32 * 1024 / 4;
-  localparam int AddrWidth = $clog2(32 * 1024);
-% if ram_numbanks_il != 0:
-  localparam int ilAddrWidth = $clog2(${ram_numbanks_il} * 32 * 1024);
-% endif
-
   logic [NUM_BANKS-1:0] ram_valid_q;
   // Clock-gating
   logic [NUM_BANKS-1:0] clk_cg;
-% if ram_numbanks_il != 0:
-  logic [NUM_BANKS-1:0][AddrWidth-3:0] ram_req_addr;
 
-  for (genvar i = 0; i < NUM_BANKS; i++) begin : gen_addr_napot
-    if (i >= NUM_BANKS - ${ram_numbanks_il}) begin
-      assign ram_req_addr[i] = {
-        ram_req_i[i].addr[ilAddrWidth-1:AddrWidth] -
-        core_v_mini_mcu_pkg::RAM${ram_numbanks_cont}_START_ADDRESS[ilAddrWidth-1:AddrWidth],
-        ram_req_i[i].addr[AddrWidth-1:${2+log_ram_numbanks_il}]
-      };
-    end else begin
-      assign ram_req_addr[i] = ram_req_i[i].addr[AddrWidth-1:2];
-    end
-  end
-% endif
+% for i, bank in enumerate(xheep.iter_ram_banks()):
+  logic [${bank.size().bit_length()-1 -2}-1:0] ram_req_addr_${i};
+% endfor
+
+% for i, bank in enumerate(xheep.iter_ram_banks()):
+<%
+  p1 = bank.size().bit_length()-1 + bank.il_level()
+  p2 = 2 + bank.il_level()
+%>
+  assign ram_req_addr_${i} = ram_req_i[${i}].addr[${p1}-1:${p2}];
+% endfor
 
   for (genvar i = 0; i < NUM_BANKS; i++) begin : gen_sram
 
@@ -66,27 +60,26 @@ module memory_subsystem
 
     assign ram_resp_o[i].gnt = ram_req_i[i].req;
     assign ram_resp_o[i].rvalid = ram_valid_q[i];
+  end
 
-    //Fixed to 8KWords per bank (32KB)
-    sram_wrapper #(
-        .NumWords (NumWords),
-        .DataWidth(32'd32)
-    ) ram_i (
-        .clk_i(clk_cg[i]),
-        .rst_ni(rst_ni),
-        .req_i(ram_req_i[i].req),
-        .we_i(ram_req_i[i].we),
-% if ram_numbanks_il == 0:
-        .addr_i(ram_req_i[i].addr[AddrWidth-1:2]),
-% else:
-        .addr_i(ram_req_addr[i]),
-% endif
-        .wdata_i(ram_req_i[i].wdata),
-        .be_i(ram_req_i[i].be),
-        .set_retentive_ni(set_retentive_ni[i]),
-        .rdata_o(ram_resp_o[i].rdata)
-    );
+%for i, bank in enumerate(xheep.iter_ram_banks()):
+  sram_wrapper #(
+      .NumWords (${bank.size() // 4}),
+      .DataWidth(32'd32)
+  ) ram${bank.name()}_i (
+      .clk_i(clk_cg[${i}]),
+      .rst_ni(rst_ni),
+      .req_i(ram_req_i[${i}].req),
+      .we_i(ram_req_i[${i}].we),
+      .addr_i(ram_req_addr_${i}),
+      .wdata_i(ram_req_i[${i}].wdata),
+      .be_i(ram_req_i[${i}].be),
+      .pwrgate_ni(pwrgate_ni[${i}]),
+      .pwrgate_ack_no(pwrgate_ack_no[${i}]),
+      .set_retentive_ni(set_retentive_ni[${i}]),
+      .rdata_o(ram_resp_o[${i}].rdata)
+  );
 
-  end
+%endfor
 
 endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv
index bb1c1d19..4fa663e6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv
@@ -50,6 +50,18 @@ module peripheral_subsystem
     output logic cio_sda_en_o,
 
     // SPI Host
+    output logic                               spi_sck_o,
+    output logic                               spi_sck_en_o,
+    output logic [spi_host_reg_pkg::NumCS-1:0] spi_csb_o,
+    output logic [spi_host_reg_pkg::NumCS-1:0] spi_csb_en_o,
+    output logic [                        3:0] spi_sd_o,
+    output logic [                        3:0] spi_sd_en_o,
+    input  logic [                        3:0] spi_sd_i,
+    output logic                               spi_intr_event_o,
+    output logic                               spi_rx_valid_o,
+    output logic                               spi_tx_ready_o,
+
+    // SPI 2 Host
     output logic                               spi2_sck_o,
     output logic                               spi2_sck_en_o,
     output logic [spi_host_reg_pkg::NumCS-1:0] spi2_csb_o,
@@ -291,11 +303,48 @@ module peripheral_subsystem
       .msip_o(msip_o)
   );
 
+  spi_host #(
+      .reg_req_t(reg_pkg::reg_req_t),
+      .reg_rsp_t(reg_pkg::reg_rsp_t)
+  ) spi_host_dma_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::SPI_HOST_IDX]),
+      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI_HOST_IDX]),
+      .alert_rx_i(),
+      .alert_tx_o(),
+      .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
+      .passthrough_o(),
+      .cio_sck_o(spi_sck_o),
+      .cio_sck_en_o(spi_sck_en_o),
+      .cio_csb_o(spi_csb_o),
+      .cio_csb_en_o(spi_csb_en_o),
+      .cio_sd_o(spi_sd_o),
+      .cio_sd_en_o(spi_sd_en_o),
+      .cio_sd_i(spi_sd_i),
+      .rx_valid_o(spi_rx_valid_o),
+      .tx_ready_o(spi_tx_ready_o),
+      .intr_error_o(),
+      .intr_spi_event_o(spi_intr_event_o)
+  );
 
-  assign cio_gpio_o = '0;
-  assign cio_gpio_en_o = '0;
-  assign gpio_intr = '0;
-  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_IDX] = '0;
+
+
+  gpio #(
+      .reg_req_t(reg_pkg::reg_req_t),
+      .reg_rsp_t(reg_pkg::reg_rsp_t)
+  ) gpio_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::GPIO_IDX]),
+      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_IDX]),
+      .gpio_in({cio_gpio_i, 8'b0}),
+      .gpio_out({cio_gpio_o, cio_gpio_unused}),
+      .gpio_tx_en_o({cio_gpio_en_o, cio_gpio_en_unused}),
+      .gpio_in_sync_o(),
+      .pin_level_interrupts_o({gpio_intr, gpio_int_unused}),
+      .global_interrupt_o()
+  );
 
   reg_to_tlul #(
       .req_t(reg_pkg::reg_req_t),
@@ -314,27 +363,34 @@ module peripheral_subsystem
       .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::I2C_IDX])
   );
 
-  assign i2c_tl_d2h = '0;
-  assign cio_scl_o = '0;
-  assign cio_scl_en_o = '0;
-  assign cio_sda_o = '0;
-  assign cio_sda_en_o = '0;
-  assign i2c_intr_fmt_watermark = '0;
-  assign i2c_intr_rx_watermark = '0;
-  assign i2c_intr_fmt_overflow = '0;
-  assign i2c_intr_rx_overflow = '0;
-  assign i2c_intr_nak = '0;
-  assign i2c_intr_scl_interference = '0;
-  assign i2c_intr_sda_interference = '0;
-  assign i2c_intr_stretch_timeout = '0;
-  assign i2c_intr_sda_unstable = '0;
-  assign i2c_intr_trans_complete = '0;
-  assign i2c_intr_tx_empty = '0;
-  assign i2c_intr_tx_nonempty = '0;
-  assign i2c_intr_tx_overflow = '0;
-  assign i2c_intr_acq_overflow = '0;
-  assign i2c_intr_ack_stop = '0;
-  assign i2c_intr_host_timeout = '0;
+  i2c i2c_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .tl_i(i2c_tl_h2d),
+      .tl_o(i2c_tl_d2h),
+      .cio_scl_i,
+      .cio_scl_o,
+      .cio_scl_en_o,
+      .cio_sda_i,
+      .cio_sda_o,
+      .cio_sda_en_o,
+      .intr_fmt_watermark_o(i2c_intr_fmt_watermark),
+      .intr_rx_watermark_o(i2c_intr_rx_watermark),
+      .intr_fmt_overflow_o(i2c_intr_fmt_overflow),
+      .intr_rx_overflow_o(i2c_intr_rx_overflow),
+      .intr_nak_o(i2c_intr_nak),
+      .intr_scl_interference_o(i2c_intr_scl_interference),
+      .intr_sda_interference_o(i2c_intr_sda_interference),
+      .intr_stretch_timeout_o(i2c_intr_stretch_timeout),
+      .intr_sda_unstable_o(i2c_intr_sda_unstable),
+      .intr_trans_complete_o(i2c_intr_trans_complete),
+      .intr_tx_empty_o(i2c_intr_tx_empty),
+      .intr_tx_nonempty_o(i2c_intr_tx_nonempty),
+      .intr_tx_overflow_o(i2c_intr_tx_overflow),
+      .intr_acq_overflow_o(i2c_intr_acq_overflow),
+      .intr_ack_stop_o(i2c_intr_ack_stop),
+      .intr_host_timeout_o(i2c_intr_host_timeout)
+  );
 
   reg_to_tlul #(
       .req_t(reg_pkg::reg_req_t),
@@ -362,29 +418,56 @@ module peripheral_subsystem
       .intr_timer_expired_1_0_o(rv_timer_3_intr_o)
   );
 
-  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI2_IDX]    = '0;
-  assign spi2_sck_o                                           = '0;
-  assign spi2_sck_en_o                                        = '0;
-  assign spi2_csb_o                                           = '0;
-  assign spi2_csb_en_o                                        = '0;
-  assign spi2_sd_o                                            = '0;
-  assign spi2_sd_en_o                                         = '0;
-  assign spi2_intr_event                                      = '0;
+  spi_host #(
+      .reg_req_t(reg_pkg::reg_req_t),
+      .reg_rsp_t(reg_pkg::reg_rsp_t)
+  ) spi2_host (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::SPI2_IDX]),
+      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI2_IDX]),
+      .alert_rx_i(),
+      .alert_tx_o(),
+      .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
+      .passthrough_o(),
+      .cio_sck_o(spi2_sck_o),
+      .cio_sck_en_o(spi2_sck_en_o),
+      .cio_csb_o(spi2_csb_o),
+      .cio_csb_en_o(spi2_csb_en_o),
+      .cio_sd_o(spi2_sd_o),
+      .cio_sd_en_o(spi2_sd_en_o),
+      .cio_sd_i(spi2_sd_i),
+      .rx_valid_o(),
+      .tx_ready_o(),
+      .intr_error_o(),
+      .intr_spi_event_o(spi2_intr_event)
+  );
 
   assign peripheral_slv_rsp[core_v_mini_mcu_pkg::PDM2PCM_IDX] = '0;
-  assign pdm2pcm_clk_o                                        = '0;
+  assign pdm2pcm_clk_o = '0;
 
-  assign pdm2pcm_clk_en_o                                     = 1;
+  assign pdm2pcm_clk_en_o = 1;
 
-  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::I2S_IDX]     = '0;
-
-  assign i2s_sck_oe_o                                         = 1'b0;
-  assign i2s_sck_o                                            = 1'b0;
-  assign i2s_ws_oe_o                                          = 1'b0;
-  assign i2s_ws_o                                             = 1'b0;
-  assign i2s_sd_oe_o                                          = 1'b0;
-  assign i2s_sd_o                                             = 1'b0;
-  assign i2s_intr_event                                       = 1'b0;
-  assign i2s_rx_valid_o                                       = 1'b0;
+  i2s #(
+      .reg_req_t(reg_pkg::reg_req_t),
+      .reg_rsp_t(reg_pkg::reg_rsp_t)
+  ) i2s_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::I2S_IDX]),
+      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::I2S_IDX]),
+
+      .i2s_sck_o(i2s_sck_o),
+      .i2s_sck_oe_o(i2s_sck_oe_o),
+      .i2s_sck_i(i2s_sck_i),
+      .i2s_ws_o(i2s_ws_o),
+      .i2s_ws_oe_o(i2s_ws_oe_o),
+      .i2s_ws_i(i2s_ws_i),
+      .i2s_sd_o(i2s_sd_o),
+      .i2s_sd_oe_o(i2s_sd_oe_o),
+      .i2s_sd_i(i2s_sd_i),
+      .intr_i2s_event_o(i2s_intr_event),
+      .i2s_rx_valid_o(i2s_rx_valid_o)
+  );
 
 endmodule : peripheral_subsystem
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
index 71215d04..4025cd88 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/peripheral_subsystem.sv.tpl
@@ -50,6 +50,18 @@ module peripheral_subsystem
     output logic cio_sda_en_o,
 
     // SPI Host
+    output logic                               spi_sck_o,
+    output logic                               spi_sck_en_o,
+    output logic [spi_host_reg_pkg::NumCS-1:0] spi_csb_o,
+    output logic [spi_host_reg_pkg::NumCS-1:0] spi_csb_en_o,
+    output logic [                        3:0] spi_sd_o,
+    output logic [                        3:0] spi_sd_en_o,
+    input  logic [                        3:0] spi_sd_i,
+    output logic                               spi_intr_event_o,
+    output logic                               spi_rx_valid_o,
+    output logic                               spi_tx_ready_o,
+
+    // SPI 2 Host
     output logic                               spi2_sck_o,
     output logic                               spi2_sck_en_o,
     output logic [spi_host_reg_pkg::NumCS-1:0] spi2_csb_o,
@@ -306,6 +318,49 @@ module peripheral_subsystem
 % endif
 % endfor
 
+% for peripheral in peripherals.items():
+% if peripheral[0] in ("spi_host"):
+% if peripheral[1]['is_included'] in ("yes"):
+  spi_host #(
+      .reg_req_t(reg_pkg::reg_req_t),
+      .reg_rsp_t(reg_pkg::reg_rsp_t)
+  ) spi_host_dma_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::SPI_HOST_IDX]),
+      .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI_HOST_IDX]),
+      .alert_rx_i(),
+      .alert_tx_o(),
+      .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
+      .passthrough_o(),
+      .cio_sck_o(spi_sck_o),
+      .cio_sck_en_o(spi_sck_en_o),
+      .cio_csb_o(spi_csb_o),
+      .cio_csb_en_o(spi_csb_en_o),
+      .cio_sd_o(spi_sd_o),
+      .cio_sd_en_o(spi_sd_en_o),
+      .cio_sd_i(spi_sd_i),
+      .rx_valid_o(spi_rx_valid_o),
+      .tx_ready_o(spi_tx_ready_o),
+      .intr_error_o(),
+      .intr_spi_event_o(spi_intr_event_o)
+  );
+% else:
+  assign peripheral_slv_rsp[core_v_mini_mcu_pkg::SPI_HOST_IDX] = '0;
+  assign spi_sck_o = '0;
+  assign spi_sck_en_o = '0;
+  assign spi_csb_o = '0;
+  assign spi_csb_en_o = '0;
+  assign spi_sd_o = '0;
+  assign spi_sd_en_o = '0;
+  assign spi_intr_event_o = '0;
+  assign spi_rx_valid_o = '0;
+  assign spi_tx_ready_o = '0;
+% endif
+% endif
+% endfor
+
+
 
 % for peripheral in peripherals.items():
 % if peripheral[0] in ("gpio"):
@@ -491,7 +546,7 @@ module peripheral_subsystem
       .reg_req_t(reg_pkg::reg_req_t),
       .reg_rsp_t(reg_pkg::reg_rsp_t)
   ) pdm2pcm_i (
-      .clk_i,
+      .clk_i(clk_cg),
       .rst_ni,
       .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::PDM2PCM_IDX]),
       .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::PDM2PCM_IDX]),
@@ -514,7 +569,7 @@ module peripheral_subsystem
       .reg_req_t(reg_pkg::reg_req_t),
       .reg_rsp_t(reg_pkg::reg_rsp_t)
   ) i2s_i (
-      .clk_i,
+      .clk_i(clk_cg),
       .rst_ni,
       .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::I2S_IDX]),
       .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::I2S_IDX]),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl
index b7dbbfdc..19bb8622 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl
@@ -157,8 +157,8 @@ module system_bus
 
   // Internal slave requests
   assign error_slave_req = int_slave_req[core_v_mini_mcu_pkg::ERROR_IDX];
-% for bank in range(ram_numbanks):
-  assign ram_req_o[${bank}] = int_slave_req[core_v_mini_mcu_pkg::RAM${bank}_IDX];
+% for bank in xheep.iter_ram_banks():
+  assign ram_req_o[${bank.name()}] = int_slave_req[core_v_mini_mcu_pkg::RAM${bank.name()}_IDX];
 % endfor
   assign debug_slave_req_o = int_slave_req[core_v_mini_mcu_pkg::DEBUG_IDX];
   assign ao_peripheral_slave_req_o = int_slave_req[core_v_mini_mcu_pkg::AO_PERIPHERAL_IDX];
@@ -175,8 +175,8 @@ module system_bus
 
   // Internal slave responses
   assign int_slave_resp[core_v_mini_mcu_pkg::ERROR_IDX] = error_slave_resp;
-% for bank in range(ram_numbanks):
-  assign int_slave_resp[core_v_mini_mcu_pkg::RAM${bank}_IDX] = ram_resp_i[${bank}];
+% for bank in xheep.iter_ram_banks():
+  assign int_slave_resp[core_v_mini_mcu_pkg::RAM${bank.name()}_IDX] = ram_resp_i[${bank.name()}];
 % endfor
   assign int_slave_resp[core_v_mini_mcu_pkg::DEBUG_IDX] = debug_slave_resp_i;
   assign int_slave_resp[core_v_mini_mcu_pkg::AO_PERIPHERAL_IDX] = ao_peripheral_slave_resp_i;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_xbar.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_xbar.sv.tpl
index 2731cb4e..18cbbe4d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_xbar.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_xbar.sv.tpl
@@ -38,7 +38,7 @@ module system_xbar
   localparam int unsigned RESP_AGG_DATA_WIDTH = 32;
 
   //Address Decoder
-% if ram_numbanks_il == 0:
+% if not xheep.has_il_ram():
   logic [XBAR_NMASTER-1:0][LOG_XBAR_NSLAVE-1:0] port_sel;
 % else:
   logic [XBAR_NMASTER-1:0][LOG_XBAR_NSLAVE-1:0] port_sel, pre_port_sel;
@@ -75,7 +75,7 @@ module system_xbar
       ) addr_decode_i (
           .addr_i(master_req_i[i].addr),
           .addr_map_i,
-% if ram_numbanks_il == 0:
+% if not xheep.has_il_ram():
           .idx_o(port_sel[i]),
 % else:
           .idx_o(pre_port_sel[i]),
@@ -86,21 +86,21 @@ module system_xbar
           .default_idx_i
       );
     end
-% if ram_numbanks_il != 0:
+% if xheep.has_il_ram():
 
     localparam ZERO = 32'h0;
 
     for (genvar j = 0; j < XBAR_NMASTER; j++) begin : gen_addr_napot
       always_comb begin
-        port_sel[j] = 1;
-        post_master_req_addr[j] = '0;
-        if (pre_port_sel[j] == NUM_BANKS[LOG_XBAR_NSLAVE-1:0] - (NUM_BANKS_IL[LOG_XBAR_NSLAVE-1:0]-1)) begin
-            port_sel[j] = NUM_BANKS[LOG_XBAR_NSLAVE-1:0] - (NUM_BANKS_IL[LOG_XBAR_NSLAVE-1:0]-1) + {ZERO[LOG_XBAR_NSLAVE-${1+log_ram_numbanks_il}:0],master_req_i[j].addr[${1+log_ram_numbanks_il}:2]};
-          post_master_req_addr[j] = {master_req_i[j].addr[31:${2+log_ram_numbanks_il}], ${2+log_ram_numbanks_il}'h0};
-        end else begin
-          port_sel[j] = pre_port_sel[j];
-          post_master_req_addr[j] = master_req_i[j].addr;
+        port_sel[j] = pre_port_sel[j];
+        post_master_req_addr[j] = master_req_i[j].addr;
+% for i, group in enumerate(xheep.iter_il_groups()):
+
+        if (pre_port_sel[j] == RAM_IL${i}_IDX[LOG_XBAR_NSLAVE-1:0]) begin
+          port_sel[j] = RAM_IL${i}_IDX[LOG_XBAR_NSLAVE-1:0] + {ZERO[LOG_XBAR_NSLAVE-${1+group.n.bit_length()}:0],master_req_i[j].addr[${group.n.bit_length()-1 +1}:2]};
+          post_master_req_addr[j] = {master_req_i[j].addr[31:${2+group.n.bit_length()-1}], ${2+group.n.bit_length()-1}'h0};
         end
+% endfor
       end
     end
 % endif    
@@ -113,7 +113,7 @@ module system_xbar
         req: master_req_i[i].req,
         we: master_req_i[i].we,
         be: master_req_i[i].be,
-  % if ram_numbanks_il == 0:
+  % if not xheep.has_il_ram():
         addr: master_req_i[i].addr,
   % else:
         addr: post_master_req_addr[i],
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc
index be620356..d3723fef 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/nexys/pin_assign.xdc
@@ -13,9 +13,8 @@ set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {rst_led_o}]
 set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {clk_led_o}];
 set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {exit_valid_o}];
 set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {exit_value_o}];
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_OBUF]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_out_OBUF]
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_led_OBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_led_o_OBUF]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_o_OBUF]
 
 ##Switches
 set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {execute_from_flash_i}]; #Sch=sw[1]
@@ -79,5 +78,24 @@ set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[2]}
 set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {gpio_io[3]}]; #IO_L10N_T1_D15_14 Sch=btnr
 set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {gpio_io[4]}]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
 
+##7 segment display
+set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports { gpio_io[11] }];
+set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports { gpio_io[12] }];
+set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports { gpio_io[13] }];
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports { gpio_io[14] }];
+set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports { pdm2pcm_clk_io }];
+set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports { pdm2pcm_pdm_io }];
+set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports { i2s_sck_io }];
+set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports { i2s_ws_io }];
+set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports { i2s_sd_io }];
+set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[15] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
+set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { gpio_io[16] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
+set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { gpio_io[17] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
+set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { spi2_csb_o[0] }]; #IO_L19P_T3_A22_15 Sch=an[3]
+set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { spi2_csb_o[1] }]; #IO_L8N_T1_D12_14 Sch=an[4]
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { spi2_sck_o }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
+set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { spi2_sd_io[0] }]; #IO_L23P_T3_35 Sch=an[6]
+
+
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc
index ed3a6e89..38e2f6b3 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/pynq-z2/constraints.xdc
@@ -1 +1 @@
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];
+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 5} [get_ports {clk_i}];
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
new file mode 100644
index 00000000..4b523cdf
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/constraints/zcu104/pin_assign.xdc
@@ -0,0 +1,99 @@
+# Copyright 2022 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# CLOCK
+set_property -dict {PACKAGE_PIN AH18 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
+set_property -dict {PACKAGE_PIN AH17 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i]
+
+# RESET
+set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports rst_i]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_i]
+
+# LEDS
+set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports rst_led_o]
+set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports clk_led_o]
+set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
+set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
+
+# SWITCHES
+set_property -dict {PACKAGE_PIN E4 IOSTANDARD LVCMOS33} [get_ports execute_from_flash_i]
+set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports boot_select_i]
+
+# FLASH
+# QSPI
+# Q0 / MOSI
+# Q1 / MISO
+# Q2 / nWP
+# Q3 / nHLD
+set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS33} [get_ports spi_flash_csb_o]
+set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS33} [get_ports spi_flash_sck_o]
+set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[0]}]
+set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[1]}]
+set_property -dict {PACKAGE_PIN M8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[2]}]
+set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS33} [get_ports {spi_flash_sd_io[3]}]
+
+# UART
+set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports uart_tx_o]
+set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports uart_rx_i]
+
+# JTAG
+set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i]
+set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o]
+set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i]
+set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i]
+set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni]
+
+# I2C
+set_property -dict {PACKAGE_PIN J7 IOSTANDARD LVCMOS33} [get_ports i2c_scl_io]
+set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports i2c_sda_io]
+
+## The following pins are sent to the FMC connector, using the LA pins as single-ended.
+## The bank only supports up to 1.8 V.
+
+# SPI SD
+set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports spi_csb_o]
+set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports spi_sck_o]
+set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[0]}]
+set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[1]}]
+set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[2]}]
+set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports {spi_sd_io[3]}]
+
+# GPIOs
+set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[0]}]
+set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[1]}]
+set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[2]}]
+set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports {gpio_io[3]}]
+set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS18} [get_ports {gpio_io[4]}]
+set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[5]}]
+set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[6]}]
+set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports {gpio_io[7]}]
+set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[8]}]
+set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports {gpio_io[9]}]
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[10]}]
+set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports {gpio_io[11]}]
+set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[12]}]
+set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports {gpio_io[13]}]
+set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[14]}]
+set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports {gpio_io[15]}]
+set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports {gpio_io[16]}]
+set_property -dict {PACKAGE_PIN B8 IOSTANDARD LVCMOS18} [get_ports {gpio_io[17]}]
+
+# PDM2PCM
+set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_clk_io]
+set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports pdm2pcm_pdm_io]
+
+# I2S
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18} [get_ports i2s_sck_io]
+set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports i2s_ws_io]
+set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports i2s_sd_io]
+
+# SPI2
+set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_o[0]}]
+set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS18} [get_ports {spi2_csb_o[1]}]
+set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports spi2_sck_o]
+set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[0]}]
+set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[1]}]
+set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[2]}]
+set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports {spi2_sd_io[3]}]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_inout_xilinx.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_inout_xilinx.sv
index 69ee4e7e..5c68364b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_inout_xilinx.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_inout_xilinx.sv
@@ -3,7 +3,8 @@
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 module pad_cell_inout #(
-    parameter PADATTR = 16
+    parameter PADATTR = 16,
+    parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP
 ) (
     input logic pad_in_i,
     input logic pad_oe_i,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_input_xilinx.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_input_xilinx.sv
index 989aad1c..470a651a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_input_xilinx.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_input_xilinx.sv
@@ -3,7 +3,8 @@
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 module pad_cell_input #(
-    parameter PADATTR = 16
+    parameter PADATTR = 16,
+    parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP
 ) (
     input logic pad_in_i,
     input logic pad_oe_i,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_output_xilinx.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_output_xilinx.sv
index 3620ad1b..43592acd 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_output_xilinx.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/pad_cell_output_xilinx.sv
@@ -3,7 +3,8 @@
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 module pad_cell_output #(
-    parameter PADATTR = 16
+    parameter PADATTR = 16,
+    parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP
 ) (
     input logic pad_in_i,
     input logic pad_oe_i,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv
index 35165b88..2893d666 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/prim_xilinx_clk.sv
@@ -9,15 +9,12 @@ module xilinx_clk_gating (
     output logic clk_o
 );
 
-  logic clk_en;
-
-  // Use a latch based clock gate instead of BUFGCE. Otherwise we quickly run out of BUFGCTRL cells on the FPGAs.
-  always_latch begin
-    if (clk_i == 1'b0) clk_en <= en_i | test_en_i;
-  end
-
-  assign clk_o = clk_i & clk_en;
-
+  // In Zynq7000, just bypass the clock gating because there are not enough BUFGs that can be 
+  // cascaded with the BUFG of the MMCM.
+  // In the Zynq UltraScale+, it can be implemented as BUFGCE without trouble, since there
+  // are > 500 BUFGCEs and the rules for cascading are more relaxed.
+  // NOTE: This **cannot** be substituted by a latch+and
+  assign clk_o = clk_i;
 
 endmodule
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl
deleted file mode 100644
index 7ba6d975..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl
+++ /dev/null
@@ -1,27 +0,0 @@
-
-set ipName xilinx_mem_gen_0
-
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name $ipName
-
-set_property -dict [list CONFIG.Enable_32bit_Address {false} \
-                        CONFIG.Use_Byte_Write_Enable {true}  \
-                        CONFIG.Byte_Size {8}  \
-                        CONFIG.Algorithm {Minimum_Area}  \
-                        CONFIG.Primitive {2kx9}  \
-                        CONFIG.Write_Width_A {32}  \
-                        CONFIG.Write_Depth_A {8192}  \
-                        CONFIG.Read_Width_A {32}  \
-                        CONFIG.Enable_A {Use_ENA_Pin}  \
-                        CONFIG.Write_Width_B {32}  \
-                        CONFIG.Read_Width_B {32}  \
-                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
-                        CONFIG.Use_RSTA_Pin {false}  \
-                        CONFIG.EN_SAFETY_CKT {false}] [get_ips $ipName]
-
-#generate_target {instantiation_template} [get_ips $ipName]
-
-#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
-
-create_ip_run [get_ips $ipName]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl.tpl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl.tpl
new file mode 100644
index 00000000..e8e6cbb4
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/generate_sram.tcl.tpl
@@ -0,0 +1,50 @@
+% for num_words in xheep.iter_bank_numwords():
+
+set ipName xilinx_mem_gen_${num_words}
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name $ipName
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \\
+
+                        CONFIG.Use_Byte_Write_Enable {true}  \\
+
+                        CONFIG.Byte_Size {8}  \\
+
+                        CONFIG.Algorithm {Minimum_Area}  \\
+
+                        CONFIG.Primitive {2kx9}  \\
+
+                        CONFIG.Write_Width_A {32}  \\
+
+                        CONFIG.Write_Depth_A {${num_words}}  \\
+
+                        CONFIG.Read_Width_A {32}  \\
+
+                        CONFIG.Enable_A {Use_ENA_Pin}  \\
+
+                        CONFIG.Write_Width_B {32}  \\
+
+                        CONFIG.Read_Width_B {32}  \\
+
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \\
+
+                        CONFIG.Use_RSTA_Pin {false}  \\
+
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips $ipName]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips $ipName]
+
+% endfor
+
+<%ips = ""
+for num_words in xheep.iter_bank_numwords():
+    ips += f" xilinx_mem_gen_{num_words}_synth_1"%>
+launch_runs -jobs 8 ${ips}
+
+% for num_words in xheep.iter_bank_numwords():
+wait_on_run xilinx_mem_gen_${num_words}_synth_1
+% endfor
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl
deleted file mode 100644
index 544cd11b..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/nexys/set_board.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Select board
-set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
-set_property -name "board_part" -value "digilentinc.com:nexys-a7-100t:part0:1.3" -objects [current_project]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl
deleted file mode 100644
index f16f754f..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/pynq-z2/set_board.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Select board
-set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
-set_property -name "board_part" -value "tul.com.tw:pynq-z2:part0:1.0" -objects [current_project]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl b/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl
deleted file mode 100644
index 0108a4c8..00000000
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/scripts/zcu104/set_board.tcl
+++ /dev/null
@@ -1,3 +0,0 @@
-# Select board
-set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
-set_property -name "board_part" -value "xilinx.com:zcu104:part0:1.0" -objects [current_project]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/sram_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/sram_wrapper.sv.tpl
similarity index 66%
rename from hw/vendor/esl_epfl_x_heep/hw/fpga/sram_wrapper.sv
rename to hw/vendor/esl_epfl_x_heep/hw/fpga/sram_wrapper.sv.tpl
index 44fb5687..6d518136 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/sram_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/sram_wrapper.sv.tpl
@@ -22,19 +22,32 @@ module sram_wrapper #(
     input logic [AddrWidth-1:0] addr_i,
     input logic [31:0] wdata_i,
     input logic [3:0] be_i,
-    input logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] set_retentive_ni,
+    // power manager signals that goes to the ASIC macros
+    input logic pwrgate_ni,
+    output logic pwrgate_ack_no,
+    input logic set_retentive_ni,
     // output ports
     output logic [31:0] rdata_o
 );
 
-  xilinx_mem_gen_0 tc_ram_i (
-      .clka (clk_i),
-      .ena  (req_i),
-      .wea  ({4{req_i & we_i}} & be_i),
-      .addra(addr_i),
-      .dina (wdata_i),
-      // output ports
-      .douta(rdata_o)
-  );
+assign pwrgate_ack_no = pwrgate_ni;
 
+<%el = ""%>
+% for num_words in xheep.iter_bank_numwords():
+  ${el}if (NumWords == 32'd${num_words}) begin
+    xilinx_mem_gen_${num_words} tc_ram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+    );
+  end
+<%el = "else "%>
+% endfor
+  else begin
+    $error("Bank size not generated.");
+  end
 endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson
index d37d92f7..58f6d3a0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson
@@ -33,13 +33,24 @@
         { bits: "31:0", name: "PTR_ADDR", desc: "Address data pointer (word aligned) - used only in Address mode" }
       ]
     },
-    { name:     "SIZE",
-      desc:     "Number of bytes to copy - Once a value is written, the copy starts",
+    { name:     "SIZE_D1",
+      desc:     "Number of bytes to copy from, defined with respect to the first dimension - Once a value is written, the copy starts",
       swaccess: "rw",
       hwaccess: "hro",
       hwqe:     "true", // enable `qe` latched signal of software write pulse
+      // Dimensioned to 16 bits to allow for 64kB transfers on 1D
       fields: [
-        { bits: "31:0", name: "SIZE", desc: "DMA counter and start" }
+        { bits: "15:0", name: "SIZE", desc: "DMA counter D1 and start" }
+      ]
+    },
+    { name:     "SIZE_D2",
+      desc:     "Number of bytes to copy from, defined with respect to the second dimension",
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse
+      // Dimensioned to 16 bits to allow for 64kB transfers on 2D
+      fields: [
+        { bits: "15:0", name: "SIZE", desc: "DMA counter D2" }
       ]
     },
     { name:     "STATUS",
@@ -50,23 +61,56 @@
       hwre:     "true", // enable `re` latched signal of software read pulse
       resval:   1,
       fields: [
-        { bits: "0", name: "READY", desc: "Transaction iss done"},
+        { bits: "0", name: "READY", desc: "Transaction is done"},
         { bits: "1", name: "WINDOW_DONE", desc: "set if DMA is copying second half"},
       ]
     },
-    { name:     "PTR_INC",
-      desc:     "Increment number of src/dst pointer every time a word is copied",
+    { name:     "SRC_PTR_INC_D1",
+      desc:     "Increment the D1 source pointer every time a word is copied",
       swaccess: "rw",
       hwaccess: "hro",
+      // Dimensioned to allow a maximum of a 15 element stride for a data_type_word case
       fields: [
-        { bits: "7:0", 
-          name: "SRC_PTR_INC", 
-          desc: "Source pointer increment",
+        { bits: "5:0", 
+          name: "INC", 
+          desc: "Source pointer d1 increment",
           resval:4
-        },
-        { bits: "15:8", 
-          name: "DST_PTR_INC", 
-          desc: "Destination pointer increment",
+        }
+      ]
+    },
+    { name:     "SRC_PTR_INC_D2",
+      desc:     "Increment the D2 source pointer every time a word is copied",
+      swaccess: "rw",
+      hwaccess: "hro",
+      // Dimensioned to allow a maximum of 15 element stride for a data_type_word
+      fields: [
+        { bits: "22:0", 
+          name: "INC", 
+          desc: "Source pointer d2 increment",
+          resval:4
+        }
+      ]
+    },
+    { name:     "DST_PTR_INC_D1",
+      desc:     "Increment the D1 destination pointer every time a word is copied",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "5:0", 
+          name: "INC", 
+          desc: "Destination pointer d1 increment",
+          resval:4
+        }
+      ]
+    },
+    { name:     "DST_PTR_INC_D2",
+      desc:     "Increment the D2 destination pointer every time a word is copied",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "22:0", 
+          name: "INC", 
+          desc: "Destination pointer d2 increment",
           resval:4
         }
       ]
@@ -87,8 +131,25 @@
         }
       ]
     },
-    { name:     "DATA_TYPE",
-      desc:     '''Width/type of the data to transfer''',
+    { name:     "SRC_DATA_TYPE",
+      desc:     '''Width/type of the source data to transfer''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:   0,
+      fields: [
+        { bits: "1:0", name: "DATA_TYPE", 
+          desc: "Data type",
+          enum: [
+            { value: "0", name: "DMA_32BIT_WORD", desc: "Transfers 32 bits"},
+            { value: "1", name: "DMA_16BIT_WORD", desc: "Transfers 16 bits"},
+            { value: "2", name: "DMA_8BIT_WORD" , desc: "Transfers  8 bits"},
+            { value: "3", name: "DMA_8BIT_WORD_2",desc: "Transfers  8 bits"},
+          ]
+        }
+      ]
+    },
+    { name:     "DST_DATA_TYPE",
+      desc:     '''Width/type of the destination data to transfer''',
       swaccess: "rw",
       hwaccess: "hro",
       resval:   0,
@@ -104,6 +165,22 @@
         }
       ]
     },
+    {
+      name:     "SIGN_EXT",
+      desc:     '''Is the data to be sign extended? (Checked only if the dst data type is wider than the src data type)''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:   0,
+      fields: [
+        { bits: "0", name: "SIGNED", 
+          desc: "Extend the sign to the destination data",
+          enum: [
+            { value: "0", name: "NO_EXTEND", desc: "Does not extend the sign"},
+            { value: "1", name: "EXTEND", desc: "Extends the sign"},
+          ]
+        }
+      ]
+    },
     { name:     "MODE",
       desc:     '''Set the operational mode of the DMA''',
       swaccess: "rw",
@@ -119,13 +196,71 @@
         }
       ]
     },
+    { name:     "DIM_CONFIG",
+      desc:     '''Set the dimensionality of the DMA''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:   0,
+      fields: [
+        { bits: "0", name: "DMA_DIM", desc: "DMA transfer dimensionality"}
+      ]
+    },
+    { name:     "DIM_INV",
+      desc:     '''DMA dimensionality inversion selector''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:   0,
+      fields: [
+        { bits: "0", name: "SEL", desc: "DMA dimensionality inversion, used to perform transposition"}
+      ]
+    },
+    { name:     "PAD_TOP",
+      desc:     '''Set the top padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Top margin padding (2D)"}
+      ]
+    },
+    { name:     "PAD_BOTTOM",
+      desc:     '''Set the bottom padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Bottom margin padding (2D)"}
+      ]
+    },
+    { name:     "PAD_RIGHT",
+      desc:     '''Set the right padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Right margin padding (1D/2D)"}
+      ]
+    },
+    { name:     "PAD_LEFT",
+      desc:     '''Set the left padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Left margin padding (1D/2D)"}
+      ]
+    },
     { name:    "WINDOW_SIZE",
       desc:    '''Will trigger a every "WINDOW_SIZE" writes
                   Set to 0 to disable.''',
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "31:0", name: "WINDOW_SIZE", desc: ""}
+        { bits: "12:0", name: "WINDOW_SIZE", desc: ""}
       ]
     },
     { name:    "WINDOW_COUNT",
@@ -136,7 +271,7 @@
       hwaccess: "hrw",
       resval: 0,
       fields: [
-        { bits: "31:0", name: "WINDOW_COUNT", desc: "Number of windows transferred in the transaction" }
+        { bits: "7:0", name: "WINDOW_COUNT", desc: "Number of windows transferred in the transaction" }
       ]
     },
     { name:    "INTERRUPT_EN",
@@ -148,6 +283,28 @@
         { bits: "0", name: "TRANSACTION_DONE", desc: "Enables transaction done interrupt" }
         { bits: "1", name: "WINDOW_DONE", desc: "Enables window done interrupt" }
       ]
+    },
+    { name:    "TRANSACTION_IFR",
+      desc:    '''Interrupt Flag Register for transactions''',
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext:    "true",
+      hwre:     "true", // latched signal of software write pulse
+      resval:        0,
+      fields: [
+        { bits: "0", name: "FLAG", desc: "Set for transaction done interrupt" }
+      ]
+    },
+    { name:    "WINDOW_IFR",
+      desc:    '''Interrupt Flag Register for windows''',
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext:    "true",
+      hwre:     "true", // latched signal of software write pulse
+      resval:        0,
+      fields: [
+        { bits: "0", name: "FLAG", desc: "Set for window done interrupt" }
+      ]
     }
    ]
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core
index 0a06c35d..86255b7a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core
@@ -1,7 +1,7 @@
 CAPI=2:
 
 name: "x-heep:ip:dma"
-description: "core-v-mini-mcu dma peripheral"
+description: "core-v-mini-mcu dma channel"
 
 # Copyright 2021 OpenHW Group
 # Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv
index c4f5e2ea..4bfe0219 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv
@@ -1,8 +1,10 @@
-// Copyright 2022 EPFL
-// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+/*
+ * Copyright 2022 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ */
 
-// DMA assume a read request is not granted before previous request rvalid is asserted
+/* DMA assume a read request is not granted before previous request rvalid is asserted */
 
 module dma #(
     parameter int unsigned FIFO_DEPTH = 4,
@@ -15,6 +17,8 @@ module dma #(
     input logic clk_i,
     input logic rst_ni,
 
+    input logic ext_dma_stop_i,
+
     input  reg_req_t reg_req_i,
     output reg_rsp_t reg_rsp_o,
 
@@ -41,14 +45,15 @@ module dma #(
   dma_reg2hw_t                       reg2hw;
   dma_hw2reg_t                       hw2reg;
 
+  logic        [               31:0] src_ptr_reg;
   logic        [               31:0] read_ptr_reg;
   logic        [               31:0] addr_ptr_reg;
   logic        [               31:0] read_ptr_valid_reg;
   logic        [               31:0] write_ptr_reg;
   logic        [               31:0] write_address;
-  logic        [               31:0] dma_cnt;
   logic        [               31:0] dma_addr_cnt;
-  logic        [                2:0] dma_cnt_dec;
+  logic        [                2:0] dma_src_cnt_du;
+  logic        [                2:0] dma_dst_cnt_du;
   logic                              dma_start;
   logic                              dma_done;
   logic                              dma_window_event;
@@ -86,6 +91,70 @@ module dma #(
   logic                              data_out_rvalid;
   logic        [               31:0] data_out_rdata;
 
+  /* Sign extension signals */
+  logic                              sign_extend;
+
+  /* 2D signals */
+
+  /* Dimensionality configuration */
+  logic                              dma_conf_1d;  // Dimensionality configuration: 0-> 1D, 1-> 2D
+  logic                              dma_conf_2d;  // Dimensionality configuration: 0-> 1D, 1-> 2D
+
+  /* Counters */
+  logic        [               16:0] dma_src_cnt_d1;  // d1 src counter
+  logic        [               16:0] dma_src_cnt_d2;  // d2 src counter
+  logic        [               16:0] dma_dst_cnt_d1;  // d2 dst counter
+
+  /* Increments */
+  logic        [                5:0] dma_src_d1_inc;  // d1 source increment
+  logic        [               22:0] dma_src_d2_inc;  // d2 source increment
+  logic        [                5:0] dma_dst_d1_inc;  // d1 destination increment
+  logic        [               22:0] dma_dst_d2_inc;  // d2 destination increment
+
+  /* Flags */
+  logic                              pad_fifo_on;  // Padding flag for FIFO
+  logic                              pad_cnt_on;  // Padding flag for counters
+  logic                              read_ptr_update_sel;  // Select the read pointer update source
+
+  /* Padding FSM conditions */
+  logic                              idle_to_left_ex;
+  logic                              idle_to_top_ex;
+  logic                              idle_to_right_ex;
+  logic                              idle_to_bottom_ex;
+  logic                              top_ex_to_top_dn;
+  logic                              top_ex_to_left_ex;
+  logic                              top_dn_to_right_ex;
+  logic                              top_dn_to_bottom_ex;
+  logic                              top_dn_to_idle;
+  logic                              left_ex_to_left_dn;
+  logic                              left_dn_to_left_ex;
+  logic                              left_dn_to_right_ex;
+  logic                              left_dn_to_bottom_ex;
+  logic                              left_dn_to_idle;
+  logic                              right_ex_to_right_dn;
+  logic                              right_ex_to_left_ex;
+  logic                              right_dn_to_right_ex;
+  logic                              right_dn_to_idle;
+  logic                              right_ex_to_bottom_ex;
+  logic                              bottom_ex_to_idle;
+
+  /* Padding synchronization signals */
+  logic                              data_in_rvalid_virt;
+  logic                              data_in_rvalid_virt_n;
+  logic                              data_in_rvalid_virt_n_n;
+  logic                              data_in_gnt_virt;
+  logic                              data_in_gnt_virt_n;
+  logic                              data_in_gnt_virt_n_n;
+
+  /* Interrupt Flag Register signals */
+  logic                              transaction_ifr;
+  logic                              dma_done_intr_n;
+  logic                              dma_done_intr;
+  logic                              window_ifr;
+  logic                              dma_window_intr;
+  logic                              dma_window_intr_n;
+
+  /* FIFO signals */
   logic                              fifo_flush;
   logic                              fifo_full;
   logic                              fifo_empty;
@@ -94,22 +163,30 @@ module dma #(
   logic                              fifo_addr_full;
   logic fifo_addr_empty, fifo_addr_empty_check;
 
-  logic        wait_for_rx;
-  logic        wait_for_tx;
+  logic wait_for_rx;
+  logic wait_for_tx;
+
+  typedef enum logic [1:0] {
+    DMA_DATA_TYPE_WORD,
+    DMA_DATA_TYPE_HALF_WORD,
+    DMA_DATA_TYPE_BYTE,
+    DMA_DATA_TYPE_BYTE_
+  } dma_data_type_t;
 
-  logic [ 1:0] data_type;
+  dma_data_type_t        dst_data_type;
+  dma_data_type_t        src_data_type;
 
-  logic [31:0] fifo_input;
-  logic [31:0] fifo_addr_input;
-  logic [31:0] fifo_output;
-  logic [31:0] fifo_addr_output;
+  logic           [31:0] fifo_input;
+  logic           [31:0] fifo_addr_input;
+  logic           [31:0] fifo_output;
+  logic           [31:0] fifo_addr_output;
 
-  logic [ 3:0] byte_enable_out;
+  logic           [ 3:0] byte_enable_out;
 
-  logic        circular_mode;
-  logic        address_mode;
+  logic                  circular_mode;
+  logic                  address_mode;
 
-  logic        dma_start_pending;
+  logic                  dma_start_pending;
 
   enum {
     DMA_READY,
@@ -118,7 +195,20 @@ module dma #(
   }
       dma_state_q, dma_state_d;
 
-  logic [Addr_Fifo_Depth-1:0] outstanding_req, outstanding_addr_req;
+  /* Padding FSM states */
+
+  enum {
+    PAD_IDLE,
+    TOP_PAD_EXEC,
+    LEFT_PAD_EXEC,
+    RIGHT_PAD_EXEC,
+    BOTTOM_PAD_EXEC,
+    TOP_PAD_DONE,
+    LEFT_PAD_DONE,
+    RIGHT_PAD_DONE,
+    BOTTOM_PAD_DONE
+  }
+      pad_state_q, pad_state_d, pad_state_x;
 
   enum logic {
     DMA_READ_FSM_IDLE,
@@ -132,14 +222,17 @@ module dma #(
   }
       dma_write_fsm_state, dma_write_fsm_n_state;
 
-  assign dma_read_ch0_req_o.req = data_in_req;
+  logic [Addr_Fifo_Depth-1:0] outstanding_req, outstanding_addr_req;
+  logic [31:0] window_counter;
+
+  assign dma_read_ch0_req_o.req = data_in_req && ~pad_fifo_on;
   assign dma_read_ch0_req_o.we = data_in_we;
   assign dma_read_ch0_req_o.be = data_in_be;
   assign dma_read_ch0_req_o.addr = data_in_addr;
   assign dma_read_ch0_req_o.wdata = 32'h0;
 
-  assign data_in_gnt = dma_read_ch0_resp_i.gnt;
-  assign data_in_rvalid = dma_read_ch0_resp_i.rvalid;
+  assign data_in_gnt = dma_read_ch0_resp_i.gnt || (data_in_gnt_virt & pad_fifo_on);
+  assign data_in_rvalid = dma_read_ch0_resp_i.rvalid || (data_in_rvalid_virt & pad_fifo_on);
   assign data_in_rdata = dma_read_ch0_resp_i.rdata;
 
   assign dma_addr_ch0_req_o.req = data_addr_in_req;
@@ -162,14 +255,16 @@ module dma #(
   assign data_out_rvalid = dma_write_ch0_resp_i.rvalid;
   assign data_out_rdata = dma_write_ch0_resp_i.rdata;
 
-  assign dma_done_intr_o = dma_done & reg2hw.interrupt_en.transaction_done.q;
-  assign dma_window_intr_o = dma_window_event & reg2hw.interrupt_en.window_done.q;
-
-
-  logic [31:0] window_counter;
+  assign dma_done_intr = transaction_ifr;
+  assign dma_window_intr = window_ifr;
 
+  assign dma_done_intr_o = dma_done_intr_n;
+  assign hw2reg.transaction_ifr.d = transaction_ifr;
+  assign dma_window_intr_o = dma_window_intr_n;
+  assign hw2reg.window_ifr.d = window_ifr;
 
-  assign data_type = reg2hw.data_type.q;
+  assign dst_data_type = dma_data_type_t'(reg2hw.dst_data_type.q);
+  assign src_data_type = dma_data_type_t'(reg2hw.src_data_type.q);
 
   assign hw2reg.status.ready.d = (dma_state_q == DMA_READY);
 
@@ -178,6 +273,84 @@ module dma #(
   assign circular_mode = reg2hw.mode.q == 1;
   assign address_mode = reg2hw.mode.q == 2;
 
+  /* DMA Dimensionality configuration flags */
+  assign dma_conf_1d = reg2hw.dim_config.q == 0;
+  assign dma_conf_2d = reg2hw.dim_config.q == 1;
+
+  /* DMA read pointer source selection */
+  assign read_ptr_update_sel = reg2hw.dim_inv.q;
+
+  /* DMA 2D increment */
+  assign dma_src_d2_inc = reg2hw.src_ptr_inc_d2.q;
+  assign dma_src_d1_inc = reg2hw.src_ptr_inc_d1.q;
+  assign dma_dst_d2_inc = reg2hw.dst_ptr_inc_d2.q;
+  assign dma_dst_d1_inc = reg2hw.dst_ptr_inc_d1.q;
+
+  /* Sign extend flag */
+
+  assign sign_extend = reg2hw.sign_ext.q & ( (src_data_type[1] & ~dst_data_type[1]) | ((src_data_type[1] == dst_data_type[1]) & (src_data_type[0] & ~dst_data_type[0])));
+
+  /* Padding FSM conditions assignments */
+
+  assign idle_to_top_ex = {|reg2hw.pad_top.q == 1'b1 && dma_start == 1'b1};
+  assign idle_to_left_ex = {
+    |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b1 && dma_start == 1'b1
+  };
+  assign idle_to_right_ex = {
+    |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 
+                      && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
+  };
+  assign idle_to_bottom_ex = {
+    |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 
+                      && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
+  };
+  assign top_ex_to_top_dn = {
+    dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
+  };
+  assign top_ex_to_left_ex = {
+    dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b1
+  };
+  assign top_dn_to_right_ex = {
+    |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
+  };
+  assign top_dn_to_bottom_ex = {
+    |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
+  };
+  assign top_dn_to_idle = {
+    |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0
+  };
+  assign left_ex_to_left_dn = {
+    dma_src_cnt_d1 == ({1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
+  };
+  assign left_dn_to_left_ex = {
+    dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({14'h0, dma_dst_cnt_du} + {11'h0, reg2hw.pad_bottom.q}) && |reg2hw.pad_right.q == 1'b0
+  };
+  assign left_dn_to_right_ex = {
+    |reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
+  };
+  assign left_dn_to_bottom_ex = {
+    |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
+  };
+  assign left_dn_to_idle = {
+    |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0
+  };
+  assign right_ex_to_right_dn = {
+    dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
+  };
+  assign right_ex_to_left_ex = {
+    dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b1
+  };
+  assign right_ex_to_bottom_ex = {
+    |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
+  };
+  assign right_dn_to_right_ex = {
+    dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
+  };
+  assign right_dn_to_idle = {|reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0};
+  assign bottom_ex_to_idle = {
+    dma_src_cnt_d1 == {14'h0, dma_dst_cnt_du} && dma_src_cnt_d2 == {14'h0, dma_dst_cnt_du}
+  };
+
   assign write_address = address_mode ? fifo_addr_output : write_ptr_reg;
 
   assign wait_for_rx = |(reg2hw.slot.rx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i));
@@ -198,6 +371,7 @@ module dma #(
   // RUNNING : waiting for transaction finish
   //           when `dma_done` rises either enter ready or restart in circular mode
   //
+
   always_comb begin
     dma_state_d = dma_state_q;
     case (dma_state_q)
@@ -218,7 +392,7 @@ module dma #(
     endcase
   end
 
-  // update state
+  /* Update DMA state */
   always_ff @(posedge clk_i, negedge rst_ni) begin
     if (~rst_ni) begin
       dma_state_q <= DMA_READY;
@@ -227,21 +401,20 @@ module dma #(
     end
   end
 
-
-  // DMA pulse start when dma_start register is written
+  /* DMA pulse start when dma_start register is written */
   always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_start
     if (~rst_ni) begin
       dma_start_pending <= 1'b0;
     end else begin
       if (dma_start == 1'b1) begin
         dma_start_pending <= 1'b0;
-      end else if (reg2hw.size.qe & |reg2hw.size.q) begin
+      end else if ((reg2hw.size_d1.qe & |reg2hw.size_d1.q)) begin
         dma_start_pending <= 1'b1;
       end
     end
   end
 
-  // Store input data pointer and increment everytime read request is granted
+  /*/ Store input data pointer and increment everytime read request is granted */
   always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_in_reg
     if (~rst_ni) begin
       read_ptr_reg <= '0;
@@ -249,7 +422,44 @@ module dma #(
       if (dma_start == 1'b1) begin
         read_ptr_reg <= reg2hw.src_ptr.q;
       end else if (data_in_gnt == 1'b1) begin
-        read_ptr_reg <= read_ptr_reg + {24'h0, reg2hw.ptr_inc.src_ptr_inc.q};
+        if (dma_conf_1d == 1'b1) begin
+          /* Increase the pointer by the amount written in ptr_inc */
+          read_ptr_reg <= read_ptr_reg + {26'h0, dma_src_d1_inc};
+        end else if (dma_conf_2d == 1'b1 && pad_cnt_on == 1'b0) begin
+          if (read_ptr_update_sel == 1'b0) begin
+            if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
+              /* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d1)*data_unit */
+              read_ptr_reg <= read_ptr_reg + {9'h0, dma_src_d2_inc};
+            end else begin
+              read_ptr_reg <= read_ptr_reg + {26'h0, dma_src_d1_inc}; /* Increment of the d1 increment (stride) */
+            end
+          end else begin
+            if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
+              /* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d2)*data_unit */
+              read_ptr_reg <= src_ptr_reg;
+            end else begin
+              read_ptr_reg <= read_ptr_reg + {9'h0, dma_src_d2_inc}; /* Increment of the d1 increment (stride) */
+            end
+          end
+        end
+      end
+    end
+  end
+
+  /* 
+   * Store input data pointer in source_ptr_reg and increment it every time read request is granted, 
+   * if the d1 has finished reading and the read pointer update is set to 1'b1 
+   */
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_src_ptr_reg
+    if (~rst_ni) begin
+      src_ptr_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        src_ptr_reg <= reg2hw.src_ptr.q + {26'h0, dma_src_d1_inc};
+      end else if (data_in_gnt == 1'b1 && dma_conf_2d == 1'b1 && pad_cnt_on == 1'b0 && read_ptr_update_sel == 1'b1 &&
+                    (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1)) begin
+        src_ptr_reg <= src_ptr_reg + {26'h0, dma_src_d1_inc};
       end
     end
   end
@@ -267,7 +477,9 @@ module dma #(
     end
   end
 
-  // Only update read_ptr_valid_reg when the data is stored in the fifo
+  // Only update read_ptr_valid_reg when the data is stored in the fifo.
+  // Since every input grant is followed by a rvalid, the read_ptr_valid_reg is a mere sample of the read_ptr_reg
+  // synched with the rvalid signal.
   always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_valid_in_reg
     if (~rst_ni) begin
       read_ptr_valid_reg <= '0;
@@ -275,7 +487,7 @@ module dma #(
       if (dma_start == 1'b1) begin
         read_ptr_valid_reg <= reg2hw.src_ptr.q;
       end else if (data_in_rvalid == 1'b1) begin
-        read_ptr_valid_reg <= read_ptr_valid_reg + {24'h0, reg2hw.ptr_inc.src_ptr_inc.q};
+        read_ptr_valid_reg <= read_ptr_reg;
       end
     end
   end
@@ -288,20 +500,74 @@ module dma #(
       if (dma_start == 1'b1) begin
         write_ptr_reg <= reg2hw.dst_ptr.q;
       end else if (data_out_gnt == 1'b1) begin
-        write_ptr_reg <= write_ptr_reg + {24'h0, reg2hw.ptr_inc.dst_ptr_inc.q};
+        if (dma_conf_1d == 1'b1) begin
+          write_ptr_reg <= write_ptr_reg + {26'h0, dma_dst_d1_inc};
+        end else if (dma_conf_2d == 1'b1) begin
+          if (dma_dst_cnt_d1 == {14'h0, dma_dst_cnt_du}) begin
+            // In this case, the d1 is finished, so we need to increment the pointer by sizeof(d1)*data_unit*strides
+            write_ptr_reg <= write_ptr_reg + {9'h0, dma_dst_d2_inc};
+          end else begin
+            write_ptr_reg <= write_ptr_reg + {26'h0, dma_dst_d1_inc}; // Increment just of one du, since we need to increase the 1d
+          end
+        end
       end
     end
   end
 
-  // Store dma transfer size and decrement it everytime input data rvalid is asserted
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_cnt_reg
+  // Store dma transfer size and decrement it everytime input data rvalid is asserted.
+  // Perform additional checks for 2D DMA
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_src_cnt_reg
     if (~rst_ni) begin
-      dma_cnt <= '0;
+      dma_src_cnt_d1 <= '0;
+      dma_src_cnt_d2 <= '0;
     end else begin
       if (dma_start == 1'b1) begin
-        dma_cnt <= reg2hw.size.q;
+        dma_src_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
+        dma_src_cnt_d2 <= {1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_top.q} + {11'h0, reg2hw.pad_bottom.q};
       end else if (data_in_gnt == 1'b1) begin
-        dma_cnt <= dma_cnt - {29'h0, dma_cnt_dec};
+        if (dma_conf_1d == 1'b1) begin
+          // 1D case
+          dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_src_cnt_du};
+        end else if (dma_conf_2d == 1'b1) begin
+          // 2D case
+          if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du}) begin
+            // In this case, the d1 is finished, so we need to decrement the d2 size and reset the d2 size
+            dma_src_cnt_d2 <= dma_src_cnt_d2 - {14'h0, dma_src_cnt_du};
+            dma_src_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
+          end else begin
+            // In this case, the d1 isn't finished, so we need to decrement the d1 size
+            dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_src_cnt_du};
+          end
+        end
+      end
+    end
+  end
+
+  // Store dma transfer size and decrement it everytime input data write request is granted.
+  // The need for two separate counters for reading and writing operations is due to the lack of synchronization between them.
+  // Since the check on the read side is done on the rvalid signal, we need only an additional counter, for d1.
+  // Performs additional checks for 2D DMA.
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_dst_cnt_reg
+    if (~rst_ni) begin
+      dma_dst_cnt_d1 <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        dma_dst_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
+      end else if (data_out_gnt == 1'b1) begin
+        if (dma_conf_1d == 1'b1) begin
+          // 1D case
+          dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_dst_cnt_du};
+        end else if (dma_conf_2d == 1'b1) begin
+          // 2D case
+          if (dma_dst_cnt_d1 == {14'h0, dma_dst_cnt_du}) begin
+            // In this case, the d1 is finished, so we need to reset the d2 size
+            dma_dst_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
+          end else begin
+            // In this case, the d1 isn't finished, so we need to decrement the d1 size
+            dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_dst_cnt_du};
+          end
+        end
       end
     end
   end
@@ -312,7 +578,7 @@ module dma #(
       dma_addr_cnt <= '0;
     end else begin
       if (dma_start == 1'b1 && address_mode) begin
-        dma_addr_cnt <= reg2hw.size.q;
+        dma_addr_cnt <= {16'h0, reg2hw.size_d1.q};
       end else if (data_addr_in_gnt == 1'b1 && address_mode) begin
         dma_addr_cnt <= dma_addr_cnt - 32'h4;  //address always 32b
       end
@@ -320,18 +586,26 @@ module dma #(
   end
 
   always_comb begin
-    case (data_type)
-      2'b00: dma_cnt_dec = 3'h4;
-      2'b01: dma_cnt_dec = 3'h2;
-      2'b10, 2'b11: dma_cnt_dec = 3'h1;
+    case (dst_data_type)
+      DMA_DATA_TYPE_WORD: dma_dst_cnt_du = 3'h4;
+      DMA_DATA_TYPE_HALF_WORD: dma_dst_cnt_du = 3'h2;
+      DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: dma_dst_cnt_du = 3'h1;
+    endcase
+  end
+
+  always_comb begin
+    case (src_data_type)
+      DMA_DATA_TYPE_WORD: dma_src_cnt_du = 3'h4;
+      DMA_DATA_TYPE_HALF_WORD: dma_src_cnt_du = 3'h2;
+      DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: dma_src_cnt_du = 3'h1;
     endcase
   end
 
   always_comb begin : proc_byte_enable_out
-    case (data_type)  // Data type 00 Word, 01 Half word, 11,10 byte
-      2'b00: byte_enable_out = 4'b1111;  // Writing a word (32 bits)
+    case (dst_data_type)  // Data type 00 Word, 01 Half word, 11,10 byte
+      DMA_DATA_TYPE_WORD: byte_enable_out = 4'b1111;  // Writing a word (32 bits)
 
-      2'b01: begin  // Writing a half-word (16 bits)
+      DMA_DATA_TYPE_HALF_WORD: begin  // Writing a half-word (16 bits)
         case (write_address[1])
           1'b0: byte_enable_out = 4'b0011;
           1'b1: byte_enable_out = 4'b1100;
@@ -339,7 +613,7 @@ module dma #(
         ;  // case(write_address[1:0])
       end
 
-      2'b10, 2'b11: begin  // Writing a byte (8 bits)
+      DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: begin  // Writing a byte (8 bits)
         case (write_address[1:0])
           2'b00: byte_enable_out = 4'b0001;
           2'b01: byte_enable_out = 4'b0010;
@@ -349,7 +623,7 @@ module dma #(
         ;  // case(write_address[1:0])
       end
     endcase
-    ;  // case (data_type)
+    ;  // case (dst_data_type)
   end
 
   // Output data shift
@@ -361,41 +635,118 @@ module dma #(
     data_out_wdata[31:24] = fifo_output[31:24];
 
     case (write_address[1:0])
-      2'b00: ;
-
-      2'b01: data_out_wdata[15:8] = fifo_output[7:0];
-
-      2'b10: begin
+      2'b00: begin
+        if (sign_extend) begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD} : ;
+            {
+              DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD
+            } :
+            data_out_wdata[31:16] = {16{fifo_output[15]}};
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_WORD
+            } :
+            data_out_wdata[31:8] = {24{fifo_output[7]}};
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[15:8] = {8{fifo_output[7]}};
+            default: ;
+          endcase
+        end else begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD} : ;
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD} : data_out_wdata[31:16] = 16'b0;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_WORD
+            } :
+            data_out_wdata[31:8] = 24'b0;
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[15:8] = 8'b0;
+            default: ;
+          endcase
+        end
+      end
+      2'b01: data_out_wdata[15:8] = fifo_output[7:0];  // Writing a byte, no need for sign extension
+      2'b10: begin  // Writing a half-word or a byte
         data_out_wdata[23:16] = fifo_output[7:0];
         data_out_wdata[31:24] = fifo_output[15:8];
-      end
 
-      2'b11: data_out_wdata[31:24] = fifo_output[7:0];
+        if (sign_extend) begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[31:24] = {8{fifo_output[7]}};
+            default: ;
+          endcase
+        end else begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[31:24] = 8'b0;
+            default: ;
+          endcase
+        end
+      end
+      2'b11:
+      data_out_wdata[31:24] = fifo_output[7:0];  // Writing a byte, no need for sign extension
     endcase
   end
 
+
   assign fifo_addr_input = data_addr_in_rdata;  //never misaligned, always 32b
 
   // Input data shift: shift the input data to be on the LSB of the fifo
   always_comb begin : proc_input_data
 
-    fifo_input[7:0]   = data_in_rdata[7:0];
-    fifo_input[15:8]  = data_in_rdata[15:8];
-    fifo_input[23:16] = data_in_rdata[23:16];
-    fifo_input[31:24] = data_in_rdata[31:24];
-
-    case (read_ptr_valid_reg[1:0])
-      2'b00: ;
-
-      2'b01: fifo_input[7:0] = data_in_rdata[15:8];
-
-      2'b10: begin
-        fifo_input[7:0]  = data_in_rdata[23:16];
-        fifo_input[15:8] = data_in_rdata[31:24];
-      end
+    if (pad_fifo_on) begin
+      fifo_input = 32'h0;
+    end else begin
+      fifo_input[7:0]   = data_in_rdata[7:0];
+      fifo_input[15:8]  = data_in_rdata[15:8];
+      fifo_input[23:16] = data_in_rdata[23:16];
+      fifo_input[31:24] = data_in_rdata[31:24];
+
+      case (read_ptr_valid_reg[1:0])
+        2'b00: ;
+        2'b01: fifo_input[7:0] = data_in_rdata[15:8];
+
+        2'b10: begin
+          fifo_input[7:0]  = data_in_rdata[23:16];
+          fifo_input[15:8] = data_in_rdata[31:24];
+        end
 
-      2'b11: fifo_input[7:0] = data_in_rdata[31:24];
-    endcase
+        2'b11: fifo_input[7:0] = data_in_rdata[31:24];
+      endcase
+    end
   end
 
   // FSM state update
@@ -410,6 +761,7 @@ module dma #(
       dma_read_fsm_state <= dma_read_fsm_n_state;
       dma_write_fsm_state <= dma_write_fsm_n_state;
       dma_read_addr_fsm_state <= dma_read_addr_fsm_n_state;
+
       outstanding_req <= outstanding_req + (data_in_req && data_in_gnt) - data_in_rvalid;
 
       if (address_mode)
@@ -418,6 +770,250 @@ module dma #(
     end
   end
 
+  /* Padding synchronization signal generation 
+   * When the pad_fifo_on is asserted, this logic mimics the behaviour of the data_in_rvalid and data_in_gnt signals
+   * coming from the memory. This is done in order to keep the read/write operations working even without an
+   * actual response from memory, reducing power consumptionnby avoiding unnecessary memory accesses.
+   */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pad_sync_signal
+    if (~rst_ni) begin
+      data_in_rvalid_virt <= 1'b0;
+      data_in_rvalid_virt_n <= 1'b1;
+      data_in_rvalid_virt_n_n <= 1'b0;
+      data_in_gnt_virt <= 1'b1;
+      data_in_gnt_virt_n <= 1'b0;
+      data_in_gnt_virt_n_n <= 1'b0;
+    end else begin
+      if (data_in_req == 1'b1 && pad_fifo_on == 1'b1) begin
+        data_in_rvalid_virt <= data_in_rvalid_virt_n;
+        data_in_rvalid_virt_n <= data_in_rvalid_virt_n_n;
+        data_in_rvalid_virt_n_n <= data_in_rvalid;
+        data_in_gnt_virt <= data_in_gnt_virt_n;
+        data_in_gnt_virt_n <= data_in_gnt_virt_n_n;
+        data_in_gnt_virt_n_n <= data_in_gnt;
+      end else begin
+        data_in_rvalid_virt <= 1'b0;
+        data_in_rvalid_virt_n <= 1'b1;
+        data_in_rvalid_virt_n_n <= 1'b0;
+        data_in_gnt_virt <= 1'b1;
+        data_in_gnt_virt_n <= 1'b0;
+        data_in_gnt_virt_n_n <= 1'b0;
+      end
+    end
+  end
+
+  // Padding FSM state update
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pad_state
+    if (~rst_ni) begin
+      pad_state_q <= PAD_IDLE;
+      pad_state_x <= PAD_IDLE;
+    end else if (dma_conf_2d == 1'b1) begin
+      if (dma_start == 1'b1 && |reg2hw.pad_top.q == 1'b1) begin
+        pad_state_q <= TOP_PAD_EXEC;
+        pad_state_x <= TOP_PAD_EXEC;
+      end else if (dma_start == 1'b1 && |reg2hw.pad_left.q == 1'b1) begin
+        pad_state_q <= LEFT_PAD_EXEC;
+        pad_state_x <= LEFT_PAD_EXEC;
+      end else begin
+        pad_state_x <= pad_state_d;
+        if (data_in_rvalid == 1'b1) begin
+          pad_state_q <= pad_state_x;
+        end
+      end
+    end
+  end
+
+  // Pad fifo flag logic
+  always_comb begin : proc_pad_fifo_on
+    if (dma_conf_2d == 1'b1) begin
+      case (pad_state_q)
+        TOP_PAD_EXEC, LEFT_PAD_EXEC, RIGHT_PAD_EXEC, BOTTOM_PAD_EXEC: pad_fifo_on = 1'b1;
+
+        default: pad_fifo_on = 1'b0;
+      endcase
+    end else begin
+      pad_fifo_on = 1'b0;
+    end
+  end
+
+  // Pad counter flag logic
+  always_comb begin : proc_pad_cnt_on
+    case (pad_state_q)
+      PAD_IDLE: begin
+        if (idle_to_right_ex || idle_to_bottom_ex || idle_to_left_ex || idle_to_top_ex) begin
+          pad_cnt_on = 1'b1;
+        end else begin
+          pad_cnt_on = pad_fifo_on;
+        end
+      end
+
+      TOP_PAD_DONE: begin
+        if (top_dn_to_right_ex) begin
+          pad_cnt_on = 1'b1;
+        end else begin
+          pad_cnt_on = pad_fifo_on;
+        end
+      end
+
+      LEFT_PAD_DONE: begin
+        if (left_dn_to_right_ex) begin
+          pad_cnt_on = 1'b1;
+        end else begin
+          pad_cnt_on = pad_fifo_on;
+        end
+      end
+
+      RIGHT_PAD_DONE: begin
+        if (right_dn_to_right_ex) begin
+          pad_cnt_on = 1'b1;
+        end else begin
+          pad_cnt_on = pad_fifo_on;
+        end
+      end
+
+      RIGHT_PAD_EXEC: begin
+        if (right_ex_to_right_dn || right_ex_to_left_ex) begin
+          pad_cnt_on = 1'b0;
+        end else begin
+          pad_cnt_on = pad_fifo_on;
+        end
+      end
+
+      default: pad_cnt_on = pad_fifo_on;
+    endcase
+  end
+
+  // Padding FSM logic
+  always_comb begin : proc_pad_fsm_logic
+    if (dma_conf_1d == 1'b1) begin
+      pad_state_d = PAD_IDLE;
+    end else begin
+      if (dma_start == 1'b1 && |reg2hw.pad_top.q == 1'b1) begin
+        pad_state_d = TOP_PAD_EXEC;
+      end else if (dma_start == 1'b1 && |reg2hw.pad_left.q == 1'b1) begin
+        pad_state_d = LEFT_PAD_EXEC;
+      end else begin
+        pad_state_d = pad_state_x;
+      end
+    end
+
+    unique case (pad_state_x)
+      PAD_IDLE: begin
+        if (idle_to_top_ex) begin
+          pad_state_d = TOP_PAD_EXEC;
+        end else if (idle_to_left_ex) begin
+          pad_state_d = LEFT_PAD_EXEC;
+        end else if (idle_to_right_ex) begin
+          pad_state_d = RIGHT_PAD_EXEC;
+        end else if (idle_to_bottom_ex) begin
+          pad_state_d = BOTTOM_PAD_EXEC;
+        end
+      end
+
+      TOP_PAD_EXEC: begin
+        if (top_ex_to_left_ex) begin
+          pad_state_d = LEFT_PAD_EXEC;
+        end else if (top_ex_to_top_dn) begin
+          pad_state_d = TOP_PAD_DONE;
+        end
+      end
+      TOP_PAD_DONE: begin
+        if (top_dn_to_right_ex) begin
+          pad_state_d = RIGHT_PAD_EXEC;
+        end else if (top_dn_to_bottom_ex) begin
+          pad_state_d = BOTTOM_PAD_EXEC;
+        end else if (top_dn_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end
+      end
+      LEFT_PAD_EXEC: begin
+        if (left_ex_to_left_dn) begin
+          pad_state_d = LEFT_PAD_DONE;
+        end
+      end
+      LEFT_PAD_DONE: begin
+        if (left_dn_to_right_ex) begin
+          pad_state_d = RIGHT_PAD_EXEC;
+        end else if (left_dn_to_bottom_ex) begin
+          pad_state_d = BOTTOM_PAD_EXEC;
+        end else if (left_dn_to_left_ex) begin
+          pad_state_d = LEFT_PAD_EXEC;
+        end else if (left_dn_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end
+      end
+      RIGHT_PAD_EXEC: begin
+        if (right_ex_to_right_dn) begin
+          pad_state_d = RIGHT_PAD_DONE;
+        end else if (right_ex_to_left_ex) begin
+          pad_state_d = LEFT_PAD_EXEC;
+        end else if (right_ex_to_bottom_ex) begin
+          pad_state_d = BOTTOM_PAD_EXEC;
+        end
+      end
+      RIGHT_PAD_DONE: begin
+        if (right_dn_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end else if (right_dn_to_right_ex) begin
+          pad_state_d = RIGHT_PAD_EXEC;
+        end
+      end
+      BOTTOM_PAD_EXEC: begin
+        if (bottom_ex_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end
+      end
+    endcase
+  end
+
+  /* Transaction IFR update */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_transaction_ifr
+    if (~rst_ni) begin
+      transaction_ifr <= '0;
+    end else if (reg2hw.interrupt_en.transaction_done.q == 1'b1) begin
+      // Enter here only if the transaction_done interrupt is enabled
+      if (dma_done == 1'b1) begin
+        transaction_ifr <= 1'b1;
+      end else if (reg2hw.transaction_ifr.re == 1'b1) begin
+        // If the IFR bit is read, we must clear the transaction_ifr
+        transaction_ifr <= 1'b0;
+      end
+    end
+  end
+
+  /* Delayed transaction interrupt signals */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_intr
+    if (~rst_ni) begin
+      dma_done_intr_n <= '0;
+    end else begin
+      dma_done_intr_n <= dma_done_intr;
+    end
+  end
+
+  /* Window IFR update */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_window_ifr
+    if (~rst_ni) begin
+      window_ifr <= '0;
+    end else if (reg2hw.interrupt_en.window_done.q == 1'b1) begin
+      // Enter here only if the window_done interrupt is enabled
+      if (dma_window_event == 1'b1) begin
+        window_ifr <= 1'b1;
+      end else if (reg2hw.window_ifr.re == 1'b1) begin
+        // If the IFR bit is read, we must clear the window_ifr
+        window_ifr <= 1'b0;
+      end
+    end
+  end
+
+  /* Delayed window interrupt signals */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_window_intr
+    if (~rst_ni) begin
+      dma_window_intr_n <= '0;
+    end else begin
+      dma_window_intr_n <= dma_window_intr;
+    end
+  end
+
   // Read master FSM
   always_comb begin : proc_dma_read_fsm_logic
 
@@ -444,17 +1040,39 @@ module dma #(
       // Read one word
       DMA_READ_FSM_ON: begin
         // If all input data read exit
-        if (|dma_cnt == 1'b0) begin
-          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
-        end else begin
-          dma_read_fsm_n_state = DMA_READ_FSM_ON;
-          // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
-          if (fifo_full == 1'b0 && fifo_alm_full == 1'b0 && wait_for_rx == 1'b0) begin
-            data_in_req  = 1'b1;
-            data_in_we   = 1'b0;
-            data_in_be   = 4'b1111;  // always read all bytes
-            data_in_addr = read_ptr_reg;
+        if (ext_dma_stop_i == 1'b0) begin
+          if (dma_conf_1d == 1'b1) begin
+            // 1D DMA case
+            if (|dma_src_cnt_d1 == 1'b0) begin
+              dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+            end else begin
+              dma_read_fsm_n_state = DMA_READ_FSM_ON;
+              // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
+              if (fifo_full == 1'b0 && fifo_alm_full == 1'b0 && wait_for_rx == 1'b0) begin
+                data_in_req  = 1'b1;
+                data_in_we   = 1'b0;
+                data_in_be   = 4'b1111;  // always read all bytes
+                data_in_addr = read_ptr_reg;
+              end
+            end
+          end else if (dma_conf_2d == 1'b1) begin
+            // 2D DMA case: exit only if both 1d and 2d counters are at 0
+            if (dma_src_cnt_d1 == {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q} && |dma_src_cnt_d2 == 1'b0) begin
+              dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+            end else begin
+              // The read operation is the same in both cases
+              dma_read_fsm_n_state = DMA_READ_FSM_ON;
+              // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
+              if (fifo_full == 1'b0 && fifo_alm_full == 1'b0 && wait_for_rx == 1'b0) begin
+                data_in_req  = 1'b1;
+                data_in_we   = 1'b0;
+                data_in_be   = 4'b1111;  // always read all bytes
+                data_in_addr = read_ptr_reg;
+              end
+            end
           end
+        end else begin
+          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
         end
       end
     endcase
@@ -528,6 +1146,8 @@ module dma #(
         // If all input data read exit
         if (fifo_empty == 1'b1 && dma_read_fsm_state == DMA_READ_FSM_IDLE) begin
           dma_done = outstanding_req == '0 && outstanding_addr_req == '0;
+          // If all input data has been read (dma_read_fsm_state == DMA_READ_FSM_IDLE, set when all data has been read) 
+          // and all requests have been granted, (outstanding_req == 0) then we are done
           dma_write_fsm_n_state = dma_done ? DMA_WRITE_FSM_IDLE : DMA_WRITE_FSM_ON;
         end else begin
           dma_write_fsm_n_state = DMA_WRITE_FSM_ON;
@@ -596,9 +1216,9 @@ module dma #(
 
   // WINDOW EVENT
   // Count gnt write transaction and generate event pulse if WINDOW_SIZE is reached
-  assign dma_window_event = |reg2hw.window_size.q &  data_out_gnt & (window_counter + 'h1 >= reg2hw.window_size.q);
+  assign dma_window_event = |reg2hw.window_size.q &  data_out_gnt & (window_counter + 'h1 >= {19'h0, reg2hw.window_size.q});
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_dma_window_cnt
     if (~rst_ni) begin
       window_counter <= 'h0;
     end else begin
@@ -606,7 +1226,7 @@ module dma #(
         if (dma_start | dma_done) begin
           window_counter <= 'h0;
         end else if (data_out_gnt) begin
-          if (window_counter + 'h1 >= reg2hw.window_size.q) begin
+          if (window_counter + 'h1 >= {19'h0, reg2hw.window_size.q}) begin
             window_counter <= 'h0;
           end else begin
             window_counter <= window_counter + 'h1;
@@ -617,7 +1237,7 @@ module dma #(
   end
 
   // Update WINDOW_COUNT register
-  always_comb begin
+  always_comb begin : proc_dma_window_cnt_reg
     hw2reg.window_count.d  = reg2hw.window_count.q + 'h1;
     hw2reg.window_count.de = 1'b0;
     if (dma_start) begin
@@ -631,7 +1251,7 @@ module dma #(
   // update window_done flag
   // set on dma_window_event
   // reset on read
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_dma_window_done
     if (~rst_ni) begin
       window_done_q <= 1'b0;
     end else begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv
index e4e31fe2..f2fe4761 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv
@@ -7,7 +7,7 @@
 package dma_reg_pkg;
 
   // Address widths within the block
-  parameter int BlockAw = 6;
+  parameter int BlockAw = 7;
 
   ////////////////////////////
   // Typedefs for registers //
@@ -20,9 +20,14 @@ package dma_reg_pkg;
   typedef struct packed {logic [31:0] q;} dma_reg2hw_addr_ptr_reg_t;
 
   typedef struct packed {
-    logic [31:0] q;
+    logic [15:0] q;
     logic        qe;
-  } dma_reg2hw_size_reg_t;
+  } dma_reg2hw_size_d1_reg_t;
+
+  typedef struct packed {
+    logic [15:0] q;
+    logic        qe;
+  } dma_reg2hw_size_d2_reg_t;
 
   typedef struct packed {
     struct packed {
@@ -35,110 +40,217 @@ package dma_reg_pkg;
     } window_done;
   } dma_reg2hw_status_reg_t;
 
-  typedef struct packed {
-    struct packed {logic [7:0] q;} src_ptr_inc;
-    struct packed {logic [7:0] q;} dst_ptr_inc;
-  } dma_reg2hw_ptr_inc_reg_t;
+  typedef struct packed {logic [5:0] q;} dma_reg2hw_src_ptr_inc_d1_reg_t;
+
+  typedef struct packed {logic [22:0] q;} dma_reg2hw_src_ptr_inc_d2_reg_t;
+
+  typedef struct packed {logic [5:0] q;} dma_reg2hw_dst_ptr_inc_d1_reg_t;
+
+  typedef struct packed {logic [22:0] q;} dma_reg2hw_dst_ptr_inc_d2_reg_t;
 
   typedef struct packed {
     struct packed {logic [15:0] q;} rx_trigger_slot;
     struct packed {logic [15:0] q;} tx_trigger_slot;
   } dma_reg2hw_slot_reg_t;
 
-  typedef struct packed {logic [1:0] q;} dma_reg2hw_data_type_reg_t;
+  typedef struct packed {logic [1:0] q;} dma_reg2hw_src_data_type_reg_t;
+
+  typedef struct packed {logic [1:0] q;} dma_reg2hw_dst_data_type_reg_t;
+
+  typedef struct packed {logic q;} dma_reg2hw_sign_ext_reg_t;
 
   typedef struct packed {logic [1:0] q;} dma_reg2hw_mode_reg_t;
 
-  typedef struct packed {logic [31:0] q;} dma_reg2hw_window_size_reg_t;
+  typedef struct packed {logic q;} dma_reg2hw_dim_config_reg_t;
+
+  typedef struct packed {logic q;} dma_reg2hw_dim_inv_reg_t;
 
-  typedef struct packed {logic [31:0] q;} dma_reg2hw_window_count_reg_t;
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } dma_reg2hw_pad_top_reg_t;
+
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } dma_reg2hw_pad_bottom_reg_t;
+
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } dma_reg2hw_pad_right_reg_t;
+
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } dma_reg2hw_pad_left_reg_t;
+
+  typedef struct packed {logic [12:0] q;} dma_reg2hw_window_size_reg_t;
+
+  typedef struct packed {logic [7:0] q;} dma_reg2hw_window_count_reg_t;
 
   typedef struct packed {
     struct packed {logic q;} transaction_done;
     struct packed {logic q;} window_done;
   } dma_reg2hw_interrupt_en_reg_t;
 
+  typedef struct packed {
+    logic q;
+    logic re;
+  } dma_reg2hw_transaction_ifr_reg_t;
+
+  typedef struct packed {
+    logic q;
+    logic re;
+  } dma_reg2hw_window_ifr_reg_t;
+
   typedef struct packed {
     struct packed {logic d;} ready;
     struct packed {logic d;} window_done;
   } dma_hw2reg_status_reg_t;
 
   typedef struct packed {
-    logic [31:0] d;
-    logic        de;
+    logic [7:0] d;
+    logic       de;
   } dma_hw2reg_window_count_reg_t;
 
+  typedef struct packed {logic d;} dma_hw2reg_transaction_ifr_reg_t;
+
+  typedef struct packed {logic d;} dma_hw2reg_window_ifr_reg_t;
+
   // Register -> HW type
   typedef struct packed {
-    dma_reg2hw_src_ptr_reg_t src_ptr;  // [250:219]
-    dma_reg2hw_dst_ptr_reg_t dst_ptr;  // [218:187]
-    dma_reg2hw_addr_ptr_reg_t addr_ptr;  // [186:155]
-    dma_reg2hw_size_reg_t size;  // [154:122]
-    dma_reg2hw_status_reg_t status;  // [121:118]
-    dma_reg2hw_ptr_inc_reg_t ptr_inc;  // [117:102]
-    dma_reg2hw_slot_reg_t slot;  // [101:70]
-    dma_reg2hw_data_type_reg_t data_type;  // [69:68]
-    dma_reg2hw_mode_reg_t mode;  // [67:66]
-    dma_reg2hw_window_size_reg_t window_size;  // [65:34]
-    dma_reg2hw_window_count_reg_t window_count;  // [33:2]
-    dma_reg2hw_interrupt_en_reg_t interrupt_en;  // [1:0]
+    dma_reg2hw_src_ptr_reg_t src_ptr;  // [287:256]
+    dma_reg2hw_dst_ptr_reg_t dst_ptr;  // [255:224]
+    dma_reg2hw_addr_ptr_reg_t addr_ptr;  // [223:192]
+    dma_reg2hw_size_d1_reg_t size_d1;  // [191:175]
+    dma_reg2hw_size_d2_reg_t size_d2;  // [174:158]
+    dma_reg2hw_status_reg_t status;  // [157:154]
+    dma_reg2hw_src_ptr_inc_d1_reg_t src_ptr_inc_d1;  // [153:148]
+    dma_reg2hw_src_ptr_inc_d2_reg_t src_ptr_inc_d2;  // [147:125]
+    dma_reg2hw_dst_ptr_inc_d1_reg_t dst_ptr_inc_d1;  // [124:119]
+    dma_reg2hw_dst_ptr_inc_d2_reg_t dst_ptr_inc_d2;  // [118:96]
+    dma_reg2hw_slot_reg_t slot;  // [95:64]
+    dma_reg2hw_src_data_type_reg_t src_data_type;  // [63:62]
+    dma_reg2hw_dst_data_type_reg_t dst_data_type;  // [61:60]
+    dma_reg2hw_sign_ext_reg_t sign_ext;  // [59:59]
+    dma_reg2hw_mode_reg_t mode;  // [58:57]
+    dma_reg2hw_dim_config_reg_t dim_config;  // [56:56]
+    dma_reg2hw_dim_inv_reg_t dim_inv;  // [55:55]
+    dma_reg2hw_pad_top_reg_t pad_top;  // [54:48]
+    dma_reg2hw_pad_bottom_reg_t pad_bottom;  // [47:41]
+    dma_reg2hw_pad_right_reg_t pad_right;  // [40:34]
+    dma_reg2hw_pad_left_reg_t pad_left;  // [33:27]
+    dma_reg2hw_window_size_reg_t window_size;  // [26:14]
+    dma_reg2hw_window_count_reg_t window_count;  // [13:6]
+    dma_reg2hw_interrupt_en_reg_t interrupt_en;  // [5:4]
+    dma_reg2hw_transaction_ifr_reg_t transaction_ifr;  // [3:2]
+    dma_reg2hw_window_ifr_reg_t window_ifr;  // [1:0]
   } dma_reg2hw_t;
 
   // HW -> register type
   typedef struct packed {
-    dma_hw2reg_status_reg_t status;  // [34:33]
-    dma_hw2reg_window_count_reg_t window_count;  // [32:0]
+    dma_hw2reg_status_reg_t status;  // [12:11]
+    dma_hw2reg_window_count_reg_t window_count;  // [10:2]
+    dma_hw2reg_transaction_ifr_reg_t transaction_ifr;  // [1:1]
+    dma_hw2reg_window_ifr_reg_t window_ifr;  // [0:0]
   } dma_hw2reg_t;
 
   // Register offsets
-  parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 6'h0;
-  parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 6'h4;
-  parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 6'h8;
-  parameter logic [BlockAw-1:0] DMA_SIZE_OFFSET = 6'hc;
-  parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 6'h10;
-  parameter logic [BlockAw-1:0] DMA_PTR_INC_OFFSET = 6'h14;
-  parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 6'h18;
-  parameter logic [BlockAw-1:0] DMA_DATA_TYPE_OFFSET = 6'h1c;
-  parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 6'h20;
-  parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 6'h24;
-  parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 6'h28;
-  parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 6'h2c;
+  parameter logic [BlockAw-1:0] DMA_SRC_PTR_OFFSET = 7'h0;
+  parameter logic [BlockAw-1:0] DMA_DST_PTR_OFFSET = 7'h4;
+  parameter logic [BlockAw-1:0] DMA_ADDR_PTR_OFFSET = 7'h8;
+  parameter logic [BlockAw-1:0] DMA_SIZE_D1_OFFSET = 7'hc;
+  parameter logic [BlockAw-1:0] DMA_SIZE_D2_OFFSET = 7'h10;
+  parameter logic [BlockAw-1:0] DMA_STATUS_OFFSET = 7'h14;
+  parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D1_OFFSET = 7'h18;
+  parameter logic [BlockAw-1:0] DMA_SRC_PTR_INC_D2_OFFSET = 7'h1c;
+  parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D1_OFFSET = 7'h20;
+  parameter logic [BlockAw-1:0] DMA_DST_PTR_INC_D2_OFFSET = 7'h24;
+  parameter logic [BlockAw-1:0] DMA_SLOT_OFFSET = 7'h28;
+  parameter logic [BlockAw-1:0] DMA_SRC_DATA_TYPE_OFFSET = 7'h2c;
+  parameter logic [BlockAw-1:0] DMA_DST_DATA_TYPE_OFFSET = 7'h30;
+  parameter logic [BlockAw-1:0] DMA_SIGN_EXT_OFFSET = 7'h34;
+  parameter logic [BlockAw-1:0] DMA_MODE_OFFSET = 7'h38;
+  parameter logic [BlockAw-1:0] DMA_DIM_CONFIG_OFFSET = 7'h3c;
+  parameter logic [BlockAw-1:0] DMA_DIM_INV_OFFSET = 7'h40;
+  parameter logic [BlockAw-1:0] DMA_PAD_TOP_OFFSET = 7'h44;
+  parameter logic [BlockAw-1:0] DMA_PAD_BOTTOM_OFFSET = 7'h48;
+  parameter logic [BlockAw-1:0] DMA_PAD_RIGHT_OFFSET = 7'h4c;
+  parameter logic [BlockAw-1:0] DMA_PAD_LEFT_OFFSET = 7'h50;
+  parameter logic [BlockAw-1:0] DMA_WINDOW_SIZE_OFFSET = 7'h54;
+  parameter logic [BlockAw-1:0] DMA_WINDOW_COUNT_OFFSET = 7'h58;
+  parameter logic [BlockAw-1:0] DMA_INTERRUPT_EN_OFFSET = 7'h5c;
+  parameter logic [BlockAw-1:0] DMA_TRANSACTION_IFR_OFFSET = 7'h60;
+  parameter logic [BlockAw-1:0] DMA_WINDOW_IFR_OFFSET = 7'h64;
 
   // Reset values for hwext registers and their fields
   parameter logic [1:0] DMA_STATUS_RESVAL = 2'h1;
   parameter logic [0:0] DMA_STATUS_READY_RESVAL = 1'h1;
   parameter logic [0:0] DMA_STATUS_WINDOW_DONE_RESVAL = 1'h0;
+  parameter logic [0:0] DMA_TRANSACTION_IFR_RESVAL = 1'h0;
+  parameter logic [0:0] DMA_TRANSACTION_IFR_FLAG_RESVAL = 1'h0;
+  parameter logic [0:0] DMA_WINDOW_IFR_RESVAL = 1'h0;
+  parameter logic [0:0] DMA_WINDOW_IFR_FLAG_RESVAL = 1'h0;
 
   // Register index
   typedef enum int {
     DMA_SRC_PTR,
     DMA_DST_PTR,
     DMA_ADDR_PTR,
-    DMA_SIZE,
+    DMA_SIZE_D1,
+    DMA_SIZE_D2,
     DMA_STATUS,
-    DMA_PTR_INC,
+    DMA_SRC_PTR_INC_D1,
+    DMA_SRC_PTR_INC_D2,
+    DMA_DST_PTR_INC_D1,
+    DMA_DST_PTR_INC_D2,
     DMA_SLOT,
-    DMA_DATA_TYPE,
+    DMA_SRC_DATA_TYPE,
+    DMA_DST_DATA_TYPE,
+    DMA_SIGN_EXT,
     DMA_MODE,
+    DMA_DIM_CONFIG,
+    DMA_DIM_INV,
+    DMA_PAD_TOP,
+    DMA_PAD_BOTTOM,
+    DMA_PAD_RIGHT,
+    DMA_PAD_LEFT,
     DMA_WINDOW_SIZE,
     DMA_WINDOW_COUNT,
-    DMA_INTERRUPT_EN
+    DMA_INTERRUPT_EN,
+    DMA_TRANSACTION_IFR,
+    DMA_WINDOW_IFR
   } dma_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] DMA_PERMIT[12] = '{
+  parameter logic [3:0] DMA_PERMIT[26] = '{
       4'b1111,  // index[ 0] DMA_SRC_PTR
       4'b1111,  // index[ 1] DMA_DST_PTR
       4'b1111,  // index[ 2] DMA_ADDR_PTR
-      4'b1111,  // index[ 3] DMA_SIZE
-      4'b0001,  // index[ 4] DMA_STATUS
-      4'b0011,  // index[ 5] DMA_PTR_INC
-      4'b1111,  // index[ 6] DMA_SLOT
-      4'b0001,  // index[ 7] DMA_DATA_TYPE
-      4'b0001,  // index[ 8] DMA_MODE
-      4'b1111,  // index[ 9] DMA_WINDOW_SIZE
-      4'b1111,  // index[10] DMA_WINDOW_COUNT
-      4'b0001  // index[11] DMA_INTERRUPT_EN
+      4'b0011,  // index[ 3] DMA_SIZE_D1
+      4'b0011,  // index[ 4] DMA_SIZE_D2
+      4'b0001,  // index[ 5] DMA_STATUS
+      4'b0001,  // index[ 6] DMA_SRC_PTR_INC_D1
+      4'b0111,  // index[ 7] DMA_SRC_PTR_INC_D2
+      4'b0001,  // index[ 8] DMA_DST_PTR_INC_D1
+      4'b0111,  // index[ 9] DMA_DST_PTR_INC_D2
+      4'b1111,  // index[10] DMA_SLOT
+      4'b0001,  // index[11] DMA_SRC_DATA_TYPE
+      4'b0001,  // index[12] DMA_DST_DATA_TYPE
+      4'b0001,  // index[13] DMA_SIGN_EXT
+      4'b0001,  // index[14] DMA_MODE
+      4'b0001,  // index[15] DMA_DIM_CONFIG
+      4'b0001,  // index[16] DMA_DIM_INV
+      4'b0001,  // index[17] DMA_PAD_TOP
+      4'b0001,  // index[18] DMA_PAD_BOTTOM
+      4'b0001,  // index[19] DMA_PAD_RIGHT
+      4'b0001,  // index[20] DMA_PAD_LEFT
+      4'b0011,  // index[21] DMA_WINDOW_SIZE
+      4'b0001,  // index[22] DMA_WINDOW_COUNT
+      4'b0001,  // index[23] DMA_INTERRUPT_EN
+      4'b0001,  // index[24] DMA_TRANSACTION_IFR
+      4'b0001  // index[25] DMA_WINDOW_IFR
   };
 
 endpackage
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv
index 4a3ff6d0..a4004830 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv
@@ -10,7 +10,7 @@
 module dma_reg_top #(
     parameter type reg_req_t = logic,
     parameter type reg_rsp_t = logic,
-    parameter int AW = 6
+    parameter int AW = 7
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -77,41 +77,78 @@ module dma_reg_top #(
   logic [31:0] addr_ptr_qs;
   logic [31:0] addr_ptr_wd;
   logic addr_ptr_we;
-  logic [31:0] size_qs;
-  logic [31:0] size_wd;
-  logic size_we;
+  logic [15:0] size_d1_qs;
+  logic [15:0] size_d1_wd;
+  logic size_d1_we;
+  logic [15:0] size_d2_qs;
+  logic [15:0] size_d2_wd;
+  logic size_d2_we;
   logic status_ready_qs;
   logic status_ready_re;
   logic status_window_done_qs;
   logic status_window_done_re;
-  logic [7:0] ptr_inc_src_ptr_inc_qs;
-  logic [7:0] ptr_inc_src_ptr_inc_wd;
-  logic ptr_inc_src_ptr_inc_we;
-  logic [7:0] ptr_inc_dst_ptr_inc_qs;
-  logic [7:0] ptr_inc_dst_ptr_inc_wd;
-  logic ptr_inc_dst_ptr_inc_we;
+  logic [5:0] src_ptr_inc_d1_qs;
+  logic [5:0] src_ptr_inc_d1_wd;
+  logic src_ptr_inc_d1_we;
+  logic [22:0] src_ptr_inc_d2_qs;
+  logic [22:0] src_ptr_inc_d2_wd;
+  logic src_ptr_inc_d2_we;
+  logic [5:0] dst_ptr_inc_d1_qs;
+  logic [5:0] dst_ptr_inc_d1_wd;
+  logic dst_ptr_inc_d1_we;
+  logic [22:0] dst_ptr_inc_d2_qs;
+  logic [22:0] dst_ptr_inc_d2_wd;
+  logic dst_ptr_inc_d2_we;
   logic [15:0] slot_rx_trigger_slot_qs;
   logic [15:0] slot_rx_trigger_slot_wd;
   logic slot_rx_trigger_slot_we;
   logic [15:0] slot_tx_trigger_slot_qs;
   logic [15:0] slot_tx_trigger_slot_wd;
   logic slot_tx_trigger_slot_we;
-  logic [1:0] data_type_qs;
-  logic [1:0] data_type_wd;
-  logic data_type_we;
+  logic [1:0] src_data_type_qs;
+  logic [1:0] src_data_type_wd;
+  logic src_data_type_we;
+  logic [1:0] dst_data_type_qs;
+  logic [1:0] dst_data_type_wd;
+  logic dst_data_type_we;
+  logic sign_ext_qs;
+  logic sign_ext_wd;
+  logic sign_ext_we;
   logic [1:0] mode_qs;
   logic [1:0] mode_wd;
   logic mode_we;
-  logic [31:0] window_size_qs;
-  logic [31:0] window_size_wd;
+  logic dim_config_qs;
+  logic dim_config_wd;
+  logic dim_config_we;
+  logic dim_inv_qs;
+  logic dim_inv_wd;
+  logic dim_inv_we;
+  logic [5:0] pad_top_qs;
+  logic [5:0] pad_top_wd;
+  logic pad_top_we;
+  logic [5:0] pad_bottom_qs;
+  logic [5:0] pad_bottom_wd;
+  logic pad_bottom_we;
+  logic [5:0] pad_right_qs;
+  logic [5:0] pad_right_wd;
+  logic pad_right_we;
+  logic [5:0] pad_left_qs;
+  logic [5:0] pad_left_wd;
+  logic pad_left_we;
+  logic [12:0] window_size_qs;
+  logic [12:0] window_size_wd;
   logic window_size_we;
-  logic [31:0] window_count_qs;
+  logic [7:0] window_count_qs;
   logic interrupt_en_transaction_done_qs;
   logic interrupt_en_transaction_done_wd;
   logic interrupt_en_transaction_done_we;
   logic interrupt_en_window_done_qs;
   logic interrupt_en_window_done_wd;
   logic interrupt_en_window_done_we;
+  logic transaction_ifr_qs;
+  logic transaction_ifr_re;
+  logic window_ifr_qs;
+  logic window_ifr_re;
 
   // Register instances
   // R[src_ptr]: V(False)
@@ -195,30 +232,57 @@ module dma_reg_top #(
   );
 
 
-  // R[size]: V(False)
+  // R[size_d1]: V(False)
 
   prim_subreg #(
-      .DW      (32),
+      .DW      (16),
       .SWACCESS("RW"),
-      .RESVAL  (32'h0)
-  ) u_size (
+      .RESVAL  (16'h0)
+  ) u_size_d1 (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
 
       // from register interface
-      .we(size_we),
-      .wd(size_wd),
+      .we(size_d1_we),
+      .wd(size_d1_wd),
 
       // from internal hardware
       .de(1'b0),
       .d ('0),
 
       // to internal hardware
-      .qe(reg2hw.size.qe),
-      .q (reg2hw.size.q),
+      .qe(reg2hw.size_d1.qe),
+      .q (reg2hw.size_d1.q),
 
       // to register interface (read)
-      .qs(size_qs)
+      .qs(size_d1_qs)
+  );
+
+
+  // R[size_d2]: V(False)
+
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_size_d2 (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(size_d2_we),
+      .wd(size_d2_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.size_d2.qe),
+      .q (reg2hw.size_d2.q),
+
+      // to register interface (read)
+      .qs(size_d2_qs)
   );
 
 
@@ -254,20 +318,19 @@ module dma_reg_top #(
   );
 
 
-  // R[ptr_inc]: V(False)
+  // R[src_ptr_inc_d1]: V(False)
 
-  //   F[src_ptr_inc]: 7:0
   prim_subreg #(
-      .DW      (8),
+      .DW      (6),
       .SWACCESS("RW"),
-      .RESVAL  (8'h4)
-  ) u_ptr_inc_src_ptr_inc (
+      .RESVAL  (6'h4)
+  ) u_src_ptr_inc_d1 (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
 
       // from register interface
-      .we(ptr_inc_src_ptr_inc_we),
-      .wd(ptr_inc_src_ptr_inc_wd),
+      .we(src_ptr_inc_d1_we),
+      .wd(src_ptr_inc_d1_wd),
 
       // from internal hardware
       .de(1'b0),
@@ -275,25 +338,53 @@ module dma_reg_top #(
 
       // to internal hardware
       .qe(),
-      .q (reg2hw.ptr_inc.src_ptr_inc.q),
+      .q (reg2hw.src_ptr_inc_d1.q),
 
       // to register interface (read)
-      .qs(ptr_inc_src_ptr_inc_qs)
+      .qs(src_ptr_inc_d1_qs)
   );
 
 
-  //   F[dst_ptr_inc]: 15:8
+  // R[src_ptr_inc_d2]: V(False)
+
   prim_subreg #(
-      .DW      (8),
+      .DW      (23),
+      .SWACCESS("RW"),
+      .RESVAL  (23'h4)
+  ) u_src_ptr_inc_d2 (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(src_ptr_inc_d2_we),
+      .wd(src_ptr_inc_d2_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.src_ptr_inc_d2.q),
+
+      // to register interface (read)
+      .qs(src_ptr_inc_d2_qs)
+  );
+
+
+  // R[dst_ptr_inc_d1]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
       .SWACCESS("RW"),
-      .RESVAL  (8'h4)
-  ) u_ptr_inc_dst_ptr_inc (
+      .RESVAL  (6'h4)
+  ) u_dst_ptr_inc_d1 (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
 
       // from register interface
-      .we(ptr_inc_dst_ptr_inc_we),
-      .wd(ptr_inc_dst_ptr_inc_wd),
+      .we(dst_ptr_inc_d1_we),
+      .wd(dst_ptr_inc_d1_wd),
 
       // from internal hardware
       .de(1'b0),
@@ -301,10 +392,37 @@ module dma_reg_top #(
 
       // to internal hardware
       .qe(),
-      .q (reg2hw.ptr_inc.dst_ptr_inc.q),
+      .q (reg2hw.dst_ptr_inc_d1.q),
 
       // to register interface (read)
-      .qs(ptr_inc_dst_ptr_inc_qs)
+      .qs(dst_ptr_inc_d1_qs)
+  );
+
+
+  // R[dst_ptr_inc_d2]: V(False)
+
+  prim_subreg #(
+      .DW      (23),
+      .SWACCESS("RW"),
+      .RESVAL  (23'h4)
+  ) u_dst_ptr_inc_d2 (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(dst_ptr_inc_d2_we),
+      .wd(dst_ptr_inc_d2_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.dst_ptr_inc_d2.q),
+
+      // to register interface (read)
+      .qs(dst_ptr_inc_d2_qs)
   );
 
 
@@ -362,19 +480,46 @@ module dma_reg_top #(
   );
 
 
-  // R[data_type]: V(False)
+  // R[src_data_type]: V(False)
+
+  prim_subreg #(
+      .DW      (2),
+      .SWACCESS("RW"),
+      .RESVAL  (2'h0)
+  ) u_src_data_type (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(src_data_type_we),
+      .wd(src_data_type_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.src_data_type.q),
+
+      // to register interface (read)
+      .qs(src_data_type_qs)
+  );
+
+
+  // R[dst_data_type]: V(False)
 
   prim_subreg #(
       .DW      (2),
       .SWACCESS("RW"),
       .RESVAL  (2'h0)
-  ) u_data_type (
+  ) u_dst_data_type (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
 
       // from register interface
-      .we(data_type_we),
-      .wd(data_type_wd),
+      .we(dst_data_type_we),
+      .wd(dst_data_type_wd),
 
       // from internal hardware
       .de(1'b0),
@@ -382,10 +527,37 @@ module dma_reg_top #(
 
       // to internal hardware
       .qe(),
-      .q (reg2hw.data_type.q),
+      .q (reg2hw.dst_data_type.q),
 
       // to register interface (read)
-      .qs(data_type_qs)
+      .qs(dst_data_type_qs)
+  );
+
+
+  // R[sign_ext]: V(False)
+
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RW"),
+      .RESVAL  (1'h0)
+  ) u_sign_ext (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(sign_ext_we),
+      .wd(sign_ext_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.sign_ext.q),
+
+      // to register interface (read)
+      .qs(sign_ext_qs)
   );
 
 
@@ -416,12 +588,174 @@ module dma_reg_top #(
   );
 
 
+  // R[dim_config]: V(False)
+
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RW"),
+      .RESVAL  (1'h0)
+  ) u_dim_config (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(dim_config_we),
+      .wd(dim_config_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.dim_config.q),
+
+      // to register interface (read)
+      .qs(dim_config_qs)
+  );
+
+
+  // R[dim_inv]: V(False)
+
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RW"),
+      .RESVAL  (1'h0)
+  ) u_dim_inv (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(dim_inv_we),
+      .wd(dim_inv_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.dim_inv.q),
+
+      // to register interface (read)
+      .qs(dim_inv_qs)
+  );
+
+
+  // R[pad_top]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_top (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_top_we),
+      .wd(pad_top_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_top.qe),
+      .q (reg2hw.pad_top.q),
+
+      // to register interface (read)
+      .qs(pad_top_qs)
+  );
+
+
+  // R[pad_bottom]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_bottom (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_bottom_we),
+      .wd(pad_bottom_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_bottom.qe),
+      .q (reg2hw.pad_bottom.q),
+
+      // to register interface (read)
+      .qs(pad_bottom_qs)
+  );
+
+
+  // R[pad_right]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_right (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_right_we),
+      .wd(pad_right_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_right.qe),
+      .q (reg2hw.pad_right.q),
+
+      // to register interface (read)
+      .qs(pad_right_qs)
+  );
+
+
+  // R[pad_left]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_left (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_left_we),
+      .wd(pad_left_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_left.qe),
+      .q (reg2hw.pad_left.q),
+
+      // to register interface (read)
+      .qs(pad_left_qs)
+  );
+
+
   // R[window_size]: V(False)
 
   prim_subreg #(
-      .DW      (32),
+      .DW      (13),
       .SWACCESS("RW"),
-      .RESVAL  (32'h0)
+      .RESVAL  (13'h0)
   ) u_window_size (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
@@ -446,9 +780,9 @@ module dma_reg_top #(
   // R[window_count]: V(False)
 
   prim_subreg #(
-      .DW      (32),
+      .DW      (8),
       .SWACCESS("RO"),
-      .RESVAL  (32'h0)
+      .RESVAL  (8'h0)
   ) u_window_count (
       .clk_i (clk_i),
       .rst_ni(rst_ni),
@@ -523,23 +857,69 @@ module dma_reg_top #(
   );
 
 
+  // R[transaction_ifr]: V(True)
 
+  prim_subreg_ext #(
+      .DW(1)
+  ) u_transaction_ifr (
+      .re (transaction_ifr_re),
+      .we (1'b0),
+      .wd ('0),
+      .d  (hw2reg.transaction_ifr.d),
+      .qre(reg2hw.transaction_ifr.re),
+      .qe (),
+      .q  (reg2hw.transaction_ifr.q),
+      .qs (transaction_ifr_qs)
+  );
+
+
+  // R[window_ifr]: V(True)
+
+  prim_subreg_ext #(
+      .DW(1)
+  ) u_window_ifr (
+      .re (window_ifr_re),
+      .we (1'b0),
+      .wd ('0),
+      .d  (hw2reg.window_ifr.d),
+      .qre(reg2hw.window_ifr.re),
+      .qe (),
+      .q  (reg2hw.window_ifr.q),
+      .qs (window_ifr_qs)
+  );
 
-  logic [11:0] addr_hit;
+
+
+
+  logic [25:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[0] = (reg_addr == DMA_SRC_PTR_OFFSET);
     addr_hit[1] = (reg_addr == DMA_DST_PTR_OFFSET);
     addr_hit[2] = (reg_addr == DMA_ADDR_PTR_OFFSET);
-    addr_hit[3] = (reg_addr == DMA_SIZE_OFFSET);
-    addr_hit[4] = (reg_addr == DMA_STATUS_OFFSET);
-    addr_hit[5] = (reg_addr == DMA_PTR_INC_OFFSET);
-    addr_hit[6] = (reg_addr == DMA_SLOT_OFFSET);
-    addr_hit[7] = (reg_addr == DMA_DATA_TYPE_OFFSET);
-    addr_hit[8] = (reg_addr == DMA_MODE_OFFSET);
-    addr_hit[9] = (reg_addr == DMA_WINDOW_SIZE_OFFSET);
-    addr_hit[10] = (reg_addr == DMA_WINDOW_COUNT_OFFSET);
-    addr_hit[11] = (reg_addr == DMA_INTERRUPT_EN_OFFSET);
+    addr_hit[3] = (reg_addr == DMA_SIZE_D1_OFFSET);
+    addr_hit[4] = (reg_addr == DMA_SIZE_D2_OFFSET);
+    addr_hit[5] = (reg_addr == DMA_STATUS_OFFSET);
+    addr_hit[6] = (reg_addr == DMA_SRC_PTR_INC_D1_OFFSET);
+    addr_hit[7] = (reg_addr == DMA_SRC_PTR_INC_D2_OFFSET);
+    addr_hit[8] = (reg_addr == DMA_DST_PTR_INC_D1_OFFSET);
+    addr_hit[9] = (reg_addr == DMA_DST_PTR_INC_D2_OFFSET);
+    addr_hit[10] = (reg_addr == DMA_SLOT_OFFSET);
+    addr_hit[11] = (reg_addr == DMA_SRC_DATA_TYPE_OFFSET);
+    addr_hit[12] = (reg_addr == DMA_DST_DATA_TYPE_OFFSET);
+    addr_hit[13] = (reg_addr == DMA_SIGN_EXT_OFFSET);
+    addr_hit[14] = (reg_addr == DMA_MODE_OFFSET);
+    addr_hit[15] = (reg_addr == DMA_DIM_CONFIG_OFFSET);
+    addr_hit[16] = (reg_addr == DMA_DIM_INV_OFFSET);
+    addr_hit[17] = (reg_addr == DMA_PAD_TOP_OFFSET);
+    addr_hit[18] = (reg_addr == DMA_PAD_BOTTOM_OFFSET);
+    addr_hit[19] = (reg_addr == DMA_PAD_RIGHT_OFFSET);
+    addr_hit[20] = (reg_addr == DMA_PAD_LEFT_OFFSET);
+    addr_hit[21] = (reg_addr == DMA_WINDOW_SIZE_OFFSET);
+    addr_hit[22] = (reg_addr == DMA_WINDOW_COUNT_OFFSET);
+    addr_hit[23] = (reg_addr == DMA_INTERRUPT_EN_OFFSET);
+    addr_hit[24] = (reg_addr == DMA_TRANSACTION_IFR_OFFSET);
+    addr_hit[25] = (reg_addr == DMA_WINDOW_IFR_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0;
@@ -558,7 +938,21 @@ module dma_reg_top #(
                (addr_hit[ 8] & (|(DMA_PERMIT[ 8] & ~reg_be))) |
                (addr_hit[ 9] & (|(DMA_PERMIT[ 9] & ~reg_be))) |
                (addr_hit[10] & (|(DMA_PERMIT[10] & ~reg_be))) |
-               (addr_hit[11] & (|(DMA_PERMIT[11] & ~reg_be)))));
+               (addr_hit[11] & (|(DMA_PERMIT[11] & ~reg_be))) |
+               (addr_hit[12] & (|(DMA_PERMIT[12] & ~reg_be))) |
+               (addr_hit[13] & (|(DMA_PERMIT[13] & ~reg_be))) |
+               (addr_hit[14] & (|(DMA_PERMIT[14] & ~reg_be))) |
+               (addr_hit[15] & (|(DMA_PERMIT[15] & ~reg_be))) |
+               (addr_hit[16] & (|(DMA_PERMIT[16] & ~reg_be))) |
+               (addr_hit[17] & (|(DMA_PERMIT[17] & ~reg_be))) |
+               (addr_hit[18] & (|(DMA_PERMIT[18] & ~reg_be))) |
+               (addr_hit[19] & (|(DMA_PERMIT[19] & ~reg_be))) |
+               (addr_hit[20] & (|(DMA_PERMIT[20] & ~reg_be))) |
+               (addr_hit[21] & (|(DMA_PERMIT[21] & ~reg_be))) |
+               (addr_hit[22] & (|(DMA_PERMIT[22] & ~reg_be))) |
+               (addr_hit[23] & (|(DMA_PERMIT[23] & ~reg_be))) |
+               (addr_hit[24] & (|(DMA_PERMIT[24] & ~reg_be))) |
+               (addr_hit[25] & (|(DMA_PERMIT[25] & ~reg_be)))));
   end
 
   assign src_ptr_we = addr_hit[0] & reg_we & !reg_error;
@@ -570,40 +964,77 @@ module dma_reg_top #(
   assign addr_ptr_we = addr_hit[2] & reg_we & !reg_error;
   assign addr_ptr_wd = reg_wdata[31:0];
 
-  assign size_we = addr_hit[3] & reg_we & !reg_error;
-  assign size_wd = reg_wdata[31:0];
+  assign size_d1_we = addr_hit[3] & reg_we & !reg_error;
+  assign size_d1_wd = reg_wdata[15:0];
+
+  assign size_d2_we = addr_hit[4] & reg_we & !reg_error;
+  assign size_d2_wd = reg_wdata[15:0];
+
+  assign status_ready_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign status_ready_re = addr_hit[4] & reg_re & !reg_error;
+  assign status_window_done_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign status_window_done_re = addr_hit[4] & reg_re & !reg_error;
+  assign src_ptr_inc_d1_we = addr_hit[6] & reg_we & !reg_error;
+  assign src_ptr_inc_d1_wd = reg_wdata[5:0];
 
-  assign ptr_inc_src_ptr_inc_we = addr_hit[5] & reg_we & !reg_error;
-  assign ptr_inc_src_ptr_inc_wd = reg_wdata[7:0];
+  assign src_ptr_inc_d2_we = addr_hit[7] & reg_we & !reg_error;
+  assign src_ptr_inc_d2_wd = reg_wdata[22:0];
 
-  assign ptr_inc_dst_ptr_inc_we = addr_hit[5] & reg_we & !reg_error;
-  assign ptr_inc_dst_ptr_inc_wd = reg_wdata[15:8];
+  assign dst_ptr_inc_d1_we = addr_hit[8] & reg_we & !reg_error;
+  assign dst_ptr_inc_d1_wd = reg_wdata[5:0];
 
-  assign slot_rx_trigger_slot_we = addr_hit[6] & reg_we & !reg_error;
+  assign dst_ptr_inc_d2_we = addr_hit[9] & reg_we & !reg_error;
+  assign dst_ptr_inc_d2_wd = reg_wdata[22:0];
+
+  assign slot_rx_trigger_slot_we = addr_hit[10] & reg_we & !reg_error;
   assign slot_rx_trigger_slot_wd = reg_wdata[15:0];
 
-  assign slot_tx_trigger_slot_we = addr_hit[6] & reg_we & !reg_error;
+  assign slot_tx_trigger_slot_we = addr_hit[10] & reg_we & !reg_error;
   assign slot_tx_trigger_slot_wd = reg_wdata[31:16];
 
-  assign data_type_we = addr_hit[7] & reg_we & !reg_error;
-  assign data_type_wd = reg_wdata[1:0];
+  assign src_data_type_we = addr_hit[11] & reg_we & !reg_error;
+  assign src_data_type_wd = reg_wdata[1:0];
+
+  assign dst_data_type_we = addr_hit[12] & reg_we & !reg_error;
+  assign dst_data_type_wd = reg_wdata[1:0];
 
-  assign mode_we = addr_hit[8] & reg_we & !reg_error;
+  assign sign_ext_we = addr_hit[13] & reg_we & !reg_error;
+  assign sign_ext_wd = reg_wdata[0];
+
+  assign mode_we = addr_hit[14] & reg_we & !reg_error;
   assign mode_wd = reg_wdata[1:0];
 
-  assign window_size_we = addr_hit[9] & reg_we & !reg_error;
-  assign window_size_wd = reg_wdata[31:0];
+  assign dim_config_we = addr_hit[15] & reg_we & !reg_error;
+  assign dim_config_wd = reg_wdata[0];
+
+  assign dim_inv_we = addr_hit[16] & reg_we & !reg_error;
+  assign dim_inv_wd = reg_wdata[0];
 
-  assign interrupt_en_transaction_done_we = addr_hit[11] & reg_we & !reg_error;
+  assign pad_top_we = addr_hit[17] & reg_we & !reg_error;
+  assign pad_top_wd = reg_wdata[5:0];
+
+  assign pad_bottom_we = addr_hit[18] & reg_we & !reg_error;
+  assign pad_bottom_wd = reg_wdata[5:0];
+
+  assign pad_right_we = addr_hit[19] & reg_we & !reg_error;
+  assign pad_right_wd = reg_wdata[5:0];
+
+  assign pad_left_we = addr_hit[20] & reg_we & !reg_error;
+  assign pad_left_wd = reg_wdata[5:0];
+
+  assign window_size_we = addr_hit[21] & reg_we & !reg_error;
+  assign window_size_wd = reg_wdata[12:0];
+
+  assign interrupt_en_transaction_done_we = addr_hit[23] & reg_we & !reg_error;
   assign interrupt_en_transaction_done_wd = reg_wdata[0];
 
-  assign interrupt_en_window_done_we = addr_hit[11] & reg_we & !reg_error;
+  assign interrupt_en_window_done_we = addr_hit[23] & reg_we & !reg_error;
   assign interrupt_en_window_done_wd = reg_wdata[1];
 
+  assign transaction_ifr_re = addr_hit[24] & reg_re & !reg_error;
+
+  assign window_ifr_re = addr_hit[25] & reg_re & !reg_error;
+
   // Read data return
   always_comb begin
     reg_rdata_next = '0;
@@ -621,45 +1052,100 @@ module dma_reg_top #(
       end
 
       addr_hit[3]: begin
-        reg_rdata_next[31:0] = size_qs;
+        reg_rdata_next[15:0] = size_d1_qs;
       end
 
       addr_hit[4]: begin
-        reg_rdata_next[0] = status_ready_qs;
-        reg_rdata_next[1] = status_window_done_qs;
+        reg_rdata_next[15:0] = size_d2_qs;
       end
 
       addr_hit[5]: begin
-        reg_rdata_next[7:0]  = ptr_inc_src_ptr_inc_qs;
-        reg_rdata_next[15:8] = ptr_inc_dst_ptr_inc_qs;
+        reg_rdata_next[0] = status_ready_qs;
+        reg_rdata_next[1] = status_window_done_qs;
       end
 
       addr_hit[6]: begin
-        reg_rdata_next[15:0]  = slot_rx_trigger_slot_qs;
-        reg_rdata_next[31:16] = slot_tx_trigger_slot_qs;
+        reg_rdata_next[5:0] = src_ptr_inc_d1_qs;
       end
 
       addr_hit[7]: begin
-        reg_rdata_next[1:0] = data_type_qs;
+        reg_rdata_next[22:0] = src_ptr_inc_d2_qs;
       end
 
       addr_hit[8]: begin
-        reg_rdata_next[1:0] = mode_qs;
+        reg_rdata_next[5:0] = dst_ptr_inc_d1_qs;
       end
 
       addr_hit[9]: begin
-        reg_rdata_next[31:0] = window_size_qs;
+        reg_rdata_next[22:0] = dst_ptr_inc_d2_qs;
       end
 
       addr_hit[10]: begin
-        reg_rdata_next[31:0] = window_count_qs;
+        reg_rdata_next[15:0]  = slot_rx_trigger_slot_qs;
+        reg_rdata_next[31:16] = slot_tx_trigger_slot_qs;
       end
 
       addr_hit[11]: begin
+        reg_rdata_next[1:0] = src_data_type_qs;
+      end
+
+      addr_hit[12]: begin
+        reg_rdata_next[1:0] = dst_data_type_qs;
+      end
+
+      addr_hit[13]: begin
+        reg_rdata_next[0] = sign_ext_qs;
+      end
+
+      addr_hit[14]: begin
+        reg_rdata_next[1:0] = mode_qs;
+      end
+
+      addr_hit[15]: begin
+        reg_rdata_next[0] = dim_config_qs;
+      end
+
+      addr_hit[16]: begin
+        reg_rdata_next[0] = dim_inv_qs;
+      end
+
+      addr_hit[17]: begin
+        reg_rdata_next[5:0] = pad_top_qs;
+      end
+
+      addr_hit[18]: begin
+        reg_rdata_next[5:0] = pad_bottom_qs;
+      end
+
+      addr_hit[19]: begin
+        reg_rdata_next[5:0] = pad_right_qs;
+      end
+
+      addr_hit[20]: begin
+        reg_rdata_next[5:0] = pad_left_qs;
+      end
+
+      addr_hit[21]: begin
+        reg_rdata_next[12:0] = window_size_qs;
+      end
+
+      addr_hit[22]: begin
+        reg_rdata_next[7:0] = window_count_qs;
+      end
+
+      addr_hit[23]: begin
         reg_rdata_next[0] = interrupt_en_transaction_done_qs;
         reg_rdata_next[1] = interrupt_en_window_done_qs;
       end
 
+      addr_hit[24]: begin
+        reg_rdata_next[0] = transaction_ifr_qs;
+      end
+
+      addr_hit[25]: begin
+        reg_rdata_next[0] = window_ifr_qs;
+      end
+
       default: begin
         reg_rdata_next = '1;
       end
@@ -681,7 +1167,7 @@ module dma_reg_top #(
 endmodule
 
 module dma_reg_top_intf #(
-    parameter  int AW = 6,
+    parameter  int AW = 7,
     localparam int DW = 32
 ) (
     input logic clk_i,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core
new file mode 100644
index 00000000..1fa1b17b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core
@@ -0,0 +1,21 @@
+CAPI=2:
+
+name: "x-heep:ip:dma_subsystem"
+description: "core-v-mini-mcu dma peripheral"
+
+# Copyright 2021 OpenHW Group
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+filesets:
+  files_rtl:
+    depend:
+      - pulp-platform.org::common_cells
+    files:
+    - rtl/dma_subsystem.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+    - files_rtl
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.vlt b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.vlt
new file mode 100644
index 00000000..a914d355
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.vlt
@@ -0,0 +1,10 @@
+// Copyright 2022 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+`verilator_config
+ 
+lint_off -rule UNUSED -file "*/rtl/dma_subsystem.sv" -match "Signal is not used: 'data_out_rvalid'"
+lint_off -rule UNUSED -file "*/rtl/dma_subsystem.sv" -match "Signal is not used: 'data_out_rdata'"
+
+lint_off -rule UNUSED -file "*/rtl/dma_subsystem.sv" -match "Bits of signal are not used: *"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv
new file mode 100644
index 00000000..22274b69
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *  
+ * Info: DMA subsystem, it instantiates 1 to 8 DMA channels and manages the data transfers.
+ */
+
+
+module dma_subsystem #(
+    parameter type reg_req_t = logic,
+    parameter type reg_rsp_t = logic,
+    parameter type obi_req_t = logic,
+    parameter type obi_resp_t = logic,
+    parameter int unsigned GLOBAL_SLOT_NUM = 0,
+    parameter int unsigned EXT_SLOT_NUM = 0
+) (
+    input logic clk_i,
+    input logic rst_ni,
+
+    input  reg_req_t reg_req_i,
+    output reg_rsp_t reg_rsp_o,
+
+    output obi_req_t  dma_read_ch0_req_o,
+    input  obi_resp_t dma_read_ch0_resp_i,
+
+    output obi_req_t  dma_write_ch0_req_o,
+    input  obi_resp_t dma_write_ch0_resp_i,
+
+    output obi_req_t  dma_addr_ch0_req_o,
+    input  obi_resp_t dma_addr_ch0_resp_i,
+
+    input logic [GLOBAL_SLOT_NUM-1:0] global_trigger_slot_i,
+    input logic [EXT_SLOT_NUM-1:0] ext_trigger_slot_i,
+
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
+
+    output dma_done_intr_o,
+    output dma_window_intr_o
+);
+
+
+  import obi_pkg::*;
+  import reg_pkg::*;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* Masters requests to the bus */
+  obi_req_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] xbar_write_req;
+  obi_req_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] xbar_read_req;
+  obi_req_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] xbar_address_req;
+
+  /* Masters response from the bus*/
+  obi_resp_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] xbar_write_resp;
+  obi_resp_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] xbar_read_resp;
+  obi_resp_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] xbar_address_resp;
+
+  /* Interrupt signals */
+  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_trans_done;
+  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_window_done;
+
+  /* Register interfaces from register demux to DMAs */
+  reg_pkg::reg_req_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] submodules_req;
+  reg_pkg::reg_rsp_t [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] submodules_rsp;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Module instantiation */
+
+  /* DMA modules */
+  generate
+    for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_CH_NUM; i++) begin : dma_i_gen
+      dma #(
+          .reg_req_t (reg_pkg::reg_req_t),
+          .reg_rsp_t (reg_pkg::reg_rsp_t),
+          .obi_req_t (obi_pkg::obi_req_t),
+          .obi_resp_t(obi_pkg::obi_resp_t),
+          .SLOT_NUM  (GLOBAL_SLOT_NUM + 2)
+      ) dma_i (
+          .clk_i,
+          .rst_ni,
+          .ext_dma_stop_i(ext_dma_stop_i[i]),
+          .reg_req_i(submodules_req[i]),
+          .reg_rsp_o(submodules_rsp[i]),
+          .dma_read_ch0_req_o(xbar_read_req[i]),
+          .dma_read_ch0_resp_i(xbar_read_resp[i]),
+          .dma_write_ch0_req_o(xbar_write_req[i]),
+          .dma_write_ch0_resp_i(xbar_write_resp[i]),
+          .dma_addr_ch0_req_o(xbar_address_req[i]),
+          .dma_addr_ch0_resp_i(xbar_address_resp[i]),
+          .trigger_slot_i({
+            ext_trigger_slot_i[2*i+1], ext_trigger_slot_i[2*i], global_trigger_slot_i
+          }),
+          .dma_done_intr_o(dma_trans_done[i]),
+          .dma_window_intr_o(dma_window_done[i])
+      );
+    end
+  endgenerate
+
+
+  generate
+    if (core_v_mini_mcu_pkg::DMA_CH_NUM > 1) begin : xbar_varlat_n_to_one_gen
+
+      /* Register interface routing signals */
+      logic [core_v_mini_mcu_pkg::DMA_CH_PORT_SEL_WIDTH-1:0] submodules_select;
+
+      /* Read, write & address mode operations xbar*/
+      xbar_varlat_n_to_one #(
+          .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
+      ) xbar_read_i (
+          .clk_i        (clk_i),
+          .rst_ni       (rst_ni),
+          .master_req_i (xbar_read_req),
+          .master_resp_o(xbar_read_resp),
+          .slave_req_o  (dma_read_ch0_req_o),
+          .slave_resp_i (dma_read_ch0_resp_i)
+      );
+
+      xbar_varlat_n_to_one #(
+          .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
+      ) xbar_write_i (
+          .clk_i        (clk_i),
+          .rst_ni       (rst_ni),
+          .master_req_i (xbar_write_req),
+          .master_resp_o(xbar_write_resp),
+          .slave_req_o  (dma_write_ch0_req_o),
+          .slave_resp_i (dma_write_ch0_resp_i)
+      );
+
+      xbar_varlat_n_to_one #(
+          .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
+      ) xbar_address_i (
+          .clk_i        (clk_i),
+          .rst_ni       (rst_ni),
+          .master_req_i (xbar_address_req),
+          .master_resp_o(xbar_address_resp),
+          .slave_req_o  (dma_addr_ch0_req_o),
+          .slave_resp_i (dma_addr_ch0_resp_i)
+      );
+
+      /* Internal address decoder */
+      addr_decode #(
+          .NoIndices(core_v_mini_mcu_pkg::DMA_CH_NUM),
+          .NoRules(core_v_mini_mcu_pkg::DMA_CH_NUM),
+          .addr_t(logic [7:0]),
+          .rule_t(addr_map_rule_pkg::addr_map_rule_8bit_t)
+      ) addr_dec_i (
+          .addr_i(reg_req_i.addr[15:8]),
+          .addr_map_i(core_v_mini_mcu_pkg::DMA_ADDR_RULES),
+          .idx_o(submodules_select),
+          .dec_valid_o(),
+          .dec_error_o(),
+          .en_default_idx_i(1'b0),
+          .default_idx_i('0)
+      );
+
+      /* Register demux */
+      reg_demux #(
+          .NoPorts(core_v_mini_mcu_pkg::DMA_CH_NUM),
+          .req_t  (reg_pkg::reg_req_t),
+          .rsp_t  (reg_pkg::reg_rsp_t)
+      ) reg_demux_i (
+          .clk_i,
+          .rst_ni,
+          .in_select_i(submodules_select),
+          .in_req_i(reg_req_i),
+          .in_rsp_o(reg_rsp_o),
+          .out_req_o(submodules_req),
+          .out_rsp_i(submodules_rsp)
+      );
+
+    end else begin
+
+      /* Bus ports routing in the case of a single DMA */
+      assign dma_read_ch0_req_o = xbar_read_req[0];
+      assign xbar_read_resp[0] = dma_read_ch0_resp_i;
+      assign dma_write_ch0_req_o = xbar_write_req[0];
+      assign xbar_write_resp[0] = dma_write_ch0_resp_i;
+      assign dma_addr_ch0_req_o = xbar_address_req[0];
+      assign xbar_address_resp[0] = dma_addr_ch0_resp_i;
+      assign submodules_req[0] = reg_req_i;
+      assign reg_rsp_o = submodules_rsp[0];
+    end
+  endgenerate
+
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  assign dma_done_intr_o   = |(dma_trans_done);
+  assign dma_window_intr_o = |(dma_window_done);
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_rx_channel.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_rx_channel.sv
index 3c0066a7..52e48f9d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_rx_channel.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/i2s/rtl/i2s_rx_channel.sv
@@ -153,7 +153,7 @@ module i2s_rx_channel #(
   // worst case drop even number of samples
   always_ff @(posedge sck_i, negedge rst_ni) begin
     if (~rst_ni) begin
-      last_data_ws <= ~start_channel_i;
+      last_data_ws <= 1'b0;
     end else begin
       if (~en) begin
         last_data_ws <= ~start_channel_i;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/fir.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/fir.sv
index 6d22d673..ce17a7a6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/fir.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/fir.sv
@@ -48,7 +48,9 @@ module fir #(
   genvar k;
   generate
     for (k = 0; k < TOTCOEFS; k = k + 1) begin : coeffs_mapping
-      assign coeffs[k] = freecoeffs[int'($floor($sqrt($pow((TOTCOEFS-1)/2.0-k, 2))))];
+      // Remove $pow function to avoid errors in Synopsys DC
+      // assign coeffs[k] = freecoeffs[int'($floor($sqrt($pow((TOTCOEFS-1)/2.0-k, 2))))];
+      assign coeffs[k] = freecoeffs[int'($floor($sqrt(((TOTCOEFS-1)/2.0-k)*((TOTCOEFS-1)/2.0-k))))];
     end
   endgenerate
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/halfband.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/halfband.sv
index 9d9355c8..a0710c58 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/halfband.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/halfband.sv
@@ -63,7 +63,11 @@ module halfband #(
   genvar k;
   generate
     for (k = 0; k < TOTCOEFS; k = k + 1) begin : coeffs_mapping
-      assign coeffs[k] = lessfreecoeffs[int'($floor($sqrt($pow((TOTCOEFS-1)/2.0-k, 2))))];
+      // Remove $pow function to avoid errors in Synopsys DC
+      // assign coeffs[k] = lessfreecoeffs[int'($floor($sqrt($pow((TOTCOEFS-1)/2.0-k, 2))))];
+      assign coeffs[k] = lessfreecoeffs[int'($floor(
+          $sqrt(((TOTCOEFS-1)/2.0-k)*((TOTCOEFS-1)/2.0-k))
+      ))];
     end
   endgenerate
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl
index fb544a59..0d336255 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl
@@ -19,12 +19,22 @@
     }
 
     { name:     "RESTORE_ADDRESS",
-      desc:     "Restore xddress value",
+      desc:     "Restore address value",
       resval:   "0x00000000"
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "31:0", name: "RESTORE_XDDRESS", desc: "Restore xddress Reg, used by BOOTROM" }
+        { bits: "31:0", name: "RESTORE_ADDRESS", desc: "Restore address Reg, used by BOOTROM" }
+      ]
+    }
+
+    { name:     "GLOBAL_POINTER",
+      desc:     "Global Pointer value",
+      resval:   "0x00000000"
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "GLOBAL_POINTER", desc: "Global Reg, used by power manager HAL" }
       ]
     }
 
@@ -214,64 +224,64 @@
     }
 
 
-% for bank in range(ram_numbanks):
-    { name:     "RAM_${bank}_CLK_GATE",
-      desc:     "Clock-gates the RAM_${bank} domain",
+% for bank in xheep.iter_ram_banks():
+    { name:     "RAM_${bank.name()}_CLK_GATE",
+      desc:     "Clock-gates the RAM_${bank.name()} domain",
       resval:   "0x00000000"
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "0", name: "RAM_${bank}_CLK_GATE", desc: "Clock-gates the RAM_${bank} domain" }
+        { bits: "0", name: "RAM_${bank.name()}_CLK_GATE", desc: "Clock-gates the RAM_${bank.name()} domain" }
       ]
     }
 
-    { name:     "POWER_GATE_RAM_BLOCK_${bank}_ACK",
-      desc:     "Used by the ram ${bank} switch to ack the power manager",
+    { name:     "POWER_GATE_RAM_BLOCK_${bank.name()}_ACK",
+      desc:     "Used by the ram ${bank.name()} switch to ack the power manager",
       resval:   "0x00000000"
       swaccess: "ro",
       hwaccess: "hrw",
       fields: [
-        { bits: "0", name: "POWER_GATE_RAM_BLOCK_${bank}_ACK", desc: "Power Gate Ram Block ${bank} Ack Reg" }
+        { bits: "0", name: "POWER_GATE_RAM_BLOCK_${bank.name()}_ACK", desc: "Power Gate Ram Block ${bank.name()} Ack Reg" }
       ]
     }
 
-    { name:     "RAM_${bank}_SWITCH",
-      desc:     "Switch off the RAM_${bank} domain",
+    { name:     "RAM_${bank.name()}_SWITCH",
+      desc:     "Switch off the RAM_${bank.name()} domain",
       resval:   "0x00000000"
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "0", name: "RAM_${bank}_SWITCH", desc: "Switch off RAM_${bank} domain" }
+        { bits: "0", name: "RAM_${bank.name()}_SWITCH", desc: "Switch off RAM_${bank.name()} domain" }
       ]
     }
 
-    { name:     "RAM_${bank}_WAIT_ACK_SWITCH_ON",
-      desc:     "Wait for the RAM_${bank} domain switch ack",
+    { name:     "RAM_${bank.name()}_WAIT_ACK_SWITCH_ON",
+      desc:     "Wait for the RAM_${bank.name()} domain switch ack",
       resval:   "0x00000000"
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "0", name: "RAM_${bank}_WAIT_ACK_SWITCH_ON", desc: "Wait RAM_${bank} domain switch ack" }
+        { bits: "0", name: "RAM_${bank.name()}_WAIT_ACK_SWITCH_ON", desc: "Wait RAM_${bank.name()} domain switch ack" }
       ]
     }
 
-    { name:     "RAM_${bank}_ISO",
-      desc:     "Set on the isolation of the RAM_${bank} domain",
+    { name:     "RAM_${bank.name()}_ISO",
+      desc:     "Set on the isolation of the RAM_${bank.name()} domain",
       resval:   "0x00000000"
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "0", name: "RAM_${bank}_ISO", desc: "Set on isolation of RAM_${bank} domain" }
+        { bits: "0", name: "RAM_${bank.name()}_ISO", desc: "Set on isolation of RAM_${bank.name()} domain" }
       ]
     }
 
-    { name:     "RAM_${bank}_RETENTIVE",
-      desc:     "Set on retentive mode for the RAM_${bank} domain",
+    { name:     "RAM_${bank.name()}_RETENTIVE",
+      desc:     "Set on retentive mode for the RAM_${bank.name()} domain",
       resval:   "0x00000000"
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
-        { bits: "0", name: "RAM_${bank}_RETENTIVE", desc: "Set on retentive mode for RAM_${bank} domain" }
+        { bits: "0", name: "RAM_${bank.name()}_RETENTIVE", desc: "Set on retentive mode for RAM_${bank.name()} domain" }
       ]
     }
 
@@ -368,14 +378,14 @@
       ]
     }
 
-% for bank in range(ram_numbanks):
-    { name:     "MONITOR_POWER_GATE_RAM_BLOCK_${bank}",
-      desc:     "Used to monitor the signals to power gate ram block ${bank}",
+% for bank in xheep.iter_ram_banks():
+    { name:     "MONITOR_POWER_GATE_RAM_BLOCK_${bank.name()}",
+      desc:     "Used to monitor the signals to power gate ram block ${bank.name()}",
       resval:   "0x00000000"
       swaccess: "ro",
       hwaccess: "hwo",
       fields: [
-        { bits: "1:0", name: "MONITOR_POWER_GATE_RAM_BLOCK_${bank}", desc: "Monitor Signals Power Gate Ram Block ${bank} Reg" }
+        { bits: "1:0", name: "MONITOR_POWER_GATE_RAM_BLOCK_${bank.name()}", desc: "Monitor Signals Power Gate Ram Block ${bank.name()} Reg" }
       ]
     }
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl
index 4b8ba22b..0e126670 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl
@@ -4,7 +4,7 @@
 
 `include "common_cells/assertions.svh"
 
-module power_manager #(
+module power_manager import power_manager_pkg::*; #(
     parameter type reg_req_t = logic,
     parameter type reg_rsp_t = logic,
     parameter logic SWITCH_IDLE_VALUE = 1'b1, //the value to have Vdd.daughter = Vdd.mother, i.e. on state
@@ -44,29 +44,18 @@ module power_manager #(
     // External interrupts
     input logic [NEXT_INT_RND-1:0] ext_irq_i,
 
-    // Clock gating signals
-    output logic peripheral_subsystem_clkgate_en_no,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0]memory_subsystem_clkgate_en_no,
-    output logic [EXT_DOMAINS_RND-1:0]external_subsystem_clkgate_en_no,
-
-    // Power gating signals
-    output logic cpu_subsystem_powergate_switch_no,
-    input  logic cpu_subsystem_powergate_switch_ack_ni,
-    output logic cpu_subsystem_powergate_iso_no,
-    output logic cpu_subsystem_rst_no,
-    output logic peripheral_subsystem_powergate_switch_no,
-    input  logic peripheral_subsystem_powergate_switch_ack_ni,
-    output logic peripheral_subsystem_powergate_iso_no,
-    output logic peripheral_subsystem_rst_no,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_no,
-    input  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack_ni,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso_no,
-    output logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_set_retentive_no,
-    output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_no,
-    input  logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_switch_ack_ni,
-    output logic [EXT_DOMAINS_RND-1:0] external_subsystem_powergate_iso_no,
-    output logic [EXT_DOMAINS_RND-1:0] external_subsystem_rst_no,
-    output logic [EXT_DOMAINS_RND-1:0] external_ram_banks_set_retentive_no
+    // Power Manager output signals
+    output power_manager_out_t cpu_subsystem_pwr_ctrl_o,
+    output power_manager_out_t peripheral_subsystem_pwr_ctrl_o,
+    output power_manager_out_t memory_subsystem_pwr_ctrl_o[core_v_mini_mcu_pkg::NUM_BANKS-1:0],
+    output power_manager_out_t external_subsystem_pwr_ctrl_o[EXT_DOMAINS_RND-1:0],
+
+    // Power Manager input signals
+    input power_manager_in_t cpu_subsystem_pwr_ctrl_i,
+    input power_manager_in_t peripheral_subsystem_pwr_ctrl_i,
+    input power_manager_in_t memory_subsystem_pwr_ctrl_i[core_v_mini_mcu_pkg::NUM_BANKS-1:0],
+    input power_manager_in_t external_subsystem_pwr_ctrl_i[EXT_DOMAINS_RND-1:0]
+
 );
 
   import power_manager_reg_pkg::*;
@@ -123,37 +112,38 @@ module power_manager #(
   logic [core_v_mini_mcu_pkg::EXTERNAL_DOMAINS-1:0] external_subsystem_rst_n;
 % endif
 
-  assign cpu_subsystem_powergate_switch_no = cpu_subsystem_powergate_switch_n;
-  assign cpu_subsystem_powergate_iso_no = cpu_subsystem_powergate_iso_n;
-  assign cpu_subsystem_rst_no = cpu_subsystem_rst_n;
-  assign peripheral_subsystem_powergate_switch_no = peripheral_subsystem_powergate_switch_n;
-  assign peripheral_subsystem_powergate_iso_no = peripheral_subsystem_powergate_iso_n;
-  assign peripheral_subsystem_rst_no = peripheral_subsystem_rst_n;
-  assign memory_subsystem_banks_powergate_switch_no = memory_subsystem_banks_powergate_switch_n;
-  assign memory_subsystem_banks_powergate_iso_no = memory_subsystem_banks_powergate_iso_n;
-% if external_domains != 0:
-  assign external_subsystem_powergate_switch_no = external_subsystem_powergate_switch_n;
-  assign external_subsystem_powergate_iso_no = external_subsystem_powergate_iso_n;
-  assign external_subsystem_rst_no = external_subsystem_rst_n;
-% else:
-  assign external_subsystem_powergate_switch_no = '0;
-  assign external_subsystem_powergate_iso_no = '0;
-  assign external_subsystem_rst_no = '0;
-% endif
-
-  // --------------------------------------------------------------------------------------
-  // CLK_GATING
-  // --------------------------------------------------------------------------------------
-
-    assign peripheral_subsystem_clkgate_en_no = ~reg2hw.periph_clk_gate.q;
-
-% for bank in range(ram_numbanks):
-    assign memory_subsystem_clkgate_en_no[${bank}] = ~reg2hw.ram_${bank}_clk_gate.q;
+  assign cpu_subsystem_pwr_ctrl_o.pwrgate_en_n = cpu_subsystem_powergate_switch_n;
+  assign cpu_subsystem_pwr_ctrl_o.isogate_en_n = cpu_subsystem_powergate_iso_n;
+  assign cpu_subsystem_pwr_ctrl_o.rst_n = cpu_subsystem_rst_n;
+  assign cpu_subsystem_pwr_ctrl_o.clkgate_en_n = 1'b1; //unused, the CPU clk gates itself via WFI
+  assign cpu_subsystem_pwr_ctrl_o.retentive_en_n = 1'b1; //unused
+
+  assign peripheral_subsystem_pwr_ctrl_o.pwrgate_en_n = peripheral_subsystem_powergate_switch_n;
+  assign peripheral_subsystem_pwr_ctrl_o.isogate_en_n = peripheral_subsystem_powergate_iso_n;
+  assign peripheral_subsystem_pwr_ctrl_o.rst_n = peripheral_subsystem_rst_n;
+  assign peripheral_subsystem_pwr_ctrl_o.retentive_en_n = 1'b1; //unused
+  assign peripheral_subsystem_pwr_ctrl_o.clkgate_en_n = ~reg2hw.periph_clk_gate.q;
+
+% for bank in xheep.iter_ram_banks():
+  assign memory_subsystem_pwr_ctrl_o[${bank.name()}].pwrgate_en_n = memory_subsystem_banks_powergate_switch_n[${bank.name()}];
+  assign memory_subsystem_pwr_ctrl_o[${bank.name()}].isogate_en_n = memory_subsystem_banks_powergate_iso_n[${bank.name()}];
+  assign memory_subsystem_pwr_ctrl_o[${bank.name()}].rst_n = 1'b1;
+  assign memory_subsystem_pwr_ctrl_o[${bank.name()}].clkgate_en_n = ~reg2hw.ram_${bank.name()}_clk_gate.q;
 % endfor
 
+% if external_domains != 0:
 % for ext in range(external_domains):
-    assign external_subsystem_clkgate_en_no[${ext}] = ~reg2hw.external_${ext}_clk_gate.q;
+    assign external_subsystem_pwr_ctrl_o[${ext}].pwrgate_en_n = external_subsystem_powergate_switch_n[${ext}];
+    assign external_subsystem_pwr_ctrl_o[${ext}].isogate_en_n = external_subsystem_powergate_iso_n[${ext}];
+    assign external_subsystem_pwr_ctrl_o[${ext}].rst_n = external_subsystem_rst_n[${ext}];
+    assign external_subsystem_pwr_ctrl_o[${ext}].clkgate_en_n = ~reg2hw.external_${ext}_clk_gate.q;
 % endfor
+% else:
+    assign external_subsystem_pwr_ctrl_o[0].pwrgate_en_n = 1'b1;
+    assign external_subsystem_pwr_ctrl_o[0].isogate_en_n = 1'b1;
+    assign external_subsystem_pwr_ctrl_o[0].rst_n = 1'b1;
+    assign external_subsystem_pwr_ctrl_o[0].clkgate_en_n = 1'b1;
+% endif
 
   // --------------------------------------------------------------------------------------
   // CPU_SUBSYSTEM DOMAIN
@@ -166,7 +156,7 @@ module power_manager #(
   ) sync_cpu_ack_i (
       .clk_i,
       .rst_ni,
-      .serial_i(cpu_subsystem_powergate_switch_ack_ni),
+      .serial_i(cpu_subsystem_pwr_ctrl_i.pwrgate_ack_n),
       .serial_o(cpu_subsystem_powergate_switch_ack_sync)
   );
 
@@ -358,7 +348,7 @@ module power_manager #(
   ) sync_periph_ack_i (
       .clk_i,
       .rst_ni,
-      .serial_i(peripheral_subsystem_powergate_switch_ack_ni),
+      .serial_i(peripheral_subsystem_pwr_ctrl_i.pwrgate_ack_n),
       .serial_o(peripheral_subsystem_powergate_switch_ack_sync)
   );
 
@@ -417,75 +407,75 @@ module power_manager #(
       .switch_onoff_signal_o(peripheral_subsystem_powergate_iso_n)
   );
 
-% for bank in range(ram_numbanks):
+% for bank in xheep.iter_ram_banks():
   // --------------------------------------------------------------------------------------
-  // RAM_${bank} DOMAIN
+  // RAM_${bank.name()} DOMAIN
   // --------------------------------------------------------------------------------------
 
-  logic ram_${bank}_subsystem_powergate_switch_ack_sync;
+  logic ram_${bank.name()}_subsystem_powergate_switch_ack_sync;
 
   sync #(
       .ResetValue(1'b0)
-  ) sync_ram_${bank}_ack_i (
+  ) sync_ram_${bank.name()}_ack_i (
       .clk_i,
       .rst_ni,
-      .serial_i(memory_subsystem_banks_powergate_switch_ack_ni[${bank}]),
-      .serial_o(ram_${bank}_subsystem_powergate_switch_ack_sync)
+      .serial_i(memory_subsystem_pwr_ctrl_i[${bank.name()}].pwrgate_ack_n),
+      .serial_o(ram_${bank.name()}_subsystem_powergate_switch_ack_sync)
   );
 
-  assign hw2reg.power_gate_ram_block_${bank}_ack.de = 1'b1;
-  assign hw2reg.power_gate_ram_block_${bank}_ack.d = ram_${bank}_subsystem_powergate_switch_ack_sync;
+  assign hw2reg.power_gate_ram_block_${bank.name()}_ack.de = 1'b1;
+  assign hw2reg.power_gate_ram_block_${bank.name()}_ack.d = ram_${bank.name()}_subsystem_powergate_switch_ack_sync;
 
   //if you want to wait for ACK, or just bypass it
-  logic ram_${bank}_switch_wait_ack;
-  assign ram_${bank}_switch_wait_ack = reg2hw.ram_${bank}_wait_ack_switch_on.q ? reg2hw.power_gate_ram_block_${bank}_ack.q == SWITCH_IDLE_VALUE : 1'b1;
+  logic ram_${bank.name()}_switch_wait_ack;
+  assign ram_${bank.name()}_switch_wait_ack = reg2hw.ram_${bank.name()}_wait_ack_switch_on.q ? reg2hw.power_gate_ram_block_${bank.name()}_ack.q == SWITCH_IDLE_VALUE : 1'b1;
 
   power_manager_sequence #(
       .IDLE_VALUE(SWITCH_IDLE_VALUE),
       .ONOFF_AT_RESET(SWITCH_VALUE_AT_RESET)
-  ) power_manager_sequence_ram_${bank}_switch_i (
+  ) power_manager_sequence_ram_${bank.name()}_switch_i (
       .clk_i,
       .rst_ni,
 
       // trigger to start the sequence
-      .start_off_sequence_i(reg2hw.ram_${bank}_switch.q),
-      .start_on_sequence_i (~reg2hw.ram_${bank}_switch.q),
+      .start_off_sequence_i(reg2hw.ram_${bank.name()}_switch.q),
+      .start_on_sequence_i (~reg2hw.ram_${bank.name()}_switch.q),
       .switch_ack_i (1'b1),
 
       // switch on and off signal, 1 means on
-      .switch_onoff_signal_o(memory_subsystem_banks_powergate_switch_n[${bank}])
+      .switch_onoff_signal_o(memory_subsystem_banks_powergate_switch_n[${bank.name()}])
   );
 
   power_manager_sequence #(
     .IDLE_VALUE(ISO_IDLE_VALUE),
     .ONOFF_AT_RESET(ISO_VALUE_AT_RESET)
-  ) power_manager_sequence_ram_${bank}_iso_i (
+  ) power_manager_sequence_ram_${bank.name()}_iso_i (
       .clk_i,
       .rst_ni,
 
       // trigger to start the sequence
-      .start_off_sequence_i(reg2hw.ram_${bank}_iso.q),
-      .start_on_sequence_i (~reg2hw.ram_${bank}_iso.q),
-      .switch_ack_i (ram_${bank}_switch_wait_ack),
+      .start_off_sequence_i(reg2hw.ram_${bank.name()}_iso.q),
+      .start_on_sequence_i (~reg2hw.ram_${bank.name()}_iso.q),
+      .switch_ack_i (ram_${bank.name()}_switch_wait_ack),
 
       // switch on and off signal, 1 means on
-      .switch_onoff_signal_o(memory_subsystem_banks_powergate_iso_n[${bank}])
+      .switch_onoff_signal_o(memory_subsystem_banks_powergate_iso_n[${bank.name()}])
   );
 
   power_manager_sequence #(
     .IDLE_VALUE(ISO_IDLE_VALUE),
     .ONOFF_AT_RESET(ISO_VALUE_AT_RESET)
-  ) power_manager_sequence_ram_${bank}_retentive_i (
+  ) power_manager_sequence_ram_${bank.name()}_retentive_i (
       .clk_i,
       .rst_ni,
 
       // trigger to start the sequence
-      .start_off_sequence_i(reg2hw.ram_${bank}_retentive.q),
-      .start_on_sequence_i (~reg2hw.ram_${bank}_retentive.q),
+      .start_off_sequence_i(reg2hw.ram_${bank.name()}_retentive.q),
+      .start_on_sequence_i (~reg2hw.ram_${bank.name()}_retentive.q),
       .switch_ack_i (1'b1),
 
       // switch on and off signal, 1 means on
-      .switch_onoff_signal_o(memory_subsystem_banks_set_retentive_no[${bank}])
+      .switch_onoff_signal_o(memory_subsystem_pwr_ctrl_o[${bank.name()}].retentive_en_n)
   );
 
 % endfor
@@ -501,7 +491,7 @@ module power_manager #(
   ) sync_external_${ext}_ack_i (
       .clk_i,
       .rst_ni,
-      .serial_i(external_subsystem_powergate_switch_ack_ni[${ext}]),
+      .serial_i(external_subsystem_pwr_ctrl_i[${ext}].pwrgate_ack_n),
       .serial_o(external_${ext}_subsystem_powergate_switch_ack_sync)
   );
 
@@ -573,7 +563,7 @@ module power_manager #(
       .switch_ack_i (1'b1),
 
       // switch on and off signal, 1 means on
-      .switch_onoff_signal_o(external_ram_banks_set_retentive_no[${ext}])
+      .switch_onoff_signal_o(external_subsystem_pwr_ctrl_o[${ext}].retentive_en_n)
   );
 
 % endfor
@@ -587,9 +577,9 @@ module power_manager #(
   assign hw2reg.monitor_power_gate_periph.de = 1'b1;
   assign hw2reg.monitor_power_gate_periph.d = {peripheral_subsystem_rst_n, peripheral_subsystem_powergate_iso_n, peripheral_subsystem_powergate_switch_n};
 
-% for bank in range(ram_numbanks):
-  assign hw2reg.monitor_power_gate_ram_block_${bank}.de = 1'b1;
-  assign hw2reg.monitor_power_gate_ram_block_${bank}.d = {memory_subsystem_banks_powergate_iso_n[${bank}], memory_subsystem_banks_powergate_switch_n[${bank}]};
+% for bank in xheep.iter_ram_banks():
+  assign hw2reg.monitor_power_gate_ram_block_${bank.name()}.de = 1'b1;
+  assign hw2reg.monitor_power_gate_ram_block_${bank.name()}.d = {memory_subsystem_banks_powergate_iso_n[${bank.name()}], memory_subsystem_banks_powergate_switch_n[${bank.name()}]};
 
 % endfor
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/power_manager.vlt b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/power_manager.vlt
index d0b73948..c9c6f472 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/power_manager.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/power_manager.vlt
@@ -12,6 +12,6 @@ lint_off -rule LITENDIAN -file "*/power_manager.sv" -match "*"
 lint_off -rule UNDRIVEN -file "*/power_manager.sv" -match "Signal is not driven: 'external_subsystem_powergate_switch*"
 lint_off -rule UNDRIVEN -file "*/power_manager.sv" -match "Signal is not driven: 'external_subsystem_powergate_iso*"
 lint_off -rule UNDRIVEN -file "*/power_manager.sv" -match "Signal is not driven: 'external_subsystem_rst_n*"
-lint_off -rule UNUSED -file "*/power_manager.sv" -match "Signal is not used: 'external_subsystem_powergate_switch_ack*"
+lint_off -rule UNUSED -file "*/power_manager.sv" -match "Signal is not used: 'external_subsystem_pwr_ctrl_i*"
 lint_off -rule WIDTH -file "*/power_manager.sv" -match "Operator ASSIGNW expects 16 bits on*"
 lint_off -rule DECLFILENAME -file "*/power_manager_reg_top.sv" -match "Filename 'power_manager_reg_top' does not match MODULE name: 'power_manager_reg_top_intf'"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_inout.sv b/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_inout.sv
index 5dcc5449..3529b257 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_inout.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_inout.sv
@@ -5,6 +5,7 @@
 /* verilator lint_off UNUSED */
 module pad_cell_inout #(
     parameter PADATTR = 16,
+    parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP,
     //do not touch these parameters
     parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR
 ) (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_input.sv b/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_input.sv
index cfd9c426..5a7b053a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_input.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_input.sv
@@ -5,6 +5,7 @@
 /* verilator lint_off UNUSED */
 module pad_cell_input #(
     parameter PADATTR = 16,
+    parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP,
     //do not touch these parameters
     parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR
 ) (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_output.sv b/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_output.sv
index cc4960ea..794e177d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_output.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/simulation/pad_cell_output.sv
@@ -5,6 +5,7 @@
 /* verilator lint_off UNUSED */
 module pad_cell_output #(
     parameter PADATTR = 16,
+    parameter core_v_mini_mcu_pkg::pad_side_e SIDE = core_v_mini_mcu_pkg::TOP,
     //do not touch these parameters
     parameter PADATTR_RND = PADATTR == 0 ? 1 : PADATTR
 ) (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/simulation/simulation.vlt b/hw/vendor/esl_epfl_x_heep/hw/simulation/simulation.vlt
index 79d2edf4..0b30dd69 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/simulation/simulation.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/simulation/simulation.vlt
@@ -5,3 +5,5 @@
 `verilator_config
 
 lint_off -rule UNOPTFLAT -file "*/hw/simulation/pad_cell_*.sv" -match "Signal unoptimizable*"
+lint_off -rule UNUSED -file "*/hw/simulation/sram_wrapper.sv" -match "Signal is not used: 'pwrgate_ni*"
+lint_off -rule UNDRIVEN -file "*/hw/simulation/sram_wrapper.sv" -match "Signal is not driven: 'pwrgate_ack_no*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/simulation/sram_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/simulation/sram_wrapper.sv
index 7be64dcf..0986b3e2 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/simulation/sram_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/simulation/sram_wrapper.sv
@@ -22,6 +22,9 @@ module sram_wrapper #(
     input logic [AddrWidth-1:0] addr_i,
     input logic [31:0] wdata_i,
     input logic [3:0] be_i,
+    // power manager signals that goes to the ASIC macros
+    input logic pwrgate_ni,
+    output logic pwrgate_ack_no,
     input logic set_retentive_ni,
     // output ports
     output logic [31:0] rdata_o
diff --git a/hw/vendor/esl_epfl_x_heep/hw/system/pad_control/data/pad_control.hjson.tpl b/hw/vendor/esl_epfl_x_heep/hw/system/pad_control/data/pad_control.hjson.tpl
index 605843dc..466fd7d4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/system/pad_control/data/pad_control.hjson.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/system/pad_control/data/pad_control.hjson.tpl
@@ -26,7 +26,7 @@
 % for pad in total_pad_list:
     { name:     "PAD_ATTRIBUTE_${pad.name.upper()}",
       desc:     "${pad.name} Attributes (Pull Up En, Pull Down En, etc. It is technology specific.",
-      resval:   "0x00"
+      resval:   "${pads_attributes['resval']}"
       swaccess: "rw",
       hwaccess: "hro",
       fields: [
diff --git a/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
index c88bdaca..e77bd1b4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
@@ -48,8 +48,9 @@ module x_heep_system
 
     output logic [31:0] exit_value_o,
 
-    input logic ext_dma_slot_tx_i,
-    input logic ext_dma_slot_rx_i,
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i,
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
 
     // eXtension interface
     if_xif.cpu_compressed xif_compressed_if,
@@ -66,13 +67,22 @@ ${pad.x_heep_system_interface}
 
   import core_v_mini_mcu_pkg::*;
 
+
+  localparam EXT_HARTS = 0;
+
+  //do not touch these parameter
+  localparam EXT_HARTS_RND = EXT_HARTS == 0 ? 1 : EXT_HARTS;
+
+
+  logic [EXT_HARTS_RND-1:0] ext_debug_req;
+  logic ext_cpu_subsystem_rst_n;
+  logic ext_debug_reset_n;
+
   // PM signals
   logic cpu_subsystem_powergate_switch_n;
   logic cpu_subsystem_powergate_switch_ack_n;
   logic peripheral_subsystem_powergate_switch_n;
   logic peripheral_subsystem_powergate_switch_ack_n;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_n;
-  logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack_n;
 
   // PAD controller
   reg_req_t pad_req;
@@ -91,12 +101,18 @@ ${pad.x_heep_system_interface}
 ${pad.internal_signals}
 % endfor
 
+`ifdef FPGA_SYNTHESIS
+  assign cpu_subsystem_powergate_switch_ack_n = cpu_subsystem_powergate_switch_n;
+  assign peripheral_subsystem_powergate_switch_ack_n = peripheral_subsystem_powergate_switch_n;
+`endif
+
   core_v_mini_mcu #(
     .COREV_PULP(COREV_PULP),
     .FPU(FPU),
     .ZFINX(ZFINX),
     .EXT_XBAR_NMASTER(EXT_XBAR_NMASTER),
-    .X_EXT(X_EXT)
+    .X_EXT(X_EXT),
+    .EXT_HARTS(EXT_HARTS)
   ) core_v_mini_mcu_i (
 
     .rst_ni(rst_ngen),
@@ -126,18 +142,20 @@ ${pad.core_v_mini_mcu_bonding}
     .ext_dma_write_ch0_resp_i,
     .ext_dma_addr_ch0_req_o,
     .ext_dma_addr_ch0_resp_i,
+    .ext_dma_stop_i,
     .ext_peripheral_slave_req_o,
     .ext_peripheral_slave_resp_i,
+    .ext_debug_req_o(ext_debug_req),
+    .ext_debug_reset_no(ext_debug_reset_n),
     .cpu_subsystem_powergate_switch_no(cpu_subsystem_powergate_switch_n),
     .cpu_subsystem_powergate_switch_ack_ni(cpu_subsystem_powergate_switch_ack_n),
     .peripheral_subsystem_powergate_switch_no(peripheral_subsystem_powergate_switch_n),
     .peripheral_subsystem_powergate_switch_ack_ni(peripheral_subsystem_powergate_switch_ack_n),
-    .memory_subsystem_banks_powergate_switch_no(memory_subsystem_banks_powergate_switch_n),
-    .memory_subsystem_banks_powergate_switch_ack_ni(memory_subsystem_banks_powergate_switch_ack_n),
     .external_subsystem_powergate_switch_no,
     .external_subsystem_powergate_switch_ack_ni,
     .external_subsystem_powergate_iso_no,
     .external_subsystem_rst_no,
+    .ext_cpu_subsystem_rst_no(ext_cpu_subsystem_rst_n),
     .external_ram_banks_set_retentive_no,
     .external_subsystem_clkgate_en_no,
     .exit_value_o,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
index 7248758f..2871b8ed 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/cv32e40px.git
-    rev: 49770e7dd5d569f440810866f4f33ce6a4f7ef1f
+    rev: 15b9dd6077513342cf44e6853a5fc33098f2e73b
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
index 547959fe..d0e289ae 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/cv32e40px.git",
-    rev: "49770e7dd5d569f440810866f4f33ce6a4f7ef1f",
+    rev: "15b9dd6077513342cf44e6853a5fc33098f2e73b",
   },
 
   exclude_from_upstream: [
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/.gitignore b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/.gitignore
index ef351b19..6c2cd791 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/.gitignore
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/.gitignore
@@ -18,3 +18,11 @@ TAGS
 /build
 /Bender.lock
 /Bender.local
+golden_reference_design
+ref_design
+golden.src
+revised.src
+cadence_conformal
+synopsys_formality
+questa_autocheck
+reports
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh
index a89ed4e4..355bc738 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_instr_trace.svh
@@ -1,23 +1,37 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
+// This file, and derivatives thereof are licensed under the
+// Solderpad License, Version 2.0 (the "License").
 //
-// https://solderpad.org/licenses/
+// Use of this file means you agree to the terms and conditions
+// of the license and are in full compliance with the License.
+//
+// You may obtain a copy of the License at:
+//
+//     https://solderpad.org/licenses/SHL-2.0/
 //
 // Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// and hardware implementations thereof distributed under the License
+// is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
+// OF ANY KIND, EITHER EXPRESSED OR IMPLIED.
+//
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// Tracer data structures and functions
-//
-// Contributors: Steve Richmond, Silicon Labs <steve.richmond@silabs.com>
-//               Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////
+// Engineer:       Steve Richmond - steve.richmond@silabs.com                 //
+//                                                                            //
+// Design Name:    cv32e40p_tracer data structures                            //
+// Project Name:   CV32E40P                                                   //
+// Language:       SystemVerilog                                              //
+//                                                                            //
+// Description:    Moves the class definition for instr_trace_t out of the    //
+//                 tracer module for readability and code partitioning        //
+//                                                                            //
+//                 Includes various enhancements to make the instr_trace_t    //
+//                 class more comprehensive                                   //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
 
 typedef struct {
   logic [5:0] addr;
@@ -35,9 +49,13 @@ typedef struct {
 
 class instr_trace_t;
   time         simtime;
+  time         stoptime;
+  bit          external_time;
   int          cycles;
+  int          stopcycles;
   logic [31:0] pc;
   logic [31:0] instr;
+  string       ctx; //Used to add context in the trace log file (Canceled, debug, interrput,....)
   bit          compressed;
   bit          wb_bypass;
   bit          misaligned;
@@ -56,10 +74,15 @@ class instr_trace_t;
     regs_read  = {};
     regs_write = {};
     mem_access = {};
+    external_time = 0;
+    stoptime = 0;
+    stopcycles = 0;
   endfunction
 
   function void init(int unsigned cycles, bit [31:0] pc, bit compressed, bit [31:0] instr);
-    this.simtime        = $time;
+    if(!this.external_time) begin
+      this.simtime        = $time;
+    end
     this.cycles         = cycles;
     this.pc             = pc;
     this.compressed     = compressed;
@@ -308,7 +331,23 @@ class instr_trace_t;
     begin
       string insn_str;  // Accumulate writes into a single string to enable single $fwrite
 
-      insn_str = $sformatf("%t %15d %h %h %-36s", simtime, cycles, pc, instr, str);
+      if(simtime < 100ns) begin
+        insn_str = $sformatf("       %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 1us) begin
+        insn_str = $sformatf("      %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 10us) begin
+        insn_str = $sformatf("     %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 100us) begin
+        insn_str = $sformatf("    %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 1ms) begin
+        insn_str = $sformatf("   %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 10ms) begin
+        insn_str = $sformatf("  %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 100ms) begin
+        insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else begin
+        insn_str = $sformatf("%t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end
 
       foreach (regs_write[i]) begin
         if (regs_write[i].addr != 0)
@@ -330,6 +369,12 @@ class instr_trace_t;
         insn_str = $sformatf("%s  PA:%08x", insn_str, mem_acc.addr);
       end
 
+      casex (instr)
+      INSTR_FDIV: insn_str = $sformatf("%s %15d %t", insn_str, stopcycles, stoptime);
+      INSTR_FSQRT:insn_str = $sformatf("%s %15d %t", insn_str, stopcycles, stoptime);
+      default: ;
+      endcase
+
       $fwrite(f, "%s\n", insn_str);
     end
   endfunction
@@ -489,7 +534,7 @@ class instr_trace_t;
     begin
       mnemonic = {compressed ? "c." : "", mnemonic};
       regs_read.push_back('{rs1, rs1_value, 0});
-      str =  $sformatf("%-16s %s, %0d", mnemonic, regAddrToStr(rs1), $signed(imm_sb_type));
+      str =  $sformatf("%-16s %s, %0d, %0d", mnemonic, regAddrToStr(rs1), $signed(imm_s2_type), $signed(imm_sb_type));
     end
   endfunction  // printSBInstr
 
@@ -587,14 +632,14 @@ class instr_trace_t;
         // immediate post-incremented load
         regs_read.push_back('{rs1, rs1_value, 0});
         regs_write.push_back('{rs1, 'x, 0});
-        str = $sformatf("cv.%-13s %s, %0d(x%0d!)", mnemonic, regAddrToStr(rd), $signed(imm_i_type), rs1);
+        str = $sformatf("cv.%-13s %s, (x%0d), %0d", mnemonic, regAddrToStr(rd), rs1, $signed(imm_i_type));
       end else if (instr[6:0] == OPCODE_CUSTOM_1) begin
         if (instr[27] == 1'b0) begin
           // reg-reg post-incremented load
           regs_read.push_back('{rs2, rs2_value, 0});
           regs_read.push_back('{rs1, rs1_value, 0});
           regs_write.push_back('{rs1, 'x, 0});
-          str = $sformatf("cv.%-13s %s, %s(x%0d!)", mnemonic, regAddrToStr(rd), regAddrToStr(rs2), rs1);
+          str = $sformatf("cv.%-13s %s, (x%0d), %s", mnemonic, regAddrToStr(rd), rs1, regAddrToStr(rs2));
         end else begin
           // reg-reg indexed load
           regs_read.push_back('{rs2, rs2_value, 0});
@@ -637,7 +682,7 @@ class instr_trace_t;
         regs_read.push_back('{rs2, rs2_value, 0});
         regs_read.push_back('{rs1, rs1_value, 0});
         regs_write.push_back('{rs1, 'x, 0});
-        str = $sformatf("cv.%-14s %s, %0d(x%0d!)", mnemonic, regAddrToStr(rs2), $signed(imm_s_type), rs1);
+        str = $sformatf("cv.%-14s %s, (x%0d), %0d", mnemonic, regAddrToStr(rs2), rs1, $signed(imm_s_type));
       end else if (instr[31:28] == 4'b0010) begin
         if (instr[27] == 1'b0) begin
           // reg-reg post-incremented store
@@ -645,7 +690,7 @@ class instr_trace_t;
           regs_read.push_back('{rs3, rs3_value, 0});
           regs_read.push_back('{rs1, rs1_value, 0});
           regs_write.push_back('{rs1, 'x, 0});
-          str = $sformatf("cv.%-13s %s, %s(x%0d!)", mnemonic, regAddrToStr(rs2), regAddrToStr(rs3), rs1);
+          str = $sformatf("cv.%-13s %s, (x%0d), %s", mnemonic, regAddrToStr(rs2), rs1, regAddrToStr(rs3));
         end else begin
           // reg-reg indexed store
           regs_read.push_back('{rs2, rs2_value, 0});
@@ -757,238 +802,429 @@ class instr_trace_t;
       else str_hb = ".h";
 
       // set mnemonic
-      case (instr[31:26])
-        6'b000000: begin
+      case (instr)
+        INSTR_CVADDH   ,
+        INSTR_CVADDSCH ,
+        INSTR_CVADDSCIH,
+        INSTR_CVADDB   ,
+        INSTR_CVADDSCB ,
+        INSTR_CVADDSCIB : begin
           mnemonic = "cv.add";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000010: begin
+        INSTR_CVSUBH   ,
+        INSTR_CVSUBSCH ,
+        INSTR_CVSUBSCIH,
+        INSTR_CVSUBB   ,
+        INSTR_CVSUBSCB ,
+        INSTR_CVSUBSCIB : begin
           mnemonic = "cv.sub";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000100: begin
+        INSTR_CVAVGH    ,
+        INSTR_CVAVGSCH  ,
+        INSTR_CVAVGSCIH ,
+        INSTR_CVAVGB    ,
+        INSTR_CVAVGSCB  ,
+        INSTR_CVAVGSCIB : begin
           mnemonic = "cv.avg";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000110: begin
+        INSTR_CVAVGUH   ,
+        INSTR_CVAVGUSCH ,
+        INSTR_CVAVGUSCIH,
+        INSTR_CVAVGUB   ,
+        INSTR_CVAVGUSCB ,
+        INSTR_CVAVGUSCIB : begin
           mnemonic = "cv.avgu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b001000: begin
+        INSTR_CVMINH   ,
+        INSTR_CVMINSCH ,
+        INSTR_CVMINSCIH,
+        INSTR_CVMINB   ,
+        INSTR_CVMINSCB ,
+        INSTR_CVMINSCIB : begin
           mnemonic = "cv.min";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001010: begin
+        INSTR_CVMINUH   ,
+        INSTR_CVMINUSCH ,
+        INSTR_CVMINUSCIH,
+        INSTR_CVMINUB   ,
+        INSTR_CVMINUSCB ,
+        INSTR_CVMINUSCIB : begin
           mnemonic = "cv.minu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b001100: begin
+        INSTR_CVMAXH    ,
+        INSTR_CVMAXSCH  ,
+        INSTR_CVMAXSCIH ,
+        INSTR_CVMAXB    ,
+        INSTR_CVMAXSCB  ,
+        INSTR_CVMAXSCIB : begin
           mnemonic = "cv.max";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001110: begin
+        INSTR_CVMAXUH    ,
+        INSTR_CVMAXUSCH  ,
+        INSTR_CVMAXUSCIH ,
+        INSTR_CVMAXUB    ,
+        INSTR_CVMAXUSCB  ,
+        INSTR_CVMAXUSCIB : begin
           mnemonic = "cv.maxu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b010000: begin
+        INSTR_CVSRLH    ,
+        INSTR_CVSRLSCH  ,
+        INSTR_CVSRLSCIH ,
+        INSTR_CVSRLB    ,
+        INSTR_CVSRLSCB  ,
+        INSTR_CVSRLSCIB : begin
           mnemonic = "cv.srl";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b010010: begin
+        INSTR_CVSRAH   ,
+        INSTR_CVSRASCH ,
+        INSTR_CVSRASCIH,
+        INSTR_CVSRAB   ,
+        INSTR_CVSRASCB ,
+        INSTR_CVSRASCIB : begin
           mnemonic = "cv.sra";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b010100: begin
+        INSTR_CVSLLH   ,
+        INSTR_CVSLLSCH ,
+        INSTR_CVSLLSCIH,
+        INSTR_CVSLLB   ,
+        INSTR_CVSLLSCB ,
+        INSTR_CVSLLSCIB : begin
           mnemonic = "cv.sll";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b010110: begin
+        INSTR_CVORH   ,
+        INSTR_CVORSCH ,
+        INSTR_CVORSCIH,
+        INSTR_CVORB   ,
+        INSTR_CVORSCB ,
+        INSTR_CVORSCIB : begin
           mnemonic = "cv.or";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b011000: begin
+        INSTR_CVXORH    ,
+        INSTR_CVXORSCH  ,
+        INSTR_CVXORSCIH ,
+        INSTR_CVXORB    ,
+        INSTR_CVXORSCB  ,
+        INSTR_CVXORSCIB : begin
           mnemonic = "cv.xor";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b011010: begin
+        INSTR_CVANDH    ,
+        INSTR_CVANDSCH  ,
+        INSTR_CVANDSCIH ,
+        INSTR_CVANDB    ,
+        INSTR_CVANDSCB  ,
+        INSTR_CVANDSCIB : begin
           mnemonic = "cv.and";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b011100: begin
+        INSTR_CVABSH,
+        INSTR_CVABSB : begin
           mnemonic = "cv.abs";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
         // dot products
-        6'b100000: begin
+        INSTR_CVDOTUPH   ,
+        INSTR_CVDOTUPSCH ,
+        INSTR_CVDOTUPSCIH,
+        INSTR_CVDOTUPB   ,
+        INSTR_CVDOTUPSCB ,
+        INSTR_CVDOTUPSCIB : begin
           mnemonic = "cv.dotup";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b100010: begin
+        INSTR_CVDOTUSPH   ,
+        INSTR_CVDOTUSPSCH ,
+        INSTR_CVDOTUSPSCIH,
+        INSTR_CVDOTUSPB   ,
+        INSTR_CVDOTUSPSCB ,
+        INSTR_CVDOTUSPSCIB : begin
           mnemonic = "cv.dotusp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b100100: begin
+        INSTR_CVDOTSPH   ,
+        INSTR_CVDOTSPSCH ,
+        INSTR_CVDOTSPSCIH,
+        INSTR_CVDOTSPB   ,
+        INSTR_CVDOTSPSCB ,
+        INSTR_CVDOTSPSCIB : begin
           mnemonic = "cv.dotsp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b100110: begin
+        INSTR_CVSDOTUPH   ,
+        INSTR_CVSDOTUPSCH ,
+        INSTR_CVSDOTUPSCIH,
+        INSTR_CVSDOTUPB   ,
+        INSTR_CVSDOTUPSCB ,
+        INSTR_CVSDOTUPSCIB : begin
           mnemonic = "cv.sdotup";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b101000: begin
+        INSTR_CVSDOTUSPH   ,
+        INSTR_CVSDOTUSPSCH ,
+        INSTR_CVSDOTUSPSCIH,
+        INSTR_CVSDOTUSPB   ,
+        INSTR_CVSDOTUSPSCB ,
+        INSTR_CVSDOTUSPSCIB : begin
           mnemonic = "cv.sdotusp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b101010: begin
+        INSTR_CVSDOTSPH   ,
+        INSTR_CVSDOTSPSCH ,
+        INSTR_CVSDOTSPSCIH,
+        INSTR_CVSDOTSPB   ,
+        INSTR_CVSDOTSPSCB ,
+        INSTR_CVSDOTSPSCIB : begin
           mnemonic = "cv.sdotsp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
 
-        6'b101110: begin
-          case (instr[14:13])
-            2'b00 : begin
-              mnemonic = "cv.extract";
-              str_imm  = $sformatf("0x%0h", imm_vs_type);
-            end
-            2'b01 : begin
-              mnemonic = "cv.extractu";
-              str_imm  = $sformatf("0x%0h", imm_vu_type);
-            end
-            2'b10 : begin
-              mnemonic = "cv.insert";
-              str_imm  = $sformatf("0x%0h", imm_vs_type);
-            end
-          endcase
-          str_sci  = "";
+        INSTR_CVEXTRACTH,
+        INSTR_CVEXTRACTB : begin
+            mnemonic = "cv.extract";
+            str_imm  = $sformatf("0x%0h", imm_vs_type);
+            str_sci  = "";
+        end
+        INSTR_CVEXTRACTUH,
+        INSTR_CVEXTRACTUB : begin
+            mnemonic = "cv.extractu";
+            str_imm  = $sformatf("0x%0h", imm_vu_type);
+            str_sci  = "";
+        end
+        INSTR_CVINSERTH,
+        INSTR_CVINSERTB : begin
+            mnemonic = "cv.insert";
+            str_imm  = $sformatf("0x%0h", imm_vs_type);
+            str_sci  = "";
         end
 
         // shuffle/pack
-        6'b110000: begin
-          if (instr[14:12] == 3'b111) begin
-            mnemonic = "cv.shuffleI0";
-            str_imm  = $sformatf("0x%8h", imm_shuffle_type);
-          end else begin
+        INSTR_CVSHUFFLEH   ,
+        INSTR_CVSHUFFLESCIH,
+        INSTR_CVSHUFFLEB   : begin
             mnemonic = "cv.shuffle";
             if (instr[14:12] == 3'b110) begin
               str_imm  = $sformatf("0x%8h", imm_shuffle_type);
             end
-          end
         end
-        6'b110010: begin
+
+        INSTR_CVSHUFFLEL0SCIB : begin
+            mnemonic = "cv.shuffleI0";
+            str_imm  = $sformatf("0x%8h", imm_shuffle_type);
+        end
+        INSTR_CVSHUFFLEL1SCIB : begin
           mnemonic = "cv.shuffleI1";
           str_imm  = $sformatf("0x%8h", imm_shuffle_type);
         end
-        6'b110100: begin
+        INSTR_CVSHUFFLEL2SCIB : begin
           mnemonic = "cv.shuffleI2";
           str_imm  = $sformatf("0x%8h", imm_shuffle_type);
         end
-        6'b110110: begin
+        INSTR_CVSHUFFLEL3SCIB : begin
           mnemonic = "cv.shuffleI3";
           str_imm  = $sformatf("0x%8h", imm_shuffle_type);
         end
-        6'b111000: begin
+        INSTR_CVSHUFFLE2H,
+        INSTR_CVSHUFFLE2B : begin
           mnemonic = "cv.shuffle2";
         end
-        6'b111100: begin
+        INSTR_CVPACK,
+        INSTR_CVPACKH : begin
           mnemonic = "cv.pack";
           if (instr[25] == 1'b0) begin
             str_hb = "";
           end
         end
-        6'b111110: begin
-          mnemonic = instr[25] ? "cv.packhi" : "cv.packlo";
-        end
+        INSTR_CVPACKHIB : mnemonic = "cv.packhi";
+        INSTR_CVPACKLOB : mnemonic = "cv.packlo";
 
         // comparisons
-        6'b000001: begin
+        INSTR_CVCMPEQH   ,
+        INSTR_CVCMPEQSCH ,
+        INSTR_CVCMPEQSCIH,
+        INSTR_CVCMPEQB   ,
+        INSTR_CVCMPEQSCB ,
+        INSTR_CVCMPEQSCIB : begin
           mnemonic = "cv.cmpeq";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000011: begin
+        INSTR_CVCMPNEH   ,
+        INSTR_CVCMPNESCH ,
+        INSTR_CVCMPNESCIH,
+        INSTR_CVCMPNEB   ,
+        INSTR_CVCMPNESCB ,
+        INSTR_CVCMPNESCIB : begin
           mnemonic = "cv.cmpne";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000101: begin
+        INSTR_CVCMPGTH   ,
+        INSTR_CVCMPGTSCH ,
+        INSTR_CVCMPGTSCIH,
+        INSTR_CVCMPGTB   ,
+        INSTR_CVCMPGTSCB ,
+        INSTR_CVCMPGTSCIB : begin
           mnemonic = "cv.cmpgt";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000111: begin
+        INSTR_CVCMPGEH   ,
+        INSTR_CVCMPGESCH ,
+        INSTR_CVCMPGESCIH,
+        INSTR_CVCMPGEB   ,
+        INSTR_CVCMPGESCB ,
+        INSTR_CVCMPGESCIB : begin
           mnemonic = "cv.cmpge";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001001: begin
+        INSTR_CVCMPLTH   ,
+        INSTR_CVCMPLTSCH ,
+        INSTR_CVCMPLTSCIH,
+        INSTR_CVCMPLTB   ,
+        INSTR_CVCMPLTSCB ,
+        INSTR_CVCMPLTSCIB : begin
           mnemonic = "cv.cmplt";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001011: begin
+        INSTR_CVCMPLEH   ,
+        INSTR_CVCMPLESCH ,
+        INSTR_CVCMPLESCIH,
+        INSTR_CVCMPLEB   ,
+        INSTR_CVCMPLESCB ,
+        INSTR_CVCMPLESCIB : begin
           mnemonic = "cv.cmple";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001101: begin
+        INSTR_CVCMPGTUH   ,
+        INSTR_CVCMPGTUSCH ,
+        INSTR_CVCMPGTUSCIH,
+        INSTR_CVCMPGTUB   ,
+        INSTR_CVCMPGTUSCB ,
+        INSTR_CVCMPGTUSCIB : begin
           mnemonic = "cv.cmpgtu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b001111: begin
+        INSTR_CVCMPGEUH   ,
+        INSTR_CVCMPGEUSCH ,
+        INSTR_CVCMPGEUSCIH,
+        INSTR_CVCMPGEUB   ,
+        INSTR_CVCMPGEUSCB ,
+        INSTR_CVCMPGEUSCIB : begin
           mnemonic = "cv.cmpgeu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b010001: begin
+        INSTR_CVCMPLTUH   ,
+        INSTR_CVCMPLTUSCH ,
+        INSTR_CVCMPLTUSCIH,
+        INSTR_CVCMPLTUB   ,
+        INSTR_CVCMPLTUSCB ,
+        INSTR_CVCMPLTUSCIB : begin
           mnemonic = "cv.cmpltu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b010011: begin
+        INSTR_CVCMPLEUH   ,
+        INSTR_CVCMPLEUSCH ,
+        INSTR_CVCMPLEUSCIH,
+        INSTR_CVCMPLEUB   ,
+        INSTR_CVCMPLEUSCB ,
+        INSTR_CVCMPLEUSCIB : begin
           mnemonic = "cv.cmpleu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
 
-        6'b010101: begin
-          unique case (instr[14:13])
-            2'b00: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r"      : "cv.cplxmul.i";
-            2'b01: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div2" : "cv.cplxmul.i.div2";
-            2'b10: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div4" : "cv.cplxmul.i.div4";
-            2'b11: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div8" : "cv.cplxmul.i.div8";
-          endcase
+        INSTR_CVCPLXMULR,
+        INSTR_CVCPLXMULI : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r"      : "cv.cplxmul.i";
           str_sci = "";
           str_hb = "";
         end
-
-        6'b010111: begin
-          mnemonic = "cv.cplxconj";
-          str_sci  = "";
+        INSTR_CVCPLXMULRDIV2,
+        INSTR_CVCPLXMULIDIV2 : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div2" : "cv.cplxmul.i.div2";
+          str_sci = "";
           str_hb = "";
         end
-
-        6'b011001: begin
-          unique case (instr[14:13])
-            2'b00: mnemonic = "cv.subrotmj";
-            2'b01: mnemonic = "cv.subrotmj.div2";
-            2'b10: mnemonic = "cv.subrotmj.div4";
-            2'b11: mnemonic = "cv.subrotmj.div8";
-          endcase
+        INSTR_CVCPLXMULRDIV4,
+        INSTR_CVCPLXMULIDIV4 : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div4" : "cv.cplxmul.i.div4";
           str_sci = "";
           str_hb = "";
         end
-
-        6'b011011: begin
-          unique case (instr[14:13])
-            2'b01: mnemonic = "cv.add.div2";
-            2'b10: mnemonic = "cv.add.div4";
-            2'b11: mnemonic = "cv.add.div8";
-          endcase
+        INSTR_CVCPLXMULRDIV8,
+        INSTR_CVCPLXMULIDIV8 : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div8" : "cv.cplxmul.i.div8";
           str_sci = "";
           str_hb = "";
         end
 
-        6'b011101: begin
-          unique case (instr[14:13])
-            2'b01: mnemonic = "cv.sub.div2";
-            2'b10: mnemonic = "cv.sub.div4";
-            2'b11: mnemonic = "cv.sub.div8";
-          endcase
-          str_sci = "";
+        INSTR_CVCPLXCONJ : begin
+          mnemonic = "cv.cplxconj";
+          str_sci  = "";
           str_hb = "";
         end
 
+        INSTR_CVSUBROTMJ     : begin
+            mnemonic = "cv.subrotmj";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBROTMJDIV2 : begin
+            mnemonic = "cv.subrotmj.div2";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBROTMJDIV4 : begin
+            mnemonic = "cv.subrotmj.div4";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBROTMJDIV8 : begin
+            mnemonic = "cv.subrotmj.div8";
+            str_sci = "";
+            str_hb = "";
+        end
+
+        INSTR_CVADDIV2 : begin
+            mnemonic = "cv.add.div2";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVADDIV4 : begin
+            mnemonic = "cv.add.div4";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVADDIV8 : begin
+            mnemonic = "cv.add.div8";
+            str_sci = "";
+            str_hb = "";
+        end
+
+        INSTR_CVSUBIV2 : begin
+            mnemonic = "cv.sub.div2";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBIV4 : begin
+            mnemonic = "cv.sub.div4";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBIV8 : begin
+            mnemonic = "cv.sub.div8";
+            str_sci = "";
+            str_hb = "";
+        end
+
         default: begin
           printMnemonic("INVALID");
           return;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv
index 4effb2b8..3675a950 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi.sv
@@ -1,24 +1,28 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// CV32E40P RVFI interface
-//
-// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>          //
+//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>     //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  CV32E40P RVFI interface                                          //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
 `include "cv32e40px_rvfi_pkg.sv"
 
@@ -27,7 +31,8 @@ module cv32e40px_rvfi
   import cv32e40px_rvfi_pkg::*;
 #(
     parameter FPU   = 0,
-    parameter ZFINX = 0
+    parameter ZFINX = 0,
+    parameter NUM_MHPMCOUNTERS = 1
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -290,7 +295,7 @@ module cv32e40px_rvfi
     // performance counters
     //  cycle,  instret,  hpcounter,  cycleh,  instreth,  hpcounterh
     // mcycle, minstret, mhpcounter, mcycleh, minstreth, mhpcounterh
-    input logic [31:0][MHPMCOUNTER_WIDTH-1:0] csr_mhpmcounter_q_i,
+    input logic [63:0][MHPMCOUNTER_WIDTH-1:0] csr_mhpmcounter_q_i,
     input logic [31:0]                        csr_mhpmcounter_write_lower_i,
     input logic [31:0]                        csr_mhpmcounter_write_upper_i,
 
@@ -327,6 +332,10 @@ module cv32e40px_rvfi
     // the convention of RISC-V Formal Interface Specification.
     output logic       [ 0:0] rvfi_valid,
     output logic       [63:0] rvfi_order,
+    output integer            rvfi_start_cycle,
+    output time               rvfi_start_time,
+    output integer            rvfi_stop_cycle,
+    output time               rvfi_stop_time,
     output logic       [31:0] rvfi_insn,
     output rvfi_trap_t        rvfi_trap,
     output logic       [ 0:0] rvfi_halt,
@@ -346,6 +355,7 @@ module cv32e40px_rvfi
     output logic        rvfi_frd_wvalid [1:0],
     output logic [ 4:0] rvfi_frd_addr   [1:0],
     output logic [31:0] rvfi_frd_wdata  [1:0],
+    output logic        rvfi_2_rd,
     output logic [ 4:0] rvfi_rs1_addr,
     output logic [ 4:0] rvfi_rs2_addr,
     output logic [ 4:0] rvfi_rs3_addr,
@@ -366,8 +376,8 @@ module cv32e40px_rvfi
     output logic [31:0] rvfi_pc_wdata,
 
     output logic [31:0] rvfi_mem_addr,
-    output logic [ 3:0] rvfi_mem_rmask,
-    output logic [ 3:0] rvfi_mem_wmask,
+    output logic [31:0] rvfi_mem_rmask,
+    output logic [31:0] rvfi_mem_wmask,
     output logic [31:0] rvfi_mem_rdata,
     output logic [31:0] rvfi_mem_wdata,
 
@@ -618,6 +628,13 @@ module cv32e40px_rvfi
   bit clk_i_d;
   assign #0.01 clk_i_d = clk_i;
 
+  integer cycles;
+  // cycle counter
+  always_ff @(posedge clk_i_d, negedge rst_ni) begin
+    if (rst_ni == 1'b0) cycles <= 0;
+    else cycles <= cycles + 1;
+  end
+
   logic pc_mux_debug;
   logic pc_mux_dret;
   logic pc_mux_exception;
@@ -626,6 +643,9 @@ module cv32e40px_rvfi
   logic pc_mux_nmi;
 
   localparam logic [31:0] MSTATUS_WRITE_MASK = 32'h0000_6088;
+  localparam logic [31:0] MCOUNTINHIBIT_WRITE_MASK = {{(29-NUM_MHPMCOUNTERS){1'b0}}, {(NUM_MHPMCOUNTERS){1'b1}}, 3'b101};
+  localparam NUM_HPM_EVENTS = 16;
+  localparam logic [31:0] MHPMEVENT_WRITE_MASK = {{(31-NUM_HPM_EVENTS){1'b0}}, {(NUM_HPM_EVENTS){1'b1}}};
 
   `include "pipe_freeze_trace.sv"
 
@@ -747,6 +767,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     end
 
     rvfi_order       = new_rvfi_trace.m_order;
+    rvfi_start_cycle = new_rvfi_trace.m_start_cycle;
+    rvfi_start_time  = new_rvfi_trace.m_start_time;
+    rvfi_stop_cycle = new_rvfi_trace.m_stop_cycle;
+    rvfi_stop_time  = new_rvfi_trace.m_stop_time;
     rvfi_pc_rdata    = new_rvfi_trace.m_pc_rdata;
     rvfi_insn        = new_rvfi_trace.m_insn;
 
@@ -801,6 +825,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     rvfi_frd_addr[1]   = '0;
     rvfi_frd_wdata[1]  = '0;
 
+    rvfi_2_rd = new_rvfi_trace.m_2_rd_insn;
     if (new_rvfi_trace.m_rd_addr[0][5] == 1'b0) begin
       rvfi_rd_addr[0]  = new_rvfi_trace.m_rd_addr[0][4:0];
       rvfi_rd_wdata[0] = new_rvfi_trace.m_rd_wdata[0];
@@ -905,15 +930,50 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     `SET_RVFI_CSR_FROM_INSN(misa)
     `SET_RVFI_CSR_FROM_INSN(mie)
     `SET_RVFI_CSR_FROM_INSN(mtvec)
-    `SET_RVFI_CSR_FROM_INSN(mcountinhibit)
+
+    rvfi_csr_mcountinhibit_rdata = new_rvfi_trace.m_csr.mcountinhibit_rdata;
+    rvfi_csr_mcountinhibit_rmask = new_rvfi_trace.m_csr.mcountinhibit_rmask;
+    rvfi_csr_mcountinhibit_wdata = new_rvfi_trace.m_csr.mcountinhibit_wdata;
+    rvfi_csr_mcountinhibit_wmask = new_rvfi_trace.m_csr.mcountinhibit_wmask & MCOUNTINHIBIT_WRITE_MASK;
+
     `SET_RVFI_CSR_FROM_INSN(mscratch)
     `SET_RVFI_CSR_FROM_INSN(mepc)
     `SET_RVFI_CSR_FROM_INSN(mcause)
+    `SET_RVFI_CSR_FROM_INSN(mcycle)
     `SET_RVFI_CSR_FROM_INSN(minstret)
+    `SET_RVFI_CSR_FROM_INSN(minstreth)
+
+    // `SET_RVFI_CSR_FROM_INSN(cycle)
+    // `SET_RVFI_CSR_FROM_INSN(instret)
+    rvfi_csr_instret_rdata = new_rvfi_trace.m_csr.minstret_rdata;
+    rvfi_csr_instret_rmask = new_rvfi_trace.m_csr.minstret_rmask;
+    rvfi_csr_instret_wdata = new_rvfi_trace.m_csr.minstret_wdata;
+    rvfi_csr_instret_wmask = new_rvfi_trace.m_csr.minstret_wmask;
+
+    for(int idx=3; idx<32; idx++) begin
+    rvfi_csr_mhpmcounter_rmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_rmask[idx][31:0];
+    rvfi_csr_mhpmcounter_wmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_wmask[idx][31:0];
+    rvfi_csr_mhpmcounter_rdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_rdata[idx][31:0];
+    rvfi_csr_mhpmcounter_wdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_wdata[idx][31:0];
+
+    rvfi_csr_mhpmcounterh_rmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_rmask[idx][63:32];
+    rvfi_csr_mhpmcounterh_wmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_wmask[idx][63:32];
+    rvfi_csr_mhpmcounterh_rdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_rdata[idx][63:32];
+    rvfi_csr_mhpmcounterh_wdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_wdata[idx][63:32];
+
+    rvfi_csr_mhpmevent_rmask[idx] = new_rvfi_trace.m_csr.mhpmevent_rmask[idx];
+    rvfi_csr_mhpmevent_wmask[idx] = new_rvfi_trace.m_csr.mhpmevent_wmask[idx] & MHPMEVENT_WRITE_MASK;
+    rvfi_csr_mhpmevent_rdata[idx] = new_rvfi_trace.m_csr.mhpmevent_rdata[idx];
+    rvfi_csr_mhpmevent_wdata[idx] = new_rvfi_trace.m_csr.mhpmevent_wdata[idx];
+    end
+    // `SET_RVFI_CSR_FROM_INSN(instreth)
+    rvfi_csr_instreth_rdata = new_rvfi_trace.m_csr.minstreth_rdata;
+    rvfi_csr_instreth_rmask = new_rvfi_trace.m_csr.minstreth_rmask;
+    rvfi_csr_instreth_wdata = new_rvfi_trace.m_csr.minstreth_wdata;
+    rvfi_csr_instreth_wmask = new_rvfi_trace.m_csr.minstreth_wmask;
+
     `SET_RVFI_CSR_FROM_INSN(mip)
-    // if(rvfi_order == 64'h00000000_00000167) begin
-    //     rvfi_csr_mip_rdata = 32'h0010_0000;
-    // end
+
     rvfi_csr_tdata_rdata[0] = 'Z;
     rvfi_csr_tdata_rmask[0] = '0;  // Does not exist
     rvfi_csr_tdata_wdata[0] = 'Z;  // Does not exist
@@ -959,36 +1019,134 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
   endfunction  // set_rvfi
 
-  function void minstret_to_id();
-    trace_id.m_csr.minstret_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2];
-    trace_id.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2];
-    trace_id.m_csr.minstret_rmask = '1;
-    trace_id.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q;
-    trace_id.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0;
+  function void sample_perf_counter_to_id(int idx);
+    trace_id.m_csr.mhpmcounter_rdata[idx][31:0] = r_pipe_freeze_trace.csr.mhpmcounter_q[idx][31:0];
+    trace_id.m_csr.mhpmcounter_rmask[idx][31:0] = '1;
   endfunction
 
-  function void minstret_to_ex();
-    trace_ex.m_csr.minstret_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2];
-    trace_ex.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2];
-    trace_ex.m_csr.minstret_rmask = '1;
-    trace_ex.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q;
-    trace_ex.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0;
+  function void perf_counter_to_id(int idx);
+    if(!trace_id.m_csr.mhpmcounter_we[idx][0]) begin
+      trace_id.m_csr.mhpmcounter_wdata[idx][31:0] = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin
+        trace_id.m_csr.mhpmcounter_we[idx][0]    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx];
+        trace_id.m_csr.mhpmcounter_wdata[idx][31:0] = r_pipe_freeze_trace.csr.wdata_int;
+        trace_id.m_csr.mhpmcounter_wmask[idx][31:0] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx] ? '1 : '0;
+    end
+    sample_perf_counter_to_id(idx);
   endfunction
 
-  function void tinfo_to_id();
-    trace_id.m_csr.tinfo_we    = '0; // READ ONLY csr_tinfo_we_i;
-    trace_id.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q;
-    trace_id.m_csr.tinfo_rmask = '1;
-    trace_id.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n;
-    trace_id.m_csr.tinfo_wmask = '0;
+  function void sample_perf_event_to_trace(int idx, insn_trace_t m_trace);
+    m_trace.m_csr.mhpmevent_rdata[idx] = r_pipe_freeze_trace.csr.mhpmevent_q[idx];
+    m_trace.m_csr.mhpmevent_rmask[idx] = '1;
   endfunction
 
-  function void tinfo_to_ex();
-    trace_ex.m_csr.tinfo_we    = '0; // READ ONLY csr_tinfo_we_i;
-    trace_ex.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q;
-    trace_ex.m_csr.tinfo_rmask = '1;
-    trace_ex.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n;
-    trace_ex.m_csr.tinfo_wmask = '0;
+  function void perf_event_to_trace(int idx, insn_trace_t m_trace);
+    if(!m_trace.m_csr.mhpmevent_we[idx]) begin
+      m_trace.m_csr.mhpmevent_wdata[idx] = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmevent_we[idx]) begin
+        m_trace.m_csr.mhpmevent_we[idx]    = r_pipe_freeze_trace.csr.mhpmevent_we[idx];
+        m_trace.m_csr.mhpmevent_wdata[idx] = r_pipe_freeze_trace.csr.wdata_int;
+        m_trace.m_csr.mhpmevent_wmask[idx] = r_pipe_freeze_trace.csr.mhpmevent_we[idx] ? '1 : '0;
+    end
+    sample_perf_event_to_trace(idx, m_trace);
+  endfunction
+
+  function void sample_minstret_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2][31:0];
+    m_trace.m_csr.minstret_rmask = '1;
+  endfunction
+
+  function void minstret_to_trace(insn_trace_t m_trace);
+    if(!m_trace.m_csr.minstret_we) begin
+      m_trace.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]) begin
+        m_trace.m_csr.minstret_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2];
+        m_trace.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.wdata_int;
+        m_trace.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0;
+    end
+    sample_minstret_to_trace(m_trace);
+  endfunction
+
+  function void sample_perf_counter_h_to_id(int idx);
+    trace_id.m_csr.mhpmcounter_rdata[idx][63:32] = r_pipe_freeze_trace.csr.mhpmcounter_q[idx][63:0];
+    trace_id.m_csr.mhpmcounter_rmask[idx][63:32] = '1;
+  endfunction
+
+  function void perf_counter_h_to_id(int idx);
+    if(!trace_id.m_csr.mhpmcounter_we[idx][1]) begin
+      trace_id.m_csr.mhpmcounter_wdata[idx][63:32] = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin
+        trace_id.m_csr.mhpmcounter_we[idx][1]    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx];
+        trace_id.m_csr.mhpmcounter_wdata[idx][63:32] = r_pipe_freeze_trace.csr.wdata_int;
+        trace_id.m_csr.mhpmcounter_wmask[idx][63:32] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx] ? '1 : '0;
+    end
+    sample_perf_counter_h_to_id(idx);
+  endfunction
+
+  function void sample_minstreth_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.minstreth_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2][63:32];
+    m_trace.m_csr.minstreth_rmask = '1;
+  endfunction
+
+  function void sample_mcycle_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.mcycle_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[0];
+    m_trace.m_csr.mcycle_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[0][31:0];
+    m_trace.m_csr.mcycle_rmask = '1;
+    m_trace.m_csr.mcycle_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q[31:0];
+    m_trace.m_csr.mcycle_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[0] ? '1 : '0;
+  endfunction
+
+  function void minstreth_to_trace(insn_trace_t m_trace);
+    if(!m_trace.m_csr.minstreth_we) begin
+      m_trace.m_csr.minstreth_wdata = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2]) begin
+        m_trace.m_csr.minstreth_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2];
+        m_trace.m_csr.minstreth_wdata = r_pipe_freeze_trace.csr.wdata_int;
+        m_trace.m_csr.minstreth_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2] ? '1 : '0;
+    end
+    sample_minstreth_to_trace(m_trace);
+  endfunction
+
+  function void sample_perf_counter_to_trace(insn_trace_t m_trace);
+    sample_minstret_to_trace(m_trace);
+    sample_minstreth_to_trace(m_trace);
+    sample_mcycle_to_trace(m_trace);
+    for(int idx=3; idx<32; idx++)begin
+      sample_perf_event_to_trace(idx, m_trace); //TO CHANGE
+    end
+  endfunction
+
+  function void perf_counter_to_trace(insn_trace_t m_trace);
+      if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]) begin
+          minstret_to_trace(m_trace);
+      end
+      if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2]) begin
+          minstreth_to_trace(m_trace);
+      end
+      for(int idx=3; idx<32; idx++) begin
+          if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin
+              perf_counter_to_id(idx);
+          end
+          if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[idx]) begin
+              perf_counter_h_to_id(idx);
+          end
+          if(r_pipe_freeze_trace.csr.mhpmevent_we[idx]) begin
+              perf_event_to_trace(idx, m_trace);
+          end
+      end
+  endfunction
+
+  function void tinfo_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.tinfo_we    = '0; // READ ONLY csr_tinfo_we_i;
+    m_trace.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q;
+    m_trace.m_csr.tinfo_rmask = '1;
+    m_trace.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n;
+    m_trace.m_csr.tinfo_wmask = '0;
   endfunction
 
   function void mtvec_to_id();
@@ -1083,8 +1241,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     lpcount1_to_id();
     lpend1_to_id();
     lpstart1_to_id();
-
-
   endfunction
 
   bit s_was_flush;  //debug exception is flagged as trap only if preceed by a flush
@@ -1155,7 +1311,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       e_dev_commit_rf_to_ex_3,
       e_dev_commit_rf_to_ex_4,
       e_dev_commit_rf_to_ex_5;
-  event e_if_2_id_1, e_if_2_id_2, e_if_2_id_3;
+  event e_if_2_id_1, e_if_2_id_2, e_if_2_id_3, e_if_2_id_4;
   event e_ex_to_wb_1, e_ex_to_wb_2;
   event e_id_to_ex_1, e_id_to_ex_2;
   event e_commit_dpc;
@@ -1257,6 +1413,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           end
         end
         csr_to_apu_resp();
+
+        trace_apu_resp.m_stop_cycle = cycles;
+        trace_apu_resp.m_stop_time = $time;
         send_rvfi(trace_apu_resp);
         ->e_send_rvfi_trace_apu_resp;
       end
@@ -1272,35 +1431,47 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
   bit s_id_done;
   function void if_to_id();
     if (trace_id.m_valid) begin
-      minstret_to_id();
       `CSR_FROM_PIPE(id, misa)
       `CSR_FROM_PIPE(id, tdata1)
       `CSR_FROM_PIPE(id, tdata2)
-      tinfo_to_id();
+      tinfo_to_trace(trace_id);
       `CSR_FROM_PIPE(id, mip)
       send_rvfi(trace_id);
     end
     trace_id.init(trace_if);
     trace_id.m_trap       = ~r_pipe_freeze_trace.minstret;
-    trace_id.m_is_illegal = r_pipe_freeze_trace.is_illegal;
+    trace_id.m_is_illegal = trace_id.m_is_illegal | r_pipe_freeze_trace.is_illegal;
+    `CSR_FROM_PIPE(id, dpc)
     s_is_pc_set           = 1'b0;
     s_is_irq_start        = 1'b0;
     trace_if.m_valid      = 1'b0;
     s_id_done             = 1'b0;
-    `CSR_FROM_PIPE(id, dpc)
   endfunction
 
   function logic [31:0] be_to_mask(logic [3:0] be);
     logic [31:0] mask;
-    mask[7:0]   = be[0] ? 8'hFF : 8'h00;
-    mask[15:8]  = be[0] ? 8'hFF : 8'h00;
-    mask[23:16] = be[0] ? 8'hFF : 8'h00;
-    mask[31:24] = be[0] ? 8'hFF : 8'h00;
+    mask[7:0]   = (be[0] == 1'b1) ? 8'hFF : 8'h00;
+    mask[15:8]  = (be[1] == 1'b1) ? 8'hFF : 8'h00;
+    mask[23:16] = (be[2] == 1'b1) ? 8'hFF : 8'h00;
+    mask[31:24] = (be[3] == 1'b1) ? 8'hFF : 8'h00;
 
     be_to_mask  = mask;
     return mask;
   endfunction
 
+  function void commit_rf_to_trace(insn_trace_t m_trace);
+    if (m_trace.m_got_ex_reg) begin
+        m_trace.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
+        m_trace.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
+        m_trace.m_2_rd_insn = 1'b1;
+        m_trace.m_got_first_data = 1'b1;
+    end else begin
+        m_trace.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
+        m_trace.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
+        m_trace.m_got_first_data = 1'b1;
+    end
+  endfunction
+
   task compute_pipeline();
     bit s_new_valid_insn;
     bit s_ex_valid_adjusted;
@@ -1320,6 +1491,8 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     bit s_ex_reg_we_adjusted;  //ex_reg_we
     bit s_rf_we_wb_adjusted;  //
 
+    bit s_dont_override_mstatus_fs_id;
+
     trace_if             = new();
     trace_id             = new();
     trace_ex             = new();
@@ -1352,6 +1525,8 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     s_ex_reg_we_adjusted = 1'b0;
     s_rf_we_wb_adjusted  = 1'b0;
 
+    s_dont_override_mstatus_fs_id = 1'b0;
+
     forever begin
       wait(e_pipe_monitor_ok.triggered);  // event triggered
       #1;
@@ -1368,23 +1543,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       end
 
       if (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID && r_pipe_freeze_trace.ebrk_insn_dec) begin
-        if (trace_wb.m_valid) begin
-          send_rvfi(trace_wb);
-          trace_wb.m_valid = 1'b0;
-          ->e_send_rvfi_trace_wb_1;
-        end
-        if (trace_ex.m_valid) begin
-          send_rvfi(trace_ex);
-          trace_ex.m_valid = 1'b0;
-          ->e_send_rvfi_trace_ex_1;
-        end
         if (trace_id.m_valid) begin
-
-          minstret_to_id();
           `CSR_FROM_PIPE(id, misa)
           `CSR_FROM_PIPE(id, tdata1)
           `CSR_FROM_PIPE(id, tdata2)
-          tinfo_to_id();
+          tinfo_to_trace(trace_id);
           `CSR_FROM_PIPE(id, mip)
         end
       end
@@ -1418,7 +1581,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       if (trace_ex.m_valid & s_wb_valid_adjusted) begin
         // Used flopped values in case write happened before wb_valid
-        minstret_to_ex();
+        sample_perf_counter_to_trace(trace_ex);
         trace_ex.m_csr.got_minstret = '1;
       end
 
@@ -1494,14 +1657,15 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       end
 
       if (trace_ex.m_valid) begin
-
-        if (!trace_ex.m_csr.got_minstret) begin
-          minstret_to_ex();
+        if(trace_ex.m_instret_smaple_trigger == 1) begin //time to sample instret
+          sample_perf_counter_to_trace(trace_ex);
         end
+        trace_ex.m_instret_smaple_trigger = trace_ex.m_instret_smaple_trigger + 1;
+
         `CSR_FROM_PIPE(ex, misa)
         `CSR_FROM_PIPE(ex, tdata1)
         `CSR_FROM_PIPE(ex, tdata2)
-        tinfo_to_ex();
+        tinfo_to_trace(trace_ex);
 
         if (s_rf_we_wb_adjusted) begin
           ->e_dev_commit_rf_to_ex_4;
@@ -1524,29 +1688,20 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
             trace_ex.m_valid = 1'b0;
             ->e_send_rvfi_trace_ex_2;
           end else begin
-            if (!s_ex_valid_adjusted & !trace_ex.m_csr.got_minstret) begin
-              minstret_to_ex();
-            end
 
             if (s_rf_we_wb_adjusted) begin
               ->e_dev_commit_rf_to_ex_1;
-              if (trace_ex.m_got_ex_reg) begin
-                trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
-                trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
-                trace_ex.m_2_rd_insn = 1'b1;
-                trace_ex.m_got_first_data = 1'b1;
-              end else begin
-                trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
-                trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-                trace_ex.m_got_first_data = 1'b1;
-              end
+              commit_rf_to_trace(trace_ex);
 
-              if (r_pipe_freeze_trace.csr.fregs_we) begin
+              if (r_pipe_freeze_trace.csr.fregs_we && (r_pipe_freeze_trace.rf_we_wb && r_pipe_freeze_trace.rf_addr_wb[5])) begin //Catching mstatus_fs updates caused by flw
                 `CSR_FROM_PIPE(ex, mstatus_fs)
                 trace_ex.m_csr.mstatus_fs_we = 1'b1;
                 trace_ex.m_csr.mstatus_fs_wmask = '1;
                 if(r_pipe_freeze_trace.csr.we && r_pipe_freeze_trace.csr.mstatus_fs_we) begin //In this specific case, two writes to mstatus_fs happen at the same time. We need to recreate the writes caused by fregs_we
                   trace_ex.m_csr.mstatus_fs_wdata = FS_DIRTY;
+                end else begin
+                  trace_id.m_csr.mstatus_fs_rdata = trace_ex.m_csr.mstatus_fs_wdata;
+                  s_dont_override_mstatus_fs_id = 1'b1;
                 end
                 ->e_fregs_dirty_3;
               end
@@ -1559,9 +1714,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
                 ->e_ex_to_wb_1;
                 trace_wb.move_down_pipe(trace_ex);
               end else begin
-                if (!trace_ex.m_csr.got_minstret) begin
-                  minstret_to_ex();
-                end
                 send_rvfi(trace_ex);
                 ->e_send_rvfi_trace_ex_6;
               end
@@ -1570,31 +1722,41 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           end
         end else if (s_rf_we_wb_adjusted && !s_was_flush) begin
           ->e_dev_commit_rf_to_ex_2;
-          if (trace_ex.m_got_ex_reg) begin
-            trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_ex.m_2_rd_insn = 1'b1;
-            trace_ex.m_got_first_data = 1'b1;
-          end else begin
-            trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_ex.m_got_first_data = 1'b1;
-          end
+          commit_rf_to_trace(trace_ex);
         end
       end
 
       // If mret, we need to keep the instruction in Id during flush_ex because mstatus update happens at that time
-      s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || ((r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) && !r_pipe_freeze_trace.mret_insn_dec)) && (!r_pipe_freeze_trace.apu_rvalid || r_pipe_freeze_trace.data_req_ex);
+      s_ex_valid_adjusted = (r_pipe_freeze_trace.ex_valid && r_pipe_freeze_trace.ex_ready) && (s_core_is_decoding || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_IF) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_TAKEN_ID) || (r_pipe_freeze_trace.ctrl_fsm_cs == DBG_FLUSH) || ((r_pipe_freeze_trace.ctrl_fsm_cs == FLUSH_EX) && !r_pipe_freeze_trace.mret_insn_dec));
       //EX_STAGE
+
       if (trace_id.m_valid) begin
+        if(trace_id.m_instret_smaple_trigger == 1) begin //time to sample instret
+          sample_perf_counter_to_trace(trace_id);
+          for(int idx=3; idx<32; idx++) begin
+              sample_perf_counter_to_id(idx);
+              sample_perf_counter_h_to_id(idx);
+              sample_perf_event_to_trace(idx, trace_id);
+          end
+        end
+        trace_id.m_instret_smaple_trigger = trace_id.m_instret_smaple_trigger + 1;
 
         if(trace_id.m_sample_csr_write_in_ex && !csr_is_irq && !s_is_irq_start) begin //First cycle after id_ready, csr write is asserted in this cycle
           `CSR_FROM_PIPE(id, mstatus)
-          `CSR_FROM_PIPE(id, mstatus_fs)
+          if(!s_dont_override_mstatus_fs_id) begin
+              `CSR_FROM_PIPE(id, mstatus_fs)
+          end
           `CSR_FROM_PIPE(id, mepc)
           `CSR_FROM_PIPE(id, mcause)
           `CSR_FROM_PIPE(id, dscratch0)
           `CSR_FROM_PIPE(id, dscratch1)
+          if(r_pipe_freeze_trace.csr.we && (r_pipe_freeze_trace.csr.addr == CSR_DPC)) begin
+            `CSR_FROM_PIPE(id, dpc)
+          end
+
+          `CSR_FROM_PIPE(id, mcountinhibit)
+
+          perf_counter_to_trace(trace_id);
           ->e_csr_in_ex;
         end
 
@@ -1614,10 +1776,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         `CSR_FROM_PIPE(id, frm)
         `CSR_FROM_PIPE(id, fcsr)
 
-        if (r_pipe_freeze_trace.csr.we) begin
-          `CSR_FROM_PIPE(id, dpc)
-        end
-
         if (r_pipe_freeze_trace.csr.dcsr_we) begin
           dcsr_to_id();
         end
@@ -1638,6 +1796,15 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         trace_ex.m_csr.frm_wmask    = '0;
         trace_ex.m_csr.fcsr_wmask   = '0;
 
+        if(r_pipe_freeze_trace.ctrl_fsm_cs == XRET_JUMP) begin //xret exit pipeline
+            tinfo_to_trace(trace_id);
+            `CSR_FROM_PIPE(id, tdata1)
+            `CSR_FROM_PIPE(id, tdata2)
+            send_rvfi(trace_id);
+            trace_id.m_valid = 1'b0;
+            s_dont_override_mstatus_fs_id = 1'b0;
+        end
+
         if (r_pipe_freeze_trace.apu_req && r_pipe_freeze_trace.apu_gnt) begin
           trace_id.m_is_apu = 1'b1;
           trace_id.m_apu_req_id = cnt_apu_req;
@@ -1647,6 +1814,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           trace_apu_req.set_to_apu();
           apu_trace_q.push_back(trace_apu_req);
           trace_id.m_valid = 1'b0;
+          s_dont_override_mstatus_fs_id = 1'b0;
 
           if(r_pipe_freeze_trace.apu_rvalid && (cnt_apu_req == cnt_apu_resp)) begin//APU return in the same cycle
             apu_resp();
@@ -1702,6 +1870,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           hwloop_to_id();
           trace_ex.move_down_pipe(trace_id);  // The instruction moves forward from ID to EX
           trace_id.m_valid = 1'b0;
+          s_dont_override_mstatus_fs_id = 1'b0;
           ->e_id_to_ex_1;
 
         end else if (r_pipe_freeze_trace.ex_reg_we && r_pipe_freeze_trace.rf_alu_we_ex) begin
@@ -1725,9 +1894,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       if (s_new_valid_insn) begin  // There is a new valid instruction
         if (trace_id.m_valid) begin
           if (trace_ex.m_valid) begin
-            if (!trace_ex.m_csr.got_minstret) begin
-              minstret_to_ex();
-            end
             if (trace_wb.m_valid) begin
               send_rvfi(trace_ex);
               ->e_send_rvfi_trace_ex_4;
@@ -1769,6 +1935,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           hwloop_to_id();
           trace_ex.move_down_pipe(trace_id);
           trace_id.m_valid = 1'b0;
+          s_dont_override_mstatus_fs_id = 1'b0;
           ->e_id_to_ex_2;
         end
         if_to_id();
@@ -1786,18 +1953,24 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       end
 
       //IF_STAGE
-      if (r_pipe_freeze_trace.if_valid && r_pipe_freeze_trace.if_ready) begin
+      if(trace_if.m_valid) begin
+        if(r_pipe_freeze_trace.is_illegal && r_pipe_freeze_trace.is_decoding) begin
+          trace_if.m_is_illegal = 1'b1;
+        end
+      end
+
+      if (r_pipe_freeze_trace.if_valid && r_pipe_freeze_trace.if_ready && r_pipe_freeze_trace.instr_valid_if) begin
         if (trace_if.m_valid) begin
           if (r_pipe_freeze_trace.id_valid && r_pipe_freeze_trace.id_ready && !trace_id.m_valid && r_pipe_freeze_trace.ebrk_insn_dec) begin
             if_to_id();
             trace_id.m_is_ebreak = '1;  //trace_if.m_is_ebreak;
             ->e_if_2_id_2;
-          end else if (r_pipe_freeze_trace.is_illegal) begin
+          end else if (trace_if.m_is_illegal) begin
             if_to_id();
-            trace_id.m_is_illegal = 1'b1;
             ->e_if_2_id_3;
           end else if (r_pipe_freeze_trace.ecall_insn_dec) begin
             if_to_id();
+            ->e_if_2_id_4;
           end
         end
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi_trace.sv
index bfb02579..bdbe6127 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_rvfi_trace.sv
@@ -1,26 +1,31 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// CV32E40P RVFI interface
-//
-// Contributors: Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>     //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  CV32E40P RVFI tracer                                             //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
 module cv32e40px_rvfi_trace
   import cv32e40px_pkg::*;
+  import cv32e40px_rvfi_pkg::*;
 #(
     parameter FPU   = 0,
     parameter ZFINX = 0
@@ -32,9 +37,14 @@ module cv32e40px_rvfi_trace
 
     input logic [31:0] imm_s3_type,
 
-    input logic        rvfi_valid,
-    input logic [31:0] rvfi_insn,
-    input logic [31:0] rvfi_pc_rdata,
+    input logic              rvfi_valid,
+    input logic       [31:0] rvfi_insn,
+    input integer            rvfi_start_cycle,
+    input time               rvfi_start_time,
+    input integer            rvfi_stop_cycle,
+    input time               rvfi_stop_time,
+    input logic       [31:0] rvfi_pc_rdata,
+    input rvfi_trap_t        rvfi_trap,
 
     input logic [ 4:0] rvfi_rd_addr [1:0],
     input logic [31:0] rvfi_rd_wdata[1:0],
@@ -42,6 +52,7 @@ module cv32e40px_rvfi_trace
     input logic        rvfi_frd_wvalid[1:0],
     input logic [ 4:0] rvfi_frd_addr  [1:0],
     input logic [31:0] rvfi_frd_wdata [1:0],
+    input logic        rvfi_2_rd,
 
     input logic [ 4:0] rvfi_rs1_addr,
     input logic [ 4:0] rvfi_rs2_addr,
@@ -61,8 +72,8 @@ module cv32e40px_rvfi_trace
     input logic [31:0] rvfi_frs3_rdata,
 
     input logic [31:0] rvfi_mem_addr,
-    input logic [ 3:0] rvfi_mem_rmask,
-    input logic [ 3:0] rvfi_mem_wmask,
+    input logic [31:0] rvfi_mem_rmask,
+    input logic [31:0] rvfi_mem_wmask,
     input logic [31:0] rvfi_mem_rdata,
     input logic [31:0] rvfi_mem_wdata
 );
@@ -74,7 +85,7 @@ module cv32e40px_rvfi_trace
 
   integer f;  //file pointer
   string fn;
-  integer cycles;
+  // integer cycles;
   string info_tag;
 
   logic is_compressed;
@@ -125,7 +136,13 @@ module cv32e40px_rvfi_trace
       rs3_value = rvfi_rs3_rdata;
     end
 
-    if (rvfi_frd_wvalid[0]) begin
+    if (rvfi_2_rd) begin
+      if (rvfi_frd_wvalid[1]) begin
+        rd = {1'b1, rvfi_frd_addr[1]};
+      end else begin
+        rd = {1'b0, rvfi_rd_addr[1]};
+      end
+    end else if (rvfi_frd_wvalid[0]) begin
       rd = {1'b1, rvfi_frd_addr[0]};
     end else begin
       rd = {1'b0, rvfi_rd_addr[0]};
@@ -134,57 +151,69 @@ module cv32e40px_rvfi_trace
 
   assign rs4 = rs3;
 
-  assign imm_i_type = {{20{rvfi_insn[31]}}, rvfi_insn[31:20]};
-  assign imm_iz_type = {20'b0, rvfi_insn[31:20]};
-  assign imm_s_type = {{20{rvfi_insn[31]}}, rvfi_insn[31:25], rvfi_insn[11:7]};
+  cv32e40p_compressed_decoder #(
+      .FPU(FPU)
+  ) rvfi_trace_decompress_i (
+      .instr_i(rvfi_insn),
+      .instr_o(decomp_insn),
+      .is_compressed_o(is_compressed)
+  );
+
+  assign imm_i_type = {{20{decomp_insn[31]}}, decomp_insn[31:20]};
+  assign imm_iz_type = {20'b0, decomp_insn[31:20]};
+  assign imm_s_type = {{20{decomp_insn[31]}}, decomp_insn[31:25], decomp_insn[11:7]};
   assign imm_sb_type = {
-    {19{rvfi_insn[31]}}, rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0
+    {19{decomp_insn[31]}},
+    decomp_insn[31],
+    decomp_insn[7],
+    decomp_insn[30:25],
+    decomp_insn[11:8],
+    1'b0
   };
-  assign imm_u_type = {rvfi_insn[31:12], 12'b0};
+  assign imm_u_type = {decomp_insn[31:12], 12'b0};
   assign imm_uj_type = {
-    {12{rvfi_insn[31]}}, rvfi_insn[19:12], rvfi_insn[20], rvfi_insn[30:21], 1'b0
+    {12{decomp_insn[31]}}, decomp_insn[19:12], decomp_insn[20], decomp_insn[30:21], 1'b0
   };
 
-  assign imm_z_type = '0;  //{27'b0, rvfi_insn[REG_S1_MSB:REG_S1_LSB]};
+  assign imm_z_type = '0;  //{27'b0, decomp_insn[REG_S1_MSB:REG_S1_LSB]};
 
-  assign imm_s2_type = {27'b0, rvfi_insn[24:20]};
+  assign imm_s2_type = {27'b0, decomp_insn[24:20]};
   assign imm_vs_type = '0;
   assign imm_vu_type = '0;
   assign imm_shuffle_type = '0;
   assign imm_clip_type = '0;
 
-  cv32e40px_compressed_decoder #(
-      .FPU(FPU)
-  ) rvfi_trace_decompress_i (
-      .instr_i(rvfi_insn),
-      .instr_o(decomp_insn),
-      .is_compressed_o(is_compressed)
-  );
-
   `include "cv32e40px_instr_trace.svh"
 instr_trace_t trace_retire;
 
   function instr_trace_t trace_new_instr();
     instr_trace_t trace;
     trace = new();
-    trace.init(.cycles(cycles), .pc(rvfi_pc_rdata), .compressed(is_compressed),
+    trace.external_time = 1;
+    trace.simtime = rvfi_start_time - 1ns;
+    trace.stoptime = rvfi_stop_time;
+    trace.stopcycles = rvfi_stop_cycle;
+    trace.ctx = (rvfi_trap.trap) ? "(C)" : "";
+    trace.init(.cycles(rvfi_start_cycle), .pc(rvfi_pc_rdata), .compressed(is_compressed),
                .instr(decomp_insn));
     return trace;
   endfunction : trace_new_instr
 
   function void apply_reg_write();
     foreach (trace_retire.regs_write[i]) begin
-      if (rvfi_frd_wvalid[0] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[0]})) begin
-        trace_retire.regs_write[i].value = rvfi_frd_wdata[0];
-      end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin
-        trace_retire.regs_write[i].value = rvfi_rd_wdata[0];
-      end
       if (rvfi_frd_wvalid[1] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[1]})) begin
         trace_retire.regs_write[i].value = rvfi_frd_wdata[1];
       end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[1]) begin
         trace_retire.regs_write[i].value = rvfi_rd_wdata[1];
       end
     end
+    foreach (trace_retire.regs_write[i]) begin
+      if (rvfi_frd_wvalid[0] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[0]})) begin
+        trace_retire.regs_write[i].value = rvfi_frd_wdata[0];
+      end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin
+        trace_retire.regs_write[i].value = rvfi_rd_wdata[0];
+      end
+    end
   endfunction : apply_reg_write
 
   function void apply_mem_access();
@@ -202,11 +231,9 @@ instr_trace_t trace_retire;
     end
   endfunction : apply_mem_access
 
-  // cycle counter
-  always_ff @(posedge clk_i, negedge rst_ni) begin
-    if (rst_ni == 1'b0) cycles <= 0;
-    else cycles <= cycles + 1;
-  end
+  string        insn_disas;
+  logic  [31:0] insn_pc;
+  logic  [31:0] insn_val;
 
   always @(posedge clk_i) begin
     if (rvfi_valid) begin
@@ -214,6 +241,9 @@ instr_trace_t trace_retire;
       apply_reg_write();
       apply_mem_access();
       trace_retire.printInstrTrace();
+      insn_disas = trace_retire.str;
+      insn_pc    = trace_retire.pc;
+      insn_val   = trace_retire.instr;
     end
   end
 
@@ -223,7 +253,8 @@ instr_trace_t trace_retire;
     $sformat(info_tag, "CORE_TRACER %2d", hart_id_i);
     $display("[%s] Output filename is: %s", info_tag, fn);
     f = $fopen(fn, "w");
-    $fwrite(f, "Time\tCycle\tPC\tInstr\tDecoded instruction\tRegister and memory contents\n");
+    $fwrite(f,
+            "            Time           Cycle PC       Instr    Ctx Decoded instruction Register and memory contents                                 Stop cycle  Stop time\n");
   end
 
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv
index d4aa94dc..c14b131b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tb_wrapper.sv
@@ -1,45 +1,49 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// Wrapper for a cv32e40px, containing cv32e40px_top, and rvfi_tracer
-//
-// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>          //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Test-bench wrapper for cv32e40px_top, tracer and and rvfi_tracer  //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
-`ifdef CV32E40P_ASSERT_ON
+`ifdef CV32E40PX_ASSERT_ON
 `include "cv32e40px_prefetch_controller_sva.sv"
 `endif
 
-`ifdef CV32E40P_CORE_LOG
+`ifdef CV32E40PX_CORE_LOG
 `include "cv32e40px_core_log.sv"
 `endif
 
-`ifdef CV32E40P_APU_TRACE
+`ifdef CV32E40PX_APU_TRACE
 `include "cv32e40px_apu_tracer.sv"
 `endif
 
-`ifdef CV32E40P_TRACE_EXECUTION
+`ifdef CV32E40PX_TRACE_EXECUTION
 `include "cv32e40px_tracer.sv"
 `endif
 
-`ifdef CV32E40P_RVFI
+`ifdef CV32E40PX_RVFI
 `include "cv32e40px_rvfi.sv"
 `endif
 
-`ifdef CV32E40P_RVFI_TRACE_EXECUTION
+`ifdef CV32E40PX_RVFI_TRACE_EXECUTION
 `include "cv32e40px_rvfi_trace.sv"
 `endif
 
@@ -101,7 +105,7 @@ module cv32e40px_tb_wrapper
     output logic core_sleep_o
 );
 
-`ifdef CV32E40P_ASSERT_ON
+`ifdef CV32E40PX_ASSERT_ON
 
   // RTL Assertions
   bind cv32e40px_prefetch_controller:
@@ -114,9 +118,9 @@ module cv32e40px_tb_wrapper
       .FIFO_ADDR_DEPTH(FIFO_ADDR_DEPTH)
   ) prefetch_controller_sva (.*);
 
-`endif  // CV32E40P_ASSERT_ON
+`endif  // CV32E40PX_ASSERT_ON
 
-`ifdef CV32E40P_CORE_LOG
+`ifdef CV32E40PX_CORE_LOG
   cv32e40px_core_log #(
       .COREV_PULP      (COREV_PULP),
       .COREV_CLUSTER   (COREV_CLUSTER),
@@ -130,9 +134,9 @@ module cv32e40px_tb_wrapper
       .hart_id_i         (cv32e40px_top_i.core_i.hart_id_i),
       .pc_id_i           (cv32e40px_top_i.core_i.pc_id)
   );
-`endif  // CV32E40P_CORE_LOG
+`endif  // CV32E40PX_CORE_LOG
 
-`ifdef CV32E40P_APU_TRACE
+`ifdef CV32E40PX_APU_TRACE
   cv32e40px_apu_tracer apu_tracer_i (
       .clk_i       (cv32e40px_top_i.core_i.rst_ni),
       .rst_n       (cv32e40px_top_i.core_i.clk_i),
@@ -143,7 +147,7 @@ module cv32e40px_tb_wrapper
   );
 `endif
 
-`ifdef CV32E40P_TRACE_EXECUTION
+`ifdef CV32E40PX_TRACE_EXECUTION
   cv32e40px_tracer #(
       .FPU  (FPU),
       .ZFINX(ZFINX)
@@ -210,11 +214,11 @@ module cv32e40px_tb_wrapper
       .apu_en_i         (cv32e40px_top_i.apu_req),
       .apu_singlecycle_i(cv32e40px_top_i.core_i.ex_stage_i.apu_singlecycle),
       .apu_multicycle_i (cv32e40px_top_i.core_i.ex_stage_i.apu_multicycle),
-      .apu_rvalid_i     (cv32e40px_top_i.apu_rvalid)
+      .apu_rvalid_i     (cv32e40px_top_i.core_i.ex_stage_i.apu_valid)
   );
 `endif
 
-`ifdef CV32E40P_RVFI
+`ifdef CV32E40PX_RVFI
   logic [1:0][31:0] hwlp_start_q;
   logic [1:0][31:0] hwlp_end_q;
   logic [1:0][31:0] hwlp_counter_q;
@@ -234,8 +238,9 @@ module cv32e40px_tb_wrapper
   endgenerate
 
   cv32e40px_rvfi #(
-      .FPU  (FPU),
-      .ZFINX(ZFINX)
+      .FPU(FPU),
+      .ZFINX(ZFINX),
+      .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
   ) rvfi_i (
       .clk_i (cv32e40px_top_i.core_i.clk_i),
       .rst_ni(cv32e40px_top_i.core_i.rst_ni),
@@ -399,6 +404,9 @@ module cv32e40px_tb_wrapper
       .csr_mcountinhibit_n_i (cv32e40px_top_i.core_i.cs_registers_i.mcountinhibit_n),
       .csr_mcountinhibit_we_i(cv32e40px_top_i.core_i.cs_registers_i.mcountinhibit_we),
 
+      .csr_mhpmevent_n_i(cv32e40px_top_i.core_i.cs_registers_i.mhpmevent_n),
+      .csr_mhpmevent_q_i(cv32e40px_top_i.core_i.cs_registers_i.mhpmevent_q),
+      .csr_mhpmevent_we_i(cv32e40px_top_i.core_i.cs_registers_i.mhpmevent_we),
       .csr_mscratch_q_i(cv32e40px_top_i.core_i.cs_registers_i.mscratch_q),
       .csr_mscratch_n_i(cv32e40px_top_i.core_i.cs_registers_i.mscratch_n),
       .csr_mepc_q_i(cv32e40px_top_i.core_i.cs_registers_i.mepc_q),
@@ -441,8 +449,7 @@ module cv32e40px_tb_wrapper
   );
 `endif
 
-
-`ifdef CV32E40P_RVFI_TRACE_EXECUTION
+`ifdef CV32E40PX_RVFI_TRACE_EXECUTION
   bind cv32e40px_rvfi: rvfi_i cv32e40px_rvfi_trace #(
       .FPU  (FPU),
       .ZFINX(ZFINX)
@@ -455,22 +462,38 @@ module cv32e40px_tb_wrapper
 
       .rvfi_valid(rvfi_valid),
       .rvfi_insn(rvfi_insn),
+      .rvfi_start_cycle(rvfi_start_cycle),
+      .rvfi_start_time(rvfi_start_time),
+      .rvfi_stop_cycle(rvfi_stop_cycle),
+      .rvfi_stop_time(rvfi_stop_time),
       .rvfi_pc_rdata(rvfi_pc_rdata),
+      .rvfi_trap(rvfi_trap),
       .rvfi_rd_addr(rvfi_rd_addr),
       .rvfi_rd_wdata(rvfi_rd_wdata),
       .rvfi_frd_wvalid(rvfi_frd_wvalid),
       .rvfi_frd_addr(rvfi_frd_addr),
       .rvfi_frd_wdata(rvfi_frd_wdata),
+      .rvfi_2_rd(rvfi_2_rd),
       .rvfi_rs1_addr(rvfi_rs1_addr),
       .rvfi_rs2_addr(rvfi_rs2_addr),
+      .rvfi_rs3_addr(rvfi_rs3_addr),
       .rvfi_rs1_rdata(rvfi_rs1_rdata),
       .rvfi_rs2_rdata(rvfi_rs2_rdata),
+      .rvfi_rs3_rdata(rvfi_rs3_rdata),
       .rvfi_frs1_addr(rvfi_frs1_addr),
       .rvfi_frs2_addr(rvfi_frs2_addr),
+      .rvfi_frs3_addr(rvfi_frs3_addr),
       .rvfi_frs1_rvalid(rvfi_frs1_rvalid),
       .rvfi_frs2_rvalid(rvfi_frs2_rvalid),
+      .rvfi_frs3_rvalid(rvfi_frs3_rvalid),
       .rvfi_frs1_rdata(rvfi_frs1_rdata),
-      .rvfi_frs2_rdata(rvfi_frs2_rdata)
+      .rvfi_frs2_rdata(rvfi_frs2_rdata),
+      .rvfi_frs3_rdata(rvfi_frs3_rdata),
+      .rvfi_mem_addr(rvfi_mem_addr),
+      .rvfi_mem_rmask(rvfi_mem_rmask),
+      .rvfi_mem_wmask(rvfi_mem_wmask),
+      .rvfi_mem_rdata(rvfi_mem_rdata),
+      .rvfi_mem_wdata(rvfi_mem_wdata)
   );
 `endif
   // Instantiate the Core and the optinal FPU
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tracer.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tracer.sv
index c0c13315..9254ccea 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tracer.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/cv32e40px_tracer.sv
@@ -1,24 +1,26 @@
-// Copyright (c) 2020 OpenHW Group
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-
-// Traces the executed instructions
-//
-// Contributors: Andreas Traber, ETHZ <atraber@iis.ee.ethz.ch>
-//               Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+////////////////////////////////////////////////////////////////////////////////
+// Engineer:       Andreas Traber - atraber@iis.ee.ethz.ch                    //
+//                                                                            //
+// Additional contributions by:                                               //
+//                 Davide Schiavone - pschiavo@iis.ee.ethz.ch                 //
+//                                                                            //
+// Design Name:    RISC-V Tracer                                              //
+// Project Name:   RI5CY                                                      //
+// Language:       SystemVerilog                                              //
+//                                                                            //
+// Description:    Traces the executed instructions                           //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
 
 `ifdef CV32E40P_TRACE_EXECUTION
 
@@ -183,7 +185,8 @@ module cv32e40px_tracer
     $sformat(info_tag, "CORE_TRACER %2d", hart_id_i);
     $display("[%s] Output filename is: %s", info_tag, fn);
     f = $fopen(fn, "w");
-    $fwrite(f, "Time\tCycle\tPC\tInstr\tDecoded instruction\tRegister and memory contents\n");
+    $fwrite(f,
+            "            Time           Cycle PC       Instr    Ctx Decoded instruction Register and memory contents\n");
   end
 
   //initial begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_rvfi_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_rvfi_pkg.sv
index 9a131a68..5a43daf6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_rvfi_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_rvfi_pkg.sv
@@ -1,24 +1,28 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// Includes to print info about the RVFI output
-//
-// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>          //
+//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>     //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Package to print info on RVFI interface                          //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
 package cv32e40px_rvfi_pkg;
   import cv32e40px_pkg::*;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv
index 90ee5be9..2046dd74 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/include/cv32e40px_tracer_pkg.sv
@@ -1,23 +1,13 @@
-// Copyright (c) 2020 OpenHW Group
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-
-// Tracer package
-//
-// Contributors: Steve Richmond, Silicon Labs <steve.richmond@silabs.com>
-//               Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
 
 package cv32e40px_tracer_pkg;
   import cv32e40px_pkg::*;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv
index 3fe7c184..8cdc06d9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/insn_trace.sv
@@ -1,5 +1,26 @@
-// Copyright 2022 Dolphin Design
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// Copyright 2024 OpenHW Group and Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
+// You may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Macros and Functions to print information on RVFI interface      //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
   `define DEFINE_CSR(CSR_NAME) \
     logic ``CSR_NAME``_we; \
@@ -23,6 +44,10 @@
   class insn_trace_t;
     bit m_valid;
     logic [63:0] m_order;
+    integer      m_start_cycle;
+    integer      m_stop_cycle;
+    time         m_start_time;
+    time         m_stop_time;
     bit          m_skip_order; //next order was used by trap;
     logic [31:0] m_pc_rdata;
     logic [31:0] m_insn;
@@ -65,14 +90,15 @@
     bit m_move_down_pipe;
 
     int m_instret_cnt;
+    int m_instret_smaple_trigger; //We need to sample minstret from csr 2 cycle after id is doen
 
     bit m_sample_csr_write_in_ex;
 
     struct {
       logic [31:0] addr ;
-      logic [ 3:0] rmask;
+      logic [31:0] rmask;
       logic [31:0] rdata;
-      logic [ 3:0] wmask;
+      logic [31:0] wmask;
       logic [31:0] wdata;
     } m_mem;
 
@@ -102,9 +128,28 @@
       `DEFINE_CSR(mscratch)
       `DEFINE_CSR(mepc)
       `DEFINE_CSR(mcause)
+      `DEFINE_CSR(mcycle)
       `DEFINE_CSR(minstret)
       bit got_minstret;
-
+      `DEFINE_CSR(mcycleh)
+      `DEFINE_CSR(minstreth)
+      `DEFINE_CSR(cycle)
+      `DEFINE_CSR(instret)
+      // bit got_minstret;
+      `DEFINE_CSR(cycleh)
+      `DEFINE_CSR(instreth)
+
+      logic [31:0][ 1:0]    mhpmcounter_we;
+      logic [31:0][63:0] mhpmcounter_rdata;
+      logic [31:0][63:0] mhpmcounter_rmask;
+      logic [31:0][63:0] mhpmcounter_wdata;
+      logic [31:0][63:0] mhpmcounter_wmask;
+
+      logic [31:0]          mhpmevent_we;
+      logic [31:0][31:0] mhpmevent_rdata;
+      logic [31:0][31:0] mhpmevent_rmask;
+      logic [31:0][31:0] mhpmevent_wdata;
+      logic [31:0][31:0] mhpmevent_wmask;
       `DEFINE_CSR(mip)
       //mnxti
       //mintstatus
@@ -148,6 +193,10 @@
 
     function new();
       this.m_order                  = 0;
+      this.m_start_cycle            = 0;
+      this.m_stop_cycle             = 0;
+      this.m_start_time             = 0;
+      this.m_stop_time              = 0;
       this.m_skip_order             = 1'b0;
       this.m_valid                  = 1'b0;
       this.m_move_down_pipe         = 1'b0;
@@ -173,6 +222,7 @@
       this.m_frm_we_non_apu         = 1'b0;
       this.m_fcsr_we_non_apu        = 1'b0;
       this.m_instret_cnt            = 0;
+      this.m_instret_smaple_trigger = 0;
       this.m_sample_csr_write_in_ex = 1'b1;
     endfunction
 
@@ -613,12 +663,12 @@
           INSTR_CVCMPLEB     : this.m_mnemonic = "cv.cmple.b";
           INSTR_CVCMPLESCB   : this.m_mnemonic = "cv.cmple.sc.b";
           INSTR_CVCMPLESCIB  : this.m_mnemonic = "cv.cmple.sci.b";
-          INSTR_CVCMPGTUH    : this.m_mnemonic = "cv.cmptu.h";
-          INSTR_CVCMPGTUSCH  : this.m_mnemonic = "cv.cmptu.sc.h";
-          INSTR_CVCMPGTUSCIH : this.m_mnemonic = "cv.cmptu.sci.h";
-          INSTR_CVCMPGTUB    : this.m_mnemonic = "cv.cmptu.b";
-          INSTR_CVCMPGTUSCB  : this.m_mnemonic = "cv.cmptu.sc.b";
-          INSTR_CVCMPGTUSCIB : this.m_mnemonic = "cv.cmptu.sci.b";
+          INSTR_CVCMPGTUH    : this.m_mnemonic = "cv.cmpgtu.h";
+          INSTR_CVCMPGTUSCH  : this.m_mnemonic = "cv.cmpgtu.sc.h";
+          INSTR_CVCMPGTUSCIH : this.m_mnemonic = "cv.cmpgtu.sci.h";
+          INSTR_CVCMPGTUB    : this.m_mnemonic = "cv.cmpgtu.b";
+          INSTR_CVCMPGTUSCB  : this.m_mnemonic = "cv.cmpgtu.sc.b";
+          INSTR_CVCMPGTUSCIB : this.m_mnemonic = "cv.cmpgtu.sci.b";
           INSTR_CVCMPGEUH    : this.m_mnemonic = "cv.cmpgeu.h";
           INSTR_CVCMPGEUSCH  : this.m_mnemonic = "cv.cmpgeu.sc.h";
           INSTR_CVCMPGEUSCIH : this.m_mnemonic = "cv.cmpgeu.sci.h";
@@ -847,7 +897,18 @@
       `INIT_CSR(mscratch)
       `INIT_CSR(mepc)
       `INIT_CSR(mcause)
+      `INIT_CSR(mcycle)
       `INIT_CSR(minstret)
+      `INIT_CSR(mcycleh)
+      `INIT_CSR(minstreth)
+      `INIT_CSR(cycle)
+      `INIT_CSR(instret)
+      `INIT_CSR(cycleh)
+      `INIT_CSR(instreth)
+      this.m_csr.mhpmcounter_we = '0;
+      this.m_csr.mhpmcounter_wmask = '0;
+      this.m_csr.mhpmevent_we = '0;
+      this.m_csr.mhpmevent_wmask = '0;
       `INIT_CSR(mip)
       `INIT_CSR(tdata1)
       `INIT_CSR(tdata2)
@@ -875,6 +936,10 @@
       this.m_valid            = 1'b1;
       this.m_stage            = ID;
       this.m_order            = this.m_order + 64'h1;
+      this.m_start_cycle      = cycles;
+      this.m_stop_cycle       = 0;
+      this.m_start_time       = $time;
+      this.m_stop_time        = 0;
       if(this.m_skip_order) begin
         this.m_order            = this.m_order + 64'h1;
       end
@@ -896,6 +961,7 @@
       this.m_got_regs_write         = 1'b0;
       this.m_move_down_pipe         = 1'b0;
       this.m_instret_cnt            = 0;
+      this.m_instret_smaple_trigger = 0;
       this.m_sample_csr_write_in_ex = 1'b1;
       this.m_rd_addr[0]             = '0;
       this.m_rd_addr[1]             = '0;
@@ -951,6 +1017,10 @@
       this.m_valid                  = m_source.m_valid;
       this.m_stage                  = m_source.m_stage;
       this.m_order                  = m_source.m_order;
+      this.m_start_cycle            = m_source.m_start_cycle;
+      this.m_stop_cycle             = m_source.m_stop_cycle;
+      this.m_start_time             = m_source.m_start_time;
+      this.m_stop_time              = m_source.m_stop_time;
       this.m_pc_rdata               = m_source.m_pc_rdata;
       this.m_insn                   = m_source.m_insn;
       this.m_mnemonic               = m_source.m_mnemonic;
@@ -970,6 +1040,7 @@
       this.m_is_illegal             = m_source.m_is_illegal;
       this.m_is_irq                 = m_source.m_is_irq;
       this.m_instret_cnt            = m_source.m_instret_cnt;
+      this.m_instret_smaple_trigger = m_source.m_instret_smaple_trigger;
       this.m_sample_csr_write_in_ex = m_source.m_sample_csr_write_in_ex;
       this.m_rs1_addr               = m_source.m_rs1_addr;
       this.m_rs2_addr               = m_source.m_rs2_addr;
@@ -1000,8 +1071,26 @@
       `ASSIGN_CSR(mscratch)
       `ASSIGN_CSR(mepc)
       `ASSIGN_CSR(mcause)
+      `ASSIGN_CSR(mcycle)
       `ASSIGN_CSR(minstret)
       this.m_csr.got_minstret = m_source.m_csr.got_minstret;
+      `ASSIGN_CSR(mcycleh)
+      `ASSIGN_CSR(minstreth)
+      `ASSIGN_CSR(cycle)
+      `ASSIGN_CSR(instret)
+      // this.m_csr.got_minstret = m_source.m_csr.got_minstret;
+      `ASSIGN_CSR(cycleh)
+      `ASSIGN_CSR(instreth)
+      this.m_csr.mhpmcounter_we = m_source.m_csr.mhpmcounter_we;
+      this.m_csr.mhpmcounter_rdata = m_source.m_csr.mhpmcounter_rdata;
+      this.m_csr.mhpmcounter_rmask = m_source.m_csr.mhpmcounter_rmask;
+      this.m_csr.mhpmcounter_wdata = m_source.m_csr.mhpmcounter_wdata;
+      this.m_csr.mhpmcounter_wmask = m_source.m_csr.mhpmcounter_wmask;
+      this.m_csr.mhpmevent_we = m_source.m_csr.mhpmevent_we;
+      this.m_csr.mhpmevent_rdata = m_source.m_csr.mhpmevent_rdata;
+      this.m_csr.mhpmevent_rmask = m_source.m_csr.mhpmevent_rmask;
+      this.m_csr.mhpmevent_wdata = m_source.m_csr.mhpmevent_wdata;
+      this.m_csr.mhpmevent_wmask = m_source.m_csr.mhpmevent_wmask;
       `ASSIGN_CSR(mip)
       `ASSIGN_CSR(tdata1)
       `ASSIGN_CSR(tdata2)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv
index 88d65d0b..39a16fa6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/bhv/pipe_freeze_trace.sv
@@ -1,27 +1,29 @@
-// Copyright (c) 2023 OpenHW Group
+// Copyright 2024 OpenHW Group and Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// CV32E40P
-//
-// Contributors: Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Structures, Functions and Task used to store all information     //
+//               coming from the core pipeline at every posedge.                  //
+//               Those information will then be processed by RVFI.                //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
-/*
-   * This struct is used to store all information comming from the core at every posedge
-   * The information will then be processed
-   */
 typedef struct {
   logic is_decoding;
   logic is_illegal;
@@ -349,6 +351,7 @@ function compute_csr_we();
   r_pipe_freeze_trace.csr.fflags_we     = 1'b0;
   r_pipe_freeze_trace.csr.frm_we        = 1'b0;
   r_pipe_freeze_trace.csr.fcsr_we       = 1'b0;
+  r_pipe_freeze_trace.csr.mhpmevent_we  = '0;
   r_pipe_freeze_trace.csr.dpc_we        = csr_dpc_we_i;
   if (r_pipe_freeze_trace.csr.we) begin
     case (r_pipe_freeze_trace.csr.addr)
@@ -366,7 +369,10 @@ function compute_csr_we();
         r_pipe_freeze_trace.csr.fflags_we = 1'b1;
         r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
       end
-      CSR_FRM:       r_pipe_freeze_trace.csr.frm_we = 1'b1;
+      CSR_FRM: begin
+        r_pipe_freeze_trace.csr.frm_we = 1'b1;
+        r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
+      end
       CSR_FCSR: begin
         r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
         r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
@@ -376,6 +382,10 @@ function compute_csr_we();
       CSR_DSCRATCH1: r_pipe_freeze_trace.csr.dscratch1_we = 1'b1;
     endcase
   end
+
+  if (csr_mhpmevent_we_i) begin
+    r_pipe_freeze_trace.csr.mhpmevent_we[r_pipe_freeze_trace.csr.addr[4:0]] = 1'b1;
+  end
   // CSR_MCAUSE:   r_pipe_freeze_trace.csr.mcause_we = r_pipe_freeze_trace.csr.mcause_n != r_pipe_freeze_trace.csr.mcause_q; //for debug purpose
 endfunction
 /*
@@ -573,7 +583,6 @@ task monitor_pipeline();
     r_pipe_freeze_trace.csr.mcountinhibit_we = csr_mcountinhibit_we_i;
     r_pipe_freeze_trace.csr.mhpmevent_n = csr_mhpmevent_n_i;
     r_pipe_freeze_trace.csr.mhpmevent_q = csr_mhpmevent_q_i;
-    r_pipe_freeze_trace.csr.mhpmevent_we = csr_mhpmevent_we_i;
     r_pipe_freeze_trace.csr.mscratch_n = csr_mscratch_n_i;
     r_pipe_freeze_trace.csr.mscratch_q = csr_mscratch_q_i;
     r_pipe_freeze_trace.csr.mepc_n = csr_mepc_n_i;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
index a3e3bac9..e9807a38 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
@@ -597,7 +597,17 @@ module cv32e40px_controller import cv32e40px_pkg::*;
 
                     csr_status_i: begin
                       halt_if_o     = 1'b1;
-                      ctrl_fsm_ns   = id_ready_i ? FLUSH_EX : DECODE;
+                      if (~id_ready_i) begin
+                        ctrl_fsm_ns = DECODE;
+                      end else begin
+                        ctrl_fsm_ns = FLUSH_EX;
+                        if (hwlp_end0_eq_pc) begin
+                          hwlp_dec_cnt_o[0] = 1'b1;
+                        end
+                        if (hwlp_end1_eq_pc) begin
+                          hwlp_dec_cnt_o[1] = 1'b1;
+                        end
+                      end
                     end
 
                     data_load_event_i: begin
@@ -617,7 +627,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                         ctrl_fsm_ns  = hwlp_end0_eq_pc_plus4 || hwlp_end1_eq_pc_plus4 ? DECODE : DECODE_HWLOOP;
 
                         // we can be at the end of HWloop due to a return from interrupt or ecall or ebreak or exceptions
-                        if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin
+                        if (hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin
                           pc_mux_o         = PC_HWLOOP;
                           if (~jump_done_q) begin
                             pc_set_o          = 1'b1;
@@ -791,7 +801,17 @@ module cv32e40px_controller import cv32e40px_pkg::*;
 
                     csr_status_i: begin
                       halt_if_o     = 1'b1;
-                      ctrl_fsm_ns   = id_ready_i ? FLUSH_EX : DECODE_HWLOOP;
+                      if (~id_ready_i) begin
+                        ctrl_fsm_ns = DECODE_HWLOOP;
+                      end else begin
+                        ctrl_fsm_ns = FLUSH_EX;
+                        if (hwlp_end0_eq_pc) begin
+                          hwlp_dec_cnt_o[0] = 1'b1;
+                        end
+                        if (hwlp_end1_eq_pc) begin
+                          hwlp_dec_cnt_o[1] = 1'b1;
+                        end
+                      end
                     end
 
                     data_load_event_i: begin
@@ -1067,16 +1087,10 @@ module cv32e40px_controller import cv32e40px_pkg::*;
               end
 
               csr_status_i: begin
-
-                if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin
-                    pc_mux_o         = PC_HWLOOP;
-                    pc_set_o          = 1'b1;
-                    hwlp_dec_cnt_o[0] = 1'b1;
-              end
-                if(hwlp_end1_eq_pc && hwlp_counter1_gt_1) begin
-                    pc_mux_o         = PC_HWLOOP;
-                    pc_set_o          = 1'b1;
-                    hwlp_dec_cnt_o[1] = 1'b1;
+                if ((hwlp_end0_eq_pc && !hwlp_counter0_eq_0) ||
+                    (hwlp_end1_eq_pc && !hwlp_counter1_eq_0)) begin
+                  pc_mux_o = PC_HWLOOP;
+                  pc_set_o = 1'b1;
                 end
               end
 
@@ -1561,7 +1575,7 @@ endgenerate
 
     // HWLoop 0 and 1 having target address constraints
     property p_hwlp_same_target_address;
-       @(posedge clk) (hwlp_counter_i[1] > 1 && hwlp_counter_i[0] > 1) |-> ( hwlp_end_addr_i[1] - 4 >= hwlp_end_addr_i[0] - 4 + 8 );
+       @(posedge clk) (hwlp_counter_i[1] > 1 && hwlp_counter_i[0] > 1 && pc_id_i >= hwlp_start_addr_i[0] && pc_id_i <= hwlp_end_addr_i[0] - 4) |-> ( hwlp_end_addr_i[1] - 4 >= hwlp_end_addr_i[0] - 4 + 8 );
     endproperty
 
     a_hwlp_same_target_address : assert property(p_hwlp_same_target_address) else $warning("%t, HWLoops target address do not respect constraints", $time);
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
index 25aa6cc9..91c4eb8d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
@@ -72,7 +72,8 @@ module cv32e40px_core
     output logic [31:0] data_wdata_o,
     input  logic [31:0] data_rdata_i,
 
-    // apu-interconnect
+    // CVFPU interface
+    output logic                              apu_busy_o,
     // handshake signals
     output logic                              apu_req_o,
     input  logic                              apu_gnt_i,
@@ -199,7 +200,6 @@ module cv32e40px_core
   logic               ctrl_busy;
   logic               if_busy;
   logic               lsu_busy;
-  logic               apu_busy;
 
   logic        [31:0] pc_ex;  // PC of last executed branch or cv.elw
 
@@ -445,7 +445,7 @@ module cv32e40px_core
       .if_busy_i  (if_busy),
       .ctrl_busy_i(ctrl_busy),
       .lsu_busy_i (lsu_busy),
-      .apu_busy_i (apu_busy),
+      .apu_busy_i (apu_busy_o),
 
       // PULP cluster
       .pulp_clock_en_i       (pulp_clock_en_i),
@@ -690,7 +690,7 @@ module cv32e40px_core
       .apu_write_regs_valid_o (apu_write_regs_valid),
       .apu_write_dep_i        (apu_write_dep),
       .apu_perf_dep_o         (perf_apu_dep),
-      .apu_busy_i             (apu_busy),
+      .apu_busy_i             (apu_busy_o),
 
       // CORE-V-XIF
       // Compressed Interface
@@ -909,9 +909,9 @@ module cv32e40px_core
       .apu_perf_cont_o(perf_apu_cont),
       .apu_perf_wb_o  (perf_apu_wb),
       .apu_ready_wb_o (apu_ready_wb),
-      .apu_busy_o     (apu_busy),
+      .apu_busy_o     (apu_busy_o),
 
-      // apu-interconnect
+      // CVFPU interface
       // handshake signals
       .apu_req_o     (apu_req_o),
       .apu_gnt_i     (apu_gnt_i),
@@ -1160,9 +1160,9 @@ module cv32e40px_core
   assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0);
 
   //  Floating-Point registers write
-  assign fregs_we     = (FPU & !ZFINX) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
-                                          (regfile_we_wb     && regfile_waddr_fw_wb_o[5]))
-                                       : 1'b0;
+  assign fregs_we     = (FPU == 1 & ZFINX == 0) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
+                                                   (regfile_we_wb     && regfile_waddr_fw_wb_o[5]))
+                                                : 1'b0;
 
   ///////////////////////////
   //   ____  __  __ ____   //
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv
index f24b3bf9..53005725 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv
@@ -509,7 +509,7 @@ module cv32e40px_cs_registers
 
         // mimpid, Machine Implementation ID
         CSR_MIMPID: begin
-          csr_rdata_int = (FPU || COREV_PULP || COREV_CLUSTER) ? 32'h1 : 'b0;
+          csr_rdata_int = (FPU == 1 || COREV_PULP == 1 || COREV_CLUSTER == 1) ? 32'h1 : 'b0;
         end
 
         // unimplemented, read 0 CSRs
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_decoder.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_decoder.sv
index 3d55fdbc..c8e11cc3 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_decoder.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_decoder.sv
@@ -1057,7 +1057,6 @@ module cv32e40px_decoder
             5'b00000: begin
               fpu_op             = cv32e40px_fpu_pkg::ADD;
               fp_op_group        = ADDMUL;
-              apu_op_o           = 2'b0;
               alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD;
               alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD;
             end
@@ -1066,7 +1065,6 @@ module cv32e40px_decoder
               fpu_op             = cv32e40px_fpu_pkg::ADD;
               fpu_op_mod         = 1'b1;
               fp_op_group        = ADDMUL;
-              apu_op_o           = 2'b1;
               alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD;
               alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD;
             end
@@ -1085,7 +1083,6 @@ module cv32e40px_decoder
               regb_used_o = 1'b0;
               fpu_op      = cv32e40px_fpu_pkg::SQRT;
               fp_op_group = DIVSQRT;
-              apu_op_o    = 1'b1;
               // rs2 must be zero
               if (instr_rdata_i[24:20] != 5'b00000) illegal_insn_o = 1'b1;
             end
@@ -1213,7 +1210,6 @@ module cv32e40px_decoder
               fpu_op      = cv32e40px_fpu_pkg::F2I;
               fp_op_group = CONV;
               fpu_op_mod  = instr_rdata_i[20]; // signed/unsigned switch
-              apu_op_o    = 2'b1;
 
               unique case (instr_rdata_i[26:25]) //fix for casting to different formats other than FP32
                 2'b00: begin
@@ -1249,7 +1245,6 @@ module cv32e40px_decoder
               fpu_op      = cv32e40px_fpu_pkg::I2F;
               fp_op_group = CONV;
               fpu_op_mod  = instr_rdata_i[20]; // signed/unsigned switch
-              apu_op_o    = 2'b0;
               // bits [21:20] used, other bits must be 0
               if (instr_rdata_i[24:21]) illegal_insn_o = 1'b1;   // in RV32, no casts to L allowed.
             end
@@ -1323,20 +1318,20 @@ module cv32e40px_decoder
           // check rounding mode
           if (check_fprm) begin
             unique case (instr_rdata_i[14:12]) inside
-              [3'b000:3'b100]: ; //legal rounding modes
+              3'b000, 3'b001, 3'b010, 3'b011, 3'b100: ; //legal rounding modes
               3'b101: begin      // Alternative Half-Precsision encded as fmt=10 and rm=101
                 if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40px_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1;
                 // actual rounding mode from frm csr
                 unique case (frm_i) inside
-                  [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
-                  default         : illegal_insn_o = 1'b1;
+                  3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
+                  default                                : illegal_insn_o = 1'b1;
                 endcase
               end
               3'b111: begin
                 // rounding mode from frm csr
                 unique case (frm_i) inside
-                  [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
-                  default         : illegal_insn_o = 1'b1;
+                  3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
+                  default                                : illegal_insn_o = 1'b1;
                 endcase
               end
               default : illegal_insn_o = 1'b1;
@@ -1364,6 +1359,7 @@ module cv32e40px_decoder
             NONCOMP : apu_lat_o = (FPU_OTHERS_LAT<2) ? FPU_OTHERS_LAT+1 : 2'h3;
             // CONV uses the same latency for all formats
             CONV    : apu_lat_o = (FPU_OTHERS_LAT<2) ? FPU_OTHERS_LAT+1 : 2'h3;
+            default: ;
           endcase
 
           // Set FPnew OP and OPMOD as the APU op
@@ -1425,25 +1421,21 @@ module cv32e40px_decoder
           unique case (instr_rdata_i[6:0])
             // fmadd.fmt - FP Fused multiply-add
             OPCODE_OP_FMADD : begin
-              fpu_op      = cv32e40px_fpu_pkg::FMADD;
-              apu_op_o    = 2'b00;
+              fpu_op     = cv32e40px_fpu_pkg::FMADD;
             end
             // fmsub.fmt - FP Fused multiply-subtract
             OPCODE_OP_FMSUB : begin
-              fpu_op      = cv32e40px_fpu_pkg::FMADD;
-              fpu_op_mod  = 1'b1;
-              apu_op_o    = 2'b01;
+              fpu_op     = cv32e40px_fpu_pkg::FMADD;
+              fpu_op_mod = 1'b1;
             end
             // fnmsub.fmt - FP Negated fused multiply-subtract
             OPCODE_OP_FNMSUB : begin
-              fpu_op      = cv32e40px_fpu_pkg::FNMSUB;
-              apu_op_o    = 2'b10;
+              fpu_op     = cv32e40px_fpu_pkg::FNMSUB;
             end
             // fnmadd.fmt - FP Negated fused multiply-add
             OPCODE_OP_FNMADD : begin
-              fpu_op      = cv32e40px_fpu_pkg::FNMSUB;
-              fpu_op_mod  = 1'b1;
-              apu_op_o    = 2'b11;
+              fpu_op     = cv32e40px_fpu_pkg::FNMSUB;
+              fpu_op_mod = 1'b1;
             end
             default : ;
           endcase
@@ -1459,19 +1451,19 @@ module cv32e40px_decoder
 
           // check rounding mode
           unique case (instr_rdata_i[14:12]) inside
-            [3'b000:3'b100]: ; //legal rounding modes
+            3'b000, 3'b001, 3'b010, 3'b011, 3'b100: ; //legal rounding modes
             3'b101: begin      // Alternative Half-Precsision encded as fmt=10 and rm=101
               if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40px_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1;
               // actual rounding mode from frm csr
               unique case (frm_i) inside
-                [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
+                3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
                 default         : illegal_insn_o = 1'b1;
               endcase
             end
             3'b111: begin
               // rounding mode from frm csr
               unique case (frm_i) inside
-                [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
+                3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
                 default         : illegal_insn_o = 1'b1;
               endcase
             end
@@ -1493,6 +1485,7 @@ module cv32e40px_decoder
 
           // Set FPnew OP and OPMOD as the APU op
           apu_op_o = {fpu_vec_op, fpu_op_mod, fpu_op};
+
         // No FPU or (ZFINX == 0 && MSTATUS.FS == FS_OFF)
         end else begin
           illegal_insn_o = 1'b1;
@@ -1900,15 +1893,14 @@ module cv32e40px_decoder
                   alu_op_b_mux_sel_o    = OP_B_REGA_OR_FWD;
 
                   unique case (instr_rdata_i[27:25])
-                    3'b000: alu_operator_o = ALU_ADD;                  // cv.addNr
-                    3'b001: alu_operator_o = ALU_ADDU;                 // cv.adduNr
-                    3'b010: alu_operator_o = ALU_ADDR;                 // cv.addRNr
-                    3'b011: alu_operator_o = ALU_ADDUR;                // cv.adduRNr
-                    3'b100: alu_operator_o = ALU_SUB;                  // cv.subNr
-                    3'b101: alu_operator_o = ALU_SUBU;                 // cv.subuNr
-                    3'b110: alu_operator_o = ALU_SUBR;                 // cv.subRNr
-                    3'b111: alu_operator_o = ALU_SUBUR;                // cv.subuRNr
-                    default: alu_operator_o = ALU_ADD;
+                    3'b001:  alu_operator_o = ALU_ADDU;                 // cv.adduNr
+                    3'b010:  alu_operator_o = ALU_ADDR;                 // cv.addRNr
+                    3'b011:  alu_operator_o = ALU_ADDUR;                // cv.adduRNr
+                    3'b100:  alu_operator_o = ALU_SUB;                  // cv.subNr
+                    3'b101:  alu_operator_o = ALU_SUBU;                 // cv.subuNr
+                    3'b110:  alu_operator_o = ALU_SUBR;                 // cv.subRNr
+                    3'b111:  alu_operator_o = ALU_SUBUR;                // cv.subuRNr
+                    default: alu_operator_o = ALU_ADD;                  // cv.addNr
                   endcase
                 end
 
@@ -2085,7 +2077,6 @@ module cv32e40px_decoder
 
               // decide between using unsigned and rounding, and combinations
               unique case ({instr_rdata_i[31:30], instr_rdata_i[12]})
-                {2'b00, 1'b0}: alu_operator_o = ALU_ADD;                   // cv.addN
                 {2'b01, 1'b0}: alu_operator_o = ALU_ADDU;                  // cv.adduN
                 {2'b10, 1'b0}: alu_operator_o = ALU_ADDR;                  // cv.addRN
                 {2'b11, 1'b0}: alu_operator_o = ALU_ADDUR;                 // cv.adduRN
@@ -2093,12 +2084,12 @@ module cv32e40px_decoder
                 {2'b01, 1'b1}: alu_operator_o = ALU_SUBU;                  // cv.subuN
                 {2'b10, 1'b1}: alu_operator_o = ALU_SUBR;                  // cv.subRN
                 {2'b11, 1'b1}: alu_operator_o = ALU_SUBUR;                 // cv.subuRN
-                default      : alu_operator_o = ALU_ADD;
+                default      : alu_operator_o = ALU_ADD;                   // cv.addN
               endcase
 
             end
 
-            2'b10, 2'b11: begin
+            default: begin
               // MUL/MAC with subword selection
               alu_en             = 1'b0;
               mult_int_en        = 1'b1;
@@ -2126,7 +2117,6 @@ module cv32e40px_decoder
                 mult_operator_o = MUL_I;
               end
             end
-            default: illegal_insn_o = 1'b1;
           endcase
         end else begin
           illegal_insn_o = 1'b1;
@@ -2267,6 +2257,11 @@ module cv32e40px_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restrictions
+              if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) ||
+                  (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b01001_0: begin // cv.sra
               alu_operator_o = ALU_SRA;
@@ -2278,6 +2273,11 @@ module cv32e40px_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restrictions
+              if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) ||
+                  (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b01010_0: begin // cv.sll
               alu_operator_o = ALU_SLL;
@@ -2289,6 +2289,11 @@ module cv32e40px_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restrictions
+              if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) ||
+                  (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b01011_0: begin // cv.or
               alu_operator_o = ALU_OR;
@@ -2425,6 +2430,11 @@ module cv32e40px_decoder
                 end
                 default: illegal_insn_o = 1'b1;
               endcase
+              // Imm6 restrictions
+              if ((instr_rdata_i[12] == 1'b0 && instr_rdata_i[24:20] != 5'b0) ||
+                  (instr_rdata_i[12] == 1'b1 && instr_rdata_i[24:21] != 4'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b11000_0: begin // cv.shuffle, cv.shuffleI0
               alu_operator_o       = ALU_SHUF;
@@ -2439,6 +2449,10 @@ module cv32e40px_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restriction
+              if (instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:21] != 4'b0) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b11001_0,
             6'b11010_0,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv
index 3beaf022..02876108 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv
@@ -266,7 +266,7 @@ module cv32e40px_ex_stage
 
     if (regfile_we_lsu) begin
       regfile_we_wb_o       = 1'b1;
-      regfile_we_wb_power_o = !COREV_PULP ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
+      regfile_we_wb_power_o = (COREV_PULP == 0) ? 1'b1 : ~data_misaligned_ex_i & wb_ready_i;
       if (apu_valid & (!apu_singlecycle & !apu_multicycle)) begin
         wb_contention_lsu = 1'b1;
       end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
index 54add99d..126a1f44 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
@@ -14,7 +14,7 @@
 module cv32e40px_fp_wrapper
   import cv32e40px_apu_core_pkg::*;
 #(
-    parameter FPU_ADDMUL_LAT = 0,  // Floating-Point ADDition/MULtiplication computing lane pipeline registers number
+    parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number
     parameter FPU_OTHERS_LAT = 0  // Floating-Point COMParison/CONVersion computing lanes pipeline registers number
 ) (
     // Clock and Reset
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
index 6e996c32..9f1f668b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
@@ -1772,9 +1772,13 @@ module cv32e40px_id_stage
       if (id_valid_o) begin  // unstall the whole pipeline
         alu_en_ex_o <= alu_en;
         if (alu_en) begin
-          alu_operator_ex_o   <= alu_operator;
-          alu_operand_a_ex_o  <= alu_operand_a;
-          alu_operand_b_ex_o  <= alu_operand_b;
+          alu_operator_ex_o  <= alu_operator;
+          alu_operand_a_ex_o <= alu_operand_a;
+          if (alu_op_b_mux_sel == OP_B_REGB_OR_FWD && (alu_operator == ALU_CLIP || alu_operator == ALU_CLIPU)) begin
+            alu_operand_b_ex_o <= {1'b0, alu_operand_b[30:0]};
+          end else begin
+            alu_operand_b_ex_o <= alu_operand_b;
+          end
           alu_operand_c_ex_o  <= alu_operand_c;
           bmask_a_ex_o        <= bmask_a_id;
           bmask_b_ex_o        <= bmask_b_id;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_load_store_unit.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_load_store_unit.sv
index 674da664..92194ccd 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_load_store_unit.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_load_store_unit.sv
@@ -121,18 +121,18 @@ module cv32e40px_load_store_unit #(
       2'b00: begin  // Writing a word
         if (misaligned_st == 1'b0) begin  // non-misaligned case
           case (data_addr_int[1:0])
-            2'b00: data_be = 4'b1111;
-            2'b01: data_be = 4'b1110;
-            2'b10: data_be = 4'b1100;
-            2'b11: data_be = 4'b1000;
+            2'b00:   data_be = 4'b1111;
+            2'b01:   data_be = 4'b1110;
+            2'b10:   data_be = 4'b1100;
+            default: data_be = 4'b1000;
           endcase
           ;  // case (data_addr_int[1:0])
         end else begin  // misaligned case
           case (data_addr_int[1:0])
-            2'b00: data_be = 4'b0000;  // this is not used, but included for completeness
-            2'b01: data_be = 4'b0001;
-            2'b10: data_be = 4'b0011;
-            2'b11: data_be = 4'b0111;
+            2'b01:   data_be = 4'b0001;
+            2'b10:   data_be = 4'b0011;
+            2'b11:   data_be = 4'b0111;
+            default: data_be = 4'b0000;  // this is not used, but included for completeness
           endcase
           ;  // case (data_addr_int[1:0])
         end
@@ -141,10 +141,10 @@ module cv32e40px_load_store_unit #(
       2'b01: begin  // Writing a half word
         if (misaligned_st == 1'b0) begin  // non-misaligned case
           case (data_addr_int[1:0])
-            2'b00: data_be = 4'b0011;
-            2'b01: data_be = 4'b0110;
-            2'b10: data_be = 4'b1100;
-            2'b11: data_be = 4'b1000;
+            2'b00:   data_be = 4'b0011;
+            2'b01:   data_be = 4'b0110;
+            2'b10:   data_be = 4'b1100;
+            default: data_be = 4'b1000;
           endcase
           ;  // case (data_addr_int[1:0])
         end else begin  // misaligned case
@@ -154,10 +154,10 @@ module cv32e40px_load_store_unit #(
 
       2'b10, 2'b11: begin  // Writing a byte
         case (data_addr_int[1:0])
-          2'b00: data_be = 4'b0001;
-          2'b01: data_be = 4'b0010;
-          2'b10: data_be = 4'b0100;
-          2'b11: data_be = 4'b1000;
+          2'b00:   data_be = 4'b0001;
+          2'b01:   data_be = 4'b0010;
+          2'b10:   data_be = 4'b0100;
+          default: data_be = 4'b1000;
         endcase
         ;  // case (data_addr_int[1:0])
       end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv
index 217150c0..63a23228 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_register_file_latch.sv
@@ -203,8 +203,8 @@ module cv32e40px_register_file #(
     mem[0] = '0;
 
     for (k = 1; k < NUM_WORDS; k++) begin : w_WordIter
-      if (~rst_n) mem[k] = '0;
-      else if (mem_clocks[k] == 1'b1) mem[k] = waddr_onehot_b_q[k] ? wdata_b_q : wdata_a_q;
+      if (~rst_n) mem[k] <= '0;
+      else if (mem_clocks[k] == 1'b1) mem[k] <= waddr_onehot_b_q[k] ? wdata_b_q : wdata_a_q;
     end
   end
 
@@ -213,9 +213,9 @@ module cv32e40px_register_file #(
     always_latch begin : latch_wdata_fp
       if (FPU == 1) begin
         for (l = 0; l < NUM_FP_WORDS; l++) begin : w_WordIter
-          if (~rst_n) mem_fp[l] = '0;
+          if (~rst_n) mem_fp[l] <= '0;
           else if (mem_clocks[l+NUM_WORDS] == 1'b1)
-            mem_fp[l] = waddr_onehot_b_q[l+NUM_WORDS] ? wdata_b_q : wdata_a_q;
+            mem_fp[l] <= waddr_onehot_b_q[l+NUM_WORDS] ? wdata_b_q : wdata_a_q;
         end
       end
     end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_top.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_top.sv
index ad3dc986..03b99626 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_top.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_top.sv
@@ -1,15 +1,27 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// Top file instantiating a CV32E40P core and an optional FPU
-// Contributor: Davide Schiavone <davide@openhwgroup.org>
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
+// You may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/////////////////////////////////////////////////////////////////////////////
+//                                                                         //
+// Contributors: Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>  //
+//                                                                         //
+// Description:  Top level module of CV32E40P instantiating the Core and   //
+//               an optional CVFPU with its clock gating cell.             //
+//                                                                         //
+/////////////////////////////////////////////////////////////////////////////
 
 module cv32e40px_top
   import cv32e40px_core_v_xif_pkg::*;
@@ -105,7 +117,7 @@ module cv32e40px_top
   import cv32e40px_apu_core_pkg::*;
 
   // Core to FPU
-  logic                              clk;
+  logic                              apu_busy;
   logic                              apu_req;
   logic [   APU_NARGS_CPU-1:0][31:0] apu_operands;
   logic [     APU_WOP_CPU-1:0]       apu_op;
@@ -117,6 +129,8 @@ module cv32e40px_top
   logic [                31:0]       apu_rdata;
   logic [APU_NUSFLAGS_CPU-1:0]       apu_rflags;
 
+  logic apu_clk_en, apu_clk;
+
   // Instantiate the Core
   cv32e40px_core #(
       .COREV_X_IF      (COREV_X_IF),
@@ -155,6 +169,7 @@ module cv32e40px_top
       .data_wdata_o (data_wdata_o),
       .data_rdata_i (data_rdata_i),
 
+      .apu_busy_o    (apu_busy),
       .apu_req_o     (apu_req),
       .apu_gnt_i     (apu_gnt),
       .apu_operands_o(apu_operands),
@@ -211,12 +226,15 @@ module cv32e40px_top
 
   generate
     if (FPU) begin : fpu_gen
+
+      assign apu_clk_en = apu_req | apu_busy;
+
       // FPU clock gate
       cv32e40px_clock_gate core_clock_gate_i (
           .clk_i       (clk_i),
-          .en_i        (!core_sleep_o),
+          .en_i        (apu_clk_en),
           .scan_cg_en_i(scan_cg_en_i),
-          .clk_o       (clk)
+          .clk_o       (apu_clk)
       );
 
       // Instantiate the FPU wrapper
@@ -224,7 +242,7 @@ module cv32e40px_top
           .FPU_ADDMUL_LAT(FPU_ADDMUL_LAT),
           .FPU_OTHERS_LAT(FPU_OTHERS_LAT)
       ) fp_wrapper_i (
-          .clk_i         (clk),
+          .clk_i         (apu_clk),
           .rst_ni        (rst_ni),
           .apu_req_i     (apu_req),
           .apu_gnt_o     (apu_gnt),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
index fe147124..dc890797 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
@@ -8,16 +8,16 @@
 // CONDITIONS OF ANY KIND, either express or implied. See the License for the
 // specific language governing permissions and limitations under the License.
 
-////////////////////////////////////////////////////////////////////////////////
-// Engineer:       Moritz Imfeld - moimfeld@student.ethz.ch                   //
-//                                                                            //
-// Design Name:    x-interface dispatcher                                     //
-// Project Name:   cv32e40px                                                   //
-// Language:       SystemVerilog                                              //
-//                                                                            //
-// Description:    Dispatcher for sending instructions to the x-interface.    //
-//                                                                            //
-////////////////////////////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////////////
+// Engineer:       Moritz Imfeld - moimfeld@ee.ethz.ch                     //
+//                                                                         //
+// Design Name:    x-interface dispatcher                                  //
+// Project Name:   cv32e40px                                               //
+// Language:       SystemVerilog                                           //
+//                                                                         //
+// Description:    Dispatcher for sending instructions to the x-interface. //
+//                                                                         //
+/////////////////////////////////////////////////////////////////////////////
 
 module cv32e40px_x_disp
   import cv32e40px_core_v_xif_pkg::*;
@@ -107,6 +107,7 @@ module cv32e40px_x_disp
   logic x_if_not_ready;
   logic x_if_memory_instr;
   logic illegal_forwarding_prevention;
+  logic x_issue_illegal;
 
   // issue interface
   assign x_issue_valid_o = x_illegal_insn_dec_i & ~branch_or_jump_i & ~instr_offloaded_q & instr_valid_i & ~illegal_forwarding_prevention;
@@ -243,10 +244,11 @@ module cv32e40px_x_disp
     end
   end
 
-  // illegal instruction assertion
+  // illegal instruction assignment
+  assign x_issue_illegal = x_illegal_insn_dec_i & ~instr_offloaded_q & instr_valid_i;
   always_comb begin
     x_illegal_insn_o = 1'b0;
-    if (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_accept_i) begin
+    if (x_issue_illegal & x_issue_ready_i & ~x_issue_resp_accept_i) begin
       x_illegal_insn_o = 1'b1;
     end
   end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.sv
index 4f79b67f..aff3d0d4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_core.sv
@@ -625,14 +625,12 @@ module cve2_core import cve2_pkg::*; #(
   assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec &
                                 id_stage_i.lsu_we;
 
-  begin : gen_no_wb_stage
-    // Without writeback stage only look into whether load or store is in ID to determine if
-    // a response is expected.
-    assign outstanding_load_resp  = outstanding_load_id;
-    assign outstanding_store_resp = outstanding_store_id;
+  // Without writeback stage only look into whether load or store is in ID to determine if
+  // a response is expected.
+  assign outstanding_load_resp  = outstanding_load_id;
+  assign outstanding_store_resp = outstanding_store_id;
 
-    `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni)
-  end
+  `ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni)
 
   `ASSERT(NoMemResponseWithoutPendingAccess,
     data_rvalid_i |-> outstanding_load_resp | outstanding_store_resp, clk_i, !rst_ni)
@@ -1094,6 +1092,9 @@ module cve2_core import cve2_pkg::*; #(
             rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
             rvfi_ext_stage_mcycle[i]      <= cs_registers_i.mcycle_counter_i.counter_val_o;
           end
+          else begin
+            rvfi_stage_trap[i]            <= 0;
+          end
         end else begin
             rvfi_stage_halt[i]      <= rvfi_stage_halt[i-1];
             rvfi_stage_trap[i]      <= rvfi_stage_trap[i-1];
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_cs_registers.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_cs_registers.sv
index dfce0985..9678638d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_cs_registers.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_cs_registers.sv
@@ -24,6 +24,7 @@ module cve2_cs_registers #(
   parameter cve2_pkg::rv32m_e RV32M             = cve2_pkg::RV32MFast,
   parameter cve2_pkg::rv32b_e RV32B             = cve2_pkg::RV32BNone
 ) (
+
   // Clock and Reset
   input  logic                 clk_i,
   input  logic                 rst_ni,
@@ -103,7 +104,7 @@ module cve2_cs_registers #(
   input  logic                 div_wait_i                   // core waiting for divide
 );
 
-  import cve2_pkg::*;
+import cve2_pkg::*;
 
   localparam int unsigned RV32BEnabled = (RV32B == RV32BNone) ? 0 : 1;
   localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1;
@@ -1444,7 +1445,83 @@ module cve2_cs_registers #(
   // CPU control register //
   //////////////////////////
 
-  // Removed
+`ifdef RVFI
+    logic [63:0] mstatus_extended_read;
+    logic [63:0] mstatus_extended_write;
+
+    assign  mstatus_extended_read[CSR_MSTATUS_MIE_BIT]                              = mstatus_q.mie;
+    assign  mstatus_extended_read[CSR_MSTATUS_MPIE_BIT]                             = mstatus_q.mpie;
+    assign  mstatus_extended_read[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q.mpp;
+    assign  mstatus_extended_read[CSR_MSTATUS_MPRV_BIT]                             = mstatus_q.mprv;
+    assign  mstatus_extended_read[CSR_MSTATUS_TW_BIT]                               = mstatus_q.tw;
+
+    assign  mstatus_extended_write[CSR_MSTATUS_MIE_BIT]                              = mstatus_d.mie;
+    assign  mstatus_extended_write[CSR_MSTATUS_MPIE_BIT]                             = mstatus_d.mpie;
+    assign  mstatus_extended_write[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_d.mpp;
+    assign  mstatus_extended_write[CSR_MSTATUS_MPRV_BIT]                             = mstatus_d.mprv;
+    assign  mstatus_extended_write[CSR_MSTATUS_TW_BIT]                               = mstatus_d.tw;
+
+    wire [63:0] rvfi_csr_bypass;
+
+    assign rvfi_csr_bypass = csr_save_cause_i;
+
+    bit [63:0] rvfi_csr_addr;
+    bit [63:0] rvfi_csr_rdata;
+    bit [63:0] rvfi_csr_wdata;
+    bit [63:0] rvfi_csr_rmask;
+    bit [63:0] rvfi_csr_wmask;
+    wire [63:0] rvfi_csr_wmask_q;
+    wire [63:0] rvfi_csr_rmask_q;
+    assign rvfi_csr_if.rvfi_csr_addr =  rvfi_csr_addr;
+    assign rvfi_csr_if.rvfi_csr_rdata = rvfi_csr_rdata;
+    assign rvfi_csr_if.rvfi_csr_wdata = rvfi_csr_wdata;
+    assign rvfi_csr_if.rvfi_csr_rmask = rvfi_csr_rmask;
+    assign rvfi_csr_if.rvfi_csr_wmask = rvfi_csr_wmask;
+    assign rvfi_csr_rmask_q =  ((~csr_wr & csr_op_en_i & ~illegal_csr_insn_o)) ? -1 : 0;
+    assign rvfi_csr_wmask_q =   ((csr_wr & csr_op_en_i & ~illegal_csr_insn_o)) ? -1 : 0;
+    always @(posedge clknrst_if.clk) begin
+        rvfi_csr_addr  = csr_addr_i;
+        rvfi_csr_rdata = csr_rdata_int;
+        rvfi_csr_wdata = csr_wdata_int;
+        rvfi_csr_rmask = (rvfi_csr_rmask_q);
+        rvfi_csr_wmask = (rvfi_csr_wmask_q);
+    end
+
+`define RVFI_CONNECT(CSR_ADDR, CSR_NAME, CSR_RDATA, CSR_WDATA, CSR_RMASK, CSR_WMASK) \
+    bit [63:0] rvfi_``CSR_NAME``_csr_rdata;\
+    bit [63:0] rvfi_``CSR_NAME``_csr_wdata;\
+    bit [63:0] rvfi_``CSR_NAME``_csr_rmask;\
+    bit [63:0] rvfi_``CSR_NAME``_csr_wmask;\
+    wire [63:0] rvfi_``CSR_NAME``_csr_wmask_q; \
+    wire [63:0] rvfi_``CSR_NAME``_csr_rmask_q; \
+    assign rvfi_csr_if.rvfi_named_csr_rdata[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_rdata : ``CSR_RDATA``; \
+    assign rvfi_csr_if.rvfi_named_csr_wdata[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_wdata : ``CSR_WDATA``; \
+    assign rvfi_csr_if.rvfi_named_csr_rmask[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_rmask : rvfi_``CSR_NAME``_csr_rmask_q; \
+    assign rvfi_csr_if.rvfi_named_csr_wmask[CSR_ADDR] = (!rvfi_csr_bypass) ? rvfi_``CSR_NAME``_csr_wmask : rvfi_``CSR_NAME``_csr_wmask_q; \
+    assign rvfi_``CSR_NAME``_csr_rmask_q =  ((~csr_wr & csr_op_en_i & ~illegal_csr_insn_o & (csr_addr_i == CSR_ADDR)) CSR_RMASK) ? -1 : 0; \
+    assign rvfi_``CSR_NAME``_csr_wmask_q =   ((csr_wr & csr_op_en_i & ~illegal_csr_insn_o & (csr_addr_i == CSR_ADDR)) CSR_WMASK) ? -1 : 0; \
+    always @(posedge clknrst_if.clk) begin \
+        rvfi_``CSR_NAME``_csr_rdata = ``CSR_RDATA``; \
+        rvfi_``CSR_NAME``_csr_wdata = ``CSR_WDATA``; \
+        rvfi_``CSR_NAME``_csr_rmask = (rvfi_``CSR_NAME``_csr_rmask_q); \
+        rvfi_``CSR_NAME``_csr_wmask = (rvfi_``CSR_NAME``_csr_wmask_q); \
+    end
+
+   `RVFI_CONNECT( CSR_MSTATUS,          mstatus                     ,  mstatus_extended_read  , mstatus_extended_write , , || mstatus_en)
+   `RVFI_CONNECT( CSR_MIE,              mie                         ,  mie_q                  , mie_d                  , , || mie_en    )
+   `RVFI_CONNECT( CSR_MIP,              mip                         ,  mip                    , csr_wdata_i            , , )
+   `RVFI_CONNECT( CSR_MISA,             misa                        ,  MISA_VALUE             , csr_wdata_i            , ,              )
+   `RVFI_CONNECT( CSR_MTVEC,            mtvec                       ,  mtvec_q                , mtvec_d                , , || mtvec_en  )
+   `RVFI_CONNECT( CSR_MEPC,             mepc                        ,  mepc_q                 , mepc_d                 , , || mepc_en   )
+   `RVFI_CONNECT( CSR_MCAUSE,           mcause                      ,  mcause_q               , mcause_d               , , || mcause_en )
+   `RVFI_CONNECT( CSR_MTVAL,            mtval                       ,  mtval_q                , mtval_d                , , || mtval_en  )
+   `RVFI_CONNECT( CSR_MSTATUSH,         mstatush                    ,  'h0                    , csr_wdata_i            , , )
+   `RVFI_CONNECT( CSR_DCSR,             dcsr                        ,  dcsr_q                 , dcsr_d                 , , || dcsr_en)
+   `RVFI_CONNECT( CSR_DPC,              dpc                         ,  depc_q                 , depc_d                 , , || depc_en)
+   `RVFI_CONNECT( CSR_DSCRATCH0,        dscratch0                   ,  dscratch0_q            , csr_wdata_i            , , || dscratch0_en)
+   `RVFI_CONNECT( CSR_DSCRATCH1,        dscratch1                   ,  dscratch1_q            , csr_wdata_i            , , || dscratch1_en)
+
+`endif
 
   ////////////////
   // Assertions //
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_fetch_fifo.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_fetch_fifo.sv
index 20b2b62b..60933a03 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_fetch_fifo.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_fetch_fifo.sv
@@ -225,7 +225,6 @@ module cve2_fetch_fifo #(
   end
 
   for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs
-    begin : g_rdata
       always_ff @(posedge clk_i or negedge rst_ni) begin
         if (!rst_ni) begin
           rdata_q[i] <= '0;
@@ -235,7 +234,6 @@ module cve2_fetch_fifo #(
           err_q[i]   <= err_d[i];
         end
       end
-    end
   end
 
   ////////////////
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_id_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_id_stage.sv
index e989ff29..e7ebf52c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_id_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_id_stage.sv
@@ -755,6 +755,7 @@ module cve2_id_stage #(
   // Signal which instructions to count as retired in minstret, all traps along with ebrk and
   // ecall instructions are not counted.
   assign instr_perf_count_id_o = ~ebrk_insn & ~ecall_insn_dec & ~illegal_insn_dec &
+      ~(dret_insn_dec & ~debug_mode_o) &
       ~illegal_csr_insn_i & ~instr_fetch_err_i;
 
   // An instruction is ready to move to the writeback
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pkg.sv
index 6cd8f4b1..2e5b3535 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_pkg.sv
@@ -574,5 +574,85 @@ package cve2_pkg;
   // alter this to point to their system specific configuration data structure.
   localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;
 
+ // RVFI CSR element
+  typedef struct packed {
+    bit [63:0] rdata;
+    bit [63:0] rmask;
+    bit [63:0] wdata;
+    bit [63:0] wmask;
+  } rvfi_csr_elmt_t;
+
+  // RVFI CSR structure
+  typedef struct packed {
+    rvfi_csr_elmt_t fflags;
+    rvfi_csr_elmt_t frm;
+    rvfi_csr_elmt_t fcsr;
+    rvfi_csr_elmt_t ftran;
+    rvfi_csr_elmt_t dcsr;
+    rvfi_csr_elmt_t dpc;
+    rvfi_csr_elmt_t dscratch0;
+    rvfi_csr_elmt_t dscratch1;
+    rvfi_csr_elmt_t sstatus;
+    rvfi_csr_elmt_t sie;
+    rvfi_csr_elmt_t sip;
+    rvfi_csr_elmt_t stvec;
+    rvfi_csr_elmt_t scounteren;
+    rvfi_csr_elmt_t sscratch;
+    rvfi_csr_elmt_t sepc;
+    rvfi_csr_elmt_t scause;
+    rvfi_csr_elmt_t stval;
+    rvfi_csr_elmt_t satp;
+    rvfi_csr_elmt_t mstatus;
+    rvfi_csr_elmt_t mstatush;
+    rvfi_csr_elmt_t misa;
+    rvfi_csr_elmt_t medeleg;
+    rvfi_csr_elmt_t mideleg;
+    rvfi_csr_elmt_t mie;
+    rvfi_csr_elmt_t mtvec;
+    rvfi_csr_elmt_t mcounteren;
+    rvfi_csr_elmt_t mscratch;
+    rvfi_csr_elmt_t mepc;
+    rvfi_csr_elmt_t mcause;
+    rvfi_csr_elmt_t mtval;
+    rvfi_csr_elmt_t mip;
+    rvfi_csr_elmt_t menvcfg;
+    rvfi_csr_elmt_t menvcfgh;
+    rvfi_csr_elmt_t mvendorid;
+    rvfi_csr_elmt_t marchid;
+    rvfi_csr_elmt_t mhartid;
+    rvfi_csr_elmt_t mcountinhibit;
+    rvfi_csr_elmt_t mcycle;
+    rvfi_csr_elmt_t mcycleh;
+    rvfi_csr_elmt_t minstret;
+    rvfi_csr_elmt_t minstreth;
+    rvfi_csr_elmt_t cycle;
+    rvfi_csr_elmt_t cycleh;
+    rvfi_csr_elmt_t instret;
+    rvfi_csr_elmt_t instreth;
+    rvfi_csr_elmt_t dcache;
+    rvfi_csr_elmt_t icache;
+    rvfi_csr_elmt_t acc_cons;
+    rvfi_csr_elmt_t pmpcfg0;
+    rvfi_csr_elmt_t pmpcfg1;
+    rvfi_csr_elmt_t pmpcfg2;
+    rvfi_csr_elmt_t pmpcfg3;
+    rvfi_csr_elmt_t pmpaddr0;
+    rvfi_csr_elmt_t pmpaddr1;
+    rvfi_csr_elmt_t pmpaddr2;
+    rvfi_csr_elmt_t pmpaddr3;
+    rvfi_csr_elmt_t pmpaddr4;
+    rvfi_csr_elmt_t pmpaddr5;
+    rvfi_csr_elmt_t pmpaddr6;
+    rvfi_csr_elmt_t pmpaddr7;
+    rvfi_csr_elmt_t pmpaddr8;
+    rvfi_csr_elmt_t pmpaddr9;
+    rvfi_csr_elmt_t pmpaddr10;
+    rvfi_csr_elmt_t pmpaddr11;
+    rvfi_csr_elmt_t pmpaddr12;
+    rvfi_csr_elmt_t pmpaddr13;
+    rvfi_csr_elmt_t pmpaddr14;
+    rvfi_csr_elmt_t pmpaddr15;
+  } rvfi_csr_t;
+
 endpackage
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top_tracing.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top_tracing.sv
index 989e83d7..7589bc3a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top_tracing.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e20/rtl/cve2_top_tracing.sv
@@ -11,7 +11,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
   parameter int unsigned MHPMCounterWidth = 40,
   parameter bit          RV32E            = 1'b0,
   parameter rv32m_e      RV32M            = RV32MFast,
-  parameter bit          BranchPredictor  = 1'b0,
   parameter int unsigned DmHaltAddr       = 32'h1A110800,
   parameter int unsigned DmExceptionAddr  = 32'h1A110808
 ) (
@@ -112,7 +111,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
     .MHPMCounterWidth ( MHPMCounterWidth ),
     .RV32E            ( RV32E            ),
     .RV32M            ( RV32M            ),
-    .BranchPredictor  ( BranchPredictor  ),
     .DmHaltAddr       ( DmHaltAddr       ),
     .DmExceptionAddr  ( DmExceptionAddr  )
   ) u_cve2_top (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson
index b122083e..fcaf1619 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/openhwgroup/cv32e40p.git
-    rev: 370cf19b3b60cbdc847ff102551392dd501029a2
+    rev: a43277c0dc64c02be3f5d713438f315ecffde2b9
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson
index 5b2ce889..9712edb0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/openhwgroup/cv32e40p.git",
-    rev: "370cf19b3b60cbdc847ff102551392dd501029a2",
+    rev: "a43277c0dc64c02be3f5d713438f315ecffde2b9",
   },
 
   patch_dir: "patches/openhwgroup_cv32e40p",
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore
index 66eb251a..6c2cd791 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/.gitignore
@@ -19,8 +19,10 @@ TAGS
 /Bender.lock
 /Bender.local
 golden_reference_design
+ref_design
 golden.src
 revised.src
 cadence_conformal
 synopsys_formality
 questa_autocheck
+reports
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh
index a89ed4e4..355bc738 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_instr_trace.svh
@@ -1,23 +1,37 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2020 Silicon Labs, Inc.
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
+// This file, and derivatives thereof are licensed under the
+// Solderpad License, Version 2.0 (the "License").
 //
-// https://solderpad.org/licenses/
+// Use of this file means you agree to the terms and conditions
+// of the license and are in full compliance with the License.
+//
+// You may obtain a copy of the License at:
+//
+//     https://solderpad.org/licenses/SHL-2.0/
 //
 // Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// and hardware implementations thereof distributed under the License
+// is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
+// OF ANY KIND, EITHER EXPRESSED OR IMPLIED.
+//
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// Tracer data structures and functions
-//
-// Contributors: Steve Richmond, Silicon Labs <steve.richmond@silabs.com>
-//               Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////
+// Engineer:       Steve Richmond - steve.richmond@silabs.com                 //
+//                                                                            //
+// Design Name:    cv32e40p_tracer data structures                            //
+// Project Name:   CV32E40P                                                   //
+// Language:       SystemVerilog                                              //
+//                                                                            //
+// Description:    Moves the class definition for instr_trace_t out of the    //
+//                 tracer module for readability and code partitioning        //
+//                                                                            //
+//                 Includes various enhancements to make the instr_trace_t    //
+//                 class more comprehensive                                   //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
 
 typedef struct {
   logic [5:0] addr;
@@ -35,9 +49,13 @@ typedef struct {
 
 class instr_trace_t;
   time         simtime;
+  time         stoptime;
+  bit          external_time;
   int          cycles;
+  int          stopcycles;
   logic [31:0] pc;
   logic [31:0] instr;
+  string       ctx; //Used to add context in the trace log file (Canceled, debug, interrput,....)
   bit          compressed;
   bit          wb_bypass;
   bit          misaligned;
@@ -56,10 +74,15 @@ class instr_trace_t;
     regs_read  = {};
     regs_write = {};
     mem_access = {};
+    external_time = 0;
+    stoptime = 0;
+    stopcycles = 0;
   endfunction
 
   function void init(int unsigned cycles, bit [31:0] pc, bit compressed, bit [31:0] instr);
-    this.simtime        = $time;
+    if(!this.external_time) begin
+      this.simtime        = $time;
+    end
     this.cycles         = cycles;
     this.pc             = pc;
     this.compressed     = compressed;
@@ -308,7 +331,23 @@ class instr_trace_t;
     begin
       string insn_str;  // Accumulate writes into a single string to enable single $fwrite
 
-      insn_str = $sformatf("%t %15d %h %h %-36s", simtime, cycles, pc, instr, str);
+      if(simtime < 100ns) begin
+        insn_str = $sformatf("       %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 1us) begin
+        insn_str = $sformatf("      %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 10us) begin
+        insn_str = $sformatf("     %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 100us) begin
+        insn_str = $sformatf("    %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 1ms) begin
+        insn_str = $sformatf("   %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 10ms) begin
+        insn_str = $sformatf("  %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else if (simtime < 100ms) begin
+        insn_str = $sformatf(" %t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end else begin
+        insn_str = $sformatf("%t %15d %h %h %-3s %-36s", simtime, cycles, pc, instr, ctx, str);
+      end
 
       foreach (regs_write[i]) begin
         if (regs_write[i].addr != 0)
@@ -330,6 +369,12 @@ class instr_trace_t;
         insn_str = $sformatf("%s  PA:%08x", insn_str, mem_acc.addr);
       end
 
+      casex (instr)
+      INSTR_FDIV: insn_str = $sformatf("%s %15d %t", insn_str, stopcycles, stoptime);
+      INSTR_FSQRT:insn_str = $sformatf("%s %15d %t", insn_str, stopcycles, stoptime);
+      default: ;
+      endcase
+
       $fwrite(f, "%s\n", insn_str);
     end
   endfunction
@@ -489,7 +534,7 @@ class instr_trace_t;
     begin
       mnemonic = {compressed ? "c." : "", mnemonic};
       regs_read.push_back('{rs1, rs1_value, 0});
-      str =  $sformatf("%-16s %s, %0d", mnemonic, regAddrToStr(rs1), $signed(imm_sb_type));
+      str =  $sformatf("%-16s %s, %0d, %0d", mnemonic, regAddrToStr(rs1), $signed(imm_s2_type), $signed(imm_sb_type));
     end
   endfunction  // printSBInstr
 
@@ -587,14 +632,14 @@ class instr_trace_t;
         // immediate post-incremented load
         regs_read.push_back('{rs1, rs1_value, 0});
         regs_write.push_back('{rs1, 'x, 0});
-        str = $sformatf("cv.%-13s %s, %0d(x%0d!)", mnemonic, regAddrToStr(rd), $signed(imm_i_type), rs1);
+        str = $sformatf("cv.%-13s %s, (x%0d), %0d", mnemonic, regAddrToStr(rd), rs1, $signed(imm_i_type));
       end else if (instr[6:0] == OPCODE_CUSTOM_1) begin
         if (instr[27] == 1'b0) begin
           // reg-reg post-incremented load
           regs_read.push_back('{rs2, rs2_value, 0});
           regs_read.push_back('{rs1, rs1_value, 0});
           regs_write.push_back('{rs1, 'x, 0});
-          str = $sformatf("cv.%-13s %s, %s(x%0d!)", mnemonic, regAddrToStr(rd), regAddrToStr(rs2), rs1);
+          str = $sformatf("cv.%-13s %s, (x%0d), %s", mnemonic, regAddrToStr(rd), rs1, regAddrToStr(rs2));
         end else begin
           // reg-reg indexed load
           regs_read.push_back('{rs2, rs2_value, 0});
@@ -637,7 +682,7 @@ class instr_trace_t;
         regs_read.push_back('{rs2, rs2_value, 0});
         regs_read.push_back('{rs1, rs1_value, 0});
         regs_write.push_back('{rs1, 'x, 0});
-        str = $sformatf("cv.%-14s %s, %0d(x%0d!)", mnemonic, regAddrToStr(rs2), $signed(imm_s_type), rs1);
+        str = $sformatf("cv.%-14s %s, (x%0d), %0d", mnemonic, regAddrToStr(rs2), rs1, $signed(imm_s_type));
       end else if (instr[31:28] == 4'b0010) begin
         if (instr[27] == 1'b0) begin
           // reg-reg post-incremented store
@@ -645,7 +690,7 @@ class instr_trace_t;
           regs_read.push_back('{rs3, rs3_value, 0});
           regs_read.push_back('{rs1, rs1_value, 0});
           regs_write.push_back('{rs1, 'x, 0});
-          str = $sformatf("cv.%-13s %s, %s(x%0d!)", mnemonic, regAddrToStr(rs2), regAddrToStr(rs3), rs1);
+          str = $sformatf("cv.%-13s %s, (x%0d), %s", mnemonic, regAddrToStr(rs2), rs1, regAddrToStr(rs3));
         end else begin
           // reg-reg indexed store
           regs_read.push_back('{rs2, rs2_value, 0});
@@ -757,238 +802,429 @@ class instr_trace_t;
       else str_hb = ".h";
 
       // set mnemonic
-      case (instr[31:26])
-        6'b000000: begin
+      case (instr)
+        INSTR_CVADDH   ,
+        INSTR_CVADDSCH ,
+        INSTR_CVADDSCIH,
+        INSTR_CVADDB   ,
+        INSTR_CVADDSCB ,
+        INSTR_CVADDSCIB : begin
           mnemonic = "cv.add";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000010: begin
+        INSTR_CVSUBH   ,
+        INSTR_CVSUBSCH ,
+        INSTR_CVSUBSCIH,
+        INSTR_CVSUBB   ,
+        INSTR_CVSUBSCB ,
+        INSTR_CVSUBSCIB : begin
           mnemonic = "cv.sub";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000100: begin
+        INSTR_CVAVGH    ,
+        INSTR_CVAVGSCH  ,
+        INSTR_CVAVGSCIH ,
+        INSTR_CVAVGB    ,
+        INSTR_CVAVGSCB  ,
+        INSTR_CVAVGSCIB : begin
           mnemonic = "cv.avg";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000110: begin
+        INSTR_CVAVGUH   ,
+        INSTR_CVAVGUSCH ,
+        INSTR_CVAVGUSCIH,
+        INSTR_CVAVGUB   ,
+        INSTR_CVAVGUSCB ,
+        INSTR_CVAVGUSCIB : begin
           mnemonic = "cv.avgu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b001000: begin
+        INSTR_CVMINH   ,
+        INSTR_CVMINSCH ,
+        INSTR_CVMINSCIH,
+        INSTR_CVMINB   ,
+        INSTR_CVMINSCB ,
+        INSTR_CVMINSCIB : begin
           mnemonic = "cv.min";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001010: begin
+        INSTR_CVMINUH   ,
+        INSTR_CVMINUSCH ,
+        INSTR_CVMINUSCIH,
+        INSTR_CVMINUB   ,
+        INSTR_CVMINUSCB ,
+        INSTR_CVMINUSCIB : begin
           mnemonic = "cv.minu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b001100: begin
+        INSTR_CVMAXH    ,
+        INSTR_CVMAXSCH  ,
+        INSTR_CVMAXSCIH ,
+        INSTR_CVMAXB    ,
+        INSTR_CVMAXSCB  ,
+        INSTR_CVMAXSCIB : begin
           mnemonic = "cv.max";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001110: begin
+        INSTR_CVMAXUH    ,
+        INSTR_CVMAXUSCH  ,
+        INSTR_CVMAXUSCIH ,
+        INSTR_CVMAXUB    ,
+        INSTR_CVMAXUSCB  ,
+        INSTR_CVMAXUSCIB : begin
           mnemonic = "cv.maxu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b010000: begin
+        INSTR_CVSRLH    ,
+        INSTR_CVSRLSCH  ,
+        INSTR_CVSRLSCIH ,
+        INSTR_CVSRLB    ,
+        INSTR_CVSRLSCB  ,
+        INSTR_CVSRLSCIB : begin
           mnemonic = "cv.srl";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b010010: begin
+        INSTR_CVSRAH   ,
+        INSTR_CVSRASCH ,
+        INSTR_CVSRASCIH,
+        INSTR_CVSRAB   ,
+        INSTR_CVSRASCB ,
+        INSTR_CVSRASCIB : begin
           mnemonic = "cv.sra";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b010100: begin
+        INSTR_CVSLLH   ,
+        INSTR_CVSLLSCH ,
+        INSTR_CVSLLSCIH,
+        INSTR_CVSLLB   ,
+        INSTR_CVSLLSCB ,
+        INSTR_CVSLLSCIB : begin
           mnemonic = "cv.sll";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b010110: begin
+        INSTR_CVORH   ,
+        INSTR_CVORSCH ,
+        INSTR_CVORSCIH,
+        INSTR_CVORB   ,
+        INSTR_CVORSCB ,
+        INSTR_CVORSCIB : begin
           mnemonic = "cv.or";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b011000: begin
+        INSTR_CVXORH    ,
+        INSTR_CVXORSCH  ,
+        INSTR_CVXORSCIH ,
+        INSTR_CVXORB    ,
+        INSTR_CVXORSCB  ,
+        INSTR_CVXORSCIB : begin
           mnemonic = "cv.xor";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b011010: begin
+        INSTR_CVANDH    ,
+        INSTR_CVANDSCH  ,
+        INSTR_CVANDSCIH ,
+        INSTR_CVANDB    ,
+        INSTR_CVANDSCB  ,
+        INSTR_CVANDSCIB : begin
           mnemonic = "cv.and";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b011100: begin
+        INSTR_CVABSH,
+        INSTR_CVABSB : begin
           mnemonic = "cv.abs";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
         // dot products
-        6'b100000: begin
+        INSTR_CVDOTUPH   ,
+        INSTR_CVDOTUPSCH ,
+        INSTR_CVDOTUPSCIH,
+        INSTR_CVDOTUPB   ,
+        INSTR_CVDOTUPSCB ,
+        INSTR_CVDOTUPSCIB : begin
           mnemonic = "cv.dotup";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b100010: begin
+        INSTR_CVDOTUSPH   ,
+        INSTR_CVDOTUSPSCH ,
+        INSTR_CVDOTUSPSCIH,
+        INSTR_CVDOTUSPB   ,
+        INSTR_CVDOTUSPSCB ,
+        INSTR_CVDOTUSPSCIB : begin
           mnemonic = "cv.dotusp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b100100: begin
+        INSTR_CVDOTSPH   ,
+        INSTR_CVDOTSPSCH ,
+        INSTR_CVDOTSPSCIH,
+        INSTR_CVDOTSPB   ,
+        INSTR_CVDOTSPSCB ,
+        INSTR_CVDOTSPSCIB : begin
           mnemonic = "cv.dotsp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b100110: begin
+        INSTR_CVSDOTUPH   ,
+        INSTR_CVSDOTUPSCH ,
+        INSTR_CVSDOTUPSCIH,
+        INSTR_CVSDOTUPB   ,
+        INSTR_CVSDOTUPSCB ,
+        INSTR_CVSDOTUPSCIB : begin
           mnemonic = "cv.sdotup";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b101000: begin
+        INSTR_CVSDOTUSPH   ,
+        INSTR_CVSDOTUSPSCH ,
+        INSTR_CVSDOTUSPSCIH,
+        INSTR_CVSDOTUSPB   ,
+        INSTR_CVSDOTUSPSCB ,
+        INSTR_CVSDOTUSPSCIB : begin
           mnemonic = "cv.sdotusp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b101010: begin
+        INSTR_CVSDOTSPH   ,
+        INSTR_CVSDOTSPSCH ,
+        INSTR_CVSDOTSPSCIH,
+        INSTR_CVSDOTSPB   ,
+        INSTR_CVSDOTSPSCB ,
+        INSTR_CVSDOTSPSCIB : begin
           mnemonic = "cv.sdotsp";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
 
-        6'b101110: begin
-          case (instr[14:13])
-            2'b00 : begin
-              mnemonic = "cv.extract";
-              str_imm  = $sformatf("0x%0h", imm_vs_type);
-            end
-            2'b01 : begin
-              mnemonic = "cv.extractu";
-              str_imm  = $sformatf("0x%0h", imm_vu_type);
-            end
-            2'b10 : begin
-              mnemonic = "cv.insert";
-              str_imm  = $sformatf("0x%0h", imm_vs_type);
-            end
-          endcase
-          str_sci  = "";
+        INSTR_CVEXTRACTH,
+        INSTR_CVEXTRACTB : begin
+            mnemonic = "cv.extract";
+            str_imm  = $sformatf("0x%0h", imm_vs_type);
+            str_sci  = "";
+        end
+        INSTR_CVEXTRACTUH,
+        INSTR_CVEXTRACTUB : begin
+            mnemonic = "cv.extractu";
+            str_imm  = $sformatf("0x%0h", imm_vu_type);
+            str_sci  = "";
+        end
+        INSTR_CVINSERTH,
+        INSTR_CVINSERTB : begin
+            mnemonic = "cv.insert";
+            str_imm  = $sformatf("0x%0h", imm_vs_type);
+            str_sci  = "";
         end
 
         // shuffle/pack
-        6'b110000: begin
-          if (instr[14:12] == 3'b111) begin
-            mnemonic = "cv.shuffleI0";
-            str_imm  = $sformatf("0x%8h", imm_shuffle_type);
-          end else begin
+        INSTR_CVSHUFFLEH   ,
+        INSTR_CVSHUFFLESCIH,
+        INSTR_CVSHUFFLEB   : begin
             mnemonic = "cv.shuffle";
             if (instr[14:12] == 3'b110) begin
               str_imm  = $sformatf("0x%8h", imm_shuffle_type);
             end
-          end
         end
-        6'b110010: begin
+
+        INSTR_CVSHUFFLEL0SCIB : begin
+            mnemonic = "cv.shuffleI0";
+            str_imm  = $sformatf("0x%8h", imm_shuffle_type);
+        end
+        INSTR_CVSHUFFLEL1SCIB : begin
           mnemonic = "cv.shuffleI1";
           str_imm  = $sformatf("0x%8h", imm_shuffle_type);
         end
-        6'b110100: begin
+        INSTR_CVSHUFFLEL2SCIB : begin
           mnemonic = "cv.shuffleI2";
           str_imm  = $sformatf("0x%8h", imm_shuffle_type);
         end
-        6'b110110: begin
+        INSTR_CVSHUFFLEL3SCIB : begin
           mnemonic = "cv.shuffleI3";
           str_imm  = $sformatf("0x%8h", imm_shuffle_type);
         end
-        6'b111000: begin
+        INSTR_CVSHUFFLE2H,
+        INSTR_CVSHUFFLE2B : begin
           mnemonic = "cv.shuffle2";
         end
-        6'b111100: begin
+        INSTR_CVPACK,
+        INSTR_CVPACKH : begin
           mnemonic = "cv.pack";
           if (instr[25] == 1'b0) begin
             str_hb = "";
           end
         end
-        6'b111110: begin
-          mnemonic = instr[25] ? "cv.packhi" : "cv.packlo";
-        end
+        INSTR_CVPACKHIB : mnemonic = "cv.packhi";
+        INSTR_CVPACKLOB : mnemonic = "cv.packlo";
 
         // comparisons
-        6'b000001: begin
+        INSTR_CVCMPEQH   ,
+        INSTR_CVCMPEQSCH ,
+        INSTR_CVCMPEQSCIH,
+        INSTR_CVCMPEQB   ,
+        INSTR_CVCMPEQSCB ,
+        INSTR_CVCMPEQSCIB : begin
           mnemonic = "cv.cmpeq";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000011: begin
+        INSTR_CVCMPNEH   ,
+        INSTR_CVCMPNESCH ,
+        INSTR_CVCMPNESCIH,
+        INSTR_CVCMPNEB   ,
+        INSTR_CVCMPNESCB ,
+        INSTR_CVCMPNESCIB : begin
           mnemonic = "cv.cmpne";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000101: begin
+        INSTR_CVCMPGTH   ,
+        INSTR_CVCMPGTSCH ,
+        INSTR_CVCMPGTSCIH,
+        INSTR_CVCMPGTB   ,
+        INSTR_CVCMPGTSCB ,
+        INSTR_CVCMPGTSCIB : begin
           mnemonic = "cv.cmpgt";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b000111: begin
+        INSTR_CVCMPGEH   ,
+        INSTR_CVCMPGESCH ,
+        INSTR_CVCMPGESCIH,
+        INSTR_CVCMPGEB   ,
+        INSTR_CVCMPGESCB ,
+        INSTR_CVCMPGESCIB : begin
           mnemonic = "cv.cmpge";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001001: begin
+        INSTR_CVCMPLTH   ,
+        INSTR_CVCMPLTSCH ,
+        INSTR_CVCMPLTSCIH,
+        INSTR_CVCMPLTB   ,
+        INSTR_CVCMPLTSCB ,
+        INSTR_CVCMPLTSCIB : begin
           mnemonic = "cv.cmplt";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001011: begin
+        INSTR_CVCMPLEH   ,
+        INSTR_CVCMPLESCH ,
+        INSTR_CVCMPLESCIH,
+        INSTR_CVCMPLEB   ,
+        INSTR_CVCMPLESCB ,
+        INSTR_CVCMPLESCIB : begin
           mnemonic = "cv.cmple";
           str_imm  = $sformatf("0x%0h", imm_vs_type);
         end
-        6'b001101: begin
+        INSTR_CVCMPGTUH   ,
+        INSTR_CVCMPGTUSCH ,
+        INSTR_CVCMPGTUSCIH,
+        INSTR_CVCMPGTUB   ,
+        INSTR_CVCMPGTUSCB ,
+        INSTR_CVCMPGTUSCIB : begin
           mnemonic = "cv.cmpgtu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b001111: begin
+        INSTR_CVCMPGEUH   ,
+        INSTR_CVCMPGEUSCH ,
+        INSTR_CVCMPGEUSCIH,
+        INSTR_CVCMPGEUB   ,
+        INSTR_CVCMPGEUSCB ,
+        INSTR_CVCMPGEUSCIB : begin
           mnemonic = "cv.cmpgeu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b010001: begin
+        INSTR_CVCMPLTUH   ,
+        INSTR_CVCMPLTUSCH ,
+        INSTR_CVCMPLTUSCIH,
+        INSTR_CVCMPLTUB   ,
+        INSTR_CVCMPLTUSCB ,
+        INSTR_CVCMPLTUSCIB : begin
           mnemonic = "cv.cmpltu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
-        6'b010011: begin
+        INSTR_CVCMPLEUH   ,
+        INSTR_CVCMPLEUSCH ,
+        INSTR_CVCMPLEUSCIH,
+        INSTR_CVCMPLEUB   ,
+        INSTR_CVCMPLEUSCB ,
+        INSTR_CVCMPLEUSCIB : begin
           mnemonic = "cv.cmpleu";
           str_imm  = $sformatf("0x%0h", imm_vu_type);
         end
 
-        6'b010101: begin
-          unique case (instr[14:13])
-            2'b00: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r"      : "cv.cplxmul.i";
-            2'b01: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div2" : "cv.cplxmul.i.div2";
-            2'b10: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div4" : "cv.cplxmul.i.div4";
-            2'b11: mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div8" : "cv.cplxmul.i.div8";
-          endcase
+        INSTR_CVCPLXMULR,
+        INSTR_CVCPLXMULI : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r"      : "cv.cplxmul.i";
           str_sci = "";
           str_hb = "";
         end
-
-        6'b010111: begin
-          mnemonic = "cv.cplxconj";
-          str_sci  = "";
+        INSTR_CVCPLXMULRDIV2,
+        INSTR_CVCPLXMULIDIV2 : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div2" : "cv.cplxmul.i.div2";
+          str_sci = "";
           str_hb = "";
         end
-
-        6'b011001: begin
-          unique case (instr[14:13])
-            2'b00: mnemonic = "cv.subrotmj";
-            2'b01: mnemonic = "cv.subrotmj.div2";
-            2'b10: mnemonic = "cv.subrotmj.div4";
-            2'b11: mnemonic = "cv.subrotmj.div8";
-          endcase
+        INSTR_CVCPLXMULRDIV4,
+        INSTR_CVCPLXMULIDIV4 : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div4" : "cv.cplxmul.i.div4";
           str_sci = "";
           str_hb = "";
         end
-
-        6'b011011: begin
-          unique case (instr[14:13])
-            2'b01: mnemonic = "cv.add.div2";
-            2'b10: mnemonic = "cv.add.div4";
-            2'b11: mnemonic = "cv.add.div8";
-          endcase
+        INSTR_CVCPLXMULRDIV8,
+        INSTR_CVCPLXMULIDIV8 : begin
+          mnemonic = instr[25] == 1'b0 ? "cv.cplxmul.r.div8" : "cv.cplxmul.i.div8";
           str_sci = "";
           str_hb = "";
         end
 
-        6'b011101: begin
-          unique case (instr[14:13])
-            2'b01: mnemonic = "cv.sub.div2";
-            2'b10: mnemonic = "cv.sub.div4";
-            2'b11: mnemonic = "cv.sub.div8";
-          endcase
-          str_sci = "";
+        INSTR_CVCPLXCONJ : begin
+          mnemonic = "cv.cplxconj";
+          str_sci  = "";
           str_hb = "";
         end
 
+        INSTR_CVSUBROTMJ     : begin
+            mnemonic = "cv.subrotmj";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBROTMJDIV2 : begin
+            mnemonic = "cv.subrotmj.div2";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBROTMJDIV4 : begin
+            mnemonic = "cv.subrotmj.div4";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBROTMJDIV8 : begin
+            mnemonic = "cv.subrotmj.div8";
+            str_sci = "";
+            str_hb = "";
+        end
+
+        INSTR_CVADDIV2 : begin
+            mnemonic = "cv.add.div2";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVADDIV4 : begin
+            mnemonic = "cv.add.div4";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVADDIV8 : begin
+            mnemonic = "cv.add.div8";
+            str_sci = "";
+            str_hb = "";
+        end
+
+        INSTR_CVSUBIV2 : begin
+            mnemonic = "cv.sub.div2";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBIV4 : begin
+            mnemonic = "cv.sub.div4";
+            str_sci = "";
+            str_hb = "";
+        end
+        INSTR_CVSUBIV8 : begin
+            mnemonic = "cv.sub.div8";
+            str_sci = "";
+            str_hb = "";
+        end
+
         default: begin
           printMnemonic("INVALID");
           return;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv
index 13a5beb0..99429d90 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi.sv
@@ -1,24 +1,28 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// CV32E40P RVFI interface
-//
-// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>          //
+//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>     //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  CV32E40P RVFI interface                                          //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
 `include "cv32e40p_rvfi_pkg.sv"
 
@@ -27,7 +31,8 @@ module cv32e40p_rvfi
   import cv32e40p_rvfi_pkg::*;
 #(
     parameter FPU   = 0,
-    parameter ZFINX = 0
+    parameter ZFINX = 0,
+    parameter NUM_MHPMCOUNTERS = 1
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -290,7 +295,7 @@ module cv32e40p_rvfi
     // performance counters
     //  cycle,  instret,  hpcounter,  cycleh,  instreth,  hpcounterh
     // mcycle, minstret, mhpcounter, mcycleh, minstreth, mhpcounterh
-    input logic [31:0][MHPMCOUNTER_WIDTH-1:0] csr_mhpmcounter_q_i,
+    input logic [63:0][MHPMCOUNTER_WIDTH-1:0] csr_mhpmcounter_q_i,
     input logic [31:0]                        csr_mhpmcounter_write_lower_i,
     input logic [31:0]                        csr_mhpmcounter_write_upper_i,
 
@@ -327,6 +332,10 @@ module cv32e40p_rvfi
     // the convention of RISC-V Formal Interface Specification.
     output logic       [ 0:0] rvfi_valid,
     output logic       [63:0] rvfi_order,
+    output integer            rvfi_start_cycle,
+    output time               rvfi_start_time,
+    output integer            rvfi_stop_cycle,
+    output time               rvfi_stop_time,
     output logic       [31:0] rvfi_insn,
     output rvfi_trap_t        rvfi_trap,
     output logic       [ 0:0] rvfi_halt,
@@ -346,6 +355,7 @@ module cv32e40p_rvfi
     output logic        rvfi_frd_wvalid [1:0],
     output logic [ 4:0] rvfi_frd_addr   [1:0],
     output logic [31:0] rvfi_frd_wdata  [1:0],
+    output logic        rvfi_2_rd,
     output logic [ 4:0] rvfi_rs1_addr,
     output logic [ 4:0] rvfi_rs2_addr,
     output logic [ 4:0] rvfi_rs3_addr,
@@ -366,8 +376,8 @@ module cv32e40p_rvfi
     output logic [31:0] rvfi_pc_wdata,
 
     output logic [31:0] rvfi_mem_addr,
-    output logic [ 3:0] rvfi_mem_rmask,
-    output logic [ 3:0] rvfi_mem_wmask,
+    output logic [31:0] rvfi_mem_rmask,
+    output logic [31:0] rvfi_mem_wmask,
     output logic [31:0] rvfi_mem_rdata,
     output logic [31:0] rvfi_mem_wdata,
 
@@ -618,6 +628,13 @@ module cv32e40p_rvfi
   bit clk_i_d;
   assign #0.01 clk_i_d = clk_i;
 
+  integer cycles;
+  // cycle counter
+  always_ff @(posedge clk_i_d, negedge rst_ni) begin
+    if (rst_ni == 1'b0) cycles <= 0;
+    else cycles <= cycles + 1;
+  end
+
   logic pc_mux_debug;
   logic pc_mux_dret;
   logic pc_mux_exception;
@@ -626,6 +643,9 @@ module cv32e40p_rvfi
   logic pc_mux_nmi;
 
   localparam logic [31:0] MSTATUS_WRITE_MASK = 32'h0000_6088;
+  localparam logic [31:0] MCOUNTINHIBIT_WRITE_MASK = {{(29-NUM_MHPMCOUNTERS){1'b0}}, {(NUM_MHPMCOUNTERS){1'b1}}, 3'b101};
+  localparam NUM_HPM_EVENTS = 16;
+  localparam logic [31:0] MHPMEVENT_WRITE_MASK = {{(31-NUM_HPM_EVENTS){1'b0}}, {(NUM_HPM_EVENTS){1'b1}}};
 
   `include "pipe_freeze_trace.sv"
 
@@ -747,6 +767,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     end
 
     rvfi_order       = new_rvfi_trace.m_order;
+    rvfi_start_cycle = new_rvfi_trace.m_start_cycle;
+    rvfi_start_time  = new_rvfi_trace.m_start_time;
+    rvfi_stop_cycle = new_rvfi_trace.m_stop_cycle;
+    rvfi_stop_time  = new_rvfi_trace.m_stop_time;
     rvfi_pc_rdata    = new_rvfi_trace.m_pc_rdata;
     rvfi_insn        = new_rvfi_trace.m_insn;
 
@@ -801,6 +825,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     rvfi_frd_addr[1]   = '0;
     rvfi_frd_wdata[1]  = '0;
 
+    rvfi_2_rd = new_rvfi_trace.m_2_rd_insn;
     if (new_rvfi_trace.m_rd_addr[0][5] == 1'b0) begin
       rvfi_rd_addr[0]  = new_rvfi_trace.m_rd_addr[0][4:0];
       rvfi_rd_wdata[0] = new_rvfi_trace.m_rd_wdata[0];
@@ -905,15 +930,50 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     `SET_RVFI_CSR_FROM_INSN(misa)
     `SET_RVFI_CSR_FROM_INSN(mie)
     `SET_RVFI_CSR_FROM_INSN(mtvec)
-    `SET_RVFI_CSR_FROM_INSN(mcountinhibit)
+
+    rvfi_csr_mcountinhibit_rdata = new_rvfi_trace.m_csr.mcountinhibit_rdata;
+    rvfi_csr_mcountinhibit_rmask = new_rvfi_trace.m_csr.mcountinhibit_rmask;
+    rvfi_csr_mcountinhibit_wdata = new_rvfi_trace.m_csr.mcountinhibit_wdata;
+    rvfi_csr_mcountinhibit_wmask = new_rvfi_trace.m_csr.mcountinhibit_wmask & MCOUNTINHIBIT_WRITE_MASK;
+
     `SET_RVFI_CSR_FROM_INSN(mscratch)
     `SET_RVFI_CSR_FROM_INSN(mepc)
     `SET_RVFI_CSR_FROM_INSN(mcause)
+    `SET_RVFI_CSR_FROM_INSN(mcycle)
     `SET_RVFI_CSR_FROM_INSN(minstret)
+    `SET_RVFI_CSR_FROM_INSN(minstreth)
+
+    // `SET_RVFI_CSR_FROM_INSN(cycle)
+    // `SET_RVFI_CSR_FROM_INSN(instret)
+    rvfi_csr_instret_rdata = new_rvfi_trace.m_csr.minstret_rdata;
+    rvfi_csr_instret_rmask = new_rvfi_trace.m_csr.minstret_rmask;
+    rvfi_csr_instret_wdata = new_rvfi_trace.m_csr.minstret_wdata;
+    rvfi_csr_instret_wmask = new_rvfi_trace.m_csr.minstret_wmask;
+
+    for(int idx=3; idx<32; idx++) begin
+    rvfi_csr_mhpmcounter_rmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_rmask[idx][31:0];
+    rvfi_csr_mhpmcounter_wmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_wmask[idx][31:0];
+    rvfi_csr_mhpmcounter_rdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_rdata[idx][31:0];
+    rvfi_csr_mhpmcounter_wdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_wdata[idx][31:0];
+
+    rvfi_csr_mhpmcounterh_rmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_rmask[idx][63:32];
+    rvfi_csr_mhpmcounterh_wmask[idx] = new_rvfi_trace.m_csr.mhpmcounter_wmask[idx][63:32];
+    rvfi_csr_mhpmcounterh_rdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_rdata[idx][63:32];
+    rvfi_csr_mhpmcounterh_wdata[idx] = new_rvfi_trace.m_csr.mhpmcounter_wdata[idx][63:32];
+
+    rvfi_csr_mhpmevent_rmask[idx] = new_rvfi_trace.m_csr.mhpmevent_rmask[idx];
+    rvfi_csr_mhpmevent_wmask[idx] = new_rvfi_trace.m_csr.mhpmevent_wmask[idx] & MHPMEVENT_WRITE_MASK;
+    rvfi_csr_mhpmevent_rdata[idx] = new_rvfi_trace.m_csr.mhpmevent_rdata[idx];
+    rvfi_csr_mhpmevent_wdata[idx] = new_rvfi_trace.m_csr.mhpmevent_wdata[idx];
+    end
+    // `SET_RVFI_CSR_FROM_INSN(instreth)
+    rvfi_csr_instreth_rdata = new_rvfi_trace.m_csr.minstreth_rdata;
+    rvfi_csr_instreth_rmask = new_rvfi_trace.m_csr.minstreth_rmask;
+    rvfi_csr_instreth_wdata = new_rvfi_trace.m_csr.minstreth_wdata;
+    rvfi_csr_instreth_wmask = new_rvfi_trace.m_csr.minstreth_wmask;
+
     `SET_RVFI_CSR_FROM_INSN(mip)
-    // if(rvfi_order == 64'h00000000_00000167) begin
-    //     rvfi_csr_mip_rdata = 32'h0010_0000;
-    // end
+
     rvfi_csr_tdata_rdata[0] = 'Z;
     rvfi_csr_tdata_rmask[0] = '0;  // Does not exist
     rvfi_csr_tdata_wdata[0] = 'Z;  // Does not exist
@@ -959,36 +1019,134 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
   endfunction  // set_rvfi
 
-  function void minstret_to_id();
-    trace_id.m_csr.minstret_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2];
-    trace_id.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2];
-    trace_id.m_csr.minstret_rmask = '1;
-    trace_id.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q;
-    trace_id.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0;
+  function void sample_perf_counter_to_id(int idx);
+    trace_id.m_csr.mhpmcounter_rdata[idx][31:0] = r_pipe_freeze_trace.csr.mhpmcounter_q[idx][31:0];
+    trace_id.m_csr.mhpmcounter_rmask[idx][31:0] = '1;
+  endfunction
+
+  function void perf_counter_to_id(int idx);
+    if(!trace_id.m_csr.mhpmcounter_we[idx][0]) begin
+      trace_id.m_csr.mhpmcounter_wdata[idx][31:0] = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin
+        trace_id.m_csr.mhpmcounter_we[idx][0]    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx];
+        trace_id.m_csr.mhpmcounter_wdata[idx][31:0] = r_pipe_freeze_trace.csr.wdata_int;
+        trace_id.m_csr.mhpmcounter_wmask[idx][31:0] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx] ? '1 : '0;
+    end
+    sample_perf_counter_to_id(idx);
+  endfunction
+
+  function void sample_perf_event_to_trace(int idx, insn_trace_t m_trace);
+    m_trace.m_csr.mhpmevent_rdata[idx] = r_pipe_freeze_trace.csr.mhpmevent_q[idx];
+    m_trace.m_csr.mhpmevent_rmask[idx] = '1;
+  endfunction
+
+  function void perf_event_to_trace(int idx, insn_trace_t m_trace);
+    if(!m_trace.m_csr.mhpmevent_we[idx]) begin
+      m_trace.m_csr.mhpmevent_wdata[idx] = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmevent_we[idx]) begin
+        m_trace.m_csr.mhpmevent_we[idx]    = r_pipe_freeze_trace.csr.mhpmevent_we[idx];
+        m_trace.m_csr.mhpmevent_wdata[idx] = r_pipe_freeze_trace.csr.wdata_int;
+        m_trace.m_csr.mhpmevent_wmask[idx] = r_pipe_freeze_trace.csr.mhpmevent_we[idx] ? '1 : '0;
+    end
+    sample_perf_event_to_trace(idx, m_trace);
+  endfunction
+
+  function void sample_minstret_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2][31:0];
+    m_trace.m_csr.minstret_rmask = '1;
+  endfunction
+
+  function void minstret_to_trace(insn_trace_t m_trace);
+    if(!m_trace.m_csr.minstret_we) begin
+      m_trace.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]) begin
+        m_trace.m_csr.minstret_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2];
+        m_trace.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.wdata_int;
+        m_trace.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0;
+    end
+    sample_minstret_to_trace(m_trace);
+  endfunction
+
+  function void sample_perf_counter_h_to_id(int idx);
+    trace_id.m_csr.mhpmcounter_rdata[idx][63:32] = r_pipe_freeze_trace.csr.mhpmcounter_q[idx][63:0];
+    trace_id.m_csr.mhpmcounter_rmask[idx][63:32] = '1;
+  endfunction
+
+  function void perf_counter_h_to_id(int idx);
+    if(!trace_id.m_csr.mhpmcounter_we[idx][1]) begin
+      trace_id.m_csr.mhpmcounter_wdata[idx][63:32] = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin
+        trace_id.m_csr.mhpmcounter_we[idx][1]    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx];
+        trace_id.m_csr.mhpmcounter_wdata[idx][63:32] = r_pipe_freeze_trace.csr.wdata_int;
+        trace_id.m_csr.mhpmcounter_wmask[idx][63:32] = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx] ? '1 : '0;
+    end
+    sample_perf_counter_h_to_id(idx);
+  endfunction
+
+  function void sample_minstreth_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.minstreth_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2][63:32];
+    m_trace.m_csr.minstreth_rmask = '1;
   endfunction
 
-  function void minstret_to_ex();
-    trace_ex.m_csr.minstret_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2];
-    trace_ex.m_csr.minstret_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[2];
-    trace_ex.m_csr.minstret_rmask = '1;
-    trace_ex.m_csr.minstret_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q;
-    trace_ex.m_csr.minstret_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2] ? '1 : '0;
+  function void sample_mcycle_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.mcycle_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[0];
+    m_trace.m_csr.mcycle_rdata = r_pipe_freeze_trace.csr.mhpmcounter_q[0][31:0];
+    m_trace.m_csr.mcycle_rmask = '1;
+    m_trace.m_csr.mcycle_wdata = r_pipe_freeze_trace.csr.mhpmcounter_q[31:0];
+    m_trace.m_csr.mcycle_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_lower[0] ? '1 : '0;
   endfunction
 
-  function void tinfo_to_id();
-    trace_id.m_csr.tinfo_we    = '0; // READ ONLY csr_tinfo_we_i;
-    trace_id.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q;
-    trace_id.m_csr.tinfo_rmask = '1;
-    trace_id.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n;
-    trace_id.m_csr.tinfo_wmask = '0;
+  function void minstreth_to_trace(insn_trace_t m_trace);
+    if(!m_trace.m_csr.minstreth_we) begin
+      m_trace.m_csr.minstreth_wdata = r_pipe_freeze_trace.csr.wdata_int;
+    end
+    if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2]) begin
+        m_trace.m_csr.minstreth_we    = r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2];
+        m_trace.m_csr.minstreth_wdata = r_pipe_freeze_trace.csr.wdata_int;
+        m_trace.m_csr.minstreth_wmask = r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2] ? '1 : '0;
+    end
+    sample_minstreth_to_trace(m_trace);
   endfunction
 
-  function void tinfo_to_ex();
-    trace_ex.m_csr.tinfo_we    = '0; // READ ONLY csr_tinfo_we_i;
-    trace_ex.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q;
-    trace_ex.m_csr.tinfo_rmask = '1;
-    trace_ex.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n;
-    trace_ex.m_csr.tinfo_wmask = '0;
+  function void sample_perf_counter_to_trace(insn_trace_t m_trace);
+    sample_minstret_to_trace(m_trace);
+    sample_minstreth_to_trace(m_trace);
+    sample_mcycle_to_trace(m_trace);
+    for(int idx=3; idx<32; idx++)begin
+      sample_perf_event_to_trace(idx, m_trace); //TO CHANGE
+    end
+  endfunction
+
+  function void perf_counter_to_trace(insn_trace_t m_trace);
+      if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[2]) begin
+          minstret_to_trace(m_trace);
+      end
+      if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[2]) begin
+          minstreth_to_trace(m_trace);
+      end
+      for(int idx=3; idx<32; idx++) begin
+          if(r_pipe_freeze_trace.csr.mhpmcounter_write_lower[idx]) begin
+              perf_counter_to_id(idx);
+          end
+          if(r_pipe_freeze_trace.csr.mhpmcounter_write_upper[idx]) begin
+              perf_counter_h_to_id(idx);
+          end
+          if(r_pipe_freeze_trace.csr.mhpmevent_we[idx]) begin
+              perf_event_to_trace(idx, m_trace);
+          end
+      end
+  endfunction
+
+  function void tinfo_to_trace(insn_trace_t m_trace);
+    m_trace.m_csr.tinfo_we    = '0; // READ ONLY csr_tinfo_we_i;
+    m_trace.m_csr.tinfo_rdata = r_pipe_freeze_trace.csr.tinfo_q;
+    m_trace.m_csr.tinfo_rmask = '1;
+    m_trace.m_csr.tinfo_wdata = r_pipe_freeze_trace.csr.tinfo_n;
+    m_trace.m_csr.tinfo_wmask = '0;
   endfunction
 
   function void mtvec_to_id();
@@ -1083,8 +1241,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     lpcount1_to_id();
     lpend1_to_id();
     lpstart1_to_id();
-
-
   endfunction
 
   bit s_was_flush;  //debug exception is flagged as trap only if preceed by a flush
@@ -1257,6 +1413,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           end
         end
         csr_to_apu_resp();
+
+        trace_apu_resp.m_stop_cycle = cycles;
+        trace_apu_resp.m_stop_time = $time;
         send_rvfi(trace_apu_resp);
         ->e_send_rvfi_trace_apu_resp;
       end
@@ -1275,7 +1434,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       `CSR_FROM_PIPE(id, misa)
       `CSR_FROM_PIPE(id, tdata1)
       `CSR_FROM_PIPE(id, tdata2)
-      tinfo_to_id();
+      tinfo_to_trace(trace_id);
       `CSR_FROM_PIPE(id, mip)
       send_rvfi(trace_id);
     end
@@ -1291,15 +1450,28 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
   function logic [31:0] be_to_mask(logic [3:0] be);
     logic [31:0] mask;
-    mask[7:0]   = be[0] ? 8'hFF : 8'h00;
-    mask[15:8]  = be[0] ? 8'hFF : 8'h00;
-    mask[23:16] = be[0] ? 8'hFF : 8'h00;
-    mask[31:24] = be[0] ? 8'hFF : 8'h00;
+    mask[7:0]   = (be[0] == 1'b1) ? 8'hFF : 8'h00;
+    mask[15:8]  = (be[1] == 1'b1) ? 8'hFF : 8'h00;
+    mask[23:16] = (be[2] == 1'b1) ? 8'hFF : 8'h00;
+    mask[31:24] = (be[3] == 1'b1) ? 8'hFF : 8'h00;
 
     be_to_mask  = mask;
     return mask;
   endfunction
 
+  function void commit_rf_to_trace(insn_trace_t m_trace);
+    if (m_trace.m_got_ex_reg) begin
+        m_trace.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
+        m_trace.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
+        m_trace.m_2_rd_insn = 1'b1;
+        m_trace.m_got_first_data = 1'b1;
+    end else begin
+        m_trace.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
+        m_trace.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
+        m_trace.m_got_first_data = 1'b1;
+    end
+  endfunction
+
   task compute_pipeline();
     bit s_new_valid_insn;
     bit s_ex_valid_adjusted;
@@ -1375,7 +1547,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           `CSR_FROM_PIPE(id, misa)
           `CSR_FROM_PIPE(id, tdata1)
           `CSR_FROM_PIPE(id, tdata2)
-          tinfo_to_id();
+          tinfo_to_trace(trace_id);
           `CSR_FROM_PIPE(id, mip)
         end
       end
@@ -1409,7 +1581,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       if (trace_ex.m_valid & s_wb_valid_adjusted) begin
         // Used flopped values in case write happened before wb_valid
-        minstret_to_ex();
+        sample_perf_counter_to_trace(trace_ex);
         trace_ex.m_csr.got_minstret = '1;
       end
 
@@ -1486,14 +1658,14 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       if (trace_ex.m_valid) begin
         if(trace_ex.m_instret_smaple_trigger == 1) begin //time to sample instret
-          minstret_to_ex();
+          sample_perf_counter_to_trace(trace_ex);
         end
         trace_ex.m_instret_smaple_trigger = trace_ex.m_instret_smaple_trigger + 1;
 
         `CSR_FROM_PIPE(ex, misa)
         `CSR_FROM_PIPE(ex, tdata1)
         `CSR_FROM_PIPE(ex, tdata2)
-        tinfo_to_ex();
+        tinfo_to_trace(trace_ex);
 
         if (s_rf_we_wb_adjusted) begin
           ->e_dev_commit_rf_to_ex_4;
@@ -1519,18 +1691,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
             if (s_rf_we_wb_adjusted) begin
               ->e_dev_commit_rf_to_ex_1;
-              if (trace_ex.m_got_ex_reg) begin
-                trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
-                trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
-                trace_ex.m_2_rd_insn = 1'b1;
-                trace_ex.m_got_first_data = 1'b1;
-              end else begin
-                trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
-                trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-                trace_ex.m_got_first_data = 1'b1;
-              end
+              commit_rf_to_trace(trace_ex);
 
-              if (r_pipe_freeze_trace.csr.fregs_we && !r_pipe_freeze_trace.apu_rvalid) begin //Catching mstatus_fs updates caused by flw
+              if (r_pipe_freeze_trace.csr.fregs_we && (r_pipe_freeze_trace.rf_we_wb && r_pipe_freeze_trace.rf_addr_wb[5])) begin //Catching mstatus_fs updates caused by flw
                 `CSR_FROM_PIPE(ex, mstatus_fs)
                 trace_ex.m_csr.mstatus_fs_we = 1'b1;
                 trace_ex.m_csr.mstatus_fs_wmask = '1;
@@ -1559,16 +1722,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           end
         end else if (s_rf_we_wb_adjusted && !s_was_flush) begin
           ->e_dev_commit_rf_to_ex_2;
-          if (trace_ex.m_got_ex_reg) begin
-            trace_ex.m_rd_addr[1] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_ex.m_rd_wdata[1] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_ex.m_2_rd_insn = 1'b1;
-            trace_ex.m_got_first_data = 1'b1;
-          end else begin
-            trace_ex.m_rd_addr[0] = r_pipe_freeze_trace.rf_addr_wb;
-            trace_ex.m_rd_wdata[0] = r_pipe_freeze_trace.rf_wdata_wb;
-            trace_ex.m_got_first_data = 1'b1;
-          end
+          commit_rf_to_trace(trace_ex);
         end
       end
 
@@ -1578,7 +1732,12 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
 
       if (trace_id.m_valid) begin
         if(trace_id.m_instret_smaple_trigger == 1) begin //time to sample instret
-          minstret_to_id();
+          sample_perf_counter_to_trace(trace_id);
+          for(int idx=3; idx<32; idx++) begin
+              sample_perf_counter_to_id(idx);
+              sample_perf_counter_h_to_id(idx);
+              sample_perf_event_to_trace(idx, trace_id);
+          end
         end
         trace_id.m_instret_smaple_trigger = trace_id.m_instret_smaple_trigger + 1;
 
@@ -1594,6 +1753,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
           if(r_pipe_freeze_trace.csr.we && (r_pipe_freeze_trace.csr.addr == CSR_DPC)) begin
             `CSR_FROM_PIPE(id, dpc)
           end
+
+          `CSR_FROM_PIPE(id, mcountinhibit)
+
+          perf_counter_to_trace(trace_id);
           ->e_csr_in_ex;
         end
 
@@ -1634,7 +1797,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         trace_ex.m_csr.fcsr_wmask   = '0;
 
         if(r_pipe_freeze_trace.ctrl_fsm_cs == XRET_JUMP) begin //xret exit pipeline
-            tinfo_to_id();
+            tinfo_to_trace(trace_id);
             `CSR_FROM_PIPE(id, tdata1)
             `CSR_FROM_PIPE(id, tdata2)
             send_rvfi(trace_id);
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi_trace.sv
index 417f562a..adf85175 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_rvfi_trace.sv
@@ -1,26 +1,31 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// CV32E40P RVFI interface
-//
-// Contributors: Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>     //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  CV32E40P RVFI tracer                                             //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
 module cv32e40p_rvfi_trace
   import cv32e40p_pkg::*;
+  import cv32e40p_rvfi_pkg::*;
 #(
     parameter FPU   = 0,
     parameter ZFINX = 0
@@ -32,9 +37,14 @@ module cv32e40p_rvfi_trace
 
     input logic [31:0] imm_s3_type,
 
-    input logic        rvfi_valid,
-    input logic [31:0] rvfi_insn,
-    input logic [31:0] rvfi_pc_rdata,
+    input logic              rvfi_valid,
+    input logic       [31:0] rvfi_insn,
+    input integer            rvfi_start_cycle,
+    input time               rvfi_start_time,
+    input integer            rvfi_stop_cycle,
+    input time               rvfi_stop_time,
+    input logic       [31:0] rvfi_pc_rdata,
+    input rvfi_trap_t        rvfi_trap,
 
     input logic [ 4:0] rvfi_rd_addr [1:0],
     input logic [31:0] rvfi_rd_wdata[1:0],
@@ -42,6 +52,7 @@ module cv32e40p_rvfi_trace
     input logic        rvfi_frd_wvalid[1:0],
     input logic [ 4:0] rvfi_frd_addr  [1:0],
     input logic [31:0] rvfi_frd_wdata [1:0],
+    input logic        rvfi_2_rd,
 
     input logic [ 4:0] rvfi_rs1_addr,
     input logic [ 4:0] rvfi_rs2_addr,
@@ -61,8 +72,8 @@ module cv32e40p_rvfi_trace
     input logic [31:0] rvfi_frs3_rdata,
 
     input logic [31:0] rvfi_mem_addr,
-    input logic [ 3:0] rvfi_mem_rmask,
-    input logic [ 3:0] rvfi_mem_wmask,
+    input logic [31:0] rvfi_mem_rmask,
+    input logic [31:0] rvfi_mem_wmask,
     input logic [31:0] rvfi_mem_rdata,
     input logic [31:0] rvfi_mem_wdata
 );
@@ -74,7 +85,7 @@ module cv32e40p_rvfi_trace
 
   integer f;  //file pointer
   string fn;
-  integer cycles;
+  // integer cycles;
   string info_tag;
 
   logic is_compressed;
@@ -125,7 +136,13 @@ module cv32e40p_rvfi_trace
       rs3_value = rvfi_rs3_rdata;
     end
 
-    if (rvfi_frd_wvalid[0]) begin
+    if (rvfi_2_rd) begin
+      if (rvfi_frd_wvalid[1]) begin
+        rd = {1'b1, rvfi_frd_addr[1]};
+      end else begin
+        rd = {1'b0, rvfi_rd_addr[1]};
+      end
+    end else if (rvfi_frd_wvalid[0]) begin
       rd = {1'b1, rvfi_frd_addr[0]};
     end else begin
       rd = {1'b0, rvfi_rd_addr[0]};
@@ -134,57 +151,69 @@ module cv32e40p_rvfi_trace
 
   assign rs4 = rs3;
 
-  assign imm_i_type = {{20{rvfi_insn[31]}}, rvfi_insn[31:20]};
-  assign imm_iz_type = {20'b0, rvfi_insn[31:20]};
-  assign imm_s_type = {{20{rvfi_insn[31]}}, rvfi_insn[31:25], rvfi_insn[11:7]};
+  cv32e40p_compressed_decoder #(
+      .FPU(FPU)
+  ) rvfi_trace_decompress_i (
+      .instr_i(rvfi_insn),
+      .instr_o(decomp_insn),
+      .is_compressed_o(is_compressed)
+  );
+
+  assign imm_i_type = {{20{decomp_insn[31]}}, decomp_insn[31:20]};
+  assign imm_iz_type = {20'b0, decomp_insn[31:20]};
+  assign imm_s_type = {{20{decomp_insn[31]}}, decomp_insn[31:25], decomp_insn[11:7]};
   assign imm_sb_type = {
-    {19{rvfi_insn[31]}}, rvfi_insn[31], rvfi_insn[7], rvfi_insn[30:25], rvfi_insn[11:8], 1'b0
+    {19{decomp_insn[31]}},
+    decomp_insn[31],
+    decomp_insn[7],
+    decomp_insn[30:25],
+    decomp_insn[11:8],
+    1'b0
   };
-  assign imm_u_type = {rvfi_insn[31:12], 12'b0};
+  assign imm_u_type = {decomp_insn[31:12], 12'b0};
   assign imm_uj_type = {
-    {12{rvfi_insn[31]}}, rvfi_insn[19:12], rvfi_insn[20], rvfi_insn[30:21], 1'b0
+    {12{decomp_insn[31]}}, decomp_insn[19:12], decomp_insn[20], decomp_insn[30:21], 1'b0
   };
 
-  assign imm_z_type = '0;  //{27'b0, rvfi_insn[REG_S1_MSB:REG_S1_LSB]};
+  assign imm_z_type = '0;  //{27'b0, decomp_insn[REG_S1_MSB:REG_S1_LSB]};
 
-  assign imm_s2_type = {27'b0, rvfi_insn[24:20]};
+  assign imm_s2_type = {27'b0, decomp_insn[24:20]};
   assign imm_vs_type = '0;
   assign imm_vu_type = '0;
   assign imm_shuffle_type = '0;
   assign imm_clip_type = '0;
 
-  cv32e40p_compressed_decoder #(
-      .FPU(FPU)
-  ) rvfi_trace_decompress_i (
-      .instr_i(rvfi_insn),
-      .instr_o(decomp_insn),
-      .is_compressed_o(is_compressed)
-  );
-
   `include "cv32e40p_instr_trace.svh"
 instr_trace_t trace_retire;
 
   function instr_trace_t trace_new_instr();
     instr_trace_t trace;
     trace = new();
-    trace.init(.cycles(cycles), .pc(rvfi_pc_rdata), .compressed(is_compressed),
+    trace.external_time = 1;
+    trace.simtime = rvfi_start_time - 1ns;
+    trace.stoptime = rvfi_stop_time;
+    trace.stopcycles = rvfi_stop_cycle;
+    trace.ctx = (rvfi_trap.trap) ? "(C)" : "";
+    trace.init(.cycles(rvfi_start_cycle), .pc(rvfi_pc_rdata), .compressed(is_compressed),
                .instr(decomp_insn));
     return trace;
   endfunction : trace_new_instr
 
   function void apply_reg_write();
     foreach (trace_retire.regs_write[i]) begin
-      if (rvfi_frd_wvalid[0] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[0]})) begin
-        trace_retire.regs_write[i].value = rvfi_frd_wdata[0];
-      end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin
-        trace_retire.regs_write[i].value = rvfi_rd_wdata[0];
-      end
       if (rvfi_frd_wvalid[1] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[1]})) begin
         trace_retire.regs_write[i].value = rvfi_frd_wdata[1];
       end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[1]) begin
         trace_retire.regs_write[i].value = rvfi_rd_wdata[1];
       end
     end
+    foreach (trace_retire.regs_write[i]) begin
+      if (rvfi_frd_wvalid[0] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[0]})) begin
+        trace_retire.regs_write[i].value = rvfi_frd_wdata[0];
+      end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin
+        trace_retire.regs_write[i].value = rvfi_rd_wdata[0];
+      end
+    end
   endfunction : apply_reg_write
 
   function void apply_mem_access();
@@ -202,11 +231,9 @@ instr_trace_t trace_retire;
     end
   endfunction : apply_mem_access
 
-  // cycle counter
-  always_ff @(posedge clk_i, negedge rst_ni) begin
-    if (rst_ni == 1'b0) cycles <= 0;
-    else cycles <= cycles + 1;
-  end
+  string        insn_disas;
+  logic  [31:0] insn_pc;
+  logic  [31:0] insn_val;
 
   always @(posedge clk_i) begin
     if (rvfi_valid) begin
@@ -214,6 +241,9 @@ instr_trace_t trace_retire;
       apply_reg_write();
       apply_mem_access();
       trace_retire.printInstrTrace();
+      insn_disas = trace_retire.str;
+      insn_pc    = trace_retire.pc;
+      insn_val   = trace_retire.instr;
     end
   end
 
@@ -223,7 +253,8 @@ instr_trace_t trace_retire;
     $sformat(info_tag, "CORE_TRACER %2d", hart_id_i);
     $display("[%s] Output filename is: %s", info_tag, fn);
     f = $fopen(fn, "w");
-    $fwrite(f, "Time\tCycle\tPC\tInstr\tDecoded instruction\tRegister and memory contents\n");
+    $fwrite(f,
+            "            Time           Cycle PC       Instr    Ctx Decoded instruction Register and memory contents                                 Stop cycle  Stop time\n");
   end
 
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv
index ca703682..25245407 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tb_wrapper.sv
@@ -1,23 +1,27 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// Wrapper for a cv32e40p, containing cv32e40p_top, and rvfi_tracer
-//
-// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>          //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Test-bench wrapper for cv32e40p_top, tracer and and rvfi_tracer  //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
 `ifdef CV32E40P_ASSERT_ON
 `include "cv32e40p_prefetch_controller_sva.sv"
@@ -234,8 +238,9 @@ module cv32e40p_tb_wrapper
   endgenerate
 
   cv32e40p_rvfi #(
-      .FPU  (FPU),
-      .ZFINX(ZFINX)
+      .FPU(FPU),
+      .ZFINX(ZFINX),
+      .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
   ) rvfi_i (
       .clk_i (cv32e40p_top_i.core_i.clk_i),
       .rst_ni(cv32e40p_top_i.core_i.rst_ni),
@@ -399,6 +404,9 @@ module cv32e40p_tb_wrapper
       .csr_mcountinhibit_n_i (cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_n),
       .csr_mcountinhibit_we_i(cv32e40p_top_i.core_i.cs_registers_i.mcountinhibit_we),
 
+      .csr_mhpmevent_n_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmevent_n),
+      .csr_mhpmevent_q_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmevent_q),
+      .csr_mhpmevent_we_i(cv32e40p_top_i.core_i.cs_registers_i.mhpmevent_we),
       .csr_mscratch_q_i(cv32e40p_top_i.core_i.cs_registers_i.mscratch_q),
       .csr_mscratch_n_i(cv32e40p_top_i.core_i.cs_registers_i.mscratch_n),
       .csr_mepc_q_i(cv32e40p_top_i.core_i.cs_registers_i.mepc_q),
@@ -454,12 +462,18 @@ module cv32e40p_tb_wrapper
 
       .rvfi_valid(rvfi_valid),
       .rvfi_insn(rvfi_insn),
+      .rvfi_start_cycle(rvfi_start_cycle),
+      .rvfi_start_time(rvfi_start_time),
+      .rvfi_stop_cycle(rvfi_stop_cycle),
+      .rvfi_stop_time(rvfi_stop_time),
       .rvfi_pc_rdata(rvfi_pc_rdata),
+      .rvfi_trap(rvfi_trap),
       .rvfi_rd_addr(rvfi_rd_addr),
       .rvfi_rd_wdata(rvfi_rd_wdata),
       .rvfi_frd_wvalid(rvfi_frd_wvalid),
       .rvfi_frd_addr(rvfi_frd_addr),
       .rvfi_frd_wdata(rvfi_frd_wdata),
+      .rvfi_2_rd(rvfi_2_rd),
       .rvfi_rs1_addr(rvfi_rs1_addr),
       .rvfi_rs2_addr(rvfi_rs2_addr),
       .rvfi_rs3_addr(rvfi_rs3_addr),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tracer.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tracer.sv
index 8208f2e6..59ed6fd7 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tracer.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/cv32e40p_tracer.sv
@@ -1,24 +1,26 @@
-// Copyright (c) 2020 OpenHW Group
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-
-// Traces the executed instructions
-//
-// Contributors: Andreas Traber, ETHZ <atraber@iis.ee.ethz.ch>
-//               Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+////////////////////////////////////////////////////////////////////////////////
+// Engineer:       Andreas Traber - atraber@iis.ee.ethz.ch                    //
+//                                                                            //
+// Additional contributions by:                                               //
+//                 Davide Schiavone - pschiavo@iis.ee.ethz.ch                 //
+//                                                                            //
+// Design Name:    RISC-V Tracer                                              //
+// Project Name:   RI5CY                                                      //
+// Language:       SystemVerilog                                              //
+//                                                                            //
+// Description:    Traces the executed instructions                           //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
 
 `ifdef CV32E40P_TRACE_EXECUTION
 
@@ -183,7 +185,8 @@ module cv32e40p_tracer
     $sformat(info_tag, "CORE_TRACER %2d", hart_id_i);
     $display("[%s] Output filename is: %s", info_tag, fn);
     f = $fopen(fn, "w");
-    $fwrite(f, "Time\tCycle\tPC\tInstr\tDecoded instruction\tRegister and memory contents\n");
+    $fwrite(f,
+            "            Time           Cycle PC       Instr    Ctx Decoded instruction Register and memory contents\n");
   end
 
   //initial begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_rvfi_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_rvfi_pkg.sv
index 68879569..f4044e6e 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_rvfi_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_rvfi_pkg.sv
@@ -1,24 +1,28 @@
-// Copyright (c) 2020 OpenHW Group
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// Includes to print info about the RVFI output
-//
-// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>
-//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
-//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Davide Schiavone, OpenHW Group <davide@openhwgroup.org>          //
+//               Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>     //
+//               Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Package to print info on RVFI interface                          //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
 package cv32e40p_rvfi_pkg;
   import cv32e40p_pkg::*;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv
index d026c4aa..b9ce57df 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/include/cv32e40p_tracer_pkg.sv
@@ -1,23 +1,13 @@
-// Copyright (c) 2020 OpenHW Group
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-
-// Tracer package
-//
-// Contributors: Steve Richmond, Silicon Labs <steve.richmond@silabs.com>
-//               Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
 
 package cv32e40p_tracer_pkg;
   import cv32e40p_pkg::*;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv
index 71cbaaff..8cdc06d9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/insn_trace.sv
@@ -1,5 +1,26 @@
-// Copyright 2022 Dolphin Design
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+// Copyright 2024 OpenHW Group and Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
+// You may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Macros and Functions to print information on RVFI interface      //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
   `define DEFINE_CSR(CSR_NAME) \
     logic ``CSR_NAME``_we; \
@@ -23,6 +44,10 @@
   class insn_trace_t;
     bit m_valid;
     logic [63:0] m_order;
+    integer      m_start_cycle;
+    integer      m_stop_cycle;
+    time         m_start_time;
+    time         m_stop_time;
     bit          m_skip_order; //next order was used by trap;
     logic [31:0] m_pc_rdata;
     logic [31:0] m_insn;
@@ -71,9 +96,9 @@
 
     struct {
       logic [31:0] addr ;
-      logic [ 3:0] rmask;
+      logic [31:0] rmask;
       logic [31:0] rdata;
-      logic [ 3:0] wmask;
+      logic [31:0] wmask;
       logic [31:0] wdata;
     } m_mem;
 
@@ -103,9 +128,28 @@
       `DEFINE_CSR(mscratch)
       `DEFINE_CSR(mepc)
       `DEFINE_CSR(mcause)
+      `DEFINE_CSR(mcycle)
       `DEFINE_CSR(minstret)
       bit got_minstret;
-
+      `DEFINE_CSR(mcycleh)
+      `DEFINE_CSR(minstreth)
+      `DEFINE_CSR(cycle)
+      `DEFINE_CSR(instret)
+      // bit got_minstret;
+      `DEFINE_CSR(cycleh)
+      `DEFINE_CSR(instreth)
+
+      logic [31:0][ 1:0]    mhpmcounter_we;
+      logic [31:0][63:0] mhpmcounter_rdata;
+      logic [31:0][63:0] mhpmcounter_rmask;
+      logic [31:0][63:0] mhpmcounter_wdata;
+      logic [31:0][63:0] mhpmcounter_wmask;
+
+      logic [31:0]          mhpmevent_we;
+      logic [31:0][31:0] mhpmevent_rdata;
+      logic [31:0][31:0] mhpmevent_rmask;
+      logic [31:0][31:0] mhpmevent_wdata;
+      logic [31:0][31:0] mhpmevent_wmask;
       `DEFINE_CSR(mip)
       //mnxti
       //mintstatus
@@ -149,6 +193,10 @@
 
     function new();
       this.m_order                  = 0;
+      this.m_start_cycle            = 0;
+      this.m_stop_cycle             = 0;
+      this.m_start_time             = 0;
+      this.m_stop_time              = 0;
       this.m_skip_order             = 1'b0;
       this.m_valid                  = 1'b0;
       this.m_move_down_pipe         = 1'b0;
@@ -615,12 +663,12 @@
           INSTR_CVCMPLEB     : this.m_mnemonic = "cv.cmple.b";
           INSTR_CVCMPLESCB   : this.m_mnemonic = "cv.cmple.sc.b";
           INSTR_CVCMPLESCIB  : this.m_mnemonic = "cv.cmple.sci.b";
-          INSTR_CVCMPGTUH    : this.m_mnemonic = "cv.cmptu.h";
-          INSTR_CVCMPGTUSCH  : this.m_mnemonic = "cv.cmptu.sc.h";
-          INSTR_CVCMPGTUSCIH : this.m_mnemonic = "cv.cmptu.sci.h";
-          INSTR_CVCMPGTUB    : this.m_mnemonic = "cv.cmptu.b";
-          INSTR_CVCMPGTUSCB  : this.m_mnemonic = "cv.cmptu.sc.b";
-          INSTR_CVCMPGTUSCIB : this.m_mnemonic = "cv.cmptu.sci.b";
+          INSTR_CVCMPGTUH    : this.m_mnemonic = "cv.cmpgtu.h";
+          INSTR_CVCMPGTUSCH  : this.m_mnemonic = "cv.cmpgtu.sc.h";
+          INSTR_CVCMPGTUSCIH : this.m_mnemonic = "cv.cmpgtu.sci.h";
+          INSTR_CVCMPGTUB    : this.m_mnemonic = "cv.cmpgtu.b";
+          INSTR_CVCMPGTUSCB  : this.m_mnemonic = "cv.cmpgtu.sc.b";
+          INSTR_CVCMPGTUSCIB : this.m_mnemonic = "cv.cmpgtu.sci.b";
           INSTR_CVCMPGEUH    : this.m_mnemonic = "cv.cmpgeu.h";
           INSTR_CVCMPGEUSCH  : this.m_mnemonic = "cv.cmpgeu.sc.h";
           INSTR_CVCMPGEUSCIH : this.m_mnemonic = "cv.cmpgeu.sci.h";
@@ -849,7 +897,18 @@
       `INIT_CSR(mscratch)
       `INIT_CSR(mepc)
       `INIT_CSR(mcause)
+      `INIT_CSR(mcycle)
       `INIT_CSR(minstret)
+      `INIT_CSR(mcycleh)
+      `INIT_CSR(minstreth)
+      `INIT_CSR(cycle)
+      `INIT_CSR(instret)
+      `INIT_CSR(cycleh)
+      `INIT_CSR(instreth)
+      this.m_csr.mhpmcounter_we = '0;
+      this.m_csr.mhpmcounter_wmask = '0;
+      this.m_csr.mhpmevent_we = '0;
+      this.m_csr.mhpmevent_wmask = '0;
       `INIT_CSR(mip)
       `INIT_CSR(tdata1)
       `INIT_CSR(tdata2)
@@ -877,6 +936,10 @@
       this.m_valid            = 1'b1;
       this.m_stage            = ID;
       this.m_order            = this.m_order + 64'h1;
+      this.m_start_cycle      = cycles;
+      this.m_stop_cycle       = 0;
+      this.m_start_time       = $time;
+      this.m_stop_time        = 0;
       if(this.m_skip_order) begin
         this.m_order            = this.m_order + 64'h1;
       end
@@ -954,6 +1017,10 @@
       this.m_valid                  = m_source.m_valid;
       this.m_stage                  = m_source.m_stage;
       this.m_order                  = m_source.m_order;
+      this.m_start_cycle            = m_source.m_start_cycle;
+      this.m_stop_cycle             = m_source.m_stop_cycle;
+      this.m_start_time             = m_source.m_start_time;
+      this.m_stop_time              = m_source.m_stop_time;
       this.m_pc_rdata               = m_source.m_pc_rdata;
       this.m_insn                   = m_source.m_insn;
       this.m_mnemonic               = m_source.m_mnemonic;
@@ -1004,8 +1071,26 @@
       `ASSIGN_CSR(mscratch)
       `ASSIGN_CSR(mepc)
       `ASSIGN_CSR(mcause)
+      `ASSIGN_CSR(mcycle)
       `ASSIGN_CSR(minstret)
       this.m_csr.got_minstret = m_source.m_csr.got_minstret;
+      `ASSIGN_CSR(mcycleh)
+      `ASSIGN_CSR(minstreth)
+      `ASSIGN_CSR(cycle)
+      `ASSIGN_CSR(instret)
+      // this.m_csr.got_minstret = m_source.m_csr.got_minstret;
+      `ASSIGN_CSR(cycleh)
+      `ASSIGN_CSR(instreth)
+      this.m_csr.mhpmcounter_we = m_source.m_csr.mhpmcounter_we;
+      this.m_csr.mhpmcounter_rdata = m_source.m_csr.mhpmcounter_rdata;
+      this.m_csr.mhpmcounter_rmask = m_source.m_csr.mhpmcounter_rmask;
+      this.m_csr.mhpmcounter_wdata = m_source.m_csr.mhpmcounter_wdata;
+      this.m_csr.mhpmcounter_wmask = m_source.m_csr.mhpmcounter_wmask;
+      this.m_csr.mhpmevent_we = m_source.m_csr.mhpmevent_we;
+      this.m_csr.mhpmevent_rdata = m_source.m_csr.mhpmevent_rdata;
+      this.m_csr.mhpmevent_rmask = m_source.m_csr.mhpmevent_rmask;
+      this.m_csr.mhpmevent_wdata = m_source.m_csr.mhpmevent_wdata;
+      this.m_csr.mhpmevent_wmask = m_source.m_csr.mhpmevent_wmask;
       `ASSIGN_CSR(mip)
       `ASSIGN_CSR(tdata1)
       `ASSIGN_CSR(tdata2)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv
index 88d65d0b..39a16fa6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/bhv/pipe_freeze_trace.sv
@@ -1,27 +1,29 @@
-// Copyright (c) 2023 OpenHW Group
+// Copyright 2024 OpenHW Group and Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
 // You may obtain a copy of the License at
 //
-// https://solderpad.org/licenses/
+// https://solderpad.org/licenses/SHL-2.1/
 //
-// Unless required by applicable law or agreed to in writing, software
+// Unless required by applicable law or agreed to in writing, any work
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
 
-// CV32E40P
-//
-// Contributors: Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>
+////////////////////////////////////////////////////////////////////////////////////
+//                                                                                //
+// Contributors: Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>         //
+//                                                                                //
+// Description:  Structures, Functions and Task used to store all information     //
+//               coming from the core pipeline at every posedge.                  //
+//               Those information will then be processed by RVFI.                //
+//                                                                                //
+////////////////////////////////////////////////////////////////////////////////////
 
-/*
-   * This struct is used to store all information comming from the core at every posedge
-   * The information will then be processed
-   */
 typedef struct {
   logic is_decoding;
   logic is_illegal;
@@ -349,6 +351,7 @@ function compute_csr_we();
   r_pipe_freeze_trace.csr.fflags_we     = 1'b0;
   r_pipe_freeze_trace.csr.frm_we        = 1'b0;
   r_pipe_freeze_trace.csr.fcsr_we       = 1'b0;
+  r_pipe_freeze_trace.csr.mhpmevent_we  = '0;
   r_pipe_freeze_trace.csr.dpc_we        = csr_dpc_we_i;
   if (r_pipe_freeze_trace.csr.we) begin
     case (r_pipe_freeze_trace.csr.addr)
@@ -366,7 +369,10 @@ function compute_csr_we();
         r_pipe_freeze_trace.csr.fflags_we = 1'b1;
         r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
       end
-      CSR_FRM:       r_pipe_freeze_trace.csr.frm_we = 1'b1;
+      CSR_FRM: begin
+        r_pipe_freeze_trace.csr.frm_we = 1'b1;
+        r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
+      end
       CSR_FCSR: begin
         r_pipe_freeze_trace.csr.fcsr_we = 1'b1;
         r_pipe_freeze_trace.csr.mstatus_fs_we = 1'b1;
@@ -376,6 +382,10 @@ function compute_csr_we();
       CSR_DSCRATCH1: r_pipe_freeze_trace.csr.dscratch1_we = 1'b1;
     endcase
   end
+
+  if (csr_mhpmevent_we_i) begin
+    r_pipe_freeze_trace.csr.mhpmevent_we[r_pipe_freeze_trace.csr.addr[4:0]] = 1'b1;
+  end
   // CSR_MCAUSE:   r_pipe_freeze_trace.csr.mcause_we = r_pipe_freeze_trace.csr.mcause_n != r_pipe_freeze_trace.csr.mcause_q; //for debug purpose
 endfunction
 /*
@@ -573,7 +583,6 @@ task monitor_pipeline();
     r_pipe_freeze_trace.csr.mcountinhibit_we = csr_mcountinhibit_we_i;
     r_pipe_freeze_trace.csr.mhpmevent_n = csr_mhpmevent_n_i;
     r_pipe_freeze_trace.csr.mhpmevent_q = csr_mhpmevent_q_i;
-    r_pipe_freeze_trace.csr.mhpmevent_we = csr_mhpmevent_we_i;
     r_pipe_freeze_trace.csr.mscratch_n = csr_mscratch_n_i;
     r_pipe_freeze_trace.csr.mscratch_q = csr_mscratch_q_i;
     r_pipe_freeze_trace.csr.mepc_n = csr_mepc_n_i;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv
index a41e345d..d1c86d6c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_controller.sv
@@ -597,7 +597,17 @@ module cv32e40p_controller import cv32e40p_pkg::*;
 
                     csr_status_i: begin
                       halt_if_o     = 1'b1;
-                      ctrl_fsm_ns   = id_ready_i ? FLUSH_EX : DECODE;
+                      if (~id_ready_i) begin
+                        ctrl_fsm_ns = DECODE;
+                      end else begin
+                        ctrl_fsm_ns = FLUSH_EX;
+                        if (hwlp_end0_eq_pc) begin
+                          hwlp_dec_cnt_o[0] = 1'b1;
+                        end
+                        if (hwlp_end1_eq_pc) begin
+                          hwlp_dec_cnt_o[1] = 1'b1;
+                        end
+                      end
                     end
 
                     data_load_event_i: begin
@@ -617,7 +627,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
                         ctrl_fsm_ns  = hwlp_end0_eq_pc_plus4 || hwlp_end1_eq_pc_plus4 ? DECODE : DECODE_HWLOOP;
 
                         // we can be at the end of HWloop due to a return from interrupt or ecall or ebreak or exceptions
-                        if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin
+                        if (hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin
                           pc_mux_o         = PC_HWLOOP;
                           if (~jump_done_q) begin
                             pc_set_o          = 1'b1;
@@ -791,7 +801,17 @@ module cv32e40p_controller import cv32e40p_pkg::*;
 
                     csr_status_i: begin
                       halt_if_o     = 1'b1;
-                      ctrl_fsm_ns   = id_ready_i ? FLUSH_EX : DECODE_HWLOOP;
+                      if (~id_ready_i) begin
+                        ctrl_fsm_ns = DECODE_HWLOOP;
+                      end else begin
+                        ctrl_fsm_ns = FLUSH_EX;
+                        if (hwlp_end0_eq_pc) begin
+                          hwlp_dec_cnt_o[0] = 1'b1;
+                        end
+                        if (hwlp_end1_eq_pc) begin
+                          hwlp_dec_cnt_o[1] = 1'b1;
+                        end
+                      end
                     end
 
                     data_load_event_i: begin
@@ -1067,16 +1087,10 @@ module cv32e40p_controller import cv32e40p_pkg::*;
               end
 
               csr_status_i: begin
-
-                if(hwlp_end0_eq_pc && hwlp_counter0_gt_1) begin
-                    pc_mux_o         = PC_HWLOOP;
-                    pc_set_o          = 1'b1;
-                    hwlp_dec_cnt_o[0] = 1'b1;
-              end
-                if(hwlp_end1_eq_pc && hwlp_counter1_gt_1) begin
-                    pc_mux_o         = PC_HWLOOP;
-                    pc_set_o          = 1'b1;
-                    hwlp_dec_cnt_o[1] = 1'b1;
+                if ((hwlp_end0_eq_pc && !hwlp_counter0_eq_0) ||
+                    (hwlp_end1_eq_pc && !hwlp_counter1_eq_0)) begin
+                  pc_mux_o = PC_HWLOOP;
+                  pc_set_o = 1'b1;
                 end
               end
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv
index d72fae9e..4275cf9c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_core.sv
@@ -70,7 +70,8 @@ module cv32e40p_core
     output logic [31:0] data_wdata_o,
     input  logic [31:0] data_rdata_i,
 
-    // apu-interconnect
+    // CVFPU interface
+    output logic                              apu_busy_o,
     // handshake signals
     output logic                              apu_req_o,
     input  logic                              apu_gnt_i,
@@ -163,7 +164,6 @@ module cv32e40p_core
   logic               ctrl_busy;
   logic               if_busy;
   logic               lsu_busy;
-  logic               apu_busy;
 
   logic        [31:0] pc_ex;  // PC of last executed branch or cv.elw
 
@@ -399,7 +399,7 @@ module cv32e40p_core
       .if_busy_i  (if_busy),
       .ctrl_busy_i(ctrl_busy),
       .lsu_busy_i (lsu_busy),
-      .apu_busy_i (apu_busy),
+      .apu_busy_i (apu_busy_o),
 
       // PULP cluster
       .pulp_clock_en_i       (pulp_clock_en_i),
@@ -634,7 +634,7 @@ module cv32e40p_core
       .apu_write_regs_valid_o (apu_write_regs_valid),
       .apu_write_dep_i        (apu_write_dep),
       .apu_perf_dep_o         (perf_apu_dep),
-      .apu_busy_i             (apu_busy),
+      .apu_busy_i             (apu_busy_o),
 
       // CSR ID/EX
       .csr_access_ex_o      (csr_access_ex),
@@ -818,9 +818,9 @@ module cv32e40p_core
       .apu_perf_cont_o(perf_apu_cont),
       .apu_perf_wb_o  (perf_apu_wb),
       .apu_ready_wb_o (apu_ready_wb),
-      .apu_busy_o     (apu_busy),
+      .apu_busy_o     (apu_busy_o),
 
-      // apu-interconnect
+      // CVFPU interface
       // handshake signals
       .apu_req_o     (apu_req_o),
       .apu_gnt_i     (apu_gnt_i),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_decoder.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_decoder.sv
index d03027ba..c1608eb4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_decoder.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_decoder.sv
@@ -1057,7 +1057,6 @@ module cv32e40p_decoder
             5'b00000: begin
               fpu_op             = cv32e40p_fpu_pkg::ADD;
               fp_op_group        = ADDMUL;
-              apu_op_o           = 2'b0;
               alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD;
               alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD;
             end
@@ -1066,7 +1065,6 @@ module cv32e40p_decoder
               fpu_op             = cv32e40p_fpu_pkg::ADD;
               fpu_op_mod         = 1'b1;
               fp_op_group        = ADDMUL;
-              apu_op_o           = 2'b1;
               alu_op_b_mux_sel_o = OP_B_REGA_OR_FWD;
               alu_op_c_mux_sel_o = OP_C_REGB_OR_FWD;
             end
@@ -1085,7 +1083,6 @@ module cv32e40p_decoder
               regb_used_o = 1'b0;
               fpu_op      = cv32e40p_fpu_pkg::SQRT;
               fp_op_group = DIVSQRT;
-              apu_op_o    = 1'b1;
               // rs2 must be zero
               if (instr_rdata_i[24:20] != 5'b00000) illegal_insn_o = 1'b1;
             end
@@ -1213,7 +1210,6 @@ module cv32e40p_decoder
               fpu_op      = cv32e40p_fpu_pkg::F2I;
               fp_op_group = CONV;
               fpu_op_mod  = instr_rdata_i[20]; // signed/unsigned switch
-              apu_op_o    = 2'b1;
 
               unique case (instr_rdata_i[26:25]) //fix for casting to different formats other than FP32
                 2'b00: begin
@@ -1249,7 +1245,6 @@ module cv32e40p_decoder
               fpu_op      = cv32e40p_fpu_pkg::I2F;
               fp_op_group = CONV;
               fpu_op_mod  = instr_rdata_i[20]; // signed/unsigned switch
-              apu_op_o    = 2'b0;
               // bits [21:20] used, other bits must be 0
               if (instr_rdata_i[24:21]) illegal_insn_o = 1'b1;   // in RV32, no casts to L allowed.
             end
@@ -1323,20 +1318,20 @@ module cv32e40p_decoder
           // check rounding mode
           if (check_fprm) begin
             unique case (instr_rdata_i[14:12]) inside
-              [3'b000:3'b100]: ; //legal rounding modes
+              3'b000, 3'b001, 3'b010, 3'b011, 3'b100: ; //legal rounding modes
               3'b101: begin      // Alternative Half-Precsision encded as fmt=10 and rm=101
                 if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40p_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1;
                 // actual rounding mode from frm csr
                 unique case (frm_i) inside
-                  [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
-                  default         : illegal_insn_o = 1'b1;
+                  3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
+                  default                                : illegal_insn_o = 1'b1;
                 endcase
               end
               3'b111: begin
                 // rounding mode from frm csr
                 unique case (frm_i) inside
-                  [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
-                  default         : illegal_insn_o = 1'b1;
+                  3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
+                  default                                : illegal_insn_o = 1'b1;
                 endcase
               end
               default : illegal_insn_o = 1'b1;
@@ -1364,6 +1359,7 @@ module cv32e40p_decoder
             NONCOMP : apu_lat_o = (FPU_OTHERS_LAT<2) ? FPU_OTHERS_LAT+1 : 2'h3;
             // CONV uses the same latency for all formats
             CONV    : apu_lat_o = (FPU_OTHERS_LAT<2) ? FPU_OTHERS_LAT+1 : 2'h3;
+            default: ;
           endcase
 
           // Set FPnew OP and OPMOD as the APU op
@@ -1425,25 +1421,21 @@ module cv32e40p_decoder
           unique case (instr_rdata_i[6:0])
             // fmadd.fmt - FP Fused multiply-add
             OPCODE_OP_FMADD : begin
-              fpu_op      = cv32e40p_fpu_pkg::FMADD;
-              apu_op_o    = 2'b00;
+              fpu_op     = cv32e40p_fpu_pkg::FMADD;
             end
             // fmsub.fmt - FP Fused multiply-subtract
             OPCODE_OP_FMSUB : begin
-              fpu_op      = cv32e40p_fpu_pkg::FMADD;
-              fpu_op_mod  = 1'b1;
-              apu_op_o    = 2'b01;
+              fpu_op     = cv32e40p_fpu_pkg::FMADD;
+              fpu_op_mod = 1'b1;
             end
             // fnmsub.fmt - FP Negated fused multiply-subtract
             OPCODE_OP_FNMSUB : begin
-              fpu_op      = cv32e40p_fpu_pkg::FNMSUB;
-              apu_op_o    = 2'b10;
+              fpu_op     = cv32e40p_fpu_pkg::FNMSUB;
             end
             // fnmadd.fmt - FP Negated fused multiply-add
             OPCODE_OP_FNMADD : begin
-              fpu_op      = cv32e40p_fpu_pkg::FNMSUB;
-              fpu_op_mod  = 1'b1;
-              apu_op_o    = 2'b11;
+              fpu_op     = cv32e40p_fpu_pkg::FNMSUB;
+              fpu_op_mod = 1'b1;
             end
             default : ;
           endcase
@@ -1459,19 +1451,19 @@ module cv32e40p_decoder
 
           // check rounding mode
           unique case (instr_rdata_i[14:12]) inside
-            [3'b000:3'b100]: ; //legal rounding modes
+            3'b000, 3'b001, 3'b010, 3'b011, 3'b100: ; //legal rounding modes
             3'b101: begin      // Alternative Half-Precsision encded as fmt=10 and rm=101
               if (~C_XF16ALT || fpu_dst_fmt_o != cv32e40p_fpu_pkg::FP16ALT) illegal_insn_o = 1'b1;
               // actual rounding mode from frm csr
               unique case (frm_i) inside
-                [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
+                3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
                 default         : illegal_insn_o = 1'b1;
               endcase
             end
             3'b111: begin
               // rounding mode from frm csr
               unique case (frm_i) inside
-                [3'b000:3'b100] : fp_rnd_mode_o = frm_i; //legal rounding modes
+                3'b000, 3'b001, 3'b010, 3'b011, 3'b100 : fp_rnd_mode_o = frm_i; //legal rounding modes
                 default         : illegal_insn_o = 1'b1;
               endcase
             end
@@ -1493,6 +1485,7 @@ module cv32e40p_decoder
 
           // Set FPnew OP and OPMOD as the APU op
           apu_op_o = {fpu_vec_op, fpu_op_mod, fpu_op};
+
         // No FPU or (ZFINX == 0 && MSTATUS.FS == FS_OFF)
         end else begin
           illegal_insn_o = 1'b1;
@@ -1900,15 +1893,14 @@ module cv32e40p_decoder
                   alu_op_b_mux_sel_o    = OP_B_REGA_OR_FWD;
 
                   unique case (instr_rdata_i[27:25])
-                    3'b000: alu_operator_o = ALU_ADD;                  // cv.addNr
-                    3'b001: alu_operator_o = ALU_ADDU;                 // cv.adduNr
-                    3'b010: alu_operator_o = ALU_ADDR;                 // cv.addRNr
-                    3'b011: alu_operator_o = ALU_ADDUR;                // cv.adduRNr
-                    3'b100: alu_operator_o = ALU_SUB;                  // cv.subNr
-                    3'b101: alu_operator_o = ALU_SUBU;                 // cv.subuNr
-                    3'b110: alu_operator_o = ALU_SUBR;                 // cv.subRNr
-                    3'b111: alu_operator_o = ALU_SUBUR;                // cv.subuRNr
-                    default: alu_operator_o = ALU_ADD;
+                    3'b001:  alu_operator_o = ALU_ADDU;                 // cv.adduNr
+                    3'b010:  alu_operator_o = ALU_ADDR;                 // cv.addRNr
+                    3'b011:  alu_operator_o = ALU_ADDUR;                // cv.adduRNr
+                    3'b100:  alu_operator_o = ALU_SUB;                  // cv.subNr
+                    3'b101:  alu_operator_o = ALU_SUBU;                 // cv.subuNr
+                    3'b110:  alu_operator_o = ALU_SUBR;                 // cv.subRNr
+                    3'b111:  alu_operator_o = ALU_SUBUR;                // cv.subuRNr
+                    default: alu_operator_o = ALU_ADD;                  // cv.addNr
                   endcase
                 end
 
@@ -2085,7 +2077,6 @@ module cv32e40p_decoder
 
               // decide between using unsigned and rounding, and combinations
               unique case ({instr_rdata_i[31:30], instr_rdata_i[12]})
-                {2'b00, 1'b0}: alu_operator_o = ALU_ADD;                   // cv.addN
                 {2'b01, 1'b0}: alu_operator_o = ALU_ADDU;                  // cv.adduN
                 {2'b10, 1'b0}: alu_operator_o = ALU_ADDR;                  // cv.addRN
                 {2'b11, 1'b0}: alu_operator_o = ALU_ADDUR;                 // cv.adduRN
@@ -2093,12 +2084,12 @@ module cv32e40p_decoder
                 {2'b01, 1'b1}: alu_operator_o = ALU_SUBU;                  // cv.subuN
                 {2'b10, 1'b1}: alu_operator_o = ALU_SUBR;                  // cv.subRN
                 {2'b11, 1'b1}: alu_operator_o = ALU_SUBUR;                 // cv.subuRN
-                default      : alu_operator_o = ALU_ADD;
+                default      : alu_operator_o = ALU_ADD;                   // cv.addN
               endcase
 
             end
 
-            2'b10, 2'b11: begin
+            default: begin
               // MUL/MAC with subword selection
               alu_en             = 1'b0;
               mult_int_en        = 1'b1;
@@ -2126,7 +2117,6 @@ module cv32e40p_decoder
                 mult_operator_o = MUL_I;
               end
             end
-            default: illegal_insn_o = 1'b1;
           endcase
         end else begin
           illegal_insn_o = 1'b1;
@@ -2267,6 +2257,11 @@ module cv32e40p_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restrictions
+              if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) ||
+                  (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b01001_0: begin // cv.sra
               alu_operator_o = ALU_SRA;
@@ -2278,6 +2273,11 @@ module cv32e40p_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restrictions
+              if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) ||
+                  (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b01010_0: begin // cv.sll
               alu_operator_o = ALU_SLL;
@@ -2289,6 +2289,11 @@ module cv32e40p_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restrictions
+              if ((instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:23] != 2'b0) ||
+                  (instr_rdata_i[14:12] == 3'b111 && instr_rdata_i[24:22] != 3'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b01011_0: begin // cv.or
               alu_operator_o = ALU_OR;
@@ -2425,6 +2430,11 @@ module cv32e40p_decoder
                 end
                 default: illegal_insn_o = 1'b1;
               endcase
+              // Imm6 restrictions
+              if ((instr_rdata_i[12] == 1'b0 && instr_rdata_i[24:20] != 5'b0) ||
+                  (instr_rdata_i[12] == 1'b1 && instr_rdata_i[24:21] != 4'b0)) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b11000_0: begin // cv.shuffle, cv.shuffleI0
               alu_operator_o       = ALU_SHUF;
@@ -2439,6 +2449,10 @@ module cv32e40p_decoder
                   instr_rdata_i[25] != 1'b0) begin
                 illegal_insn_o = 1'b1;
               end
+              // Imm6 restriction
+              if (instr_rdata_i[14:12] == 3'b110 && instr_rdata_i[24:21] != 4'b0) begin
+                illegal_insn_o = 1'b1;
+              end
             end
             6'b11001_0,
             6'b11010_0,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv
index 62ec46c2..839d58aa 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_fp_wrapper.sv
@@ -14,7 +14,7 @@
 module cv32e40p_fp_wrapper
   import cv32e40p_apu_core_pkg::*;
 #(
-    parameter FPU_ADDMUL_LAT = 0,  // Floating-Point ADDition/MULtiplication computing lane pipeline registers number
+    parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number
     parameter FPU_OTHERS_LAT = 0  // Floating-Point COMParison/CONVersion computing lanes pipeline registers number
 ) (
     // Clock and Reset
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv
index 93bb1380..f323cbe5 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_id_stage.sv
@@ -1514,9 +1514,13 @@ module cv32e40p_id_stage
       if (id_valid_o) begin  // unstall the whole pipeline
         alu_en_ex_o <= alu_en;
         if (alu_en) begin
-          alu_operator_ex_o   <= alu_operator;
-          alu_operand_a_ex_o  <= alu_operand_a;
-          alu_operand_b_ex_o  <= alu_operand_b;
+          alu_operator_ex_o  <= alu_operator;
+          alu_operand_a_ex_o <= alu_operand_a;
+          if (alu_op_b_mux_sel == OP_B_REGB_OR_FWD && (alu_operator == ALU_CLIP || alu_operator == ALU_CLIPU)) begin
+            alu_operand_b_ex_o <= {1'b0, alu_operand_b[30:0]};
+          end else begin
+            alu_operand_b_ex_o <= alu_operand_b;
+          end
           alu_operand_c_ex_o  <= alu_operand_c;
           bmask_a_ex_o        <= bmask_a_id;
           bmask_b_ex_o        <= bmask_b_id;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_load_store_unit.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_load_store_unit.sv
index 7c08ffe1..f9c4db4a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_load_store_unit.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_load_store_unit.sv
@@ -121,18 +121,18 @@ module cv32e40p_load_store_unit #(
       2'b00: begin  // Writing a word
         if (misaligned_st == 1'b0) begin  // non-misaligned case
           case (data_addr_int[1:0])
-            2'b00: data_be = 4'b1111;
-            2'b01: data_be = 4'b1110;
-            2'b10: data_be = 4'b1100;
-            2'b11: data_be = 4'b1000;
+            2'b00:   data_be = 4'b1111;
+            2'b01:   data_be = 4'b1110;
+            2'b10:   data_be = 4'b1100;
+            default: data_be = 4'b1000;
           endcase
           ;  // case (data_addr_int[1:0])
         end else begin  // misaligned case
           case (data_addr_int[1:0])
-            2'b00: data_be = 4'b0000;  // this is not used, but included for completeness
-            2'b01: data_be = 4'b0001;
-            2'b10: data_be = 4'b0011;
-            2'b11: data_be = 4'b0111;
+            2'b01:   data_be = 4'b0001;
+            2'b10:   data_be = 4'b0011;
+            2'b11:   data_be = 4'b0111;
+            default: data_be = 4'b0000;  // this is not used, but included for completeness
           endcase
           ;  // case (data_addr_int[1:0])
         end
@@ -141,10 +141,10 @@ module cv32e40p_load_store_unit #(
       2'b01: begin  // Writing a half word
         if (misaligned_st == 1'b0) begin  // non-misaligned case
           case (data_addr_int[1:0])
-            2'b00: data_be = 4'b0011;
-            2'b01: data_be = 4'b0110;
-            2'b10: data_be = 4'b1100;
-            2'b11: data_be = 4'b1000;
+            2'b00:   data_be = 4'b0011;
+            2'b01:   data_be = 4'b0110;
+            2'b10:   data_be = 4'b1100;
+            default: data_be = 4'b1000;
           endcase
           ;  // case (data_addr_int[1:0])
         end else begin  // misaligned case
@@ -154,10 +154,10 @@ module cv32e40p_load_store_unit #(
 
       2'b10, 2'b11: begin  // Writing a byte
         case (data_addr_int[1:0])
-          2'b00: data_be = 4'b0001;
-          2'b01: data_be = 4'b0010;
-          2'b10: data_be = 4'b0100;
-          2'b11: data_be = 4'b1000;
+          2'b00:   data_be = 4'b0001;
+          2'b01:   data_be = 4'b0010;
+          2'b10:   data_be = 4'b0100;
+          default: data_be = 4'b1000;
         endcase
         ;  // case (data_addr_int[1:0])
       end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_register_file_latch.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_register_file_latch.sv
index d8e2f4aa..57383e6a 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_register_file_latch.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_register_file_latch.sv
@@ -172,8 +172,8 @@ module cv32e40p_register_file #(
     mem[0] = '0;
 
     for (k = 1; k < NUM_WORDS; k++) begin : w_WordIter
-      if (~rst_n) mem[k] = '0;
-      else if (mem_clocks[k] == 1'b1) mem[k] = waddr_onehot_b_q[k] ? wdata_b_q : wdata_a_q;
+      if (~rst_n) mem[k] <= '0;
+      else if (mem_clocks[k] == 1'b1) mem[k] <= waddr_onehot_b_q[k] ? wdata_b_q : wdata_a_q;
     end
   end
 
@@ -182,9 +182,9 @@ module cv32e40p_register_file #(
     always_latch begin : latch_wdata_fp
       if (FPU == 1) begin
         for (l = 0; l < NUM_FP_WORDS; l++) begin : w_WordIter
-          if (~rst_n) mem_fp[l] = '0;
+          if (~rst_n) mem_fp[l] <= '0;
           else if (mem_clocks[l+NUM_WORDS] == 1'b1)
-            mem_fp[l] = waddr_onehot_b_q[l+NUM_WORDS] ? wdata_b_q : wdata_a_q;
+            mem_fp[l] <= waddr_onehot_b_q[l+NUM_WORDS] ? wdata_b_q : wdata_a_q;
         end
       end
     end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_top.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_top.sv
index 7ddd2d5a..43eee77b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_top.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cv32e40p/rtl/cv32e40p_top.sv
@@ -1,15 +1,27 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-// Top file instantiating a CV32E40P core and an optional FPU
-// Contributor: Davide Schiavone <davide@openhwgroup.org>
+// Copyright 2024 Dolphin Design
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the "License");
+// you may not use this file except in compliance with the License, or,
+// at your option, the Apache License version 2.0.
+// You may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/////////////////////////////////////////////////////////////////////////////
+//                                                                         //
+// Contributors: Pascal Gouedo, Dolphin Design <pascal.gouedo@dolphin.fr>  //
+//                                                                         //
+// Description:  Top level module of CV32E40P instantiating the Core and   //
+//               an optional CVFPU with its clock gating cell.             //
+//                                                                         //
+/////////////////////////////////////////////////////////////////////////////
 
 module cv32e40p_top #(
     parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw)
@@ -70,7 +82,7 @@ module cv32e40p_top #(
   import cv32e40p_apu_core_pkg::*;
 
   // Core to FPU
-  logic                              clk;
+  logic                              apu_busy;
   logic                              apu_req;
   logic [   APU_NARGS_CPU-1:0][31:0] apu_operands;
   logic [     APU_WOP_CPU-1:0]       apu_op;
@@ -82,6 +94,8 @@ module cv32e40p_top #(
   logic [                31:0]       apu_rdata;
   logic [APU_NUSFLAGS_CPU-1:0]       apu_rflags;
 
+  logic apu_clk_en, apu_clk;
+
   // Instantiate the Core
   cv32e40p_core #(
       .COREV_PULP      (COREV_PULP),
@@ -119,6 +133,7 @@ module cv32e40p_top #(
       .data_wdata_o (data_wdata_o),
       .data_rdata_i (data_rdata_i),
 
+      .apu_busy_o    (apu_busy),
       .apu_req_o     (apu_req),
       .apu_gnt_i     (apu_gnt),
       .apu_operands_o(apu_operands),
@@ -143,12 +158,15 @@ module cv32e40p_top #(
 
   generate
     if (FPU) begin : fpu_gen
+
+      assign apu_clk_en = apu_req | apu_busy;
+
       // FPU clock gate
       cv32e40p_clock_gate core_clock_gate_i (
           .clk_i       (clk_i),
-          .en_i        (!core_sleep_o),
+          .en_i        (apu_clk_en),
           .scan_cg_en_i(scan_cg_en_i),
-          .clk_o       (clk)
+          .clk_o       (apu_clk)
       );
 
       // Instantiate the FPU wrapper
@@ -156,7 +174,7 @@ module cv32e40p_top #(
           .FPU_ADDMUL_LAT(FPU_ADDMUL_LAT),
           .FPU_OTHERS_LAT(FPU_OTHERS_LAT)
       ) fp_wrapper_i (
-          .clk_i         (clk),
+          .clk_i         (apu_clk),
           .rst_ni        (rst_ni),
           .apu_req_i     (apu_req),
           .apu_gnt_o     (apu_gnt),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson
index a9251111..fc70c877 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/openhwgroup/cve2.git
-    rev: f5b21e71c9b511477b04ef81d1292858c51ac20c
+    rev: 7f3bb9fcb28e55b227c966734d8e81ddef58b7e3
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson
index d398c1eb..28cb1df6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/openhwgroup_cve2.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/openhwgroup/cve2.git",
-    rev: "f5b21e71c9b511477b04ef81d1292858c51ac20c",
+    rev: "7f3bb9fcb28e55b227c966734d8e81ddef58b7e3",
   },
 
   patch_dir: "patches/openhwgroup_cv32e20",
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_riscv_dbg/fix_nrharts.patch b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_riscv_dbg/fix_nrharts.patch
new file mode 100644
index 00000000..ea96dec8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/patches/pulp_platform_riscv_dbg/fix_nrharts.patch
@@ -0,0 +1,28 @@
+diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv
+index 59d1c90..2338028 100644
+--- a/src/dm_csrs.sv
++++ b/src/dm_csrs.sv
+@@ -547,7 +547,7 @@ module dm_csrs #(
+     if (!dmcontrol_q.resumereq && dmcontrol_d.resumereq) begin
+       clear_resumeack_o = 1'b1;
+     end
+-    if (dmcontrol_q.resumereq && resumeack_i) begin
++    if (dmcontrol_q.resumereq && resumeack_i[selected_hart]) begin
+       dmcontrol_d.resumereq = 1'b0;
+     end
+     // static values for dcsr
+diff --git a/src/dm_mem.sv b/src/dm_mem.sv
+index 9ff3c86..8f97bec 100755
+--- a/src/dm_mem.sv
++++ b/src/dm_mem.sv
+@@ -535,8 +535,8 @@ module dm_mem #(
+ 
+   always_ff @(posedge clk_i or negedge rst_ni) begin
+     if (!rst_ni) begin
+-      halted_q   <= 1'b0;
+-      resuming_q <= 1'b0;
++        halted_q   <= '0;
++        resuming_q <= '0;
+     end else begin
+       halted_q   <= SelectableHarts & halted_d;
+       resuming_q <= SelectableHarts & resuming_d;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson
index 1c13cb43..9b0fb8b9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg.vendor.hjson
@@ -10,6 +10,8 @@
     rev: "358f90110220adf7a083f8b65d157e836d706236",
   },
 
+  patch_dir: "patches/pulp_platform_riscv_dbg",
+
   exclude_from_upstream: [
     "ci",
     "tb",
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv
index 59d1c90a..23380289 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_csrs.sv
@@ -547,7 +547,7 @@ module dm_csrs #(
     if (!dmcontrol_q.resumereq && dmcontrol_d.resumereq) begin
       clear_resumeack_o = 1'b1;
     end
-    if (dmcontrol_q.resumereq && resumeack_i) begin
+    if (dmcontrol_q.resumereq && resumeack_i[selected_hart]) begin
       dmcontrol_d.resumereq = 1'b0;
     end
     // static values for dcsr
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv
index 9ff3c86a..8f97bec7 100755
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_riscv_dbg/src/dm_mem.sv
@@ -535,8 +535,8 @@ module dm_mem #(
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
-      halted_q   <= 1'b0;
-      resuming_q <= 1'b0;
+        halted_q   <= '0;
+        resuming_q <= '0;
     end else begin
       halted_q   <= SelectableHarts & halted_d;
       resuming_q <= SelectableHarts & resuming_d;
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40px.vlt b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40px.vlt
index a6665860..f2eebf7b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40px.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/cv32e40px.vlt
@@ -114,3 +114,6 @@ lint_off -rule WIDTH -file "*/rtl/cv32e40px_decoder.sv" -match "Logical operator
 lint_off -rule WIDTH -file "*/rtl/cv32e40px_controller.sv" -match "Logical operator LOGAND expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*"
 lint_off -rule WIDTH -file "*/rtl/cv32e40px_cs_registers.sv" -match "Logical operator LOGOR expects 1 bit on the LHS, but LHS's VARREF 'FPU' generates 32 bits.*"
 lint_off -rule LATCH -file "*/rtl/cv32e40px_id_stage.sv" -match "Latch inferred for signal*apu_read_regs*"
+lint_off -rule WIDTH -file "*/rtl/cv32e40px_register_file_ff.sv" -match "Logical operator COND expects 1 bit on the Conditional Test*"
+lint_off -rule WIDTH -file "*/rtl/cv32e40px_decoder.sv" -match "Logical operator LOGNOT expects 1 bit on the LHS*"
+lint_off -rule WIDTH -file "*/rtl/cv32e40px_ex_stage.sv" -match "Logical operator LOGNOT expects 1 bit on the LHS*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt
index 6a33f058..2d2888d2 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/waiver/lint/riscv_dbg.vlt
@@ -12,3 +12,4 @@ lint_off -rule DECLFILENAME -file "*/src/cdc_fifo_gray_clearable.sv" -match "Fil
 lint_off -rule WIDTH -file "*/src/cdc_2phase_clearable.sv" -match "Logical operator GENIF expects 1 bit on the If, but If's VARREF 'CLEAR_ON_ASYNC_RESET' generates 32 bits.*"
 lint_off -rule UNOPTFLAT -file "*/src/cdc_4phase.sv" -match "Signal unoptimizable*"
 lint_off -rule WIDTH -file "*/src/dm_mem.sv" -match "*"
+lint_off -rule CMPCONST -file "*/src/dm_csrs.sv" -match "*"
diff --git a/hw/vendor/esl_epfl_x_heep/logo/x-heep.png b/hw/vendor/esl_epfl_x_heep/logo/x-heep.png
deleted file mode 100644
index 76814a075c16d37d0cb10d1c779a9b498d1f6a94..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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zd*SYj;$r=Q3_;0csLQ99oNONT3g0@@7>f?O{AdC>+8ud!B)!<$pDq>f(yDBlvku{!
zzs*WwV)6fu%9uj{dusHHBtmc7YONT#9b{hTmM(Jii^qcl(SLSFJN-AS7)Zl*Yuawe
zTJ&5FYPefhzK@)~1m_K;ofgXqlV834fbL)EH{-uz9Z&vuhL!`!8F&)`-`m<N>E}l)
z)WAS!nUb}*1?7LYcKrVTKf%E8|9bGO$(2?rIa-}n&vI+HrD+2ccHg%+Fi-+BzMQbt
z+hhD+ww%^=4v2p`neJI4Cvj%$PJTU}zPDB8;DC!00z3WeLs@(X|Cy@uR0Yl@*)Ytp
zHB{T!$-DwFeNFU7rV%6M)O!4XPl}w(`79So4T{9}88<CBH+uiO4oKwpNwzjIiK2rO
zD19h}=^>W|Hm<4TtxUAgfTdLo!<J#m2t#zfEnG$N4T@R_yASzGvx1E%FMPIHm)WL;
zD&00kcU}Jc{7enC|NPOxe<vdCF_z4twgWm((?9P(*o?+A3O{2KIKyU7F#Ah#C^j3N
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zR4}B0J#dnMS|k$dO%pF{oh^&WO)4d8)DsjNdAcw~C@>CFmW>!QF00c=K{HqtM8M~>
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zl&!XcQFqv<;5+aDetncy2pcfo_cdbU-!6Ln-@|h3zoZ_*T@bd}2fE*_saRV8L(-EU
z^=fBg?SBDb=ho4jiSU}{ciMRQ5R+C+8RDC8_s<K4U)9ALIesA84_&0ShFY_L9SvG)
zc#L`8)<)&&o=;_r%hGIA+<?~#iY-rJx~KL=5^j=PsFFUA+xL376xGMliw3WAQ>nSK
ht&3?_gl~x2UCA-to^|*y*d`aHt*M92KW+2Z{{c@{&I14d

diff --git a/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson b/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
index f1d435df..df55d160 100644
--- a/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
+++ b/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
@@ -7,26 +7,7 @@
 
     cpu_type: cv32e20
 
-    bus_type: onetoM
-
-    ram: {
-        address: 0x00000000, #only tried with 0, cannot be changed for now
-        numbanks: 2, #each bank is 32kB, cannot be changed for now
-        numbanks_interleaved: 0,
-    },
-
     linker_script: {
-        #value used for the on-chip linker script, the on-flash linker script is generated using FLASH values and the whole RAM values
-        onchip_ls: {
-            code: {
-                address: 0x00000000,
-                lenght: 0x00000C800, #minimum size for freeRTOS and clang
-            }
-            data: {
-                address: 0x00000C800,
-                lenght: whatisleft, #keyword used to calculate the size as: ram.length - code.lenght
-            }
-        },
         stack_size: 0x800,
         heap_size: 0x800,
     }
@@ -56,10 +37,12 @@
             offset:  0x00028000,
             length:  0x00008000,
         },
-        spi_host: {
+        dma: {
             offset:  0x00030000,
             length:  0x00010000,
-            path:    "./hw/vendor/lowrisc_opentitan_spi_host/data/spi_host.hjson"
+            ch_length:    0x100,
+            num_channels:   0x1,
+            path:    "./hw/ip/dma/data/dma.hjson"
         },
         power_manager: {
             offset:  0x00040000,
@@ -70,30 +53,25 @@
             offset:  0x00050000,
             length:  0x00010000,
         },
-        dma: {
-            offset:  0x00060000,
-            length:  0x00010000,
-            path:    "./hw/ip/dma/data/dma.hjson"
-        },
         fast_intr_ctrl: {
-            offset:  0x00070000,
+            offset:  0x00060000,
             length:  0x00010000,
             path:    "./hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson"
         },
         ext_peripheral: {
-            offset:  0x00080000,
+            offset:  0x00070000,
             length:  0x00010000,
         },
         pad_control: {
-            offset:  0x00090000,
+            offset:  0x00080000,
             length:  0x00010000,
         },
         gpio_ao: {
-            offset:  0x000A0000,
+            offset:  0x00090000,
             length:  0x00010000,
         },
         uart: {
-            offset:  0x000B0000,
+            offset:  0x000A0000,
             length:  0x00010000,
             path:    "./hw/vendor/lowrisc_opentitan/hw/ip/uart/data/uart.hjson"
         },
@@ -108,6 +86,12 @@
             is_included: "yes",
             path:    "./hw/vendor/lowrisc_opentitan/hw/ip/rv_plic/data/rv_plic.hjson"
         },
+        spi_host: {
+            offset:  0x00010000,
+            length:  0x00010000,
+            is_included: "yes",
+            path:    "./hw/vendor/lowrisc_opentitan_spi_host/data/spi_host.hjson"
+        },
         gpio: {
             offset:  0x00020000,
             length:  0x00010000,
@@ -143,6 +127,7 @@
             is_included: "yes",
             path:    "./hw/ip/i2s/data/i2s.hjson"
         },
+
     },
 
     flash_mem: {
diff --git a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
index 605ccbb2..0be257d7 100644
--- a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
+++ b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
@@ -7,26 +7,7 @@
 
     cpu_type: cv32e20
 
-    bus_type: onetoM
-
-    ram: {
-        address: 0x00000000, #only tried with 0, cannot be changed for now
-        numbanks: 2, #each bank is 32kB, cannot be changed for now
-        numbanks_interleaved: 0,
-    },
-
     linker_script: {
-        #value used for the on-chip linker script, the on-flash linker script is generated using FLASH values and the whole RAM values
-        onchip_ls: {
-            code: {
-                address: 0x00000000,
-                lenght: 0x00000C800, #minimum size for freeRTOS and clang
-            }
-            data: {
-                address: 0x00000C800,
-                lenght: whatisleft, #keyword used to calculate the size as: ram.length - code.lenght
-            }
-        },
         stack_size: 0x800,
         heap_size: 0x800,
     }
@@ -56,10 +37,12 @@
             offset:  0x00028000,
             length:  0x00008000,
         },
-        spi_host: {
+        dma: {
             offset:  0x00030000,
             length:  0x00010000,
-            path:    "./hw/vendor/lowrisc_opentitan_spi_host/data/spi_host.hjson"
+            ch_length:    0x100,
+            num_channels:   0x1,
+            path:    "./hw/ip/dma/data/dma.hjson"
         },
         power_manager: {
             offset:  0x00040000,
@@ -70,30 +53,25 @@
             offset:  0x00050000,
             length:  0x00010000,
         },
-        dma: {
-            offset:  0x00060000,
-            length:  0x00010000,
-            path:    "./hw/ip/dma/data/dma.hjson"
-        },
         fast_intr_ctrl: {
-            offset:  0x00070000,
+            offset:  0x00060000,
             length:  0x00010000,
             path:    "./hw/ip/fast_intr_ctrl/data/fast_intr_ctrl.hjson"
         },
         ext_peripheral: {
-            offset:  0x00080000,
+            offset:  0x00070000,
             length:  0x00010000,
         },
         pad_control: {
-            offset:  0x00090000,
+            offset:  0x00080000,
             length:  0x00010000,
         },
         gpio_ao: {
-            offset:  0x000A0000,
+            offset:  0x00090000,
             length:  0x00010000,
         },
         uart: {
-            offset:  0x000B0000,
+            offset:  0x000A0000,
             length:  0x00010000,
             path:    "./hw/vendor/lowrisc_opentitan/hw/ip/uart/data/uart.hjson"
         },
@@ -105,9 +83,15 @@
         rv_plic: {
             offset:  0x00000000,
             length:  0x00010000,
-            is_included: "yes",
+            is_included: "no",
             path:    "./hw/vendor/lowrisc_opentitan/hw/ip/rv_plic/data/rv_plic.hjson"
         },
+        spi_host: {
+            offset:  0x00010000,
+            length:  0x00010000,
+            is_included: "no",
+            path:    "./hw/vendor/lowrisc_opentitan_spi_host/data/spi_host.hjson"
+        },
         gpio: {
             offset:  0x00020000,
             length:  0x00010000,
@@ -123,7 +107,7 @@
         rv_timer: {
             offset:  0x00040000,
             length:  0x00010000,
-            is_included: "yes",
+            is_included: "no",
             path:    "./hw/vendor/lowrisc_opentitan/hw/ip/rv_timer/data/rv_timer.hjson"
         },
         spi2: {
diff --git a/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson b/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson
index cc7303a1..1cfa8c79 100644
--- a/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson
+++ b/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson
@@ -2,11 +2,25 @@
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 // Derived from Occamy: https://github.com/pulp-platform/snitch/blob/master/hw/system/occamy/src/occamy_cfg.hjson
-// Peripherals configuration for core-v-mini-mcu.
-
+//
+// Pads configuration for core-v-mini-mcu. Read by mcu_gen.py.
+// 
+// The pads contains the list of all the pads available in the design.
+// Each pad is defined by its name and can have the following attributes:
+//    num: <number> (mandatory) - the number of pads of this type
+//    type: <input|output|inout> (mandatory) - the type of the pad
+//    num_offset: <number> (optional) - the offset to the first pad of this type (default 0)
+//    mapping: <top|right|bottom|left> (optional) - the mapping of the pad in the design. Useful for ASICs (default top)
+//    active: <low|high> (optional) - the active level of the pad (default high)
+//    driven_manually: <True|False> (optional) - the pad is driven manually (default False)
+//    mux: <dict> (optional) - the muxing options for the pad
+//    skip_declaration: <True|False> (optional) - skip the declaration of the pad in the top level (default False)
+//    keep_internal: <True|False> (optional) - keep the pad internal to the design (default False)
+// 
 // Add this field at the same level of pads (not inside) if you want to define PADs attributes
 //    attributes: {
 //        bits: 7:0
+//        resval: 0x3
 //    },
 
 {
diff --git a/hw/vendor/esl_epfl_x_heep/scripts/synthesis/dc_shell/dc_script.tcl b/hw/vendor/esl_epfl_x_heep/scripts/synthesis/dc_shell/dc_script.tcl
index 8edeb7f9..3a246ab8 100644
--- a/hw/vendor/esl_epfl_x_heep/scripts/synthesis/dc_shell/dc_script.tcl
+++ b/hw/vendor/esl_epfl_x_heep/scripts/synthesis/dc_shell/dc_script.tcl
@@ -10,11 +10,15 @@ remove_design -all
 
 source ${SET_LIBS}
 
+define_design_lib WORK -path ./work
+
 source ${READ_SOURCES}.tcl
 
 elaborate ${TOP_MODULE}
 link
 
+load_upf ../../../core-v-mini-mcu.dc.upf
+
 write -f ddc -hierarchy -output ${REPORT_DIR}/precompiled.ddc
 
 source ${CONSTRAINTS}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
index ef5743c6..cdb2a8f7 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
+++ b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
@@ -42,7 +42,7 @@ if(NOT WIN32)
 endif()
 
 # set the project name
-project(${PROJECT} ASM C)
+project(${PROJECT} ASM C CXX)
 
 # set the required CMake standard
 set(CMAKE_CXX_STANDARD 14)
@@ -89,17 +89,18 @@ FOREACH(file_path ${new_list})
     # Add it to the string format list
     SET(dir_list_str ${dir_list_str} "-I ${dir_path} \
     ")
-    string(REPLACE ";" "" dir_list_str ${dir_list_str})
-
+    
     # Add it to the header list
     SET(h_dir_list_ ${h_dir_list_} "${dir_path}")
   endif()
 
 ENDFOREACH()
 
-LIST(REMOVE_DUPLICATES dir_list_str)
+LIST(REMOVE_DUPLICATES dir_list_str) 
+string(REPLACE ";" "" dir_list_str ${dir_list_str}) #This has been moved here to avoid multiple includes of the same path, see: https://github.com/esl-epfl/x-heep/issues/470
 LIST(REMOVE_DUPLICATES h_dir_list_)
 
+
 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
 # Add list to the directories to be included
 
@@ -108,8 +109,7 @@ SET(INCLUDE_FOLDERS "-I ${RISCV}/${COMPILER_PREFIX}elf/include \
                      -I ${RISCV}/${COMPILER_PREFIX}elf/include/ \
                      -I ${ROOT_PROJECT} \
                      -I ${SOURCE_PATH} \
-					           ${dir_list_str}")
-
+					           ${dir_list_str}")                                      
 
 #######################################################################
 #      FIND SOURCE FILES TO BE INCLUDED
@@ -118,15 +118,25 @@ SET(INCLUDE_FOLDERS "-I ${RISCV}/${COMPILER_PREFIX}elf/include \
 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
 # Preliminary list of source files inside the source path
 
-# Make a list of the source files that need to be linked
-FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS ${SOURCE_PATH}*.c)
+# Make a list of the .c source files that need to be linked
+FILE(GLOB_RECURSE c_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.c)
+# Make a list of the .s source files that need to be linked
+FILE(GLOB_RECURSE s_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.s)
+# Make a list of the .S source files that need to be linked
+FILE(GLOB_RECURSE S_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.S)
+# Make a list of the .cpp source files that need to be linked
+FILE(GLOB_RECURSE cpp_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.cpp)
+SET(new_list ${c_files} ${s_files} ${S_files} ${cpp_files})
+
 SET( c_dir_list "" )
 SET( app_found 0 )
 FOREACH(file_path IN LISTS new_list)
   SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
   if(${file_path} MATCHES "${SOURCE_PATH}device/")
-    SET(add 1)
-  elseif( ${file_path} MATCHES "${SOURCE_PATH}external/" )
+    if(NOT ${file_path} MATCHES  ".*/crt/.*") 
+      SET(add 1)
+    endif()
+  elseif( (${file_path} MATCHES "${SOURCE_PATH}external/") AND ( NOT  ${file_path} MATCHES "exclude" ) )
     SET(add 1)
   elseif( ${file_path} MATCHES "${SOURCE_PATH}applications/${PROJECT}/.*${MAINFILE}\." ) # look for main.*
     SET(app_found 1)
@@ -134,7 +144,7 @@ FOREACH(file_path IN LISTS new_list)
     SET(add 1)
   endif()
 
-  if( add EQUAL 1 ) # If the file path mathced one of the criterion, add it to the list
+  if( add EQUAL 1 ) # If the file path matched one of the criteria, add it to the list
     SET(c_dir_list ${c_dir_list} "${file_path}\
     ")
     string(REPLACE ";" "" c_dir_list ${c_dir_list})
@@ -148,28 +158,39 @@ ENDFOREACH()
 if( app_found EQUAL 0 )
   SET(SOURCE_PATH ${ROOT_PROJECT})
 
-  # Make a list of the source files that need to be linked
-  FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS ${SOURCE_PATH}*.c)
+  # Make a list of the .c source files that need to be linked
+  FILE(GLOB_RECURSE c_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.c)
+  # Make a list of the .s source files that need to be linked
+  FILE(GLOB_RECURSE s_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.s)
+  # Make a list of the .S source files that need to be linked
+  FILE(GLOB_RECURSE S_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.S)
+  # Make a list of the .cpp source files that need to be linked
+  FILE(GLOB_RECURSE cpp_files FOLLOW_SYMLINKS ${SOURCE_PATH}*.cpp)
+  SET(new_list ${c_files} ${s_files} ${S_files} ${cpp_files})
+
   SET(c_dir_list "")
   FOREACH(file_path IN LISTS new_list)
     SET(add 0) # This variable is set to 1 if the file_pth needs to be added to the list
     if(${file_path} MATCHES "${ROOT_PROJECT}device/")
-      SET(add 1)
-    elseif( ( ${file_path} MATCHES "${ROOT_PROJECT}/applications/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES "${ROOT_PROJECT}applications/${PROJECT}/.*${MAINFILE}\." ) )
+      if(NOT ${file_path} MATCHES ".*/crt/.*")
+        SET(add 1)
+      endif()
+    elseif( ( ${file_path} MATCHES "${ROOT_PROJECT}applications/${PROJECT}/" ) AND ( NOT ${file_path} MATCHES "${ROOT_PROJECT}applications/${PROJECT}/.*${MAINFILE}\." ) AND ( NOT  ${file_path} MATCHES "exclude" ) )
       SET(add 1)
     endif()
 
-    if( add EQUAL 1 ) # If the file path mathced one of the criterion, add it to the list
+    if( add EQUAL 1 ) # If the file path matched one of the criteria, add it to the list
       SET(c_dir_list ${c_dir_list} "${file_path}\
       ")
       string(REPLACE ";" "" c_dir_list ${c_dir_list})
     endif()
 
     ENDFOREACH()
-endif()
-
+  endif()
+  
 LIST(REMOVE_DUPLICATES c_dir_list)
 
+
 #######################################################################
 #      DETERMINE IF APP IS EXTERNAL
 #######################################################################
@@ -266,7 +287,7 @@ message( "${Magenta}Target: ${TARGET}${ColourReset}")
 SET(LINKED_FILES    "${LIB_CRT_P} \
                      ${LIB_VCTR_P} \
                      ${LIB_CRT_EXT_P} \
-                     ${c_dir_list}")
+                     ${c_dir_list}") 
 
 message( "${Magenta}Linked files: ${LINKED_FILES}${ColourReset}")
 
@@ -325,10 +346,10 @@ else()
   ")
 endif()
 set(CMAKE_C_FLAGS ${COMPILER_LINKER_FLAGS})
+set(CMAKE_CXX_FLAGS ${COMPILER_LINKER_FLAGS})
 
 if (${COMPILER} MATCHES "clang")
      set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} --target=riscv32 \
-                                          -mabi=ilp32 \
                                           --gcc-toolchain=${RISCV} \
                                           --sysroot=${RISCV}/${COMPILER_PREFIX}elf \
                                           -static \
@@ -347,8 +368,18 @@ endif()
 #######################################################################
 #      SET TARGETS
 #######################################################################
-
-set(SOURCES ${SOURCE_PATH}applications/${PROJECT}/${MAINFILE}.c)
+if (${COMPILER} MATCHES "gcc")
+  set(SOURCES ${SOURCE_PATH}applications/${PROJECT}/${MAINFILE}.c)
+  if(NOT EXISTS ${SOURCES})
+    # If main.c does not exist, set the source file to main.cpp
+    set(SOURCES ${SOURCE_PATH}applications/${PROJECT}/${MAINFILE}.cpp)
+    message("${Red}cpp SOURCES set")
+  endif()
+elseif(${COMPILER} MATCHES "clang")
+  set(SOURCES ${SOURCE_PATH}applications/${PROJECT}/${MAINFILE}.c)
+elseif(${COMPILER} MATCHES "g\\+\\+.*$")
+  set(SOURCES ${SOURCE_PATH}applications/${PROJECT}/${MAINFILE}.cpp)
+endif()
 
 # add the executable
 add_executable(${MAINFILE}.elf ${SOURCES})
@@ -378,6 +409,7 @@ SET(CMAKE_EXE_LINKER_FLAGS  "-T ${LINKER_SCRIPT}  \
                              -Wl,-Map=${MAINFILE}.map \
                              -L ${RISCV}/${COMPILER_PREFIX}elf/lib \
                              -lc -lm -lgcc -flto \
+                             -fpermissive -fno-rtti -fno-exceptions -fno-threadsafe-statics \
                             -ffunction-sections -fdata-sections -specs=nano.specs")
 message( "${Magenta}Lib Folder RISCV-GCC: ${RISCV}/${COMPILER_PREFIX}elf/lib${ColourReset}")
 
@@ -433,12 +465,31 @@ add_custom_command(TARGET ${MAINFILE}.elf POST_BUILD
         COMMENT "Invoking: Hexdump")
 
 # Pre-processing command to create disassembly for each source file
-foreach (SRC_MODULE ${MAINFILE} )
+if ((${COMPILER} MATCHES "gcc") OR (${COMPILER} MATCHES "clang"))
+  if(EXISTS ${SOURCE_PATH}applications/${PROJECT}/${MAINFILE}.c)
+   foreach (SRC_MODULE ${MAINFILE} )
+    add_custom_command(TARGET ${MAINFILE}.elf
+                       PRE_LINK
+                       COMMAND ${CMAKE_OBJDUMP} -S ${ROOT_PROJECT}build/CMakeFiles/${MAINFILE}.elf.dir/${OBJ_PATH}applications/${PROJECT}/${SRC_MODULE}.c.obj > ${SRC_MODULE}.s
+                       COMMENT "Invoking: GCC C Disassemble ( CMakeFiles/${MAINFILE}.dir/${SRC_MODULE}.c.obj)")   
+   endforeach()
+  else() #main.cpp targets
+  foreach (SRC_MODULE ${MAINFILE} )
+    add_custom_command(TARGET ${MAINFILE}.elf
+                       PRE_LINK
+                      COMMAND ${CMAKE_OBJDUMP} -S ${ROOT_PROJECT}build/CMakeFiles/${MAINFILE}.elf.dir/${OBJ_PATH}applications/${PROJECT}/${SRC_MODULE}.cpp.obj > ${SRC_MODULE}.s
+                      COMMENT "Invoking:  GCC CPP Disassemble ( CMakeFiles/${MAINFILE}.dir/${SRC_MODULE}.cpp.obj)")
+    endforeach()
+  endif()
+elseif(${COMPILER} MATCHES "g\\+\\+.*$")
+  foreach (SRC_MODULE ${MAINFILE} )
   add_custom_command(TARGET ${MAINFILE}.elf
                      PRE_LINK
-                     COMMAND ${CMAKE_OBJDUMP} -S ${ROOT_PROJECT}build/CMakeFiles/${MAINFILE}.elf.dir/${OBJ_PATH}applications/${PROJECT}/${SRC_MODULE}.c.obj > ${SRC_MODULE}.s
-                     COMMENT "Invoking: Disassemble ( CMakeFiles/${MAINFILE}.dir/${SRC_MODULE}.c.obj)")
-endforeach()
+                    COMMAND ${CMAKE_OBJDUMP} -S ${ROOT_PROJECT}build/CMakeFiles/${MAINFILE}.elf.dir/${OBJ_PATH}applications/${PROJECT}/${SRC_MODULE}.cpp.obj > ${SRC_MODULE}.s
+                    COMMENT "Invoking: G++ Disassemble ( CMakeFiles/${MAINFILE}.dir/${SRC_MODULE}.cpp.obj)")
+  endforeach()
+endif()
+
 
 # Adding gdb command - TBD
 #add_custom_target(gdb DEPENDS ${MAINFILE}.elf)
@@ -447,4 +498,4 @@ endforeach()
 
 SET(DCMAKE_EXPORT_COMPILE_COMMANDS ON)
 
-#message( FATAL_ERROR "You can not do this at all, CMake will exit." )
+#message( FATAL_ERROR "You can not do this at all, CMake will exit." )
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/Makefile b/hw/vendor/esl_epfl_x_heep/sw/Makefile
index a36f5ead..e327138b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/sw/Makefile
@@ -59,7 +59,7 @@ $(info $$You are fetching sources from $(source_path) )
 SOURCE_PATH   		       = $(source_path)/
 ROOT_PROJECT               = $(mkfile_path)/
 INC_FOLDERS                = $(mkfile_path)/device/target/$(TARGET)/
-LINK_FOLDER                = $(mkfile_path)/linker
+LINK_FOLDER                ?= $(mkfile_path)/linker
 
 # CMake keyword
 CMAKE_DIR=cmake
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h
index 1501da49..4f2b074d 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/coremark/coremark.h
@@ -64,7 +64,7 @@ Original Author: Shay Gal-on
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define ee_printf(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define ee_printf(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define ee_printf printf
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_ams_peripheral/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_ams_peripheral/main.c
index accf4c4d..817cbff6 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_ams_peripheral/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_ams_peripheral/main.c
@@ -10,7 +10,7 @@
 #include "ams_regs.h"
 #include "mmio.h"
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
   #error ( "This app does NOT work on the FPGA as it relies on the simulator testbench" )
 #endif
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/add.s b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/add.s
new file mode 100644
index 00000000..2e61b29a
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/add.s
@@ -0,0 +1,6 @@
+    .section .text
+    .globl add_asm_function
+
+add_asm_function:
+    add a0, a0, a1   # Add the values in a0 and a1, store the result in a0
+    ret              # Return from the function
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/constants.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/constants.h
new file mode 100644
index 00000000..58834c58
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/constants.h
@@ -0,0 +1 @@
+#define MULTIPLY_CONSTANT 2
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/main.c
new file mode 100644
index 00000000..48ca9c9e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/main.c
@@ -0,0 +1,31 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "constants.h"
+#include "x-heep.h"
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+extern int add_asm_function(int a, int b);
+extern int mul_by_const_asm_function( int a);
+
+int main() {
+    int num1 = 10;
+    int num2 = 20;
+    int sum = add_asm_function(num1, num2);
+    int mul = mul_by_const_asm_function(num2);
+
+    PRINTF("%d+%d=%d\n", num1, num2, sum);
+    PRINTF("%d*%d=%d\n", num2, MULTIPLY_CONSTANT, mul );
+    
+    return (sum == num1+num2) && (mul == num2*MULTIPLY_CONSTANT) ? EXIT_SUCCESS : EXIT_FAILURE;   
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/multiply.S b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/multiply.S
new file mode 100644
index 00000000..7130f488
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_asm/multiply.S
@@ -0,0 +1,9 @@
+#include "constants.h"
+
+    .section .text
+    .globl mul_by_const_asm_function
+
+mul_by_const_asm_function:
+    li t0, MULTIPLY_CONSTANT    # Load the constant into temporary register t0
+    mul a0, a0, t0              # Multiply the value in a0 by the constant in t0
+    ret                         # Return from the function
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_clock_gating/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_clock_gating/main.c
deleted file mode 100644
index 958e0492..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_clock_gating/main.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "power_manager.h"
-#include "x-heep.h"
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-static power_manager_t power_manager;
-
-int main(int argc, char *argv[])
-{
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-
-    // Clock-gating the peripheral subsystem
-    mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(POWER_MANAGER_PERIPH_CLK_GATE_REG_OFFSET), 0x1);
-
-    // Clock-gating ram-banks
-    // We probably should not clockgate the bank where our RAM resides
-    for(uint32_t i = 2; i < MEMORY_BANKS; ++i)
-        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_ram_map[i].clk_gate), 0x1);
-
-    // Clock-gating external subsystems
-    for(uint32_t i = 0; i < EXTERNAL_DOMAINS; ++i)
-        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_external_map[i].clk_gate), 0x1);
-
-    // Wait some time
-    for (int i=0; i<100; i++) asm volatile("nop;");
-
-    // Enabling the peripheral subsystem
-    mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(POWER_MANAGER_PERIPH_CLK_GATE_REG_OFFSET), 0x0);
-
-    // Enabling ram-banks
-    for(uint32_t i = 2; i < MEMORY_BANKS; ++i)
-        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_ram_map[i].clk_gate), 0x0);
-
-    // Enabling external subsystems
-    for(uint32_t i = 0; i < EXTERNAL_DOMAINS; ++i)
-        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_external_map[i].clk_gate), 0x0);
-
-    /* write something to stdout */
-    PRINTF("Success.\n\r");
-    return EXIT_SUCCESS;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.cpp b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.cpp
new file mode 100644
index 00000000..00d1b576
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.cpp
@@ -0,0 +1,21 @@
+
+extern "C" {
+    #include <stdio.h>
+    #include <stdlib.h>
+}
+
+#include "MyClass.hpp"
+
+MyClass::MyClass(int initialValue) : value(initialValue) {}
+
+void MyClass::setValue(int newValue) {
+    value = newValue;
+}
+
+int MyClass::getValue() {
+    return value*5;
+}
+
+void MyClass::printValue() {
+    printf("Value: %d\n\r",  value);
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.hpp b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.hpp
new file mode 100644
index 00000000..82922878
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/MyClass.hpp
@@ -0,0 +1,15 @@
+#ifndef MYCLASS_HPP
+#define MYCLASS_HPP
+
+class MyClass {
+public:
+    MyClass(int initialValue); // Constructor
+    void setValue(int newValue); // Setter
+    int getValue(); // Getter
+    void printValue(); // Method to print the value
+
+private:
+    int value;
+};
+
+#endif // MYCLASS_HPP
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.c
deleted file mode 100644
index bbe2f071..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2020 ETH Zurich
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Author: Robert Balas <balasr@iis.ee.ethz.ch>
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-int main(int argc, char *argv[])
-{
-    /* write something to stdout */
-    printf("hello world!\n");
-    return EXIT_SUCCESS;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.cpp b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.cpp
new file mode 100644
index 00000000..b314a2b8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/main.cpp
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2024 EPFL
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Author: Juan Sapriza <juan.sapriza@epfl.ch>
+ */
+
+
+
+extern "C" {
+    #include <stdio.h>
+    #include <stdlib.h>
+}
+
+#include "MyClass.hpp"
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+
+#if TARGET_SIM && PRINTF_IN_SIM
+#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define PRINTF(...)
+#endif
+
+int main()
+{
+    MyClass myObject(10); // Create an object with initial value 10
+    myObject.printValue(); // Print the initial value
+
+    myObject.setValue(20); // Change the value to 20
+    myObject.printValue(); // Print the updated value
+
+    int value = myObject.getValue(); // Get the value
+    PRINTF("Retrieved Value: %d\n\r" ,value); // Print the retrieved value
+
+    return value == 20*5 ? EXIT_SUCCESS : EXIT_FAILURE;
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.cpp b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.cpp
deleted file mode 100644
index 53d08e36..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.cpp
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2022 ESL EPFL
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Author: Jose Miranda <jose.mirandacalero@epfl.ch>
- */
-
-extern "C" {
-    #include <stdio.h>
-    #include <stdlib.h>
-    #include "test_cpp.h"
-}
-
-#define LOOPS 5
-template <typename T> 
-T mySum(T x, T y)
-{
-    return x+y;
-}
-
-int test_numbers(void) 
-{
-    int i = 0, a = 3, b = 7;
-	
-    while (i < LOOPS)   
-    {
-     printf("Integer sum %d\n", mySum(a, b));
-     i = i + 1;
-    }
-	
-    return 0;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.h
deleted file mode 100644
index 31121435..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_cpp/test_cpp.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/// @brief 
-/// @param  
-/// @return 
-int test_numbers(void);
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py
new file mode 100644
index 00000000..5a4a6cd2
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py
@@ -0,0 +1,65 @@
+#!/usr/bin/env python
+
+## Copyright 2024 EPFL
+## Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# type " python gen_stimuly.py " in the terminal to generate the matrices.h file
+
+import sys
+import random
+import numpy as np
+
+def write_arr(f, name, arr, ctype, size):
+    f.write("const " + ctype + " " + name + "[] = {\n")
+
+    for row in arr:
+        for elem in row[:-1]:
+            f.write('%d,' % (elem))
+        f.write('%d,\n' % (row[-1]))
+
+    f.write('};\n\n')
+    return
+
+def write_arr_flash_only(f, name, arr, ctype, size):
+    f.write( ctype + " __attribute__((section(\".xheep_data_flash_only\"))) __attribute__ ((aligned (16)))" + name + "[] = {\n")
+
+    for row in arr:
+        for elem in row[:-1]:
+            f.write('%d,' % (elem))
+        f.write('%d,\n' % (row[-1]))
+
+    f.write('};\n\n')
+    return
+
+
+################################################################################
+f = open('matrices.h', 'w')
+f.write('#ifndef MATRICES_H_\n')
+f.write('#define MATRICES_H_\n')
+f.write('// This file is automatically generated\n')
+
+
+SIZE  = 64
+RANGE = 10
+
+m_a   = []
+m_b   = []
+m_exp = []
+
+# Generate random 8 bit integers from -RANGE to RANGE for A and B
+A = np.random.randint(0, RANGE, size=(SIZE, SIZE), dtype=np.int32)
+B = np.random.randint(0, RANGE, size=(SIZE, SIZE), dtype=np.int32)
+C = np.zeros((SIZE, SIZE), dtype=np.int32)
+
+# Test the function with A and B
+C = np.matmul(A,B)
+
+write_arr_flash_only(f, 'A',   A, 'int32_t', SIZE)
+write_arr(f, 'B',   B, 'int32_t', SIZE)
+write_arr(f, 'C',   C, 'int32_t', SIZE)
+
+f.write('#define MATRIX_SIZE %d\n' % SIZE)
+
+
+f.write('#endif')
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c
new file mode 100644
index 00000000..01f7dab7
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c
@@ -0,0 +1,87 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: sw/applications/example_data_processing_from_flash/main.c
+// Author:  Francesco Poluzzi
+// Date: 29/07/2024
+
+/**
+ * @file main.c
+ * @brief Example of data processing (matrix multiplication) reading data from flash memory
+ *
+ * Simple example that read a matrix from flash memory in many step and performs
+ * matrix multiplication. This is useful for applications where the
+ * data size does not fit in the available SRAM memory, so some data needs to be
+ * stored as "flash_only" and read trough the spi interface. This usually requires
+ * filling a buffer and tiling the data processing.
+*/
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "x-heep.h"
+#include "w25q128jw.h"
+#include "main.h"
+#include "dma_sdk.h"
+
+#define TILING_ROWS 2
+
+ /* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+int32_t buffer_data[MATRIX_SIZE*TILING_ROWS] = {0};
+int32_t output_matrix[MATRIX_SIZE*MATRIX_SIZE] = {0};
+
+int main(int argc, char *argv[]) {
+
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+
+    #ifdef TARGET_SIM
+        PRINTF("This application is meant to run on FPGA only\n");
+        return EXIT_SUCCESS;
+    #endif
+
+    if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO ) {
+        PRINTF("This application cannot work with the memory mapped SPI FLASH"
+            "module - do not use the FLASH_EXEC linker script for this application\n");
+        return EXIT_SUCCESS;
+    }
+
+    // Pick the correct spi device based on simulation type
+    spi_host_t* spi = spi_flash;
+
+    // Init SPI host and SPI<->Flash bridge parameters
+    if (w25q128jw_init(spi) != FLASH_OK){
+        PRINTF("Error initializing SPI flash\n");
+        return EXIT_FAILURE;
+    } 
+
+    for (int i = 0; i < MATRIX_SIZE; i+=TILING_ROWS) {
+        // read first half matrix A from flash and perform matmul
+        if(fill_buffer(&A[i*MATRIX_SIZE], buffer_data, MATRIX_SIZE*TILING_ROWS)!=FLASH_OK){
+            PRINTF("Error reading from flash\n");
+            return EXIT_FAILURE;
+        }
+        matmul(buffer_data, B, &output_matrix[i*MATRIX_SIZE], TILING_ROWS, MATRIX_SIZE, MATRIX_SIZE);
+    }
+
+    for(int i = 0; i < MATRIX_SIZE*MATRIX_SIZE; i++){
+        if (output_matrix[i] != C[i]){
+             PRINTF("Result[%d][%d]:golden model   %d : %d\n", (i/MATRIX_SIZE), (i % MATRIX_SIZE), output_matrix[i], C[i]);
+            return EXIT_FAILURE;
+       }
+    }
+    PRINTF("All tests passed!\n");
+    return EXIT_SUCCESS;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.h
new file mode 100644
index 00000000..0e588e78
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.h
@@ -0,0 +1,42 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: sw/applications/example_data_processing_from_flash/main.h
+// Author:  Francesco Poluzzi
+// Date: 29/07/2024
+
+#ifndef MAIN_H_
+#define MAIN_H_
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "x-heep.h"
+#include "w25q128jw.h"
+#include "matrices.h"
+
+w25q_error_codes_t fill_buffer(uint32_t *source, uint32_t *buffer, uint32_t len);
+void matmul(int32_t *A, int32_t *B, int32_t *res, int rowsA, int colsA, int colsB);
+
+w25q_error_codes_t fill_buffer(uint32_t *source, uint32_t *buffer, uint32_t len){
+    uint32_t *source_flash = heep_get_flash_address_offset(source);
+    w25q_error_codes_t status = w25q128jw_read_standard(source_flash, buffer, len*4);
+    return status;
+}
+
+void matmul(int32_t *A, int32_t *B, int32_t *res, int rowsA, int colsA, int colsB) {
+    for (int i = 0; i < rowsA; i++) {
+        for (int j = 0; j < colsB; j++) {
+            int32_t sum = 0;
+            for (int k = 0; k < colsA; k++) {
+                sum += A[i*colsA + k] * B[k*colsB + j];
+            }
+            res[i*colsB + j] = sum;
+        }
+    }
+}
+
+
+#endif // DATA_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h
new file mode 100644
index 00000000..323d1a06
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h
@@ -0,0 +1,206 @@
+#ifndef MATRICES_H_
+#define MATRICES_H_
+// This file is automatically generated
+int32_t __attribute__((section(".xheep_data_flash_only"))) __attribute__ ((aligned (16)))A[] = {
+8,0,9,3,0,0,7,3,4,4,4,0,5,1,9,3,9,1,0,4,1,1,9,4,6,9,8,1,3,3,2,6,5,6,8,7,4,3,3,1,1,9,8,9,6,3,1,6,4,3,6,1,9,0,6,7,5,0,6,5,1,5,6,2,
+3,1,8,2,9,8,1,3,0,2,4,6,6,5,7,1,5,5,5,8,6,5,4,9,2,6,7,1,7,2,5,0,9,9,7,6,2,1,6,5,4,9,5,3,1,5,6,9,3,4,4,1,1,7,2,5,8,0,6,4,3,1,8,2,
+3,8,8,0,7,5,1,9,1,2,2,2,0,6,4,6,2,4,7,6,0,9,9,8,5,1,9,5,9,8,2,2,7,7,7,5,9,0,3,4,5,3,9,0,2,2,0,7,2,3,1,1,5,5,3,6,4,4,3,7,5,6,0,4,
+9,4,4,2,0,4,3,5,7,5,7,5,3,6,5,4,5,7,4,2,4,0,2,8,6,8,4,0,1,3,8,5,4,8,5,1,6,0,7,6,3,1,1,6,2,5,4,9,4,9,5,1,3,7,0,1,0,2,6,3,8,0,1,6,
+3,7,8,9,5,1,7,5,5,8,9,7,2,1,2,1,0,3,5,5,3,0,3,0,8,3,3,5,6,3,7,2,2,6,6,1,7,1,7,6,7,1,7,2,0,6,5,1,7,6,6,4,6,3,7,2,1,0,5,9,1,1,1,1,
+4,5,6,7,5,3,5,0,2,9,1,7,1,5,6,6,8,8,1,4,5,8,5,2,5,8,8,5,9,5,2,5,6,4,1,2,9,7,1,1,0,6,9,1,2,2,6,3,7,6,6,1,2,0,1,1,8,9,7,0,4,9,0,3,
+5,9,0,0,6,3,8,2,4,5,2,9,1,4,4,8,9,3,5,7,1,6,8,8,7,9,3,7,7,4,8,4,9,6,3,1,5,0,6,7,9,6,9,6,4,9,0,6,0,2,1,4,9,4,7,6,0,1,8,2,8,4,2,9,
+5,0,0,9,3,7,3,3,8,4,2,0,1,9,5,5,0,0,4,9,8,7,1,3,3,4,3,0,0,3,3,0,2,5,1,8,6,0,2,0,4,2,3,2,9,5,5,2,8,9,4,2,9,7,7,8,8,3,8,9,3,9,1,9,
+6,8,4,2,5,3,3,5,1,0,0,8,1,3,9,9,5,5,9,0,5,9,8,2,4,1,4,3,0,6,7,9,9,2,1,8,1,5,1,9,6,3,9,5,0,1,3,6,4,7,5,0,4,6,3,1,4,9,2,1,8,2,8,5,
+9,8,5,1,8,0,0,0,1,5,2,6,2,3,2,6,6,7,3,6,6,3,5,9,8,8,1,7,4,4,1,2,0,2,4,3,0,0,5,5,3,8,6,1,4,6,4,8,5,9,7,9,8,1,0,9,8,1,9,6,4,4,0,2,
+1,6,0,4,7,8,1,6,8,8,9,4,7,8,1,3,5,4,1,2,8,3,6,4,2,0,1,9,3,9,6,9,2,2,3,3,2,7,1,0,2,8,9,9,9,8,7,4,2,9,4,8,2,0,9,0,3,2,5,6,4,9,3,1,
+0,9,9,8,5,4,5,4,1,9,3,3,0,1,6,3,8,6,6,6,3,8,5,7,8,9,4,1,8,2,6,0,5,3,6,7,1,9,8,7,9,0,5,5,3,7,0,1,2,9,4,3,8,3,2,6,1,0,5,5,6,0,4,8,
+8,6,2,6,1,4,4,2,0,3,9,8,9,3,1,8,2,9,5,9,9,4,6,0,9,9,9,4,8,7,7,4,4,1,7,9,9,7,3,2,1,6,5,6,5,4,7,9,0,1,0,5,6,9,1,5,1,1,7,5,8,6,7,6,
+7,6,5,8,6,2,3,1,2,8,3,9,5,9,3,9,8,8,2,4,7,0,7,4,1,1,9,8,9,7,4,9,3,4,8,3,6,1,1,7,4,9,7,6,8,3,9,1,2,8,2,1,1,6,0,1,2,1,2,2,2,1,0,1,
+3,2,7,7,9,2,1,4,0,0,4,4,4,1,4,3,2,1,1,6,4,0,4,6,2,4,9,1,1,3,6,9,0,0,0,0,4,4,6,7,5,9,0,4,1,7,7,0,5,9,4,5,4,1,9,1,3,0,8,4,9,1,8,3,
+9,9,3,9,1,9,4,5,3,6,0,5,8,4,3,9,0,2,7,6,1,9,7,4,0,0,9,4,1,6,3,6,7,9,3,9,4,6,6,1,1,7,0,8,0,3,1,0,5,9,3,9,4,7,7,1,1,7,7,1,1,0,2,1,
+0,8,7,7,8,0,9,0,4,3,9,1,3,8,3,8,4,2,1,2,2,9,0,2,4,6,1,3,1,8,9,0,1,7,9,0,1,7,2,3,7,7,7,0,0,1,4,4,8,4,8,7,8,9,9,8,9,3,1,6,5,4,5,2,
+6,1,9,3,1,9,0,6,0,0,1,5,3,0,0,4,7,7,2,4,8,8,9,3,8,8,9,4,5,3,8,4,1,2,7,5,4,4,9,3,7,5,2,9,4,5,0,3,2,3,7,2,2,8,7,1,4,4,9,2,1,7,7,6,
+6,3,0,2,7,7,2,8,8,7,1,6,8,1,5,6,7,7,7,4,9,8,4,8,7,6,0,8,0,9,8,0,8,8,1,4,7,8,7,3,3,9,8,6,5,7,8,9,0,8,6,6,7,4,8,3,6,0,2,8,3,9,3,1,
+5,9,0,5,3,9,5,4,6,8,4,9,9,6,8,2,5,8,0,1,3,8,5,9,8,3,1,4,9,0,9,8,1,6,6,9,9,5,0,4,9,4,2,5,3,0,2,9,8,1,6,3,7,3,8,2,9,9,9,6,0,7,4,5,
+7,0,7,7,1,7,7,3,2,5,4,5,7,5,7,2,8,7,2,0,2,8,3,9,7,5,1,0,5,8,7,2,1,9,2,3,3,7,7,1,4,3,2,2,8,3,0,7,4,6,1,5,0,3,6,5,0,9,4,2,3,1,5,0,
+9,4,2,7,3,2,5,8,5,1,7,2,1,9,1,6,7,3,7,0,2,7,9,4,3,1,9,6,1,3,2,5,9,9,1,9,0,5,4,2,3,3,3,3,1,7,2,2,9,9,8,4,1,1,1,1,6,6,5,4,0,3,1,2,
+1,9,3,6,6,3,4,9,3,4,2,2,4,3,5,4,0,6,5,1,1,1,2,7,9,4,0,0,3,7,1,8,9,0,7,7,1,3,7,7,5,7,9,7,0,0,8,1,9,0,3,9,3,9,0,8,4,5,4,5,6,0,9,4,
+5,6,4,1,1,8,9,4,3,2,5,9,5,4,5,6,9,4,1,7,1,3,0,0,5,9,5,2,3,2,5,5,7,2,2,9,3,1,2,8,5,0,1,0,8,9,2,9,3,4,6,9,5,4,7,4,7,9,6,1,0,8,2,8,
+5,3,4,4,8,1,5,5,2,4,2,1,1,5,6,3,2,4,9,1,1,5,3,1,3,3,8,0,4,8,8,4,7,0,1,1,6,2,1,0,8,2,0,4,4,4,5,4,0,7,7,8,5,5,0,0,0,1,8,8,7,4,7,9,
+1,7,2,6,1,6,7,6,2,9,6,2,5,7,7,8,1,5,7,3,3,4,9,8,7,6,5,5,2,8,7,8,7,1,6,0,5,2,2,4,2,3,3,2,0,0,3,4,5,2,2,9,2,9,7,7,9,5,9,0,1,5,3,0,
+7,4,1,9,4,5,0,6,7,4,1,2,7,4,0,8,8,3,7,0,5,3,2,2,4,2,7,0,0,5,0,4,6,9,6,2,2,4,5,3,4,4,2,8,7,3,9,4,5,8,5,2,9,4,1,3,2,9,2,2,4,3,9,8,
+6,7,8,8,8,8,9,1,1,5,0,5,5,4,2,0,3,0,4,2,1,0,2,6,2,8,1,4,1,6,8,0,0,5,1,3,8,0,2,3,6,6,3,3,4,8,9,2,8,3,1,3,7,2,1,4,9,9,4,4,3,1,2,1,
+0,9,9,6,9,3,9,7,5,3,9,3,0,2,9,6,2,2,5,6,8,2,9,6,8,3,6,7,4,4,3,8,6,1,2,6,6,0,9,0,0,9,3,9,9,8,4,8,6,8,0,6,1,3,0,8,4,3,5,3,0,6,2,2,
+1,7,1,4,3,5,6,3,7,2,3,1,6,3,5,2,9,3,7,0,6,9,6,5,3,9,6,0,2,3,1,0,6,2,5,8,2,3,0,0,0,4,3,9,4,6,3,5,2,0,3,8,8,2,8,2,5,6,9,7,3,2,9,9,
+5,5,4,0,2,4,0,4,5,2,7,6,6,8,5,3,5,5,2,7,3,8,7,5,5,3,6,0,8,6,3,1,7,4,7,1,0,4,3,0,7,9,5,0,6,0,7,3,3,8,2,5,1,4,4,1,6,4,2,5,5,6,8,0,
+8,5,9,6,7,9,8,2,9,1,5,1,0,5,9,6,1,9,8,7,6,9,1,0,1,2,8,4,7,4,5,6,9,1,5,8,7,2,4,3,8,3,8,9,0,6,3,1,6,5,7,0,3,1,3,8,5,7,0,8,8,2,7,3,
+7,2,8,3,9,8,9,1,6,5,0,4,5,7,3,9,9,0,9,9,2,6,4,3,3,3,3,9,5,5,7,4,2,4,7,2,3,5,5,9,8,6,3,1,5,7,6,8,9,4,1,8,8,5,4,9,0,7,5,4,5,3,6,9,
+0,4,8,3,0,9,2,7,1,2,8,5,6,2,8,5,2,0,4,8,2,5,8,2,0,5,7,8,8,0,8,9,3,7,9,5,4,9,4,2,6,9,7,1,5,4,6,3,2,6,3,9,8,4,1,0,1,6,2,0,5,3,7,6,
+6,4,6,1,0,7,3,4,6,2,7,1,3,9,0,5,5,4,7,0,0,3,4,8,2,6,6,9,9,0,2,6,5,9,9,7,7,0,6,2,2,7,8,3,8,6,0,4,7,7,0,9,2,2,1,5,1,8,2,3,7,7,1,9,
+0,4,2,8,9,7,3,4,1,5,3,3,0,6,4,1,1,8,1,4,9,6,4,0,8,0,2,7,2,2,1,2,8,3,2,3,7,5,9,1,7,8,5,5,6,2,0,0,1,4,3,5,2,8,4,2,7,7,0,5,7,3,4,0,
+1,7,4,5,1,3,9,1,8,2,3,7,0,2,9,3,5,3,3,9,2,6,0,5,7,4,9,7,9,6,9,6,4,1,5,3,7,3,0,2,3,9,7,7,8,2,5,8,4,0,8,3,3,0,4,3,0,5,7,3,7,3,9,7,
+4,5,5,0,8,1,5,7,8,1,2,5,8,3,0,6,2,9,6,4,5,5,6,6,0,3,8,0,2,0,9,9,1,7,9,4,8,8,7,5,8,1,5,0,0,4,7,1,2,0,2,0,6,7,8,0,1,3,4,0,8,6,9,5,
+6,6,9,6,5,1,2,7,1,6,5,5,5,7,2,8,3,5,6,0,8,7,6,9,3,8,8,8,5,3,4,8,5,6,9,2,7,5,7,3,1,7,2,2,9,6,1,9,2,4,4,3,9,2,5,1,6,7,7,2,9,8,6,0,
+9,4,4,3,0,3,4,7,1,0,8,4,8,3,1,4,2,5,9,0,0,1,8,5,1,9,3,0,8,9,9,7,4,2,0,3,7,5,8,8,9,1,6,8,3,2,1,6,7,1,6,9,5,9,9,3,5,2,3,4,7,2,1,1,
+4,8,0,1,3,6,6,2,5,2,7,2,5,5,7,0,6,4,6,4,8,0,6,4,0,3,6,7,9,7,4,6,8,9,8,7,8,5,0,5,4,5,4,2,8,6,7,8,2,2,0,8,6,4,3,9,7,1,2,3,5,2,5,2,
+8,7,0,9,4,4,0,7,5,9,1,8,7,6,9,3,5,6,8,7,8,8,6,9,4,8,6,1,2,8,5,1,1,3,3,3,6,2,8,0,7,3,1,3,2,4,1,1,3,5,6,1,0,9,7,7,7,9,3,4,3,3,6,7,
+3,2,8,4,1,0,4,9,4,2,9,5,7,0,9,0,7,8,1,1,8,9,9,3,4,0,7,9,1,4,7,7,9,6,1,8,1,4,1,2,1,6,8,5,8,9,5,1,2,4,3,2,4,6,9,0,6,7,0,8,5,5,2,4,
+2,8,7,9,4,3,4,7,0,1,6,9,2,4,9,0,4,2,4,7,6,2,7,7,6,1,5,7,0,2,4,8,4,9,0,1,4,0,1,5,4,9,1,6,8,6,7,9,6,7,6,5,2,0,1,7,1,0,8,0,1,2,5,2,
+0,6,8,8,3,3,5,7,1,1,7,5,2,6,2,0,4,2,7,0,7,9,6,9,1,8,4,3,5,7,1,9,3,3,0,5,6,2,0,5,1,6,8,0,1,2,0,6,7,7,9,6,5,6,2,6,9,4,2,7,4,9,6,8,
+3,3,9,1,5,2,9,1,4,4,8,9,3,8,1,4,7,9,0,2,4,8,4,5,6,0,7,4,8,9,6,9,9,3,4,9,6,2,2,6,4,0,5,2,5,3,2,3,4,1,3,4,1,9,5,4,9,3,0,3,4,1,2,8,
+4,2,0,9,7,5,7,2,9,0,8,6,0,1,5,6,8,3,4,7,5,9,2,0,8,7,6,6,7,1,3,5,3,7,6,2,1,8,2,0,4,1,6,9,3,0,5,7,1,1,6,8,3,4,1,2,7,6,5,6,6,1,1,2,
+6,3,5,8,4,9,2,0,9,7,5,4,3,5,7,0,5,7,7,4,4,0,5,3,4,6,0,0,2,2,7,7,0,5,7,2,6,5,3,5,9,9,4,1,6,7,7,3,4,8,6,6,1,1,7,1,3,4,4,4,4,2,1,1,
+7,1,2,0,5,9,2,1,3,9,3,7,4,9,5,1,6,5,7,2,0,5,2,4,8,0,5,2,6,6,7,9,8,7,7,8,5,2,4,6,9,3,4,8,8,1,3,4,5,2,2,7,3,9,2,8,8,8,8,8,1,4,1,4,
+8,6,3,2,5,1,1,0,9,9,9,8,3,9,5,4,6,2,0,0,4,6,7,1,0,0,0,2,5,2,5,4,9,1,1,5,6,7,6,0,6,4,3,6,5,2,8,7,3,4,0,7,5,4,6,8,8,9,9,6,2,3,2,9,
+0,4,9,6,2,5,0,6,0,6,2,0,5,9,7,9,9,7,9,7,3,0,9,7,9,2,5,0,7,5,7,6,7,7,9,9,1,7,1,6,1,3,9,3,6,4,4,9,8,9,6,4,8,5,8,1,5,9,2,5,4,7,2,7,
+1,1,3,6,0,1,9,3,5,0,5,0,0,3,0,3,7,7,5,7,5,8,0,4,9,8,8,2,3,7,1,9,8,3,2,1,4,7,8,4,3,7,6,0,2,7,6,2,4,6,2,4,9,2,5,0,0,0,7,5,3,5,7,1,
+7,5,9,1,5,8,8,6,5,1,8,4,3,2,1,9,7,8,1,2,3,5,6,0,6,1,0,3,7,9,1,3,0,2,0,5,4,7,3,9,3,4,6,6,6,8,2,0,4,8,3,1,1,2,0,6,9,9,9,8,3,4,7,7,
+4,9,4,5,0,9,6,5,5,2,5,5,5,5,1,9,4,9,8,1,5,2,9,8,1,9,9,0,0,7,4,8,7,1,8,8,7,3,3,2,2,4,5,0,1,2,3,6,9,0,0,2,1,5,5,7,7,0,7,6,5,5,7,6,
+9,1,9,3,8,2,2,9,7,9,4,9,5,2,6,5,5,3,7,2,8,8,7,7,9,2,1,4,0,2,2,8,8,5,9,9,0,5,2,1,5,5,3,3,7,0,7,3,5,9,8,2,6,0,3,7,8,8,4,6,6,3,3,3,
+0,8,6,6,5,9,4,8,7,8,4,8,3,8,7,9,4,4,5,5,6,0,9,4,9,2,8,7,0,1,2,5,3,6,1,9,2,7,4,6,4,7,9,5,6,0,4,1,1,2,6,5,2,1,1,9,6,2,0,8,0,4,7,5,
+8,5,6,2,3,3,9,4,4,1,9,2,7,0,6,8,1,5,6,7,3,9,9,4,5,6,9,6,7,9,0,2,8,5,1,3,9,2,8,3,5,3,9,2,5,6,3,7,0,2,4,8,2,8,4,2,2,1,8,9,2,1,7,4,
+3,8,3,6,2,1,1,6,1,1,7,9,3,4,5,4,8,7,2,3,9,8,8,1,8,0,8,5,8,1,1,2,2,3,9,5,6,1,0,3,1,5,2,1,6,4,4,7,0,4,9,8,7,6,6,9,6,3,0,6,7,6,3,5,
+2,1,9,4,2,4,3,9,1,9,0,9,9,2,2,1,5,2,2,9,2,4,6,2,3,3,4,0,0,8,8,4,6,2,2,5,6,7,5,6,1,3,9,7,0,1,2,2,5,9,2,1,3,1,8,8,1,3,6,9,6,0,9,2,
+5,4,8,8,6,8,9,1,7,6,2,0,7,8,6,1,0,6,9,2,7,6,8,1,3,6,2,1,5,1,0,4,9,1,5,2,4,4,4,5,6,4,4,6,8,5,6,7,8,5,3,1,3,3,6,9,6,0,0,8,1,8,8,6,
+9,0,5,0,9,6,4,8,3,9,9,8,2,8,0,0,9,5,2,1,2,0,1,5,2,1,9,6,3,8,7,0,1,0,9,1,0,1,6,0,8,7,4,5,6,4,5,6,5,9,5,8,9,4,2,0,8,2,6,5,4,5,4,5,
+8,7,5,6,8,4,8,2,4,6,5,0,2,1,1,0,8,3,0,0,6,7,6,5,5,7,0,9,4,2,1,0,8,1,5,0,4,5,5,1,4,6,6,5,5,2,2,7,9,8,6,6,4,3,9,5,7,6,5,8,5,7,7,3,
+2,4,8,3,7,6,5,0,3,8,0,4,8,7,6,3,6,0,3,2,8,7,4,6,2,1,6,3,5,7,5,1,5,3,8,9,9,3,0,7,2,6,7,5,5,7,3,3,9,7,6,3,6,4,3,2,5,3,5,0,1,2,7,3,
+6,0,1,2,3,9,7,8,4,6,3,8,3,0,5,2,9,1,9,6,9,6,2,1,0,6,0,1,2,5,6,4,9,8,9,4,1,2,6,6,4,7,1,2,7,3,7,9,9,2,6,0,4,4,2,5,0,0,4,6,2,4,8,0,
+};
+
+const int32_t B[] = {
+1,1,9,1,9,6,7,6,2,8,2,8,5,6,3,0,2,4,0,1,7,5,9,1,7,4,7,3,2,2,8,0,3,1,3,7,1,9,2,5,6,5,2,3,7,1,6,3,3,2,1,4,2,4,8,9,4,0,8,3,6,4,0,9,
+6,1,6,9,1,4,3,4,2,3,4,8,0,0,1,2,7,7,9,6,1,5,8,7,6,7,1,8,0,2,7,1,4,5,7,4,2,7,6,0,0,1,7,9,0,4,3,8,8,9,4,3,4,7,6,3,4,0,8,9,5,1,1,7,
+3,3,4,7,0,4,1,5,2,1,2,5,6,6,1,4,4,2,8,7,5,4,0,5,8,1,7,2,3,4,7,7,6,3,1,5,6,2,8,5,7,8,7,7,9,3,5,9,9,1,1,1,6,8,5,5,9,7,9,5,8,9,0,9,
+2,9,2,2,4,4,6,7,4,7,4,2,4,2,7,2,2,2,9,6,7,2,1,5,0,9,5,2,8,6,8,6,2,7,8,2,0,1,0,2,9,0,3,9,9,6,9,2,1,7,1,1,4,6,7,9,8,8,5,3,1,1,8,5,
+2,2,8,2,0,6,7,3,0,1,2,0,5,2,6,9,3,5,2,0,9,7,6,7,2,5,2,3,0,6,0,4,5,1,6,4,7,8,0,1,0,7,1,6,6,5,4,7,2,3,0,3,8,0,7,4,5,0,3,8,6,3,5,0,
+9,1,3,8,5,9,4,9,0,2,9,7,1,1,0,8,4,7,8,5,3,2,3,0,9,8,3,7,5,8,8,5,9,5,6,5,2,7,3,3,7,2,2,7,0,0,4,9,8,8,0,6,0,9,3,9,6,5,7,0,8,2,2,3,
+4,3,2,5,2,0,4,6,7,1,5,1,6,4,1,0,4,6,1,1,3,8,8,9,1,1,9,9,7,5,0,8,5,5,9,0,4,1,7,5,2,2,7,8,5,1,1,0,0,2,0,1,7,9,2,0,3,7,7,8,6,9,4,0,
+6,0,4,1,4,2,0,2,5,4,0,6,9,9,1,1,8,7,5,0,3,3,8,6,1,1,3,1,9,2,4,6,2,5,6,6,8,4,6,1,3,0,7,1,3,3,0,3,3,2,7,4,6,0,6,7,7,7,0,4,9,4,9,4,
+1,9,5,5,4,5,7,7,2,4,9,4,6,0,3,5,2,6,8,0,3,0,5,5,1,6,9,2,6,9,7,3,8,0,6,1,0,0,4,4,2,3,3,7,8,1,7,4,7,0,9,2,1,4,2,7,0,3,0,7,7,7,4,0,
+5,0,9,9,7,4,0,5,7,3,7,5,2,4,4,9,5,4,5,7,5,1,2,1,3,8,8,5,1,6,6,3,9,8,1,1,9,4,7,9,8,8,4,5,0,9,5,3,0,3,5,7,4,2,5,5,2,9,9,7,7,9,2,3,
+4,9,9,2,5,3,1,7,6,2,5,2,5,9,3,1,1,9,0,3,1,1,2,5,0,7,6,0,4,0,0,5,5,9,8,4,1,0,9,8,9,7,1,5,8,5,7,1,1,3,7,1,3,4,7,8,7,8,8,5,2,7,5,5,
+0,9,7,2,6,8,5,7,0,3,6,9,1,2,5,7,7,2,9,6,6,9,7,1,0,6,6,4,3,3,7,1,8,0,7,2,8,9,2,1,0,1,7,9,5,7,6,8,5,4,0,1,7,9,8,9,0,5,4,9,8,5,5,9,
+9,9,3,4,5,3,7,5,7,3,3,2,1,5,7,5,0,8,4,5,8,9,4,3,9,8,2,6,3,9,3,1,3,6,5,3,9,0,8,4,5,5,5,9,4,0,9,6,0,4,4,6,2,5,8,2,0,9,0,0,0,0,7,9,
+4,9,3,6,2,7,0,5,9,6,9,4,8,6,2,1,9,0,2,2,6,9,5,0,5,8,7,6,3,8,6,9,8,9,8,2,8,2,9,4,2,7,2,6,6,9,0,1,9,8,9,0,0,5,3,5,8,7,9,1,4,9,8,1,
+3,5,1,8,4,8,7,4,0,4,9,8,0,8,6,7,0,7,9,1,6,6,4,8,2,0,8,9,7,8,9,0,1,4,2,0,9,4,9,5,3,0,4,0,6,8,2,0,3,9,7,4,8,3,4,9,4,6,9,6,2,9,9,6,
+5,2,1,9,2,2,6,4,4,3,4,4,6,0,2,9,0,8,4,6,3,4,1,6,6,5,4,4,5,0,0,3,4,4,1,1,4,9,8,0,1,6,2,6,1,3,7,3,4,1,5,9,0,1,9,2,7,3,6,7,1,4,7,7,
+7,7,9,0,8,0,2,4,2,3,7,5,7,4,2,0,8,8,3,7,1,4,7,2,7,9,4,3,0,8,1,6,9,8,6,0,3,4,7,8,8,6,7,1,7,9,9,9,6,0,3,9,4,8,8,3,8,9,5,0,4,4,4,7,
+7,8,3,4,5,8,1,6,7,5,2,0,9,5,9,7,1,8,6,4,4,9,3,8,6,2,8,3,0,7,6,5,9,6,5,8,0,9,8,7,4,4,1,1,8,7,8,7,2,2,8,8,3,1,9,2,2,5,8,6,3,3,7,8,
+1,3,6,6,2,8,8,1,2,5,2,4,8,3,8,5,0,8,4,9,9,3,4,4,3,6,6,7,3,3,8,5,0,9,6,9,0,2,5,8,9,3,1,0,8,8,4,4,3,5,9,8,6,1,2,0,9,4,2,9,4,0,0,1,
+8,1,7,6,0,2,2,7,6,0,1,7,6,9,0,9,7,8,4,9,6,2,4,3,3,8,8,8,5,6,3,2,2,7,1,7,8,6,6,1,4,0,8,3,5,0,0,3,5,2,3,4,2,4,9,2,1,0,4,3,3,2,0,5,
+3,8,0,3,8,6,8,3,8,8,7,2,5,4,6,5,5,8,2,8,8,1,4,0,8,9,3,2,0,9,7,2,9,4,6,2,5,0,2,5,9,1,7,7,9,9,4,5,3,7,6,3,3,9,4,8,5,4,6,4,0,8,8,2,
+0,0,8,9,8,3,3,9,7,2,6,9,2,9,4,6,8,3,8,7,7,6,4,7,8,5,8,6,1,3,0,2,2,9,4,8,0,1,3,6,4,2,9,2,1,4,7,0,3,8,5,6,6,1,6,2,0,0,2,4,1,4,4,4,
+6,8,7,2,1,9,3,3,8,5,8,2,7,5,9,8,5,6,5,9,8,6,3,2,7,1,1,2,7,6,7,1,1,6,8,5,0,8,4,4,3,6,8,1,7,6,0,9,2,6,0,2,2,8,6,2,6,9,7,3,3,3,5,4,
+6,0,5,0,9,4,5,1,9,8,1,4,5,7,2,2,9,0,3,7,3,2,9,2,6,5,3,7,2,6,1,3,1,5,7,1,4,6,0,6,4,9,1,5,0,1,8,0,5,9,8,5,2,1,0,7,3,2,5,8,1,7,5,3,
+0,5,8,3,4,8,3,3,6,1,2,9,6,8,3,6,6,9,8,1,5,2,0,9,6,7,1,7,6,3,0,9,0,3,5,6,2,4,2,8,2,7,5,7,6,5,2,2,0,2,8,9,3,6,7,6,1,5,2,9,0,1,7,5,
+9,0,0,5,5,8,3,0,9,7,6,8,5,7,2,4,9,8,2,2,8,3,1,6,5,1,8,6,2,0,8,5,5,8,0,3,1,8,0,0,6,8,4,1,4,1,5,0,0,9,0,0,2,2,3,3,1,8,6,6,3,7,1,3,
+6,6,0,9,4,8,7,5,0,3,1,4,0,1,1,2,8,7,4,4,8,3,1,1,6,3,7,9,2,0,8,9,6,5,8,7,0,8,8,6,3,4,9,1,5,0,9,8,8,2,0,4,2,5,7,0,7,5,1,6,5,8,6,9,
+9,6,7,5,2,9,9,1,7,1,0,4,4,9,5,8,9,3,2,8,4,0,7,3,5,8,2,6,2,1,7,0,5,0,1,9,3,2,7,7,4,1,6,4,9,6,3,5,6,8,2,5,3,9,1,5,3,2,7,1,9,1,2,8,
+1,0,7,9,9,1,7,7,0,5,6,8,6,8,7,4,9,6,3,7,9,3,2,5,2,4,6,7,8,9,7,5,6,9,7,4,3,7,0,1,7,1,1,7,8,4,9,8,7,1,0,2,6,8,4,9,1,9,1,3,9,7,4,5,
+1,9,7,9,0,0,4,3,2,4,4,8,0,6,1,8,8,2,0,9,0,7,0,5,4,8,9,8,7,7,8,5,9,2,6,2,2,9,6,7,1,1,1,7,7,4,3,0,8,5,5,0,1,1,0,9,3,8,3,0,9,3,8,7,
+4,7,5,5,2,4,5,1,3,4,6,7,7,4,3,0,7,7,8,4,0,3,4,9,0,4,6,6,4,3,9,5,5,5,2,6,2,1,8,0,8,5,0,8,2,5,7,2,6,4,3,4,7,4,3,5,0,0,1,3,0,6,7,4,
+1,7,8,7,4,6,1,9,2,1,3,1,4,5,8,6,8,0,2,8,8,7,6,5,5,4,3,7,0,0,3,6,7,8,2,4,0,0,7,0,8,0,8,7,1,2,1,5,4,0,6,9,4,6,0,4,0,6,6,4,6,2,3,8,
+3,2,5,5,6,6,0,8,2,5,8,5,8,9,8,6,6,2,5,0,4,4,5,9,6,3,9,5,7,6,1,6,2,6,5,8,2,2,4,1,0,6,2,1,9,7,9,5,9,7,8,3,1,2,1,0,7,5,4,4,6,4,5,8,
+1,4,1,3,8,8,1,0,5,0,2,4,8,3,4,0,7,0,0,9,6,6,0,3,8,3,2,8,2,3,5,5,4,9,5,3,7,9,8,6,6,3,4,6,7,7,3,1,1,5,4,2,0,9,5,1,4,5,4,0,8,2,4,8,
+5,4,4,9,9,1,0,6,9,8,4,6,0,3,8,9,4,9,5,6,2,7,0,5,7,8,0,3,7,0,1,3,1,4,7,4,7,6,3,4,7,2,4,8,9,2,4,1,7,1,9,9,5,5,4,0,5,4,5,8,6,8,1,2,
+9,0,0,2,7,4,2,1,3,1,7,3,6,2,5,9,3,8,5,5,8,8,2,9,3,5,2,6,9,3,0,4,3,7,8,3,7,2,6,5,8,2,9,7,1,1,9,0,8,5,8,0,1,3,1,5,9,8,1,9,1,9,2,9,
+6,7,5,6,2,5,7,6,0,9,5,7,4,3,0,6,1,8,7,9,5,7,2,8,1,5,4,3,4,7,4,7,5,0,0,4,2,8,0,2,9,9,5,1,7,3,0,7,3,3,3,0,9,7,6,8,5,6,0,2,1,5,3,5,
+7,7,8,2,6,6,6,8,2,9,8,3,7,5,7,9,2,1,4,8,0,4,7,6,1,7,1,0,8,3,5,7,9,1,0,9,5,9,6,6,7,1,8,1,5,6,9,6,0,1,2,9,9,7,8,2,5,8,6,1,5,2,9,3,
+1,7,5,1,6,1,4,2,8,5,1,7,0,3,0,4,1,3,2,8,0,3,6,1,8,9,4,1,7,1,2,0,3,8,7,8,1,6,9,6,5,7,6,3,3,3,9,8,2,1,0,6,6,2,4,2,5,0,8,2,6,4,6,3,
+2,6,1,2,4,1,3,3,9,5,8,6,2,1,4,7,7,3,1,6,4,3,2,5,8,9,9,6,5,0,0,3,1,1,4,2,7,6,4,8,9,8,1,5,6,7,0,3,3,6,4,8,8,8,8,9,3,8,3,5,5,4,4,5,
+2,3,0,1,6,0,0,1,6,3,0,9,6,8,9,5,1,4,0,7,0,5,5,2,2,8,5,1,8,2,9,9,1,9,4,5,9,6,6,5,9,2,7,6,4,4,5,2,9,5,4,6,8,4,0,7,6,1,5,3,0,9,5,1,
+2,5,4,4,4,8,2,8,8,6,6,9,6,4,1,7,7,8,1,6,8,7,9,4,2,4,1,4,2,0,5,8,8,9,6,9,7,6,1,0,9,7,1,5,2,0,7,7,3,4,5,1,0,7,3,1,5,4,4,9,6,1,0,8,
+2,6,8,2,6,9,8,4,3,6,5,9,8,0,0,6,7,1,8,4,0,1,8,1,2,8,2,2,2,8,1,6,1,5,9,8,9,5,6,3,2,1,4,2,9,3,2,0,9,6,8,8,3,3,7,6,7,0,0,4,8,4,0,6,
+9,8,0,2,7,2,8,4,0,6,1,8,3,9,8,4,0,0,6,3,0,5,9,8,0,6,8,5,1,9,7,5,4,8,5,5,1,4,3,2,4,5,5,0,5,5,3,8,0,2,5,2,1,3,1,6,1,6,8,2,8,4,1,3,
+1,0,1,5,5,2,9,9,4,1,0,0,3,6,4,0,8,5,0,6,2,9,4,5,6,2,8,8,5,5,6,0,7,4,6,3,6,9,6,1,4,3,5,4,0,3,2,6,6,5,8,1,5,7,3,0,4,5,4,8,0,0,5,4,
+5,7,1,4,4,4,2,7,3,2,7,7,8,6,5,1,1,0,3,1,4,6,7,3,7,1,6,3,7,5,6,6,8,4,9,1,2,7,3,0,2,8,8,3,9,3,7,2,8,5,0,9,4,5,1,3,4,6,6,8,6,9,7,7,
+1,4,8,6,7,9,7,5,6,7,4,2,0,5,4,8,2,2,4,3,4,2,3,7,2,0,4,9,6,9,1,2,6,3,2,0,4,9,9,4,9,7,7,8,4,3,4,7,8,4,9,1,9,3,1,3,4,2,5,6,2,2,8,6,
+3,5,9,4,5,9,7,1,6,7,7,3,1,9,3,2,8,5,7,7,8,1,7,7,0,0,2,3,7,3,6,8,6,3,7,6,6,3,6,0,1,9,9,3,0,9,2,2,3,0,2,6,3,3,2,8,5,6,2,6,9,6,7,0,
+6,5,6,4,9,5,8,1,4,2,1,7,0,7,2,9,7,7,3,8,3,2,3,7,0,0,2,7,6,7,0,6,6,8,4,9,8,5,6,3,4,4,7,0,6,6,8,2,0,4,8,2,4,2,6,0,9,7,0,9,5,2,4,1,
+4,5,1,2,4,3,7,7,9,5,0,7,3,2,0,8,4,1,6,5,9,8,8,1,2,3,4,0,2,4,0,3,2,6,1,0,9,2,2,3,4,0,7,3,3,0,4,7,7,1,2,9,7,8,5,5,6,3,4,1,8,9,3,5,
+1,2,9,2,1,6,5,1,5,7,5,0,2,6,5,7,6,6,8,9,1,8,3,3,6,8,2,3,0,7,8,0,9,9,8,9,7,6,1,8,8,3,7,5,5,7,6,5,5,9,0,8,6,3,1,9,5,6,2,3,4,9,2,7,
+5,1,9,8,5,2,6,7,8,7,1,2,1,1,6,8,0,0,1,0,4,3,1,8,3,4,1,8,4,7,3,3,0,3,6,7,7,5,6,3,0,7,6,7,9,3,9,4,1,9,1,2,1,8,8,9,6,6,1,0,8,9,8,6,
+9,4,9,5,4,3,6,1,2,9,8,6,9,1,4,4,6,0,3,6,4,6,5,0,4,2,0,1,6,8,2,6,4,6,5,5,6,8,6,8,8,2,9,9,2,9,7,4,9,3,1,3,2,1,2,2,5,8,2,2,4,2,7,0,
+5,1,3,4,8,7,2,7,3,2,1,4,0,0,4,8,5,6,6,7,9,0,7,6,0,8,1,2,3,0,5,9,1,3,6,1,8,2,7,1,7,5,9,5,1,9,5,9,1,8,5,0,8,2,9,0,8,1,6,9,1,5,1,8,
+4,6,2,3,5,2,7,1,6,9,9,5,2,6,1,3,6,3,3,3,7,6,5,1,4,6,2,3,0,6,0,7,4,6,0,1,9,1,5,3,3,7,3,9,0,2,8,8,8,1,1,9,0,9,7,5,3,8,8,6,7,4,0,9,
+7,8,8,4,4,9,3,1,1,5,2,7,5,6,2,2,9,3,0,8,1,7,1,8,5,5,3,0,9,9,6,4,6,0,4,2,3,6,2,8,4,8,4,9,9,6,1,0,0,0,6,1,9,7,7,2,8,4,7,8,4,4,6,2,
+2,4,9,4,4,3,2,9,1,4,5,2,2,4,1,9,0,0,8,0,1,5,8,5,9,0,8,3,7,8,3,3,2,1,9,5,6,0,7,6,2,1,8,4,4,4,3,2,9,3,2,8,4,1,6,3,6,2,1,4,3,0,0,5,
+9,4,8,3,1,9,6,4,0,9,7,7,6,3,9,4,0,3,2,2,1,9,0,6,5,2,0,7,8,3,3,4,6,0,6,0,0,5,7,8,3,4,6,5,8,2,7,8,9,7,9,0,8,1,9,8,5,7,4,4,9,8,5,7,
+3,3,3,1,4,2,9,1,7,3,7,7,9,2,7,3,1,8,6,3,6,2,0,2,0,7,6,9,6,1,9,6,2,3,7,0,1,6,7,0,0,5,8,1,0,2,2,5,8,3,3,4,1,6,8,9,3,8,0,9,2,1,6,6,
+0,7,1,3,6,0,7,0,3,9,4,1,5,2,6,3,7,6,1,3,8,4,6,3,3,4,6,6,0,6,5,6,3,6,9,4,4,0,0,8,0,5,3,7,4,0,9,4,2,2,9,1,8,7,5,3,8,6,1,9,9,8,9,0,
+4,8,3,0,7,6,1,6,3,7,6,5,0,1,3,4,7,3,7,0,7,8,2,8,4,0,3,3,3,2,6,3,9,1,2,6,5,6,1,7,2,8,8,5,8,0,1,4,3,8,4,4,5,6,3,4,2,9,1,7,4,0,4,5,
+8,4,8,6,5,5,1,2,2,9,9,2,4,7,0,1,1,8,6,2,9,1,7,0,8,9,3,2,6,9,1,4,6,6,2,8,1,6,7,3,0,7,7,4,3,9,3,5,6,5,6,5,8,9,5,3,1,0,9,5,4,6,7,6,
+7,8,3,7,7,2,5,3,4,1,7,3,8,0,0,5,2,3,6,4,5,2,0,3,3,3,1,2,6,1,1,1,4,7,6,0,4,9,1,2,8,5,0,3,3,2,5,0,1,4,5,9,0,3,6,8,2,2,4,1,2,3,7,3,
+9,5,2,1,0,7,2,1,3,5,2,3,0,5,6,2,2,9,0,4,1,6,5,3,0,4,8,2,2,1,2,1,2,2,1,7,7,2,0,3,4,7,3,6,8,0,9,0,0,8,3,2,0,4,6,7,9,6,0,1,7,1,7,6,
+};
+
+const int32_t C[] = {
+1223,1282,1286,1163,1319,1270,1192,1100,1142,1261,1291,1367,1260,1311,985,1232,1313,1316,1148,1320,1277,1275,1145,1199,1157,1203,1225,1211,1177,1281,1164,1239,1209,1454,1377,1145,1189,1335,1306,1108,1302,1233,1421,1194,1339,1065,1322,1063,1169,979,1109,1155,976,1341,1258,1173,1250,1486,1204,1322,1273,1303,1130,1377,
+1184,1267,1312,1237,1443,1455,1188,1232,1260,1222,1312,1451,1244,1331,1078,1464,1396,1375,1279,1437,1466,1272,1208,1262,1248,1352,1314,1335,1209,1309,1263,1277,1264,1509,1546,1222,1369,1428,1334,1090,1392,1323,1378,1303,1411,1190,1443,1195,1305,1244,1177,1218,1132,1317,1370,1300,1356,1338,1210,1421,1310,1349,1236,1435,
+1162,1146,1395,1317,1216,1378,1119,1124,1091,1251,1202,1479,1236,1287,1005,1364,1472,1348,1223,1445,1362,1273,1148,1252,1226,1323,1226,1294,1205,1235,1192,1299,1135,1351,1441,1303,1192,1422,1313,1142,1138,1213,1390,1262,1400,1148,1242,1149,1390,1197,1230,1127,1164,1269,1347,1231,1377,1294,1109,1386,1400,1285,1202,1375,
+1085,1269,1161,1032,1288,1306,1093,1075,1208,1217,1133,1354,1087,1180,994,1148,1230,1282,1151,1255,1213,1176,1122,1190,1027,1230,1284,1184,1022,1073,1237,1162,1222,1300,1273,1038,1101,1271,1263,1053,1266,1276,1277,1185,1288,1092,1256,1066,1070,1100,1139,1110,1041,1201,1214,1307,1153,1334,1146,1282,1220,1292,1202,1281,
+953,1262,1262,1113,1165,1134,1165,1034,1155,1150,1092,1340,1127,1129,991,1264,1190,1241,1146,1305,1178,1086,1038,1146,925,1348,1187,1146,1084,1170,1147,1201,1109,1331,1327,1101,1191,1195,1240,1088,1269,1097,1275,1367,1394,1097,1289,1092,1121,1008,1014,1078,1185,1328,1277,1274,1192,1304,1097,1331,1288,1287,1139,1227,
+1201,1282,1518,1325,1281,1510,1265,1336,1105,1327,1407,1443,1225,1295,1066,1483,1340,1349,1354,1403,1371,1315,1151,1265,1189,1335,1343,1363,1137,1399,1248,1254,1465,1378,1333,1240,1131,1468,1371,1139,1253,1175,1496,1213,1473,1246,1402,1272,1330,1226,1126,1186,1212,1376,1462,1329,1229,1447,1227,1339,1347,1301,1240,1524,
+1377,1419,1524,1328,1441,1503,1332,1263,1372,1402,1486,1771,1459,1449,1219,1424,1629,1493,1295,1539,1427,1451,1453,1399,1276,1583,1497,1480,1279,1354,1389,1403,1376,1571,1552,1346,1348,1654,1440,1173,1324,1504,1554,1499,1542,1332,1499,1277,1431,1402,1203,1382,1206,1560,1479,1448,1313,1516,1372,1582,1508,1404,1374,1553,
+1180,1190,1170,1150,1253,1280,1261,1120,1132,1291,1259,1295,1148,1178,936,1279,1199,1307,1136,1266,1352,1219,1137,1104,1051,1323,1299,1210,1202,1416,1149,1190,1192,1345,1331,1059,1264,1186,1238,1078,1212,1136,1433,1338,1238,1081,1314,980,1253,1209,1241,996,1074,1264,1301,1235,1360,1275,1076,1355,1130,1254,1272,1195,
+1159,1328,1348,1187,1256,1466,1220,1187,1064,1249,1357,1457,1216,1173,1179,1494,1289,1263,1350,1375,1310,1373,1248,1356,1142,1296,1226,1265,1158,1135,1179,1185,1210,1338,1376,1222,1213,1348,1378,1129,1272,1097,1444,1236,1363,1248,1324,1170,1316,1302,1266,1319,1195,1216,1356,1352,1313,1320,1173,1359,1298,1234,1253,1485,
+1134,1192,1510,1136,1287,1364,1271,1096,1336,1308,1148,1414,1194,1245,1032,1431,1381,1276,1130,1384,1336,1264,1240,1175,1239,1336,1183,1249,1064,1289,1208,1102,1247,1302,1428,1224,1265,1470,1235,1161,1156,1305,1444,1343,1369,1177,1340,1132,1237,1177,1092,1239,1110,1324,1379,1318,1259,1278,1188,1466,1312,1262,1205,1355,
+1266,1520,1489,1292,1362,1379,1379,1383,1309,1375,1416,1341,1262,1346,1139,1468,1367,1283,1245,1376,1341,1328,1405,1194,1162,1568,1256,1316,1109,1523,1281,1251,1550,1493,1500,1225,1303,1342,1463,1098,1279,1224,1440,1471,1384,1199,1433,1338,1395,1243,1313,1311,1093,1536,1311,1466,1223,1480,1327,1313,1491,1332,1396,1461,
+1324,1267,1330,1251,1403,1288,1188,1214,1312,1302,1313,1591,1341,1331,1203,1456,1421,1408,1342,1529,1301,1337,1204,1372,1206,1499,1416,1278,1280,1291,1305,1313,1258,1588,1452,1262,1314,1473,1316,1285,1467,1271,1521,1386,1488,1250,1570,1182,1258,1285,1140,1369,1305,1405,1438,1359,1400,1532,1314,1458,1338,1451,1351,1364,
+1508,1591,1551,1501,1560,1630,1454,1467,1378,1516,1488,1608,1383,1444,1297,1613,1483,1759,1421,1635,1655,1449,1270,1550,1260,1637,1451,1499,1405,1380,1486,1452,1522,1566,1612,1445,1283,1683,1534,1209,1565,1462,1665,1582,1626,1309,1625,1376,1302,1344,1358,1280,1260,1595,1679,1500,1399,1654,1363,1613,1365,1399,1545,1702,
+1128,1402,1315,1329,1340,1389,1269,1399,1237,1236,1196,1382,1177,1206,1166,1486,1421,1321,1176,1538,1402,1373,1244,1194,1180,1494,1352,1365,1053,1302,1324,1224,1425,1421,1437,1106,1273,1479,1411,1069,1432,1156,1353,1414,1474,1224,1352,1368,1351,1155,1216,1164,1160,1468,1376,1301,1283,1407,1340,1365,1333,1314,1222,1562,
+990,1242,1037,945,1056,1066,1122,1041,1072,1106,1025,1176,971,1006,867,1205,1076,1045,1000,1134,1225,1119,1020,1013,914,1099,1048,1067,931,982,1033,1069,1108,1191,1107,972,1094,1217,1063,856,1183,1130,1222,1157,1123,796,1215,1122,1048,969,815,1089,996,1210,1176,1192,1055,1217,1003,1157,1077,1052,1133,1251,
+1284,1200,1269,1326,1294,1339,1278,1318,1181,1223,1209,1465,1143,1136,1127,1486,1193,1233,1248,1465,1402,1356,1180,1231,1176,1432,1200,1408,1160,1184,1267,1200,1191,1474,1389,1208,1165,1362,1425,1053,1281,1076,1472,1331,1252,1040,1517,1310,1238,1248,1084,1152,967,1341,1425,1250,1309,1399,1241,1257,1382,1239,1175,1577,
+1157,1371,1479,1324,1290,1274,1173,1187,1301,1333,1326,1392,1165,1215,985,1438,1376,1284,1211,1396,1195,1319,1162,1383,1117,1438,1185,1208,1183,1294,1112,1369,1307,1449,1440,1203,1413,1294,1443,1230,1321,1264,1402,1575,1427,1266,1471,1020,1234,1245,1201,1196,1241,1327,1444,1219,1381,1343,1251,1407,1293,1369,1284,1303,
+1316,1298,1260,1190,1373,1338,1219,1183,1240,1283,1256,1493,1236,1335,1122,1382,1292,1488,1302,1486,1338,1254,1162,1173,1297,1483,1244,1220,1166,1161,1344,1272,1290,1480,1411,1317,1103,1441,1318,1080,1426,1259,1527,1254,1328,1124,1486,1371,1274,1181,1027,1319,1105,1419,1442,1367,1249,1373,1263,1297,1258,1317,1227,1527,
+1421,1598,1719,1432,1649,1684,1592,1420,1513,1671,1607,1690,1512,1581,1246,1737,1578,1567,1514,1660,1608,1495,1644,1490,1460,1731,1507,1492,1354,1732,1465,1436,1612,1657,1650,1527,1527,1676,1606,1398,1527,1522,1674,1585,1600,1498,1731,1449,1478,1458,1463,1573,1379,1600,1567,1585,1439,1563,1439,1575,1620,1505,1612,1670,
+1491,1497,1680,1447,1639,1595,1469,1385,1371,1551,1666,1664,1403,1545,1403,1621,1512,1657,1560,1631,1536,1573,1433,1514,1314,1649,1409,1603,1415,1605,1462,1469,1523,1675,1690,1356,1478,1533,1601,1331,1565,1380,1688,1687,1424,1429,1693,1375,1481,1428,1447,1426,1364,1620,1623,1724,1355,1714,1367,1620,1474,1547,1523,1614,
+1090,1249,1258,1115,1331,1239,1173,1167,1179,1179,1203,1371,1159,1269,1009,1150,1245,1181,1104,1338,1191,1301,1036,1221,1125,1263,1207,1256,1169,1232,1197,1194,1278,1346,1321,997,1116,1309,1316,1143,1253,1186,1246,1267,1269,1089,1401,1067,1059,1099,1098,1109,1089,1309,1330,1325,1136,1422,1227,1181,1224,1284,1296,1325,
+1083,1217,1287,1048,1226,1301,1124,1133,1146,1134,1156,1229,1271,1223,1073,1232,1203,1169,1079,1252,1233,1235,1179,1147,1137,1240,1198,1207,1135,1142,1101,1184,1170,1434,1480,1202,1022,1193,1354,1134,1161,1055,1393,1101,1390,1119,1408,1067,1225,1142,1141,1134,982,1215,1252,1163,1391,1336,1110,1216,1293,1274,1213,1374,
+1176,1248,1367,1209,1350,1327,1126,1169,1186,1257,1147,1409,1134,1158,1140,1539,1249,1262,1208,1267,1171,1228,1130,1483,1033,1346,1135,1305,1283,1225,1075,1250,1112,1364,1485,1199,1257,1356,1297,1102,1262,1223,1307,1367,1397,1109,1360,1064,1102,1259,1421,1132,1150,1122,1323,1293,1342,1352,1120,1478,1299,1183,1290,1328,
+1358,1196,1378,1279,1255,1332,1182,1268,1170,1229,1412,1412,1192,1322,1065,1309,1291,1437,1206,1262,1288,1387,1202,1326,1237,1347,1386,1400,1304,1272,1176,1260,1337,1353,1438,1130,1291,1371,1493,1071,1218,1283,1566,1423,1335,1169,1460,1183,1396,1247,1090,1229,1152,1443,1453,1404,1296,1502,1227,1393,1356,1435,1306,1545,
+970,1102,1135,1132,1034,1115,1110,1029,968,1150,1057,1154,1067,1083,1050,1148,1048,1194,1057,1091,1223,1172,1002,1175,842,1109,1236,1167,1003,1080,1207,1133,1084,1245,1215,1080,1015,1208,1115,949,1090,1113,1203,1106,1225,993,1243,1012,1082,1110,1004,989,1072,1076,1100,1213,1163,1220,937,1160,1132,1206,1271,1157,
+1280,1299,1484,1423,1264,1417,1198,1259,1318,1303,1342,1413,1185,1310,1112,1504,1318,1388,1303,1392,1330,1217,1124,1375,1184,1439,1286,1431,1277,1300,1269,1324,1198,1410,1436,1153,1171,1297,1529,1139,1252,1276,1397,1376,1339,1280,1301,1146,1227,1303,1277,1239,1122,1313,1444,1336,1289,1461,1322,1437,1257,1302,1310,1431,
+1213,1324,1265,1154,1335,1331,1249,1177,1102,1299,1174,1296,1159,1095,1117,1293,1148,1228,1118,1345,1221,1292,1112,1155,1161,1335,1152,1185,1161,1244,1133,1151,1287,1381,1380,1096,1145,1420,1294,1142,1364,1169,1359,1304,1370,1133,1458,1201,1186,1127,1257,1200,1028,1197,1323,1221,1332,1368,1115,1191,1290,1125,1327,1335,
+1100,1107,1206,1076,1070,1217,1152,1037,976,1124,1102,1303,1049,1040,882,1175,1105,1061,1042,1170,1089,1200,1062,1149,1001,1083,1126,1249,1103,1233,1170,1129,1187,1130,1274,933,1092,1276,1166,982,1200,1136,1238,1307,1227,953,1190,1037,1182,1145,936,850,1108,1180,1121,1178,1162,1225,1059,1234,1170,1117,1057,1164,
+1304,1421,1468,1398,1297,1510,1405,1379,1285,1250,1266,1486,1317,1492,1127,1487,1396,1510,1326,1485,1468,1341,1380,1525,1189,1391,1401,1442,1377,1416,1318,1342,1377,1510,1619,1288,1212,1407,1511,1086,1297,1355,1607,1403,1533,1261,1387,1344,1291,1234,1317,1152,1280,1513,1394,1379,1461,1464,1440,1650,1456,1457,1417,1467,
+1311,1229,1205,1189,1294,1243,1263,1098,1123,1304,1394,1277,1192,1149,1133,1228,1157,1342,1180,1163,1268,1249,1113,1244,1099,1237,1215,1302,1102,1304,1141,1175,1185,1392,1483,1056,1062,1223,1203,1080,1165,1221,1384,1235,1295,1041,1492,1081,1176,1246,1169,1099,897,1234,1279,1242,1253,1482,1052,1325,1231,1235,1262,1267,
+1040,1219,1342,1241,1334,1251,1081,1293,1204,1209,1230,1364,1124,1250,975,1353,1284,1270,1159,1251,1291,1236,1125,1121,1154,1273,1190,1220,1133,1240,1114,1134,1208,1417,1376,1149,1219,1342,1313,1052,1175,1109,1288,1249,1294,1029,1356,1157,1294,1130,1236,1131,1045,1275,1329,1190,1158,1222,1145,1239,1212,1243,1217,1354,
+1330,1514,1426,1478,1427,1534,1396,1449,1113,1412,1455,1612,1408,1417,1252,1604,1356,1498,1443,1472,1434,1509,1309,1542,1292,1482,1586,1417,1344,1534,1440,1396,1500,1590,1601,1427,1239,1447,1447,1338,1503,1249,1509,1459,1763,1201,1585,1278,1501,1317,1409,1322,1357,1424,1436,1494,1504,1462,1386,1541,1526,1580,1334,1504,
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+1030,1264,1235,1155,1239,1140,1107,1169,1228,1181,1199,1289,1264,1173,908,1223,1267,1189,1040,1262,1244,1091,1075,1137,1063,1274,1222,1202,1090,1111,969,1306,1205,1427,1291,1148,953,1258,1254,1058,1239,1108,1343,1147,1290,1008,1357,1026,1152,999,1101,1209,994,1239,1195,1079,1115,1298,1073,1232,1165,1155,1254,1254,
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+1238,1391,1654,1282,1535,1583,1349,1371,1349,1438,1396,1503,1400,1483,1352,1670,1451,1452,1393,1511,1507,1553,1343,1431,1373,1456,1367,1364,1333,1462,1290,1251,1432,1511,1557,1338,1462,1445,1472,1429,1484,1300,1658,1546,1579,1316,1561,1295,1411,1270,1516,1399,1360,1430,1484,1458,1469,1569,1336,1635,1471,1468,1405,1548,
+1328,1454,1420,1339,1301,1584,1286,1280,1242,1267,1371,1399,1361,1255,1125,1574,1424,1452,1350,1505,1338,1342,1278,1317,1284,1571,1323,1374,1275,1421,1342,1274,1397,1487,1589,1303,1386,1468,1493,1298,1385,1243,1476,1502,1498,1285,1414,1261,1274,1307,1370,1280,1183,1533,1502,1422,1490,1479,1370,1480,1419,1377,1417,1481,
+1222,1364,1443,1416,1382,1408,1431,1338,1335,1312,1306,1510,1331,1404,1159,1485,1364,1526,1255,1513,1490,1320,1246,1408,1261,1466,1481,1469,1303,1305,1353,1331,1239,1519,1619,1349,1219,1522,1492,1206,1306,1366,1531,1346,1561,1139,1528,1252,1285,1321,1207,1237,1181,1438,1533,1434,1404,1478,1258,1462,1425,1431,1400,1589,
+1207,1377,1473,1278,1359,1422,1204,1284,1197,1383,1316,1329,1130,1287,1145,1371,1422,1446,1296,1427,1422,1393,1162,1300,1248,1385,1149,1205,1164,1347,1224,1188,1328,1362,1530,1244,1269,1378,1281,1228,1304,1222,1561,1470,1516,1302,1417,1272,1254,1233,1184,1200,1226,1510,1500,1344,1353,1468,1197,1424,1285,1343,1358,1503,
+1191,1379,1246,1083,1210,1174,1160,1093,1102,1200,1219,1429,1167,1147,923,1368,1318,1166,1231,1362,1215,1256,1084,1156,1002,1320,1218,1141,1110,1254,1116,1175,1212,1297,1225,1082,1283,1247,1229,1081,1218,1143,1336,1235,1273,986,1269,1137,1107,975,1089,1161,1112,1296,1385,1268,1172,1429,1053,1191,1338,1190,1197,1337,
+1259,1436,1359,1390,1411,1479,1330,1340,1282,1402,1434,1360,1272,1425,1205,1464,1312,1423,1284,1440,1498,1374,1303,1352,1285,1402,1470,1302,1314,1571,1313,1321,1376,1566,1517,1295,1295,1339,1354,1200,1421,1357,1432,1424,1544,1293,1445,1228,1226,1258,1330,1254,1275,1477,1365,1285,1438,1490,1414,1492,1384,1388,1358,1277,
+1203,1315,1492,1177,1365,1245,1219,1234,1241,1305,1174,1385,1160,1270,1017,1348,1315,1297,1118,1263,1216,1289,1330,1083,1083,1391,1298,1197,1140,1290,1254,1276,1399,1398,1534,1247,1368,1413,1429,1207,1287,1267,1412,1361,1376,1170,1480,1240,1385,1103,1117,1211,1131,1291,1320,1385,1357,1369,1198,1306,1478,1417,1300,1326,
+1277,1318,1539,1185,1440,1354,1365,1235,1312,1446,1350,1412,1227,1379,1083,1407,1381,1347,1233,1348,1337,1269,1350,1304,1212,1405,1226,1215,1164,1413,1163,1254,1348,1431,1470,1297,1250,1341,1255,1221,1268,1348,1484,1347,1474,1210,1514,1269,1228,1253,1159,1259,1213,1468,1432,1361,1359,1421,1314,1402,1464,1348,1241,1340,
+1276,1309,1326,1354,1357,1323,1325,1275,1202,1251,1403,1463,1174,1212,1064,1536,1341,1326,1305,1491,1351,1375,1168,1253,1217,1436,1278,1363,1195,1441,1184,1246,1358,1420,1478,1120,1412,1381,1337,1141,1416,1238,1449,1368,1412,1217,1425,1182,1378,1282,1199,1218,1140,1381,1329,1357,1345,1478,1152,1357,1294,1417,1230,1416,
+1071,1204,1308,1204,1446,1269,1175,1132,1209,1188,1315,1368,1169,1283,1042,1331,1380,1409,1113,1452,1307,1186,1166,1205,1120,1335,1265,1279,1207,1236,1194,1144,1336,1483,1401,1154,1251,1352,1293,1073,1423,1138,1343,1257,1280,1237,1323,1077,1118,1105,1228,1177,1158,1301,1205,1194,1234,1343,1162,1376,1295,1242,1234,1213,
+};
+
+#define MATRIX_SIZE 64
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
index ea842d8a..6ed19c0c 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
@@ -5,57 +5,218 @@
 #include <stdio.h>
 #include <stdlib.h>
 
-
 #include "dma.h"
 #include "core_v_mini_mcu.h"
 #include "x-heep.h"
 #include "csr.h"
 #include "rv_plic.h"
 
-#define TEST_SINGULAR_MODE
+// TEST DEFINES AND CONFIGURATION
+
+#define TEST_SINGLE_MODE
+#define TEST_ADDRESS_MODE
 #define TEST_PENDING_TRANSACTION
 #define TEST_WINDOW
-#define TEST_ADDRESS_MODE
 #define TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
-#define TEST_DATA_SIZE      16
-#define TEST_DATA_LARGE     1024
-#define TRANSACTIONS_N      3       // Only possible to perform transaction at a time, others should be blocked
-#define TEST_WINDOW_SIZE_DU  1024    // if put at <=71 the isr is too slow to react to the interrupt
+#define TEST_DATA_SIZE 16
+#define TEST_DATA_LARGE 1024
+#define TRANSACTIONS_N 3         // Only possible to perform one transaction at a time, others should be blocked
+#define TEST_WINDOW_SIZE_DU 1024 // if put at <=71 the isr is too slow to react to the interrupt
 
-
-
-#if TEST_DATA_LARGE < 2* TEST_DATA_SIZE
-    #errors("TEST_DATA_LARGE must be at least 2*TEST_DATA_SIZE")
+#if TEST_DATA_LARGE < 2 * TEST_DATA_SIZE
+#errors("TEST_DATA_LARGE must be at least 2*TEST_DATA_SIZE")
 #endif
 
 /* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
+#define PRINTF_IN_FPGA 1
+#define PRINTF_IN_SIM 0
 
 #if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
 #else
-    #define PRINTF(...)
+#define PRINTF(...)
 #endif
 
+// UTILITIES
+
+#define type2name(dma_type)                                                                   \
+    dma_type == DMA_DATA_TYPE_BYTE ? "8-bit" : dma_type == DMA_DATA_TYPE_HALF_WORD ? "16-bit" \
+                                           : dma_type == DMA_DATA_TYPE_WORD        ? "32-bit" \
+                                                                                   : "TYPE NOT VALID"
+
+dma_data_type_t C_type_2_dma_type(int C_type)
+{
+    switch (C_type)
+    {
+    case 1:
+        return DMA_DATA_TYPE_BYTE;
+    case 2:
+        return DMA_DATA_TYPE_HALF_WORD;
+    case 4:
+        return DMA_DATA_TYPE_WORD;
+    default:
+        return DMA_DATA_TYPE_WORD;
+    }
+}
+
+#define WAIT_DMA                              \
+    while (!dma_is_ready(0))                   \
+    {                                         \
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8); \
+        if (dma_is_ready(0) == 0)              \
+        {                                     \
+            wait_for_interrupt();             \
+        }                                     \
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);   \
+    }
+
+#define RUN_DMA                                                                               \
+    trans.flags = 0x0;                                                                        \
+    res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY); \
+    PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ? "Ok!" : "Error!");                \
+    res = dma_load_transaction(&trans);                                                       \
+    PRINTF("load: %u \t%s\n\r", res, res == DMA_CONFIG_OK ? "Ok!" : "Error!");                \
+    res = dma_launch(&trans);                                                                 \
+    PRINTF("laun: %u \t%s\n\r", res, res == DMA_CONFIG_OK ? "Ok!" : "Error!");
+
+// TEST MACROS
+
+#define PRINT_TEST(signed, data_size, dma_src_type, dma_dst_type) \
+    PRINTF("TEST:\n\r");                                          \
+    PRINTF("Data size: %d\n\r", data_size);                       \
+    PRINTF("Signed: %d\n\r", signed);                             \
+    PRINTF("Source type size: %s\n\r", type2name(dma_src_type));  \
+    PRINTF("Destination type size: %s\n\r", type2name(dma_dst_type));
+
+#define DEFINE_DATA(data_size, C_src_type, C_dst_type, signed) \
+    C_src_type src[data_size] __attribute__((aligned(4)));     \
+    C_dst_type dst[data_size] __attribute__((aligned(4)));     \
+    if (data_size <= TEST_DATA_SIZE)                           \
+        for (int i = 0; i < data_size; i++)                    \
+            if (signed && (i % 2) == 0)                        \
+                src[i] = (C_src_type)(-test_data_4B[i]);       \
+            else                                               \
+                src[i] = (C_src_type)test_data_4B[i];
+
+#define CHECK_RESULTS(data_size)                                                            \
+    for (int i = 0; i < data_size; i++)                                                     \
+    {                                                                                       \
+        if (src[i] != dst[i])                                                               \
+        {                                                                                   \
+            PRINTF("[%d] Expected: %x Got : %x\n\r", i, src[i], dst[i]);                      \
+            errors++;                                                                       \
+        }                                                                                   \
+    }                                                                                       \
+    if (errors != 0)                                                                        \
+    {                                                                                       \
+        PRINTF("DMA failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b); \
+        return EXIT_FAILURE;                                                                \
+    }
+
+#define INIT_TEST(signed, data_size, dma_src_type, dma_dst_type) \
+    tgt_src.ptr = (uint8_t *)src;                                \
+    tgt_src.inc_du = 1;                                          \
+    tgt_src.inc_d2_du = 0;                                       \
+    tgt_src.size_du = data_size;                                 \
+    tgt_src.trig = DMA_TRIG_MEMORY;                              \
+    tgt_src.type = dma_src_type;                                 \
+    tgt_src.env = NULL;                                          \
+    tgt_dst.ptr = (uint8_t *)dst;                                \
+    tgt_dst.inc_du = 1;                                          \
+    tgt_dst.inc_d2_du = 0;                                       \
+    tgt_dst.size_du = data_size;                                 \
+    tgt_dst.trig = DMA_TRIG_MEMORY;                              \
+    tgt_dst.type = dma_dst_type;                                 \
+    tgt_dst.env = NULL;                                          \
+    trans.src = &tgt_src;                                        \
+    trans.dst = &tgt_dst;                                        \
+    trans.src_addr = &tgt_addr;                                  \
+    trans.src_type = dma_src_type;                               \
+    trans.dst_type = dma_dst_type;                               \
+    trans.mode = DMA_TRANS_MODE_SINGLE;                          \
+    trans.win_du = 0;                                            \
+    trans.sign_ext = signed;                                     \
+    trans.end = DMA_TRANS_END_INTR;                              \
+    trans.dim = DMA_DIM_CONF_1D;                                 \
+
+#define TEST(C_src_type, C_dst_type, test_size, sign_extend)                                                         \
+    PRINT_TEST(sign_extend, test_size, C_type_2_dma_type(sizeof(C_src_type)), C_type_2_dma_type(sizeof(C_dst_type))) \
+    DEFINE_DATA(test_size, C_src_type, C_dst_type, sign_extend)                                                      \
+    INIT_TEST(sign_extend, test_size, C_type_2_dma_type(sizeof(C_src_type)), C_type_2_dma_type(sizeof(C_dst_type)))  \
+    RUN_DMA                                                                                                          \
+    WAIT_DMA                                                                                                         \
+    CHECK_RESULTS(test_size)                                                                                         \
+    PRINTF("\n\r")
+
+#define TEST_SINGLE                                  \
+    {                                                \
+        TEST(uint8_t, uint8_t, TEST_DATA_SIZE, 0);   \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(uint8_t, uint16_t, TEST_DATA_SIZE, 0);  \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(uint8_t, uint32_t, TEST_DATA_SIZE, 0);  \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(int8_t, int8_t, TEST_DATA_SIZE, 1);     \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(int8_t, int16_t, TEST_DATA_SIZE, 1);    \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(int8_t, int32_t, TEST_DATA_SIZE, 1);    \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(uint16_t, uint16_t, TEST_DATA_SIZE, 0); \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(uint16_t, uint32_t, TEST_DATA_SIZE, 0); \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(int16_t, int16_t, TEST_DATA_SIZE, 1);   \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(int16_t, int32_t, TEST_DATA_SIZE, 1);   \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(uint32_t, uint32_t, TEST_DATA_SIZE, 0); \
+        errors += errors;                            \
+    }                                                \
+    {                                                \
+        TEST(int32_t, int32_t, TEST_DATA_SIZE, 1);   \
+        errors += errors;                            \
+    }
+
+// GLOBAL VARIABLES
 
 int32_t errors = 0;
 int8_t cycles = 0;
 
-void dma_intr_handler_trans_done()
+// INTERRUPT HANDLERS
+void dma_intr_handler_trans_done(uint8_t channel)
 {
     cycles++;
 }
 
-
 #ifdef TEST_WINDOW
 
 int32_t window_intr_flag;
 
-void dma_intr_handler_window_done(void) {
+void dma_intr_handler_window_done(uint8_t channel) {
     window_intr_flag ++;
 }
 
@@ -66,94 +227,64 @@ uint8_t dma_window_ratio_warning_threshold()
 
 #endif // TEST_WINDOW
 
+dma_trans_t trans;
 
 int main(int argc, char *argv[])
 {
 
-    static uint32_t test_data_4B[TEST_DATA_SIZE] __attribute__ ((aligned (4))) = {
-      0x76543210, 0xfedcba98, 0x579a6f90, 0x657d5bee, 0x758ee41f, 0x01234567, 0xfedbca98, 0x89abcdef, 0x679852fe, 0xff8252bb, 0x763b4521, 0x6875adaa, 0x09ac65bb, 0x666ba334, 0x55446677, 0x65ffba98};
-    static uint32_t copied_data_4B[TEST_DATA_LARGE] __attribute__ ((aligned (4))) = { 0 };
-    static uint32_t test_data_large[TEST_DATA_LARGE] __attribute__ ((aligned (4))) = { 0 };
 
-     // this array will contain the even address of copied_data_4B
-    uint32_t* test_addr_4B_PTR = &test_data_large[0];
+    static uint32_t test_data_4B[TEST_DATA_SIZE] __attribute__((aligned(4))) = {
+        0x76543210, 0xfedcba98, 0x579a6f90, 0x657d5bee, 0x758ee41f, 0x01234567, 0xfedbca98, 0x89abcdef, 0x679852fe, 0xff8252bb, 0x763b4521, 0x6875adaa, 0x09ac65bb, 0x666ba334, 0x55446677, 0x65ffba98};
+    static uint32_t copied_data_4B[TEST_DATA_LARGE] __attribute__((aligned(4))) = {0};
+    static uint32_t test_data_large[TEST_DATA_LARGE] __attribute__((aligned(4))) = {0};
+
+    // this array will contain the even address of copied_data_4B
+    uint32_t *test_addr_4B_PTR = &test_data_large[0];
 
     // The DMA is initialized (i.e. Any current transaction is cleaned.)
     dma_init(NULL);
-
     dma_config_flags_t res;
-
-    dma_target_t tgt_src = {
-                                .ptr        = test_data_4B,
-                                .inc_du     = 1,
-                                .size_du    = TEST_DATA_SIZE,
-                                .trig       = DMA_TRIG_MEMORY,
-                                .type       = DMA_DATA_TYPE_WORD,
-                                };
-    dma_target_t tgt_dst = {
-                                .ptr        = copied_data_4B,
-                                .inc_du     = 1,
-                                .size_du    = TEST_DATA_SIZE,
-                                .trig       = DMA_TRIG_MEMORY,
-                                };
-
+    dma_target_t tgt_src;
+    dma_target_t tgt_dst;
     dma_target_t tgt_addr = {
-                                .ptr        = test_addr_4B_PTR,
-                                .inc_du     = 1,
-                                .size_du    = TEST_DATA_SIZE,
-                                .trig       = DMA_TRIG_MEMORY,
-                                };
-
-    dma_trans_t trans = {
-                                .src        = &tgt_src,
-                                .dst        = &tgt_dst,
-                                .src_addr   = &tgt_addr,
-                                .mode       = DMA_TRANS_MODE_SINGLE,
-                                .win_du     = 0,
-                                .end        = DMA_TRANS_END_INTR,
-                                };
-    // Create a target pointing at the buffer to be copied. Whole WORDs, no skippings, in memory, no environment.
-
-#ifdef TEST_SINGULAR_MODE
+        .ptr = (uint8_t *)test_addr_4B_PTR,
+        .inc_du = 1,
+        .size_du = TEST_DATA_SIZE,
+        .trig = DMA_TRIG_MEMORY,
+    };
+
+#ifdef TEST_SINGLE_MODE
 
     PRINTF("\n\n\r===================================\n\n\r");
     PRINTF("    TESTING SINGLE MODE   ");
     PRINTF("\n\n\r===================================\n\n\r");
 
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-    res = dma_load_transaction(&trans);
-    PRINTF("load: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-    res = dma_launch(&trans);
-    PRINTF("laun: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-
-    while( ! dma_is_ready()) {
-        // disable_interrupts
-        // this does not prevent waking up the core as this is controlled by the MIP register
-        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-        if ( dma_is_ready() == 0 ) {
-            wait_for_interrupt();
-            //from here we wake up even if we did not jump to the ISR
-        }
-        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    }
-    PRINTF(">> Finished transaction. \n\r");
+    TEST_SINGLE
 
-    for(uint32_t i = 0; i < trans.size_b; i++ ) {
-        if ( ((uint8_t*)copied_data_4B)[i] != ((uint8_t*)test_data_4B)[i] ) {
-            PRINTF("ERROR [%d]: %04x != %04x\n\r", i, ((uint8_t*)copied_data_4B)[i], ((uint8_t*)test_data_4B)[i]);
-            errors++;
-        }
-    }
+#endif // TEST_SINGLE_MODE
 
-    if (errors == 0) {
-        PRINTF("DMA single mode success.\n\r");
-    } else {
-        PRINTF("DMA single mode failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b );
-        return EXIT_FAILURE;
-    }
+    // Initialize the DMA for the next tests
+    tgt_src.ptr = (uint8_t *)test_data_4B;
+    tgt_src.inc_du = 1;
+    tgt_src.size_du = TEST_DATA_SIZE;
+    tgt_src.trig = DMA_TRIG_MEMORY;
+    tgt_src.type = DMA_DATA_TYPE_WORD;
 
-#endif // TEST_SINGULAR_MODE
+    tgt_dst.ptr = (uint8_t *)copied_data_4B;
+    tgt_dst.inc_du = 1;
+    tgt_dst.size_du = TEST_DATA_LARGE;
+    tgt_dst.trig = DMA_TRIG_MEMORY;
+    tgt_dst.type = DMA_DATA_TYPE_WORD;
+
+    trans.src = &tgt_src;
+    trans.dst = &tgt_dst;
+    trans.src_addr = &tgt_addr;
+    trans.src_type = DMA_DATA_TYPE_WORD;
+    trans.dst_type = DMA_DATA_TYPE_WORD;
+    trans.mode = DMA_TRANS_MODE_SINGLE;
+    trans.win_du = 0;
+    trans.sign_ext = 0;
+    trans.end = DMA_TRANS_END_INTR;
 
 #ifdef TEST_ADDRESS_MODE
 
@@ -162,66 +293,55 @@ int main(int argc, char *argv[])
     PRINTF("\n\n\r===================================\n\n\r");
 
     // Prepare the data
-    for (int i = 0; i < TEST_DATA_SIZE; i++) {
-        test_addr_4B_PTR[i] = &copied_data_4B[i*2];
+    for (int i = 0; i < TEST_DATA_SIZE; i++)
+    {
+        test_addr_4B_PTR[i] = (uint32_t)&copied_data_4B[i * 2];
     }
 
     trans.mode = DMA_TRANS_MODE_ADDRESS;
 
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-    res = dma_load_transaction(&trans);
-    PRINTF("load: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-    res = dma_launch(&trans);
-    PRINTF("laun: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-
-    while( ! dma_is_ready()) {
-        // disable_interrupts
-        // this does not prevent waking up the core as this is controlled by the MIP register
-        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-        if ( dma_is_ready() == 0 ) {
-            wait_for_interrupt();
-            //from here we wake up even if we did not jump to the ISR
-        }
-        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    }
+    RUN_DMA
 
+    WAIT_DMA
 
     PRINTF(">> Finished transaction. \n\r");
 
-    for(uint32_t i = 0; i < trans.size_b >> 2; i++ ) {
-        if ( copied_data_4B[i*2] != test_data_4B[i] ) {
-            PRINTF("ERROR [%d]: %04x != %04x\n\r", i, copied_data_4B[i*2], test_data_4B[i]);
+    for (uint32_t i = 0; i < trans.size_b >> 2; i++)
+    {
+        if (copied_data_4B[i * 2] != test_data_4B[i])
+        {
+            PRINTF("ERROR [%d]: %04x != %04x\n\r", i, copied_data_4B[i * 2], test_data_4B[i]);
             errors++;
         }
     }
 
-    if (errors == 0) {
+    if (errors == 0)
+    {
         PRINTF("DMA address mode success.\n\r");
-    } else {
-        PRINTF("DMA address mode failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b );
+    }
+    else
+    {
+        PRINTF("DMA address mode failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b);
         return EXIT_FAILURE;
     }
 
     trans.mode = DMA_TRANS_MODE_SINGLE;
 
-
 #endif // TEST_ADDRESS_MODE
 
 #if defined(TARGET_SIM) || defined(TARGET_SYSTEMC)
 
 #ifdef TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
-#pragma message ( "this application should not be ran in a system integrating x-heep as in the external \
-    slave can be plugged something else than a slow memory as in our testbench" )
-
-    uint32_t* ext_test_addr_4B_PTR = EXT_SLAVE_START_ADDRESS;
-    uint32_t* ext_copied_data_4B;
+#pragma message("this application should not be ran in a system integrating x-heep as in the external \
+    slave can be plugged something else than a slow memory as in our testbench")
 
-    ext_copied_data_4B = &ext_test_addr_4B_PTR[TEST_DATA_SIZE+1];
+    uint32_t *ext_test_addr_4B_PTR = (uint32_t *)EXT_SLAVE_START_ADDRESS;
+    uint32_t *ext_copied_data_4B;
 
+    ext_copied_data_4B = &ext_test_addr_4B_PTR[TEST_DATA_SIZE + 1];
 
-    tgt_addr.ptr = ext_test_addr_4B_PTR;
+    tgt_addr.ptr = (uint8_t *) ext_test_addr_4B_PTR;
     trans.src_addr = &tgt_addr;
 
     PRINTF("\n\n\r=====================================\n\n\r");
@@ -229,53 +349,44 @@ int main(int argc, char *argv[])
     PRINTF("\n\n\r=====================================\n\n\r");
 
     // Prepare the data
-    for (int i = 0; i < TEST_DATA_SIZE; i++) {
-        ext_test_addr_4B_PTR[i] = &ext_copied_data_4B[i*2];
+    for (int i = 0; i < TEST_DATA_SIZE; i++)
+    {
+        ext_test_addr_4B_PTR[i] = (uint32_t) &ext_copied_data_4B[i * 2];
     }
 
     trans.mode = DMA_TRANS_MODE_ADDRESS;
 
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-    res = dma_load_transaction(&trans);
-    PRINTF("load: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-    res = dma_launch(&trans);
-    PRINTF("laun: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-
-    while( ! dma_is_ready()) {
-        // disable_interrupts
-        // this does not prevent waking up the core as this is controlled by the MIP register
-        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-        if ( dma_is_ready() == 0 ) {
-            wait_for_interrupt();
-            //from here we wake up even if we did not jump to the ISR
-        }
-        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    }
+    RUN_DMA
 
+    WAIT_DMA
 
     PRINTF(">> Finished transaction. \n\r");
 
-    for(uint32_t i = 0; i < trans.size_b >> 2; i++ ) {
-        if ( ext_copied_data_4B[i*2] != test_data_4B[i] ) {
+    for (uint32_t i = 0; i < trans.size_b >> 2; i++)
+    {
+        if (ext_copied_data_4B[i * 2] != test_data_4B[i])
+        {
             PRINTF("ERROR [%d]: %04x != %04x\n\r", i, ext_copied_data_4B[i], test_data_4B[i]);
             errors++;
         }
     }
 
-    if (errors == 0) {
+    if (errors == 0)
+    {
         PRINTF("DMA address mode in external memory success.\n\r");
-    } else {
-        PRINTF("DMA address mode in external memory failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b );
+    }
+    else
+    {
+        PRINTF("DMA address mode in external memory failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b);
         return EXIT_FAILURE;
     }
 
     trans.mode = DMA_TRANS_MODE_SINGLE;
 
-#endif //TEST_ADDRESS_MODE_EXTERNAL_DEVICE
+#endif // TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
 #else
-    #pragma message( "TEST_ADDRESS_MODE_EXTERNAL_DEVICE is not executed on target different than TARGET_SIM" )
+#pragma message("TEST_ADDRESS_MODE_EXTERNAL_DEVICE is not executed on target different than TARGET_SIM")
 #endif
 
 #ifdef TEST_PENDING_TRANSACTION
@@ -283,61 +394,70 @@ int main(int argc, char *argv[])
     PRINTF("    TESTING MULTIPLE TRANSACTIONS   ");
     PRINTF("\n\n\r===================================\n\n\r");
 
-    for (uint32_t i = 0; i < TEST_DATA_LARGE; i++) {
+    for (uint32_t i = 0; i < TEST_DATA_LARGE; i++)
+    {
         test_data_large[i] = i;
     }
 
-
-    tgt_src.ptr     = test_data_large;
+    tgt_src.ptr = (uint8_t *)test_data_large;
     tgt_src.size_du = TEST_DATA_LARGE;
+    tgt_dst.size_du = TEST_DATA_LARGE;
 
     // trans.end = DMA_TRANS_END_INTR_WAIT; // This option makes no sense, because the launch is blocking the program until the trans finishes.
     trans.end = DMA_TRANS_END_INTR;
     // trans.end = DMA_TRANS_END_POLLING;
 
-
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ? "Ok!" : "Error!");
     cycles = 0;
     uint8_t consecutive_trans = 0;
 
-    for(  uint8_t i = 0; i < TRANSACTIONS_N; i++ ){
-        res =  dma_load_transaction(&trans);
+    for (uint8_t i = 0; i < TRANSACTIONS_N; i++)
+    {
+        res = dma_load_transaction(&trans);
         res |= dma_launch(&trans);
-        if( res == DMA_CONFIG_OK ) consecutive_trans++;
+        if (res == DMA_CONFIG_OK)
+            consecutive_trans++;
     }
 
-    if( trans.end == DMA_TRANS_END_POLLING ){
-        while( cycles < consecutive_trans ){
-            while( ! dma_is_ready() );
+    if (trans.end == DMA_TRANS_END_POLLING)
+    {
+        while (cycles < consecutive_trans)
+        {
+            while (!dma_is_ready(0));
             cycles++;
         }
-    } else {
-        while( cycles < consecutive_trans ){
+    }
+    else
+    {
+        while (cycles < consecutive_trans)
+        {
             wait_for_interrupt();
         }
     }
     PRINTF(">> Finished %d transactions. That is %s.\n\r", consecutive_trans, consecutive_trans > 1 ? "bad" : "good");
 
-
-
-    for(int i=0; i<TEST_DATA_LARGE; i++) {
-        if (tgt_src.ptr[i] != tgt_dst.ptr[i]) {
+    for (int i = 0; i < TEST_DATA_LARGE; i++)
+    {
+        if (tgt_src.ptr[i] != tgt_dst.ptr[i])
+        {
             PRINTF("ERROR COPY [%d]: %08x != %08x : %04x != %04x\n\r", i, &tgt_src.ptr[i], &tgt_dst.ptr[i], tgt_src.ptr[i], tgt_dst.ptr[i]);
             errors++;
         }
     }
 
-    if (errors == 0) {
+    if (errors == 0)
+    {
         PRINTF("DMA multiple transactions success.\n\r");
-    } else {
+    }
+    else
+    {
         PRINTF("DMA multiple transactions failure: %d errors out of %d words checked\n\r", errors, TEST_DATA_SIZE);
         return EXIT_FAILURE;
     }
 
 #endif // TEST_PENDING_TRANSACTION
 
-
 #ifdef TEST_WINDOW
 
     PRINTF("\n\n\r===================================\n\n\r");
@@ -345,60 +465,63 @@ int main(int argc, char *argv[])
     PRINTF("\n\n\r===================================\n\n\r");
 
     plic_Init();
-    plic_irq_set_priority( DMA_WINDOW_INTR, 1);
-    plic_irq_set_enabled(  DMA_WINDOW_INTR, kPlicToggleEnabled);
+    plic_irq_set_priority(DMA_WINDOW_INTR, 1);
+    plic_irq_set_enabled(DMA_WINDOW_INTR, kPlicToggleEnabled);
 
     window_intr_flag = 0;
 
-    for (uint32_t i = 0; i < TEST_DATA_LARGE; i++) {
-        test_data_large [i] = i;
-        copied_data_4B  [i] = 0;
+    for (uint32_t i = 0; i < TEST_DATA_LARGE; i++)
+    {
+        test_data_large[i] = i;
+        copied_data_4B[i] = 0;
     }
 
-    tgt_src.ptr     = test_data_large;
+    tgt_src.ptr = (uint8_t *)test_data_large;
     tgt_src.size_du = TEST_DATA_LARGE;
 
-    tgt_src.type    = DMA_DATA_TYPE_WORD;
-    tgt_dst.type    = DMA_DATA_TYPE_WORD;
+    tgt_src.type = DMA_DATA_TYPE_WORD;
+    tgt_dst.type = DMA_DATA_TYPE_WORD;
 
-    trans.win_du     = TEST_WINDOW_SIZE_DU;
-    trans.end       = DMA_TRANS_END_INTR;
-
-    res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-    PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
-    res = dma_load_transaction(&trans);
-    PRINTF("load: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    trans.win_du = TEST_WINDOW_SIZE_DU;
+    trans.end = DMA_TRANS_END_INTR;
 
-    dma_launch(&trans);
+    RUN_DMA
 
-    if( trans.end == DMA_TRANS_END_POLLING ){ //There will be no interrupts whatsoever!
-        while( ! dma_is_ready() );
+    if (trans.end == DMA_TRANS_END_POLLING)
+    { // There will be no interrupts whatsoever!
+        while (!dma_is_ready(0));
         PRINTF("?\n\r");
-    } else {
-        while( !dma_is_ready() ){
+    }
+    else
+    {
+        while (!dma_is_ready(0))
+        {
             wait_for_interrupt();
-            PRINTF("i\n\r");
+            PRINTF("i\n\r");//@ToDo: is this a debugging?
         }
     }
 
     PRINTF("\nWe had %d window interrupts.\n\r", window_intr_flag);
 
-    for(uint32_t i = 0; i < TEST_DATA_LARGE; i++ ) {
-        if (copied_data_4B[i] != test_data_large[i]) {
+    for (uint32_t i = 0; i < TEST_DATA_LARGE; i++)
+    {
+        if (copied_data_4B[i] != test_data_large[i])
+        {
             PRINTF("[%d] %04x\tvs.\t%04x\n\r", i, copied_data_4B[i], test_data_large[i]);
             errors++;
         }
     }
 
-    if (errors == 0) {
+    if (errors == 0)
+    {
         PRINTF("DMA window success\n\r");
-    } else {
+    }
+    else
+    {
         PRINTF("DMA window failure: %d errors out of %d words checked\n\r", errors, TEST_DATA_SIZE);
         return EXIT_FAILURE;
     }
-
 #endif // TEST_WINDOW
 
-
     return EXIT_SUCCESS;
-}
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c
new file mode 100644
index 00000000..0a5651c1
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c
@@ -0,0 +1,890 @@
+/*
+ *  Copyright EPFL contributors.
+ *  Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *  
+ *  Info: Example application of matrix manipulation by exploiting the 2D DMA.
+ *        In this code, there are some optional features:
+ *        - Verification of several matrix operations carried out by the 2D DMA
+ *        - Performance comparison between the DMA and the CPU, obtained by performing similar matrix operations
+ *          and monitoring the performance counter.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "dma.h"
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+#include "csr.h"
+#include "rv_plic.h"
+#include "test_data.h"
+
+/*  
+ *  This code contains four different tests that can be run by defining the corresponding TEST_ID_* macro.
+ *  - Extract a NxM matrix, perform optional padding and copy it to a AxB matrix, using HALs
+ *  - Extract a NxM matrix and copy its transposed version to AxB matrix, using HALs
+ *  - Extract a 1xN matrix (array), perform optional padding and copy it to an array, using HALs
+ *  - Extract a NxM matrix, perform optional padding and copy it to a AxB matrix, using direct register operations
+ */
+
+#define TEST_ID_0
+#define TEST_ID_1
+#define TEST_ID_2
+#define TEST_ID_3
+
+/* Enable performance analysis */
+#define EN_PERF 1
+
+/* Enable verification */
+#define EN_VERIF 1
+
+/* Parameters */
+
+/* Size of the extracted matrix (including strides on the input, excluding strides on the outputs) */
+#define SIZE_EXTR_D1 10
+#define SIZE_EXTR_D2 10
+
+/* Set strides of the input ad output matrix */
+#define STRIDE_IN_D1 1
+#define STRIDE_IN_D2 1
+#define STRIDE_OUT_D1 1
+#define STRIDE_OUT_D2 1
+
+/* Set the padding parameters */
+#define TOP_PAD 1
+#define BOTTOM_PAD 1
+#define LEFT_PAD 1
+#define RIGHT_PAD 1
+
+/* Macros for dimensions computation */
+#define OUT_D1_PAD ( SIZE_EXTR_D1 + LEFT_PAD + RIGHT_PAD )
+#define OUT_D2_PAD ( SIZE_EXTR_D2  + TOP_PAD + BOTTOM_PAD )
+#define OUT_D1_PAD_STRIDE ( (OUT_D1_PAD * STRIDE_OUT_D1) - (STRIDE_OUT_D1 - 1)  )
+#define OUT_D2_PAD_STRIDE ( (OUT_D2_PAD * STRIDE_OUT_D2) - (STRIDE_OUT_D2 - 1)  )
+#define OUT_DIM_1D ( OUT_D1_PAD_STRIDE  )
+#define OUT_DIM_2D ( OUT_D1_PAD_STRIDE * OUT_D2_PAD_STRIDE )
+
+/* Mask for the direct register operations example */
+#define DMA_CSR_REG_MIE_MASK (( 1 << 19 ) | (1 << 11 ))
+
+/* Transposition example def */
+#define TRANSPOSITION_EN 1
+
+/* Pointer increments computation */
+#define SRC_INC_D1 STRIDE_IN_D1
+#define DST_INC_D1 STRIDE_OUT_D1
+#define SRC_INC_D2 (STRIDE_IN_D2 * SIZE_IN_D1 - (SIZE_EXTR_D1 - 1 + (STRIDE_IN_D1 - 1) * (SIZE_EXTR_D1 - 1)))
+#define DST_INC_D2 ((STRIDE_OUT_D2 - 1) * OUT_DIM_1D + 1)
+#define SRC_INC_TRSP_D1 SRC_INC_D1
+#define SRC_INC_TRSP_D2 (STRIDE_IN_D2 * SIZE_IN_D1)
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+dma_input_data_type copied_data_2D_DMA[OUT_DIM_2D];
+dma_input_data_type copied_data_1D_DMA[OUT_DIM_1D];
+dma_input_data_type copied_data_2D_CPU[OUT_DIM_2D];
+dma_input_data_type copied_data_1D_CPU[OUT_DIM_2D];
+
+dma_config_flags_t res_valid, res_load, res_launch;
+
+dma *peri = dma_peri(0);
+
+dma_target_t tgt_src;
+dma_target_t tgt_dst;
+dma_trans_t trans;
+
+uint32_t dst_ptr = 0, src_ptr = 0;
+uint32_t cycles_dma, cycles_cpu;
+uint32_t size_dst_trans_d1;
+uint32_t dst_stride_d1;
+uint32_t dst_stride_d2;
+uint32_t size_src_trans_d1;
+uint32_t src_stride_d1;
+uint32_t src_stride_d2;
+uint32_t i_in;
+uint32_t j_in;
+uint32_t i_in_last;
+uint16_t left_pad_cnt = 0;
+uint16_t top_pad_cnt = 0;
+uint8_t stride_1d_cnt = 0;
+uint8_t stride_2d_cnt = 0;
+char passed = 1;
+
+int main()
+{    
+    #ifdef TEST_ID_0
+
+    /* Testing copy and padding of a NxM matrix using HALs */
+    
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    tgt_src.ptr = (uint8_t *) test_data;
+    tgt_src.inc_du = SRC_INC_D1;
+    tgt_src.inc_d2_du = SRC_INC_D2;
+    tgt_src.size_du = SIZE_EXTR_D1;
+    tgt_src.size_d2_du = SIZE_EXTR_D2;
+    tgt_src.trig = DMA_TRIG_MEMORY;
+    tgt_src.type = DMA_DATA_TYPE;
+    
+    tgt_dst.ptr = (uint8_t *)  copied_data_2D_DMA;
+    tgt_dst.inc_du = DST_INC_D1;
+    tgt_dst.inc_d2_du = DST_INC_D2;
+    tgt_dst.size_du = OUT_D1_PAD_STRIDE;
+    tgt_dst.size_d2_du = OUT_D2_PAD_STRIDE;
+    tgt_dst.trig = DMA_TRIG_MEMORY;
+    tgt_dst.type = DMA_DATA_TYPE;
+
+    trans.src = &tgt_src;
+    trans.dst = &tgt_dst;
+    trans.mode = DMA_TRANS_MODE_SINGLE;
+    trans.dim = DMA_DIM_CONF_2D;
+    trans.pad_top_du     = TOP_PAD,
+    trans.pad_bottom_du  = BOTTOM_PAD,
+    trans.pad_left_du    = LEFT_PAD,
+    trans.pad_right_du   = RIGHT_PAD,
+    trans.win_du         = 0,
+    trans.end            = DMA_TRANS_END_INTR;
+    
+    dma_init(NULL);
+    
+    #if EN_PERF
+
+    res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    res_load = dma_load_transaction(&trans);
+    res_launch = dma_launch(&trans);
+    
+    #else
+
+    res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    PRINTF("tran: %u \t%s\n\r", res_valid, res_valid == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_load = dma_load_transaction(&trans);
+    PRINTF("load: %u \t%s\n\r", res_load, res_load == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_launch = dma_launch(&trans);
+    PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    #endif
+
+    while( ! dma_is_ready(0)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+            /* From here the core wakes up even if we did not jump to the ISR */
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+
+    #if EN_PERF    
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+    {
+        stride_1d_cnt = 0;
+        j_in = 0;
+
+        for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+        {
+            dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+            src_ptr = (i_in - top_pad_cnt ) * STRIDE_IN_D2 * SIZE_IN_D1 + (j_in - left_pad_cnt) * STRIDE_IN_D1;
+            if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                stride_1d_cnt != 0 || stride_2d_cnt != 0)
+            {
+                copied_data_2D_CPU[dst_ptr] = 0;
+            }
+            else
+            {
+                copied_data_2D_CPU[dst_ptr] = test_data[src_ptr];
+            }
+
+            if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+            {
+                left_pad_cnt++;
+            }
+
+            if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+            {
+                stride_1d_cnt = 0;
+                j_in++;
+            }
+            else
+            {
+                stride_1d_cnt++;
+            }
+
+        }
+
+        if (i_in < TOP_PAD && stride_2d_cnt == 0)
+        {
+            top_pad_cnt++;
+        }
+        
+        if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+        {
+            stride_2d_cnt = 0;
+            i_in++;
+        }
+        else
+        {
+            stride_2d_cnt++;
+        }
+
+        left_pad_cnt = 0;
+    }
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+    PRINTF("\n\r");
+
+    #endif
+
+    #if EN_VERIF
+    
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
+        for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
+            if (copied_data_2D_DMA[i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_CPU[i * OUT_D1_PAD_STRIDE + j]) {
+                passed = 0;
+            }
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 0\n\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 0\n\r");
+        return EXIT_FAILURE;
+    }
+    #endif
+
+    #endif
+    
+    /* Reset for second test */
+    passed = 1;
+    i_in = 0;
+    j_in = 0;
+    left_pad_cnt = 0;
+    top_pad_cnt = 0;
+    stride_1d_cnt = 0;
+    stride_2d_cnt = 0;
+
+    for (int i = 0; i < OUT_DIM_2D; i++) {
+        copied_data_2D_DMA[i] = 0;
+        copied_data_2D_CPU[i] = 0;
+    }
+
+    #ifdef TEST_ID_1
+
+    /* Testing transposition and copy of a NxM matrix using HALs */
+ 
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    tgt_src.ptr            = (uint8_t *) test_data;
+    tgt_src.inc_du         = SRC_INC_TRSP_D1;
+    tgt_src.inc_d2_du      = SRC_INC_TRSP_D2;
+    tgt_src.size_du        = SIZE_EXTR_D1;
+    tgt_src.size_d2_du     = SIZE_EXTR_D2;
+    tgt_src.trig           = DMA_TRIG_MEMORY;
+    tgt_src.type           = DMA_DATA_TYPE;
+
+    tgt_dst.ptr            = (uint8_t *) copied_data_2D_DMA;
+    tgt_dst.inc_du         = DST_INC_D1;
+    tgt_dst.inc_d2_du      = DST_INC_D2;
+    tgt_dst.trig           = DMA_TRIG_MEMORY;
+
+    trans.src            = &tgt_src;
+    trans.dst            = &tgt_dst;
+    trans.mode           = DMA_TRANS_MODE_SINGLE;
+    trans.dim            = DMA_DIM_CONF_2D;
+    trans.pad_top_du     = TOP_PAD;
+    trans.pad_bottom_du  = BOTTOM_PAD;
+    trans.pad_left_du    = LEFT_PAD;
+    trans.pad_right_du   = RIGHT_PAD;
+    trans.dim_inv        = TRANSPOSITION_EN;
+    trans.win_du         = 0,
+    trans.end            = DMA_TRANS_END_INTR;
+    
+    dma_init(NULL);
+    
+    #if EN_PERF
+
+    res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    res_load = dma_load_transaction(&trans);
+    res_launch = dma_launch(&trans);
+    
+    #else
+
+    res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    PRINTF("tran: %u \t%s\n\r", res_valid, res_valid == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_load = dma_load_transaction(&trans);
+    PRINTF("load: %u \t%s\n\r", res_load, res_load == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_launch = dma_launch(&trans);
+    PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    #endif
+
+    while( ! dma_is_ready(0)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+            /* From here the core wakes up even if we did not jump to the ISR */
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+
+    #if EN_PERF    
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+    {
+        stride_1d_cnt = 0;
+        j_in = 0;
+
+        for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+        {
+            dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+            src_ptr = (j_in - left_pad_cnt) * STRIDE_IN_D2 * SIZE_IN_D1 + (i_in - top_pad_cnt ) * STRIDE_IN_D1;
+            if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                stride_1d_cnt != 0 || stride_2d_cnt != 0)
+            {
+                copied_data_2D_CPU[dst_ptr] = 0;
+            }
+            else
+            {
+                copied_data_2D_CPU[dst_ptr] = test_data[src_ptr];
+            }
+
+            if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+            {
+                left_pad_cnt++;
+            }
+
+            if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+            {
+                stride_1d_cnt = 0;
+                j_in++;
+            }
+            else
+            {
+                stride_1d_cnt++;
+            }
+
+        }
+
+        if (i_in < TOP_PAD && stride_2d_cnt == 0)
+        {
+            top_pad_cnt++;
+        }
+        
+        if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+        {
+            stride_2d_cnt = 0;
+            i_in++;
+        }
+        else
+        {
+            stride_2d_cnt++;
+        }
+
+        left_pad_cnt = 0;
+    }
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+    PRINTF("\n\r");
+
+    #endif
+
+    #if EN_VERIF
+    
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
+        for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
+            if (copied_data_2D_DMA[i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_CPU[i * OUT_D1_PAD_STRIDE + j]) {
+                passed = 0;
+            }
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 1\n\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 1\n\r");
+        return EXIT_FAILURE;
+    }
+    #endif
+
+    #endif
+    
+    /* Reset for third test */
+    passed = 1;
+    i_in = 0;
+    j_in = 0;
+    left_pad_cnt = 0;
+    top_pad_cnt = 0;
+    stride_1d_cnt = 0;
+    stride_2d_cnt = 0;
+
+    #ifdef TEST_ID_2
+
+    /* Testing copy and padding of a 1xN matrix (an array) */
+
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    tgt_src.ptr            = (uint8_t *) test_data;
+    tgt_src.inc_du         = SRC_INC_D1;
+    tgt_src.size_du        = SIZE_EXTR_D1;
+    tgt_src.inc_d2_du      = 0;
+    tgt_src.size_d2_du     = 0;
+    tgt_src.trig           = DMA_TRIG_MEMORY;
+    tgt_src.type           = DMA_DATA_TYPE;
+
+    tgt_dst.ptr            = (uint8_t *) copied_data_1D_DMA;
+    tgt_dst.inc_du         = DST_INC_D1;
+    tgt_dst.inc_d2_du      = 0;
+    tgt_dst.trig           = DMA_TRIG_MEMORY;
+
+    trans.src            = &tgt_src;
+    trans.dst            = &tgt_dst;
+    trans.mode           = DMA_TRANS_MODE_SINGLE;
+    trans.dim            = DMA_DIM_CONF_1D;
+    trans.pad_top_du     = 0;
+    trans.pad_bottom_du  = 0;
+    trans.pad_left_du    = LEFT_PAD;
+    trans.pad_right_du   = RIGHT_PAD;
+    trans.dim_inv        = 0;
+    trans.win_du         = 0;
+    trans.end            = DMA_TRANS_END_INTR;
+
+    dma_init(NULL);
+    
+    #if EN_PERF
+
+    res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    res_load = dma_load_transaction(&trans);
+    res_launch = dma_launch(&trans);
+    
+    #else
+
+    res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    PRINTF("tran: %u \t%s\n\r", res_valid, res_valid == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_load = dma_load_transaction(&trans);
+    PRINTF("load: %u \t%s\n\r", res_load, res_load == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_launch = dma_launch(&trans);
+    PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    #endif
+
+    while( ! dma_is_ready(0)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+
+    #if EN_PERF
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+    {
+        dst_ptr = j;
+        src_ptr = (j_in - left_pad_cnt) * STRIDE_IN_D1;
+
+        if (j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+            stride_1d_cnt != 0)
+        {
+            copied_data_1D_CPU[dst_ptr] = 0;
+        }
+        else
+        {
+            copied_data_1D_CPU[dst_ptr] = test_data[src_ptr];
+        }
+
+        if (j_in < LEFT_PAD && stride_1d_cnt == 0)
+        {
+            left_pad_cnt++;
+        }
+
+        if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+        {
+            stride_1d_cnt = 0;
+            j_in++;
+        }
+        else
+        {
+            stride_1d_cnt++;
+        }
+    }
+    
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+    PRINTF("\n\r");
+    #endif
+
+    #if EN_VERIF
+    
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int i = 0; i < OUT_D1_PAD_STRIDE; i++) {
+        if (copied_data_1D_DMA[i] != copied_data_1D_CPU[i]) {
+            passed = 0;
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 2\n\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 2\n\r");
+        return EXIT_FAILURE;
+    }
+    #endif
+
+    #endif
+    
+    /* Reset for fourth test */
+    passed = 1;
+    i_in = 0;
+    j_in = 0;
+    left_pad_cnt = 0;
+    top_pad_cnt = 0;
+    stride_1d_cnt = 0;
+    stride_2d_cnt = 0;
+    for (int i = 0; i < OUT_DIM_2D; i++) {
+        copied_data_2D_DMA[i] = 0;
+        copied_data_2D_CPU[i] = 0;
+    }
+
+    #ifdef TEST_ID_3
+
+    /* Testing copy and padding of a NxM matrix using direct register operations.
+     * This strategy allows for maximum performance but doesn't perform any checks on the data integrity.
+     */
+    
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    /* The DMA is initialized (i.e. Any current transaction is cleaned.) */
+    dma_init(NULL);
+
+    /* Enable the DMA interrupt logic */
+    write_register( 0x1,
+                    DMA_INTERRUPT_EN_REG_OFFSET,
+                    0xffff,
+                    DMA_INTERRUPT_EN_TRANSACTION_DONE_BIT,
+                    peri );
+
+    /* Enable global interrupts */
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+    /* Enable fast interrupts */
+    CSR_SET_BITS(CSR_REG_MIE, DMA_CSR_REG_MIE_MASK);
+
+    /* Pointer set up */
+    peri->SRC_PTR = (uint32_t) (test_data);
+    peri->DST_PTR = (uint32_t) (copied_data_2D_DMA);
+
+    /* Dimensionality configuration */
+    write_register( 0x1,
+                    DMA_DIM_CONFIG_REG_OFFSET,
+                    0xffff,
+                    DMA_DIM_CONFIG_DMA_DIM_BIT,
+                    peri );
+
+    /* Operation mode configuration */
+    write_register( DMA_TRANS_MODE_SINGLE,
+                    DMA_MODE_REG_OFFSET,
+                    DMA_MODE_MODE_MASK,
+                    DMA_MODE_MODE_OFFSET,
+                    peri );
+    
+    /* Data type configuration */
+    write_register( DMA_DATA_TYPE,
+                    DMA_DST_DATA_TYPE_REG_OFFSET,
+                    DMA_DST_DATA_TYPE_DATA_TYPE_MASK,
+                    DMA_DST_DATA_TYPE_DATA_TYPE_OFFSET,
+                    peri );
+    write_register( DMA_DATA_TYPE,
+                    DMA_SRC_DATA_TYPE_REG_OFFSET,
+                    DMA_SRC_DATA_TYPE_DATA_TYPE_MASK,
+                    DMA_SRC_DATA_TYPE_DATA_TYPE_OFFSET,
+                    peri );
+
+    /* Set the source strides */
+    write_register( SRC_INC_D1 * DMA_DATA_TYPE_2_SIZE(DMA_DATA_TYPE),
+                    DMA_SRC_PTR_INC_D1_REG_OFFSET,
+                    DMA_SRC_PTR_INC_D1_INC_MASK,
+                    DMA_SRC_PTR_INC_D1_INC_OFFSET,
+                    peri );
+    
+    write_register( SRC_INC_D2 * DMA_DATA_TYPE_2_SIZE(DMA_DATA_TYPE),
+                    DMA_SRC_PTR_INC_D2_REG_OFFSET,
+                    DMA_SRC_PTR_INC_D2_INC_MASK,
+                    DMA_SRC_PTR_INC_D2_INC_OFFSET,
+                    peri );
+    
+    write_register( DST_INC_D1 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_DST_PTR_INC_D1_REG_OFFSET,
+                    DMA_DST_PTR_INC_D1_INC_MASK,
+                    DMA_DST_PTR_INC_D1_INC_OFFSET,
+                    peri );
+    
+    write_register( DST_INC_D2 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_DST_PTR_INC_D2_REG_OFFSET,
+                    DMA_DST_PTR_INC_D2_INC_MASK,
+                    DMA_DST_PTR_INC_D2_INC_OFFSET,
+                    peri );
+
+    /* Padding configuration */
+    write_register( TOP_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_PAD_TOP_REG_OFFSET,
+                    DMA_PAD_TOP_PAD_MASK,
+                    DMA_PAD_TOP_PAD_OFFSET,
+                    peri );
+
+    write_register( RIGHT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_PAD_RIGHT_REG_OFFSET,
+                    DMA_PAD_RIGHT_PAD_MASK,
+                    DMA_PAD_RIGHT_PAD_OFFSET,
+                    peri );
+
+    write_register( LEFT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_PAD_LEFT_REG_OFFSET,
+                    DMA_PAD_LEFT_PAD_MASK,
+                    DMA_PAD_LEFT_PAD_OFFSET,
+                    peri );
+
+    write_register( BOTTOM_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_PAD_BOTTOM_REG_OFFSET,
+                    DMA_PAD_BOTTOM_PAD_MASK,
+                    DMA_PAD_BOTTOM_PAD_OFFSET,
+                    peri );
+
+    /* Set the sizes */
+
+    write_register( SIZE_EXTR_D2 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_SIZE_D2_REG_OFFSET,
+                    DMA_SIZE_D2_SIZE_MASK,
+                    DMA_SIZE_D2_SIZE_OFFSET,
+                    peri );
+
+    write_register( SIZE_EXTR_D1 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                    DMA_SIZE_D1_REG_OFFSET,
+                    DMA_SIZE_D1_SIZE_MASK,
+                    DMA_SIZE_D1_SIZE_OFFSET,
+                    peri );
+
+    while( ! dma_is_ready(0)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+            /* From here the core wakes up even if we did not jump to the ISR */
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+
+    #if EN_PERF
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+    {
+        stride_1d_cnt = 0;
+        j_in = 0;
+
+        for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+        {
+            dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+            src_ptr = (i_in - top_pad_cnt ) * STRIDE_IN_D2 * SIZE_IN_D1 + (j_in - left_pad_cnt) * STRIDE_IN_D1;
+            if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                stride_1d_cnt != 0 || stride_2d_cnt != 0)
+            {
+                copied_data_2D_CPU[dst_ptr] = 0;
+            }
+            else
+            {
+                copied_data_2D_CPU[dst_ptr] = test_data[src_ptr];
+            }
+
+            if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+            {
+                left_pad_cnt++;
+            }
+
+            if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+            {
+                stride_1d_cnt = 0;
+                j_in++;
+            }
+            else
+            {
+                stride_1d_cnt++;
+            }
+
+        }
+
+        if (i_in < TOP_PAD && stride_2d_cnt == 0)
+        {
+            top_pad_cnt++;
+        }
+        
+        if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+        {
+            stride_2d_cnt = 0;
+            i_in++;
+        }
+        else
+        {
+            stride_2d_cnt++;
+        }
+
+        left_pad_cnt = 0;
+    }
+    
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+    PRINTF("\n\r");
+    #endif
+
+    #if EN_VERIF
+    
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
+        for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
+            if (copied_data_2D_DMA[i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_CPU[i * OUT_D1_PAD_STRIDE + j]) {
+                passed = 0;
+            }
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 3\n\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 3\n\r");
+        return EXIT_FAILURE;
+    }
+    #endif
+
+    #endif
+
+    return EXIT_SUCCESS;
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h
new file mode 100644
index 00000000..d1232223
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h
@@ -0,0 +1,40 @@
+#ifndef __TEST_DATA_H__
+#define __TEST_DATA_H__
+
+#define SIZE_IN_D1 25
+#define SIZE_IN_D2 25
+#define DMA_DATA_TYPE DMA_DATA_TYPE_WORD
+
+/* Change the input datatype depending on the DMA_DATA_TYPE
+ * The test data has been generated using byte as datatype, so it's possible to use both uint8_t, uint16_t and uint32_t
+ */
+typedef uint32_t dma_input_data_type;
+
+dma_input_data_type test_data[SIZE_IN_D1 * SIZE_IN_D2] = {
+    93 ,178 ,28 ,23 ,5 ,231 ,211 ,236 ,45 ,196 ,55 ,124 ,113 ,188 ,36 ,43 ,147 ,111 ,254 ,126 ,145 ,83 ,77 ,7 ,126,
+    92 ,179 ,157 ,41 ,64 ,7 ,105 ,93 ,176 ,196 ,171 ,42 ,251 ,175 ,120 ,63 ,134 ,56 ,233 ,0 ,189 ,133 ,71 ,226 ,9,
+    252 ,214 ,243 ,177 ,205 ,75 ,100 ,165 ,160 ,42 ,112 ,71 ,238 ,208 ,62 ,1 ,113 ,87 ,116 ,212 ,107 ,165 ,214 ,239 ,151,
+    215 ,3 ,80 ,243 ,0 ,18 ,30 ,149 ,237 ,35 ,81 ,149 ,227 ,23 ,240 ,13 ,117 ,122 ,158 ,253 ,120 ,175 ,203 ,30 ,204,
+    45 ,18 ,176 ,241 ,38 ,232 ,189 ,208 ,50 ,120 ,4 ,47 ,136 ,141 ,154 ,207 ,180 ,160 ,46 ,191 ,48 ,29 ,122 ,30 ,45,
+    56 ,8 ,137 ,197 ,185 ,210 ,103 ,123 ,116 ,25 ,57 ,126 ,41 ,213 ,165 ,17 ,111 ,151 ,39 ,115 ,21 ,59 ,220 ,165 ,142,
+    175 ,169 ,150 ,41 ,68 ,241 ,228 ,121 ,125 ,163 ,16 ,244 ,157 ,8 ,205 ,148 ,194 ,115 ,7 ,59 ,164 ,127 ,88 ,184 ,215,
+    13 ,6 ,102 ,204 ,29 ,15 ,182 ,125 ,141 ,251 ,172 ,13 ,159 ,196 ,93 ,200 ,211 ,42 ,10 ,154 ,105 ,82 ,109 ,175 ,117,
+    115 ,109 ,201 ,196 ,242 ,139 ,178 ,191 ,190 ,181 ,140 ,197 ,233 ,34 ,69 ,20 ,193 ,35 ,243 ,11 ,41 ,131 ,196 ,8 ,133,
+    70 ,234 ,210 ,171 ,107 ,57 ,133 ,162 ,114 ,168 ,118 ,250 ,12 ,30 ,223 ,95 ,246 ,122 ,73 ,220 ,247 ,6 ,102 ,214 ,108,
+    48 ,55 ,22 ,243 ,241 ,45 ,147 ,32 ,105 ,25 ,185 ,22 ,41 ,2 ,5 ,82 ,221 ,237 ,223 ,162 ,77 ,95 ,62 ,198 ,97,
+    206 ,210 ,61 ,7 ,163 ,142 ,20 ,215 ,35 ,92 ,232 ,88 ,52 ,207 ,137 ,234 ,123 ,251 ,214 ,221 ,23 ,19 ,51 ,245 ,188,
+    251 ,139 ,176 ,240 ,126 ,29 ,247 ,228 ,248 ,164 ,14 ,198 ,143 ,15 ,178 ,72 ,238 ,220 ,145 ,7 ,253 ,233 ,245 ,32 ,95,
+    142 ,30 ,227 ,66 ,67 ,177 ,47 ,2 ,87 ,155 ,74 ,255 ,1 ,69 ,157 ,181 ,73 ,57 ,60 ,39 ,64 ,93 ,146 ,4 ,220,
+    129 ,219 ,109 ,159 ,65 ,112 ,162 ,145 ,241 ,59 ,55 ,21 ,12 ,196 ,239 ,239 ,31 ,58 ,148 ,215 ,241 ,109 ,72 ,108 ,61,
+    178 ,205 ,116 ,33 ,240 ,137 ,150 ,150 ,148 ,80 ,211 ,87 ,46 ,160 ,64 ,9 ,179 ,221 ,91 ,113 ,87 ,132 ,141 ,70 ,95,
+    104 ,62 ,121 ,12 ,149 ,108 ,197 ,154 ,51 ,247 ,78 ,121 ,186 ,124 ,140 ,138 ,155 ,117 ,221 ,55 ,233 ,1 ,61 ,190 ,220,
+    123 ,200 ,239 ,89 ,200 ,167 ,191 ,121 ,24 ,249 ,145 ,189 ,15 ,249 ,235 ,165 ,243 ,239 ,102 ,41 ,62 ,159 ,45 ,248 ,28,
+    128 ,200 ,95 ,240 ,148 ,118 ,168 ,156 ,62 ,88 ,102 ,14 ,197 ,252 ,135 ,54 ,170 ,249 ,133 ,250 ,172 ,67 ,60 ,35 ,246,
+    7 ,9 ,7 ,181 ,49 ,60 ,239 ,70 ,33 ,29 ,132 ,112 ,37 ,28 ,34 ,233 ,37 ,178 ,40 ,20 ,189 ,43 ,45 ,65 ,194,
+    104 ,43 ,31 ,59 ,49 ,157 ,15 ,198 ,205 ,47 ,201 ,88 ,49 ,199 ,55 ,223 ,43 ,13 ,118 ,225 ,175 ,94 ,222 ,236 ,10,
+    157 ,75 ,239 ,221 ,34 ,14 ,26 ,232 ,18 ,240 ,198 ,3 ,23 ,226 ,110 ,118 ,172 ,0 ,17 ,210 ,136 ,226 ,223 ,162 ,169,
+    4 ,35 ,179 ,115 ,9 ,54 ,89 ,178 ,2 ,108 ,123 ,178 ,61 ,107 ,228 ,73 ,70 ,46 ,236 ,102 ,179 ,182 ,49 ,130 ,229,
+    72 ,159 ,179 ,125 ,24 ,152 ,13 ,104 ,186 ,2 ,174 ,204 ,191 ,241 ,158 ,84 ,96 ,184 ,19 ,171 ,135 ,101 ,27 ,218 ,217,
+    211 ,180 ,172 ,64 ,213 ,56 ,76 ,16 ,82 ,205 ,105 ,165 ,185 ,61 ,19 ,158 ,252 ,192 ,135 ,110 ,246 ,84 ,2 ,18 ,72};
+
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c
index a4fa35a7..e73f84af 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c
@@ -20,7 +20,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
@@ -29,7 +29,7 @@
 
 int32_t errors = 0;
 
-void dma_intr_handler_trans_done()
+void dma_intr_handler_trans_done(uint8_t channel)
 {
     PRINTF("D");
 }
@@ -82,11 +82,11 @@ int main(int argc, char *argv[])
     res = dma_launch(&trans);
     PRINTF("laun: %u \t%s\n\r", res, res == DMA_CONFIG_OK ?  "Ok!" : "Error!");
 
-    while( ! dma_is_ready() ){
+    while( ! dma_is_ready(0) ){
         // disable_interrupts
         // this does not prevent waking up the core as this is controlled by the MIP register
         CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-        if ( dma_is_ready() == 0 ) {
+        if ( dma_is_ready(0) == 0 ) {
             wait_for_interrupt();
             //from here we wake up even if we did not jump to the ISR
         }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c
new file mode 100644
index 00000000..2e7f2bc8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c
@@ -0,0 +1,1261 @@
+/*
+ *  Copyright EPFL contributors.
+ *  Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *  
+ *  Info: Example application of matrix manipulation by exploiting the multichannel feature of the DMA subsystem.
+ *        This code is capable of testing the following features:
+ *        - Verification of matrix operations carried out by the DMA subsystem
+ *        - Performance comparison between the DMA multichannel and the CPU, obtained by performing similar matrix operations
+ *          and monitoring the performance counter. 
+ *          The performance of the DMA is compared against sequential CPU loops for each operation performed by a single channel.
+ *          A typical case in which the DMA could be used to improve the performance is a series of matrix operations, 
+ *          like extracting 3 matrices from a larger one.
+ *          By exploiting the DMA, these three separate calls can be performed in parallel.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "dma.h"
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+#include "csr.h"
+#include "rv_plic.h"
+#include "test_data.h"
+#include "w25q128jw.h"
+
+/*   
+ *  The following code is designed to test the DMA subsystem multichannel feature. In order to do so, several
+ *  tests are available, which are run using some or all of the DMA channels available.
+ * 
+ *  DISCLAIMER:
+ *  When using the default memory configuration (64kB), pay attention to the dimensions of the output matrices.
+ *  When executing TEST_ID_4 on QuestaSim, make sure to enable the SPI FLASH.
+ * 
+ *  Enable one or more of the following tests by defining the correct TEST_ID_* macro:
+ *  
+ *  0: Extract a NxM matrix, perform optional padding and copy the result to two separate
+ *     AxB matrices using N channels at the same time and using direct register writes. 
+ *     Additionally, each DMA channel is set with a window of M size. For each window interrupt,
+ *     the correct window flag is set.
+ * 
+ *  1: Extract a NxM matrix, perform optional padding and copy the result to two separate
+ *     AxB matrices using N channels at the same time and using HALs. For each transaction interrupt, 
+ *     the correct transaction flag is set.
+ * 
+ *  2: Each DMA channel performs, alternatively, one of the following operations:
+ *      - Extract a NxM matrix, perform optional padding and copy the result
+ *      - Extract a NxM matrix, perform optional padding, transpose it and copy the result
+ * 
+ *  3: Extract a NxM matrix, perform optional padding and copy the result to a location using one channel (with HALs), 
+ *     while at the same time read a buffer from SPI and copy it to another location using another channel (with HALs).
+ *     This test can only be performed on FPGA boards or using QuestaSim, by setting the correct macro (SIM_QUESTASIM).
+ *     When executing on QuestaSim, make sure to compile in the correct way:
+ *     - Include LINKER=flash_load in "make app ..."
+ *     - Add boot_sel and execute_from_flash: 
+ *       'make run PLUSARGS="c firmware=../../../sw/build/main.hex boot_sel=1 execute_from_flash=0" '
+ *     
+ */
+
+#define TEST_ID_0
+#define TEST_ID_1
+#define TEST_ID_2
+#define TEST_ID_3
+
+/* Enable performance analysis */
+#define EN_PERF 1
+
+/* Enable verification */
+#define EN_VERIF 1
+
+/* Parameters */
+
+/* Size of the extracted matrix (including strides on the input, excluding strides on the outputs) */
+#define SIZE_EXTR_D1 10
+#define SIZE_EXTR_D2 10
+
+/* Set strides of the input ad output matrix */
+#define STRIDE_IN_D1 1
+#define STRIDE_IN_D2 1
+#define STRIDE_OUT_D1 1
+#define STRIDE_OUT_D2 1
+
+/* Set the padding parameters */
+#define TOP_PAD 0
+#define BOTTOM_PAD 0
+#define LEFT_PAD 0
+#define RIGHT_PAD 0
+
+/* Macros for dimensions computation */
+#define OUT_D1_PAD ( SIZE_EXTR_D1 + LEFT_PAD + RIGHT_PAD )
+#define OUT_D2_PAD ( SIZE_EXTR_D2  + TOP_PAD + BOTTOM_PAD )
+#define OUT_D1_PAD_STRIDE ( (OUT_D1_PAD * STRIDE_OUT_D1) - (STRIDE_OUT_D1 - 1)  )
+#define OUT_D2_PAD_STRIDE ( (OUT_D2_PAD * STRIDE_OUT_D2) - (STRIDE_OUT_D2 - 1)  )
+#define OUT_DIM_1D ( OUT_D1_PAD_STRIDE  )
+#define OUT_DIM_2D ( OUT_D1_PAD_STRIDE * OUT_D2_PAD_STRIDE )
+
+/* 
+ * Window size for the DMA. Since it has to be > 71 for the ISR to have the time to react,
+ * the OUT_DIM_2D has to be big enough. DMA_WINDOW_SIZE is by default set to 80 for good measure.
+ */
+
+#define DMA_WINDOW_SIZE 80 
+
+#if defined(TEST_ID_0) && ((OUT_DIM_2D < DMA_WINDOW_SIZE) || (DMA_WINDOW_SIZE < 72))
+    #error "In order to correctly execute TEST_ID_0, the matrix output dimension has to be bigger than 72 and bigger than the window dimension.\nCheck these parameters and recompile.\n"
+#endif
+
+/* Defines for DMA channels */
+#define DMA_CH0_IDX 0
+#define DMA_CH1_IDX 1
+#define DMA_CH2_IDX 2
+#define DMA_CH3_IDX 3
+
+/* Assigning a pointer to a define writes the pointed array in the flash */
+#define TEST_DATA_FLASH_PTR test_data_flash
+
+/* Mask for direct register operations example */
+#define DMA_CSR_REG_MIE_MASK (( 1 << 19 ) | (1 << 11 ))
+
+/* Transposition example def */
+#define TRANSPOSITION_EN 1
+
+/* Pointer increments computation */
+#define SRC_INC_D1 STRIDE_IN_D1
+#define DST_INC_D1 STRIDE_OUT_D1
+#define SRC_INC_D2 (STRIDE_IN_D2 * SIZE_IN_D1 - (SIZE_EXTR_D1 - 1 + (STRIDE_IN_D1 - 1) * (SIZE_EXTR_D1 - 1)))
+#define DST_INC_D2 ((STRIDE_OUT_D2 - 1) * OUT_DIM_1D + 1)
+#define SRC_INC_TRSP_D1 SRC_INC_D1
+#define SRC_INC_TRSP_D2 (STRIDE_IN_D2 * SIZE_IN_D1)
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_IS_FPGA && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+/* FPGA SPI board selection */
+#if !TARGET_SIM
+    #define USE_SPI_FLASH
+#endif
+
+/* QuestaSim macro to enable test 4, by default is disabled */
+//#define SIM_QUESTASIM
+
+/* Size of FLASH buffer */
+#define TEST_DATA_FLASH_SIZE 32
+
+/* Memory allocation for examples */
+uint32_t copied_test_data_flash[TEST_DATA_FLASH_SIZE];
+dma_input_data_type copied_data_2D_DMA[DMA_CH_NUM][OUT_DIM_2D];
+dma_input_data_type copied_data_2D_CPU[DMA_CH_NUM][OUT_DIM_2D];
+
+#if (TARGET_SIM == 0 || defined(TARGET_QUESTASIM))
+/* Data for TEST_ID_3 to be stored in the FLASH */
+uint32_t __attribute__((section(".xheep_data_flash_only"))) __attribute__ ((aligned (16))) test_data_flash[TEST_DATA_FLASH_SIZE] = {
+    105 ,82 ,221 ,172 ,77 ,62,
+    81 ,185 ,33 ,213 ,249 ,117,
+    69 ,212 ,99 ,137 ,9 ,233,
+    107 ,105 ,166 ,141 ,53 ,207,
+    53 ,21 ,221 ,102 ,84 ,108,
+    43 ,99 ,123 ,71 ,30 ,179
+    };
+
+/* Data for TEST_ID_3 to compare the copied data from the FLASH */
+uint32_t test_data_flash_golden[TEST_DATA_FLASH_SIZE] = {
+    105 ,82 ,221 ,172 ,77 ,62,
+    81 ,185 ,33 ,213 ,249 ,117,
+    69 ,212 ,99 ,137 ,9 ,233,
+    107 ,105 ,166 ,141 ,53 ,207,
+    53 ,21 ,221 ,102 ,84 ,108,
+    43 ,99 ,123 ,71 ,30 ,179
+    };
+#endif
+
+/* DMA source, destination and transaction */
+dma_target_t tgt_src;
+dma_target_t tgt_src_trsp;
+dma_target_t tgt_dst[DMA_CH_NUM];
+dma_trans_t trans[DMA_CH_NUM];
+
+dma_config_flags_t res_valid, res_load, res_launch;
+
+/* CPU computation variables */
+uint32_t dst_ptr = 0, src_ptr = 0;
+uint32_t cycles_dma, cycles_cpu;
+uint32_t size_dst_trans_d1;
+uint32_t dst_stride_d1;
+uint32_t dst_stride_d2;
+uint32_t size_src_trans_d1;
+uint32_t src_stride_d1;
+uint32_t src_stride_d2;
+uint32_t i_in;
+uint32_t j_in;
+uint32_t i_in_last;
+uint32_t j_in_last;
+uint16_t left_pad_cnt = 0;
+uint16_t top_pad_cnt = 0;
+uint8_t stride_1d_cnt = 0;
+uint8_t stride_2d_cnt = 0;
+uint8_t transaction_flag[DMA_CH_NUM];
+uint8_t window_flag[DMA_CH_NUM];
+char passed = 1;
+char flag = 0;
+
+/* Strong transaction ISR implementation */
+void dma_intr_handler_trans_done(uint8_t channel)
+{
+    transaction_flag[channel] = 1;
+    return;
+}
+
+/* Strong window ISR implementation */
+void dma_intr_handler_window_done(uint8_t channel)
+{
+    window_flag[channel] = 1;
+    return;
+}
+
+int main()
+{
+
+    #ifdef TEST_ID_0
+
+    /* 
+     * Testing copy and padding of a NxM matrix using direct register operations.
+     * This strategy allows for maximum performance but doesn't perform any checks on the data integrity.
+     * The data is copied using N channels to N different memory locations.
+     */
+    
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    /* The DMA channels are initialized (i.e. Any current transaction is cleaned.) */
+    dma_init(NULL);
+
+    plic_Init();
+    plic_irq_set_priority( DMA_WINDOW_INTR, 1);
+    plic_irq_set_enabled(  DMA_WINDOW_INTR, kPlicToggleEnabled);
+
+    /* Enable global interrupts */
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+    /* Enable fast interrupts */
+    CSR_SET_BITS(CSR_REG_MIE, DMA_CSR_REG_MIE_MASK);
+
+    
+    for (int i=0; i<DMA_CH_NUM; i++)
+    {
+        /* Enable the DMA transaction interrupt logic for every channel */
+        write_register(  
+                    0x1,
+                    DMA_INTERRUPT_EN_REG_OFFSET,
+                    0xffff,
+                    DMA_INTERRUPT_EN_TRANSACTION_DONE_BIT,
+                    dma_peri(i)
+                    );
+
+        /* Enable the DMA transaction interrupt logic for every channel */
+        write_register(  
+                    0x1,
+                    DMA_INTERRUPT_EN_REG_OFFSET,
+                    0xffff,
+                    DMA_INTERRUPT_EN_WINDOW_DONE_BIT,
+                    dma_peri(i)
+                    );
+                    
+        /* Pointer set up */
+        dma_peri(i)->SRC_PTR = &test_data[0];
+        dma_peri(i)->DST_PTR = copied_data_2D_DMA[i];
+
+        /* Dimensionality configuration */
+        write_register( 0x1,
+                        DMA_DIM_CONFIG_REG_OFFSET,
+                        0x1,
+                        DMA_DIM_CONFIG_DMA_DIM_BIT,
+                        dma_peri(i) );
+
+        /* Operation mode configuration */
+        write_register( DMA_TRANS_MODE_SINGLE,
+                        DMA_MODE_REG_OFFSET,
+                        DMA_MODE_MODE_MASK,
+                        DMA_MODE_MODE_OFFSET,
+                        dma_peri(i) );
+
+        /* Data type configuration */
+        write_register(  DMA_DATA_TYPE,
+                        DMA_DST_DATA_TYPE_REG_OFFSET,
+                        DMA_DST_DATA_TYPE_DATA_TYPE_MASK,
+                        DMA_DST_DATA_TYPE_DATA_TYPE_OFFSET,
+                        dma_peri(i)  );
+    
+        write_register(  DMA_DATA_TYPE,
+                        DMA_SRC_DATA_TYPE_REG_OFFSET,
+                        DMA_SRC_DATA_TYPE_DATA_TYPE_MASK,
+                        DMA_SRC_DATA_TYPE_DATA_TYPE_OFFSET,
+                        dma_peri(i) );
+
+        /* Set the source strides */
+        write_register( SRC_INC_D1 * DMA_DATA_TYPE_2_SIZE(DMA_DATA_TYPE),
+                        DMA_SRC_PTR_INC_D1_REG_OFFSET,
+                        DMA_SRC_PTR_INC_D1_INC_MASK,
+                        DMA_SRC_PTR_INC_D1_INC_OFFSET,
+                        dma_peri(i) );
+        
+        write_register( SRC_INC_D2 * DMA_DATA_TYPE_2_SIZE(DMA_DATA_TYPE),
+                        DMA_SRC_PTR_INC_D2_REG_OFFSET,
+                        DMA_SRC_PTR_INC_D2_INC_MASK,
+                        DMA_SRC_PTR_INC_D2_INC_OFFSET,
+                        dma_peri(i) );
+        
+        write_register( DST_INC_D1 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_DST_PTR_INC_D1_REG_OFFSET,
+                        DMA_DST_PTR_INC_D1_INC_MASK,
+                        DMA_DST_PTR_INC_D1_INC_OFFSET,
+                        dma_peri(i) );
+        
+        write_register( DST_INC_D2 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_DST_PTR_INC_D2_REG_OFFSET,
+                        DMA_DST_PTR_INC_D2_INC_MASK,
+                        DMA_DST_PTR_INC_D2_INC_OFFSET,
+                        dma_peri(i) );
+        
+        /* Padding configuration */
+        write_register( TOP_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_PAD_TOP_REG_OFFSET,
+                        DMA_PAD_TOP_PAD_MASK,
+                        DMA_PAD_TOP_PAD_OFFSET,
+                        dma_peri(i) );
+        
+        write_register( RIGHT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_PAD_RIGHT_REG_OFFSET,
+                        DMA_PAD_RIGHT_PAD_MASK,
+                        DMA_PAD_RIGHT_PAD_OFFSET,
+                        dma_peri(i) );
+        
+        write_register( LEFT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_PAD_LEFT_REG_OFFSET,
+                        DMA_PAD_LEFT_PAD_MASK,
+                        DMA_PAD_LEFT_PAD_OFFSET,
+                        dma_peri(i) );
+        
+        write_register( BOTTOM_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_PAD_BOTTOM_REG_OFFSET,
+                        DMA_PAD_BOTTOM_PAD_MASK,
+                        DMA_PAD_BOTTOM_PAD_OFFSET,
+                        dma_peri(i) );
+
+        /* Set the window size */
+        write_register( DMA_WINDOW_SIZE,
+                        DMA_WINDOW_SIZE_REG_OFFSET,
+                        DMA_WINDOW_SIZE_WINDOW_SIZE_MASK,
+                        DMA_WINDOW_SIZE_WINDOW_SIZE_OFFSET,
+                        dma_peri(i) );        
+    }
+
+    for (int i=0; i<DMA_CH_NUM; i++)
+    {
+        /* Set the sizes to start the transaction */
+        write_register( SIZE_EXTR_D2 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_SIZE_D2_REG_OFFSET,
+                        DMA_SIZE_D2_SIZE_MASK,
+                        DMA_SIZE_D2_SIZE_OFFSET,
+                        dma_peri(i) );
+        
+        write_register( SIZE_EXTR_D1 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+                        DMA_SIZE_D1_REG_OFFSET,
+                        DMA_SIZE_D1_SIZE_MASK,
+                        DMA_SIZE_D1_SIZE_OFFSET,
+                        dma_peri(i) );
+    }
+
+    /* Wait for CH(N-1) to end */
+    while(!dma_is_ready(DMA_CH_NUM-1)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+            /* From here the core wakes up even if we did not jump to the ISR */
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+
+    #if EN_PERF
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        i_in = 0;
+        left_pad_cnt = 0;
+        top_pad_cnt = 0;
+        stride_2d_cnt = 0;
+
+        for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+        {
+            stride_1d_cnt = 0;
+            j_in = 0;
+
+            for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+            {
+                dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+                src_ptr = (i_in - top_pad_cnt ) * STRIDE_IN_D2 * SIZE_IN_D1 + (j_in - left_pad_cnt) * STRIDE_IN_D1;
+                if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                    stride_1d_cnt != 0 || stride_2d_cnt != 0)
+                {
+                    copied_data_2D_CPU[c][dst_ptr] = 0;
+                }
+                else
+                {
+                    copied_data_2D_CPU[c][dst_ptr] = test_data[src_ptr];
+                }
+
+                if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+                {
+                    left_pad_cnt++;
+                }
+
+                if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+                {
+                    stride_1d_cnt = 0;
+                    j_in++;
+                }
+                else
+                {
+                    stride_1d_cnt++;
+                }
+
+            }
+
+            if (i_in < TOP_PAD && stride_2d_cnt == 0)
+            {
+                top_pad_cnt++;
+            }
+            
+            if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+            {
+                stride_2d_cnt = 0;
+                i_in++;
+            }
+            else
+            {
+                stride_2d_cnt++;
+            }
+
+            left_pad_cnt = 0;
+        }
+    }
+    
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+    #endif
+
+    #if EN_VERIF
+
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
+            for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
+                if ((copied_data_2D_CPU[c][i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_DMA[c][i * OUT_D1_PAD_STRIDE + j])) 
+                {
+                    passed = 0;
+                }
+            }
+        }
+    }
+
+    /* Verify that the window flags where correctly set */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        if (window_flag[c] == 0)
+        {
+            passed = 0;
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 0\n\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 0\n\r");
+        return EXIT_FAILURE;
+    }
+
+    #endif 
+
+    #endif
+    
+    #ifdef TEST_ID_1
+
+    /* Testing copy and padding of a NxM matrix to two different locations using 2 channels and HALs */
+    
+    /* Reset for third test */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        for (int i = 0; i < OUT_DIM_2D; i++) {
+            copied_data_2D_DMA[c][i] = 0;
+            copied_data_2D_CPU[c][i] = 0;
+        }
+    }
+
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    dma_init(NULL);
+
+    tgt_src.ptr            = (uint8_t *) test_data;
+    tgt_src.inc_du         = SRC_INC_D1;
+    tgt_src.inc_d2_du      = SRC_INC_D2;
+    tgt_src.size_du        = SIZE_EXTR_D1;
+    tgt_src.size_d2_du     = SIZE_EXTR_D2;
+    tgt_src.trig           = DMA_TRIG_MEMORY;
+    tgt_src.type           = DMA_DATA_TYPE;
+
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        tgt_dst[c].ptr            = (uint8_t *) copied_data_2D_DMA[c];
+        tgt_dst[c].inc_du         = DST_INC_D1;
+        tgt_dst[c].inc_d2_du      = DST_INC_D2;
+        tgt_dst[c].trig           = DMA_TRIG_MEMORY;
+
+        trans[c].src            = &tgt_src;
+        trans[c].dst            = &tgt_dst[c];
+        trans[c].mode           = DMA_TRANS_MODE_SINGLE;
+        trans[c].dim            = DMA_DIM_CONF_2D;
+        trans[c].pad_top_du     = TOP_PAD;
+        trans[c].pad_bottom_du  = BOTTOM_PAD;
+        trans[c].pad_left_du    = LEFT_PAD;
+        trans[c].pad_right_du   = RIGHT_PAD;
+        trans[c].win_du         = 0;
+        trans[c].end            = DMA_TRANS_END_INTR;
+        trans[c].channel        = c;
+        
+        #if EN_PERF
+
+        dma_validate_transaction(&trans[c], DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+        dma_load_transaction(&trans[c]);
+        dma_launch(&trans[c]);
+        
+        #else
+
+        res_valid = dma_validate_transaction(&trans[c], DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+        PRINTF("tran: %u \t%s\n\r", res_valid, res_valid == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+        res_load = dma_load_transaction(&trans[c]);
+        PRINTF("load: %u \t%s\n\r", res_load, res_load == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+        res_launch = dma_launch(&trans[c]);
+        PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+        #endif
+    }
+
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        #if EN_PERF
+        dma_launch(&trans[c]);
+        #else
+        res_launch = dma_launch(&trans[c]);
+        PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+        #endif
+    }
+
+    /* Wait for CH1 to end */
+    while(!dma_is_ready(DMA_CH_NUM-1)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+            /* From here the core wakes up even if we did not jump to the ISR */
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+
+    #if EN_PERF    
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        i_in = 0;
+        left_pad_cnt = 0;
+        top_pad_cnt = 0;
+        stride_2d_cnt = 0;
+
+        for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+        {
+            stride_1d_cnt = 0;
+            j_in = 0;
+
+            for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+            {
+                dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+                src_ptr = (i_in - top_pad_cnt ) * STRIDE_IN_D2 * SIZE_IN_D1 + (j_in - left_pad_cnt) * STRIDE_IN_D1;
+                if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                    stride_1d_cnt != 0 || stride_2d_cnt != 0)
+                {
+                    copied_data_2D_CPU[c][dst_ptr] = 0;
+                }
+                else
+                {
+                    copied_data_2D_CPU[c][dst_ptr] = test_data[src_ptr];
+                }
+
+                if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+                {
+                    left_pad_cnt++;
+                }
+
+                if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+                {
+                    stride_1d_cnt = 0;
+                    j_in++;
+                }
+                else
+                {
+                    stride_1d_cnt++;
+                }
+
+            }
+
+            if (i_in < TOP_PAD && stride_2d_cnt == 0)
+            {
+                top_pad_cnt++;
+            }
+            
+            if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+            {
+                stride_2d_cnt = 0;
+                i_in++;
+            }
+            else
+            {
+                stride_2d_cnt++;
+            }
+
+            left_pad_cnt = 0;
+        }
+    }
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+
+    #endif
+
+    #if EN_VERIF
+
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
+            for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
+                if (copied_data_2D_DMA[c][i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_CPU[c][i * OUT_D1_PAD_STRIDE + j]) 
+                {
+                    passed = 0;
+                }
+            }
+        }
+    }
+
+    /* Verify that the transaction flags where correctly set */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        if (transaction_flag[c] == 0)
+        {
+            passed = 0;
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 1\n\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 1\n\r");
+        return EXIT_FAILURE;
+    }
+    #endif
+
+    #endif
+    
+    #ifdef TEST_ID_2
+    
+    /* Transposing and standard matrix manipulation DMA test */
+
+    /* Reset for third test */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        for (int i = 0; i < OUT_DIM_2D; i++) {
+            copied_data_2D_DMA[c][i] = 0;
+            copied_data_2D_CPU[c][i] = 0;
+        }
+    }
+    
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    tgt_src.ptr            = (uint8_t *) test_data;
+    tgt_src.inc_du         = SRC_INC_D1;
+    tgt_src.inc_d2_du      = SRC_INC_D2;
+    tgt_src.size_du        = SIZE_EXTR_D1;
+    tgt_src.size_d2_du     = SIZE_EXTR_D2;
+    tgt_src.trig           = DMA_TRIG_MEMORY;
+    tgt_src.type           = DMA_DATA_TYPE;
+
+    tgt_src_trsp.ptr            = (uint8_t *) test_data;
+    tgt_src_trsp.inc_du         = SRC_INC_TRSP_D1;
+    tgt_src_trsp.inc_d2_du      = SRC_INC_TRSP_D2;
+    tgt_src_trsp.size_du        = SIZE_EXTR_D1;
+    tgt_src_trsp.size_d2_du     = SIZE_EXTR_D2;
+    tgt_src_trsp.trig           = DMA_TRIG_MEMORY;
+    tgt_src_trsp.type           = DMA_DATA_TYPE;
+
+    dma_init(NULL);
+
+    /* Reset flag to alternate DMA functions */
+    flag = 0;
+
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        tgt_dst[c].ptr            = (uint8_t *) copied_data_2D_DMA[c];
+        tgt_dst[c].inc_du         = DST_INC_D1;
+        tgt_dst[c].inc_d2_du      = DST_INC_D2;
+        tgt_dst[c].trig           = DMA_TRIG_MEMORY;
+
+        if (flag == 0)
+        {
+            trans[c].src            = &tgt_src;
+            trans[c].dst            = &tgt_dst[c];
+            trans[c].mode           = DMA_TRANS_MODE_SINGLE;
+            trans[c].dim            = DMA_DIM_CONF_2D;
+            trans[c].pad_top_du     = TOP_PAD;
+            trans[c].pad_bottom_du  = BOTTOM_PAD;
+            trans[c].pad_left_du    = LEFT_PAD;
+            trans[c].pad_right_du   = RIGHT_PAD;
+            trans[c].win_du         = 0;
+            trans[c].end            = DMA_TRANS_END_INTR;
+            trans[c].channel        = c;
+            flag = 1;
+        } 
+        else
+        {
+            trans[c].src            = &tgt_src_trsp;
+            trans[c].dst            = &tgt_dst[c];
+            trans[c].mode           = DMA_TRANS_MODE_SINGLE;
+            trans[c].dim            = DMA_DIM_CONF_2D;
+            trans[c].pad_top_du     = TOP_PAD;
+            trans[c].pad_bottom_du  = BOTTOM_PAD;
+            trans[c].pad_left_du    = LEFT_PAD;
+            trans[c].pad_right_du   = RIGHT_PAD;
+            trans[c].win_du         = 0;
+            trans[c].end            = DMA_TRANS_END_INTR;
+            trans[c].dim_inv        = TRANSPOSITION_EN;
+            trans[c].channel        = c;
+            flag = 0;
+        }
+        
+        #if EN_PERF
+
+        dma_validate_transaction(&trans[c], DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+        dma_load_transaction(&trans[c]);
+        
+        #else
+
+        res_valid = dma_validate_transaction(&trans[c], DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+        PRINTF("tran: %u \t%s\n\r", res_valid, res_valid == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+        res_load = dma_load_transaction(&trans[c]);
+        PRINTF("load: %u \t%s\n\r", res_load, res_load == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+        #endif
+    }
+
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        #if EN_PERF
+        dma_launch(&trans[c]);
+        #else
+        res_launch = dma_launch(&trans[c]);
+        PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+        #endif
+    }
+
+    /* Wait for CH(DMA_CH_NUM-1) to end */
+    while(!dma_is_ready(DMA_CH_NUM-1)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+            /* From here the core wakes up even if we did not jump to the ISR */
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+    
+
+    #if EN_PERF    
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    flag = 0;
+    for (int c=0; c<DMA_CH_NUM; c++)
+    { 
+        j_in_last = -1;
+        stride_2d_cnt = 0;
+        left_pad_cnt = 0;
+        j_in = 0;
+        i_in = 0;
+        top_pad_cnt = 0;
+
+        if (flag == 0)
+        {
+            for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+            {
+                stride_1d_cnt = 0;
+                j_in = 0;
+
+                for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+                {
+                    dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+                    src_ptr = (i_in - top_pad_cnt ) * STRIDE_IN_D2 * SIZE_IN_D1 + (j_in - left_pad_cnt) * STRIDE_IN_D1;
+                    if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                        stride_1d_cnt != 0 || stride_2d_cnt != 0)
+                    {
+                        copied_data_2D_CPU[c][dst_ptr] = 0;
+                    }
+                    else
+                    {
+                        copied_data_2D_CPU[c][dst_ptr] = test_data[src_ptr];
+                    }
+
+                    if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+                    {
+                        left_pad_cnt++;
+                    }
+
+                    if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+                    {
+                        stride_1d_cnt = 0;
+                        j_in++;
+                    }
+                    else
+                    {
+                        stride_1d_cnt++;
+                    }
+
+                }
+
+                if (i_in < TOP_PAD && stride_2d_cnt == 0)
+                {
+                    top_pad_cnt++;
+                }
+                
+                if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+                {
+                    stride_2d_cnt = 0;
+                    i_in++;
+                }
+                else
+                {
+                    stride_2d_cnt++;
+                }
+
+                left_pad_cnt = 0;
+            }
+            flag = 1;
+        } 
+        else
+        {
+            for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+            {
+                stride_1d_cnt = 0;
+                j_in = 0;
+
+                for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+                {
+                    dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+                    src_ptr = (j_in - left_pad_cnt) * STRIDE_IN_D2 * SIZE_IN_D1 + (i_in - top_pad_cnt ) * STRIDE_IN_D1;
+                    if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                        stride_1d_cnt != 0 || stride_2d_cnt != 0)
+                    {
+                        copied_data_2D_CPU[c][dst_ptr] = 0;
+                    }
+                    else
+                    {
+                        copied_data_2D_CPU[c][dst_ptr] = test_data[src_ptr];
+                    }
+
+                    if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+                    {
+                        left_pad_cnt++;
+                    }
+
+                    if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+                    {
+                        stride_1d_cnt = 0;
+                        j_in++;
+                    }
+                    else
+                    {
+                        stride_1d_cnt++;
+                    }
+
+                }
+
+                if (i_in < TOP_PAD && stride_2d_cnt == 0)
+                {
+                    top_pad_cnt++;
+                }
+
+                if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+                {
+                    stride_2d_cnt = 0;
+                    i_in++;
+                }
+                else
+                {
+                    stride_2d_cnt++;
+                }
+
+                left_pad_cnt = 0;
+            }
+            flag = 0;
+        }
+    }
+    
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+
+    #endif
+
+    #if EN_VERIF
+
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int c=0; c<DMA_CH_NUM; c++)
+    {
+        for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
+            for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
+                if (copied_data_2D_DMA[c][i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_CPU[c][i * OUT_D1_PAD_STRIDE + j])
+                {
+                    passed = 0;
+                }
+            }
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 2\n\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 2\n\r");
+        return EXIT_FAILURE;
+    }
+    #endif
+
+    #endif
+
+    #if defined(TEST_ID_3) && (TARGET_SIM == 0 || defined(TARGET_QUESTASIM)) && DMA_CH_NUM > 1
+
+    /* Testing SPI2RAM & RAM2RAM operations on 2 channels */
+
+    /* Reset for fourth test */
+    passed = 1;
+    i_in = 0;
+    j_in = 0;
+    left_pad_cnt = 0;
+    top_pad_cnt = 0;
+    stride_1d_cnt = 0;
+    stride_2d_cnt = 0;
+    for (int i = 0; i < OUT_DIM_2D; i++) {
+        copied_data_2D_DMA[1][i] = 0;
+        copied_data_2D_CPU[1][i] = 0;
+    }
+
+    #if EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    dma_init(NULL);
+
+    tgt_src.ptr            = (uint8_t *) test_data;
+    tgt_src.inc_du         = SRC_INC_D1;
+    tgt_src.inc_d2_du      = SRC_INC_D2;
+    tgt_src.size_du        = SIZE_EXTR_D1;
+    tgt_src.size_d2_du     = SIZE_EXTR_D2;
+    tgt_src.trig           = DMA_TRIG_MEMORY;
+    tgt_src.type           = DMA_DATA_TYPE;
+
+    tgt_dst[1].ptr            = (uint8_t *) copied_data_2D_DMA[1];
+    tgt_dst[1].inc_du         = DST_INC_D1;
+    tgt_dst[1].inc_d2_du      = DST_INC_D2;
+    tgt_dst[1].trig           = DMA_TRIG_MEMORY;
+
+    trans[1].src            = &tgt_src;
+    trans[1].dst            = &tgt_dst[1];
+    trans[1].mode           = DMA_TRANS_MODE_SINGLE;
+    trans[1].dim            = DMA_DIM_CONF_2D;
+    trans[1].pad_top_du     = TOP_PAD;
+    trans[1].pad_bottom_du  = BOTTOM_PAD;
+    trans[1].pad_left_du    = LEFT_PAD;
+    trans[1].pad_right_du   = RIGHT_PAD;
+    trans[1].win_du         = 0;
+    trans[1].end            = DMA_TRANS_END_INTR;
+    trans[1].channel        = DMA_CH1_IDX;
+    
+    /* Initialize the SPI */
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+
+    if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO ) {
+        PRINTF("This application cannot work with the memory mapped SPI FLASH"
+            "module - do not use the FLASH_EXEC linker script for this application\n");
+        return EXIT_SUCCESS;
+    }
+
+    /* Pick the correct spi device based on simulation type */
+    spi_host_t *spi;
+    #ifndef USE_SPI_FLASH
+    spi = spi_host1;
+    #else
+    spi = spi_flash;
+    #endif
+
+    /* Init SPI host and SPI<->Flash bridge parameters */
+    if (w25q128jw_init(spi) != FLASH_OK)
+    {
+        PRINTF("Error initializing the flash SPI\n\r");
+        return EXIT_FAILURE;
+    }
+
+    /* Start the reading process from the SPI, avoiding both sanity checks and waiting for the DMA to finish */
+    w25q_error_codes_t status = w25q128jw_read_standard_dma(TEST_DATA_FLASH_PTR, copied_test_data_flash, TEST_DATA_FLASH_SIZE*4, 1, 1);
+    if (status != FLASH_OK)
+    {
+        PRINTF("Error reading from flash\n\r");
+        return EXIT_FAILURE;
+    }
+    
+    #if EN_PERF
+
+    dma_validate_transaction(&trans[1], DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    dma_load_transaction(&trans[1]);
+    dma_launch(&trans[1]);
+    
+    #else
+
+    res_valid = dma_validate_transaction(&trans_ch1, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    PRINTF("tran: %u \t%s\n\r", res_valid, res_valid == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_load = dma_load_transaction(&trans_ch1);
+    PRINTF("load: %u \t%s\n\r", res_load, res_load == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    res_launch = dma_launch(&trans_ch1);
+    PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
+    #endif
+
+    /* Wait for CH1 to end */
+    while(!dma_is_ready(1)) {
+        #if !EN_PERF
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(1) == 0 ) {
+            wait_for_interrupt();
+            /* From here the core wakes up even if we did not jump to the ISR */
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+        #endif
+    }
+
+    #if EN_PERF    
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+
+    /* Reset the performance counter to evaluate the CPU performance */
+    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    #endif
+
+    #if EN_VERIF
+
+    /* Run the same computation on the CPU */
+    for (int i=0; i < OUT_D2_PAD_STRIDE; i++)
+    {
+        stride_1d_cnt = 0;
+        j_in = 0;
+
+        for (int j=0; j < OUT_D1_PAD_STRIDE; j++)
+        {
+            dst_ptr = i * OUT_D1_PAD_STRIDE + j;
+            src_ptr = (i_in - top_pad_cnt ) * STRIDE_IN_D2 * SIZE_IN_D1 + (j_in - left_pad_cnt) * STRIDE_IN_D1;
+            if (i_in < TOP_PAD || i_in >= SIZE_EXTR_D2 + TOP_PAD || j_in < LEFT_PAD || j_in >= SIZE_EXTR_D1 + LEFT_PAD ||
+                stride_1d_cnt != 0 || stride_2d_cnt != 0)
+            {
+                copied_data_2D_CPU[1][dst_ptr] = 0;
+            }
+            else
+            {
+                copied_data_2D_CPU[1][dst_ptr] = test_data[src_ptr];
+            }
+
+            if (j_in < LEFT_PAD && i_in >= TOP_PAD && stride_1d_cnt == 0 && stride_2d_cnt == 0)
+            {
+                left_pad_cnt++;
+            }
+
+            if (stride_1d_cnt == STRIDE_OUT_D1 - 1)
+            {
+                stride_1d_cnt = 0;
+                j_in++;
+            }
+            else
+            {
+                stride_1d_cnt++;
+            }
+
+        }
+
+        if (i_in < TOP_PAD && stride_2d_cnt == 0)
+        {
+            top_pad_cnt++;
+        }
+        
+        if (stride_2d_cnt == STRIDE_OUT_D2 - 1)
+        {
+            stride_2d_cnt = 0;
+            i_in++;
+        }
+        else
+        {
+            stride_2d_cnt++;
+        }
+
+        left_pad_cnt = 0;
+    }
+    #endif
+
+    #if EN_PERF
+
+    /* Read the cycles count after the CPU run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+    PRINTF("DMA cycles: %d\n\r", cycles_dma);
+    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
+
+    #endif
+
+    #if EN_VERIF
+
+    /* Verify that the DMA and the CPU outputs are the same */
+    for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
+        for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
+            if ((copied_data_2D_DMA[1][i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_CPU[1][i * OUT_D1_PAD_STRIDE + j])) 
+            {
+                passed = 0;
+            }
+        }
+    }
+
+    /* Verify that the SPI copy was successful */
+    for (int i=0; i < TEST_DATA_FLASH_SIZE; i++)
+    {
+        if (copied_test_data_flash[i] != test_data_flash_golden[i])
+        {
+            passed = 0;
+        }
+    }
+
+    if (passed) {
+        PRINTF("Success test 3\n\r");
+    } 
+    else 
+    {
+        PRINTF("Fail test 3\n\r");
+        return EXIT_FAILURE;
+    }
+    #endif
+
+    #endif
+
+    return EXIT_SUCCESS;
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/test_data.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/test_data.h
new file mode 100644
index 00000000..c582490e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/test_data.h
@@ -0,0 +1,34 @@
+#ifndef __TEST_DATA_H__
+#define __TEST_DATA_H__
+
+#define SIZE_IN_D1 15
+#define SIZE_IN_D2 15
+#define DMA_DATA_TYPE DMA_DATA_TYPE_WORD
+
+/* 
+ * Change the input datatype depending on the DMA_DATA_TYPE.
+ * The test data has been generated using byte as datatype, so it's possible to use both uint8_t, uint16_t and uint32_t.
+ * NOTE: To fully evaluate the performance gains of the DMA it's recommended to increase the number of memory banks and
+ * the size of the data to be copied up ot at least 50x50.
+ */
+typedef uint32_t dma_input_data_type;
+
+dma_input_data_type test_data[SIZE_IN_D1 * SIZE_IN_D2] = {
+    236 ,19 ,35 ,109 ,59 ,58 ,216 ,210 ,72 ,169 ,123 ,74 ,132 ,27 ,208,
+    43 ,93 ,216 ,145 ,94 ,235 ,80 ,25 ,146 ,127 ,115 ,9 ,45 ,61 ,60,
+    78 ,218 ,28 ,230 ,140 ,236 ,152 ,242 ,98 ,173 ,20 ,206 ,176 ,157 ,219,
+    225 ,182 ,118 ,22 ,153 ,196 ,7 ,9 ,87 ,99 ,173 ,11 ,103 ,173 ,49,
+    122 ,185 ,128 ,93 ,243 ,29 ,172 ,32 ,207 ,64 ,184 ,40 ,165 ,87 ,157,
+    182 ,196 ,160 ,93 ,182 ,91 ,20 ,82 ,156 ,45 ,109 ,132 ,168 ,234 ,85,
+    121 ,39 ,188 ,109 ,190 ,127 ,192 ,124 ,149 ,90 ,247 ,68 ,26 ,82 ,57,
+    189 ,249 ,91 ,193 ,23 ,210 ,167 ,79 ,175 ,31 ,212 ,131 ,102 ,43 ,4,
+    192 ,184 ,234 ,9 ,81 ,4 ,221 ,12 ,181 ,76 ,64 ,131 ,59 ,26 ,83,
+    86 ,140 ,176 ,18 ,120 ,115 ,153 ,50 ,41 ,83 ,110 ,157 ,173 ,145 ,81,
+    9 ,120 ,250 ,3 ,27 ,119 ,64 ,195 ,48 ,245 ,160 ,78 ,177 ,246 ,59,
+    156 ,114 ,97 ,7 ,11 ,224 ,75 ,154 ,223 ,221 ,90 ,77 ,254 ,181 ,198,
+    193 ,254 ,161 ,177 ,201 ,3 ,182 ,18 ,36 ,23 ,67 ,46 ,116 ,229 ,166,
+    90 ,158 ,248 ,194 ,224 ,218 ,245 ,34 ,60 ,126 ,68 ,248 ,143 ,232 ,226,
+    58 ,202 ,172 ,209 ,229 ,89 ,246 ,184 ,215 ,7 ,163 ,204 ,43 ,116 ,33};
+;
+
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_sdk/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_sdk/main.c
new file mode 100644
index 00000000..22b3ce65
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_sdk/main.c
@@ -0,0 +1,112 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: example_dma_sdk.c
+// Author: Juan Sapriza
+// Date: 13/06/2024
+// Description: Example application to test the DMA SDK. Will copy
+//              a constant value in a buffer and then copy the content
+//              of the buffer into another. Will check that both transactions
+//              are performed correctly.
+
+#include <stdint.h>
+#include <stdio.h>              // For compatibility with OH Group compiler
+#include <stdlib.h>
+#include "dma_sdk.h"
+#include "dma.h"                // For compatibility with OH Group compiler
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+#include "csr.h"                // For compatibility with OH Group compiler
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA 1
+#define PRINTF_IN_SIM 0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define PRINTF(...)
+#endif
+
+#define SOURCE_BUFFER_SIZE_32b 5
+#define SOURCE_BUFFER_SIZE_16b 5
+#define SOURCE_BUFFER_SIZE_8b 5
+#define CONST_VALUE_32B 123
+#define CONST_NEG_VALUE_32B -123
+#define CONST_VALUE_16B 123
+#define CONST_NEG_VALUE_16B -123
+#define CONST_VALUE_8B 123
+#define CONST_NEG_VALUE_8B -123
+
+static uint32_t source_32b[SOURCE_BUFFER_SIZE_32b];
+static uint32_t destin_32b[SOURCE_BUFFER_SIZE_32b];
+
+static uint16_t destin_16b[SOURCE_BUFFER_SIZE_16b];
+static uint16_t source_16b[SOURCE_BUFFER_SIZE_16b];
+
+static uint8_t destin_8b[SOURCE_BUFFER_SIZE_8b];
+static uint8_t source_8b[SOURCE_BUFFER_SIZE_8b];
+
+static int32_t neg_source_32b[SOURCE_BUFFER_SIZE_32b];
+static int32_t neg_destin_32b[SOURCE_BUFFER_SIZE_32b];
+
+static int16_t neg_destin_16b[SOURCE_BUFFER_SIZE_16b];
+static int16_t neg_source_16b[SOURCE_BUFFER_SIZE_16b];
+
+static int8_t neg_destin_8b[SOURCE_BUFFER_SIZE_8b];
+static int8_t neg_source_8b[SOURCE_BUFFER_SIZE_8b];
+
+static uint32_t value_32b = CONST_VALUE_32B;
+static uint16_t value_16b = CONST_VALUE_16B;
+static uint8_t value_8b = CONST_VALUE_8B;
+
+static int32_t neg_value_32b = CONST_NEG_VALUE_32B;
+static int16_t neg_value_16b = CONST_NEG_VALUE_16B;
+static int8_t neg_value_8b = CONST_NEG_VALUE_8B;
+
+uint32_t i;
+uint32_t errors = 0;
+
+int main()
+{
+    dma_sdk_init();
+
+    dma_fill((uint32_t)source_32b, (uint32_t)&value_32b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD, 0);
+    dma_copy((uint32_t)destin_32b, (uint32_t)source_32b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD, 0);
+
+    for (i = 0; i < SOURCE_BUFFER_SIZE_32b; i++)
+    {
+        errors += destin_32b[i] != CONST_VALUE_32B;
+    }
+
+    dma_fill((uint32_t)source_16b, (uint32_t)&value_16b, SOURCE_BUFFER_SIZE_16b, 0, DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD, 0);
+    dma_copy((uint32_t)destin_16b, (uint32_t)source_16b, SOURCE_BUFFER_SIZE_16b, 0, DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD, 0);
+
+    for (i = 0; i < SOURCE_BUFFER_SIZE_16b; i++)
+    {
+        errors += destin_16b[i] != CONST_VALUE_16B;
+    }
+
+    dma_fill((uint32_t)source_8b, (uint32_t)&value_8b, SOURCE_BUFFER_SIZE_8b, 0, DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE, 0);
+    dma_copy((uint32_t)destin_8b, (uint32_t)source_8b, SOURCE_BUFFER_SIZE_8b, 0, DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE, 0);
+
+    for (i = 0; i < SOURCE_BUFFER_SIZE_8b; i++)
+    {
+        errors += destin_8b[i] != CONST_VALUE_8B;
+    }
+
+    dma_fill((uint32_t)neg_source_16b, (uint32_t)&neg_value_8b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD, 1);
+    dma_copy((uint32_t)neg_destin_32b, (uint32_t)neg_source_16b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD, 1);
+
+    for (i = 0; i < SOURCE_BUFFER_SIZE_32b; i++)
+    {
+        errors += destin_32b[i] != CONST_VALUE_32B;
+    }
+
+    PRINTF("Errors:%d\n\r", errors);
+
+    return errors ? EXIT_FAILURE : EXIT_SUCCESS;
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_freertos_blinky/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_freertos_blinky/main.c
index fbb9941f..77c0c461 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_freertos_blinky/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_freertos_blinky/main.c
@@ -116,7 +116,7 @@
 
 /* The rate at which data is sent to the queue.  The 200ms value is converted
 to ticks using the pdMS_TO_TICKS() macro. */
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
 #define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 200 )
 #else
 #define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 3 )
@@ -148,7 +148,7 @@ or 0 to run the more comprehensive test and demo application. */
 #endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
 
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     #define GPIO_LD5_R  15
     #define GPIO_LD5_B  16
 	#define GPIO_LD5_G  17
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_intr/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_intr/main.c
index acad473a..bbdb9bc5 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_intr/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_intr/main.c
@@ -29,7 +29,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
@@ -41,7 +41,7 @@
 #endif
 
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     #define GPIO_TB_OUT 8
     #define GPIO_TB_IN  9
     #define GPIO_INTR  GPIO_INTR_9
@@ -150,6 +150,7 @@ int main(int argc, char *argv[])
         // wait_for_interrupt();
         CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
     }
+    gpio_res = gpio_write(GPIO_TB_OUT, false);
 
     gpio_assign_irq_handler( GPIO_INTR, &handler_2 );
     gpio_intr_flag = 0;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_toggle/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_toggle/main.c
index 9f920281..426de0f1 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_toggle/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_gpio_toggle/main.c
@@ -16,7 +16,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c
index dc8a5c1d..2c7d9a16 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c
@@ -34,7 +34,7 @@
 #include "i2s_structs.h"
 
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
 #define I2S_TEST_BATCH_SIZE    128
 #define I2S_TEST_BATCHES      16
 #define I2S_CLK_DIV           8
@@ -72,7 +72,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
@@ -104,7 +104,7 @@ void handler_irq_i2s(uint32_t id) {
 }
 
 #ifdef USE_DMA
-void dma_intr_handler_trans_done(void)
+void dma_intr_handler_trans_done(uint8_t channel)
 {
     dma_intr_flag = 1;
 }
@@ -173,7 +173,7 @@ void setup()
 int main(int argc, char *argv[]) {
     bool success = true;
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
     for (uint32_t i = 0; i < 0x10000; i++) asm volatile("nop");
 #endif
     PRINTF("I2S DEMO\r\n\r");
@@ -182,7 +182,7 @@ int main(int argc, char *argv[]) {
 
     //PRINTF("Setup done!\r\n\r");
 
-#ifdef TARGET_PYNQ_Z2
+#ifdef TARGET_IS_FPGA
 
 
     for (uint32_t i = 0; i < I2S_WAIT_CYCLES; i++) asm volatile("nop");
@@ -301,22 +301,47 @@ int main(int argc, char *argv[]) {
         PRINTF("B%x\r\n\r", batch);
 
         int32_t* data = audio_data_0;
-        for (int i = 0; i < AUDIO_DATA_NUM; i+=2) {
-            PRINTF("0x%x 0x%x\r\n\r", data[i], data[i+1]);
+        int32_t data_even = 0;
+        int32_t data_odd  = 0;
+        for (int i = 0; i < AUDIO_DATA_NUM; i++) {
+            PRINTF("0x%x\r\n\r", data[i]);
             if (data[i] != 0) {
                 mic_connected = true; // the microphone testbench is connected
-                if (data[i] != 0x8765431) {
-                    PRINTF("ERROR left sample %d (B%d) = 0x%08x != 0x8765431\r\n\r", i, batch, data[i]);
-                    success = false;
+            } else {
+                if(i == 0) {
+                    //check what is the first data to expect, left or right
+                    //the testbench alternatively sends these 2 data, catching which one is first for each BATCH
+                    if ( (data[0] == 0x8765431) || (data[0] == 0xfedcba9) ) {
+                        if (data[0] == 0x8765431) {
+                            data_even = 0x8765431;
+                            data_odd  = 0xfedcba9;
+                        } else {
+                            data_odd  = 0x8765431;
+                            data_even = 0xfedcba9;
+                        }
+                    } else {
+                        PRINTF("ERROR sample %d (B%d) = 0x%08x != 0x8765431 or 0xfedcba9\r\n\r", i, batch, data[0]);
+                        success = false;
+                    }
+
+                } else {
+                    //check whether even or odd
+                    if (i & 0x1) {
+                        //odd
+                        if (data[i] != data_odd) {
+                                PRINTF("ERROR left sample %d (B%d) = 0x%08x != 0x%08x\r\n\r", i, batch, data[i], data_odd);
+                                success = false;
+                        }
+                    }
+                    else {
+                        //even
+                        if (data[i] != data_even) {
+                                PRINTF("ERROR left sample %d (B%d) = 0x%08x != 0x%08x\r\n\r", i, batch, data[i], data_even);
+                                success = false;
+                        }
+                    }
                 }
-            }
-            if (data[i+1] != 0) {
-                mic_connected = true; // the microphone testbench is connected
-                if (data[i+1] != 0xfedcba9) {
-                    PRINTF("ERROR left sample data[%d] = 0x%08x != 0xfedcba9\r\n\r", i+1, batch, data[i+1]);
-                    success = false;
-                }
-            }
+             }
         }
     }
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
index b62fab6a..89cc242b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
@@ -32,7 +32,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
@@ -44,16 +44,16 @@ int32_t to_fifo  [6]   __attribute__ ((aligned (4)))  = { 1, 2, 3, 4, 5, 6 };
 int32_t from_fifo[4]   __attribute__ ((aligned (4)))  = { 0, 0, 0, 0 };
 
 int8_t dma_intr_flag = 0;
-void dma_intr_handler_trans_done()
+void dma_intr_handler_trans_done(uint8_t channel)
 {
   dma_intr_flag = 1;
 }
 
 void protected_wait_for_dma_interrupt(void)
 {
-  while(!dma_is_ready()) {
+  while(!dma_is_ready(0)) {
     CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-    if (!dma_is_ready()) {
+    if (!dma_is_ready(0)) {
         wait_for_interrupt();
     }
     CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c
new file mode 100644
index 00000000..7ffd56bb
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c
@@ -0,0 +1,72 @@
+/*
+   Copyright EPFL contributors.
+  Licensed under the Apache License, Version 2.0, see LICENSE for details.
+  SPDX-License-Identifier: Apache-2.0
+
+  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+
+  Info: Contains randomly generated input activations and the golden result of the im2col algorithm.
+*/
+
+#include "im2colGolden.h"
+
+const uint32_t input_image_nchw[48] = {
+    13932, 24003, 46802, 9895,
+    46807, 33972, 44507, 1507,
+    14638, 51479, 39560, 22725,
+    38212, 35631, 40479, 39503,
+    53705, 5796, 58640, 51585,
+    45069, 32035, 41983, 18828,
+    22247, 54792, 20499, 6640,
+    20565, 25501, 4154, 2925,
+    43660, 10618, 52141, 45092,
+    46500, 63085, 57079, 16974,
+    52033, 46977, 35992, 6933,
+    3158, 21127, 28588, 61815
+};
+
+const uint32_t golden_im2col_nchw[108] = {
+    0, 0, 0, 0, 33972, 1507, 0, 35631, 39503,
+    0, 0, 0, 46807, 44507, 0, 38212, 40479, 0,
+    0, 24003, 9895, 0, 51479, 22725, 0, 0, 0,
+    13932, 46802, 0, 14638, 39560, 0, 0, 0, 0,
+    0, 0, 0, 0, 32035, 18828, 0, 25501, 2925,
+    0, 0, 0, 45069, 41983, 0, 20565, 4154, 0,
+    0, 5796, 51585, 0, 54792, 6640, 0, 0, 0,
+    53705, 58640, 0, 22247, 20499, 0, 0, 0, 0,
+    0, 0, 0, 0, 63085, 16974, 0, 21127, 61815,
+    0, 0, 0, 46500, 57079, 0, 3158, 28588, 0,
+    0, 10618, 45092, 0, 46977, 6933, 0, 0, 0,
+    43660, 52141, 0, 52033, 35992, 0, 0, 0, 0
+};
+
+const uint32_t input_image_nhwc[48] = {
+ 4047, 16986, 10416,
+ 22393, 36967, 57252,
+ 30217, 40720, 42651,
+ 3810, 4754, 56157,
+ 44724, 26083, 1010,
+ 44426, 14005, 35222,
+ 47712, 1887, 65,
+ 37412, 50137, 2236,
+ 7582, 53150, 12696,
+ 24415, 40340, 26558,
+ 22643, 14656, 7085,
+ 804, 32415, 17930,
+ 47706, 3314, 2947,
+ 19673, 37744, 24015,
+ 55137, 1975, 54009,
+ 25888, 50886, 35445
+};
+
+const uint32_t golden_im2col_nhwc[108] = {
+ 0, 0, 0, 4047, 0, 0, 0, 16986, 0, 0, 0, 10416,
+ 0, 0, 22393, 30217, 0, 0, 36967, 40720, 0, 0, 57252, 42651,
+ 0, 0, 3810, 0, 0, 0, 4754, 0, 0, 0, 56157, 0,
+ 0, 44724, 0, 7582, 0, 26083, 0, 53150, 0, 1010, 0, 12696,
+ 44426, 47712, 24415, 22643, 14005, 1887, 40340, 14656, 35222, 65, 26558, 7085,
+ 37412, 0, 804, 0, 50137, 0, 32415, 0, 2236, 0, 17930, 0,
+ 0, 47706, 0, 0, 0, 3314, 0, 0, 0, 2947, 0, 0,
+ 19673, 55137, 0, 0, 37744, 1975, 0, 0, 24015, 54009, 0, 0,
+ 25888, 0, 0, 0, 50886, 0, 0, 0, 35445, 0, 0, 0
+};
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h
new file mode 100644
index 00000000..27083aad
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h
@@ -0,0 +1,31 @@
+/*
+   Copyright EPFL contributors.
+  Licensed under the Apache License, Version 2.0, see LICENSE for details.
+  SPDX-License-Identifier: Apache-2.0
+
+  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+
+  Info: Header file of im2colGolden, contains activations parameters and the prototypes of both input tensors and golden output.
+*/
+
+#ifndef IMAGE_AND_COL_H
+#define IMAGE_AND_COL_H
+
+#include <stdint.h>
+
+// Parameters
+#define IW 4
+#define IH 4
+#define CH 3
+#define FW 2
+#define FH 2
+#define STRIDES 2
+#define PAD 1
+#define BATCH 1
+
+extern const uint32_t input_image_nchw[48];
+extern const uint32_t golden_im2col_nchw[108];
+extern const uint32_t input_image_nhwc[48];
+extern const uint32_t golden_im2col_nhwc[108];
+
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c
new file mode 100644
index 00000000..75d38d74
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c
@@ -0,0 +1,211 @@
+/*
+    Copyright EPFL contributors.
+    Licensed under the Apache License, Version 2.0, see LICENSE for details.
+    SPDX-License-Identifier: Apache-2.0
+
+    Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+
+    Info: im2col_lib.c describes functions used to calculate im2col and verify it using 
+    the golden result in im2colGolden.c.
+
+    Notes: im2col_nchw_int32() and im2col_nhwc_int32() algorithms are inspired from the library SHL, developed by T-HEAD Semi.
+    For reference, check out the following link:
+    https://github.com/T-head-Semi/csi-nn2/blob/main/source/reference/im2col.c
+*/
+
+#include "im2col_lib.h"
+
+int output_data[OH_NCHW*OW_NCHW];
+
+int im2col_nchw_int32()
+{
+    PRINTF("OH: %d, OW: %d\n", OH_NCHW, OW_NCHW);
+
+    int size_transfer = 0;
+    int im_row = 0;
+    int im_col = 0;
+    int w_offset = 0;  // the offset ALONG the IW
+    int h_offset = 0; // the offset ALONG the IH
+    int im_c = 0; // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
+    int col_index = 0;
+    
+    // Iterate over each row of the output matrix.
+    for (int c = 0; c < CH_COL; ++c) {
+        // Calculate offsets within the kernel window.
+        // These are used to move the filter around the input image
+
+        w_offset = c % FW;  
+        h_offset = (c / FW) % FH;
+        im_c = c / (FH * FW); // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
+
+        // Iterate over each BATCH.
+        for (int b = 0; b < BATCH; ++b) {
+            // Iterate over each patch on the IW of the input matrix.
+            for (int h = 0; h < N_PATCHES_H; ++h) {
+                // Iterate over each patch on the heigth in the output matrix.
+                for (int w = 0; w < N_PATCHES_W; ++w) {
+                    // Calculate the row and column indices in the original input image, applying the stride and offset.
+                    im_row = h_offset + h * STRIDES - PAD;
+                    im_col = w_offset + w * STRIDES - PAD;
+
+                    // Calculate the index in the flattened output array where this value should be stored.
+                    col_index = ((c * BATCH + b) * N_PATCHES_H + h) * N_PATCHES_W + w;
+                    
+                    // If the calculated indices are outside the bounds of the input image, set the output to 0 (padding effect).
+                    // Otherwise, fetch the value from the input image and store it in the output array.
+                    if (im_row < 0 || im_col < 0 || im_row >= IH || im_col >= IW) {
+                        output_data[col_index] = 0;
+                    } else {
+                        output_data[col_index] = input_image_nchw[get_index(CH, IH, IW, b, im_c, im_row, im_col)];                        
+                    }
+                }
+            }
+        }
+    }
+
+    // Finished!
+
+    PRINTF("Final output matrix:\n\n");
+
+    #if DEBUG
+    for (int i=0; i<OH; i++)
+    {
+        for (int j=0; j<OW; j++)
+        {
+            PRINTF("%d ", output_data[i*OW + j]);
+        }
+        PRINTF("\n");
+    }
+    #endif
+
+    // Return a 0 to indicate a success
+    return 0;
+}
+
+int im2col_nhwc_int32()
+{
+    PRINTF("OH: %d, OW: %d\n", OH_NHWC, OW_NHWC);
+
+    int size_transfer = 0;
+    int im_row = 0;
+    int im_col = 0;
+    int w_offset = 0;  // the offset ALONG the IW
+    int h_offset = 0; // the offset ALONG the IH
+    int im_c = 0; // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
+    int col_index = 0;
+
+    // Calculate the heigth of the output matrix
+
+    // Iterate over each row of the output matrix.
+    for (int b = 0; b < BATCH; ++b) {
+        // Iterate over each BATCH.
+        for (int h = 0; h < N_PATCHES_H; ++h) {
+            // Iterate over each patch on the IW of the input matrix.
+            for (int w = 0; w < N_PATCHES_W; ++w) {
+                // Iterate over each patch on the heigth in the output matrix.
+                for (int c = 0; c < CH_COL; ++c) {
+                    // Calculate offsets within the kernel window.
+                    // These are used to move the filter around the input image
+
+                    w_offset = c % FW;  
+                    h_offset = (c / FW) % FH;
+                    im_c = c / (FH * FW); // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
+                    
+                    // Calculate the row and column indices in the original input image, applying the stride and offset.
+                    im_row = h_offset + h * STRIDES - PAD;
+                    im_col = w_offset + w * STRIDES - PAD;
+
+                    // Calculate the index in the flattened output array where this value should be stored.
+                    col_index = ((b * N_PATCHES_H + h) * N_PATCHES_W + w) * CH_COL + c; //  ((c * BATCH + b) * N_PATCHES_H + h) * N_PATCHES_W + w;
+                    
+                    // If the calculated indices are outside the bounds of the input image, set the output to 0 (padding effect).
+                    // Otherwise, fetch the value from the input image and store it in the output array.
+                    if (im_row < 0 || im_col < 0 || im_row >= IH || im_col >= IW) {
+                        output_data[col_index] = 0;
+                    } else {
+                        output_data[col_index] = input_image_nhwc[get_index(IH, IW, CH, b, im_row, im_col, im_c)];
+                    }                    
+                }
+            }
+        }
+    }
+
+    PRINTF("Final output matrix:\n\n");
+
+    #if DEBUG
+    for (int i=0; i<OH; i++)
+    {
+        for (int j=0; j<OW; j++)
+        {
+            PRINTF("%d ", output_data[i*OW + j]);
+        }
+        PRINTF("\n");
+    }
+    #endif
+
+    // Return a 0 to indicate a success
+    return 0;
+}
+
+
+int get_index(int dim1, int dim2, int dim3, int index0, int index1, int index2,
+                          int index3)
+{
+    return ((index0 * dim1 + index1) * dim2 + index2) * dim3 + index3;
+}
+
+// Verifies the im2col using golden values generated by "verification_script.py"
+int verify(int format)
+{
+    int errors = 0;
+
+    if (format == 0)
+    {
+        for (int i=0; i<OH_NCHW; i++)
+        {
+            for (int j=0; j<OW_NCHW; j++)
+            {    
+                if (golden_im2col_nchw[i*OW_NCHW + j] != output_data[i*OW_NCHW + j])
+                {
+                    PRINTF("ERROR: Golden: %d, Output: %d, at %d %d\n", golden_im2col_nchw[i*OW_NCHW + j], output_data[i*OW_NCHW + j], i, j);
+                    errors ++;
+                }
+            }
+        }
+    }
+    else
+    {
+        for (int i=0; i<OH_NHWC; i++)
+        {
+            for (int j=0; j<OW_NHWC; j++)
+            {    
+                if (golden_im2col_nhwc[i*OW_NHWC + j] != output_data[i*OW_NHWC + j])
+                {
+                    PRINTF("ERROR: Golden: %d, Output: %d, at %d %d\n", golden_im2col_nhwc[i*OW_NHWC + j], output_data[i*OW_NHWC + j], i, j);
+                    errors ++;
+                }
+            }
+        }
+    }
+    return errors;
+}
+
+void dma_run(dma_trans_t * trans)
+{
+    int res = dma_validate_transaction(trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    res = dma_load_transaction(trans);
+    res = dma_launch(trans);
+
+    while( ! dma_is_ready(0)) {
+        // disable_interrupts
+        // this does not prevent waking up the core as this is controlled by the MIP register
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if ( dma_is_ready(0) == 0 ) {
+            wait_for_interrupt();
+            //from here we wake up even if we did not jump to the ISR
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+    }
+
+    return;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h
new file mode 100644
index 00000000..179f0e07
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h
@@ -0,0 +1,74 @@
+/*
+    Copyright EPFL contributors.
+    Licensed under the Apache License, Version 2.0, see LICENSE for details.
+    SPDX-License-Identifier: Apache-2.0
+
+    Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+    
+    Info: Header file of im2col_lib.c, containing the function prototypes, parameters macros and the configuration of prints and performance analysis.
+*/
+
+#ifndef _IM2COL_
+#define _IM2COL_
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include "im2colGolden.h"
+#include "dma.h"
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+#include "rv_plic.h"
+#include "csr.h"
+
+// By default, printfs are activated for FPGA and for simulation.
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+#define DEBUG 0 // Set to 1 to enable debug prints
+#define TIMING 0 // Set to 1 to enable timing measurements
+
+// Format is defined in im2colGolden.h
+
+#if TARGET_SIM && PRINTF_IN_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+    #define PRINTF_DEB(...) 
+    #define PRINTF_TIM(...)   
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+    #if DEBUG
+        #define PRINTF_DEB(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+    #else
+        #define PRINTF_DEB(...)
+    #endif
+    #if TIMING
+        #define PRINTF_TIM(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+    #else
+        #define PRINTF_TIM(...)
+    #endif
+#else
+    #define PRINTF(...)
+    #define PRINTF_DEB(...)
+    #define PRINTF_TIM(...)
+#endif
+
+// Define the dimensions of the input tensor and the kernel
+
+#define N_PATCHES_H ((IH + (PAD + PAD) - FH)/ STRIDES + 1)
+#define N_PATCHES_W ((IW + (PAD + PAD) - FW)/ STRIDES + 1)
+
+#define CH_COL (CH * FH * FW)
+
+#define OH_NCHW (CH * FH * FW * BATCH)
+#define OW_NCHW (N_PATCHES_H) * (N_PATCHES_W)
+
+#define OW_NHWC (FW * FH * CH * BATCH)
+#define OH_NHWC (N_PATCHES_W) * (N_PATCHES_H)
+
+int im2col_nchw_int32();
+int im2col_nhwc_int32();
+
+int get_index(int dim1, int dim2, int dim3, int index0, int index1, int index2, int index3);
+                
+int verify(int format);
+
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c
new file mode 100644
index 00000000..a22c8bf8
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c
@@ -0,0 +1,81 @@
+/*
+    Copyright EPFL contributors.
+    Licensed under the Apache License, Version 2.0, see LICENSE for details.
+    SPDX-License-Identifier: Apache-2.0
+
+    Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+    
+    Info: Example application of im2col algorithm with configurable format, verification and performance analysis.
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include "x-heep.h"
+#include "im2col_lib.h"
+
+#define NCHW_FORMAT 0
+#define NHWC_FORMAT 1
+
+int main()
+{
+    PRINTF("\nStarting test...\n\n");
+    
+    int errors;
+    unsigned int cycles;
+    
+    #if TIMING
+        CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+        CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif 
+    
+    im2col_nchw_int32(); // Execute the im2col algorithm with NCHW format
+
+    #if TIMING
+        CSR_READ(CSR_REG_MCYCLE, &cycles);
+    #endif
+    
+    errors = verify(NCHW_FORMAT);
+
+    PRINTF("im2col NCHW test executed\n");
+    
+    PRINTF_TIM("Total number of cycles: [%d]\n\n", cycles);
+
+    if (errors != 0)
+    {
+        PRINTF("TEST FAILED: %d errors\n", errors);
+        return 1;
+    } 
+    else
+    {
+        PRINTF("TEST PASSED!\n");
+    }
+
+    #if TIMING
+        CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+        CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    im2col_nhwc_int32(); // Execute the im2col algorithm with NHWC format
+
+    #if TIMING
+        CSR_READ(CSR_REG_MCYCLE, &cycles);
+    #endif
+
+    errors = verify(NHWC_FORMAT);
+
+    PRINTF("im2col NHWC test executed\n");
+    PRINTF_TIM("Total number of cycles: [%d]\n\n", cycles);
+
+    if (errors != 0)
+    {
+        PRINTF("TEST FAILED: %d errors\n", errors);
+        return 1;
+    } 
+    else
+    {
+        PRINTF("TEST PASSED!\n");
+    }
+
+    return 0;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd/main.c
index 80fdb655..7c35229c 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd/main.c
@@ -14,7 +14,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c
index 86f69972..058aadbe 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matadd_interleaved/main.c
@@ -15,7 +15,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matfadd/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matfadd/main.c
index ab2191bd..59dc2bef 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matfadd/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matfadd/main.c
@@ -17,7 +17,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
@@ -28,11 +28,24 @@ uint32_t check_results(float *  C, int N, int M);
 
 float m_c[HEIGHT*WIDTH];
 
-void swap(char *a, char *b)
+void putlong(long i)
 {
-    char temp = *a;
-    *a = *b;
-    *b = temp;
+    char int_str[20]; // An array to store the digits
+    int len = 0; // The length of the string
+    do
+    {
+        // Get the last digit and store it in the array
+        int_str[len] = '0' + i % 10;
+        len++;
+        // Remove the last digit from i
+        i /= 10;
+    } while (i > 0);
+
+    // Print the  reversed string of digits
+    for (int j = len - 1; j >= 0; j--)
+    {
+        putchar(int_str[j]);
+    }
 }
 
 // A function to print a floating point number using putchar
@@ -47,57 +60,68 @@ void putfloat(float x, int p)
         x = -x;
     }
 
-    // Convert the integer part of x into a string of digits
-    long i = (long)x; // Get the integer part
-    char int_str[20]; // An array to store the digits
-    int len = 0; // The length of the string
-    do
-    {
-        // Get the last digit and store it in the array
-        int_str[len] = '0' + i % 10;
-        len++;
-        // Remove the last digit from i
-        i /= 10;
-    } while (i > 0);
+    float f = x - (long)x; // Get the fractional part of x
 
-    // Reverse the string of digits
-    for (int j = 0; j < len / 2; j++)
+    // Get the p most significant digits of the fractional part as the
+    // integer part of f.
+    // Count the number of initial zeros.
+    int initial_zeros = 0;
+    // Check if the fraction will overflow to the integer part when
+    // rounding up (i.e. if the fraction is 0.999...)
+    int fraction_overflow = 1;
+    for (int j = 0; j < p; j++)
     {
-        // Swap the elements at both ends
-        swap(&int_str[j], &int_str[len - 1 - j]);
+        f *= 10;
+        if (f < 1)
+        {
+            // exclude the last digit with round up
+            if (!(j == p - 1 && f >= 0.5f))
+                initial_zeros++;
+        }
+        if (fraction_overflow && (long)f % 10 < 9)
+        {
+            fraction_overflow = 0;
+        }
     }
 
-    // Print the string of digits
-    for (int j = 0; j < len; j++)
+    // Round up if necessary
+    if ((f - (long)f) >= 0.5f)
     {
-        putchar(int_str[j]);
+        // If the rounding causes a digit to overflow in the fractional
+        // part, then we need to print one less zero
+        if (fraction_overflow == 0)
+        {
+            f += 1;
+            if (f >= 10 && initial_zeros > 0)
+            {
+                initial_zeros--;
+            }
+        }
+        // If the overflow is in the integer part, then we need to print
+        // one more digit in the integer part, and none in the fractional
+        else
+        {
+            f = 0;
+            x += 1;
+            initial_zeros = p - 1;
+        }
     }
 
+    // Convert the integer part of x into a string of digits
+    putlong((long)x);
+
     // Print a decimal point
     putchar('.');
 
-    // Convert the fractional part of x into a string of digits
-    float f = x - (long)x; // Get the fractional part
-    char frac_str[20]; // An array to store the digits
-    len = 0; // The length of the string
-    while (p--)
+    // Print the initial zeros
+    while (initial_zeros--)
     {
-        // Get the first digit after the decimal point and store it in the array
-        f = (f - (long)f) * 10;
-        frac_str[len] = '0' + (long)f;
-        len++;
-        // Round up if necessary
-        if (fabs(f - (long)f) >= 0.5f)
-        {
-            frac_str[len - 1]++;
-        }
+        putchar('0');
     }
 
-    // Print the string of digits
-    for (int j = 0; j < len; j++)
-    {
-        putchar(frac_str[j]);
-    }
+    // Convert the fractional part of x into a string of digits
+    if (f > 1)
+        putlong((long)f);
 }
 
 void __attribute__ ((noinline)) printMatrix(float *  C, int N, int M)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c
index aec6ca4e..69d1750b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_matmul/main.c
@@ -14,7 +14,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_pdm2pcm/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_pdm2pcm/main.c
index b4f9c3b3..72551c21 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_pdm2pcm/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_pdm2pcm/main.c
@@ -35,7 +35,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_core/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_core/main.c
deleted file mode 100644
index da7d8448..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_core/main.c
+++ /dev/null
@@ -1,189 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "rv_timer.h"
-#include "power_manager.h"
-#include "soc_ctrl.h"
-#include "rv_plic.h"
-#include "rv_plic_regs.h"
-#include "gpio.h"
-#include "pad_control.h"
-#include "pad_control_regs.h"
-#include "x-heep.h"
-
-
-#ifndef RV_PLIC_IS_INCLUDED
-  #error ( "This app does NOT work as the RV_PLIC peripheral is not included" )
-#endif
-
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-static rv_timer_t timer_0_1;
-static rv_timer_t timer_2_3;
-static const uint64_t kTickFreqHz = 1000 * 1000; // 1 MHz
-static power_manager_t power_manager;
-
-#ifndef TARGET_PYNQ_Z2
-    #define GPIO_TB_OUT 30
-    #define GPIO_TB_IN  31
-    #define GPIO_INTR  GPIO_INTR_31
-#endif
-
-int main(int argc, char *argv[])
-{
-
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-    power_manager_counters_t power_manager_cpu_counters;
-    //counters
-    uint32_t reset_off, reset_on, switch_off, switch_on, iso_off, iso_on;
-
-    // Setup pads
-#ifndef TARGET_PYNQ_Z2
-    pad_control_t pad_control;
-    pad_control.base_addr = mmio_region_from_addr((uintptr_t)PAD_CONTROL_START_ADDRESS);
-    pad_control_set_mux(&pad_control, (ptrdiff_t)(PAD_CONTROL_PAD_MUX_I2C_SCL_REG_OFFSET), 1);
-    pad_control_set_mux(&pad_control, (ptrdiff_t)(PAD_CONTROL_PAD_MUX_I2C_SDA_REG_OFFSET), 1);
-#endif
-
-    // Setup plic
-    plic_Init();
-
-    // Get current Frequency
-    soc_ctrl_t soc_ctrl;
-    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
-    uint32_t freq_hz = soc_ctrl_get_frequency(&soc_ctrl);
-
-    // Setup rv_timer_0_1
-    mmio_region_t timer_0_1_reg = mmio_region_from_addr(RV_TIMER_AO_START_ADDRESS);
-    rv_timer_init(timer_0_1_reg, (rv_timer_config_t){.hart_count = 2, .comparator_count = 1}, &timer_0_1);
-    rv_timer_tick_params_t tick_params;
-    rv_timer_approximate_tick_params(freq_hz, kTickFreqHz, &tick_params);
-
-    // Setup rv_timer_2_3
-    mmio_region_t timer_2_3_reg = mmio_region_from_addr(RV_TIMER_START_ADDRESS);
-    rv_timer_init(timer_2_3_reg, (rv_timer_config_t){.hart_count = 2, .comparator_count = 1}, &timer_2_3);
-
-    // Init cpu_subsystem's counters
-
-    //Turn off: first, isolate the CPU outputs, then I reset it, then I switch it off (reset and switch off order does not really matter)
-    iso_off = 10;
-    reset_off = iso_off + 5;
-    switch_off = reset_off + 5;
-    //Turn on: first, give back power by switching on, then deassert the reset, the unisolate the CPU outputs
-    switch_on = 10;
-    reset_on = switch_on + 20; //give 20 cycles to emulate the turn on time, this number depends on technology and here it is just a random number
-    iso_on = reset_on + 5;
-
-    if (power_gate_counters_init(&power_manager_cpu_counters, reset_off, reset_on, switch_off, switch_on, iso_off, iso_on, 0, 0) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Power-gate and wake-up due to timer_0
-    rv_timer_set_tick_params(&timer_0_1, 0, tick_params);
-    rv_timer_irq_enable(&timer_0_1, 0, 0, kRvTimerEnabled);
-    rv_timer_arm(&timer_0_1, 0, 0, 1024);
-    rv_timer_counter_set_enabled(&timer_0_1, 0, kRvTimerEnabled);
-
-    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-    if (power_gate_core(&power_manager, kTimer_0_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-
-    // Power-gate and wake-up due to timer_1
-    rv_timer_set_tick_params(&timer_0_1, 1, tick_params);
-    rv_timer_irq_enable(&timer_0_1, 1, 0, kRvTimerEnabled);
-    rv_timer_arm(&timer_0_1, 1, 0, 1024);
-    rv_timer_counter_set_enabled(&timer_0_1, 1, kRvTimerEnabled);
-
-    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-    if (power_gate_core(&power_manager, kTimer_1_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-
-    // Power-gate and wake-up due to timer_2
-    rv_timer_set_tick_params(&timer_2_3, 0, tick_params);
-    rv_timer_irq_enable(&timer_2_3, 0, 0, kRvTimerEnabled);
-    rv_timer_arm(&timer_2_3, 0, 0, 1024);
-    rv_timer_counter_set_enabled(&timer_2_3, 0, kRvTimerEnabled);
-
-    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-    if (power_gate_core(&power_manager, kTimer_2_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-
-    // Power-gate and wake-up due to timer_3
-    rv_timer_set_tick_params(&timer_2_3, 1, tick_params);
-    rv_timer_irq_enable(&timer_2_3, 1, 0, kRvTimerEnabled);
-    rv_timer_arm(&timer_2_3, 1, 0, 1024);
-    rv_timer_counter_set_enabled(&timer_2_3, 1, kRvTimerEnabled);
-
-    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-    if (power_gate_core(&power_manager, kTimer_3_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-
-#ifndef TARGET_PYNQ_Z2
-    // Power-gate and wake-up due to plic
-	bool state = false;
-    plic_irq_set_priority(GPIO_INTR_31, 1);
-    plic_irq_set_enabled(GPIO_INTR_31, kPlicToggleEnabled);
-
-    gpio_cfg_t pin2_cfg = {.pin = GPIO_TB_IN, .mode = GpioModeIn,.en_input_sampling = true,
-        .en_intr = true, .intr_type = GpioIntrEdgeRising};
-    gpio_config (pin2_cfg);
-
-    gpio_cfg_t pin1_cfg = {.pin = GPIO_TB_OUT, .mode = GpioModeOutPushPull};
-    gpio_config (pin1_cfg);
-    gpio_write(GPIO_TB_OUT, true);
-
-    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-    if (power_gate_core(&power_manager, kPlic_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-
-    uint32_t intr_num;
-    plic_irq_complete(&intr_num);
-#endif
-
-    /* write something to stdout */
-    PRINTF("Success.\n\r");
-    return EXIT_SUCCESS;
-
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_external/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_external/main.c
deleted file mode 100644
index 1ffc90c4..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_external/main.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "power_manager.h"
-#include "x-heep.h"
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-static power_manager_t power_manager;
-
-int main(int argc, char *argv[])
-{
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-
-    power_manager_counters_t power_manager_external_counters;
-
-    // Init ram block 2's counters
-    if (power_gate_counters_init(&power_manager_external_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Power off external domain
-    if (power_gate_external(&power_manager, 0, kOff_e, &power_manager_external_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Check that the external domain is actually OFF
-    while(!external_power_domain_is_off(&power_manager, 0));
-
-    // Wait some time
-    for (int i=0; i<100; i++) asm volatile("nop");
-
-    // Power on external domain
-    if (power_gate_external(&power_manager, 0, kOn_e, &power_manager_external_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    /* write something to stdout */
-    PRINTF("Success.\n\r");
-    return EXIT_SUCCESS;
-
-    return EXIT_FAILURE;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_periph/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_periph/main.c
deleted file mode 100644
index fb51e1c7..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_periph/main.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "power_manager.h"
-#include "x-heep.h"
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-static power_manager_t power_manager;
-
-int main(int argc, char *argv[])
-{
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-
-    power_manager_counters_t power_manager_periph_counters;
-
-    // Init peripheral_subsystem's counters
-    if (power_gate_counters_init(&power_manager_periph_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Power off peripheral_subsystem domain
-    if (power_gate_periph(&power_manager, kOff_e, &power_manager_periph_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Check that the peripheral_subsystem domain is actually OFF
-    while(!periph_power_domain_is_off(&power_manager));
-
-    // Wait some time
-    for (int i=0; i<100; i++) asm volatile("nop;");
-
-    // Power on peripheral_subsystem domain
-    if (power_gate_periph(&power_manager, kOn_e, &power_manager_periph_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    /* write something to stdout */
-    PRINTF("Success.\n\r");
-    return EXIT_SUCCESS;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_ram_blocks/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_ram_blocks/main.c
deleted file mode 100644
index fe673403..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_gating_ram_blocks/main.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "power_manager.h"
-#include "x-heep.h"
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-static power_manager_t power_manager;
-
-int main(int argc, char *argv[])
-{
-
-#if MEMORY_BANKS > 2
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-
-    power_manager_counters_t power_manager_ram_blocks_counters;
-
-    // Init ram block 2's counters
-    if (power_gate_counters_init(&power_manager_ram_blocks_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Power off ram block 2 domain
-    if (power_gate_ram_block(&power_manager, 2, kOff_e, &power_manager_ram_blocks_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Check that the ram block 2 domain is actually OFF
-    while(!ram_block_power_domain_is_off(&power_manager, 2));
-
-    // Wait some time
-    for (int i=0; i<100; i++) asm volatile("nop");
-
-    // Power on ram block 2 domain
-    if (power_gate_ram_block(&power_manager, 2, kOn_e, &power_manager_ram_blocks_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    /* write something to stdout */
-    PRINTF("Success.\n\r");
-    return EXIT_SUCCESS;
-
-#else
-    #pragma message ( "this application can run only when MEMORY_BANKS > 2" )
-    return EXIT_SUCCESS;
-#endif
-
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c
new file mode 100644
index 00000000..4f025e1e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c
@@ -0,0 +1,471 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "csr.h"
+#include "hart.h"
+#include "handler.h"
+#include "core_v_mini_mcu.h"
+#include "rv_timer.h"
+#include "power_manager.h"
+#include "soc_ctrl.h"
+#include "rv_plic.h"
+#include "rv_plic_regs.h"
+#include "gpio.h"
+#include "pad_control.h"
+#include "pad_control_regs.h"
+#include "x-heep.h"
+#include "dma.h"
+
+#ifndef RV_PLIC_IS_INCLUDED
+  #error ( "This app does NOT work as the RV_PLIC peripheral is not included" )
+#endif
+
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+static rv_timer_t timer_0_1;
+static rv_timer_t timer_2_3;
+static const uint64_t kTickFreqHz = 1000 * 1000; // 1 MHz
+static power_manager_t power_manager;
+
+#ifndef TARGET_IS_FPGA
+    #define GPIO_TB_OUT 30
+    #define GPIO_TB_IN  31
+    #define GPIO_INTR  GPIO_INTR_31
+#endif
+
+#define TEST_WORD
+//this data has to be big to allow the CPU to power gate
+#define TEST_DATA_SIZE 500
+
+// Source and destination addresses have to be aligned on a 4 bytes address
+uint32_t test_data_4B[TEST_DATA_SIZE] __attribute__ ((aligned (4))) = { 0 };
+uint32_t copied_data_4B[TEST_DATA_SIZE] __attribute__ ((aligned (4))) = { 0 };
+
+uint8_t gpio_intr_flag = 0;
+
+void gpio_handler_in()
+{
+    gpio_intr_flag = 1;
+}
+
+int main(int argc, char *argv[])
+{
+
+    // Setup power_manager
+    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
+    power_manager.base_addr = power_manager_reg;
+    power_manager_counters_t power_manager_counters;
+    //counters
+    uint32_t reset_off, reset_on, switch_off, switch_on, iso_off, iso_on;
+
+    // Setup pads
+#ifndef TARGET_IS_FPGA
+    pad_control_t pad_control;
+    pad_control.base_addr = mmio_region_from_addr((uintptr_t)PAD_CONTROL_START_ADDRESS);
+    pad_control_set_mux(&pad_control, (ptrdiff_t)(PAD_CONTROL_PAD_MUX_I2C_SCL_REG_OFFSET), 1);
+    pad_control_set_mux(&pad_control, (ptrdiff_t)(PAD_CONTROL_PAD_MUX_I2C_SDA_REG_OFFSET), 1);
+#endif
+
+    // Setup plic
+    plic_Init();
+
+    // Get current Frequency
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz = soc_ctrl_get_frequency(&soc_ctrl);
+
+    // Setup rv_timer_0_1
+    mmio_region_t timer_0_1_reg = mmio_region_from_addr(RV_TIMER_AO_START_ADDRESS);
+    rv_timer_init(timer_0_1_reg, (rv_timer_config_t){.hart_count = 2, .comparator_count = 1}, &timer_0_1);
+    rv_timer_tick_params_t tick_params;
+    rv_timer_approximate_tick_params(freq_hz, kTickFreqHz, &tick_params);
+
+    // Setup rv_timer_2_3
+    mmio_region_t timer_2_3_reg = mmio_region_from_addr(RV_TIMER_START_ADDRESS);
+    rv_timer_init(timer_2_3_reg, (rv_timer_config_t){.hart_count = 2, .comparator_count = 1}, &timer_2_3);
+
+    // Init cpu_subsystem's counters
+
+    //Turn off: first, isolate the CPU outputs, then I reset it, then I switch it off (reset and switch off order does not really matter)
+    iso_off = 10;
+    reset_off = iso_off + 5;
+    switch_off = reset_off + 5;
+    //Turn on: first, give back power by switching on, then deassert the reset, the unisolate the CPU outputs
+    switch_on = 10;
+    reset_on = switch_on + 20; //give 20 cycles to emulate the turn on time, this number depends on technology and here it is just a random number
+    iso_on = reset_on + 5;
+
+    if (power_gate_counters_init(&power_manager_counters, reset_off, reset_on, switch_off, switch_on, iso_off, iso_on, 0, 0) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
+        return EXIT_FAILURE;
+    }
+
+    // Power-gate and wake-up due to timer_0
+    rv_timer_set_tick_params(&timer_0_1, 0, tick_params);
+    rv_timer_irq_enable(&timer_0_1, 0, 0, kRvTimerEnabled);
+    rv_timer_arm(&timer_0_1, 0, 0, 1024);
+    rv_timer_counter_set_enabled(&timer_0_1, 0, kRvTimerEnabled);
+
+    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+    if (power_gate_core(&power_manager, kTimer_0_pm_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+    // Power-gate and wake-up due to timer_1
+    rv_timer_set_tick_params(&timer_0_1, 1, tick_params);
+    rv_timer_irq_enable(&timer_0_1, 1, 0, kRvTimerEnabled);
+    rv_timer_arm(&timer_0_1, 1, 0, 1024);
+    rv_timer_counter_set_enabled(&timer_0_1, 1, kRvTimerEnabled);
+
+    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+    if (power_gate_core(&power_manager, kTimer_1_pm_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+    // Power-gate and wake-up due to timer_2
+    rv_timer_set_tick_params(&timer_2_3, 0, tick_params);
+    rv_timer_irq_enable(&timer_2_3, 0, 0, kRvTimerEnabled);
+    rv_timer_arm(&timer_2_3, 0, 0, 1024);
+    rv_timer_counter_set_enabled(&timer_2_3, 0, kRvTimerEnabled);
+
+    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+    if (power_gate_core(&power_manager, kTimer_2_pm_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+    // Power-gate and wake-up due to timer_3
+    rv_timer_set_tick_params(&timer_2_3, 1, tick_params);
+    rv_timer_irq_enable(&timer_2_3, 1, 0, kRvTimerEnabled);
+    rv_timer_arm(&timer_2_3, 1, 0, 1024);
+    rv_timer_counter_set_enabled(&timer_2_3, 1, kRvTimerEnabled);
+
+    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+    if (power_gate_core(&power_manager, kTimer_3_pm_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+    // Power-gate and wake-up due to DMA
+
+    //prepare data
+    for(int i=0; i<TEST_DATA_SIZE;i++){
+        test_data_4B[i] = i;
+    }
+
+    dma_init(NULL);
+    dma_config_flags_t res;
+    dma_target_t tgt_src;
+    dma_target_t tgt_dst;
+    dma_target_t tgt_addr = {
+        .ptr = NULL,
+        .inc_du = 1,
+        .size_du = 0,
+        .trig = DMA_TRIG_MEMORY,
+    };
+    dma_trans_t trans;
+
+    // Initialize the DMA for the next tests
+    tgt_src.ptr = (uint8_t *)test_data_4B;
+    tgt_src.inc_du = 1;
+    tgt_src.size_du = TEST_DATA_SIZE;
+    tgt_src.trig = DMA_TRIG_MEMORY;
+    tgt_src.type = DMA_DATA_TYPE_WORD;
+    tgt_src.env = NULL;
+    tgt_src.inc_d2_du = 0;
+
+    tgt_dst.ptr = (uint8_t *)copied_data_4B;
+    tgt_dst.inc_du = 1;
+    tgt_dst.size_du = TEST_DATA_SIZE;
+    tgt_dst.trig = DMA_TRIG_MEMORY;
+    tgt_dst.type = DMA_DATA_TYPE_WORD;
+    tgt_dst.env = NULL;
+    tgt_dst.inc_d2_du = 0;
+
+    trans.src = &tgt_src;
+    trans.dst = &tgt_dst;
+    trans.src_addr = &tgt_addr;
+    trans.src_type = DMA_DATA_TYPE_WORD;
+    trans.dst_type = DMA_DATA_TYPE_WORD;
+    trans.mode = DMA_TRANS_MODE_SINGLE;
+    trans.win_du = 0;
+    trans.sign_ext = 0;
+    trans.end = DMA_TRANS_END_INTR;
+    trans.dim = DMA_DIM_CONF_1D;
+    trans.dim_inv = 0;
+    trans.channel = 0;
+
+    trans.pad_top_du = 0;
+    trans.pad_bottom_du = 0;
+    trans.pad_left_du = 0;
+    trans.pad_right_du = 0;
+
+    trans.flags = 0x0;
+    res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    res = dma_load_transaction(&trans);
+    res = dma_launch(&trans);
+
+    while (!dma_is_ready(0))
+    {
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if (dma_is_ready(0) == 0)
+        {
+                if (power_gate_core(&power_manager, kDma_pm_e, &power_manager_counters) != kPowerManagerOk_e)
+                {
+                    PRINTF("Error: power manager fail.\n\r");
+                    return EXIT_FAILURE;
+                }
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+    }
+
+    for(int i=0; i<TEST_DATA_SIZE; i++) {
+        if (copied_data_4B[i] != test_data_4B[i]) {
+            PRINTF("ERROR COPY [%d]: %08x != %08x : %04x != %04x\n", i, &copied_data_4B[i], &test_data_4B[i], copied_data_4B[i], test_data_4B[i]);
+            return -1;
+        }
+    }
+
+#ifndef TARGET_IS_FPGA
+    // Power-gate and wake-up due to plic GPIO
+
+    gpio_assign_irq_handler( GPIO_INTR_31, &gpio_handler_in );
+
+    bool state = false;
+    plic_irq_set_priority(GPIO_INTR_31, 1);
+    plic_irq_set_enabled(GPIO_INTR_31, kPlicToggleEnabled);
+
+    gpio_cfg_t pin2_cfg = {.pin = GPIO_TB_IN, .mode = GpioModeIn,.en_input_sampling = true,
+        .en_intr = true, .intr_type = GpioIntrEdgeRising};
+    gpio_config (pin2_cfg);
+
+    gpio_cfg_t pin1_cfg = {.pin = GPIO_TB_OUT, .mode = GpioModeOutPushPull};
+    gpio_config (pin1_cfg);
+    gpio_write(GPIO_TB_OUT, true);
+
+    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+    if (power_gate_core(&power_manager, kPlic_pm_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+    uint32_t intr_num;
+    plic_irq_complete(&intr_num);
+
+    if(gpio_intr_flag == 0){
+        PRINTF("Error: GPIO interrupt not detected\n\r");
+        return EXIT_FAILURE;
+    }
+
+#endif
+
+    /* write something to stdout */
+    PRINTF("CPU Power Gating Test Successefull\n\r");
+
+    // ------------ PERIPHERAL SUBSYSTEM  ------------
+    PRINTF("Testing Peripheral Subsystem...\n\r");
+
+    // ------------ clock gating ------------
+    mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(POWER_MANAGER_PERIPH_CLK_GATE_REG_OFFSET), 0x1);
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop;");
+    // Enabling the peripheral subsystem
+    mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(POWER_MANAGER_PERIPH_CLK_GATE_REG_OFFSET), 0x0);
+
+    PRINTF("Peripheral Clock Gating Test Successefull\n\r");
+
+    // ------------ power gating ------------
+    if (power_gate_counters_init(&power_manager_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
+        return EXIT_FAILURE;
+    }
+
+    // Power off peripheral_subsystem domain
+    if (power_gate_periph(&power_manager, kOff_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+
+    // Check that the peripheral_subsystem domain is actually OFF
+    while(!periph_power_domain_is_off(&power_manager));
+
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop;");
+
+    // Power on peripheral_subsystem domain
+    if (power_gate_periph(&power_manager, kOn_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("Peripheral Power Gating Test Successefull\n\r");
+
+#if MEMORY_BANKS > 2
+    // ------------ MEMORY SUBSYSTEM  ------------
+    PRINTF("Testing Memory Subsystem...\n\r");
+
+    // ------------ clock gating ------------
+    // do not clock gate instruction and data memory (usually first 2 banks)
+    for(uint32_t i = 2; i < MEMORY_BANKS; ++i)
+        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_ram_map[i].clk_gate), 0x1);
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop;");
+    // Enabling ram-banks
+    for(uint32_t i = 2; i < MEMORY_BANKS; ++i)
+        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_ram_map[i].clk_gate), 0x0);
+
+    PRINTF("Memory Clock Gating Test Successefull\n\r");
+
+    // ------------ power gating ------------
+    if (power_gate_counters_init(&power_manager_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
+        return EXIT_FAILURE;
+    }
+    // Power off ram block 2 domain
+    if (power_gate_ram_block(&power_manager, 2, kOff_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    // Check that the ram block 2 domain is actually OFF
+    while(!ram_block_power_domain_is_off(&power_manager, 2));
+
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop");
+    // Power on ram block 2 domain
+    if (power_gate_ram_block(&power_manager, 2, kOn_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("Memory Power Gating Test Successefull\n\r");
+
+    // ------------ set retentive ------------
+    if (power_gate_counters_init(&power_manager_counters, 0, 0, 0, 0, 0, 0, 30, 30) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
+        return EXIT_FAILURE;
+    }
+    // Set retention mode on for ram block 2 domain
+    if (power_gate_ram_block(&power_manager, 2, kRetOn_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop");
+    // Set retention mode off for ram block 2 domain
+    if (power_gate_ram_block(&power_manager, 2, kRetOff_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("Memory Set Retentive Test Successefull\n\r");
+
+
+#else
+    #pragma message ( "the memory test can only run if MEMORY_BANKS > 2" )
+#endif
+
+#if EXTERNAL_DOMAINS > 0
+
+    // ------------ External SUBSYSTEM  ------------
+    PRINTF("Testing External Domain Subsystems...\n\r");
+
+    // ------------ clock gating ------------
+    for(uint32_t i = 0; i < EXTERNAL_DOMAINS; ++i)
+        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_external_map[i].clk_gate), 0x1);
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop;");
+    // Enabling external subsystems
+    for(uint32_t i = 0; i < EXTERNAL_DOMAINS; ++i)
+        mmio_region_write32(power_manager.base_addr, (ptrdiff_t)(power_manager_external_map[i].clk_gate), 0x0);
+
+    PRINTF("External Clock Gating Test Successefull\n\r");
+
+    // ------------ power gating domain 0 ------------
+    if (power_gate_counters_init(&power_manager_counters, 30, 30, 30, 30, 30, 30, 0, 0) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
+        return EXIT_FAILURE;
+    }
+    // Power off external domain
+    if (power_gate_external(&power_manager, 0, kOff_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    // Check that the external domain is actually OFF
+    while(!external_power_domain_is_off(&power_manager, 0));
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop");
+    // Power on external domain
+    if (power_gate_external(&power_manager, 0, kOn_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("External Power Gating Test Successefull\n\r");
+
+    // ------------ set retentive domain 0------------
+   if (power_gate_counters_init(&power_manager_counters, 0, 0, 0, 0, 0, 0, 30, 30) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
+        return EXIT_FAILURE;
+    }
+    // Set retention mode on for external domain block 0
+    if (power_gate_external(&power_manager, 0, kRetOn_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+    // Wait some time
+    for (int i=0; i<100; i++) asm volatile("nop");
+    // Set retention mode off for external domain block 0
+    if (power_gate_external(&power_manager, 0, kRetOff_e, &power_manager_counters) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail.\n\r");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("External Set Retentive Test Successefull\n\r");
+#else
+    #pragma message ( "the external domain test can only run if EXTERNAL_DOMAINS > 0" )
+#endif
+    return EXIT_SUCCESS;
+
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_sdk_spi_flash/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_sdk_spi_flash/main.c
new file mode 100644
index 00000000..226a2a02
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_sdk_spi_flash/main.c
@@ -0,0 +1,353 @@
+/**
+ * @file main.c
+ * @brief Simple spi communication example using SDK
+ *
+ * Simple example that reads a sector (4096 Bytes) from flash, overwrites the
+ * specified location range with new data, erases that sector from flash, writes
+ * the modified sector back to the flash and finally reads the modified location
+ * range directly from the flash to verify the operation has succeeded.
+ * 
+ * The flash device being used is the w25q128jw
+ *
+*/
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "x-heep.h"
+#include "core_v_mini_mcu.h"
+#include "spi_sdk.h"
+
+#include "fast_intr_ctrl.h"
+#include "csr.h"
+#include "csr_registers.h"
+
+/* By default, PRINTFs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif TARGET_IS_FPGA && PRINTF_IN_FPGA
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+#ifdef TARGET_IS_FPGA
+    #define USE_SPI_FLASH
+#endif
+
+// =========================== VARS & DEFS ==================================
+
+// 1 to print the modified data at the end of program 0 to disable
+#define PRINT_DATA 1
+
+// Flash w25q128jw SPI commands
+#define FC_WE      0x06 /** Write Enable */
+#define FC_RD      0x03 /** Read Data */
+#define FC_PP      0x02 /** Page Program */
+#define FC_SE      0x20 /** Sector Erase 4kb */
+#define FC_RSR1    0x05 /** Read Status Register 1 */
+
+#define READ_WRITE_LEN 16                           // Amount words to read/write
+#define START_ADDRESS  ((FLASH_MEM_SIZE / 2) + 256) // Flash address where read/write
+#define SECT_ADDRESS   (START_ADDRESS & 0xfffff000) // Start sector address
+#define SECT_LEN       4096             // Length bytes of a sector
+#define PAGE_LEN       256              // Length bytes of a page
+#define FLASH_MAX_FREQ (133*1000*1000)  // Device max spi frequency
+#define FIC_FLASH_MEIE 21               // SPI Flash fast interrupt bit enable
+#define CSR_INTR_EN    0x08             // CPU Global interrupt enable
+
+// Hold sector data
+uint8_t sect_data[SECT_LEN];
+
+// Data to write
+uint32_t flash_original_1024B[PAGE_LEN] = {
+    0x76543211, 0xfedcba99, 0x579a6f91, 0x657d5bef, 0x758ee420, 0x01234568, 0xfedbca97, 0x89abde00,
+    0x76543212, 0xfedcba9a, 0x579a6f92, 0x657d5bf0, 0x758ee421, 0x01234569, 0xfedbca98, 0x89abde01,
+    0x76543213, 0xfedcba9b, 0x579a6f93, 0x657d5bf1, 0x758ee422, 0x0123456a, 0xfedbca99, 0x89abde02,
+    0x76543214, 0xfedcba9c, 0x579a6f94, 0x657d5bf2, 0x758ee423, 0x0123456b, 0xfedbca9a, 0x89abde03,
+    0x76543215, 0xfedcba9d, 0x579a6f95, 0x657d5bf3, 0x758ee424, 0x0123456c, 0xfedbca9b, 0x89abde04,
+    0x76543216, 0xfedcba9e, 0x579a6f96, 0x657d5bf4, 0x758ee425, 0x0123456d, 0xfedbca9c, 0x89abde05,
+    0x76543217, 0xfedcba9f, 0x579a6f97, 0x657d5bf5, 0x758ee426, 0x0123456e, 0xfedbca9d, 0x89abde06,
+    0x76543218, 0xfedcbaa0, 0x579a6f98, 0x657d5bf6, 0x758ee427, 0x0123456f, 0xfedbca9e, 0x89abde07,
+    0x76543219, 0xfedcbaa1, 0x579a6f99, 0x657d5bf7, 0x758ee428, 0x01234570, 0xfedbca9f, 0x89abde08,
+    0x7654321a, 0xfedcbaa2, 0x579a6f9a, 0x657d5bf8, 0x758ee429, 0x01234571, 0xfedbcaa0, 0x89abde09,
+    0x7654321b, 0xfedcbaa3, 0x579a6f9b, 0x657d5bf9, 0x758ee42a, 0x01234572, 0xfedbcaa1, 0x89abde0a,
+    0x7654321c, 0xfedcbaa4, 0x579a6f9c, 0x657d5bfa, 0x758ee42b, 0x01234573, 0xfedbcaa2, 0x89abde0b,
+    0x7654321d, 0xfedcbaa5, 0x579a6f9d, 0x657d5bfb, 0x758ee42c, 0x01234574, 0xfedbcaa3, 0x89abde0c,
+    0x7654321e, 0xfedcbaa6, 0x579a6f9e, 0x657d5bfc, 0x758ee42d, 0x01234575, 0xfedbcaa4, 0x89abde0d,
+    0x7654321f, 0xfedcbaa7, 0x579a6f9f, 0x657d5bfd, 0x758ee42e, 0x01234576, 0xfedbcaa5, 0x89abde0e,
+    0x76543220, 0xfedcbaa8, 0x579a6fa0, 0x657d5bfe, 0x758ee42f, 0x01234577, 0xfedbcaa6, 0x89abde0f,
+    0x76543221, 0xfedcbaa9, 0x579a6fa1, 0x657d5bff, 0x758ee430, 0x01234578, 0xfadbcaa7, 0x89abde10,
+    0x76543222, 0xfedcbaaa, 0x579a6fa2, 0x657d5c00, 0x758ee431, 0x01234579, 0xfadbcaa8, 0x89abde11,
+    0x76543223, 0xfedcbaab, 0x579a6fa3, 0x657d5c01, 0x758ee432, 0x0123457a, 0xfadbcaa9, 0x89abde12,
+    0x76543224, 0xfedcbaac, 0x579a6fa4, 0x657d5c02, 0x758ee433, 0x0123457b, 0xfadbcaaa, 0x89abde13,
+    0x76543225, 0xfedcbaad, 0x579a6fa5, 0x657d5c03, 0x758ee434, 0x0123457c, 0xfadbcaab, 0x89abde14,
+    0x76543226, 0xfedcbaae, 0x579a6fa6, 0x657d5c04, 0x758ee435, 0x0123457d, 0xfadbcaac, 0x89abde15,
+    0x76543227, 0xfedcbaaf, 0x579a6fa7, 0x657d5c05, 0x758ee436, 0x0123457e, 0xfadbcaad, 0x89abde16,
+    0x76543228, 0xfedcbab0, 0x579a6fa8, 0x657d5c06, 0x758ee437, 0x0123457f, 0xfadbcaae, 0x89abde17,
+    0x76543220, 0xfedcbaa8, 0x579a6fa0, 0x657d5bfe, 0x758ee42f, 0x01234577, 0xfedbcaa6, 0x89abde0f,
+    0x76543221, 0xfedcbaa9, 0x579a6fa1, 0x657d5bff, 0x758ee430, 0x01234578, 0xfadbcaa7, 0x89abde10,
+    0x76543222, 0xfedcbaaa, 0x579a6fa2, 0x657d5c00, 0x758ee431, 0x01234579, 0xfadbcaa8, 0x89abde11,
+    0x76543223, 0xfedcbaab, 0x579a6fa3, 0x657d5c01, 0x758ee432, 0x0123457a, 0xfadbcaa9, 0x89abde12,
+    0x76543224, 0xfedcbaac, 0x579a6fa4, 0x657d5c02, 0x758ee433, 0x0123457b, 0xfadbcaaa, 0x89abde13,
+    0x76543225, 0xfedcbaad, 0x579a6fa5, 0x657d5c03, 0x758ee434, 0x0123457c, 0xfadbcaab, 0x89abde14,
+    0x76543226, 0xfedcbaae, 0x579a6fa6, 0x657d5c04, 0x758ee435, 0x0123457d, 0xfadbcaac, 0x89abde15,
+    0x76543227, 0xfedcbaaf, 0x579a6fa7, 0x657d5c05, 0x758ee436, 0x0123457e, 0xfadbcaad, 0x89abde16,
+    0x76543228, 0xfedcbab0, 0x579a6fa8, 0x657d5c06, 0x758ee437, 0x0123457f, 0xfadbcaae, 0x89abde17
+};
+
+// ====================== PROTOTYPES ======================
+
+bool flash_read(spi_t* spi, uint32_t addr, uint32_t* dest_buff, uint32_t len);
+bool flash_read_non_blocking(spi_t* spi, uint32_t addr, uint32_t* dest_buff, uint32_t len);
+bool flash_write_enable(spi_t* spi);
+bool flash_erase_sector(spi_t* spi, uint32_t addr);
+bool flash_write_sector(spi_t* spi, uint32_t addr, uint32_t* src_buff);
+void flash_wait(spi_t* spi);
+
+void done_cb(const uint32_t* txbuff, uint32_t txlen, uint32_t* rxbuff, uint32_t rxlen);
+void rxwm_cb(const uint32_t* txbuff, uint32_t txlen, uint32_t* rxbuff, uint32_t rxlen);
+
+// ========================= MAIN =========================
+
+int main(int argc, char *argv[]) {
+    // Create our slave (flash device) with its specifications
+    spi_slave_t slave = SPI_SLAVE(0, FLASH_MAX_FREQ);
+
+    // Initialize the spi device that is CONNECTED to the flash with our slave
+    #ifdef USE_SPI_FLASH
+    spi_t spi = spi_init(SPI_IDX_FLASH, slave);
+    #else
+    spi_t spi = spi_init(SPI_IDX_HOST, slave);
+    #endif
+
+    // Check if initialization succeeded
+    if (!spi.init) {
+        PRINTF("\nFailed to initialize spi\n");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("\nSPI initialized\n");
+
+    // Enable global interrupt for machine-level interrupts
+    CSR_SET_BITS(CSR_REG_MSTATUS, CSR_INTR_EN);
+    // Set mie.MEIE bit to one to enable machine-level fast spi_flash interrupt
+    const uint32_t mask = 1 << FIC_FLASH_MEIE;
+    CSR_SET_BITS(CSR_REG_MIE, mask);
+
+    // Buffer to hold data for final comparison
+    uint32_t rxbuffer[READ_WRITE_LEN] = {0};
+
+    // Read whole sector containing the desired START_ADDRESS
+    if (!flash_read_non_blocking(&spi, SECT_ADDRESS, sect_data, SECT_LEN)) 
+        return EXIT_FAILURE;
+
+    // No need to erase if on simulation
+    #ifdef USE_SPI_FLASH
+    // Erase that sector
+    if (!flash_erase_sector(&spi, START_ADDRESS)) return EXIT_FAILURE;
+    #endif
+
+    // Copy the data to overwrite
+    memcpy(&sect_data[START_ADDRESS - SECT_ADDRESS], flash_original_1024B, READ_WRITE_LEN * 4);
+    // Write the whole sector with the new data back to flash
+    if (!flash_write_sector(&spi, START_ADDRESS, sect_data)) return EXIT_FAILURE;
+    // Read the modified part
+    if (!flash_read(&spi, START_ADDRESS, rxbuffer, 4*READ_WRITE_LEN)) return EXIT_FAILURE;
+
+    // Compare the modified part with the data used to modify
+    if (memcmp(rxbuffer, flash_original_1024B, 4*READ_WRITE_LEN))
+         PRINTF("\nMISMATCH\n\n");
+    else PRINTF("\nSUCCESS\n\n");
+
+    // If wanted display the data
+    #if PRINT_DATA
+    PRINTF(" address     original  on flash\n");
+    PRINTF("-------------------------------\n");
+    for (int i = 0; i < READ_WRITE_LEN; i++)
+    {
+        PRINTF("0x%08X:  %08X  %08X\n", START_ADDRESS+4*i, flash_original_1024B[i], rxbuffer[i]);
+    }
+    #endif
+
+    PRINTF("\n==================================================\n\n");
+    
+
+    return EXIT_SUCCESS;
+}
+
+// ========================= FUNCTIONS =========================
+
+bool flash_read(spi_t* spi, uint32_t addr, uint32_t* dest_buff, uint32_t len) {
+    // Transaction segments
+    spi_segment_t segments[2] = { SPI_SEG_TX(4), SPI_SEG_RX(len) };
+
+    // TX SPI command to send to flash for read
+    // Flash uses Big Endian, CPU Little Endian, hence swap bytes
+    uint32_t read_byte_cmd = ((bitfield_byteswap32(addr & 0x00ffffff)) | FC_RD);
+
+    PRINTF("Blocking Reading %4i Bytes at 0x%08X\n", len, addr);
+
+    // Start transaction
+    spi_codes_e error = spi_execute(spi, segments, 2, &read_byte_cmd, dest_buff);
+    if (error) {
+        PRINTF("FAILED! Error Code: %i\n", error);
+        return false;
+    }
+    return true;
+}
+
+bool flash_read_non_blocking(spi_t* spi, uint32_t addr, uint32_t* dest_buff, uint32_t len) {
+    // Transaction segments
+    spi_segment_t segments[2] = { SPI_SEG_TX(4), SPI_SEG_RX(len) };
+
+    // TX SPI command to send to flash for read
+    // Flash uses Big Endian, CPU Little Endian, hence swap bytes
+    uint32_t read_byte_cmd = ((bitfield_byteswap32(addr & 0x00ffffff)) | FC_RD);
+
+    PRINTF("\nNon-Blocking Reading %4i Bytes at 0x%08X\n", len, addr);
+    PRINTF("Counter set to 0.\n");
+
+    uint32_t counter = 0;
+    spi_callbacks_t callbacks = {
+        .done_cb  = &done_cb,
+        .error_cb = NULL,//&done_cb,
+        .rxwm_cb  = &rxwm_cb,
+        .txwm_cb  = NULL
+    };
+
+    // Save previous watermark to reset it after transaction completes
+    uint8_t watermark;
+    spi_get_rxwm(spi, &watermark);
+    spi_set_rxwm(spi, 12); // Arbitrarily chosen watermark
+
+    // Start transaction
+    spi_codes_e error = spi_execute_nb(spi, segments, 2, &read_byte_cmd, dest_buff, callbacks);
+    if (error) {
+        PRINTF("FAILED! Error Code: %i\n", error);
+        return false;
+    }
+
+    while(spi_get_state(spi) == SPI_STATE_BUSY) counter++;
+    // Check if the communication ended because of an error
+    if (spi_get_state(spi) == SPI_STATE_ERROR) {
+        PRINTF("FAILED! Hardware ERROR !\n");
+        return false;
+    }
+
+    // Reset the watermark to its previous value
+    spi_set_rxwm(spi, watermark);
+
+    PRINTF("Counter reached %4i. => Non Blocking\n\n", counter);
+
+    return true;
+}
+
+bool flash_erase_sector(spi_t* spi, uint32_t addr) {
+    // Sector start address
+    const uint32_t sect_start = addr & 0xfffff000;
+    // Sector erase command
+    // Flash uses Big Endian, CPU Little Endian, hence swap bytes
+    const uint32_t cmd = ((bitfield_byteswap32(sect_start & 0x00ffffff)) | FC_SE);
+
+    PRINTF("Blocking Erasing 4096 Bytes at 0x%08X\n", sect_start);
+
+    // Enable write before erase
+    if (!flash_write_enable(spi)) return false;
+
+    // Start TX Only transaction
+    spi_codes_e error = spi_transmit(spi, &cmd, 4);
+    if (error) {
+        PRINTF("FAILED! Error Code: %i\n", error);
+        return false;
+    }
+
+    // Wait flash finished processing
+    flash_wait(spi);
+
+    return true;
+}
+
+bool flash_write_sector(spi_t* spi, uint32_t addr, uint32_t* src_buff) {
+    // Sector start address
+    uint32_t sect = addr & 0xfffff000;
+    // Current page (256 bytes) address (can't write more than one page at a time...)
+    uint32_t curr_addr = sect;
+
+    for (int i = 0; i < SECT_LEN / PAGE_LEN; i++)
+    {
+        // Our TX Buffer
+        uint32_t wbuff[PAGE_LEN/4 + 1] = {0};
+        // Our segments for the SPI transaction
+        spi_segment_t segments[2] = { SPI_SEG_TX(4), SPI_SEG_TX(PAGE_LEN) };
+
+        // Flash uses Big Endian, CPU Little Endian, hence swap bytes
+        wbuff[0] = ((bitfield_byteswap32(curr_addr & 0x00ffffff)) | FC_PP);
+        memcpy(&wbuff[1], &src_buff[i * (PAGE_LEN/4)], PAGE_LEN);
+
+        if (!flash_write_enable(spi)) return false;
+
+        // Start transaction
+        // Note that since segments are only TX we could have used spi_transmit
+        // instead of spi_execute, but both work perfectly fine
+        spi_codes_e error = spi_execute(spi, segments, 2, wbuff, NULL);
+        if (error) {
+            PRINTF("FAILED! Error Code: %i\n", error);
+            return false;
+        }
+        curr_addr += PAGE_LEN;
+
+        PRINTF("\rBlocking Written %4i/4096 Bytes at 0x%08X", (i+1) * PAGE_LEN, sect);
+
+        // Wait flash finished processing
+        flash_wait(spi);
+    }
+
+    PRINTF("\n");
+    
+    return true;
+}
+
+bool flash_write_enable(spi_t* spi) {
+    // SPI Flash command
+    const uint32_t cmd = FC_WE;
+    // Start TX Only transaction
+    spi_codes_e error = spi_transmit(spi, &cmd, 1);
+    if (error) {
+        PRINTF("FAILED! Error Code: %i\n", error);
+        return false;
+    }
+    return true;
+}
+
+void flash_wait(spi_t* spi) {
+    // Response buffer
+    uint32_t resp;
+    // SPI Flash command
+    uint32_t cmd = FC_RSR1;
+    // Here we have to use segments and execute since our transaction is composed
+    // of a TX Only part and thereafter a RX Only
+    spi_segment_t segments[2] = {SPI_SEG_TX(1), SPI_SEG_RX(2)};
+    // Flash busy flag
+    bool busy = true;
+    while (busy)
+    {
+        spi_execute(spi, segments, 2, &cmd, &resp);
+        busy = resp & 0x01;
+    }
+}
+
+void done_cb(const uint32_t* txbuff, uint32_t txlen, uint32_t* rxbuff, uint32_t rxlen) {
+    PRINTF("\x1b[33mTXN DONE CALLBACK with txlen: %i, rxlen: %i\x1b[m\n", txlen, rxlen);
+}
+
+void rxwm_cb(const uint32_t* txbuff, uint32_t txlen, uint32_t* rxbuff, uint32_t rxlen) {
+    PRINTF("\x1b[36mTXN RXWM CALLBACK with txlen: %i, rxlen: %i\x1b[m\n", txlen, rxlen);
+}
+
+// ========================= THE END =========================
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks/main.c
deleted file mode 100644
index cde898ad..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks/main.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "power_manager.h"
-#include "x-heep.h"
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-static power_manager_t power_manager;
-
-int main(int argc, char *argv[])
-{
-#if MEMORY_BANKS > 2
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-
-    power_manager_counters_t power_manager_ram_blocks_counters;
-
-    // Init ram block 2's counters
-    if (power_gate_counters_init(&power_manager_ram_blocks_counters, 0, 0, 0, 0, 0, 0, 30, 30) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Set retention mode on for ram block 2 domain
-    if (power_gate_ram_block(&power_manager, 2, kRetOn_e, &power_manager_ram_blocks_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Wait some time
-    for (int i=0; i<100; i++) asm volatile("nop");
-
-    // Set retention mode off for ram block 2 domain
-    if (power_gate_ram_block(&power_manager, 2, kRetOff_e, &power_manager_ram_blocks_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    /* write something to stdout */
-    PRINTF("Success.\n\r");
-    return EXIT_SUCCESS;
-
-#else
-    #pragma message ( "this application can run only when MEMORY_BANKS > 2" )
-    return EXIT_SUCCESS;
-#endif
-
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks_external/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks_external/main.c
deleted file mode 100644
index 7b455591..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_set_retentive_ram_blocks_external/main.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "core_v_mini_mcu.h"
-#include "power_manager.h"
-#include "x-heep.h"
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-static power_manager_t power_manager;
-
-int main(int argc, char *argv[])
-{
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-
-    power_manager_counters_t power_manager_external_ram_blocks_counters;
-
-    // Init external ram block 0's counters
-    if (power_gate_counters_init(&power_manager_external_ram_blocks_counters, 0, 0, 0, 0, 0, 0, 30, 30) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Set retention mode on for external ram block 0
-    if (power_gate_external(&power_manager, 0, kRetOn_e, &power_manager_external_ram_blocks_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    // Wait some time
-    for (int i=0; i<100; i++) asm volatile("nop");
-
-    // Set retention mode off for external ram block 0
-    if (power_gate_external(&power_manager, 0, kRetOff_e, &power_manager_external_ram_blocks_counters) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail.\n\r");
-        return EXIT_FAILURE;
-    }
-
-    /* write something to stdout */
-    PRINTF("Success.\n\r");
-    return EXIT_SUCCESS;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c
index 71de642f..53fb896b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_simple_accelerator/main.c
@@ -10,7 +10,7 @@
 
 #define TEST_DATA_SIZE      16
 
-#define PRINTF_IN_SIM   1
+#define PRINTF_IN_SIM   0
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c
deleted file mode 100644
index 0f1a444a..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_host_dma_power_gate/main.c
+++ /dev/null
@@ -1,341 +0,0 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "core_v_mini_mcu.h"
-#include "csr.h"
-#include "hart.h"
-#include "handler.h"
-#include "soc_ctrl.h"
-#include "spi_host.h"
-#include "dma.h"
-#include "fast_intr_ctrl.h"
-#include "power_manager.h"
-#include "x-heep.h"
-
-#ifdef TARGET_PYNQ_Z2
-    #define USE_SPI_FLASH
-#endif
-
-/* By default, printfs are activated for FPGA and disabled for simulation. */
-#define PRINTF_IN_FPGA  1
-#define PRINTF_IN_SIM   0
-
-#if TARGET_SIM && PRINTF_IN_SIM
-        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
-    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#else
-    #define PRINTF(...)
-#endif
-
-// Type of data frome the SPI. For types different than words the SPI data is requested in separate transactions
-// word(0), half-word(1), byte(2,3)
-#define SPI_DATA_TYPE DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD
-
-// Number of elements to copy
-#define COPY_DATA_NUM 16
-
-#define FLASH_CLK_MAX_HZ (133*1000*1000) // In Hz (133 MHz for the flash w25q128jvsim used in the EPFL Programmer)
-
-#define REVERT_24b_ADDR(addr) ((((uint32_t)(addr) & 0xff0000) >> 16) | ((uint32_t)(addr) & 0xff00) | (((uint32_t)(addr) & 0xff) << 16))
-
-volatile int8_t dma_intr_flag;
-int8_t core_sleep_flag;
-spi_host_t spi_host;
-
-static power_manager_t power_manager;
-
-void dma_intr_handler_trans_done(void)
-{
-    PRINTF("Non-weak implementation of a DMA interrupt\n\r");
-    dma_intr_flag = 1;
-}
-
-// Reserve memory array
-uint32_t flash_data[COPY_DATA_NUM] __attribute__ ((aligned (4))) = {0x76543210,0xfedcba98,0x579a6f90,0x657d5bee,0x758ee41f,0x01234567,0xfedbca98,0x89abcdef,0x679852fe,0xff8252bb,0x763b4521,0x6875adaa,0x09ac65bb,0x666ba334,0x44556677,0x0000ba98};
-uint32_t copy_data[COPY_DATA_NUM] __attribute__ ((aligned (4)))  = { 0 };
-
-#if SPI_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD
-    #define DATA_TYPE uint32_t
-#elif SPI_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD
-    #define DATA_TYPE uint16_t
-#else
-    #define DATA_TYPE uint8_t
-#endif
-
-#define COPY_DATA_TYPE (COPY_DATA_NUM/(sizeof(uint32_t)/sizeof(DATA_TYPE)))
-
-int main(int argc, char *argv[])
-{
-
-    soc_ctrl_t soc_ctrl;
-    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
-    uint32_t read_byte_cmd;
-    uint32_t* flash_data_lma = flash_data;
-    //set MS 8 bits to 0 as the flash only uses 24b
-    flash_data_lma = (uint32_t*) ((uint32_t)(flash_data_lma) & 0x00FFFFFF);
-
-
-   if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO )
-    {
-#ifdef USE_SPI_FLASH
-        PRINTF("This application cannot work with the memory mapped SPI FLASH module - do not use the FLASH_EXEC linker script for this application\n");
-        return EXIT_SUCCESS;
-#else
-        /*
-            if we are using in SIMULATION the SPIMMIO from Yosys, then the flash_original data is different
-            as the compilation is done differently, so we will store there the first WORDs of code mapped at the beginning of the FLASH
-        */
-        uint32_t* ptr_flash = (uint32_t*)FLASH_MEM_START_ADDRESS;
-        for(int i =0; i < COPY_DATA_NUM ; i++){
-            flash_data[i] = ptr_flash[i];
-        }
-#endif
-    }
-
-    #ifndef USE_SPI_FLASH
-        spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
-    #else
-        spi_host.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
-    #endif
-
-    // Setup power_manager
-    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
-    power_manager.base_addr = power_manager_reg;
-    power_manager_counters_t power_manager_cpu_counters;
-    // Init cpu_subsystem's counters
-    if (power_gate_counters_init(&power_manager_cpu_counters, 300, 300, 300, 300, 300, 300, 0, 0) != kPowerManagerOk_e)
-    {
-        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
-        return EXIT_FAILURE;
-    }
-
-    uint32_t core_clk = soc_ctrl_get_frequency(&soc_ctrl);
-
-    // Enable interrupt on processor side
-    // Enable global interrupt for machine-level interrupts
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-
-    // Set mie.MEIE bit to one to enable machine-level fast dma interrupt
-    const uint32_t mask = 1 << 19;
-    CSR_SET_BITS(CSR_REG_MIE, mask);
-
-    #ifdef USE_SPI_FLASH
-        // Select SPI host as SPI output
-        soc_ctrl_select_spi_host(&soc_ctrl);
-    #endif
-
-    // Enable SPI host device
-    spi_set_enable(&spi_host, true);
-    // Enable SPI output
-    spi_output_enable(&spi_host, true);
-
-    // SPI and SPI_FLASH are the same IP so same register map
-    uint32_t *fifo_ptr_rx = spi_host.base_addr.base + SPI_HOST_RXDATA_REG_OFFSET;
-
-    core_sleep_flag = 0;
-
-    // -- DMA CONFIGURATION --
-
-    dma_init(NULL);
-
-    #ifndef USE_SPI_FLASH
-        uint8_t slot =  DMA_TRIG_SLOT_SPI_RX ; // The DMA will wait for the SPI RX FIFO valid signal
-    #else
-        uint8_t slot =  DMA_TRIG_SLOT_SPI_FLASH_RX ; // The DMA will wait for the SPI FLASH RX FIFO valid signal
-    #endif
-
-    static dma_target_t tgt_src = {
-        .size_du = COPY_DATA_NUM,
-        .inc_du = 0,
-        .type = SPI_DATA_TYPE,
-    };
-    tgt_src.ptr = fifo_ptr_rx;
-    tgt_src.trig = slot;
-
-    static dma_target_t tgt_dst = {
-        .ptr = copy_data,
-        .inc_du = 1,
-        .type = SPI_DATA_TYPE,
-        .trig = DMA_TRIG_MEMORY,
-    };
-
-    static dma_trans_t trans = {
-        .src = &tgt_src,
-        .dst = &tgt_dst,
-        .end = DMA_TRANS_END_INTR,
-    };
-
-    dma_config_flags_t res;
-
-    res = dma_validate_transaction(&trans ,DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
-    PRINTF("trans: %u \n\r", res );
-    res = dma_load_transaction(&trans);
-    PRINTF(" load: %u \n\r", res );
-
-
-
-    // Configure SPI clock
-    // SPI clk freq = 1/2 core clk freq when clk_div = 0
-    // SPI_CLK = CORE_CLK/(2 + 2 * CLK_DIV) <= CLK_MAX => CLK_DIV > (CORE_CLK/CLK_MAX - 2)/2
-    uint16_t clk_div = 0;
-    if(FLASH_CLK_MAX_HZ < core_clk/2){
-        clk_div = (core_clk/(FLASH_CLK_MAX_HZ) - 2)/2; // The value is truncated
-        if (core_clk/(2 + 2 * clk_div) > FLASH_CLK_MAX_HZ) clk_div += 1; // Adjust if the truncation was not 0
-    }
-    // SPI Configuration
-    // Configure chip 0 (flash memory)
-    const uint32_t chip_cfg = spi_create_configopts((spi_configopts_t){
-        .clkdiv     = clk_div,
-        .csnidle    = 0xF,
-        .csntrail   = 0xF,
-        .csnlead    = 0xF,
-        .fullcyc    = false,
-        .cpha       = 0,
-        .cpol       = 0
-    });
-    spi_set_configopts(&spi_host, 0, chip_cfg);
-    spi_set_csid(&spi_host, 0);
-
-    // Reset
-    const uint32_t reset_cmd = 0xFFFFFFFF;
-    spi_write_word(&spi_host, reset_cmd);
-    const uint32_t cmd_reset = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_reset);
-    spi_wait_for_ready(&spi_host);
-
-    // Power up flash
-    const uint32_t powerup_byte_cmd = 0xab;
-    spi_write_word(&spi_host, powerup_byte_cmd);
-    const uint32_t cmd_powerup = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_powerup);
-    spi_wait_for_ready(&spi_host);
-
-    // Load command FIFO with read command (1 Byte at single speed)
-    const uint32_t cmd_read = spi_create_command((spi_command_t){
-        .len        = 3,
-        .csaat      = true,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-
-    dma_intr_flag = 0;
-    dma_launch(&trans);
-    PRINTF("Launched\n\r");
-
-    #if SPI_DATA_TYPE == DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD
-        if(get_spi_flash_mode(&soc_ctrl) != SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO)
-            read_byte_cmd = ((REVERT_24b_ADDR(flash_data_lma) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-        else
-            // we read the data from the FLASH address 0x0, which corresponds to FLASH_MEM_START_ADDRESS
-            read_byte_cmd = ((REVERT_24b_ADDR(0x0) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-        const uint32_t cmd_read_rx = spi_create_command((spi_command_t){ // Single transaction
-            .len        = COPY_DATA_NUM*sizeof(DATA_TYPE) - 1, // In bytes - 1
-            .csaat      = false,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirRxOnly
-        });
-        spi_write_word(&spi_host, read_byte_cmd); // Fill TX FIFO with TX data (read command + 3B address)
-        spi_wait_for_ready(&spi_host); // Wait for readiness to process commands
-        spi_set_command(&spi_host, cmd_read); // Send read command to the external device through SPI
-        spi_wait_for_ready(&spi_host);
-        spi_set_command(&spi_host, cmd_read_rx); // Receive data in RX
-        spi_wait_for_ready(&spi_host);
-    #else
-        const uint32_t cmd_read_rx = spi_create_command((spi_command_t){ // Multiple transactions of the data type
-            .len        = (sizeof(DATA_TYPE) - 1),
-            .csaat      = false,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirRxOnly
-        });
-        DATA_TYPE* flash_ptr = (DATA_TYPE *)flash_data_lma;
-        for (int i = 0; i<COPY_DATA_NUM; i++) { // Multiple 8 or 16-bit transactions, just to try a new mode, we could treat it as int32
-            // Request the same data multiple times
-            if(get_spi_flash_mode(&soc_ctrl) != SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO)
-                read_byte_cmd = ((REVERT_24b_ADDR(&flash_ptr[i]) << 8) | 0x03); // The address bytes sent through the SPI to the Flash are in reverse order
-            else
-                read_byte_cmd = ((REVERT_24b_ADDR(i) << 8) | 0x03);
-            spi_write_word(&spi_host, read_byte_cmd); // Fill TX FIFO with TX data (read command + 3B address)
-            spi_wait_for_ready(&spi_host); // Wait for readiness to process commands
-            spi_set_command(&spi_host, cmd_read); // Send read command to the external device through SPI
-            spi_wait_for_ready(&spi_host);
-            spi_set_command(&spi_host, cmd_read_rx); // Receive data in RX
-            spi_wait_for_ready(&spi_host);
-        }
-    #endif
-
-    // Power gate core and wait for fast DMA interrupt
-    CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-    if(dma_intr_flag == 0) {
-        if (power_gate_core(&power_manager, kDma_pm_e, &power_manager_cpu_counters) != kPowerManagerOk_e)
-        {
-            PRINTF("Error: power manager fail.\n\r");
-            return EXIT_FAILURE;
-        }
-        core_sleep_flag = 1;
-    }
-    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-    if(core_sleep_flag == 1) PRINTF("Woke up from sleep!\n\r");
-
-    // Wait for DMA interrupt
-    if( trans.end == DMA_TRANS_END_POLLING ){
-        PRINTF("Waiting for DMA DONE...\n\r");
-        while( ! dma_is_ready() ){};
-    } else{
-        PRINTF("Waiting for the DMA interrupt...\n\r");
-        while(dma_intr_flag == 0) {
-            wait_for_interrupt();
-        }
-    }
-    PRINTF("triggered!\n\r");
-
-    // Power down flash
-    const uint32_t powerdown_byte_cmd = 0xb9;
-    spi_write_word(&spi_host, powerdown_byte_cmd);
-    const uint32_t cmd_powerdown = spi_create_command((spi_command_t){
-        .len        = 0,
-        .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
-    });
-    spi_set_command(&spi_host, cmd_powerdown);
-    spi_wait_for_ready(&spi_host);
-
-    // The data is already in memory -- Check results
-    PRINTF("flash vs ram...\n\r");
-
-    uint32_t errors = 0;
-    uint32_t count = 0;
-    for (int i = 0; i<COPY_DATA_TYPE; i++) {
-        if(flash_data[i] != copy_data[i]) {
-            PRINTF("@%08x-@%08x : %02x != %02x\n\r" , &flash_data[i] , &copy_data[i], flash_data[i], copy_data[i]);
-            errors++;
-        }
-        count++;
-    }
-
-    if (errors == 0) {
-        PRINTF("success! (bytes checked: %d)\n\r", count*sizeof(DATA_TYPE));
-    } else {
-        PRINTF("failure, %d errors! (Out of %d)\n\r", errors, count);
-
-        return EXIT_FAILURE;
-    }
-
-    return EXIT_SUCCESS;
-}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c
index 2e952816..e602ca88 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_read/main.c
@@ -20,13 +20,13 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
 #endif
 
-#ifdef TARGET_PYNQ_Z2
+#if defined(TARGET_PYNQ_Z2) || defined(TARGET_ZCU104) || defined(TARGET_NEXYS_A7_100T)
     #define USE_SPI_FLASH
 #endif
 
@@ -147,11 +147,11 @@ int main(int argc, char *argv[]) {
     PRINTF("BSP read test\n", LENGTH);
 
     // Pick the correct spi device based on simulation type
-    spi_host_t spi;
+    spi_host_t* spi;
     #ifndef USE_SPI_FLASH
-    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
+    spi = spi_host1;
     #else
-    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
+    spi = spi_flash;
     #endif
 
     // Define status variable
@@ -233,7 +233,7 @@ uint32_t test_read_dma(uint32_t *test_buffer, uint32_t len) {
     uint32_t *test_buffer_flash = test_buffer;
 
     // Read from flash memory at the same address
-    w25q_error_codes_t status = w25q128jw_read_standard_dma(test_buffer_flash, flash_data, len);
+    w25q_error_codes_t status = w25q128jw_read_standard_dma(test_buffer_flash, flash_data, len, 0, 0);
     if (status != FLASH_OK) exit(EXIT_FAILURE);
 
     // Check if what we read is correct (i.e. flash_data == test_buffer)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c
index 2b1a362b..b95fcad0 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spi_write/main.c
@@ -25,13 +25,13 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
 #endif
 
-#ifdef TARGET_PYNQ_Z2
+#if defined(TARGET_PYNQ_Z2) || defined(TARGET_ZCU104) || defined(TARGET_NEXYS_A7_100T)
     #define USE_SPI_FLASH
 #endif
 
@@ -140,6 +140,9 @@ void erase_memory(uint32_t addr);
 w25q_error_codes_t global_status;
 
 int main(int argc, char *argv[]) {
+    // Initialize the DMA
+    dma_init(NULL);
+    
     soc_ctrl_t soc_ctrl;
     soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
 
@@ -151,12 +154,12 @@ int main(int argc, char *argv[]) {
 
     PRINTF("BSP write test\n");
 
-    // Pick the correct spi device
-    spi_host_t spi;
+    // Pick the correct spi device based on simulation type
+    spi_host_t* spi;
     #ifndef USE_SPI_FLASH
-    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_HOST_START_ADDRESS);
+    spi = spi_host1;
     #else
-    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
+    spi = spi_flash;
     #endif
 
     // Define status variable
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_spidma_powergate/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spidma_powergate/main.c
new file mode 100644
index 00000000..6e197adf
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_spidma_powergate/main.c
@@ -0,0 +1,192 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "x-heep.h"
+#include "w25q128jw.h"
+#include "csr.h"
+#include "core_v_mini_mcu.h"
+#include "power_manager.h"
+
+/* By default, PRINTFs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+#if defined(TARGET_PYNQ_Z2) || defined(TARGET_ZCU104) || defined(TARGET_NEXYS_A7_100T)
+    #define USE_SPI_FLASH
+#endif
+
+#define FLASH_ONLY_WORDS 32
+#define FLASH_ONLY_BYTES (FLASH_ONLY_WORDS*4)
+
+uint32_t on_chip_buffer[FLASH_ONLY_WORDS];
+
+int32_t __attribute__((section(".xheep_data_flash_only"))) __attribute__ ((aligned (16))) flash_only_buffer[FLASH_ONLY_WORDS] = {
+    0xABCDEF00,
+    0xABCDEF01,
+    0xABCDEF02,
+    0xABCDEF03,
+    0xABCDEF04,
+    0xABCDEF05,
+    0xABCDEF06,
+    0xABCDEF07,
+    0xABCDEF08,
+    0xABCDEF09,
+    0xABCDEF0A,
+    0xABCDEF0B,
+    0xABCDEF0C,
+    0xABCDEF0D,
+    0xABCDEF0E,
+    0xABCDEF0F,
+    0xABCDEF10,
+    0xABCDEF11,
+    0xABCDEF12,
+    0xABCDEF13,
+    0xABCDEF14,
+    0xABCDEF15,
+    0xABCDEF16,
+    0xABCDEF17,
+    0xABCDEF18,
+    0xABCDEF19,
+    0xABCDEF1A,
+    0xABCDEF1B,
+    0xABCDEF1C,
+    0xABCDEF1D,
+    0xABCDEF1E,
+    0xABCDEF1F,
+};
+
+int32_t __attribute__ ((aligned (16))) flash_only_buffer_golden_value[FLASH_ONLY_WORDS] = {
+    0xABCDEF00,
+    0xABCDEF01,
+    0xABCDEF02,
+    0xABCDEF03,
+    0xABCDEF04,
+    0xABCDEF05,
+    0xABCDEF06,
+    0xABCDEF07,
+    0xABCDEF08,
+    0xABCDEF09,
+    0xABCDEF0A,
+    0xABCDEF0B,
+    0xABCDEF0C,
+    0xABCDEF0D,
+    0xABCDEF0E,
+    0xABCDEF0F,
+    0xABCDEF10,
+    0xABCDEF11,
+    0xABCDEF12,
+    0xABCDEF13,
+    0xABCDEF14,
+    0xABCDEF15,
+    0xABCDEF16,
+    0xABCDEF17,
+    0xABCDEF18,
+    0xABCDEF19,
+    0xABCDEF1A,
+    0xABCDEF1B,
+    0xABCDEF1C,
+    0xABCDEF1D,
+    0xABCDEF1E,
+    0xABCDEF1F,
+};
+
+
+int main(int argc, char *argv[])
+{
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+
+    if ( get_spi_flash_mode(&soc_ctrl) == SOC_CTRL_SPI_FLASH_MODE_SPIMEMIO ) {
+        PRINTF("This application cannot work with the memory mapped SPI FLASH"
+            "module - do not use the FLASH_EXEC linker script for this application\n");
+        return EXIT_SUCCESS;
+    }
+
+    // Pick the correct spi device based on simulation type
+    spi_host_t* spi;
+    #ifndef USE_SPI_FLASH
+    spi = spi_host1;
+    #else
+    spi = spi_flash;
+    #endif
+
+    // Setup power_manager
+    power_manager_t power_manager;
+    mmio_region_t power_manager_reg = mmio_region_from_addr(POWER_MANAGER_START_ADDRESS);
+    power_manager.base_addr = power_manager_reg;
+    power_manager_counters_t power_manager_counters;
+    //counters
+    uint32_t reset_off, reset_on, switch_off, switch_on, iso_off, iso_on;
+
+    //Turn off: first, isolate the CPU outputs, then I reset it, then I switch it off (reset and switch off order does not really matter)
+    iso_off = 10;
+    reset_off = iso_off + 5;
+    switch_off = reset_off + 5;
+    //Turn on: first, give back power by switching on, then deassert the reset, the unisolate the CPU outputs
+    switch_on = 10;
+    reset_on = switch_on + 20; //give 20 cycles to emulate the turn on time, this number depends on technology and here it is just a random number
+    iso_on = reset_on + 5;
+
+    if (power_gate_counters_init(&power_manager_counters, reset_off, reset_on, switch_off, switch_on, iso_off, iso_on, 0, 0) != kPowerManagerOk_e)
+    {
+        PRINTF("Error: power manager fail. Check the reset and powergate counters value\n\r");
+        return EXIT_FAILURE;
+    }
+
+    // Define status variable
+    int32_t errors = 0;
+
+    // Init SPI host and SPI<->Flash bridge parameters
+    if (w25q128jw_init(spi) != FLASH_OK) return EXIT_FAILURE;
+
+    uint32_t *test_buffer_flash = heep_get_flash_address_offset(flash_only_buffer);
+    // Read from flash memory at the same address
+    w25q_error_codes_t status = w25q128jw_read_standard_dma_async(test_buffer_flash, on_chip_buffer, FLASH_ONLY_BYTES);
+    if (status != FLASH_OK) exit(EXIT_FAILURE);
+
+    //wait for the DMA to finish in DEEP SLEEP mode
+    while (!dma_is_ready(0))
+    {
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
+        if (dma_is_ready(0) == 0)
+        {
+                PRINTF("Going to sleep...\r\n");
+                if (power_gate_core(&power_manager, kDma_pm_e, &power_manager_counters) != kPowerManagerOk_e)
+                {
+                    PRINTF("Error: power manager fail.\n\r");
+                    return EXIT_FAILURE;
+                }
+                PRINTF("Woken up...\r\n");
+
+        }
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+    }
+
+
+    PRINTF("Check results...\r\n");
+
+    // Check if what we read is correct (i.e. on_chip_buffer == flash_only_buffer_golden_value)
+    for(int i = 0; i < FLASH_ONLY_WORDS; i++) {
+        if (on_chip_buffer[i] != flash_only_buffer_golden_value[i]) {
+            errors++;
+            PRINTF("Error: on_chip_buffer[%d] = 0x%08x, flash_only_buffer_golden_value[%d] = 0x%08x\n", i, on_chip_buffer[i], i, flash_only_buffer_golden_value[i]);
+        }
+    }
+
+    if(errors==0) PRINTF("TEST RUN SUCCEFFULLY\r\n");
+
+    return errors;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_timer_sdk/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_timer_sdk/main.c
new file mode 100644
index 00000000..cb5bb5ae
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_timer_sdk/main.c
@@ -0,0 +1,126 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: example_timer_sdk.c
+// Author: Juan Sapriza, Francesco Poluzzi
+// Date: 23/07/2024
+// Description: Example application to test the Timer SDK. Will count the time to execute a few short tasks.
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <math.h>
+#include "core_v_mini_mcu.h"
+#include "timer_sdk.h"
+#include "x-heep.h"
+#include "soc_ctrl.h"
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+/* Error tolerances for the tests. */
+#define CYCLE_TOLERANCE  2         // cycles tolerance for simple timer reads
+#define INTERRUPT_TOLERANCE 70     // cycles tolerance for timer interrupt
+#define TIMER_WAIT_TOLERANCE 20   // milliseconds tolerance for timer wait
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+void __attribute__((aligned(4), interrupt)) handler_irq_timer(void) {
+    timer_arm_stop();
+    timer_irq_clear();
+    return;   
+}
+
+int main(){
+    uint32_t i = 0;
+    uint32_t timer_cycles;
+    uint32_t nop_cycles[4];
+
+    // Get current Frequency
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz = soc_ctrl_get_frequency(&soc_ctrl);
+
+    timer_cycles_init();         // Init the timer SDK for clock cycles
+    timer_start();              // Start counting the time
+    nop_cycles[0] = timer_stop();  // Stop counting the time
+    PRINTF("0 NOPs:\t%d cc\n\r", nop_cycles[0] );
+      
+    timer_start();     
+    asm volatile ("nop");
+    nop_cycles[1] = timer_stop();  
+    PRINTF("1 NOP:\t%d cc\n\r", nop_cycles[1] );
+    
+    timer_start();              
+    asm volatile ("nop");
+    asm volatile ("nop");
+    nop_cycles[2] = timer_stop();  
+    PRINTF("2 NOPs:\t%d cc\n\r", nop_cycles[2] );
+
+    timer_start();              
+    asm volatile ("nop");
+    asm volatile ("nop");
+    asm volatile ("nop");
+    nop_cycles[3] = timer_stop();  
+    PRINTF("3 NOPs:\t%d cc\n\r", nop_cycles[3] );
+
+    if( abs(nop_cycles[1] - nop_cycles[0])>CYCLE_TOLERANCE || abs(nop_cycles[2] - nop_cycles[1])>CYCLE_TOLERANCE || abs(nop_cycles[3] - nop_cycles[2])>CYCLE_TOLERANCE){ 
+        PRINTF("Clock count failed\n\r");
+        return EXIT_FAILURE;
+    } 
+
+    enable_timer_interrupt();   // Enable the timer machine-level interrupt
+
+    timer_cycles_init();
+    timer_irq_enable();
+    timer_arm_start(1000);            
+    asm volatile ("wfi");       // Wait for interrupt
+    timer_cycles = timer_stop();  
+    if(abs(timer_cycles-1000) < INTERRUPT_TOLERANCE){ 
+        PRINTF("Timer threshold interrupt working\n" );
+    } else {
+        PRINTF("Timer threshold interrupt failed\n\r");
+        return EXIT_FAILURE;
+    }
+    
+    timer_cycles_init();           // Init the timer SDK for microseconds
+    timer_start(); 
+    for(i = 0; i < 1000; i++){
+        asm volatile ("nop");
+    }
+    timer_cycles = timer_stop();  
+    PRINTF("Microseconds for 1000 NOPs:\t%d μs\n\r", (uint32_t)get_time_from_cycles(timer_cycles) );
+
+    #ifdef TARGET_IS_FPGA
+        PRINTF("Wait 5 second\n\r");
+        timer_wait_us(5000000);       // Wait for 5 seconds 
+        timer_cycles = timer_stop();     
+        PRINTF("Done\n\r");
+
+        if(abs(timer_cycles-(5*freq_hz)) > TIMER_WAIT_TOLERANCE){ 
+            PRINTF("Timer wait failed\n\r");
+            return EXIT_FAILURE;
+        }
+    #endif
+    #ifdef TARGET_SIM  // Reduced time for simulation for faster testing
+        PRINTF("Wait 0.001 second\n\r");
+        timer_wait_us(1000);       // Wait for 1 millisecond
+        timer_cycles = timer_stop();     
+        PRINTF("Done\n\r");
+
+        if(abs(timer_cycles-(0.001*freq_hz)) > TIMER_WAIT_TOLERANCE){ 
+            PRINTF("Timer wait failed\n\r");
+            return EXIT_FAILURE;
+        }
+    #endif
+
+    PRINTF("All tests passed\n\r");
+    return EXIT_SUCCESS;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/hello_world/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/hello_world/main.c
index e6133973..bbe2f071 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/hello_world/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/hello_world/main.c
@@ -25,4 +25,3 @@ int main(int argc, char *argv[])
     printf("hello world!\n");
     return EXIT_SUCCESS;
 }
-
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c
index 3228651d..181a3dd9 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/minver/chipsupport.c
@@ -31,7 +31,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
+#elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
diff --git a/hw/vendor/esl_epfl_x_heep/sw/cmake/riscv.cmake b/hw/vendor/esl_epfl_x_heep/sw/cmake/riscv.cmake
index 5c9d070d..972710f5 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/cmake/riscv.cmake
+++ b/hw/vendor/esl_epfl_x_heep/sw/cmake/riscv.cmake
@@ -43,7 +43,7 @@ get_filename_component(RISCV_TOOLCHAIN_BIN_EXT ${RISCV_GCC_COMPILER} EXT)
 
 #message( "RISC-V GCC Path: ${RISCV_TOOLCHAIN_BIN_PATH}" )
 
-STRING(REGEX REPLACE "\-gcc" "-" GCC_CROSS_COMPILE ${RISCV_GCC_COMPILER})
+STRING(REGEX REPLACE "\-gcc$" "-" GCC_CROSS_COMPILE ${RISCV_GCC_COMPILER})
 if ($ENV{COMPILER} MATCHES "clang")
      STRING(REGEX REPLACE "clang" "" CLANG_CROSS_COMPILE ${RISCV_CLANG_COMPILER})
 endif()
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
index 5c7763f5..04908d8e 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
@@ -24,6 +24,10 @@
 * @brief  Source file of the W25Q-family flash memory driver.
 */
 
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
 /****************************************************************************/
 /**                                                                        **/
 /*                             MODULES USED                                 */
@@ -46,6 +50,8 @@
 
 /* To get TX and RX FIFO depth */
 #include "spi_host_regs.h"
+/* To get SPI functions */
+#include "spi_host.h"
 
 /* To get the target of the compilation (sim or pynq) */
 #include "x-heep.h"
@@ -72,7 +78,7 @@
 /**
  * @bref If the target is the FPGA, use the SPI FLASH.
 */
-#ifdef TARGET_PYNQ_Z2
+#ifndef TARGET_SIM
 #define USE_SPI_FLASH
 #endif
 
@@ -210,7 +216,7 @@ static int32_t MIN(int32_t a, int32_t b) {
 /**
  * @brief SPI structure.
 */
-spi_host_t __attribute__((section(".xheep_init_data_crt0"))) spi; //this variable is also used by the crt0, thus keep it in this section
+spi_host_t* __attribute__((section(".xheep_init_data_crt0"))) spi; //this variable is also used by the crt0, thus keep it in this section
 
 /**
  * @brief Static vector used in the erase_and_write function.
@@ -231,11 +237,11 @@ uint8_t sector_data[FLASH_SECTOR_SIZE];
 
 void w25q128jw_init_crt0() {
     //make sure spi variable is into the xheep_init_data_crt0 section
-    spi.base_addr = mmio_region_from_addr((uintptr_t)SPI_FLASH_START_ADDRESS);
+    spi = spi_flash;
     return;
 }
 
-w25q_error_codes_t w25q128jw_init(spi_host_t spi_host) {
+w25q_error_codes_t w25q128jw_init(spi_host_t* spi_host) {
     /*
      * Check if memory mapped SPI is enabled. Current version of the bsp
      * does not support memory mapped SPI.
@@ -253,24 +259,24 @@ w25q_error_codes_t w25q128jw_init(spi_host_t spi_host) {
     #endif // USE_SPI_FLASH
 
     // Enable SPI host device
-    spi_set_enable(&spi, true);
+    spi_set_enable(spi, true);
 
     // Enable SPI output
-    spi_output_enable(&spi, true);
+    spi_output_enable(spi, true);
 
     // Configure SPI<->Flash connection on CSID 0
     configure_spi();
 
     // Set CSID
-    spi_set_csid(&spi, 0);
+    spi_set_csid(spi, 0);
 
     // Power up flash
     flash_power_up();
 
     // Set QE bit (only FPGA, simulation do not support status registers at all)
-    #ifdef TARGET_PYNQ_Z2
+    #ifndef TARGET_SIM
     if (set_QE_bit() == FLASH_ERROR) return FLASH_ERROR; // Error occurred while setting QE bit
-    #endif // TARGET_PYNQ_Z2
+    #endif // TARGET_SIM
 
     return FLASH_OK; // Success
 }
@@ -287,7 +293,7 @@ w25q_error_codes_t w25q128jw_read(uint32_t addr, void *data, uint32_t length) {
         if (status != FLASH_OK) return status;
     } else {
         // Wait DMA to be free
-        while(!dma_is_ready());
+        while(!dma_is_ready(0));
         status = w25q128jw_read_quad_dma(addr, data, length);
         if (status != FLASH_OK) return status;
     }
@@ -306,7 +312,7 @@ w25q_error_codes_t w25q128jw_write(uint32_t addr, void *data, uint32_t length, u
         status = erase_and_write(addr, data, length);
     } else {
         // Wait DMA to be free
-        while(!dma_is_ready());
+        while(!dma_is_ready(0));
         status = w25q128jw_write_quad_dma(addr, data, length);
     }
 
@@ -320,29 +326,29 @@ w25q_error_codes_t w25q128jw_read_standard(uint32_t addr, void* data, uint32_t l
     // Address + Read command
     uint32_t read_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_RD);
     // Load command to TX FIFO
-    spi_write_word(&spi, read_byte_cmd);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, read_byte_cmd);
+    spi_wait_for_ready(spi);
 
     // Set up segment parameters -> send command and address
     const uint32_t cmd_read_1 = spi_create_command((spi_command_t){
         .len        = 3,                 // 4 Bytes
         .csaat      = true,              // Command not finished
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
     // Load segment parameters to COMMAND register
-    spi_set_command(&spi, cmd_read_1);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read_1);
+    spi_wait_for_ready(spi);
 
     // Set up segment parameters -> read length bytes
     const uint32_t cmd_read_2 = spi_create_command((spi_command_t){
         .len        = length-1,          // len bytes
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirRxOnly      // Read only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_RX_ONLY      // Read only
     });
-    spi_set_command(&spi, cmd_read_2);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read_2);
+    spi_wait_for_ready(spi);
 
     /*
      * Set RX watermark to length. The watermark is in words.
@@ -359,20 +365,20 @@ w25q_error_codes_t w25q128jw_read_standard(uint32_t addr, void* data, uint32_t l
     uint32_t *data_32bit = (uint32_t *)data;
     while (flag) {
         if (length >= SPI_HOST_PARAM_RX_DEPTH) {
-            spi_set_rx_watermark(&spi, SPI_HOST_PARAM_RX_DEPTH>>2);
+            spi_set_rx_watermark(spi, SPI_HOST_PARAM_RX_DEPTH>>2);
             length -= SPI_HOST_PARAM_RX_DEPTH;
             to_read += SPI_HOST_PARAM_RX_DEPTH;
         }
         else {
-            spi_set_rx_watermark(&spi, (length%4==0 ? length>>2 : (length>>2)+1));
+            spi_set_rx_watermark(spi, (length%4==0 ? length>>2 : (length>>2)+1));
             to_read += length;
             flag = 0;
         }
         // Wait till SPI RX FIFO is full (or I read all the data)
-        spi_wait_for_rx_watermark(&spi);
+        spi_wait_for_rx_watermark(spi);
         // Read data from SPI RX FIFO
         for (int i = i_start; i < to_read>>2; i++) {
-            spi_read_word(&spi, &data_32bit[i]); // Writes a full word
+            spi_read_word(spi, &data_32bit[i]); // Writes a full word
         }
         // Update the starting index
         i_start += SPI_HOST_PARAM_RX_DEPTH>>2;
@@ -380,7 +386,7 @@ w25q_error_codes_t w25q128jw_read_standard(uint32_t addr, void* data, uint32_t l
     // Take into account the extra bytes (if any)
     if (length_original % 4 != 0) {
         uint32_t last_word = 0;
-        spi_read_word(&spi, &last_word);
+        spi_read_word(spi, &last_word);
         memcpy(&data_32bit[length_original>>2], &last_word, length%4);
     }
 
@@ -410,9 +416,9 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data,
         if (status != FLASH_OK) return FLASH_ERROR;
 
         // Erase the sector (no need to do so in simulation)
-        #ifdef TARGET_PYNQ_Z2
+        #ifndef TARGET_SIM
         w25q128jw_4k_erase(sector_start_addr);
-        #endif // TARGET_PYNQ_Z2
+        #endif // TARGET_SIM
 
         // Calculate the length of data to write in this sector
         uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
@@ -435,19 +441,19 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data,
 }
 
 
+w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_dma, uint8_t no_sanity_checks) {
 
-w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length) {
     // Sanity checks
-    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+    if (!no_sanity_checks)  if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
 
     /*
      * SET UP DMA
     */
     // SPI and SPI_FLASH are the same IP so same register map
-    uint32_t *fifo_ptr_rx = spi.base_addr.base + SPI_HOST_RXDATA_REG_OFFSET;
+    uint32_t *fifo_ptr_rx = (uint32_t *)((uintptr_t)spi + SPI_HOST_RXDATA_REG_OFFSET);
 
     // Init DMA, the integrated DMA is used (peri == NULL)
-    dma_init(NULL);
+    if(!no_wait_dma)    dma_init(NULL);
 
     // The DMA will wait for the SPI HOST/FLASH RX FIFO valid signal
     #ifndef USE_SPI_FLASH
@@ -484,6 +490,7 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32
     };
 
     // Validate, load and launch DMA transaction
+
     dma_config_flags_t res;
     res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
     res = dma_load_transaction(&trans);
@@ -492,42 +499,139 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32
     // Address + Read command
     uint32_t read_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_RD);
     // Load command to TX FIFO
-    spi_write_word(&spi, read_byte_cmd);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, read_byte_cmd);
+    spi_wait_for_ready(spi);
 
     // Set up segment parameters -> send command and address
     const uint32_t cmd_read_1 = spi_create_command((spi_command_t){
         .len        = 3,                 // 4 Bytes
         .csaat      = true,              // Command not finished
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
     // Load segment parameters to COMMAND register
-    spi_set_command(&spi, cmd_read_1);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read_1);
+    spi_wait_for_ready(spi);
 
     // Set up segment parameters -> read length bytes
     const uint32_t cmd_read_2 = spi_create_command((spi_command_t){
         .len        = length-1,          // len bytes
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirRxOnly      // Read only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_RX_ONLY      // Read only
     });
-    spi_set_command(&spi, cmd_read_2);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read_2);
+    spi_wait_for_ready(spi);
 
     // Wait for DMA to finish transaction
-    while(!dma_is_ready());
+    if(!no_wait_dma) while(!dma_is_ready(0));
 
     // Take into account the extra bytes (if any)
     if (length % 4 != 0) {
         uint32_t last_word = 0;
-        spi_read_word(&spi, &last_word);
+
+        spi_read_word((spi_host_t *)spi, &last_word);
+    #ifdef __cplusplus
+        memcpy(static_cast<uint8_t*>(data) + length - (length % 4), &last_word, length % 4);
+    #else
         memcpy(&data[length - length%4], &last_word, length%4);
+    #endif
     }
 
     return FLASH_OK;
 }
+w25q_error_codes_t w25q128jw_read_standard_dma_async(uint32_t addr, void *data, uint32_t length) {
+
+    // Sanity checks
+    if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
+
+    // Take into account the extra bytes (if any)
+    if (length % 4 != 0) {
+        //only multiple of 4 bytes are supported in this function
+        return FLASH_ERROR;
+    }
+
+    /*
+     * SET UP DMA
+    */
+    // SPI and SPI_FLASH are the same IP so same register map
+    uint32_t *fifo_ptr_rx = (uint32_t *)((uintptr_t)spi + SPI_HOST_RXDATA_REG_OFFSET);
+
+    // Init DMA, the integrated DMA is used (peri == NULL)
+    dma_init(NULL);
+
+    // The DMA will wait for the SPI HOST/FLASH RX FIFO valid signal
+    #ifndef USE_SPI_FLASH
+        uint8_t slot = DMA_TRIG_SLOT_SPI_RX;
+    #else
+        uint8_t slot = DMA_TRIG_SLOT_SPI_FLASH_RX;
+    #endif
+
+    // Set up DMA source target
+    static dma_target_t tgt_src = {
+        .inc_du = 0, // Target is peripheral, no increment
+        .type = DMA_DATA_TYPE_WORD, // Data type is word
+    };
+    // Size is in data units (words in this case)
+    tgt_src.size_du = length>>2;
+    // Target is SPI RX FIFO
+    tgt_src.ptr = (uint8_t*)fifo_ptr_rx;
+    // Trigger to control the data flow
+    tgt_src.trig = slot;
+
+    // Set up DMA destination target
+    static dma_target_t tgt_dst = {
+        .inc_du = 1, // Increment by 1 data unit (word)
+        .type = DMA_DATA_TYPE_WORD, // Data type is byte
+        .trig = DMA_TRIG_MEMORY, // Read-write operation to memory
+    };
+    tgt_dst.ptr = (uint8_t*)data; // Target is the data buffer
+
+    // Set up DMA transaction
+    static dma_trans_t trans = {
+        .src = &tgt_src,
+        .dst = &tgt_dst,
+        .end = DMA_TRANS_END_INTR, //so that you can wait for interrupt
+    };
+    // Validate, load and launch DMA transaction
+    dma_config_flags_t res;
+    res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    res = dma_load_transaction(&trans);
+    res = dma_launch(&trans);
+
+    // Address + Read command
+    uint32_t read_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_RD);
+    // Load command to TX FIFO
+    spi_write_word(spi, read_byte_cmd);
+    spi_wait_for_ready(spi);
+
+    // Set up segment parameters -> send command and address
+    const uint32_t cmd_read_1 = spi_create_command((spi_command_t){
+        .len        = 3,                 // 4 Bytes
+        .csaat      = true,              // Command not finished
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
+    });
+    // Load segment parameters to COMMAND register
+    spi_set_command(spi, cmd_read_1);
+    spi_wait_for_ready(spi);
+
+    // Set up segment parameters -> read length bytes
+    const uint32_t cmd_read_2 = spi_create_command((spi_command_t){
+        .len        = length-1,          // len bytes
+        .csaat      = false,             // End command
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_RX_ONLY      // Read only
+    });
+    spi_set_command(spi, cmd_read_2);
+    spi_wait_for_ready(spi);
+
+    // Wait for DMA to finish transaction outside this function, the DMA generates also an interrupt
+    // However, you need to enable the interrupt in the INT controllers, and CPU
+
+    return FLASH_OK;
+}
+
 
 w25q_error_codes_t w25q128jw_write_standard_dma(uint32_t addr, void *data, uint32_t length) {
     // Call the wrapper with quad = 0, dma = 1
@@ -547,13 +651,13 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard_dma(uint32_t addr, void* d
         uint32_t sector_start_addr = current_addr & 0xfffff000;
 
         // Read the full sector and save it into RAM
-        status = w25q128jw_read_standard_dma(sector_start_addr, sector_data, FLASH_SECTOR_SIZE);
+        status = w25q128jw_read_standard_dma(sector_start_addr, sector_data, FLASH_SECTOR_SIZE, 0, 0);
         if (status != FLASH_OK) return FLASH_ERROR;
 
         // Erase the sector (no need to do so in simulation)
-        #ifdef TARGET_PYNQ_Z2
+        #ifndef TARGET_SIM
         w25q128jw_4k_erase(sector_start_addr);
-        #endif // TARGET_PYNQ_Z2
+        #endif // TARGET_SIM
 
         // Calculate the length of data to write in this sector
         uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
@@ -582,54 +686,54 @@ w25q_error_codes_t w25q128jw_read_quad(uint32_t addr, void *data, uint32_t lengt
 
     // Send quad read command at standard speed
     uint32_t cmd_read_quadIO = FC_RDQIO;
-    spi_write_word(&spi, cmd_read_quadIO);
+    spi_write_word(spi, cmd_read_quadIO);
     const uint32_t cmd_read = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = true,              // Command not finished
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_read);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read);
+    spi_wait_for_ready(spi);
 
     /*
      * Send address at quad speed.
      * Last byte is Fxh (here FFh) required by W25Q128JW
     */
     uint32_t read_byte_cmd = (REVERT_24b_ADDR(addr) | (0xFF << 24));
-    spi_write_word(&spi, read_byte_cmd);
+    spi_write_word(spi, read_byte_cmd);
     const uint32_t cmd_address = spi_create_command((spi_command_t){
         .len        = 3,                // 3 Byte
         .csaat      = true,             // Command not finished
-        .speed      = kSpiSpeedQuad,    // Quad speed
-        .direction  = kSpiDirTxOnly     // Write only
+        .speed      = SPI_SPEED_QUAD,    // Quad speed
+        .direction  = SPI_DIR_TX_ONLY     // Write only
     });
-    spi_set_command(&spi, cmd_address);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_address);
+    spi_wait_for_ready(spi);
 
     // Quad read requires dummy clocks
     const uint32_t dummy_clocks_cmd = spi_create_command((spi_command_t){
-        #ifdef TARGET_PYNQ_Z2
+        #ifndef TARGET_SIM
         .len        = DUMMY_CLOCKS_FAST_READ_QUAD_IO-1,
         #else
         .len        = DUMMY_CLOCKS_SIM-1,
         #endif
         .csaat      = true,            // Command not finished
-        .speed      = kSpiSpeedQuad,   // Quad speed
-        .direction  = kSpiDirDummy     // Dummy
+        .speed      = SPI_SPEED_QUAD,   // Quad speed
+        .direction  = SPI_DIR_DUMMY     // Dummy
     });
-    spi_set_command(&spi, dummy_clocks_cmd);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, dummy_clocks_cmd);
+    spi_wait_for_ready(spi);
 
     // Read back the requested data at quad speed
     const uint32_t cmd_read_rx = spi_create_command((spi_command_t){
         .len        = length-1,        // 32 Byte
         .csaat      = false,           // End command
-        .speed      = kSpiSpeedQuad,   // Quad speed
-        .direction  = kSpiDirRxOnly    // Read only
+        .speed      = SPI_SPEED_QUAD,   // Quad speed
+        .direction  = SPI_DIR_RX_ONLY    // Read only
     });
-    spi_set_command(&spi, cmd_read_rx);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read_rx);
+    spi_wait_for_ready(spi);
 
     /* COMMAND FINISHED */
 
@@ -648,20 +752,20 @@ w25q_error_codes_t w25q128jw_read_quad(uint32_t addr, void *data, uint32_t lengt
     uint32_t *data_32bit = (uint32_t *)data;
     while (flag) {
         if (length >= SPI_HOST_PARAM_RX_DEPTH) {
-            spi_set_rx_watermark(&spi, SPI_HOST_PARAM_RX_DEPTH>>2);
+            spi_set_rx_watermark(spi, SPI_HOST_PARAM_RX_DEPTH>>2);
             length -= SPI_HOST_PARAM_RX_DEPTH;
             to_read += SPI_HOST_PARAM_RX_DEPTH;
         }
         else {
-            spi_set_rx_watermark(&spi, (length%4==0 ? length>>2 : (length>>2)+1));
+            spi_set_rx_watermark(spi, (length%4==0 ? length>>2 : (length>>2)+1));
             to_read += length;
             flag = 0;
         }
         // Wait till SPI RX FIFO is full (or I read all the data)
-        spi_wait_for_rx_watermark(&spi);
+        spi_wait_for_rx_watermark(spi);
         // Read data from SPI RX FIFO
         for (int i = i_start; i < to_read>>2; i++) {
-            spi_read_word(&spi, &data_32bit[i]); // Writes a full word
+            spi_read_word(spi, &data_32bit[i]); // Writes a full word
         }
         // Update the starting index
         i_start += SPI_HOST_PARAM_RX_DEPTH>>2;
@@ -669,7 +773,7 @@ w25q_error_codes_t w25q128jw_read_quad(uint32_t addr, void *data, uint32_t lengt
     // Take into account the extra bytes (if any)
     if (length_original%4 != 0) {
         uint32_t last_word = 0;
-        spi_read_word(&spi, &last_word);
+        spi_read_word(spi, &last_word);
         memcpy(&data_32bit[length_original>>2], &last_word, length%4);
     }
 
@@ -699,9 +803,9 @@ w25q_error_codes_t w25q128jw_erase_and_write_quad(uint32_t addr, void *data, uin
         if (status != FLASH_OK) return FLASH_ERROR;
 
         // Erase the sector (no need to do so in simulation)
-        #ifdef TARGET_PYNQ_Z2
+        #ifndef TARGET_SIM
         w25q128jw_4k_erase(sector_start_addr);
-        #endif // TARGET_PYNQ_Z2
+        #endif // TARGET_SIM
 
         // Calculate the length of data to write in this sector
         uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
@@ -730,54 +834,54 @@ w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t l
 
     // Send quad read command at standard speed
     uint32_t cmd_read_quadIO = FC_RDQIO;
-    spi_write_word(&spi, cmd_read_quadIO);
+    spi_write_word(spi, cmd_read_quadIO);
     const uint32_t cmd_read = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = true,              // Command not finished
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_read);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read);
+    spi_wait_for_ready(spi);
 
     /*
      * Send address at quad speed.
      * Last byte is Fxh (here FFh) required by W25Q128JW
     */
     uint32_t read_byte_cmd = (REVERT_24b_ADDR(addr) | (0xFF << 24));
-    spi_write_word(&spi, read_byte_cmd);
+    spi_write_word(spi, read_byte_cmd);
     const uint32_t cmd_address = spi_create_command((spi_command_t){
         .len        = 3,                // 3 Byte
         .csaat      = true,             // Command not finished
-        .speed      = kSpiSpeedQuad,    // Quad speed
-        .direction  = kSpiDirTxOnly     // Write only
+        .speed      = SPI_SPEED_QUAD,    // Quad speed
+        .direction  = SPI_DIR_TX_ONLY     // Write only
     });
-    spi_set_command(&spi, cmd_address);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_address);
+    spi_wait_for_ready(spi);
 
     // Quad read requires dummy clocks
     const uint32_t dummy_clocks_cmd = spi_create_command((spi_command_t){
-        #ifdef TARGET_PYNQ_Z2
+        #ifndef TARGET_SIM
         .len        = DUMMY_CLOCKS_FAST_READ_QUAD_IO-1, // W25Q128JW flash needs 4 dummy cycles
         #else
         .len        = DUMMY_CLOCKS_SIM-1, // SPI flash simulation model needs 8 dummy cycles
         #endif
         .csaat      = true,              // Command not finished
-        .speed      = kSpiSpeedQuad,     // Quad speed
-        .direction  = kSpiDirDummy       // Dummy
+        .speed      = SPI_SPEED_QUAD,     // Quad speed
+        .direction  = SPI_DIR_DUMMY       // Dummy
     });
-    spi_set_command(&spi, dummy_clocks_cmd);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, dummy_clocks_cmd);
+    spi_wait_for_ready(spi);
 
     // Read back the requested data at quad speed
     const uint32_t cmd_read_rx = spi_create_command((spi_command_t){
         .len        = length-1,        // length bytes
         .csaat      = false,           // End command
-        .speed      = kSpiSpeedQuad,   // Quad speed
-        .direction  = kSpiDirRxOnly    // Read only
+        .speed      = SPI_SPEED_QUAD,   // Quad speed
+        .direction  = SPI_DIR_RX_ONLY    // Read only
     });
-    spi_set_command(&spi, cmd_read_rx);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_read_rx);
+    spi_wait_for_ready(spi);
 
     /* COMMAND FINISHED */
 
@@ -785,7 +889,7 @@ w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t l
      * SET UP DMA
     */
     // SPI and SPI_FLASH are the same IP so same register map
-    uint32_t *fifo_ptr_rx = spi.base_addr.base + SPI_HOST_RXDATA_REG_OFFSET;
+    uint32_t *fifo_ptr_rx = (uint32_t *)((uintptr_t)spi + SPI_HOST_RXDATA_REG_OFFSET);
 
     // Init DMA, the integrated DMA is used (peri == NULL)
     dma_init(NULL);
@@ -831,13 +935,20 @@ w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t l
     res = dma_launch(&trans);
 
     // Wait for DMA to finish transaction
-    while(!dma_is_ready());
+    while(!dma_is_ready(0));
 
     // Take into account the extra bytes (if any)
     if (length % 4 != 0) {
         uint32_t last_word = 0;
-        spi_read_word(&spi, &last_word);
+      
+        spi_read_word((spi_host_t *)spi, &last_word);
+
+    #ifdef __cplusplus
+        memcpy(static_cast<uint8_t*>(data) + length - (length % 4), &last_word, length % 4);
+    #else
         memcpy(&data[length - length%4], &last_word, length%4);
+    #endif
+     
     }
 
     return FLASH_OK;
@@ -845,14 +956,14 @@ w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t l
 
 w25q_error_codes_t w25q128jw_write_quad_dma(uint32_t addr, void *data, uint32_t length) {
     // Call the wrapper with quad = 1, dma = 1
-    return page_write_wrapper(addr, data, length, 1, 1);
+    return page_write_wrapper(addr, (uint8_t *)data, length, 1, 1);
 }
 
 w25q_error_codes_t w25q128jw_erase_and_write_quad_dma(uint32_t addr, void *data, uint32_t length) {
 
     uint32_t remaining_length = length;
     uint32_t current_addr = addr;
-    uint8_t *current_data = data;
+    uint8_t *current_data = (uint8_t *)data;
 
     w25q_error_codes_t status;
 
@@ -865,9 +976,9 @@ w25q_error_codes_t w25q128jw_erase_and_write_quad_dma(uint32_t addr, void *data,
         if (status != FLASH_OK) return FLASH_ERROR;
 
         // Erase the sector (no need to do so in simulation)
-        #ifdef TARGET_PYNQ_Z2
+        #ifndef TARGET_SIM
         w25q128jw_4k_erase(sector_start_addr);
-        #endif // TARGET_PYNQ_Z2
+        #endif // TARGET_SIM
 
         // Calculate the length of data to write in this sector
         uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
@@ -901,16 +1012,16 @@ w25q_error_codes_t w25q128jw_4k_erase(uint32_t addr) {
 
     // Build and send erase command
     uint32_t erase_4k_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_SE);
-    spi_write_word(&spi, erase_4k_cmd);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, erase_4k_cmd);
+    spi_wait_for_ready(spi);
     const uint32_t cmd_erase = spi_create_command((spi_command_t){
         .len        = 3,                 // 4 Bytes
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_erase);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_erase);
+    spi_wait_for_ready(spi);
 
     // Wait for the erase operation to be finished
     flash_wait();
@@ -928,16 +1039,16 @@ w25q_error_codes_t w25q128jw_32k_erase(uint32_t addr) {
 
     // Build and send erase command
     uint32_t erase_32k_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_BE32);
-    spi_write_word(&spi, erase_32k_cmd);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, erase_32k_cmd);
+    spi_wait_for_ready(spi);
     const uint32_t cmd_erase = spi_create_command((spi_command_t){
         .len        = 3,                 // 4 Bytes
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_erase);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_erase);
+    spi_wait_for_ready(spi);
 
     // Wait for the erase operation to be finished
     flash_wait();
@@ -955,16 +1066,16 @@ w25q_error_codes_t w25q128jw_64k_erase(uint32_t addr) {
 
     // Build and send erase command
     uint32_t erase_64k_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | FC_BE64);
-    spi_write_word(&spi, erase_64k_cmd);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, erase_64k_cmd);
+    spi_wait_for_ready(spi);
     const uint32_t cmd_erase = spi_create_command((spi_command_t){
         .len        = 3,                 // 4 Bytes
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_erase);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_erase);
+    spi_wait_for_ready(spi);
 
     // Wait for the erase operation to be finished
     flash_wait();
@@ -978,16 +1089,16 @@ void w25q128jw_chip_erase(void) {
     flash_write_enable();
 
     // Build and send erase command
-    spi_write_word(&spi, FC_CE);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, FC_CE);
+    spi_wait_for_ready(spi);
     const uint32_t cmd_erase = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Bytes
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_erase);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_erase);
+    spi_wait_for_ready(spi);
 
     // Wait for the erase operation to be finished
     flash_wait();
@@ -1014,15 +1125,15 @@ void w25q128jw_reset_force(void) {
 
 void w25q128jw_power_down(void) {
     // Build and send power down command
-    spi_write_word(&spi, FC_PD);
+    spi_write_word(spi, FC_PD);
     const uint32_t cmd_power_down = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_power_down);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_power_down);
+    spi_wait_for_ready(spi);
 }
 
 
@@ -1033,50 +1144,50 @@ void w25q128jw_power_down(void) {
 /****************************************************************************/
 
 static void flash_power_up(void) {
-    spi_write_word(&spi, FC_RPD);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, FC_RPD);
+    spi_wait_for_ready(spi);
     const uint32_t cmd_powerup = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_powerup);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_powerup);
+    spi_wait_for_ready(spi);
 }
 
 static w25q_error_codes_t set_QE_bit(void) {
-    spi_set_rx_watermark(&spi,1);
+    spi_set_rx_watermark(spi,1);
 
     // Read Status Register 2
     const uint32_t reg2_read_cmd = FC_RSR2;
-    spi_write_word(&spi, reg2_read_cmd);
+    spi_write_word(spi, reg2_read_cmd);
 
     const uint32_t reg2_read_1 = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = true,              // Command not finished
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, reg2_read_1);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, reg2_read_1);
+    spi_wait_for_ready(spi);
 
     const uint32_t reg2_read_2 = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Standard speed
-        .direction  = kSpiDirRxOnly      // Read only
+        .speed      = SPI_SPEED_STANDARD, // Standard speed
+        .direction  = SPI_DIR_RX_ONLY      // Read only
     });
-    spi_set_command(&spi, reg2_read_2);
-    spi_wait_for_ready(&spi);
-    spi_wait_for_rx_watermark(&spi);
+    spi_set_command(spi, reg2_read_2);
+    spi_wait_for_ready(spi);
+    spi_wait_for_rx_watermark(spi);
 
     /*
      * the partial word will be zero-padded and inserted into the RX FIFO once the segment is completed
      * The actual register is 8 bit, but the SPI host gives a full word
     */
     uint32_t reg2_data;
-    spi_read_word(&spi, &reg2_data);
+    spi_read_word(spi, &reg2_data);
 
     // Set bit in position 1 (QE bit), leaving the others unchanged
     reg2_data |= 0x2;
@@ -1086,42 +1197,42 @@ static w25q_error_codes_t set_QE_bit(void) {
 
     // Write Status Register 2 (set QE bit)
     const uint32_t reg2_write_cmd = FC_WSR2;
-    spi_write_word(&spi, reg2_write_cmd);
+    spi_write_word(spi, reg2_write_cmd);
 
     const uint32_t reg2_write_1 = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = true,              // Command not finished
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, reg2_write_1);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, reg2_write_1);
+    spi_wait_for_ready(spi);
 
     // Load data to TX FIFO
-    spi_write_word(&spi, reg2_data);
+    spi_write_word(spi, reg2_data);
 
     // Create command segment
     const uint32_t reg2_write_2 = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Standard speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Standard speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, reg2_write_2);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, reg2_write_2);
+    spi_wait_for_ready(spi);
 
     // Wait flash to complete write routine
     flash_wait();
 
     // Read back Status Register 2
-    spi_write_word(&spi, reg2_read_cmd);
-    spi_set_command(&spi, reg2_read_1);
-    spi_wait_for_ready(&spi);
-    spi_set_command(&spi, reg2_read_2);
-    spi_wait_for_ready(&spi);
-    spi_wait_for_rx_watermark(&spi);
+    spi_write_word(spi, reg2_read_cmd);
+    spi_set_command(spi, reg2_read_1);
+    spi_wait_for_ready(spi);
+    spi_set_command(spi, reg2_read_2);
+    spi_wait_for_ready(spi);
+    spi_wait_for_rx_watermark(spi);
     uint32_t reg2_data_check = 0x00;
-    spi_read_word(&spi, &reg2_data_check);
+    spi_read_word(spi, &reg2_data_check);
 
     // Check if the QE bit is set
     if ((reg2_data_check & 0x2) == 0) return FLASH_ERROR;
@@ -1147,60 +1258,60 @@ static void configure_spi(void) {
         .cpha       = 0,
         .cpol       = 0
     });
-    spi_set_configopts(&spi, 0, chip_cfg);
+    spi_set_configopts(spi, 0, chip_cfg);
 }
 
 static void flash_wait(void) {
-    spi_set_rx_watermark(&spi,1);
+    spi_set_rx_watermark(spi,1);
     bool flash_busy = true;
     uint8_t flash_resp[4] = {0xff,0xff,0xff,0xff};
 
     while(flash_busy){
         uint32_t flash_cmd = FC_RSR1; // [CMD] Read status register 1
-        spi_write_word(&spi, flash_cmd); // Push TX buffer
+        spi_write_word(spi, flash_cmd); // Push TX buffer
         uint32_t spi_status_cmd = spi_create_command((spi_command_t){
             .len        = 0,
             .csaat      = true,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirTxOnly
+            .speed      = SPI_SPEED_STANDARD,
+            .direction  = SPI_DIR_TX_ONLY
         });
         uint32_t spi_status_read_cmd = spi_create_command((spi_command_t){
             .len        = 0,
             .csaat      = false,
-            .speed      = kSpiSpeedStandard,
-            .direction  = kSpiDirRxOnly
+            .speed      = SPI_SPEED_STANDARD,
+            .direction  = SPI_DIR_RX_ONLY
         });
-        spi_set_command(&spi, spi_status_cmd);
-        spi_wait_for_ready(&spi);
-        spi_set_command(&spi, spi_status_read_cmd);
-        spi_wait_for_ready(&spi);
-        spi_wait_for_rx_watermark(&spi);
-        spi_read_word(&spi, (uint32_t *)flash_resp);
+        spi_set_command(spi, spi_status_cmd);
+        spi_wait_for_ready(spi);
+        spi_set_command(spi, spi_status_read_cmd);
+        spi_wait_for_ready(spi);
+        spi_wait_for_rx_watermark(spi);
+        spi_read_word(spi, (uint32_t *)flash_resp);
         if ((flash_resp[0] & 0x01) == 0) flash_busy = false;
     }
 }
 
 static void flash_reset(void) {
-    spi_write_word(&spi, FC_ERESET);
-    spi_write_word(&spi, FC_RESET);
-    spi_wait_for_ready(&spi);
+    spi_write_word(spi, FC_ERESET);
+    spi_write_word(spi, FC_RESET);
+    spi_wait_for_ready(spi);
 
     const uint32_t cmd_reset_enable = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_reset_enable);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_reset_enable);
+    spi_wait_for_ready(spi);
     const uint32_t cmd_reset = spi_create_command((spi_command_t){
         .len        = 0,                 // 1 Byte
         .csaat      = false,             // End command
-        .speed      = kSpiSpeedStandard, // Single speed
-        .direction  = kSpiDirTxOnly      // Write only
+        .speed      = SPI_SPEED_STANDARD, // Single speed
+        .direction  = SPI_DIR_TX_ONLY      // Write only
     });
-    spi_set_command(&spi, cmd_reset);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_reset);
+    spi_wait_for_ready(spi);
 }
 
 w25q_error_codes_t erase_and_write(uint32_t addr, uint8_t *data, uint32_t length) {
@@ -1220,9 +1331,9 @@ w25q_error_codes_t erase_and_write(uint32_t addr, uint8_t *data, uint32_t length
         if (status != FLASH_OK) return FLASH_ERROR;
 
         // Erase the sector (no need to do so in simulation)
-        #ifdef TARGET_PYNQ_Z2
+        #ifndef TARGET_SIM
         w25q128jw_4k_erase(sector_start_addr);
-        #endif // TARGET_PYNQ_Z2
+        #endif // TARGET_SIM
 
         // Calculate the length of data to write in this sector
         uint32_t write_length = MIN(FLASH_SECTOR_SIZE - (current_addr - sector_start_addr), remaining_length);
@@ -1299,15 +1410,15 @@ static w25q_error_codes_t page_write(uint32_t addr, uint8_t *data, uint32_t leng
      * The command is picked based on the quad flag.
     */
     const uint32_t write_byte_cmd = ((REVERT_24b_ADDR(addr & 0x00ffffff) << 8) | (quad ? FC_PPQ : FC_PP));
-    spi_write_word(&spi, write_byte_cmd);
+    spi_write_word(spi, write_byte_cmd);
     const uint32_t cmd_write = spi_create_command((spi_command_t){
         .len        = 3,
         .csaat      = true,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
+        .speed      = SPI_SPEED_STANDARD,
+        .direction  = SPI_DIR_TX_ONLY
     });
-    spi_set_command(&spi, cmd_write);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_write);
+    spi_wait_for_ready(spi);
 
     /*
      * Place data in TX FIFO
@@ -1319,14 +1430,14 @@ static w25q_error_codes_t page_write(uint32_t addr, uint8_t *data, uint32_t leng
     } else {
         uint32_t *data_32bit = (uint32_t *)data;
         for (int i = 0; i < length>>2; i++) {
-            spi_wait_for_tx_not_full(&spi);
-            spi_write_word(&spi, data_32bit[i]);
+            spi_wait_for_tx_not_full(spi);
+            spi_write_word(spi, data_32bit[i]);
         }
         if (length % 4 != 0) {
             uint32_t last_word = 0;
             memcpy(&last_word, &data[length - length % 4], length % 4);
-            spi_wait_for_tx_not_full(&spi);
-            spi_write_word(&spi, last_word);
+            spi_wait_for_tx_not_full(spi);
+            spi_write_word(spi, last_word);
         }
     }
 
@@ -1337,21 +1448,21 @@ static w25q_error_codes_t page_write(uint32_t addr, uint8_t *data, uint32_t leng
     const uint32_t cmd_write_2 = spi_create_command((spi_command_t){
         .len        = length-1,
         .csaat      = false,
-        .speed      = quad ? kSpiSpeedQuad : kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
+        .speed      = quad ? SPI_SPEED_QUAD : SPI_SPEED_STANDARD,
+        .direction  = SPI_DIR_TX_ONLY
     });
-    spi_set_command(&spi, cmd_write_2);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_write_2);
+    spi_wait_for_ready(spi);
 
     // Wait for flash to be ready again (FPGA only)
-    #ifdef TARGET_PYNQ_Z2
+    #ifndef TARGET_SIM
     flash_wait();
-    #endif // TARGET_PYNQ_Z2
+    #endif // TARGET_SIM
 }
 
 static w25q_error_codes_t dma_send_toflash(uint8_t *data, uint32_t length) {
     // SPI and SPI_FLASH are the same IP so same register map
-    uint32_t *fifo_ptr_tx = spi.base_addr.base + SPI_HOST_TXDATA_REG_OFFSET;
+    uint32_t *fifo_ptr_tx = (uint32_t *)((uintptr_t)spi + SPI_HOST_TXDATA_REG_OFFSET);
 
     // Init DMA, the integrated DMA is used (peri == NULL)
     dma_init(NULL);
@@ -1402,28 +1513,28 @@ static w25q_error_codes_t dma_send_toflash(uint8_t *data, uint32_t length) {
     if (res != DMA_CONFIG_OK) return FLASH_ERROR_DMA;
 
     // Wait for DMA to finish transaction
-    while(!dma_is_ready());
+    while(!dma_is_ready(0));
 
     // Take into account the extra bytes (if any)
     if (length % 4 != 0) {
         uint32_t last_word = 0;
         memcpy(&last_word, &data[length - length % 4], length % 4);
-        spi_wait_for_tx_not_full(&spi);
-        spi_write_word(&spi, last_word);
+        spi_wait_for_tx_not_full(spi);
+        spi_write_word(spi, last_word);
     }
     return FLASH_OK;
 }
 
 static void flash_write_enable(void) {
-    spi_write_word(&spi, FC_WE);
+    spi_write_word(spi, FC_WE);
     const uint32_t cmd_write_en = spi_create_command((spi_command_t){
         .len        = 0,
         .csaat      = false,
-        .speed      = kSpiSpeedStandard,
-        .direction  = kSpiDirTxOnly
+        .speed      = SPI_SPEED_STANDARD,
+        .direction  = SPI_DIR_TX_ONLY
     });
-    spi_set_command(&spi, cmd_write_en);
-    spi_wait_for_ready(&spi);
+    spi_set_command(spi, cmd_write_en);
+    spi_wait_for_ready(spi);
 }
 
 static w25q_error_codes_t w25q128jw_sanity_checks(uint32_t addr, uint8_t *data, uint32_t length) {
@@ -1441,7 +1552,9 @@ static w25q_error_codes_t w25q128jw_sanity_checks(uint32_t addr, uint8_t *data,
 
     return FLASH_OK; // Success
 }
-
+#ifdef __cplusplus
+} // extern "C"
+#endif  // __cplusplus
 /****************************************************************************/
 /**                                                                        **/
 /*                                 EOF                                      */
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
index c6f29e9c..1bc8b5e4 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
@@ -49,6 +49,7 @@
 */
 #define FLASH_CLK_MAX_HZ (133*1000*1000)
 
+
 /**
  * @defgroup flash_commands Flash commands
  * @{
@@ -191,7 +192,7 @@ void w25q128jw_init_crt0();
  *
  * @return FLASH_OK if the flash is correctly initialized, @ref error_codes otherwise.
 */
-w25q_error_codes_t w25q128jw_init(spi_host_t spi_host);
+w25q_error_codes_t w25q128jw_init(spi_host_t* spi_host);
 
 /**
  * @brief Read from flash.
@@ -266,8 +267,17 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data,
  * @param length number of bytes to read.
  * @return FLASH_OK if the read is successful, @ref error_codes otherwise.
 */
-w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void* data, uint32_t length);
+w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_dma, uint8_t no_sanity_checks);
 
+/**
+ * @brief Read from flash at standard speed using DMA but wait for DMA in the application
+ *
+ * @param addr 24-bit flash address to read from.
+ * @param data pointer to the data buffer.
+ * @param length number of bytes to read, must be multiple of 4
+ * @return FLASH_OK if the read is successful, @ref error_codes otherwise.
+*/
+w25q_error_codes_t w25q128jw_read_standard_dma_async(uint32_t addr, void *data, uint32_t length);
 
 /**
  * @brief Write to flash at standard speed using DMA. Use this function only to write to unitialized data
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/assert.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/assert.h
index 0b701dc8..2619af76 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/assert.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/assert.h
@@ -21,11 +21,26 @@
 // defined for C.
 #ifndef __cplusplus
 #define static_assert _Static_assert
-#endif  // __cplusplus
+#endif
+
 
 // `assert()` should not be used. When building with Clang, using this function
 // in device code will emit a compile-time error.
+
+
+#ifndef __cplusplus
 #define assert(do_not_use) \
   static_assert(false, "do not use assert(); use CHECK() instead")
+#else
+    #include <stdio.h>
+    #define assert(expression) \
+        do { \
+            if (!(expression)) { \
+                printf("Assertion failed: %s, file %s, line %d\n", \
+                        #expression, __FILE__, __LINE__); \
+                while(1); \
+            } \
+        } while (0)
+#endif  // __cplusplus*/
 
 #endif  // OPENTITAN_SW_DEVICE_LIB_BASE_FREESTANDING_ASSERT_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdalign.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdalign.h
index 10126c9e..d0cc3f2a 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdalign.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdalign.h
@@ -13,10 +13,16 @@
  * S4p6. This header is specified in detail in S7.15 of the same.
  */
 
+
+
+#ifndef __cplusplus
 #define alignas _Alignas
 #define __alignas_is_defined 1
 
 #define alignof _Alignof
 #define __alignof_is_defined 1
+#endif  // __cplusplus
+
+
 
 #endif  // OPENTITAN_SW_DEVICE_LIB_BASE_FREESTANDING_STDALIGN_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdbool.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdbool.h
index f9a9fa0b..2b04a3af 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdbool.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/freestanding/stdbool.h
@@ -12,11 +12,15 @@
  * This header implements the stdbool.h standard header, as required by C11
  * S4p6. This header is specified in detail in S7.18 of the same.
  */
+#ifndef __cplusplus
+#define _Bool char
 
 #define bool _Bool
 #define true 1
 #define false 0
 
 #define __bool_true_false_are_defined 1
+#endif
+
 
 #endif  // OPENTITAN_SW_DEVICE_LIB_BASE_FREESTANDING_STDBOOL_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c
index 180cdd90..e0234bf1 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c
@@ -2,6 +2,10 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
 #include "memory.h"
 
 extern uint32_t read_32(const void *);
@@ -18,7 +22,7 @@ extern void write_32(uint32_t, void *);
 // built for host-side software.
 
 #if !defined(HOST_BUILD)
-void *memcpy(void *restrict dest, const void *restrict src, size_t len) {
+void *memcpy(void *__restrict dest, const void *__restrict src, size_t len) {
   uint8_t *dest8 = (uint8_t *)dest;
   uint8_t *src8 = (uint8_t *)src;
   for (size_t i = 0; i < len; ++i) {
@@ -84,3 +88,9 @@ void *memrchr(const void *ptr, int value, size_t len) {
   }
   return NULL;
 }
+
+
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h
index 4a9f213b..3ff64ff7 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h
@@ -107,7 +107,7 @@ inline void write_32(uint32_t value, void *ptr) {
  * @param len the number of bytes to copy.
  * @return the value of `dest`.
  */
-void *memcpy(void *restrict dest, const void *restrict src, size_t len);
+void *memcpy(void *__restrict dest, const void *__restrict src, size_t len);
 
 /**
  * Set a region of memory to a particular byte value.
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c
index 58309170..dff7f78a 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c
@@ -2,6 +2,11 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+
 #include "mmio.h"
 
 #include <stdalign.h>
@@ -158,3 +163,8 @@ extern void mmio_region_nonatomic_set_bit32(mmio_region_t base,
 extern void mmio_region_write_only_set_bit32(mmio_region_t base,
                                              ptrdiff_t offset,
                                              uint32_t bit_index);
+
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S.tpl
similarity index 83%
rename from hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S
rename to hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S.tpl
index 82776471..72d2b2e6 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S.tpl
@@ -1,164 +1,153 @@
-/* Copyright (c) 2017  SiFive Inc. All rights reserved.
- * Copyright (c) 2019  ETH Zürich and University of Bologna
- * Copyright (c) 2022 EPFL
- * This copyrighted material is made available to anyone wishing to use,
- * modify, copy, or redistribute it subject to the terms and conditions
- * of the FreeBSD License.   This program is distributed in the hope that
- * it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
- * including the implied warranties of MERCHANTABILITY or FITNESS FOR
- * A PARTICULAR PURPOSE.  A copy of this license is available at
- * http://www.opensource.org/licenses.
- */
-
-#include "x-heep.h"
-#include "core_v_mini_mcu.h"
-#include "soc_ctrl_regs.h"
-
-#define RAMSIZE_COPIEDBY_BOOTROM 2048
-
-/* Entry point for bare metal programs */
-.section .text.start
-.global _start
-.type _start, @function
-
-_start:
-/* initialize global pointer */
-.option push
-.option norelax
-1: auipc gp, %pcrel_hi(__global_pointer$)
-   addi  gp, gp, %pcrel_lo(1b)
-.option pop
-
-/* initialize stack pointer */
-   la sp, _sp
-
-/* set the frequency */
-   li a0, SOC_CTRL_START_ADDRESS
-   li a2, REFERENCE_CLOCK_Hz
-   sw a2, SOC_CTRL_SYSTEM_FREQUENCY_HZ_REG_OFFSET(a0)
-
-#ifdef EXTERNAL_CRTO
-   #include "external_crt0.S"
-#endif
-
-#ifdef FLASH_LOAD
-
-    call w25q128jw_init_crt0
-
-    // This assumes ram base address is 0x00000000 and the section .text stars from ram0 (in the first RAMSIZE_COPIEDBY_BOOTROM Byte)
-    li     s1, RAMSIZE_COPIEDBY_BOOTROM
-    li     s2, FLASH_MEM_START_ADDRESS
-
-    // copy the remaining (if any) text and data sections //
-    // Setup the in/out pointers and copy size knowing 1KiB as already been copied
-    mv     a0, s2 // src ptr (flash)
-    add   a0, a0, s1
-
-    la     a1, _etext
-    // Skip if everything has already been copied, and copy the data section
-    blt    a1, s1, _load_data_section
-
-    // copy size in bytes, i.e. _etext - RAMSIZE_COPIEDBY_BOOTROM
-    sub   a2, a1, s1
-
-    // dst ptr (ram)
-    mv     a1, s1
-
-    // copy the remaining data --> w25q128jw_read_standard(a0 is src addr, a1 is dest ptr data, a2 is length)
-
-    // this sub is redundat as we could have simply set a0 to RAMSIZE_COPIEDBY_BOOTROM+0x0,
-    // but like this is more readable as we set the FLASH address as memory mapped to FLASH_MEM_START_ADDRESS, and then remove the offset
-    // as required bz the w25q128jw_read_standard function
-    sub    a0,a0,s2
-    call w25q128jw_read_standard
-
-_load_data_section:
-    // src ptr
-    la     a0, _lma_data_start
-    // dst ptr
-    la     a1, __data_start
-    // copy size in bytes
-    la     a2, _lma_data_end
-    sub    a2, a2, a0
-
-    bltz   a2, _load_data_interleaved_section // dont do anything if you do not have data
-
-    sub    a0,a0,s2
-    call w25q128jw_read_standard
-
-
-_load_data_interleaved_section:
-    #ifdef HAS_MEMORY_BANKS_IL
-    // src ptr
-    la     a0, _lma_data_interleaved_start
-    // dst ptr
-    la     a1, __data_interleaved_start
-    // copy size in bytes
-    la     a2, _lma_data_interleaved_end
-    sub    a2, a2, a0
-
-    bltz   a2, _init_bss // dont do anything if you do not have interleaved data
-
-    sub    a0,a0,s2
-    call w25q128jw_read_standard
-    #endif
-
-#endif
-
-/* clear the bss segment */
-_init_bss:
-    la     a0, __bss_start
-    la     a2, __bss_end
-    sub    a2, a2, a0
-    li     a1, 0
-    call   memset
-
-#ifdef FLASH_EXEC
-/* copy initialized data sections from flash to ram (to be verified, copied from picosoc)*/
-    la a0, _sidata
-    la a1, _sdata
-    la a2, _edata
-    bge a1, a2, end_init_data
-    loop_init_data:
-    lw a3, 0(a0)
-    sw a3, 0(a1)
-    addi a0, a0, 4
-    addi a1, a1, 4
-    blt a1, a2, loop_init_data
-    end_init_data:
-#endif
-
-/* set vector table address and vectored mode */
-    la a0, __vector_start
-    ori a0, a0, 0x1
-    csrw mtvec, a0
-
-/* new-style constructors and destructors */
-    la a0, __libc_fini_array
-    call atexit
-    call __libc_init_array
-
-/* call main */
-    lw a0, 0(sp)                    /* a0 = argc */
-    addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
-    li a2, 0                        /* a2 = envp = NULL */
-    call main
-    tail exit
-
-.size  _start, .-_start
-
-.global _init
-.type   _init, @function
-.global _fini
-.type   _fini, @function
-_init:
-    call init
-_fini:
- /* These don't have to do anything since we use init_array/fini_array. Prevent
-    missing symbol error */
-    ret
-.size  _init, .-_init
-.size _fini, .-_fini
-
-
-
+/* Copyright (c) 2017  SiFive Inc. All rights reserved.
+ * Copyright (c) 2019  ETH Zürich and University of Bologna
+ * Copyright (c) 2022 EPFL
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the FreeBSD License.   This program is distributed in the hope that
+ * it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
+ * including the implied warranties of MERCHANTABILITY or FITNESS FOR
+ * A PARTICULAR PURPOSE.  A copy of this license is available at
+ * http://www.opensource.org/licenses.
+ */
+
+#include "x-heep.h"
+#include "core_v_mini_mcu.h"
+#include "soc_ctrl_regs.h"
+
+#define RAMSIZE_COPIEDBY_BOOTROM 2048
+
+/* Entry point for bare metal programs */
+.section .text.start
+.global _start
+.type _start, @function
+
+_start:
+/* initialize global pointer */
+.option push
+.option norelax
+1: auipc gp, %pcrel_hi(__global_pointer$)
+   addi  gp, gp, %pcrel_lo(1b)
+.option pop
+
+/* initialize stack pointer */
+   la sp, _sp
+
+/* set the frequency */
+   li a0, SOC_CTRL_START_ADDRESS
+   li a2, REFERENCE_CLOCK_Hz
+   sw a2, SOC_CTRL_SYSTEM_FREQUENCY_HZ_REG_OFFSET(a0)
+
+#ifdef EXTERNAL_CRTO
+   #include "external_crt0.S"
+#endif
+
+#ifdef FLASH_LOAD
+
+    call w25q128jw_init_crt0
+
+    // This assumes ram base address is 0x00000000 and the section .text stars from ram0 (in the first RAMSIZE_COPIEDBY_BOOTROM Byte)
+    li     s1, RAMSIZE_COPIEDBY_BOOTROM
+    li     s2, FLASH_MEM_START_ADDRESS
+
+    // copy the remaining (if any) text and data sections //
+    // Setup the in/out pointers and copy size knowing 1KiB as already been copied
+    mv     a0, s2 // src ptr (flash)
+    add   a0, a0, s1
+
+    la     a1, _etext
+    // Skip if everything has already been copied, and copy the data section
+    blt    a1, s1, _load_data_section
+
+    // copy size in bytes, i.e. _etext - RAMSIZE_COPIEDBY_BOOTROM
+    sub   a2, a1, s1
+
+    // dst ptr (ram)
+    mv     a1, s1
+
+    // copy the remaining data --> w25q128jw_read_standard(a0 is src addr, a1 is dest ptr data, a2 is length)
+
+    // this sub is redundat as we could have simply set a0 to RAMSIZE_COPIEDBY_BOOTROM+0x0,
+    // but like this is more readable as we set the FLASH address as memory mapped to FLASH_MEM_START_ADDRESS, and then remove the offset
+    // as required bz the w25q128jw_read_standard function
+    sub    a0,a0,s2
+    call w25q128jw_read_standard
+
+% for i, section in enumerate(xheep.iter_linker_sections()):
+% if section.name != "code":
+_load_${section.name}_section:
+    // src ptr
+    la     a0, _lma_${section.name}_start
+    // dst ptr
+    la     a1, __${section.name}_start
+    // copy size in bytes
+    la     a2, _lma_${section.name}_end
+    sub    a2, a2, a0
+
+    bltz   a2, _load_${section.name}_section_end // dont do anything if you do not have something in ${section.name}
+
+    sub    a0,a0,s2
+    call w25q128jw_read_standard
+_load_${section.name}_section_end:
+
+% endif
+% endfor
+
+#endif
+
+/* clear the bss segment */
+_init_bss:
+    la     a0, __bss_start
+    la     a2, __bss_end
+    sub    a2, a2, a0
+    li     a1, 0
+    call   memset
+
+#ifdef FLASH_EXEC
+/* copy initialized data sections from flash to ram (to be verified, copied from picosoc)*/
+    la a0, _sidata
+    la a1, _sdata
+    la a2, _edata
+    bge a1, a2, end_init_data
+    loop_init_data:
+    lw a3, 0(a0)
+    sw a3, 0(a1)
+    addi a0, a0, 4
+    addi a1, a1, 4
+    blt a1, a2, loop_init_data
+    end_init_data:
+#endif
+
+/* set vector table address and vectored mode */
+    la a0, __vector_start
+    ori a0, a0, 0x1
+    csrw mtvec, a0
+
+/* new-style constructors and destructors */
+    la a0, __libc_fini_array
+    call atexit
+    call __libc_init_array
+
+/* call main */
+    lw a0, 0(sp)                    /* a0 = argc */
+    addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
+    li a2, 0                        /* a2 = envp = NULL */
+    call main
+    tail exit
+
+.size  _start, .-_start
+
+.global _init
+.type   _init, @function
+.global _fini
+.type   _fini, @function
+_init:
+    call init
+_fini:
+ /* These don't have to do anything since we use init_array/fini_array. Prevent
+    missing symbol error */
+    ret
+.size  _init, .-_init
+.size _fini, .-_fini
+
+
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors.S b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors.S
index f6a805c6..8e573eef 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors.S
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors.S
@@ -126,39 +126,13 @@ new vector table (which is at mtvec) */
 
 .section .text.vecs
 /* exception handling */
+.globl __no_irq_handler
 __no_irq_handler:
 	la a0, no_exception_handler_msg
 	jal ra, puts
 	j __no_irq_handler
 
-
-sw_irq_handler:
-	csrr t0, mcause
-	slli t0, t0, 1  /* shift off the high bit */
-	srli t0, t0, 1
-	li t1, 2
-	beq t0, t1, handle_illegal_insn
-	li t1, 11
-	beq t0, t1, handle_ecall
-	li t1, 3
-	beq t0, t1, handle_ebreak
-	j handle_unknown
-
-handle_ecall:
-	la a0, ecall_msg
-	jal ra, puts
-	j end_handler
-
-handle_ebreak:
-	la a0, ebreak_msg
-	jal ra, puts
-	j end_handler
-
-handle_illegal_insn:
-	la a0, illegal_insn_msg
-	jal ra, puts
-	j end_handler
-
+.globl handle_unknown
 handle_unknown:
 	la a0, unknown_msg
 	jal ra, puts
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors_freertos.S b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors_freertos.S
index 3596dc18..c4586b30 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors_freertos.S
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/vectors_freertos.S
@@ -132,33 +132,6 @@ __no_irq_handler:
 	jal ra, puts
 	j __no_irq_handler
 
-sw_irq_handler:
-	csrr t0, mcause
-	slli t0, t0, 1  /* shift off the high bit */
-	srli t0, t0, 1
-	li t1, 2
-	beq t0, t1, handle_illegal_insn
-	li t1, 11
-	beq t0, t1, handle_ecall
-	li t1, 3
-	beq t0, t1, handle_ebreak
-	j handle_unknown
-
-handle_ecall:
-	la a0, ecall_msg
-	jal ra, puts
-	j end_handler
-
-handle_ebreak:
-	la a0, ebreak_msg
-	jal ra, puts
-	j end_handler
-
-handle_illegal_insn:
-	la a0, illegal_insn_msg
-	jal ra, puts
-	j end_handler
-
 handle_unknown:
 	la a0, unknown_msg
 	jal ra, puts
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
index d0b977d2..52097770 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
@@ -31,6 +31,11 @@
 /**                                                                        **/
 /****************************************************************************/
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif // __cplusplus
+
 #include "dma.h"
 
 /* To manage addresses. */
@@ -57,11 +62,6 @@
  */
 #define DMA_CSR_REG_MIE_MASK (( 1 << 19 ) | (1 << 11 ) ) // @ToDo Add definitions for this 19 and 11
 
-/**
- * Size of a register of 32 bits.
- */
-#define DMA_REGISTER_SIZE_BYTES sizeof(int)
-
 /**
  * Mask to determine if an address is multiple of 4 (Word aligned).
  */
@@ -165,36 +165,49 @@ static inline uint8_t get_misalignment_b(   uint8_t         *p_ptr,
  * @retval 1 There is an outbound.
  * @retval 0 There is NOT an outbound.
  */
-static inline uint8_t is_region_outbound(   uint8_t  *p_start,
+static inline uint8_t is_region_outbound_1D(   uint8_t  *p_start,
                                             uint8_t  *p_end,
                                             uint32_t p_type,
                                             uint32_t p_size_du,
                                             uint32_t p_inc_du );
 
 /**
- * @brief Writes a given value into the specified register. Its operation
- * mimics that of bitfield_field32_write(), but does not require the use of
- * a field structure, that is not always provided in the _regs.h file.
- * @param p_val The value to be written.
- * @param p_offset The register's offset from the peripheral's base address
- *  where the target register is located.
- * @param p_mask The variable's mask to only modify its bits inside the whole
- * register.
- * @param p_sel The selection index (i.e. From which bit inside the register
- * the value is to be written).
+ * @brief Determines whether a given region will fit before the end of an
+ * environment with a 2D transaction.
+ * @param p_start Pointer to the beginning of the region.
+ * @param p_end Pointer to the last byte of the environment.
+ * @param p_type The data type to be transferred.
+ * @param p_size_du The number of data units to be transferred. Must be
+ * non-zero.
+ * @param p_inc_du The size in data units of each increment.
+ * @retval 1 There is an outbound.
+ * @retval 0 There is NOT an outbound.
  */
-static inline void write_register(  uint32_t p_val,
-                                    uint32_t p_offset,
-                                    uint32_t p_mask,
-                                    uint8_t  p_sel );
+static inline uint8_t is_region_outbound_2D(   uint8_t  *p_start,
+                                            uint8_t  *p_end,
+                                            uint32_t p_type,
+                                            uint32_t p_size_d1_du,
+                                            uint32_t p_size_d2_du,
+                                            uint32_t p_inc_d1_du,
+                                            uint32_t p_inc_d2_du );
 
+/**
+ * @brief Analyzes a target to determine the size of its D1 increment (in bytes).
+ * @param p_tgt A pointer to the target to analyze.
+ * @param channel The channel to use as target.
+ * @return The number of bytes of the increment.
+ */
+static inline uint32_t get_increment_b_1D( dma_target_t * p_tgt,
+                                    uint8_t channel );
 
 /**
- * @brief Analyzes a target to determine the size of its increment (in bytes).
+ * @brief Analyzes a target to determine the size of its D2 increment (in bytes).
  * @param p_tgt A pointer to the target to analyze.
+ * @param channel The channel to use as target.
  * @return The number of bytes of the increment.
  */
-static inline uint32_t get_increment_b( dma_target_t * p_tgt );
+static inline uint32_t get_increment_b_2D( dma_target_t * p_tgt,
+                                    uint8_t channel  );
 
 
 /****************************************************************************/
@@ -210,10 +223,10 @@ static inline uint32_t get_increment_b( dma_target_t * p_tgt );
 /****************************************************************************/
 
 /**
- * Control Block (CB) of the DMA peripheral.
+ * Control Block (CB) of a single DMA channel.
  * Has variables and constant necessary/useful for its control.
  */
-static struct
+typedef struct
 {
     /**
     * Pointer to the transaction to be performed.
@@ -232,7 +245,14 @@ static struct
      */
     dma *peri;
 
-}dma_cb;
+}dma_ch_cb;
+
+/* Allocate the channel's memory space */
+static dma_ch_cb dma_subsys_per[DMA_CH_NUM];
+
+/* High priority interrupts counters */
+uint16_t dma_hp_tr_intr_counter = 0;
+uint16_t dma_hp_win_intr_counter = 0;
 
 
 /****************************************************************************/
@@ -243,45 +263,130 @@ static struct
 
 void handler_irq_dma(uint32_t id)
 {
-    /*
-     * Call the weak implementation provided in this module,
+    /* 
+     * Find out which channel raised the interrupt and call
+     * either the weak implementation provided in this module,
      * or the non-weak implementation.
      */
-    dma_intr_handler_window_done();
+
+    for (int i = 0; i < DMA_CH_NUM; i++)
+    {
+        if (dma_subsys_per[i].peri->WINDOW_IFR == 1)
+        {
+            dma_intr_handler_window_done(i);
+
+             #ifdef DMA_HP_INTR_INDEX
+            /* 
+             * If the channel that raised the interrupt is among the high priority channels,
+             * return to break the loop. 
+             */
+            #ifdef DMA_NUM_HP_INTR
+            if (i <= DMA_HP_INTR_INDEX && dma_hp_win_intr_counter < DMA_NUM_HP_INTR)
+            {
+                dma_hp_win_intr_counter++;
+                return;
+            } else if (i > DMA_HP_INTR_INDEX)
+            {
+                dma_hp_win_intr_counter = 0;
+            }
+
+            #else
+
+            if (i <= DMA_HP_INTR_INDEX)
+            {
+                return;
+            }
+            #endif
+
+            #endif
+        }
+    }
+    return;
 }
 
 void fic_irq_dma(void)
 {
-    /* The flag is raised so the waiting loop can be broken.*/
-    dma_cb.intrFlag = 1;
-
-    /*
-     * Call the weak implementation provided in this module,
+    /* 
+     * Find out which channel raised the interrupt and call
+     * either the weak implementation provided in this module,
      * or the non-weak implementation.
      */
-    dma_intr_handler_trans_done();
+    
+    for (int i = 0; i < DMA_CH_NUM; i++)
+    {
+        if (dma_subsys_per[i].peri->TRANSACTION_IFR == 1)
+        {
+            dma_subsys_per[i].intrFlag = 1;
+            dma_intr_handler_trans_done(i);
+
+            #ifdef DMA_HP_INTR_INDEX
+            /* 
+             * If the channel that raised the interrupt is among the high priority channels,
+             * return to break the loop. 
+             */
+            #ifdef DMA_NUM_HP_INTR
+            if (i <= DMA_HP_INTR_INDEX && dma_hp_tr_intr_counter < DMA_NUM_HP_INTR)
+            {
+                dma_hp_tr_intr_counter++;
+                return;
+            }
+            else if (i > DMA_HP_INTR_INDEX)
+            {
+                dma_hp_tr_intr_counter = 0;
+            }
+
+            #else
+
+            if (i <= DMA_HP_INTR_INDEX)
+            {
+                return;
+            }
+            #endif
+
+            #endif
+        }
+    }
+    return;
 }
 
-void dma_init( dma *peri )
+void dma_init( dma *dma_peri )
 {
     /*
      * If a DMA peripheral was provided, use that one, otherwise use the
      * integrated one.
      */
-    dma_cb.peri = peri ? peri : dma_peri;
-
-    /* Clear the loaded transaction */
-    dma_cb.trans = NULL;
-    /* Clear all values in the DMA registers. */
-    dma_cb.peri->SRC_PTR       = 0;
-    dma_cb.peri->DST_PTR       = 0;
-    dma_cb.peri->SIZE          = 0;
-    dma_cb.peri->PTR_INC       = 0;
-    dma_cb.peri->SLOT          = 0;
-    dma_cb.peri->DATA_TYPE     = 0;
-    dma_cb.peri->MODE          = 0;
-    dma_cb.peri->WINDOW_SIZE   = 0;
-    dma_cb.peri->INTERRUPT_EN  = 0;
+
+    for (int i = 0; i < DMA_CH_NUM; i++)
+    {
+        dma_subsys_per[i].peri = dma_peri ? dma_peri : dma_peri(i);
+
+        /* Clear the loaded transaction */
+        dma_subsys_per[i].trans = NULL;
+
+        /* Clear all values in the DMA registers. */
+        dma_subsys_per[i].peri->SRC_PTR        = 0;
+        dma_subsys_per[i].peri->DST_PTR        = 0;
+        dma_subsys_per[i].peri->ADDR_PTR       = 0;
+        dma_subsys_per[i].peri->SIZE_D1        = 0;
+        dma_subsys_per[i].peri->SIZE_D2        = 0;
+        dma_subsys_per[i].peri->SRC_PTR_INC_D1 = 0;
+        dma_subsys_per[i].peri->SRC_PTR_INC_D2 = 0;
+        dma_subsys_per[i].peri->DST_PTR_INC_D1 = 0;
+        dma_subsys_per[i].peri->DST_PTR_INC_D2 = 0;
+        dma_subsys_per[i].peri->DIM_CONFIG     = 0;
+        dma_subsys_per[i].peri->DIM_INV        = 0;
+        dma_subsys_per[i].peri->SLOT           = 0;
+        dma_subsys_per[i].peri->SRC_DATA_TYPE  = 0;
+        dma_subsys_per[i].peri->DST_DATA_TYPE  = 0;
+        dma_subsys_per[i].peri->SIGN_EXT       = 0;
+        dma_subsys_per[i].peri->MODE           = 0;
+        dma_subsys_per[i].peri->WINDOW_SIZE    = 0;
+        dma_subsys_per[i].peri->PAD_TOP        = 0;
+        dma_subsys_per[i].peri->PAD_BOTTOM     = 0;
+        dma_subsys_per[i].peri->PAD_LEFT       = 0;
+        dma_subsys_per[i].peri->PAD_RIGHT      = 0;
+        dma_subsys_per[i].peri->INTERRUPT_EN   = 0;
+    }
 }
 
 dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
@@ -308,6 +413,14 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
     /* The checks request should be a valid request. */
     DMA_STATIC_ASSERT( p_check         < DMA_PERFORM_CHECKS__size,
                        "Check request not valid");
+    /* The padding should be a valid number */
+    DMA_STATIC_ASSERT( ((p_trans->pad_top_du >= 0 && p_trans->pad_top_du < 64) && 
+                        (p_trans->pad_bottom_du >= 0 && p_trans->pad_bottom_du < 64) && 
+                        (p_trans->pad_left_du >= 0 && p_trans->pad_left_du < 64) &&
+                        (p_trans->pad_right_du >= 0 && p_trans->pad_right_du < 64)), 
+                       "Padding not valid");
+    /* The dimensionality should be valid*/
+    DMA_STATIC_ASSERT( p_trans->dim < DMA_DIM_CONF__size, "Dimensionality not valid");
 
     /*
      * CHECK IF TARGETS HAVE ERRORS
@@ -335,6 +448,43 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
         return p_trans->flags;
     }
 
+    /*
+     * CHECK IF THERE ARE INCREMENTS INCONSISTENCIES
+     */
+
+    /*
+     * A transaction is considered 2D if the source and/or the destination has a 2D increment.
+     * e.g. It's possible to copy a 1x9 matrix to a 3x3 matrix or to copy a 3x3 matrix to a 1x9 one.
+     */
+
+    if (p_check)
+    {
+        // If the transaction is 2D, check that the D2 increment of the targets are non zero.
+        // If the transaction is 1D, check that the D2 increment of the targets are zero.
+        if((p_trans->dim == DMA_DIM_CONF_2D && (p_trans->src->inc_d2_du == 0 || p_trans->dst->inc_d2_du == 0)) ||
+           (p_trans->dim == DMA_DIM_CONF_1D && (p_trans->src->inc_d2_du != 0 || p_trans->dst->inc_d2_du != 0)))
+        {
+            p_trans->flags |= DMA_CONFIG_INCOMPATIBLE;
+            p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
+            return p_trans->flags;
+        }
+    }
+
+    /*
+     * CHECK IF THERE ARE PADDING INCONSISTENCIES
+     */
+
+    if (p_check)
+    {
+        // If the transaction is 1D, check that the top and bottom paddings are set to zero.
+        if((p_trans->dim == DMA_DIM_CONF_1D && (p_trans->pad_top_du != 0 || p_trans->pad_bottom_du != 0)))
+        {
+            p_trans->flags |= DMA_CONFIG_INCOMPATIBLE;
+            p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
+            return p_trans->flags;
+        }
+    }
+
     /*
      * CHECK IF THERE ARE TRIGGER INCONSISTENCIES
      */
@@ -387,12 +537,16 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
 
     /* The flags are cleaned in case the structure was used before.*/
     p_trans->flags = DMA_CONFIG_OK;
+
     /* The copy size of the source (in data units -of the source-) is
     transformed to bytes, to be used as default size.*/
     uint8_t dataSize_b = DMA_DATA_TYPE_2_SIZE(p_trans->src->type);
     p_trans->size_b = p_trans->src->size_du * dataSize_b;
-    /* By default, the source defines the data type.*/
-    p_trans->type = p_trans->src->type;
+    p_trans->size_d2_b = p_trans->src->size_d2_du * dataSize_b;
+
+    p_trans->src_type = p_trans->src->type;
+    p_trans->dst_type = p_trans->dst->type;
+
     /*
      * By default, the transaction increment is set to 0 and, if required,
      * it will be changed to 1 (in which case both src and dst will have an
@@ -416,12 +570,12 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
 
         if( p_trans->src->trig == DMA_TRIG_MEMORY )
         {
-            misalignment = get_misalignment_b( p_trans->src->ptr, p_trans->type );
+            misalignment = get_misalignment_b( p_trans->src->ptr, p_trans->src_type );
         }
 
         if( p_trans->dst->trig == DMA_TRIG_MEMORY )
         {
-            dstMisalignment = get_misalignment_b( p_trans->dst->ptr, p_trans->type );
+            dstMisalignment = get_misalignment_b( p_trans->dst->ptr, p_trans->dst_type );
         }
 
         p_trans->flags  |= ( misalignment ? DMA_CONFIG_SRC : DMA_CONFIG_OK );
@@ -507,27 +661,28 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
              * If realignment is allowed and there are no discontinuities,
              * a more granular data type is used according to the detected
              * misalignment in order to overcome it.
-             */
-            p_trans->type += misalignment;
-            /*
+             */ 
+            p_trans->dst_type = p_trans->dst_type + misalignment;
+
+           /*
              * Source and destination increment should now be of the size
              * of the data.
              * As increments are given in bytes, in both cases should be the
              * size of a data unit.
              */
-            p_trans->inc_b = DMA_DATA_TYPE_2_SIZE( p_trans->type );
+            p_trans->inc_b = DMA_DATA_TYPE_2_SIZE( p_trans->dst_type );
             /* The copy size does not change, as it is already stored in bytes.*/
         }
 
         /*
-         * CHECK IF SOURCE HAS SIZE 0
+         * CHECK IF SOURCE HAS ZERO SIZE(s)
          */
 
         /*
          * No further operations are done to prevent corrupting information
          * that could be useful for debugging purposes.
          */
-        if( p_trans->src->size_du == 0 )
+        if(p_trans->src->size_du == 0 || (p_trans->dim == DMA_DIM_CONF_2D && p_trans->src->size_d2_du == 0))
         {
             p_trans->flags |= DMA_CONFIG_SRC;
             p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
@@ -563,20 +718,23 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
          * that could be useful for debugging purposes.
          */
         uint8_t isEnv = (p_trans->dst->env != NULL);
-        uint8_t isOutb = is_region_outbound(
-                                    p_trans->dst->ptr,
-                                    p_trans->dst->env->end,
-                                    p_trans->type,
-                                    p_trans->src->size_du,
-                                    p_trans->dst->inc_du );
-        if( isEnv && isOutb )
-        {
-            p_trans->flags |= DMA_CONFIG_DST;
-            p_trans->flags |= DMA_CONFIG_OUTBOUNDS;
-            p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
-            return p_trans->flags;
-        }
 
+        if(isEnv) {
+            uint8_t isOutb = is_region_outbound_1D(
+                                        p_trans->dst->ptr,
+                                        p_trans->dst->env->end,
+                                        p_trans->dst_type,
+                                        p_trans->src->size_du,
+                                        p_trans->dst->inc_du );
+            if( isOutb )
+            {
+                p_trans->flags |= DMA_CONFIG_DST;
+                p_trans->flags |= DMA_CONFIG_OUTBOUNDS;
+                p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
+
+                return p_trans->flags;
+            }
+        }
         // @ToDo: It should also be checked that the destination is behind the
         // source if there will be overlap.
         // @ToDo: Consider if (when a destination target has no environment)
@@ -622,8 +780,9 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
     return p_trans->flags;
 }
 
-dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans )
+dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans)
 {
+    uint8_t channel = p_trans->channel;
     /*
      * CHECK FOR CRITICAL ERRORS
      */
@@ -635,7 +794,7 @@ dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans )
      */
     if( p_trans->flags & DMA_CONFIG_CRITICAL_ERROR )
     {
-        dma_cb.trans = NULL;
+        dma_subsys_per[channel].trans = NULL;
         return DMA_CONFIG_CRITICAL_ERROR;
     }
 
@@ -650,61 +809,138 @@ dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans )
      * until it has ended.
      * Transactions can still be validated in the meantime.
      */
-    if( !dma_is_ready() )
+    if( !dma_is_ready(channel) )
     {
         return DMA_CONFIG_TRANS_OVERRIDE;
     }
 
     /* Save the current transaction */
-    dma_cb.trans = p_trans;
+    dma_subsys_per[channel].trans = p_trans;
 
     /*
      * ENABLE/DISABLE INTERRUPTS
      */
 
     /*
-     * If the selected en event is polling, interrupts are disabled.
+     * If the selected end event is polling, interrupts are disabled.
      * Otherwise the mie.MEIE bit is set to one to enable machine-level
      * fast DMA interrupt.
      */
-    dma_cb.peri->INTERRUPT_EN = INTR_EN_NONE;
+    dma_subsys_per[channel].peri->INTERRUPT_EN = INTR_EN_NONE;
     CSR_CLEAR_BITS(CSR_REG_MIE, DMA_CSR_REG_MIE_MASK );
 
-    if( dma_cb.trans->end != DMA_TRANS_END_POLLING )
+    if( dma_subsys_per[channel].trans->end != DMA_TRANS_END_POLLING )
     {
-        /* Enable global interrupt for machine-level interrupts. */
+        /* Enable global interrupt. */
         CSR_SET_BITS(CSR_REG_MSTATUS, 0x8 );
-        /* @ToDo: What does this do? */
+        /* Enable machine-level fast interrupt. */
         CSR_SET_BITS(CSR_REG_MIE, DMA_CSR_REG_MIE_MASK );
 
-        dma_cb.peri->INTERRUPT_EN |= INTR_EN_TRANS_DONE;
+        /* Enable the transaction interrupt for the channel by setting the corresponding bit in Transaction IFR */
+        write_register(  
+                        0x1,
+                        DMA_INTERRUPT_EN_REG_OFFSET,
+                        0xffff,
+                        DMA_INTERRUPT_EN_TRANSACTION_DONE_BIT,
+                        dma_subsys_per[channel].peri
+                    );
 
         /* Only if a window is used should the window interrupt be set. */
         if( p_trans->win_du > 0 )
         {
-            dma_cb.peri->INTERRUPT_EN |= INTR_EN_WINDOW_DONE;
+            write_register(  
+                        0x1,
+                        DMA_INTERRUPT_EN_REG_OFFSET,
+                        0xffff,
+                        DMA_INTERRUPT_EN_WINDOW_DONE_BIT,
+                        dma_subsys_per[channel].peri
+                    );
         }
     }
 
+    /*
+     * SET THE PADDING
+     */
+
+    /*
+    * In the case of a 1D transaction with padding enabled, the DMA has to be configured to treat
+    * the transaction as a 2D one with a second dimension of 1 du and a second dimension increment of 1 du.
+    */
+
+    if (p_trans->dim == DMA_DIM_CONF_1D && (p_trans->pad_left_du != 0 || p_trans->pad_right_du != 0))
+    {
+        p_trans->dim = DMA_DIM_CONF_2D;
+        p_trans->size_d2_b = DMA_DATA_TYPE_2_SIZE( p_trans->dst_type );
+        p_trans->src->inc_d2_du = DMA_DATA_TYPE_2_SIZE( p_trans->dst_type );
+        
+        write_register( dma_subsys_per[channel].trans->pad_left_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+                        DMA_PAD_LEFT_REG_OFFSET,
+                        DMA_PAD_LEFT_PAD_MASK,
+                        DMA_PAD_LEFT_PAD_OFFSET,
+                        dma_subsys_per[channel].peri);
+
+        write_register( dma_subsys_per[channel].trans->pad_right_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+                        DMA_PAD_RIGHT_REG_OFFSET,
+                        DMA_PAD_RIGHT_PAD_MASK,
+                        DMA_PAD_RIGHT_PAD_OFFSET,
+                        dma_subsys_per[channel].peri);
+    }
+    else if (p_trans->dim == DMA_DIM_CONF_2D)
+    {
+        write_register( dma_subsys_per[channel].trans->pad_top_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+                        DMA_PAD_TOP_REG_OFFSET,
+                        DMA_PAD_TOP_PAD_MASK,
+                        DMA_PAD_TOP_PAD_OFFSET,
+                        dma_subsys_per[channel].peri);
+
+        write_register( dma_subsys_per[channel].trans->pad_bottom_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+                        DMA_PAD_BOTTOM_REG_OFFSET,
+                        DMA_PAD_BOTTOM_PAD_MASK,
+                        DMA_PAD_BOTTOM_PAD_OFFSET,
+                        dma_subsys_per[channel].peri);
+
+        write_register( dma_subsys_per[channel].trans->pad_left_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+                        DMA_PAD_LEFT_REG_OFFSET,
+                        DMA_PAD_LEFT_PAD_MASK,
+                        DMA_PAD_LEFT_PAD_OFFSET,
+                        dma_subsys_per[channel].peri);
+
+        write_register( dma_subsys_per[channel].trans->pad_right_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+                        DMA_PAD_RIGHT_REG_OFFSET,
+                        DMA_PAD_RIGHT_PAD_MASK,
+                        DMA_PAD_RIGHT_PAD_OFFSET,
+                        dma_subsys_per[channel].peri);
+    }
+
     /*
      * SET THE POINTERS
      */
-    dma_cb.peri->SRC_PTR = (uint32_t)dma_cb.trans->src->ptr;
+    dma_subsys_per[channel].peri->SRC_PTR = (uint32_t)dma_subsys_per[channel].trans->src->ptr;
 
-    if(dma_cb.trans->mode != DMA_TRANS_MODE_ADDRESS)
+    if(dma_subsys_per[channel].trans->mode != DMA_TRANS_MODE_ADDRESS)
     {
         /*
         Write to the destination pointers only if we are not in address mode,
         otherwise the destination address is read in a separate port in parallel with the data
         from the address port
         */
-        dma_cb.peri->DST_PTR = (uint32_t)dma_cb.trans->dst->ptr;
+        dma_subsys_per[channel].peri->DST_PTR = (uint32_t)dma_subsys_per[channel].trans->dst->ptr;
     }
     else
     {
-        dma_cb.peri->ADDR_PTR = (uint32_t)dma_cb.trans->src_addr->ptr;
+        dma_subsys_per[channel].peri->ADDR_PTR = (uint32_t)dma_subsys_per[channel].trans->src_addr->ptr;
     }
 
+    /*
+     * SET THE TRANSPOSITION MODE
+     */
+
+    write_register(dma_subsys_per[channel].trans->dim_inv,
+                   DMA_DIM_INV_REG_OFFSET,
+                   0x1 << DMA_DIM_INV_SEL_BIT,
+                   DMA_DIM_INV_SEL_BIT,
+                   dma_subsys_per[channel].peri);
+
     /*
      * SET THE INCREMENTS
      */
@@ -717,66 +953,124 @@ dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans )
      * In that case, a increment of 0 is necessary.
      * In case of DMA Address mode transaction, the dst pointer is ignored
      * as the values read from the second port are instead used.
+     * In case of a 2D DMA transaction, the second dimension increment is set.
      */
 
-    write_register(  get_increment_b( dma_cb.trans->src ),
-                    DMA_PTR_INC_REG_OFFSET,
-                    DMA_PTR_INC_SRC_PTR_INC_MASK,
-                    DMA_PTR_INC_SRC_PTR_INC_OFFSET );
+    write_register(  get_increment_b_1D( dma_subsys_per[channel].trans->src, channel),
+                    DMA_SRC_PTR_INC_D1_REG_OFFSET,
+                    DMA_SRC_PTR_INC_D1_INC_MASK,
+                    DMA_SRC_PTR_INC_D1_INC_OFFSET,
+                    dma_subsys_per[channel].peri);
 
-
-
-    if(dma_cb.trans->mode != DMA_TRANS_MODE_ADDRESS)
+    if(dma_subsys_per[channel].trans->dim == DMA_DIM_CONF_2D)
     {
-        write_register(  get_increment_b( dma_cb.trans->dst ),
-                        DMA_PTR_INC_REG_OFFSET,
-                        DMA_PTR_INC_DST_PTR_INC_MASK,
-                        DMA_PTR_INC_DST_PTR_INC_OFFSET );
+        write_register(  get_increment_b_2D( dma_subsys_per[channel].trans->src, channel),
+                        DMA_SRC_PTR_INC_D2_REG_OFFSET,
+                        DMA_SRC_PTR_INC_D2_INC_MASK,
+                        DMA_SRC_PTR_INC_D2_INC_OFFSET,
+                        dma_subsys_per[channel].peri );
     }
 
+    if(dma_subsys_per[channel].trans->mode != DMA_TRANS_MODE_ADDRESS)
+    {
+        write_register(  get_increment_b_1D( dma_subsys_per[channel].trans->dst, channel),
+                        DMA_DST_PTR_INC_D1_REG_OFFSET,
+                        DMA_DST_PTR_INC_D1_INC_MASK,
+                        DMA_DST_PTR_INC_D1_INC_OFFSET,
+                        dma_subsys_per[channel].peri );
+        
+        if(dma_subsys_per[channel].trans->dim == DMA_DIM_CONF_2D)
+        {
+            write_register(  get_increment_b_2D( dma_subsys_per[channel].trans->dst, channel),
+                        DMA_DST_PTR_INC_D2_REG_OFFSET,
+                        DMA_DST_PTR_INC_D2_INC_MASK,
+                        DMA_DST_PTR_INC_D2_INC_OFFSET,
+                        dma_subsys_per[channel].peri );
+        }
+    }
 
     /*
      * SET THE OPERATION MODE AND WINDOW SIZE
      */
 
-    dma_cb.peri->MODE = dma_cb.trans->mode;
+    dma_subsys_per[channel].peri->MODE = dma_subsys_per[channel].trans->mode;
     /* The window size is set to the transaction size if it was set to 0 in
     order to disable the functionality (it will never be triggered). */
 
-    dma_cb.peri->WINDOW_SIZE =   dma_cb.trans->win_du
-                            ? dma_cb.trans->win_du
-                            : dma_cb.trans->size_b;
+    dma_subsys_per[channel].peri->WINDOW_SIZE =   dma_subsys_per[channel].trans->win_du
+                            ? dma_subsys_per[channel].trans->win_du
+                            : dma_subsys_per[channel].trans->size_b;
+
+    /* 
+     * SET THE DIMENSIONALITY
+     */
+    write_register(  dma_subsys_per[channel].trans->dim,
+                    DMA_DIM_CONFIG_REG_OFFSET,
+                    0x1,
+                    DMA_DIM_CONFIG_DMA_DIM_BIT,
+                    dma_subsys_per[channel].peri );
+
+    /*
+     * SET THE SIGN EXTENSION BIT
+     */
+    write_register( dma_subsys_per[channel].trans->sign_ext,
+                    DMA_SIGN_EXT_REG_OFFSET,
+                    0x1 << DMA_SIGN_EXT_SIGNED_BIT,
+                    DMA_SIGN_EXT_SIGNED_BIT,
+                    dma_subsys_per[channel].peri  );
+
+
+    /*
+     * SET THE SIGN EXTENSION BIT
+     */
+    write_register( dma_subsys_per[channel].trans->sign_ext,
+                    DMA_SIGN_EXT_REG_OFFSET,
+                    0x1 << DMA_SIGN_EXT_SIGNED_BIT,
+                    DMA_SIGN_EXT_SIGNED_BIT,
+                    dma_subsys_per[channel].peri  );
+
 
     /*
      * SET TRIGGER SLOTS AND DATA TYPE
      */
-    write_register(  dma_cb.trans->src->trig,
+    write_register(  dma_subsys_per[channel].trans->src->trig,
                     DMA_SLOT_REG_OFFSET,
                     DMA_SLOT_RX_TRIGGER_SLOT_MASK,
-                    DMA_SLOT_RX_TRIGGER_SLOT_OFFSET );
+                    DMA_SLOT_RX_TRIGGER_SLOT_OFFSET,
+                    dma_subsys_per[channel].peri );
 
-    write_register(  dma_cb.trans->dst->trig,
+    write_register(  dma_subsys_per[channel].trans->dst->trig,
                     DMA_SLOT_REG_OFFSET,
                     DMA_SLOT_TX_TRIGGER_SLOT_MASK,
-                    DMA_SLOT_TX_TRIGGER_SLOT_OFFSET );
-
-    write_register(  dma_cb.trans->type,
-                    DMA_DATA_TYPE_REG_OFFSET,
-                    DMA_DATA_TYPE_DATA_TYPE_MASK,
-                    DMA_SELECTION_OFFSET_START );
+                    DMA_SLOT_TX_TRIGGER_SLOT_OFFSET,
+                    dma_subsys_per[channel].peri );
+
+    write_register(  dma_subsys_per[channel].trans->dst_type,
+                    DMA_DST_DATA_TYPE_REG_OFFSET,
+                    DMA_DST_DATA_TYPE_DATA_TYPE_MASK,
+                    DMA_SELECTION_OFFSET_START,
+                    dma_subsys_per[channel].peri  );
+    
+    write_register(  dma_subsys_per[channel].trans->src_type,
+                    DMA_SRC_DATA_TYPE_REG_OFFSET,
+                    DMA_SRC_DATA_TYPE_DATA_TYPE_MASK,
+                    DMA_SELECTION_OFFSET_START,
+                    dma_subsys_per[channel].peri );
 
     return DMA_CONFIG_OK;
 }
 
-dma_config_flags_t dma_launch( dma_trans_t *p_trans )
+dma_config_flags_t dma_launch( dma_trans_t *p_trans)
 {
+    uint8_t channel = p_trans->channel;
+
     /*
      * Make sure that the loaded transaction is the intended transaction.
      * If the loaded trans was NULL'd, then this the transaction is never
      * launched.
      */
     if(     ( p_trans == NULL )
-        ||  ( dma_cb.trans != p_trans ) ) // @ToDo: Check per-element.
+        ||  ( dma_subsys_per[channel].trans != p_trans ) ) // @ToDo: Check per-element.
     {
         return DMA_CONFIG_CRITICAL_ERROR;
     }
@@ -792,7 +1086,7 @@ dma_config_flags_t dma_launch( dma_trans_t *p_trans )
      * until it has ended.
      * Transactions can still be validated in the meantime.
      */
-    if( !dma_is_ready() )
+    if( !dma_is_ready(channel) )
     {
         return DMA_CONFIG_TRANS_OVERRIDE;
     }
@@ -801,58 +1095,74 @@ dma_config_flags_t dma_launch( dma_trans_t *p_trans )
      * This has to be done prior to writing the register because otherwise
      * the interrupt could arrive before it is lowered.
      */
-    dma_cb.intrFlag = 0;
+    dma_subsys_per[channel].intrFlag = 0;
 
-    /* Load the size and start the transaction. */
-    dma_cb.peri->SIZE = dma_cb.trans->size_b;
+    /* Load the size(s) and start the transaction. */
 
+    if(dma_subsys_per[channel].trans->dim == DMA_DIM_CONF_2D)
+    {
+        write_register( dma_subsys_per[channel].trans->size_d2_b,
+                        DMA_SIZE_D2_REG_OFFSET,
+                        DMA_SIZE_D2_SIZE_MASK,
+                        DMA_SIZE_D2_SIZE_OFFSET,
+                        dma_subsys_per[channel].peri
+                      );
+    }
+
+    write_register( dma_subsys_per[channel].trans->size_b,
+                    DMA_SIZE_D1_REG_OFFSET,
+                    DMA_SIZE_D1_SIZE_MASK,
+                    DMA_SIZE_D1_SIZE_OFFSET,
+                    dma_subsys_per[channel].peri
+    ); 
     /*
      * If the end event was set to wait for the interrupt, the dma_launch
      * will not return until the interrupt arrives.
      */
+
+    
     while(    p_trans->end == DMA_TRANS_END_INTR_WAIT
-          && ( dma_cb.intrFlag != 0 ) ) { // @ToDo: add a label for this 0
-        wait_for_interrupt();
+          && ( dma_subsys_per[channel].intrFlag != 0x0 ) ) {
+            wait_for_interrupt();
     }
 
     return DMA_CONFIG_OK;
 }
 
-
-__attribute__((optimize("O0"))) uint32_t dma_is_ready(void)
+__attribute__((optimize("O0"))) uint32_t dma_is_ready(uint8_t channel)
 {
     /* The transaction READY bit is read from the status register*/
-    uint32_t ret = ( dma_cb.peri->STATUS & (1<<DMA_STATUS_READY_BIT) );
+    uint32_t ret = ( dma_subsys_per[channel].peri->STATUS & (1<<DMA_STATUS_READY_BIT) );
     return ret;
 }
 /* @ToDo: Reconsider this decision.
  * In case a return wants to be forced in case of an error, there are 2
  * alternatives:
  *    1) Consider any value != 0 to be a valid 1 using a LOGIC AND:
- *  return ( 1 && dma_cb.peri->DONE );
+ *  return ( 1 && dma_subsys_per[channel].peri->DONE );
  *    2) Consider only the LSB == 1 to be a valid 1 using a BITWISE AND.
- *  return ( 1 &  dma_cb.peri->DONE );
+ *  return ( 1 &  dma_subsys_per[channel].peri->DONE );
  * This would be fixed if the DONE register was a 1 bit field.
  */
 
 
-uint32_t dma_get_window_count()
+uint32_t dma_get_window_count(uint8_t channel)
 {
-    return dma_cb.peri->WINDOW_COUNT;
+    return dma_subsys_per[channel].peri->WINDOW_COUNT;
 }
 
 
-void dma_stop_circular()
+void dma_stop_circular(uint8_t channel)
 {
     /*
      * The DMA finishes the current transaction before and does not start
      * a new one.
      */
-    dma_cb.peri->MODE = DMA_TRANS_MODE_SINGLE;
+    dma_subsys_per[channel].peri->MODE = DMA_TRANS_MODE_SINGLE;
 }
 
 
-__attribute__((weak, optimize("O0"))) void dma_intr_handler_trans_done()
+__attribute__((weak, optimize("O0"))) void dma_intr_handler_trans_done(uint8_t channel)
 {
     /*
      * The DMA transaction has finished!
@@ -863,7 +1173,7 @@ __attribute__((weak, optimize("O0"))) void dma_intr_handler_trans_done()
      */
 }
 
-__attribute__((weak, optimize("O0"))) void dma_intr_handler_window_done()
+__attribute__((weak, optimize("O0"))) void dma_intr_handler_window_done(uint8_t channel)
 {
     /*
      * The DMA has copied another window.
@@ -901,14 +1211,19 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
      */
 
     /* Increment can be 0 when a trigger is used. */
-    DMA_STATIC_ASSERT( p_tgt->inc_du   >= 0 , "Increment not valid");
+    DMA_STATIC_ASSERT( p_tgt->inc_du   >= 0  &&  p_tgt->inc_du < 64 , "Increment not valid");
+    /* Increment on D2 has to be 0 for 1D operations */
+    DMA_STATIC_ASSERT( p_tgt->inc_d2_du  >= 0  &&  p_tgt->inc_d2_du < 4194304 , "Increment d2 not valid");
     /* The size could be 0 if the target is only going to be used as a
     destination. */
-    DMA_STATIC_ASSERT( p_tgt->size_du  >=  0 , "Size not valid");
+    DMA_STATIC_ASSERT( p_tgt->size_du  >= 0 && p_tgt->size_du  < 65536 , "Size not valid");
+    /* The size can be 0 or 1 if the target is involved in a 1D padded transaction */
+    DMA_STATIC_ASSERT( p_tgt->size_d2_du >= 0 && p_tgt->size_du  < 65536  , "Size d2 not valid");
     /* The data type must be a valid type */
-    DMA_STATIC_ASSERT( p_tgt->type     < DMA_DATA_TYPE__size , "Type not valid");
+    DMA_STATIC_ASSERT( p_tgt->type     < DMA_DATA_TYPE__size , "Source type not valid");
     /* The trigger must be among the valid trigger values. */
     DMA_STATIC_ASSERT( p_tgt->trig     < DMA_TRIG__size , "Trigger not valid");
+    
 
     /*
      * INTEGRITY CHECKS
@@ -923,7 +1238,6 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
     {
         /* Check if the environment was properly formed.*/
         flags |= validate_environment( p_tgt->env );
-
         /*
          * Check if the target selected size goes beyond the boundaries of
          * the environment.
@@ -931,7 +1245,7 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
          */
         if( p_tgt->size_du != 0 )
         {
-            uint8_t isOutb = is_region_outbound(  p_tgt->ptr,
+            uint8_t isOutb = is_region_outbound_1D(  p_tgt->ptr,
                                           p_tgt->env->end,
                                           p_tgt->type,
                                           p_tgt->size_du,
@@ -941,6 +1255,21 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
                 flags |= DMA_CONFIG_OUTBOUNDS;
             }
         }
+        /* Do the same but for 2D case */
+        if( p_tgt->size_d2_du != 0 )
+        {
+            uint8_t isOutb = is_region_outbound_2D(  p_tgt->ptr,
+                                          p_tgt->env->end,
+                                          p_tgt->type,
+                                          p_tgt->size_du,
+                                          p_tgt->size_d2_du,
+                                          p_tgt->inc_du,
+                                          p_tgt->inc_d2_du);
+            if( isOutb )
+            {
+                flags |= DMA_CONFIG_OUTBOUNDS;
+            }
+        }
 
         /* Check if the target starts before the environment starts. */
         uint8_t beforeEnv = ( p_tgt->ptr < p_tgt->env->start );
@@ -1071,7 +1400,7 @@ static inline uint8_t get_misalignment_b(   uint8_t         *p_ptr,
     return misalignment;
 }
 
-static inline uint8_t is_region_outbound(   uint8_t  *p_start,
+static inline uint8_t is_region_outbound_1D(   uint8_t  *p_start,
                                             uint8_t  *p_end,
                                             uint32_t p_type,
                                             uint32_t p_size_du,
@@ -1093,37 +1422,34 @@ static inline uint8_t is_region_outbound(   uint8_t  *p_start,
    */
     uint32_t affectedUnits      = ( p_size_du - 1 ) * p_inc_du + 1;
     uint32_t rangeSize          = DMA_DATA_TYPE_2_SIZE(p_type) * affectedUnits;
-    uint32_t lasByteInsideRange = (uint32_t)p_start + rangeSize -1;
-    return ( p_end < lasByteInsideRange );
+    uint32_t lastByteInsideRange = (uint32_t)p_start + rangeSize -1;
+    return ( p_end < lastByteInsideRange );
     // Size is be guaranteed to be non-zero before calling this function.
 }
 
-/* @ToDo: Consider changing the "mask" parameter for a bitfield definition
-(see dma_regs.h) */
-static inline void write_register( uint32_t  p_val,
-                                  uint32_t  p_offset,
-                                  uint32_t  p_mask,
-                                  uint8_t   p_sel )
+static inline uint8_t is_region_outbound_2D(   uint8_t  *p_start,
+                                            uint8_t  *p_end,
+                                            uint32_t p_type,
+                                            uint32_t p_size_d1_du,
+                                            uint32_t p_size_d2_du,
+                                            uint32_t p_inc_d1_du,
+                                            uint32_t p_inc_d2_du )
 {
-    /*
-     * The index is computed to avoid needing to access the structure
-     * as a structure.
-     */
-    uint8_t index = p_offset / DMA_REGISTER_SIZE_BYTES;
-    /*
-     * An intermediate variable "value" is used to prevent writing twice into
-     * the register.
-     */
-    uint32_t value  =  (( uint32_t * ) dma_cb.peri ) [ index ];
-    value           &= ~( p_mask << p_sel );
-    value           |= (p_val & p_mask) << p_sel;
-    (( uint32_t * ) dma_cb.peri ) [ index ] = value;
+  /* 
+   * If the environment ends before the last affected byte, then there is
+   * outbound writing and the function returns 1.
+   */
 
-// @ToDo: mmio_region_write32(dma->base_addr, (ptrdiff_t)(DMA_SLOT_REG_OFFSET), (tx_slot_mask << DMA_SLOT_TX_TRIGGER_SLOT_OFFSET) + rx_slot_mask)
+    uint32_t affectedUnits      = (( p_size_d1_du - 1 ) * p_inc_d1_du + 1) * (p_size_d2_du) + p_inc_d2_du * (p_size_d2_du - 1);
+    uint32_t rangeSize          = DMA_DATA_TYPE_2_SIZE(p_type) * affectedUnits;
+    uint32_t lastByteInsideRange = (uint32_t)p_start + rangeSize -1;
+    return ( p_end < lastByteInsideRange );
 
+    // Size is be guaranteed to be non-zero before calling this function.
 }
 
-static inline uint32_t get_increment_b( dma_target_t * p_tgt )
+static inline uint32_t get_increment_b_1D( dma_target_t * p_tgt,
+                                           uint8_t        channel)
 {
     uint32_t inc_b = 0;
     /* If the target uses a trigger, the increment remains 0. */
@@ -1133,7 +1459,7 @@ static inline uint32_t get_increment_b( dma_target_t * p_tgt )
          * If the transaction increment has been overriden (due to
          * misalignments), then that value is used (it's always set to 1).
          */
-        inc_b = dma_cb.trans->inc_b;
+        inc_b = dma_subsys_per[channel].trans->inc_b;
 
         /*
         * Otherwise, the target-specific increment is used transformed into
@@ -1141,15 +1467,46 @@ static inline uint32_t get_increment_b( dma_target_t * p_tgt )
         */
         if( inc_b == 0 )
         {
-            uint8_t dataSize_b = DMA_DATA_TYPE_2_SIZE( dma_cb.trans->type );
+            uint8_t dataSize_b = DMA_DATA_TYPE_2_SIZE( p_tgt->type );
             inc_b = ( p_tgt->inc_du * dataSize_b );
         }
     }
     return inc_b;
 }
 
+static inline uint32_t get_increment_b_2D( dma_target_t * p_tgt,
+                                           uint8_t channel )
+{
+    uint32_t inc_b = 0;
+    /* If the target uses a trigger, the increment remains 0. */
+    if(  p_tgt->trig  == DMA_TRIG_MEMORY )
+    {
+        /*
+         * If the transaction increment has been overriden (due to
+         * misalignments), then that value is used (it's always set to 1).
+         */
+        inc_b = dma_subsys_per[channel].trans->inc_b;
+
+        /*
+        * Otherwise, the target-specific increment is used transformed into
+        * bytes).
+        */
+        if( inc_b == 0 )
+        {
+            uint8_t dataSize_b = DMA_DATA_TYPE_2_SIZE( p_tgt->type );
+            inc_b = ( p_tgt->inc_d2_du * dataSize_b );
+        }
+    }
+    return inc_b;
+}
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
 /****************************************************************************/
 /**                                                                        **/
 /*                                 EOF                                      */
 /**                                                                        **/
-/****************************************************************************/
+/****************************************************************************/
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
index 85ee6475..ad87434a 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
@@ -68,6 +68,36 @@
 #define DMA_SPI_FLASH_TX_SLOT     0x08
 #define DMA_I2S_RX_SLOT           0x10
 
+#define DMA_INT_TR_START     0x0
+
+/* 
+ * For multichannel configurations, a priority mechanism can be set up to allow the interrupt handler 
+ * to prioritize a set of channels.
+ * 
+ * In order to enable this feature, the user must define DMA_HP_INTR_INDEX.
+ * 
+ * When an interrupt is raised, the handler will loop through the channels. If the channel that
+ * raised the interrupt is part of the high priority channels (index <= DMA_HP_INTR_INDEX), 
+ * it will call the actual handler and exit the loop. 
+ * It this way, low index channels will always be serviced first.
+ * 
+ * However, this feature could cause low priority channels to never be serviced if the high priority
+ * interrupts are raised at a faster frequency.
+ * In order to avoid this, the user can define DMA_NUM_HP_INTR (uint16_t).
+ * This macro puts a limit to the number of consecutive interrupts raised by high priority channels 
+ * that can trigger a "return".
+ * If N = DMA_NUM_HP_INTR interrupts are raised by high priority channels, the N+1 interrupt will be
+ * serviced and then no "return" will be triggered, thus allowing the handler's loop to continue and 
+ * low priority channels to be serviced, if necessary.
+ * 
+ * The priority mechanism is applied to both transaction done and window done interrupts, if enabled.
+ * Separate counters are used for each type of interrupt.
+ */
+
+//#define DMA_HP_INTR_INDEX 0
+//#define DMA_NUM_HP_INTR 5
+
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -77,6 +107,8 @@ extern "C" {
  */
 #define DMA_DATA_TYPE_2_SIZE(type) (0b00000100 >> (type) )
 
+#define DMA_SELECTION_OFFSET_START 0
+
 /****************************************************************************/
 /**                                                                        **/
 /**                       TYPEDEFS AND STRUCTURES                          **/
@@ -118,11 +150,11 @@ typedef enum
  */
 typedef enum
 {
-    DMA_DATA_TYPE_WORD      = DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD,/*!<
+    DMA_DATA_TYPE_WORD      = DMA_SRC_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD,/*!<
     Word      = 4 bytes = 32 bits */
-    DMA_DATA_TYPE_HALF_WORD = DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD,/*!<
+    DMA_DATA_TYPE_HALF_WORD = DMA_SRC_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD,/*!<
     Half Word = 2 bytes = 16 bits */
-    DMA_DATA_TYPE_BYTE      = DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD,/*!<
+    DMA_DATA_TYPE_BYTE      = DMA_SRC_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD,/*!<
      Byte      = 1 byte  = 8 bits  */
     /* DMA_DATA_TYPE_BYTE_alt = DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD_2,
      * BYTE and BYTE_alt are interchangeable in hw, but we advice against
@@ -134,6 +166,19 @@ typedef enum
     DMA_DATA_TYPE__undef,   /*!< DMA will not be used. */
 } dma_data_type_t;
 
+typedef enum
+{
+    DMA_DIM_CONF_1D = 0, /* The DMA will copy data along D1 only. */
+    DMA_DIM_CONF_2D = 1, /* The DMA will copy data along D1 and D2. */
+    DMA_DIM_CONF__size,  /* Not used, only for sanity checks. */
+    /*
+        Padding is enabled with the 2D mode. This means that to pad a 1D
+        data structure, i.e. an array, the DMA would have to be set in 2D
+        mode with the D2 dimension set to 1.
+        This case is handled by the DMA HAL, so it's transparent to the user.
+     */
+} dma_dim_t;
+
 /**
  * It is possible to choose the level of safety with which the DMA operation
  * should be configured.
@@ -279,11 +324,15 @@ typedef struct
     if the target is a peripheral. */
     uint8_t*                ptr;     /*!< Pointer to the start address from/to
     where data will be copied/pasted. */
-    uint16_t                inc_du;  /*!< How much the pointer will increase
+    uint8_t                inc_du;  /*!< How much the pointer will increase
     every time a read/write operation is done. It is a multiple of the data units.
     Can be left blank if the target is a peripheral. */
-    uint32_t                size_du; /*!< The size (in data units) of the data to
+    uint32_t                inc_d2_du; /*!< How much the D2 pointer will increase
+    every time the DMA finishes to read a #D1 of data units. */
+    uint16_t                size_du; /*!< The size (in data units) of the data to
     be copied. Can be left blank if the target will only be used as destination.*/
+    uint16_t                size_d2_du; /*!< The size (in data units) of the data
+    to be copied along D2.*/
     dma_data_type_t         type;    /*!< The type of data to be transferred.
     Can be left blank if the target will only be used as destination. */
     dma_trigger_slot_mask_t trig;    /*!< If the target is a peripheral, a
@@ -296,6 +345,7 @@ typedef struct
  * It also includes control parameters to override the targets' specific ones
  * if needed.
  */
+
 typedef struct
 {
     dma_target_t*       src;   /*!< Target from where the data will be
@@ -306,11 +356,23 @@ typedef struct
     copied. - only valid in address mode */
     uint16_t            inc_b;  /*!< A common increment in case both targets
     need to use one same increment. */
-    uint32_t            size_b; /*!< The size of the transfer, in bytes (in
+    uint32_t            size_b; /*!< The size of the transfer along D1, in bytes (in
+    contrast, the size stored in the targets is in data units). */
+    uint32_t            size_d2_b; /*!< The size of the transfer along D2, in bytes (in
     contrast, the size stored in the targets is in data units). */
-    dma_data_type_t     type;   /*!< The data type to use. One is chosen among
+    dma_dim_t           dim; /*!< Sets the dimensionality of the
+    DMA, either 1D or 2D. */
+    uint8_t             pad_top_du; /*!< Padding at the top of the 2D transfer. */
+    uint8_t             pad_bottom_du; /*!< Padding at the bottom of the 2D transfer. */
+    uint8_t             pad_left_du; /*!< Padding at the left of the 2D transfer. */
+    uint8_t             pad_right_du; /*!< Padding at the right of the 2D transfer. */
+    dma_data_type_t     src_type;   /*!< Source data type to use. One is chosen among
     the targets. */
+    dma_data_type_t     dst_type;   /*!< Destination data type to use. One is chosen among
+    the targets. */
+    uint8_t             sign_ext;   /*!< Whether to sign extend the data. */
     dma_trans_mode_t    mode;   /*!< The copy mode to use. */
+    uint8_t             dim_inv; /*!< If the D1 and D2 dimensions are inverted, i.e. perform transposition. */
     uint32_t            win_du;  /*!< The amount of data units every which the
     WINDOW_DONE flag is raised and its corresponding interrupt triggered. It
     can be set to 0 to disable this functionality. */
@@ -318,6 +380,7 @@ typedef struct
     is launched. */
     dma_config_flags_t  flags;  /*!< A mask with possible issues aroused from
     the creation of the transaction. */
+    uint8_t             channel; /*!< The channel to use. */
 } dma_trans_t;
 
 /****************************************************************************/
@@ -335,22 +398,62 @@ typedef struct
 /**
  * @brief Attends the plic interrupt.
  */
-void handler_irq_dma( uint32_t id );
+__attribute__((optimize("O0"))) void handler_irq_dma( uint32_t id );
 
 /**
  * @brief This is a non-weak implementation of the function declared in
  * fast_intr_ctrl.c
  */
-void fic_irq_dma(void);
+__attribute__((optimize("O0"))) void fic_irq_dma(void);
+
+/**
+ * @brief Writes a given value into the specified register. Its operation
+ * mimics that of bitfield_field32_write(), but does not require the use of
+ * a field structure, that is not always provided in the _regs.h file.
+ * @param p_val The value to be written.
+ * @param p_offset The register's offset from the peripheral's base address
+ *  where the target register is located.
+ * @param p_mask The variable's mask to only modify its bits inside the whole
+ * register.
+ * @param p_sel The selection index (i.e. From which bit inside the register
+ * the value is to be written).
+ * @param p_peri The peripheral where the register is located.
+ */
+/* @ToDo: Consider changing the "mask" parameter for a bitfield definition
+(see dma_regs.h) */
+inline void write_register( uint32_t  p_val,
+                                  uint32_t  p_offset,
+                                  uint32_t  p_mask,
+                                  uint8_t   p_sel,
+                                  dma*      p_dma)
+{
+    /*
+     * The index is computed to avoid needing to access the structure
+     * as a structure.
+     */
+    uint8_t index = p_offset / sizeof(uint32_t);
+    /*
+     * An intermediate variable "value" is used to prevent writing twice into
+     * the register.
+     */
+    uint32_t value  =  (( uint32_t * ) p_dma ) [ index ];
+    value           &= ~( p_mask << p_sel );
+    value           |= (p_val & p_mask) << p_sel;
+    (( uint32_t * ) p_dma ) [ index ] = value;
+
+// @ToDo: mmio_region_write32(dma->base_addr, (ptrdiff_t)(DMA_SLOT_REG_OFFSET), (tx_slot_mask << DMA_SLOT_TX_TRIGGER_SLOT_OFFSET) + rx_slot_mask)
+
+}
+
 
 /**
  *@brief Takes all DMA configurations to a state where no accidental
  * transaction can be performed.
  * It can be called anytime to reset the DMA control block.
- * @param peri Pointer to a register address following the dma structure. By
+ * @param dma_peri Pointer to a register address following the dma structure. By
  * default (peri == NULL), the integrated DMA will be used.
  */
-void dma_init( dma *peri );
+void dma_init( dma *dma_peri);
 
 /**
  * @brief Creates a transaction that can be loaded into the DMA.
@@ -381,7 +484,7 @@ dma_config_flags_t dma_validate_transaction(  dma_trans_t       *p_trans,
  * the result from inside target structure as an error could have appeared
  * before the creation of the structure.
  */
-dma_config_flags_t dma_load_transaction( dma_trans_t* p_trans );
+dma_config_flags_t dma_load_transaction( dma_trans_t* p_trans);
 
 /**
  * @brief Launches the loaded transaction.
@@ -393,7 +496,7 @@ dma_config_flags_t dma_load_transaction( dma_trans_t* p_trans );
  * loaded is not the desired one).
  * @retval DMA_CONFIG_OK == 0 otherwise.
  */
-dma_config_flags_t dma_launch( dma_trans_t* p_trans );
+dma_config_flags_t dma_launch( dma_trans_t* p_trans);
 
 /**
  * @brief Read from the done register of the DMA. Additionally decreases the
@@ -402,41 +505,45 @@ dma_config_flags_t dma_launch( dma_trans_t* p_trans );
  * running or a new transaction was launched.
  * Be careful when calling this function if interrupts were chosen as the end
  * event.
+ * @param channel The channel to read from.
  * @return Whether the DMA is working or not. It starts returning 0 as soon as
  * the dma_launch function has returned.
  * @retval 0 - DMA is working.
  * @retval 1 - DMA has finished the transmission. DMA is idle.
  */
-uint32_t dma_is_ready(void);
+uint32_t dma_is_ready(uint8_t channel);
 
 /**
  * @brief Get the number of windows that have already been written. Resets on
  * the start of each transaction.
+ * @param channel The channel to read from.
  * @return The number of windows that have been written from this transaction.
  */
-uint32_t dma_get_window_count(void);
+uint32_t dma_get_window_count(uint8_t channel);
 
 /**
  * @brief Prevent the DMA from relaunching the transaction automatically after
  * finishing the current one. It does not affect the currently running
- * transaction. It has no effect if the DMA is operating in SINGULAR
+ * transaction. It has no effect if the DMA is operating in SINGLE
  * transaction mode.
+ * @param channel The channel to stop.
  */
-void dma_stop_circular(void);
+void dma_stop_circular(uint8_t channel);
 
 /**
 * @brief DMA interrupt handler.
 * `dma.c` provides a weak definition of this symbol, which can be overridden
 * at link-time by providing an additional non-weak definition.
+* @param channel The channel that triggered the interrupt.
 */
-void dma_intr_handler_trans_done(void);
+void dma_intr_handler_trans_done(uint8_t channel);
 
 /**
 * @brief DMA interrupt handler.
 * `dma.c` provides a weak definition of this symbol, which can be overridden
 * at link-time by providing an additional non-weak definition.
 */
-void dma_intr_handler_window_done(void);
+void dma_intr_handler_window_done(uint8_t channel);
 
 /**
  * @brief This weak implementation allows the user to override the threshold
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h
index ce6169c1..408b23ae 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h
@@ -25,27 +25,56 @@ extern "C" {
 // Addess data pointer (word aligned)
 #define DMA_ADDR_PTR_REG_OFFSET 0x8
 
-// Number of bytes to copy - Once a value is written, the copy starts
-#define DMA_SIZE_REG_OFFSET 0xc
+// Number of bytes to copy from, defined with respect to the first dimension
+// - Once a value is written, the copy starts
+#define DMA_SIZE_D1_REG_OFFSET 0xc
+#define DMA_SIZE_D1_SIZE_MASK 0xffff
+#define DMA_SIZE_D1_SIZE_OFFSET 0
+#define DMA_SIZE_D1_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_SIZE_D1_SIZE_MASK, .index = DMA_SIZE_D1_SIZE_OFFSET })
+
+// Number of bytes to copy from, defined with respect to the second dimension
+#define DMA_SIZE_D2_REG_OFFSET 0x10
+#define DMA_SIZE_D2_SIZE_MASK 0xffff
+#define DMA_SIZE_D2_SIZE_OFFSET 0
+#define DMA_SIZE_D2_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_SIZE_D2_SIZE_MASK, .index = DMA_SIZE_D2_SIZE_OFFSET })
 
 // Status bits are set to one if a given event occurred
-#define DMA_STATUS_REG_OFFSET 0x10
+#define DMA_STATUS_REG_OFFSET 0x14
 #define DMA_STATUS_READY_BIT 0
 #define DMA_STATUS_WINDOW_DONE_BIT 1
 
-// Increment number of src/dst pointer every time a word is copied
-#define DMA_PTR_INC_REG_OFFSET 0x14
-#define DMA_PTR_INC_SRC_PTR_INC_MASK 0xff
-#define DMA_PTR_INC_SRC_PTR_INC_OFFSET 0
-#define DMA_PTR_INC_SRC_PTR_INC_FIELD \
-  ((bitfield_field32_t) { .mask = DMA_PTR_INC_SRC_PTR_INC_MASK, .index = DMA_PTR_INC_SRC_PTR_INC_OFFSET })
-#define DMA_PTR_INC_DST_PTR_INC_MASK 0xff
-#define DMA_PTR_INC_DST_PTR_INC_OFFSET 8
-#define DMA_PTR_INC_DST_PTR_INC_FIELD \
-  ((bitfield_field32_t) { .mask = DMA_PTR_INC_DST_PTR_INC_MASK, .index = DMA_PTR_INC_DST_PTR_INC_OFFSET })
+// Increment the D1 source pointer every time a word is copied
+#define DMA_SRC_PTR_INC_D1_REG_OFFSET 0x18
+#define DMA_SRC_PTR_INC_D1_INC_MASK 0x3f
+#define DMA_SRC_PTR_INC_D1_INC_OFFSET 0
+#define DMA_SRC_PTR_INC_D1_INC_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_SRC_PTR_INC_D1_INC_MASK, .index = DMA_SRC_PTR_INC_D1_INC_OFFSET })
+
+// Increment the D2 source pointer every time a word is copied
+#define DMA_SRC_PTR_INC_D2_REG_OFFSET 0x1c
+#define DMA_SRC_PTR_INC_D2_INC_MASK 0x7fffff
+#define DMA_SRC_PTR_INC_D2_INC_OFFSET 0
+#define DMA_SRC_PTR_INC_D2_INC_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_SRC_PTR_INC_D2_INC_MASK, .index = DMA_SRC_PTR_INC_D2_INC_OFFSET })
+
+// Increment the D1 destination pointer every time a word is copied
+#define DMA_DST_PTR_INC_D1_REG_OFFSET 0x20
+#define DMA_DST_PTR_INC_D1_INC_MASK 0x3f
+#define DMA_DST_PTR_INC_D1_INC_OFFSET 0
+#define DMA_DST_PTR_INC_D1_INC_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_DST_PTR_INC_D1_INC_MASK, .index = DMA_DST_PTR_INC_D1_INC_OFFSET })
+
+// Increment the D2 destination pointer every time a word is copied
+#define DMA_DST_PTR_INC_D2_REG_OFFSET 0x24
+#define DMA_DST_PTR_INC_D2_INC_MASK 0x7fffff
+#define DMA_DST_PTR_INC_D2_INC_OFFSET 0
+#define DMA_DST_PTR_INC_D2_INC_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_DST_PTR_INC_D2_INC_MASK, .index = DMA_DST_PTR_INC_D2_INC_OFFSET })
 
 // The DMA will wait for the signal
-#define DMA_SLOT_REG_OFFSET 0x18
+#define DMA_SLOT_REG_OFFSET 0x28
 #define DMA_SLOT_RX_TRIGGER_SLOT_MASK 0xffff
 #define DMA_SLOT_RX_TRIGGER_SLOT_OFFSET 0
 #define DMA_SLOT_RX_TRIGGER_SLOT_FIELD \
@@ -55,19 +84,35 @@ extern "C" {
 #define DMA_SLOT_TX_TRIGGER_SLOT_FIELD \
   ((bitfield_field32_t) { .mask = DMA_SLOT_TX_TRIGGER_SLOT_MASK, .index = DMA_SLOT_TX_TRIGGER_SLOT_OFFSET })
 
-// Width/type of the data to transfer
-#define DMA_DATA_TYPE_REG_OFFSET 0x1c
-#define DMA_DATA_TYPE_DATA_TYPE_MASK 0x3
-#define DMA_DATA_TYPE_DATA_TYPE_OFFSET 0
-#define DMA_DATA_TYPE_DATA_TYPE_FIELD \
-  ((bitfield_field32_t) { .mask = DMA_DATA_TYPE_DATA_TYPE_MASK, .index = DMA_DATA_TYPE_DATA_TYPE_OFFSET })
-#define DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD 0x0
-#define DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD 0x1
-#define DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD 0x2
-#define DMA_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD_2 0x3
+// Width/type of the source data to transfer
+#define DMA_SRC_DATA_TYPE_REG_OFFSET 0x2c
+#define DMA_SRC_DATA_TYPE_DATA_TYPE_MASK 0x3
+#define DMA_SRC_DATA_TYPE_DATA_TYPE_OFFSET 0
+#define DMA_SRC_DATA_TYPE_DATA_TYPE_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_SRC_DATA_TYPE_DATA_TYPE_MASK, .index = DMA_SRC_DATA_TYPE_DATA_TYPE_OFFSET })
+#define DMA_SRC_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD 0x0
+#define DMA_SRC_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD 0x1
+#define DMA_SRC_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD 0x2
+#define DMA_SRC_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD_2 0x3
+
+// Width/type of the destination data to transfer
+#define DMA_DST_DATA_TYPE_REG_OFFSET 0x30
+#define DMA_DST_DATA_TYPE_DATA_TYPE_MASK 0x3
+#define DMA_DST_DATA_TYPE_DATA_TYPE_OFFSET 0
+#define DMA_DST_DATA_TYPE_DATA_TYPE_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_DST_DATA_TYPE_DATA_TYPE_MASK, .index = DMA_DST_DATA_TYPE_DATA_TYPE_OFFSET })
+#define DMA_DST_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD 0x0
+#define DMA_DST_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD 0x1
+#define DMA_DST_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD 0x2
+#define DMA_DST_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD_2 0x3
+
+// Is the data to be sign extended? (Checked only if the dst data type is
+// wider than the src data type)
+#define DMA_SIGN_EXT_REG_OFFSET 0x34
+#define DMA_SIGN_EXT_SIGNED_BIT 0
 
 // Set the operational mode of the DMA
-#define DMA_MODE_REG_OFFSET 0x20
+#define DMA_MODE_REG_OFFSET 0x38
 #define DMA_MODE_MODE_MASK 0x3
 #define DMA_MODE_MODE_OFFSET 0
 #define DMA_MODE_MODE_FIELD \
@@ -76,17 +121,69 @@ extern "C" {
 #define DMA_MODE_MODE_VALUE_CIRCULAR_MODE 0x1
 #define DMA_MODE_MODE_VALUE_ADDRESS_MODE 0x2
 
+// Set the dimensionality of the DMA
+#define DMA_DIM_CONFIG_REG_OFFSET 0x3c
+#define DMA_DIM_CONFIG_DMA_DIM_BIT 0
+
+// DMA dimensionality inversion selector
+#define DMA_DIM_INV_REG_OFFSET 0x40
+#define DMA_DIM_INV_SEL_BIT 0
+
+// Set the top padding
+#define DMA_PAD_TOP_REG_OFFSET 0x44
+#define DMA_PAD_TOP_PAD_MASK 0x3f
+#define DMA_PAD_TOP_PAD_OFFSET 0
+#define DMA_PAD_TOP_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_PAD_TOP_PAD_MASK, .index = DMA_PAD_TOP_PAD_OFFSET })
+
+// Set the bottom padding
+#define DMA_PAD_BOTTOM_REG_OFFSET 0x48
+#define DMA_PAD_BOTTOM_PAD_MASK 0x3f
+#define DMA_PAD_BOTTOM_PAD_OFFSET 0
+#define DMA_PAD_BOTTOM_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_PAD_BOTTOM_PAD_MASK, .index = DMA_PAD_BOTTOM_PAD_OFFSET })
+
+// Set the right padding
+#define DMA_PAD_RIGHT_REG_OFFSET 0x4c
+#define DMA_PAD_RIGHT_PAD_MASK 0x3f
+#define DMA_PAD_RIGHT_PAD_OFFSET 0
+#define DMA_PAD_RIGHT_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_PAD_RIGHT_PAD_MASK, .index = DMA_PAD_RIGHT_PAD_OFFSET })
+
+// Set the left padding
+#define DMA_PAD_LEFT_REG_OFFSET 0x50
+#define DMA_PAD_LEFT_PAD_MASK 0x3f
+#define DMA_PAD_LEFT_PAD_OFFSET 0
+#define DMA_PAD_LEFT_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_PAD_LEFT_PAD_MASK, .index = DMA_PAD_LEFT_PAD_OFFSET })
+
 // Will trigger a every "WINDOW_SIZE" writes
-#define DMA_WINDOW_SIZE_REG_OFFSET 0x24
+#define DMA_WINDOW_SIZE_REG_OFFSET 0x54
+#define DMA_WINDOW_SIZE_WINDOW_SIZE_MASK 0x1fff
+#define DMA_WINDOW_SIZE_WINDOW_SIZE_OFFSET 0
+#define DMA_WINDOW_SIZE_WINDOW_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_WINDOW_SIZE_WINDOW_SIZE_MASK, .index = DMA_WINDOW_SIZE_WINDOW_SIZE_OFFSET })
 
 // Number of times the end of the window was reached since the beginning.
-#define DMA_WINDOW_COUNT_REG_OFFSET 0x28
+#define DMA_WINDOW_COUNT_REG_OFFSET 0x58
+#define DMA_WINDOW_COUNT_WINDOW_COUNT_MASK 0xff
+#define DMA_WINDOW_COUNT_WINDOW_COUNT_OFFSET 0
+#define DMA_WINDOW_COUNT_WINDOW_COUNT_FIELD \
+  ((bitfield_field32_t) { .mask = DMA_WINDOW_COUNT_WINDOW_COUNT_MASK, .index = DMA_WINDOW_COUNT_WINDOW_COUNT_OFFSET })
 
 // Interrupt Enable Register
-#define DMA_INTERRUPT_EN_REG_OFFSET 0x2c
+#define DMA_INTERRUPT_EN_REG_OFFSET 0x5c
 #define DMA_INTERRUPT_EN_TRANSACTION_DONE_BIT 0
 #define DMA_INTERRUPT_EN_WINDOW_DONE_BIT 1
 
+// Interrupt Flag Register for transactions
+#define DMA_TRANSACTION_IFR_REG_OFFSET 0x60
+#define DMA_TRANSACTION_IFR_FLAG_BIT 0
+
+// Interrupt Flag Register for windows
+#define DMA_WINDOW_IFR_REG_OFFSET 0x64
+#define DMA_WINDOW_IFR_FLAG_BIT 0
+
 #ifdef __cplusplus
 }  // extern "C"
 #endif
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.c
index 27c000a0..0493864e 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.c
@@ -29,6 +29,9 @@
 /*                             MODULES USED                                 */
 /**                                                                        **/
 /****************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #include "fast_intr_ctrl.h"
 #include "core_v_mini_mcu.h"
@@ -418,6 +421,9 @@ void handler_irq_fast_gpio_7(void)
     // call the weak fic handler
     fic_irq_gpio_7();
 }
+#ifdef __cplusplus
+}
+#endif
 
 /****************************************************************************/
 /**                                                                        **/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.h
index 87997551..46c0ada2 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/fast_intr_ctrl/fast_intr_ctrl.h
@@ -32,7 +32,9 @@
 /**                            MODULES USED                                **/
 /**                                                                        **/
 /****************************************************************************/
-
+#ifdef __cplusplus
+extern "C" {
+#endif
 #include <stddef.h>
 #include <stdint.h>
 #include "mmio.h"
@@ -242,7 +244,9 @@ void fic_irq_gpio_7(void);
 /**                          INLINE FUNCTIONS                              **/
 /**                                                                        **/
 /****************************************************************************/
-
+#ifdef __cplusplus
+}
+#endif
 /****************************************************************************/
 /**                                                                        **/
 /**                                EOF                                     **/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c
index f5cb004f..7f28db54 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/gpio/gpio.c
@@ -23,7 +23,9 @@
 * @version  1
 * @brief    GPIO driver
 */
-
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
 /****************************************************************************/
 /**                                                                        **/
 /*                             MODULES USED                                 */
@@ -572,4 +574,9 @@ __attribute__((optimize("O0"))) static void gpio_handler_irq_dummy( uint32_t dum
 /**                                                                        **/
 /*                                 EOF                                      */
 /**                                                                        **/
-/****************************************************************************/
\ No newline at end of file
+/****************************************************************************/
+
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/data/power_manager.h.tpl b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/data/power_manager.h.tpl
index 7f0d939e..52215d27 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/data/power_manager.h.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/data/power_manager.h.tpl
@@ -105,16 +105,16 @@ typedef struct power_manager_ram_map_t {
   uint32_t monitor_power_gate;
 } power_manager_ram_map_t;
 
-static power_manager_ram_map_t power_manager_ram_map[${ram_numbanks}] = {
-% for bank in range(ram_numbanks):
+static power_manager_ram_map_t power_manager_ram_map[${xheep.ram_numbanks()}] = {
+% for bank in xheep.iter_ram_banks():
   (power_manager_ram_map_t) {
-    .clk_gate = POWER_MANAGER_RAM_${bank}_CLK_GATE_REG_OFFSET,
-    .power_gate_ack = POWER_MANAGER_POWER_GATE_RAM_BLOCK_${bank}_ACK_REG_OFFSET,
-    .switch_off = POWER_MANAGER_RAM_${bank}_SWITCH_REG_OFFSET,
-    .wait_ack_switch = POWER_MANAGER_RAM_${bank}_WAIT_ACK_SWITCH_ON_REG_OFFSET,
-    .iso = POWER_MANAGER_RAM_${bank}_ISO_REG_OFFSET,
-    .retentive = POWER_MANAGER_RAM_${bank}_RETENTIVE_REG_OFFSET,
-    .monitor_power_gate = POWER_MANAGER_MONITOR_POWER_GATE_RAM_BLOCK_${bank}_REG_OFFSET
+    .clk_gate = POWER_MANAGER_RAM_${bank.name()}_CLK_GATE_REG_OFFSET,
+    .power_gate_ack = POWER_MANAGER_POWER_GATE_RAM_BLOCK_${bank.name()}_ACK_REG_OFFSET,
+    .switch_off = POWER_MANAGER_RAM_${bank.name()}_SWITCH_REG_OFFSET,
+    .wait_ack_switch = POWER_MANAGER_RAM_${bank.name()}_WAIT_ACK_SWITCH_ON_REG_OFFSET,
+    .iso = POWER_MANAGER_RAM_${bank.name()}_ISO_REG_OFFSET,
+    .retentive = POWER_MANAGER_RAM_${bank.name()}_RETENTIVE_REG_OFFSET,
+    .monitor_power_gate = POWER_MANAGER_MONITOR_POWER_GATE_RAM_BLOCK_${bank.name()}_REG_OFFSET
   },
 % endfor
 };
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager.c
index 4a9c37a8..06677121 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager.c
@@ -15,174 +15,7 @@
 
 #include "x-heep.h"
 
-
-void __attribute__ ((noinline)) power_gate_core_asm()
-{
-    asm volatile (
-
-        // write POWER_GATE_CORE[0] = 1
-        "lui a0, %[base_address_20bit]\n"
-        "li  a1, 1\n"
-        "sw  a1, %[power_manager_power_gate_core_reg_offset](a0)\n"
-
-        // write WAKEUP_STATE[0] = 1
-        "sw  a1, %[power_manager_wakeup_state_reg_offset](a0)\n" : : \
-        \
-        [base_address_20bit] "i" (POWER_MANAGER_START_ADDRESS >> 12), \
-        [power_manager_power_gate_core_reg_offset] "i" (POWER_MANAGER_POWER_GATE_CORE_REG_OFFSET), \
-        [power_manager_wakeup_state_reg_offset] "i" (POWER_MANAGER_WAKEUP_STATE_REG_OFFSET) : "a0", "a1" \
-    );
-
-    asm volatile (
-
-        // write registers
-        "la a0, __power_manager_start\n"
-        "sw x1,  0(a0)\n"
-        "sw x2,  4(a0)\n"
-        "sw x3,  8(a0)\n"
-        "sw x4,  12(a0)\n"
-        "sw x5,  16(a0)\n"
-        "sw x6,  20(a0)\n"
-        "sw x7,  24(a0)\n"
-        "sw x8,  28(a0)\n"
-        "sw x9,  32(a0)\n"
-        "sw x10, 36(a0)\n"
-        "sw x11, 40(a0)\n"
-        "sw x12, 44(a0)\n"
-        "sw x13, 48(a0)\n"
-        "sw x14, 52(a0)\n"
-        "sw x15, 56(a0)\n"
-        "sw x16, 60(a0)\n"
-        "sw x17, 64(a0)\n"
-        "sw x18, 68(a0)\n"
-        "sw x19, 72(a0)\n"
-        "sw x20, 76(a0)\n"
-        "sw x21, 80(a0)\n"
-        "sw x22, 88(a0)\n"
-        "sw x23, 92(a0)\n"
-        "sw x24, 96(a0)\n"
-        "sw x25, 100(a0)\n"
-        "sw x26, 104(a0)\n"
-        "sw x27, 108(a0)\n"
-        "sw x28, 112(a0)\n"
-        "sw x29, 116(a0)\n"
-        "sw x30, 120(a0)\n"
-        "sw x31, 124(a0)\n"
-        //csr
-        "csrr a1, mstatus\n"
-        "sw a1, 128(a0)\n"
-        "csrr a1, mie\n"
-        "sw a1, 132(a0)\n"
-        "csrr a1, mtvec\n"
-        "sw a1, 136(a0)\n"
-        "csrr a1, mscratch\n"
-        "sw a1, 140(a0)\n"
-        "csrr a1, mepc\n"
-        "sw a1, 144(a0)\n"
-        "csrr a1, mcause\n"
-        "sw a1, 148(a0)\n"
-        "csrr a1, mtval\n"
-        "sw a1, 152(a0)\n"
-        "csrr a1, mcycle\n"
-        "sw a1, 156(a0)\n"
-        "csrr a1, minstret\n"
-        "sw a1, 160(a0)\n"  : : : "a0", "a1" \
-    );
-
-    asm volatile (
-
-        // write RESTORE_ADDRESS[31:0] = PC
-        "lui a0, %[base_address_20bit]\n"
-        "la  a1, wakeup\n"
-        "sw  a1, %[power_manager_restore_address_reg_offset](a0)\n"
-
-        // wait for interrupt
-        "wfi\n"
-
-        // ----------------------------
-        // power-gate
-        // ----------------------------
-
-        // ----------------------------
-        // wake-up
-        // ----------------------------
-
-        // write POWER_GATE_CORE[0] = 0
-        "wakeup:"
-        "lui a0, %[base_address_20bit]\n"
-        "sw  x0, %[power_manager_power_gate_core_reg_offset](a0)\n"
-
-        // write WAKEUP_STATE[0] = 0
-        "sw x0, %[power_manager_wakeup_state_reg_offset](a0)\n"
-
-        // write RESTORE_ADDRESS[31:0] = 0
-        "sw x0, %[power_manager_restore_address_reg_offset](a0)\n" : : \
-        \
-        [base_address_20bit] "i" (POWER_MANAGER_START_ADDRESS >> 12), \
-        [power_manager_power_gate_core_reg_offset] "i" (POWER_MANAGER_POWER_GATE_CORE_REG_OFFSET), \
-        [power_manager_wakeup_state_reg_offset] "i" (POWER_MANAGER_WAKEUP_STATE_REG_OFFSET), \
-        [power_manager_restore_address_reg_offset] "i" (POWER_MANAGER_RESTORE_ADDRESS_REG_OFFSET) : "a0", "a1" \
-    );
-
-    asm volatile (
-
-        // write CORE_REG_Xn[31:0] = Xn
-        "la a0, __power_manager_start\n"
-        //one of the following load is gonna overwrite a0, but a0 was already stored before to the right value
-        "lw x1,  0(a0)\n"
-        "lw x2,  4(a0)\n"
-        "lw x3,  8(a0)\n"
-        "lw x4,  12(a0)\n"
-        "lw x5,  16(a0)\n"
-        "lw x6,  20(a0)\n"
-        "lw x7,  24(a0)\n"
-        "lw x8,  28(a0)\n"
-        "lw x9,  32(a0)\n"
-        "lw x10, 36(a0)\n"
-        "lw x11, 40(a0)\n"
-        "lw x12, 44(a0)\n"
-        "lw x13, 48(a0)\n"
-        "lw x14, 52(a0)\n"
-        "lw x15, 56(a0)\n"
-        "lw x16, 60(a0)\n"
-        "lw x17, 64(a0)\n"
-        "lw x18, 68(a0)\n"
-        "lw x19, 72(a0)\n"
-        "lw x20, 76(a0)\n"
-        "lw x21, 80(a0)\n"
-        "lw x22, 88(a0)\n"
-        "lw x23, 92(a0)\n"
-        "lw x24, 96(a0)\n"
-        "lw x25, 100(a0)\n"
-        "lw x26, 104(a0)\n"
-        "lw x27, 108(a0)\n"
-        "lw x28, 112(a0)\n"
-        "lw x29, 116(a0)\n"
-        "lw x30, 120(a0)\n"
-        "lw x31, 124(a0)\n"
-        //csr
-        "lw a1, 128(a0)\n"
-        "csrw mstatus, a1\n"
-        "lw a1, 132(a0)\n"
-        "csrw mie, a1\n"
-        "lw a1, 136(a0)\n"
-        "csrw mtvec, a1\n"
-        "lw a1, 140(a0)\n"
-        "csrw mscratch, a1\n"
-        "lw a1, 144(a0)\n"
-        "csrw mepc, a1\n"
-        "lw a1, 148(a0)\n"
-        "csrw mcause, a1\n"
-        "lw a1, 152(a0)\n"
-        "csrw mtval, a1\n"
-        "lw a1, 156(a0)\n"
-        "csrw mcycle, a1\n"
-        "lw a1, 160(a0)\n"
-        "csrw minstret, a1\n": : : "a0", "a1" \
-    );
-
-    return;
-}
+extern void power_manager_cpu_store();
 
 power_manager_result_t __attribute__ ((noinline)) power_gate_core(const power_manager_t *power_manager, power_manager_sel_intr_t sel_intr, power_manager_counters_t* cpu_counter)
 {
@@ -201,14 +34,11 @@ power_manager_result_t __attribute__ ((noinline)) power_gate_core(const power_ma
     mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(POWER_MANAGER_INTR_STATE_REG_OFFSET), 0x0);
 
     // enable wait for SWITCH ACK
-    #ifdef TARGET_PYNQ_Z2
-        reg = bitfield_bit32_write(reg, POWER_MANAGER_CPU_WAIT_ACK_SWITCH_ON_COUNTER_CPU_WAIT_ACK_SWITCH_ON_COUNTER_BIT, 0x0);
-    #else
-        reg = bitfield_bit32_write(reg, POWER_MANAGER_CPU_WAIT_ACK_SWITCH_ON_COUNTER_CPU_WAIT_ACK_SWITCH_ON_COUNTER_BIT, 0x1);
-    #endif
+    reg = bitfield_bit32_write(reg, POWER_MANAGER_CPU_WAIT_ACK_SWITCH_ON_COUNTER_CPU_WAIT_ACK_SWITCH_ON_COUNTER_BIT, 0x1);
+
     mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(POWER_MANAGER_CPU_WAIT_ACK_SWITCH_ON_COUNTER_REG_OFFSET), reg);
 
-    power_gate_core_asm();
+    power_manager_cpu_store();
 
     // clean up states
     mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(POWER_MANAGER_EN_WAIT_FOR_INTR_REG_OFFSET), 0x0);
@@ -231,11 +61,7 @@ power_manager_result_t __attribute__ ((noinline)) power_gate_periph(const power_
 {
     uint32_t reg = 0;
 
-    #ifdef TARGET_PYNQ_Z2
-        mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(POWER_MANAGER_PERIPH_WAIT_ACK_SWITCH_ON_REG_OFFSET), 0x0);
-    #else
-        mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(POWER_MANAGER_PERIPH_WAIT_ACK_SWITCH_ON_REG_OFFSET), 0x1);
-    #endif
+    mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(POWER_MANAGER_PERIPH_WAIT_ACK_SWITCH_ON_REG_OFFSET), 0x1);
 
     if (sel_state == kOn_e)
     {
@@ -265,11 +91,7 @@ power_manager_result_t __attribute__ ((noinline)) power_gate_ram_block(const pow
 
     if (sel_state == kOn_e)
     {
-        #ifdef TARGET_PYNQ_Z2
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].wait_ack_switch), 0x0);
-        #else
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].wait_ack_switch), 0x1);
-        #endif
+        mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].wait_ack_switch), 0x1);
         for (int i=0; i<ram_block_counters->switch_on; i++) asm volatile ("nop\n;");
         mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].switch_off), 0x0);
         for (int i=0; i<ram_block_counters->iso_off; i++) asm volatile ("nop\n;");
@@ -277,11 +99,7 @@ power_manager_result_t __attribute__ ((noinline)) power_gate_ram_block(const pow
     }
     else if (sel_state == kOff_e)
     {
-        #ifdef TARGET_PYNQ_Z2
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].wait_ack_switch), 0x0);
-        #else
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].wait_ack_switch), 0x1);
-        #endif
+        mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].wait_ack_switch), 0x1);
         for (int i=0; i<ram_block_counters->iso_on; i++) asm volatile ("nop\n;");
         mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_ram_map[sel_block].iso), 0x1);
         for (int i=0; i<ram_block_counters->switch_off; i++) asm volatile ("nop\n;");
@@ -309,11 +127,7 @@ power_manager_result_t __attribute__ ((noinline)) power_gate_external(const powe
 
     if (sel_state == kOn_e)
     {
-        #ifdef TARGET_PYNQ_Z2
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].wait_ack_switch), 0x0);
-        #else
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].wait_ack_switch), 0x1);
-        #endif
+        mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].wait_ack_switch), 0x1);
         for (int i=0; i<external_counters->switch_on; i++) asm volatile ("nop\n;");
         mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].switch_off), 0x0);
         for (int i=0; i<external_counters->iso_off; i++) asm volatile ("nop\n;");
@@ -323,11 +137,7 @@ power_manager_result_t __attribute__ ((noinline)) power_gate_external(const powe
     }
     else if (sel_state == kOff_e)
     {
-        #ifdef TARGET_PYNQ_Z2
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].wait_ack_switch), 0x0);
-        #else
-            mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].wait_ack_switch), 0x1);
-        #endif
+        mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].wait_ack_switch), 0x1);
         for (int i=0; i<external_counters->iso_on; i++) asm volatile ("nop\n;");
         mmio_region_write32(power_manager->base_addr, (ptrdiff_t)(power_manager_external_map[sel_external].iso), 0x1);
         for (int i=0; i<external_counters->switch_off; i++) asm volatile ("nop\n;");
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_restore.S b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_restore.S
new file mode 100644
index 00000000..00c9f9f3
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_restore.S
@@ -0,0 +1,88 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include "core_v_mini_mcu.h"
+#include "power_manager_regs.h"  // Generated.
+
+# power_manager_cpu.S
+# This function re-stores the CPU context when back from (deep) sleep
+.global power_manager_cpu_restore
+.type power_manager_cpu_restore, @function
+
+#define POWER_MANAGER_START_ADDRESS_20bit (POWER_MANAGER_START_ADDRESS >> 12)
+
+
+power_manager_cpu_restore:
+
+    //using lui to load the upper 20 bits of the address instead of la as I want to be sure no other registers are used
+    lui t0, POWER_MANAGER_START_ADDRESS_20bit
+    sw  x0, POWER_MANAGER_POWER_GATE_CORE_REG_OFFSET(t0)
+
+    // write WAKEUP_STATE[0] = 0
+    sw x0, POWER_MANAGER_WAKEUP_STATE_REG_OFFSET(t0)
+
+    // write RESTORE_ADDRESS[31:0] = 0
+    sw x0, POWER_MANAGER_RESTORE_ADDRESS_REG_OFFSET(t0)
+
+    // restore gp as it is gonna be used to calculate the address of __power_manager_start
+    lw  gp, POWER_MANAGER_GLOBAL_POINTER_REG_OFFSET(t0)
+
+    // write CORE_REG_Xn[31:0] = Xn
+    la t0, __power_manager_start
+    // restore context, this part could be optimized
+
+    //one of the following load is gonna overwrite t0, but t0 was already stored before to the right value
+    lw x1,  0(t0)
+    lw x2,  4(t0)
+    lw x3,  8(t0)
+    lw x4,  12(t0)
+    lw x5,  16(t0)
+    lw x6,  20(t0)
+    lw x7,  24(t0)
+    lw x8,  28(t0)
+    lw x9,  32(t0)
+    lw x10, 36(t0)
+    lw x11, 40(t0)
+    lw x12, 44(t0)
+    lw x13, 48(t0)
+    lw x14, 52(t0)
+    lw x15, 56(t0)
+    lw x16, 60(t0)
+    lw x17, 64(t0)
+    lw x18, 68(t0)
+    lw x19, 72(t0)
+    lw x20, 76(t0)
+    lw x21, 80(t0)
+    lw x22, 88(t0)
+    lw x23, 92(t0)
+    lw x24, 96(t0)
+    lw x25, 100(t0)
+    lw x26, 104(t0)
+    lw x27, 108(t0)
+    lw x28, 112(t0)
+    lw x29, 116(t0)
+    lw x30, 120(t0)
+    lw x31, 124(t0)
+    //csr
+    lw t1, 128(t0)
+    csrw mstatus, t1
+    lw t1, 132(t0)
+    csrw mie, t1
+    lw t1, 136(t0)
+    csrw mtvec, t1
+    lw t1, 140(t0)
+    csrw mscratch, t1
+    lw t1, 144(t0)
+    csrw mepc, t1
+    lw t1, 148(t0)
+    csrw mcause, t1
+    lw t1, 152(t0)
+    csrw mtval, t1
+    lw t1, 156(t0)
+    csrw mcycle, t1
+    lw t1, 160(t0)
+    csrw minstret, t1
+
+
+    ret
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_store.S b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_store.S
new file mode 100644
index 00000000..92e1ca8e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/power_manager/power_manager_cpu_store.S
@@ -0,0 +1,88 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#include "core_v_mini_mcu.h"
+#include "power_manager_regs.h"  // Generated.
+
+# power_manager_cpu.S
+# This function stores the CPU context, goes to (deep) sleep with WFI
+.global power_manager_cpu_store # make the function visible to the linker
+.type power_manager_cpu_store, @function
+
+power_manager_cpu_store:
+
+    // write POWER_GATE_CORE[0] = 1
+    la t0, POWER_MANAGER_START_ADDRESS
+    li  t1, 1
+    sw  t1, POWER_MANAGER_POWER_GATE_CORE_REG_OFFSET(t0)
+
+    // write WAKEUP_STATE[0] = 1, this is check in the bootrom at reset time when waking up
+    sw t1, POWER_MANAGER_WAKEUP_STATE_REG_OFFSET(t0)
+
+    // save the global pointer, _power_manager_start is the start of the power_manager section and saved in the gp reg
+    // when returning from deep sleep, the gp register is used to restore the context, thus saving it in an always on register
+    sw  gp, POWER_MANAGER_GLOBAL_POINTER_REG_OFFSET(t0)
+
+    // save context, this part could be optimized
+    la t0, __power_manager_start
+    sw x1,  0(t0)
+    sw x2,  4(t0)
+    sw x3,  8(t0)
+    sw x4,  12(t0)
+    sw x5,  16(t0)
+    sw x6,  20(t0)
+    sw x7,  24(t0)
+    sw x8,  28(t0)
+    sw x9,  32(t0)
+    sw x10, 36(t0)
+    sw x11, 40(t0)
+    sw x12, 44(t0)
+    sw x13, 48(t0)
+    sw x14, 52(t0)
+    sw x15, 56(t0)
+    sw x16, 60(t0)
+    sw x17, 64(t0)
+    sw x18, 68(t0)
+    sw x19, 72(t0)
+    sw x20, 76(t0)
+    sw x21, 80(t0)
+    sw x22, 88(t0)
+    sw x23, 92(t0)
+    sw x24, 96(t0)
+    sw x25, 100(t0)
+    sw x26, 104(t0)
+    sw x27, 108(t0)
+    sw x28, 112(t0)
+    sw x29, 116(t0)
+    sw x30, 120(t0)
+    sw x31, 124(t0)
+    //csr
+    csrr t1, mstatus
+    sw t1, 128(t0)
+    csrr t1, mie
+    sw t1, 132(t0)
+    csrr t1, mtvec
+    sw t1, 136(t0)
+    csrr t1, mscratch
+    sw t1, 140(t0)
+    csrr t1, mepc
+    sw t1, 144(t0)
+    csrr t1, mcause
+    sw t1, 148(t0)
+    csrr t1, mtval
+    sw t1, 152(t0)
+    csrr t1, mcycle
+    sw t1, 156(t0)
+    csrr t1, minstret
+    sw t1, 160(t0)
+
+    la t0, POWER_MANAGER_START_ADDRESS
+    //save return address to restore
+    la t1, power_manager_cpu_restore
+    sw t1, POWER_MANAGER_RESTORE_ADDRESS_REG_OFFSET(t0)
+
+    // wait for interrupt
+    wfi
+
+    ret
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c
index ffbb822d..c7fb8c7c 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_plic/rv_plic.c
@@ -34,6 +34,9 @@
 /*                             MODULES USED                                 */
 /**                                                                        **/
 /****************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #include "rv_plic.h"
 #include "rv_plic_structs.h"
@@ -72,7 +75,7 @@ const uint32_t plicMaxPriority = RV_PLIC_PRIO0_PRIO0_MASK;
  * Pointer used to dynamically access the different interrupt handlers.
 */
 typedef void (*handler_funct_t)(uint32_t);
-
+//#endif
 /****************************************************************************/
 /**                                                                        **/
 /*                      PROTOTYPES OF LOCAL FUNCTIONS                       */
@@ -366,8 +369,7 @@ plic_result_t plic_software_irq_is_pending(void)
 }
 
 
-plic_result_t plic_assign_external_irq_handler( uint32_t id,
-                                                void *handler )
+plic_result_t plic_assign_external_irq_handler( uint32_t id, void *handler )                                             
 {
   if( id >= EXT_IRQ_START && id <= QTY_INTR )
   {
@@ -377,6 +379,7 @@ plic_result_t plic_assign_external_irq_handler( uint32_t id,
   return kPlicBadArg;
 }
 
+
 void plic_reset_handlers_list(void)
 {
   handlers[NULL_INTR] = &handler_irq_dummy;
@@ -433,7 +436,9 @@ static uint8_t plic_irq_bit_index( uint32_t irq)
 {
   return irq % RV_PLIC_PARAM_REG_WIDTH;
 }
-
+#ifdef __cplusplus
+}
+#endif
 /****************************************************************************/
 /**                                                                        **/
 /*                                 EOF                                      */
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_timer/rv_timer.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_timer/rv_timer.h
index 09f30945..cba44974 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_timer/rv_timer.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/rv_timer/rv_timer.h
@@ -105,6 +105,12 @@ typedef enum rv_timer_approximate_tick_params_result {
  * @param[out] out Tick parameters that will approximately produce the desired
  *         counter frequency.
  * @return The result of the operation.
+ * 
+ * The minimum value for `counter_freq` is given by:
+ * counter_freq_min = (255/4096) * clock_freq 
+ * For example, if the clock frequency is 15MHz, the minimum value for `counter_freq` is about
+ * 1 MHz.
+ * The maximum value for `counter_freq` is given by the clock frequency.
  */
 rv_timer_approximate_tick_params_result_t
 rv_timer_approximate_tick_params(uint64_t clock_freq, uint64_t counter_freq,
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/soc_ctrl/soc_ctrl.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/soc_ctrl/soc_ctrl.h
index 9cfa45af..fe0e33c7 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/soc_ctrl/soc_ctrl.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/soc_ctrl/soc_ctrl.h
@@ -21,7 +21,7 @@ extern "C" {
  * Initialization parameters for SOC CTRL.
  *
  */
-typedef struct soc_ctrl {
+typedef struct /*soc_ctrl*/ {
   /**
    * The base address for the soc_ctrl hardware registers.
    */
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.c
index 3312b8cd..f22c2bdb 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.c
@@ -1,127 +1,491 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
+/*
+                              *******************
+******************************* C SOURCE FILE *****************************
+**                            *******************
+**
+** project  : X-HEEP
+** filename : spi_host.c
+** version  : 1
+** date     : 06/03/24
+**
+***************************************************************************
+**
+** Copyright (c) EPFL contributors.
+** All rights reserved.
+**
+***************************************************************************
+*/
 
+/***************************************************************************/
+/***************************************************************************/
+/**
+* @file   spi_host.c
+* @date   06/03/24
+* @author Llorenç Muela
+* @brief  The Serial Peripheral Interface (SPI) driver to set up and use the
+* SPI peripheral
+*/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                             MODULES USED                                 */
+/**                                                                        **/
+/****************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
 #include "spi_host.h"
 
-#include "mmio.h"
 #include "bitfield.h"
 
-// SPI get functions
 
-volatile uint8_t spi_get_tx_queue_depth(const spi_host_t *spi) {
-    volatile uint32_t status_reg = spi_get_status(spi);
-    return bitfield_field32_read(status_reg, SPI_HOST_STATUS_TXQD_FIELD);
+/****************************************************************************/
+/**                                                                        **/
+/*                        DEFINITIONS AND MACROS                            */
+/**                                                                        **/
+/****************************************************************************/
+
+#define SPI_EVENTS_INDEX    0
+#define SPI_ERRORS_INDEX    0
+
+#define SPI_CONFIGOPTS_ADDR(spi, csid) ((&SPI_HW(spi)->CONFIGOPTS0) + csid*sizeof(uint32_t))
+
+/****************************************************************************/
+/**                                                                        **/
+/*                        TYPEDEFS AND STRUCTURES                           */
+/**                                                                        **/
+/****************************************************************************/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                      PROTOTYPES OF LOCAL FUNCTIONS                       */
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Function that translates the status register to spi_event_e type. This
+ * has been implemented because the SPI peripheral has no other way to know which
+ * event was triggered other than reading the status.
+ * This function has been made local since only the event interrupt handler should
+ * need it.
+ * 
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param events Pointer to store the events that were triggered.
+ * @return spi_return_flags_e indicating problems, SPI_FLAG_OK if all went well.
+ */
+spi_return_flags_e spi_get_events(spi_host_t* spi, spi_event_e* events);
+
+/**
+ * @brief Function to acknoledge event interrupts once received to prevent them
+ * from triggering again.
+ * 
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return spi_return_flags_e indicating problems, SPI_FLAG_OK if all went well.
+ */
+spi_return_flags_e spi_acknowledge_event(spi_host_t* spi);
+
+/****************************************************************************/
+/**                                                                        **/
+/*                           EXPORTED VARIABLES                             */
+/**                                                                        **/
+/****************************************************************************/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            GLOBAL VARIABLES                              */
+/**                                                                        **/
+/****************************************************************************/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                           EXPORTED FUNCTIONS                             */
+/**                                                                        **/
+/****************************************************************************/
+
+spi_return_flags_e spi_get_events_enabled(spi_host_t* spi, spi_event_e* events) 
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    *events = bitfield_read(SPI_HW(spi)->EVENT_ENABLE, SPI_EVENT_ALL, SPI_EVENTS_INDEX);
+    return SPI_FLAG_OK;
 }
 
-volatile spi_ch_status_t spi_get_tx_channel_status(const spi_host_t *spi) {
-    volatile uint32_t status_reg = spi_get_status(spi);
-    spi_ch_status_t ch_status = {
-        .empty = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_TXEMPTY_BIT),
-        .full = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_TXFULL_BIT),
-        .stall = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_TXSTALL_BIT),
-        .wm = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_TXWM_BIT)
-    };
-    return ch_status;
+spi_return_flags_e spi_set_events_enabled(spi_host_t* spi, spi_event_e events, bool enable) 
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    if (events > SPI_EVENT_ALL) return SPI_FLAG_EVENT_INVALID;
+    // Since spi_event_e is mapped to EVENT_ENABLE: | = set, & ~ = clear
+    if (enable) SPI_HW(spi)->EVENT_ENABLE |= events;
+    else        SPI_HW(spi)->EVENT_ENABLE &= ~events;
+
+    return SPI_FLAG_OK;
 }
 
-volatile uint8_t spi_get_rx_queue_depth(const spi_host_t *spi) {
-    volatile uint32_t status_reg = spi_get_status(spi);
-    return bitfield_field32_read(status_reg, SPI_HOST_STATUS_RXQD_FIELD);
+spi_return_flags_e spi_get_errors_enabled(spi_host_t* spi, spi_error_e* errors) 
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    *errors = bitfield_read(SPI_HW(spi)->ERROR_ENABLE, SPI_ERROR_IRQALL, SPI_ERRORS_INDEX);
+    return SPI_FLAG_OK;
 }
 
-volatile spi_ch_status_t spi_get_rx_channel_status(const spi_host_t *spi) {
-    volatile uint32_t status_reg = spi_get_status(spi);
-    spi_ch_status_t ch_status = {
-        .empty = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_RXEMPTY_BIT),
-        .full = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_RXFULL_BIT),
-        .stall = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_RXSTALL_BIT),
-        .wm = bitfield_bit32_read(status_reg, SPI_HOST_STATUS_RXWM_BIT)
-    };
-    return ch_status;
+spi_return_flags_e spi_set_errors_enabled(spi_host_t* spi, spi_error_e errors, bool enable)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    if (errors > SPI_ERROR_IRQALL) return SPI_FLAG_ERROR_INVALID;
+    // Since spi_error_e is mapped to ERROR_ENABLE: | = set, & ~ = clear
+    if (enable) SPI_HW(spi)->ERROR_ENABLE |= errors;
+    else        SPI_HW(spi)->ERROR_ENABLE &= ~errors;
+
+    return SPI_FLAG_OK;
+}
+
+spi_return_flags_e spi_get_errors(spi_host_t* spi, spi_error_e* errors)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    *errors = bitfield_read(SPI_HW(spi)->ERROR_STATUS, SPI_ERROR_ALL, SPI_ERRORS_INDEX);
+    return SPI_FLAG_OK;
+}
+
+spi_return_flags_e spi_acknowledge_errors(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    // Write a one to each bit in ERROR_STATUS to clear these bits
+    SPI_HW(spi)->ERROR_STATUS = bitfield_write(SPI_HW(spi)->ERROR_STATUS, 
+                                               SPI_ERROR_ALL, SPI_ERRORS_INDEX, 
+                                               SPI_ERROR_ALL);
+    // Write a one to INTR_STATE error bit to clear the error
+    SPI_HW(spi)->INTR_STATE   = bitfield_write(SPI_HW(spi)->INTR_STATE, BIT_MASK_1, 
+                                               SPI_HOST_INTR_STATE_ERROR_BIT, true);
+    return SPI_FLAG_OK;
+}
+
+spi_return_flags_e spi_enable_error_intr_test(spi_host_t* spi, bool enable)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    SPI_HW(spi)->INTR_TEST = bitfield_write(SPI_HW(spi)->INTR_TEST, BIT_MASK_1, 
+                                            SPI_HOST_INTR_TEST_ERROR_BIT, enable);
+    return SPI_FLAG_OK;
+}
+
+spi_return_flags_e spi_enable_evt_intr_test(spi_host_t* spi, bool enable)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    SPI_HW(spi)->INTR_TEST = bitfield_write(SPI_HW(spi)->INTR_TEST, BIT_MASK_1, 
+                                            SPI_HOST_INTR_TEST_SPI_EVENT_BIT, enable);
+    return SPI_FLAG_OK;
+}
+
+spi_return_flags_e spi_alert_test_fatal_fault_trigger(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    SPI_HW(spi)->ALERT_TEST = bitfield_write(SPI_HW(spi)->ALERT_TEST, BIT_MASK_1, 
+                                             SPI_HOST_ALERT_TEST_FATAL_FAULT_BIT, true);
+    return SPI_FLAG_OK;
+}
+
+volatile uint8_t spi_get_tx_queue_depth(spi_host_t* spi)
+{
+    // Returning an impossible value (tx fifo is 76 words long...)
+    SPI_NULL_CHECK(spi, UINT8_MAX)
+    return spi_get_status(spi).txqd;
+}
+
+volatile uint8_t spi_get_rx_queue_depth(spi_host_t* spi)
+{
+    // Returning an impossible value (rx fifo is 64 words long...)
+    SPI_NULL_CHECK(spi, UINT8_MAX)
+    return spi_get_status(spi).rxqd;
+}
+
+volatile uint32_t spi_get_csid(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, UINT32_MAX)
+    return SPI_HW(spi)->CSID;
+}
+
+spi_return_flags_e spi_sw_reset(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    // Assert spi reset bit
+    SPI_HW(spi)->CONTROL = bitfield_write(SPI_HW(spi)->CONTROL, BIT_MASK_1, 
+                                          SPI_HOST_CONTROL_SW_RST_BIT, true);
+
+    volatile spi_status_t status = spi_get_status(spi);
+    // Wait for spi active and txqd & rxqd both go to 0
+    while (status.active || status.txqd || status.rxqd);
+    // Deassert spi reset bit
+    SPI_HW(spi)->CONTROL = bitfield_write(SPI_HW(spi)->CONTROL, BIT_MASK_1, 
+                                          SPI_HOST_CONTROL_SW_RST_BIT, false);
+    return SPI_FLAG_OK;
 }
 
-volatile uint32_t spi_get_csid(const spi_host_t *spi) {
-    return mmio_region_read32(spi->base_addr, SPI_HOST_CSID_REG_OFFSET);
+spi_return_flags_e spi_set_enable(spi_host_t* spi, bool enable)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    SPI_HW(spi)->CONTROL = bitfield_write(SPI_HW(spi)->CONTROL, BIT_MASK_1, 
+                                          SPI_HOST_CONTROL_SPIEN_BIT, enable);
+    return SPI_FLAG_OK;
 }
 
-// SPI set functions
+spi_return_flags_e spi_set_tx_watermark(spi_host_t* spi, uint8_t watermark)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    // Check that watermark is not bigger than the fifo size (makes no sense otherwise)
+    if (watermark > SPI_HOST_PARAM_TX_DEPTH) return SPI_FLAG_WATERMARK_EXCEEDS;
 
-void spi_sw_reset(const spi_host_t *spi) {
-    volatile uint32_t ctrl_reg = mmio_region_read32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET);
-    ctrl_reg = bitfield_bit32_write(ctrl_reg, SPI_HOST_CONTROL_SW_RST_BIT, 1);
-    mmio_region_write32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET, ctrl_reg);
+    SPI_HW(spi)->CONTROL = bitfield_write(SPI_HW(spi)->CONTROL, 
+                                          SPI_HOST_CONTROL_TX_WATERMARK_MASK, 
+                                          SPI_HOST_CONTROL_TX_WATERMARK_OFFSET, 
+                                          watermark);
+    return SPI_FLAG_OK;
 }
 
-void spi_set_enable(const spi_host_t *spi, bool enable) {
-    volatile uint32_t ctrl_reg = mmio_region_read32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET);
-    ctrl_reg = bitfield_bit32_write(ctrl_reg, SPI_HOST_CONTROL_SPIEN_BIT, enable);
-    mmio_region_write32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET, ctrl_reg);
+spi_return_flags_e spi_set_rx_watermark(spi_host_t* spi, uint8_t watermark)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    // Check that watermark is not bigger than the fifo size (makes no sense otherwise)
+    if (watermark > SPI_HOST_PARAM_RX_DEPTH) return SPI_FLAG_WATERMARK_EXCEEDS;
+
+    SPI_HW(spi)->CONTROL = bitfield_write(SPI_HW(spi)->CONTROL, 
+                                          SPI_HOST_CONTROL_RX_WATERMARK_MASK, 
+                                          SPI_HOST_CONTROL_RX_WATERMARK_OFFSET, 
+                                          watermark);
+    return SPI_FLAG_OK;
 }
 
-void spi_set_tx_watermark(const spi_host_t *spi, uint8_t watermark) {
-    volatile uint32_t ctrl_reg = mmio_region_read32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET);
-    ctrl_reg = bitfield_field32_write(ctrl_reg, SPI_HOST_CONTROL_TX_WATERMARK_FIELD, watermark);
-    mmio_region_write32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET, ctrl_reg);
+spi_return_flags_e spi_set_configopts(spi_host_t* spi, uint32_t csid, const uint32_t conf_reg)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    if (SPI_CSID_INVALID(csid)) return SPI_FLAG_CSID_INVALID;
+    // Since the configopts registers always follow one after another, offset
+    // by csid times address delta
+    *SPI_CONFIGOPTS_ADDR(spi, csid) = conf_reg;
+    return SPI_FLAG_OK;
 }
 
-void spi_set_rx_watermark(const spi_host_t *spi, uint8_t watermark) {
-    volatile uint32_t ctrl_reg = mmio_region_read32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET);
-    ctrl_reg = bitfield_field32_write(ctrl_reg, SPI_HOST_CONTROL_RX_WATERMARK_FIELD, watermark);
-    mmio_region_write32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET, ctrl_reg);
+spi_return_flags_e spi_get_configopts(spi_host_t* spi, uint32_t csid, uint32_t* conf_reg)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    if (SPI_CSID_INVALID(csid)) return SPI_FLAG_CSID_INVALID;
+    // Since the configopts registers always follow one after another, offset
+    // by csid times address delta
+    *conf_reg = *SPI_CONFIGOPTS_ADDR(spi, csid);
+    return SPI_FLAG_OK;
 }
 
-void spi_set_configopts(const spi_host_t *spi, uint32_t csid, const uint32_t conf_reg) {
-    mmio_region_write32(spi->base_addr, sizeof(uint32_t) * csid + SPI_HOST_CONFIGOPTS_0_REG_OFFSET, conf_reg);
+spi_return_flags_e spi_set_csid(spi_host_t* spi, uint32_t csid)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    if (SPI_CSID_INVALID(csid)) return SPI_FLAG_CSID_INVALID;
+
+    SPI_HW(spi)->CSID = csid;
+    return SPI_FLAG_OK;
 }
 
-void spi_set_csid(const spi_host_t* spi, uint32_t csid) {
-    mmio_region_write32(spi->base_addr, SPI_HOST_CSID_REG_OFFSET, csid);
+spi_return_flags_e spi_set_command(spi_host_t* spi, const uint32_t cmd_reg)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+
+    spi_return_flags_e flags = SPI_FLAG_OK;
+    spi_speed_e speed   = bitfield_read(cmd_reg, SPI_HOST_COMMAND_SPEED_MASK, 
+                                        SPI_HOST_COMMAND_SPEED_OFFSET);
+    spi_dir_e direction = bitfield_read(cmd_reg, SPI_HOST_COMMAND_DIRECTION_MASK, 
+                                        SPI_HOST_COMMAND_DIRECTION_OFFSET);
+
+    // Incompatible speed and direction produces an error
+    if (!spi_validate_cmd(direction, speed))     flags |= SPI_FLAG_SPEED_INVALID;
+    // Writing a command while not ready produces an error
+    if (spi_get_ready(spi) != SPI_TRISTATE_TRUE) flags |= SPI_FLAG_NOT_READY;
+    if (flags) return flags;
+
+    SPI_HW(spi)->COMMAND = cmd_reg;
+    return SPI_FLAG_OK;
 }
 
-void spi_set_command(const spi_host_t *spi, const uint32_t cmd_reg) {
-    mmio_region_write32(spi->base_addr, SPI_HOST_COMMAND_REG_OFFSET, cmd_reg);
+spi_return_flags_e spi_write_word(spi_host_t* spi, uint32_t wdata)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    // Check we're not overflowing
+    if (spi_get_tx_queue_depth(spi) >= SPI_HOST_PARAM_TX_DEPTH) 
+        return SPI_FLAG_TX_QUEUE_FULL;
+    SPI_HW(spi)->TXDATA = wdata;
+    return SPI_FLAG_OK;
 }
 
-void spi_write_word(const spi_host_t *spi, uint32_t wdata) {
-    mmio_region_write32(spi->base_addr, SPI_HOST_TXDATA_REG_OFFSET, wdata);
+spi_return_flags_e spi_write_byte(spi_host_t* spi, uint8_t bdata)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    // Check we're not overflowing
+    if (spi_get_tx_queue_depth(spi) >= SPI_HOST_PARAM_TX_DEPTH) 
+        return SPI_FLAG_TX_QUEUE_FULL;
+    SPI_HW(spi)->TXDATA = bdata;
+    return SPI_FLAG_OK;
 }
 
-void spi_read_word(const spi_host_t *spi, uint32_t* dst) {
-    *dst = mmio_region_read32(spi->base_addr, SPI_HOST_RXDATA_REG_OFFSET);
+spi_return_flags_e spi_read_word(spi_host_t* spi, uint32_t* dst)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    // Check we're not underflowing
+    if (spi_get_rx_queue_depth(spi) == 0) return SPI_FLAG_RX_QUEUE_EMPTY;
+    *dst = SPI_HW(spi)->RXDATA;
+    return SPI_FLAG_OK;
 }
 
-void spi_enable_evt_intr(const spi_host_t *spi, bool enable) {
-    volatile uint32_t intr_enable_reg = mmio_region_read32(spi->base_addr, SPI_HOST_INTR_ENABLE_REG_OFFSET);
-    intr_enable_reg = bitfield_bit32_write(intr_enable_reg, SPI_HOST_INTR_ENABLE_SPI_EVENT_BIT, enable);
-    mmio_region_write32(spi->base_addr, SPI_HOST_INTR_ENABLE_REG_OFFSET, intr_enable_reg);
+spi_return_flags_e spi_enable_evt_intr(spi_host_t* spi, bool enable)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    SPI_HW(spi)->INTR_ENABLE = bitfield_write(SPI_HW(spi)->INTR_ENABLE, BIT_MASK_1, 
+                                              SPI_HOST_INTR_ENABLE_SPI_EVENT_BIT, 
+                                              enable);
+    return SPI_FLAG_OK;
 }
 
-void spi_enable_error_intr(const spi_host_t *spi, bool enable) {
-    volatile uint32_t intr_enable_reg = mmio_region_read32(spi->base_addr, SPI_HOST_INTR_ENABLE_REG_OFFSET);
-    intr_enable_reg = bitfield_bit32_write(intr_enable_reg, SPI_HOST_INTR_STATE_ERROR_BIT, enable);
-    mmio_region_write32(spi->base_addr, SPI_HOST_INTR_ENABLE_REG_OFFSET, intr_enable_reg);
+spi_return_flags_e spi_enable_error_intr(spi_host_t* spi, bool enable)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    SPI_HW(spi)->INTR_ENABLE = bitfield_write(SPI_HW(spi)->INTR_ENABLE, BIT_MASK_1, 
+                                              SPI_HOST_INTR_STATE_ERROR_BIT, 
+                                              enable);
+    return SPI_FLAG_OK;
 }
 
-void spi_enable_rxwm_intr(const spi_host_t *spi, bool enable) {
-    volatile uint32_t intr_enable_reg = mmio_region_read32(spi->base_addr, SPI_HOST_EVENT_ENABLE_REG_OFFSET);
-    intr_enable_reg = bitfield_bit32_write(intr_enable_reg, SPI_HOST_EVENT_ENABLE_RXWM_BIT, enable);
-    mmio_region_write32(spi->base_addr, SPI_HOST_EVENT_ENABLE_REG_OFFSET, intr_enable_reg);
+spi_return_flags_e spi_output_enable(spi_host_t* spi, bool enable)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    SPI_HW(spi)->CONTROL = bitfield_write(SPI_HW(spi)->CONTROL, BIT_MASK_1, 
+                                          SPI_HOST_CONTROL_OUTPUT_EN_BIT, enable);
+    return SPI_FLAG_OK;
 }
 
-void spi_enable_txempty_intr(const spi_host_t *spi, bool enable) {
-    volatile uint32_t intr_enable_reg = mmio_region_read32(spi->base_addr, SPI_HOST_EVENT_ENABLE_REG_OFFSET);
-    intr_enable_reg = bitfield_bit32_write(intr_enable_reg, SPI_HOST_EVENT_ENABLE_TXEMPTY_BIT, enable);
-    mmio_region_write32(spi->base_addr, SPI_HOST_EVENT_ENABLE_REG_OFFSET, intr_enable_reg);
+// PLIC handles SPI Host 2 interrupts
+void handler_irq_spi(uint32_t id)
+{
+    spi_error_e errors;
+    // Get errors and check if error triggered the interrupt
+    spi_get_errors(spi_host2, &errors);
+    if (errors) {
+        // Call either weak error handler in this module, or user implementation
+        spi_intr_handler_error_host2(errors);
+    }
+    else {
+        // If it wasn't an error it must have been an event
+        spi_event_e events;
+        // We need to acknowledge the event to avoid triggering in loop
+        spi_acknowledge_event(spi_host2);
+        spi_get_events(spi_host2, &events);
+        // Call either weak event handler in this module, or user implementation
+        spi_intr_handler_event_host2(events);
+    }
 }
 
-void spi_output_enable(const spi_host_t *spi, bool enable){
-    volatile uint32_t output_enable_reg = mmio_region_read32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET);
-    output_enable_reg = bitfield_bit32_write(output_enable_reg, SPI_HOST_CONTROL_OUTPUT_EN_BIT, enable);
-    mmio_region_write32(spi->base_addr, SPI_HOST_CONTROL_REG_OFFSET, output_enable_reg);
+// FIC SPI Host 1 interrupt handler
+void fic_irq_spi(void)
+{
+    spi_error_e errors;
+    // Get errors and check if error triggered the interrupt
+    spi_get_errors(spi_host1, &errors);
+    if (errors) {
+        // Call either weak error handler in this module, or user implementation
+        spi_intr_handler_error_host(errors);
+    }
+    else {
+        // If it wasn't an error it must have been an event
+        spi_event_e events;
+        // We need to acknowledge the event to avoid triggering in loop
+        spi_acknowledge_event(spi_host1);
+        spi_get_events(spi_host1, &events);
+        // Call either weak event handler in this module, or user implementation
+        spi_intr_handler_event_host(events);
+    }
 }
 
-__attribute__((weak, optimize("O0"))) void handler_irq_spi(uint32_t id)
+// FIC SPI Flash interrupt handler
+void fic_irq_spi_flash(void)
 {
- // Replace this function with a non-weak implementation
-}
\ No newline at end of file
+    spi_error_e errors;
+    // Get errors and check if error triggered the interrupt
+    spi_get_errors(spi_flash, &errors);
+    if (errors) {
+        // Call either weak error handler in this module, or user implementation
+        spi_intr_handler_error_flash(errors);
+    }
+    else {
+        // If it wasn't an error it must have been an event
+        spi_event_e events;
+        // We need to acknowledge the event to avoid triggering in loop
+        spi_acknowledge_event(spi_flash);
+        spi_get_events(spi_flash, &events);
+        // Call either weak event handler in this module, or user implementation
+        spi_intr_handler_event_flash(events);
+    }
+}
+
+__attribute__((weak, optimize("O0"))) void spi_intr_handler_event_flash(spi_event_e events) {
+
+}
+
+__attribute__((weak, optimize("O0"))) void spi_intr_handler_error_flash(spi_error_e errors) {
+
+}
+
+__attribute__((weak, optimize("O0"))) void spi_intr_handler_event_host(spi_event_e events) {
+
+}
+
+__attribute__((weak, optimize("O0"))) void spi_intr_handler_error_host(spi_error_e errors) {
+
+}
+
+__attribute__((weak, optimize("O0"))) void spi_intr_handler_event_host2(spi_event_e events) {
+
+}
+
+__attribute__((weak, optimize("O0"))) void spi_intr_handler_error_host2(spi_error_e errors) {
+
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            LOCAL FUNCTIONS                               */
+/**                                                                        **/
+/****************************************************************************/
+
+spi_return_flags_e spi_get_events(spi_host_t* spi, spi_event_e* events) {
+    // This function is somewhat a little cheat. Since there is no hardware implementation
+    // telling which event triggered the interrupt, we just read the status register and
+    // map the statuses to their respective event. This allows to pass a pseudo-event
+    // variable to the event handlers.
+    volatile spi_status_t status = spi_get_status(spi);
+    // Also, we do not need any NULL check since this function is made to be called
+    // __ONLY__ from `handler_irq_spi`, `fic_irq_spi`, `fic_irq_spi_flash`.
+    // Therefore we know that spi argument will not be NULL.
+    *events = bitfield_write(*events, BIT_MASK_1, 
+                             SPI_HOST_EVENT_ENABLE_RXFULL_BIT,  status.rxfull);
+    *events = bitfield_write(*events, BIT_MASK_1, 
+                             SPI_HOST_EVENT_ENABLE_TXEMPTY_BIT, status.txempty);
+    *events = bitfield_write(*events, BIT_MASK_1, 
+                             SPI_HOST_EVENT_ENABLE_RXWM_BIT,    status.rxwm);
+    *events = bitfield_write(*events, BIT_MASK_1, 
+                             SPI_HOST_EVENT_ENABLE_TXWM_BIT,    status.txwm);
+    *events = bitfield_write(*events, BIT_MASK_1, 
+                             SPI_HOST_EVENT_ENABLE_READY_BIT,   status.ready);
+    *events = bitfield_write(*events, BIT_MASK_1, 
+                             SPI_HOST_EVENT_ENABLE_IDLE_BIT,   ~status.active);
+    return SPI_FLAG_OK;
+}
+
+spi_return_flags_e spi_acknowledge_event(spi_host_t* spi) {
+    // We do not need any NULL check since this function is made to be called
+    // __ONLY__ from `handler_irq_spi`, `fic_irq_spi`, `fic_irq_spi_flash`.
+    // Therefore we know that spi argument will not be NULL.
+    SPI_HW(spi)->INTR_STATE = bitfield_write(SPI_HW(spi)->INTR_STATE, BIT_MASK_1, 
+                                             SPI_HOST_INTR_STATE_SPI_EVENT_BIT, true);
+    return SPI_FLAG_OK;
+}
+#ifdef __cplusplus
+}
+#endif
+/****************************************************************************/
+/**                                                                        **/
+/*                                 EOF                                      */
+/**                                                                        **/
+/****************************************************************************/
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h
index af81fe21..6eef81b9 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/spi_host/spi_host.h
@@ -1,360 +1,1014 @@
-// Copyright EPFL contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
+/*
+                              *******************
+******************************* C SOURCE FILE *****************************
+**                            *******************
+**
+** project  : X-HEEP
+** filename : spi_host.h
+** version  : 1
+** date     : 06/03/24
+**
+***************************************************************************
+**
+** Copyright (c) EPFL contributors.
+** All rights reserved.
+**
+***************************************************************************
+*/
 
-// Basic device functions for opentitan SPI host
+/***************************************************************************/
+/***************************************************************************/
+/**
+* @file   spi_host.h
+* @date   06/03/24
+* @author Llorenç Muela
+* @brief  The Serial Peripheral Interface (SPI) driver to set up and use the
+* SPI peripheral
+*/
 
 #ifndef _DRIVERS_SPI_HOST_H_
 #define _DRIVERS_SPI_HOST_H_
 
+/****************************************************************************/
+/**                                                                        **/
+/**                            MODULES USED                                **/
+/**                                                                        **/
+/****************************************************************************/
+
 #include <stdint.h>
+#include <stdbool.h>
+
+#include "fast_intr_ctrl.h"
+#include "rv_plic.h"
+
+#include "spi_host_regs.h"       // Generated
+#include "spi_host_structs.h"    // Generated
+
+/****************************************************************************/
+/**                                                                        **/
+/**                       DEFINITIONS AND MACROS                           **/
+/**                                                                        **/
+/****************************************************************************/
+
+#define SPI_CSID_INVALID(csid)  csid >= SPI_HOST_PARAM_NUM_C_S
+
+#define spi_host1_peri ((volatile spi_host *) SPI_HOST_START_ADDRESS)
+#define spi_host2_peri ((volatile spi_host *) SPI2_START_ADDRESS)
+#define spi_flash_peri ((volatile spi_host *) SPI_FLASH_START_ADDRESS)
+
+#define spi_host1 ((spi_host_t*) spi_host1_peri)
+#define spi_host2 ((spi_host_t*) spi_host2_peri)
+#define spi_flash ((spi_host_t*) spi_flash_peri)
+
+#define SPI_HW(spi_inst) ((volatile spi_host *) spi_inst)
 
-#include "mmio.h"
-#include "spi_host_regs.h"
+// Sanity check to return retval when spi is NULL.
+// For development purposes. If 100% sure spi will NEVER be NULL, comment out
+// the macro expansion to speed up SPI HAL.
+#define SPI_NULL_CHECK(spi,retval) if (spi == NULL) return retval;
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * Initialization parameters for SPI.
- *
- */
-typedef struct spi {
-    /**
-    * The base address for the SPI hardware registers.
-    */
-    mmio_region_t base_addr;
-} spi_host_t;
+/****************************************************************************/
+/**                                                                        **/
+/**                       TYPEDEFS AND STRUCTURES                          **/
+/**                                                                        **/
+/****************************************************************************/
 
 /**
-* SPI channel status structure
+* SPI endianness
 */
-typedef struct spi_ch_status {
-    bool empty : 1;
-    bool full  : 1;
-    bool wm    : 1;
-    bool stall : 1;
-} spi_ch_status_t;
+typedef enum {
+    SPI_BYTE_ORDER_BIG_ENDIAN      = 0,
+    SPI_BYTE_ORDER_LITTLE_ENDIAN   = 1
+} spi_byte_order_e;
 
 /**
 * SPI speed type
 */
 typedef enum {
-    kSpiSpeedStandard   = 0,
-    kSpiSpeedDual       = 1,
-    kSpiSpeedQuad       = 2
+    SPI_SPEED_STANDARD   = 0,
+    SPI_SPEED_DUAL       = 1,
+    SPI_SPEED_QUAD       = 2
 } spi_speed_e;
 
 /**
 * SPI directionality
 */
 typedef enum {
-    kSpiDirDummy        = 0,
-    kSpiDirRxOnly       = 1,
-    kSpiDirTxOnly       = 2,
-    kSpiDirBidir        = 3
+    SPI_DIR_DUMMY       = 0,
+    SPI_DIR_RX_ONLY     = 1,
+    SPI_DIR_TX_ONLY     = 2,
+    SPI_DIR_BIDIR       = 3
 } spi_dir_e;
 
+/**
+* SPI events
+*/
+typedef enum {
+    SPI_EVENT_NONE      = 0,
+    // Triggers event when RX becomes full
+    SPI_EVENT_RXFULL    = (1 << SPI_HOST_EVENT_ENABLE_RXFULL_BIT),
+    // Triggers event when TX becomes empty
+    SPI_EVENT_TXEMPTY   = (1 << SPI_HOST_EVENT_ENABLE_TXEMPTY_BIT),
+    // Triggers event when RX goes above watermark
+    SPI_EVENT_RXWM      = (1 << SPI_HOST_EVENT_ENABLE_RXWM_BIT),
+    // Triggers event when TX falls below watermark
+    SPI_EVENT_TXWM      = (1 << SPI_HOST_EVENT_ENABLE_TXWM_BIT),
+    // Triggers event as soon as SPI Host IP is ready to receive more commands
+    SPI_EVENT_READY     = (1 << SPI_HOST_EVENT_ENABLE_READY_BIT),
+    // Triggers event as soon as SPI Host IP is not processing any command
+    SPI_EVENT_IDLE      = (1 << SPI_HOST_EVENT_ENABLE_IDLE_BIT),
+    // All the above mentioned events
+    SPI_EVENT_ALL       = (1 << SPI_HOST_EVENT_ENABLE_IDLE_BIT+1) - 1
+} spi_event_e;
+
+/**
+* SPI errors
+*/
+typedef enum {
+    SPI_ERROR_NONE          = 0,
+    // Triggers error interrupt whenever a command is issued while busy.
+    SPI_ERROR_CMDBUSY       = (1 << SPI_HOST_ERROR_ENABLE_CMDBUSY_BIT),
+    // Triggers error interrupt whenever the TX FIFO overflows.
+    SPI_ERROR_OVERFLOW      = (1 << SPI_HOST_ERROR_ENABLE_OVERFLOW_BIT),
+    // Triggers error interrupt whenever there is a read from RXDATA but the RX 
+    // FIFO is empty. 
+    SPI_ERROR_UNDERFLOW     = (1 << SPI_HOST_ERROR_ENABLE_UNDERFLOW_BIT),
+    // Triggers error interrupt whenever a command is sent with invalid values for 
+    // COMMAND.SPEED or COMMAND.DIRECTION.
+    SPI_ERROR_CMDINVAL      = (1 << SPI_HOST_ERROR_ENABLE_CMDINVAL_BIT),
+    // Triggers error interrupt whenever a command is submitted, but CSID exceeds 
+    // NumCS.
+    SPI_ERROR_CSIDINVAL     = (1 << SPI_HOST_ERROR_ENABLE_CSIDINVAL_BIT),
+    // INDICATES that TLUL attempted to write to TXDATA with no bytes enabled.
+    // This error cannot be set (enabled or disabled).
+    // This error should never happen since it is the hardware that controls this.
+    SPI_ERROR_ACCESSINVAL   = (1 << SPI_HOST_ERROR_STATUS_ACCESSINVAL_BIT),
+    // All the above mentioned errors that can be set.
+    SPI_ERROR_IRQALL        = (1 << SPI_HOST_ERROR_ENABLE_CSIDINVAL_BIT+1) - 1,
+    // All the above mentioned errors.
+    SPI_ERROR_ALL           = (1 << SPI_HOST_ERROR_STATUS_ACCESSINVAL_BIT+1) - 1
+} spi_error_e;
+
+/**
+* SPI functions return flags, informs user what problem there was or if all OK
+*/
+typedef enum {
+    // Everithing went well
+    SPI_FLAG_OK                 = 0x0000,
+    // The SPI variabled passed was a null pointer
+    SPI_FLAG_NULL_PTR           = 0x0001,
+    // The Watermark exceeded SPI_HOST_PARAM_TX_DEPTH or SPI_HOST_PARAM_RX_DEPTH 
+    // and was therefore not set
+    SPI_FLAG_WATERMARK_EXCEEDS  = 0x0002,
+    // The CSID was out of the bounds specified inSPI_HOST_PARAM_NUM_C_S 
+    SPI_FLAG_CSID_INVALID       = 0x0004,
+    // The CMD FIFO is currently full so couldn't write command
+    SPI_FLAG_COMMAND_FULL       = 0x0008,
+    // The specified speed is not valid so couldn't write command
+    SPI_FLAG_SPEED_INVALID      = 0x0010,
+    // The TX Queue is full, thus could not write to TX register
+    SPI_FLAG_TX_QUEUE_FULL      = 0x0020,
+    // The RX Queue is empty, thus could not read from RX register
+    SPI_FLAG_RX_QUEUE_EMPTY     = 0x0040,
+    // The SPI is not ready
+    SPI_FLAG_NOT_READY          = 0x0080,
+    // The event to enable is not a valid event
+    SPI_FLAG_EVENT_INVALID      = 0x0100,
+    // The error irq to enable is not a valid error irq
+    SPI_FLAG_ERROR_INVALID      = 0x0200 
+} spi_return_flags_e;
+
+/**
+* Extended bool to return if a function catched an error
+*/
+typedef enum {
+    SPI_TRISTATE_ERROR  = 0,
+    SPI_TRISTATE_TRUE   = 1,
+    SPI_TRISTATE_FALSE  = 2
+} spi_tristate_e;
+
+/**
+ * Opaque structure definition to hide the registers.
+ */
+typedef struct spi_s spi_host_t;
+
 /**
 * SPI chip (slave) configuration structure
 */
-typedef struct spi_configopts {
+typedef struct spi_configopts_s {
+    // The clock divider to use with a paricular slave
     uint16_t clkdiv     : 16;
-    uint8_t  csnidle    : 4;
+    // Indicates the minimum number of sck half-cycles to hold cs_n high between 
+    // commands
+    uint8_t  csnidle    : 4; 
+    // Indicates the number of half sck cycles, CSNTRAIL+1, to leave between last 
+    // edge of sck and the rising edge of cs_n
     uint8_t  csntrail   : 4;
+    // Indicates the number of half sck cycles, CSNLEAD+1, to leave between the 
+    // falling edge of cs_n and the first edge of sck
     uint8_t  csnlead    : 4;
+    // Will be ignored by hardware
     bool     __rsvd0    : 1;
+    // If 1 data is sampled a full cycle after shifting data out, instead of half cycle
     bool     fullcyc    : 1;
+    // If 0 data lines change on trailing edge and sample done on leading edge, 
+    // if 1 it is the opposite
     bool     cpha       : 1;
+    // If 0 sck is low when idle, and emits high pulses. If 1 sck is high when idle, 
+    // and emits of low pulses
     bool     cpol       : 1;
 } spi_configopts_t;
 
 /**
 * SPI command structure
 */
-typedef struct spi_command {
+typedef struct spi_command_s {
+    // Length-1 in bytes for the command to transmit/receive
     uint32_t    len         : 24;
+    // Keep CS line active after command has finished (allows to instruct series 
+    // of commands)
     bool        csaat       : 1;
+    // Speed of communication
     spi_speed_e speed       : 2;
+    // Direction of communication
     spi_dir_e   direction   : 2;
 } spi_command_t;
 
-// SPI registers access functions
+/**
+* SPI status structure
+*/
+typedef struct spi_status_s {
+    union {
+        struct {
+            // TX queue depth (how many unsent words are in the FIFO)
+            uint8_t txqd        : 8;
+            // RX queue depth (how many unread words are in the FIFO)
+            uint8_t rxqd        : 8;
+            // CMD queue depth (how many unprocessed commands are in the FIFO)
+            uint8_t cmdqd       : 4;
+            // Indicates wether rxqd is above the RX Watermark
+            bool    rxwm        : 1;
+            // Not used
+            bool    __rsvd0     : 1;
+            // The endianness of the SPI Peripheral
+            bool    byteorder   : 1;
+            // Indicates if the SPI still still has more data to read but the RX FIFO is full
+            bool    rxstall     : 1;
+            // Indicates RX FIFO is empty
+            bool    rxempty     : 1;
+            // Indicates RX FIFO is full
+            bool    rxfull      : 1;
+            // Indicates wether txqd is below the TX Watermark
+            bool    txwm        : 1;
+            // Indicates if the SPI still has more data to send but the TX FIFO is empty
+            bool    txstall     : 1;
+            // Indicates TX FIFO is empty
+            bool    txempty     : 1;
+            // Indicates TX FIFO is full
+            bool    txfull      : 1;
+            // Indicates if the SPI peripheral is currently processing a command
+            bool    active      : 1;
+            // Indicates if the SPI peripheral is ready to receive more commands
+            bool    ready       : 1;
+        };
+        uint32_t value; // This allows accessing all the bitfields as a single 32-bit integer
+    };
+} spi_status_t;
+
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED VARIABLES                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED FUNCTIONS                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Get enabled events for a specified SPI peripheral.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param events Pointer to store enabled event interrupts.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
+ */
+spi_return_flags_e spi_get_events_enabled(spi_host_t* spi, spi_event_e* events);
+
+/**
+ * @brief Set enabled events for a specified SPI peripheral.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param events Pointer to events to enable/disable and to store the currently enabled
+ *               event interrupts.
+ * @param enable Flag to enable (true) or disable (false) the specified event interrupts.
+ * @return SPI_FLAG_NULL_PTR      if spi NULL pointer.
+ * @return SPI_FLAG_EVENT_INVALID if events not valid.
+ * @return SPI_FLAG_OK            if success.
+ */
+spi_return_flags_e spi_set_events_enabled(spi_host_t* spi, spi_event_e events, bool enable);
+
+/**
+ * @brief Get enabled error interrupts for a specified SPI peripheral.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param errors Pointer to store enabled error interrupts.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
+ */
+spi_return_flags_e spi_get_errors_enabled(spi_host_t* spi, spi_error_e* errors);
+
+/**
+ * @brief Set enabled error interrupts for a specified SPI peripheral.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param errors Pointer to error interrupts to enable/disable and to store the currently
+ *               enabled error interrupts.
+ * @param enable Flag to enable (true) or disable (false) the specified error interrupts.
+ * @return SPI_FLAG_NULL_PTR      if spi NULL pointer.
+ * @return SPI_FLAG_ERROR_INVALID if errors not valid.
+ * @return SPI_FLAG_OK            if success.
+ */
+spi_return_flags_e spi_set_errors_enabled(spi_host_t* spi, spi_error_e errors, bool enable);
 
 /**
- * Read the TX FIFO depth register.
+ * @brief Get the errors that have raised if any.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @return TX FIFO depth.
+ * @param errors Pointer to store the errors.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-volatile uint8_t spi_get_tx_queue_depth(const spi_host_t *spi);
+spi_return_flags_e spi_get_errors(spi_host_t* spi, spi_error_e* errors);
 
 /**
- * Read the TX channel status register.
+ * @brief Acknoledge the errors that have raised once solved in order to renable 
+ *        the SPI peripheral operation.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @return TX channel status structure.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-volatile spi_ch_status_t spi_get_tx_channel_status(const spi_host_t *spi);
+spi_return_flags_e spi_acknowledge_errors(spi_host_t* spi);
 
 /**
- * Read the RX FIFO depth register.
+ * @brief Enable or disable error interrupt test mode for a specified SPI peripheral.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @return RX FIFO depth.
+ * @param enable Flag to enable (true) or disable (false) error interrupt test mode.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-volatile uint8_t spi_get_rx_queue_depth(const spi_host_t *spi);
+spi_return_flags_e spi_enable_error_intr_test(spi_host_t* spi, bool enable);
 
 /**
- * Read the RX channel status register.
+ * @brief Enable or disable event interrupt test mode for a specified SPI peripheral.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @return RX channel status structure.
+ * @param enable Flag to enable (true) or disable (false) event interrupt test mode.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-volatile spi_ch_status_t spi_get_rx_channel_status(const spi_host_t *spi);
+spi_return_flags_e spi_enable_evt_intr_test(spi_host_t* spi, bool enable);
 
 /**
- * Read the Chip Select (CS) ID register.
+ * @brief Trigger a fatal fault test alert for a specified SPI peripheral.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @return Chip Select (CS) ID.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-volatile uint32_t spi_get_csid(const spi_host_t *spi);
+spi_return_flags_e spi_alert_test_fatal_fault_trigger(spi_host_t* spi);
 
 /**
- * Reset the SPI from software.
+ * @brief Read the TX FIFO depth register.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return TX FIFO depth. UINT8_MAX if spi is NULL.
  */
-void spi_sw_reset(const spi_host_t *spi);
+volatile uint8_t spi_get_tx_queue_depth(spi_host_t* spi);
 
 /**
- * Enable the SPI host.
+ * @brief Read the RX FIFO depth register.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return RX FIFO depth. UINT8_MAX if spi is NULL.
+ */
+volatile uint8_t spi_get_rx_queue_depth(spi_host_t* spi);
+
+/**
+ * @brief Read the Chip Select (CS) ID register.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return Chip Select (CS) ID. UINT32_MAX if spi is NULL.
+ */
+volatile uint32_t spi_get_csid(spi_host_t* spi);
+
+/**
+ * @brief Reset the SPI from software.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
+ */
+spi_return_flags_e spi_sw_reset(spi_host_t* spi);
+
+/**
+ * @brief Enable the SPI host.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param enable SPI enable register value.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-void spi_set_enable(const spi_host_t *spi, bool enable);
+spi_return_flags_e spi_set_enable(spi_host_t* spi, bool enable);
 
 /**
- * Set the transmit queue watermark level (to enable interrupt triggering).
+ * @brief Set the transmit queue watermark level (to enable interrupt triggering).
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param watermark Queue/fifo trigger level (minimum level).
+ * @return SPI_FLAG_NULL_PTR          if spi NULL pointer.
+ * @return SPI_FLAG_WATERMARK_EXCEEDS if watermark exceeds max (currently 76).
+ * @return SPI_FLAG_OK                if success.
  */
-void spi_set_tx_watermark(const spi_host_t *spi, uint8_t watermark);
+spi_return_flags_e spi_set_tx_watermark(spi_host_t* spi, uint8_t watermark);
 
 /**
- * Set the receive queue watermark level (to enable interrupt triggering).
+ * @brief Set the receive queue watermark level (to enable interrupt triggering).
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param watermark Queue/fifo trigger level (maximum level).
+ * @return SPI_FLAG_NULL_PTR          if spi NULL pointer.
+ * @return SPI_FLAG_WATERMARK_EXCEEDS if watermark exceeds max (currently 64).
+ * @return SPI_FLAG_OK                if success.
  */
-void spi_set_rx_watermark(const spi_host_t *spi, uint8_t watermark);
+spi_return_flags_e spi_set_rx_watermark(spi_host_t* spi, uint8_t watermark);
 
 /**
- * Set the requirement of a target device (i.e., a slave).
+ * @brief Set the requirement of a target device (slave).
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param csid Chip Select (CS) ID.
- * @param conf_reg Slave transmission configuration.
+ * @param conf_reg Slave configuration.
+ * @return SPI_FLAG_NULL_PTR     if spi NULL pointer.
+ * @return SPI_FLAG_CSID_INVALID if csid out of range.
+ * @return SPI_FLAG_OK           if success.
  */
-void spi_set_configopts(const spi_host_t *spi, uint32_t csid, uint32_t conf_reg);
+spi_return_flags_e spi_set_configopts(spi_host_t* spi, uint32_t csid, const uint32_t conf_reg);
 
 /**
- * Select which device to target with the next command.
+ * @brief Get the requirement of a target device (slave).
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param csid Chip Select (CS) ID.
+ * @param conf_reg Where slave configuration gets stored.
+ * @return SPI_FLAG_NULL_PTR     if spi NULL pointer.
+ * @return SPI_FLAG_CSID_INVALID if csid out of range.
+ * @return SPI_FLAG_OK           if success.
+ */
+spi_return_flags_e spi_get_configopts(spi_host_t* spi, uint32_t csid, uint32_t* conf_reg);
+
+/**
+ * @brief Select which device to target with the next command.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param csid Chip Select (SC) ID.
+ * @return SPI_FLAG_NULL_PTR     if spi NULL pointer.
+ * @return SPI_FLAG_CSID_INVALID if csid out of range.
+ * @return SPI_FLAG_OK           if success.
  */
-void spi_set_csid(const spi_host_t *spi, uint32_t csid);
+spi_return_flags_e spi_set_csid(spi_host_t* spi, uint32_t csid);
 
 /**
- * Set the next command (one for all attached SPI devices).
+ * @brief Set the next command (one for all attached SPI devices).
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param cmd_reg Command register value (Length, speed, ...).
+ * @return SPI_FLAG_NULL_PTR      if spi NULL pointer.
+ * @return SPI_FLAG_SPEED_INVALID if direction and speed incompatible.
+ * @return SPI_FLAG_NOT_READY     if SPI Host not ready.
+ * @return SPI_FLAG_OK            if success.
  */
-void spi_set_command(const spi_host_t *spi, uint32_t cmd_reg);
+spi_return_flags_e spi_set_command(spi_host_t* spi, uint32_t cmd_reg);
 
 /**
- * Write one word to the TX FIFO.
+ * @brief Write one word to the TX FIFO.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param wdata Data to write.
+ * @return SPI_FLAG_NULL_PTR      if spi NULL pointer.
+ * @return SPI_FLAG_TX_QUEUE_FULL if TX FIFO is full.
+ * @return SPI_FLAG_OK            if success.
+ */
+spi_return_flags_e spi_write_word(spi_host_t* spi, uint32_t wdata);
+
+/**
+ * @brief Write a byte of data to the transmit queue of a specified SPI peripheral.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param bdata Byte of data to write.
+ * @return SPI_FLAG_NULL_PTR      if spi NULL pointer.
+ * @return SPI_FLAG_TX_QUEUE_FULL if TX FIFO is full.
+ * @return SPI_FLAG_OK            if success.
  */
-void spi_write_word(const spi_host_t *spi, uint32_t wdata);
+spi_return_flags_e spi_write_byte(spi_host_t* spi, uint8_t bdata);
 
 /**
- * Read one word to the RX FIFO.
+ * @brief Read one word to the RX FIFO.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param rdata Read data.
+ * @return SPI_FLAG_NULL_PTR       if spi NULL pointer.
+ * @return SPI_FLAG_RX_QUEUE_EMPTY if RX FIFO is empty.
+ * @return SPI_FLAG_OK             if success.
  */
-void spi_read_word(const spi_host_t *spi, uint32_t* dst);
+spi_return_flags_e spi_read_word(spi_host_t* spi, uint32_t* dst);
 
 /**
- * Enable SPI event interrupt
+ * @brief Enable SPI event interrupt
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param enable SPI event interrupt bit value.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-void spi_enable_evt_intr(const spi_host_t *spi, bool enable);
+spi_return_flags_e spi_enable_evt_intr(spi_host_t* spi, bool enable);
 
 /**
- * Enable SPI error interrupt
+ * @brief Enable SPI error interrupt
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
  * @param enable SPI error interrupt bit value.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
+ */
+spi_return_flags_e spi_enable_error_intr(spi_host_t* spi, bool enable);
+
+/**
+ * @brief Enable SPI output
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @param enable SPI TX empty interrupt bit value.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-void spi_enable_error_intr(const spi_host_t *spi, bool enable);
+spi_return_flags_e spi_output_enable(spi_host_t* spi, bool enable);
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          INLINE FUNCTIONS                              **/
+/**                                                                        **/
+/****************************************************************************/
 
 /**
- * Enable SPI watermark event interrupt
+ * @brief Check if a given direction and speed are compatible.
+ * i.e. bidirectional communication only possible at standard speed
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @param enable SPI RX watermark interrupt bit value.
+ * @param direction spi_dir_e direction of communication.
+ * @param speed spi_speed_e speed of communication.
+ * @return true if compatible false otherwise.
  */
-void spi_enable_rxwm_intr(const spi_host_t *spi, bool enable);
+static inline __attribute__((always_inline)) 
+bool spi_validate_cmd(uint8_t direction, uint8_t speed)
+{
+    if (speed > SPI_SPEED_QUAD || direction > SPI_DIR_BIDIR || 
+       (direction == SPI_DIR_BIDIR && speed != SPI_SPEED_STANDARD))
+        return false;
+    else 
+        return true;
+}
 
 /**
- * Enable SPI TX empty event interrupt
+ * @brief Get the state of the event interrupt flag (indicates if event has been 
+ *        triggered).
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @param enable SPI TX empty interrupt bit value.
+ * @return SPI_TRISTATE_ERROR if null pointer, else SPI_TRISTATE_TRUE if flag active 
+ *         or SPI_TRISTATE_FALSE if not active.
  */
-void spi_enable_txempty_intr(const spi_host_t *spi, bool enable);
+static inline __attribute__((always_inline)) 
+spi_tristate_e spi_get_evt_intr_state(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_TRISTATE_ERROR)
+
+    if (bitfield_read(SPI_HW(spi)->INTR_STATE, BIT_MASK_1, 
+                      SPI_HOST_INTR_STATE_SPI_EVENT_BIT))
+        return SPI_TRISTATE_TRUE;
+    else
+        return SPI_TRISTATE_FALSE;
+}
 
 /**
- * Enable SPI output
+ * @brief Get the state of the error interrupt flag (indicates if error has been 
+ *        triggered).
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
- * @param enable SPI TX empty interrupt bit value.
+ * @return SPI_TRISTATE_ERROR if null pointer, else SPI_TRISTATE_TRUE if flag active 
+ *         or SPI_TRISTATE_FALSE if not active.
+ */
+static inline __attribute__((always_inline)) 
+spi_tristate_e spi_get_error_intr_state(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_TRISTATE_ERROR)
+
+    if (bitfield_read(SPI_HW(spi)->INTR_STATE, BIT_MASK_1,
+                      SPI_HOST_INTR_STATE_ERROR_BIT))
+        return SPI_TRISTATE_TRUE;
+    else
+        return SPI_TRISTATE_FALSE;
+}
+
+/**
+ * @brief Check if event interrupts are enabled.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_TRISTATE_ERROR if null pointer, else SPI_TRISTATE_TRUE if enabled 
+ *         or SPI_TRISTATE_FALSE otherwise.
+ */
+static inline __attribute__((always_inline))
+spi_tristate_e spi_get_evt_intr_enable(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_TRISTATE_ERROR)
+
+    if (bitfield_read(SPI_HW(spi)->INTR_ENABLE, BIT_MASK_1,
+                      SPI_HOST_INTR_ENABLE_SPI_EVENT_BIT))
+        return SPI_TRISTATE_TRUE;
+    else
+        return SPI_TRISTATE_FALSE;
+}
+
+/**
+ * @brief Check if error interrupts are enabled.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_TRISTATE_ERROR if null pointer, else SPI_TRISTATE_TRUE if enabled 
+ *         or SPI_TRISTATE_FALSE otherwise.
+ */
+static inline __attribute__((always_inline))
+spi_tristate_e spi_get_error_intr_enable(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_TRISTATE_ERROR)
+
+    if (bitfield_read(SPI_HW(spi)->INTR_ENABLE, BIT_MASK_1,
+                      SPI_HOST_INTR_ENABLE_ERROR_BIT))
+        return SPI_TRISTATE_TRUE;
+    else
+        return SPI_TRISTATE_FALSE;
+}
+
+/**
+ * @brief Read SPI status register
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return Pointer to spi_status_t structure. NULL if spi is NULL.
+ */
+static inline __attribute__((always_inline)) 
+const volatile spi_status_t spi_get_status(spi_host_t* spi)
+{
+    spi_status_t status;
+    status.value = SPI_HW(spi)->STATUS; // Assuming SPI_HW(spi)->STATUS returns a uint32_t value representing the status
+    return status;
+}
+
+/**
+ * @brief Read SPI active bit from status register (indicates if SPI peripheral 
+ *        is currently processing a command)
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_TRISTATE_ERROR if null pointer, else SPI_TRISTATE_TRUE if active 
+ *         or SPI_TRISTATE_FALSE otherwise.
+ */
+static inline __attribute__((always_inline)) 
+spi_tristate_e spi_get_active(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_TRISTATE_ERROR)
+    //return spi_get_status(spi)->active ? SPI_TRISTATE_TRUE : SPI_TRISTATE_FALSE;
+    spi_status_t spi_status;
+    spi_status.value = 0x00;
+    spi_status.value = SPI_HW(spi)->STATUS;
+}
+
+/**
+ * @brief Read SPI ready bit from status register (indicates if SPI peripheral 
+ *        is ready to receive more commands)
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_TRISTATE_ERROR if null pointer, else SPI_TRISTATE_TRUE if ready 
+ *         or SPI_TRISTATE_FALSE otherwise.
  */
-void spi_output_enable(const spi_host_t *spi, bool enable);
+static inline __attribute__((always_inline)) 
+spi_tristate_e spi_get_ready(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_TRISTATE_ERROR)
+    return spi_get_status(spi).ready ? SPI_TRISTATE_TRUE : SPI_TRISTATE_FALSE;
+}
 
+/**
+ * @brief Wait SPI is ready to receive commands.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
+ */
+static inline __attribute__((always_inline)) 
+spi_return_flags_e spi_wait_for_ready(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (spi_get_ready(spi) == SPI_TRISTATE_FALSE);
+    return SPI_FLAG_OK;
+}
 
-// Inline functions
+/**
+ * @brief Wait SPI is no longer processing commands.
+ *
+ * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
+ */
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_idle(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (spi_get_active(spi) == SPI_TRISTATE_TRUE);
+    return SPI_FLAG_OK;
+}
 
 /**
- * Read SPI status register
+ * @brief Wait CMD FIFO not full.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) volatile uint32_t spi_get_status(const spi_host_t *spi) {
-    return mmio_region_read32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET);
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_cmdqd_not_full(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (spi_get_status(spi).cmdqd >= SPI_HOST_PARAM_CMD_DEPTH);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Read SPI active bit from status register
+ * @brief Wait TX FIFO reach watermark.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) volatile bool spi_get_active(const spi_host_t *spi) {
-    volatile uint32_t status_reg = spi_get_status(spi);
-    return bitfield_bit32_read(status_reg, SPI_HOST_STATUS_ACTIVE_BIT);
+static inline __attribute__((always_inline)) 
+spi_return_flags_e spi_wait_for_tx_watermark(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (!spi_get_status(spi).txwm);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Read SPI ready bit from status register
+ * @brief Wait TX FIFO empty.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) volatile bool spi_get_ready(const spi_host_t *spi) {
-    volatile uint32_t status_reg = spi_get_status(spi);
-    return bitfield_bit32_read(status_reg, SPI_HOST_STATUS_READY_BIT);
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_tx_empty(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (!spi_get_status(spi).txempty);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Wait SPI is ready to receive commands.
+ * @brief Wait TX FIFO not empty.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) void spi_wait_for_ready(const spi_host_t *spi) {
-    while (!spi_get_ready(spi));
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_tx_not_empty(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (spi_get_status(spi).txempty);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Wait TX FIFO reach watermark.
+ * @brief Wait TX FIFO not full.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) void spi_wait_for_tx_watermark(const spi_host_t *spi) {
-    while (!mmio_region_get_bit32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET, SPI_HOST_STATUS_TXWM_BIT));
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_tx_not_full(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (spi_get_status(spi).txfull);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Wait TX FIFO empty.
+ * @brief Wait RX FIFO empty.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) void spi_wait_for_tx_empty(const spi_host_t *spi) {
-    while (!mmio_region_get_bit32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET, SPI_HOST_STATUS_TXEMPTY_BIT));
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_rx_empty(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (!spi_get_status(spi).rxempty);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Wait TX FIFO not empty.
+ * @brief Wait RX FIFO not empty.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) void spi_wait_for_tx_not_empty(const spi_host_t *spi) {
-    while (mmio_region_get_bit32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET, SPI_HOST_STATUS_TXEMPTY_BIT));
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_rx_not_empty(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (spi_get_status(spi).rxempty);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Wait TX FIFO not full.
+ * @brief Wait RX FIFO full.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) void spi_wait_for_tx_not_full(const spi_host_t *spi) {
-    while (mmio_region_get_bit32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET, SPI_HOST_STATUS_TXFULL_BIT));
+static inline __attribute__((always_inline))
+spi_return_flags_e spi_wait_for_rx_full(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (!spi_get_status(spi).rxfull);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Wait RX FIFO reach watermark.
+ * @brief Wait RX FIFO reach watermark.
  *
  * @param spi Pointer to spi_host_t representing the target SPI.
+ * @return SPI_FLAG_NULL_PTR if spi NULL pointer.
+ * @return SPI_FLAG_OK       if success.
  */
-static inline __attribute__((always_inline)) void spi_wait_for_rx_watermark(const spi_host_t *spi) {
-    while (!mmio_region_get_bit32(spi->base_addr, SPI_HOST_STATUS_REG_OFFSET, SPI_HOST_STATUS_RXWM_BIT));
+static inline __attribute__((always_inline)) 
+spi_return_flags_e spi_wait_for_rx_watermark(spi_host_t* spi)
+{
+    SPI_NULL_CHECK(spi, SPI_FLAG_NULL_PTR)
+    while (!spi_get_status(spi).rxwm);
+    return SPI_FLAG_OK;
 }
 
 /**
- * Create SPI target device configuration word.
+ * @brief Create SPI target device configuration word.
  *
  * @param configopts Target device configuation structure.
+ * @return uint32 representing the configopts.
  */
-static inline __attribute__((always_inline)) __attribute__((const)) uint32_t spi_create_configopts(const spi_configopts_t configopts) {
+static inline __attribute__((always_inline)) __attribute__((const))
+uint32_t spi_create_configopts(const spi_configopts_t configopts)
+{
     uint32_t conf_reg = 0;
-    conf_reg = bitfield_field32_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CLKDIV_0_FIELD, configopts.clkdiv);
-    conf_reg = bitfield_field32_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CSNIDLE_0_FIELD, configopts.csnidle);
-    conf_reg = bitfield_field32_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CSNTRAIL_0_FIELD, configopts.csntrail);
-    conf_reg = bitfield_field32_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CSNLEAD_0_FIELD, configopts.csnlead);
-    conf_reg = bitfield_bit32_write(conf_reg, SPI_HOST_CONFIGOPTS_0_FULLCYC_0_BIT, configopts.fullcyc);
-    conf_reg = bitfield_bit32_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CPHA_0_BIT, configopts.cpha);
-    conf_reg = bitfield_bit32_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CPOL_0_BIT, configopts.cpol);
+    conf_reg = bitfield_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CLKDIV_0_MASK, 
+                              SPI_HOST_CONFIGOPTS_0_CLKDIV_0_OFFSET, configopts.clkdiv);
+    conf_reg = bitfield_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CSNIDLE_0_MASK, 
+                              SPI_HOST_CONFIGOPTS_0_CSNIDLE_0_OFFSET, configopts.csnidle);
+    conf_reg = bitfield_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CSNTRAIL_0_MASK, 
+                              SPI_HOST_CONFIGOPTS_0_CSNTRAIL_0_OFFSET, configopts.csntrail);
+    conf_reg = bitfield_write(conf_reg, SPI_HOST_CONFIGOPTS_0_CSNLEAD_0_MASK, 
+                              SPI_HOST_CONFIGOPTS_0_CSNLEAD_0_OFFSET, configopts.csnlead);
+    conf_reg = bitfield_write(conf_reg, BIT_MASK_1, 
+                              SPI_HOST_CONFIGOPTS_0_FULLCYC_0_BIT, configopts.fullcyc);
+    conf_reg = bitfield_write(conf_reg, BIT_MASK_1, 
+                              SPI_HOST_CONFIGOPTS_0_CPHA_0_BIT, configopts.cpha);
+    conf_reg = bitfield_write(conf_reg, BIT_MASK_1,
+                              SPI_HOST_CONFIGOPTS_0_CPOL_0_BIT, configopts.cpol);
     return conf_reg;
 }
 
 /**
- * Create SPI command word.
+ * @brief Convert SPI target device configuration word to spi_configopts_t structure.
+ *
+ * @param configopts Target device configuation structure.
+ * @return spi_configopts_t representing the config_reg.
+ */
+static inline __attribute__((always_inline)) __attribute__((const))
+spi_configopts_t spi_create_configopts_structure(const uint32_t config_reg)
+{
+    spi_configopts_t configopts = {
+        .clkdiv   = bitfield_read(config_reg, SPI_HOST_CONFIGOPTS_0_CLKDIV_0_MASK, 
+                                  SPI_HOST_CONFIGOPTS_0_CLKDIV_0_OFFSET),
+        .csnidle  = bitfield_read(config_reg, SPI_HOST_CONFIGOPTS_0_CSNIDLE_0_MASK, 
+                                  SPI_HOST_CONFIGOPTS_0_CSNIDLE_0_OFFSET),
+        .csntrail = bitfield_read(config_reg, SPI_HOST_CONFIGOPTS_0_CSNTRAIL_0_MASK, 
+                                  SPI_HOST_CONFIGOPTS_0_CSNTRAIL_0_OFFSET),
+        .csnlead  = bitfield_read(config_reg, SPI_HOST_CONFIGOPTS_0_CSNLEAD_0_MASK, 
+                                  SPI_HOST_CONFIGOPTS_0_CSNLEAD_0_OFFSET),
+        .fullcyc  = bitfield_read(config_reg, BIT_MASK_1, 
+                                  SPI_HOST_CONFIGOPTS_0_FULLCYC_0_BIT),
+        .cpha     = bitfield_read(config_reg, BIT_MASK_1, 
+                                  SPI_HOST_CONFIGOPTS_0_CPHA_0_BIT),
+        .cpol     = bitfield_read(config_reg, BIT_MASK_1, 
+                                  SPI_HOST_CONFIGOPTS_0_CPOL_0_BIT)
+    };
+    return configopts;
+}
+
+/**
+ * @brief Create SPI command word.
  *
  * @param command Command configuration structure.
+ * @return uint32 representing the command.
  */
-static inline __attribute__((always_inline)) __attribute__((const)) uint32_t spi_create_command(const spi_command_t command) {
+static inline __attribute__((always_inline)) __attribute__((const))
+uint32_t spi_create_command(const spi_command_t command)
+{
     uint32_t cmd_reg = 0;
-    cmd_reg = bitfield_field32_write(cmd_reg, SPI_HOST_COMMAND_LEN_FIELD, command.len);
-    cmd_reg = bitfield_bit32_write(cmd_reg, SPI_HOST_COMMAND_CSAAT_BIT, command.csaat);
-    cmd_reg = bitfield_field32_write(cmd_reg, SPI_HOST_COMMAND_SPEED_FIELD, command.speed);
-    cmd_reg = bitfield_field32_write(cmd_reg, SPI_HOST_COMMAND_DIRECTION_FIELD, command.direction);
+    cmd_reg = bitfield_write(cmd_reg, SPI_HOST_COMMAND_LEN_MASK, 
+                             SPI_HOST_COMMAND_LEN_OFFSET, command.len);
+    cmd_reg = bitfield_write(cmd_reg, BIT_MASK_1, 
+                             SPI_HOST_COMMAND_CSAAT_BIT, command.csaat);
+    cmd_reg = bitfield_write(cmd_reg, SPI_HOST_COMMAND_SPEED_MASK, 
+                             SPI_HOST_COMMAND_SPEED_OFFSET, command.speed);
+    cmd_reg = bitfield_write(cmd_reg, SPI_HOST_COMMAND_DIRECTION_MASK, 
+                             SPI_HOST_COMMAND_DIRECTION_OFFSET, command.direction);
     return cmd_reg;
 }
 
 /**
- * @brief Attends the plic interrupt.
+ * @brief Attends the plic interrupt for SPI Host 2.
  */
-__attribute__((weak, optimize("O0"))) void handler_irq_spi(uint32_t id);
+void handler_irq_spi(uint32_t id);
+
+/**
+ * @brief Attends the fic interrupt for SPI Host.
+ */
+void fic_irq_spi(void);
+
+/**
+ * @brief Attends the fic interrupt for SPI Flash.
+ */
+void fic_irq_spi_flash(void);
+
+/**
+ * @brief weak implementation of the function that gets called when an event 
+ *        interrupt is triggered on the SPI Flash.
+ *        Replace with your own implementation.
+ */
+void spi_intr_handler_event_flash(spi_event_e events);
+
+/**
+ * @brief weak implementation of the function that gets called when an error 
+ *        interrupt is triggered on the SPI Flash.
+ *        Replace with your own implementation.
+ */
+void spi_intr_handler_error_flash(spi_error_e errors);
+
+/**
+ * @brief weak implementation of the function that gets called when an event 
+ *        interrupt is triggered on the SPI Host.
+ *        Replace with your own implementation.
+ */
+void spi_intr_handler_event_host(spi_event_e events);
+
+/**
+ * @brief weak implementation of the function that gets called when an error 
+ *        interrupt is triggered on the SPI Host.
+ *        Replace with your own implementation.
+ */
+void spi_intr_handler_error_host(spi_error_e errors);
+
+/**
+ * @brief weak implementation of the function that gets called when an event 
+ *        interrupt is triggered on the SPI Host 2.
+ *        Replace with your own implementation.
+ */
+void spi_intr_handler_event_host2(spi_event_e events);
+
+/**
+ * @brief weak implementation of the function that gets called when an error 
+ *        interrupt is triggered on the SPI Host 2.
+ *        Replace with your own implementation.
+ */
+void spi_intr_handler_error_host2(spi_error_e errors);
 
 
 #ifdef __cplusplus
@@ -362,3 +1016,9 @@ __attribute__((weak, optimize("O0"))) void handler_irq_spi(uint32_t id);
 #endif
 
 #endif // _DRIVERS_SPI_HOST_H_
+
+/****************************************************************************/
+/**                                                                        **/
+/**                                EOF                                     **/
+/**                                                                        **/
+/****************************************************************************/
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/uart/uart.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/uart/uart.c
index 08a32fa7..fef349c4 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/uart/uart.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/uart/uart.c
@@ -4,12 +4,14 @@
 
 // Modified version for core-v-mini-mcu
 // original at: https://github.com/lowRISC/opentitan/blob/master/sw/
-
+#ifdef __cplusplus
+extern "C" {
+#endif
 #include "uart.h"
 
 #include <stddef.h>
 #include <stdint.h>
-
+#include "assert.h"
 #include "bitfield.h"
 #include "mmio.h"
 #include "error.h"
@@ -17,8 +19,12 @@
 #include "uart_regs.h"  // Generated.
 
 #define NCO_WIDTH 16
-_Static_assert((1UL << NCO_WIDTH) - 1 == UART_CTRL_NCO_MASK,
-               "Bad value for NCO_WIDTH");
+
+//#ifdef __cplusplus
+static_assert((1UL << NCO_WIDTH) - 1 == UART_CTRL_NCO_MASK, "Bad value for NCO_WIDTH");
+//#else
+static_assert((1UL << NCO_WIDTH) - 1 == UART_CTRL_NCO_MASK, "Bad value for NCO_WIDTH");
+//#endif
 
 static void uart_reset(const uart_t *uart) {
   mmio_region_write32(uart->base_addr, UART_CTRL_REG_OFFSET, 0u);
@@ -147,4 +153,8 @@ size_t uart_sink(void *uart, const char *data, size_t len) {
 __attribute__((weak, optimize("O0"))) void handler_irq_uart(uint32_t id)
 {
  // Replace this function with a non-weak implementation
-}
\ No newline at end of file
+}
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
index 2bfec7d9..710cf02e 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
@@ -9,11 +9,17 @@
 extern "C" {
 #endif  // __cplusplus
 
-#define MEMORY_BANKS ${ram_numbanks}
-% if ram_numbanks_il > 0:
+#define MEMORY_BANKS ${xheep.ram_numbanks()}
+% if xheep.has_il_ram():
 #define HAS_MEMORY_BANKS_IL
 % endif
 
+% for bank in xheep.iter_ram_banks():
+#define RAM${bank.name()}_START_ADDRESS 0x${f'{bank.start_address():08X}'}
+#define RAM${bank.name()}_END_ADDRESS 0x${f'{bank.end_address():08X}'}
+% endfor
+
+
 #define EXTERNAL_DOMAINS ${external_domains}
 
 #define DEBUG_START_ADDRESS 0x${debug_start_address}
@@ -29,9 +35,13 @@ extern "C" {
 #define ${name.upper()}_START_ADDRESS (AO_PERIPHERAL_START_ADDRESS + 0x${peripheral['offset']})
 #define ${name.upper()}_SIZE 0x${peripheral['length']}
 #define ${name.upper()}_END_ADDRESS (${name.upper()}_START_ADDRESS + ${name.upper()}_SIZE)
+#define ${name.upper()}_IDX ${loop.index}
 
 %endfor
 
+#define DMA_CH_NUM ${dma_ch_count}
+#define DMA_CH_SIZE 0x${dma_ch_size}
+
 //switch-on/off peripherals
 #define PERIPHERAL_START_ADDRESS 0x${peripheral_start_address}
 #define PERIPHERAL_SIZE 0x${peripheral_size_address}
@@ -41,6 +51,7 @@ extern "C" {
 #define ${name.upper()}_START_ADDRESS (PERIPHERAL_START_ADDRESS + 0x${peripheral['offset']})
 #define ${name.upper()}_SIZE 0x${peripheral['length']}
 #define ${name.upper()}_END_ADDRESS (${name.upper()}_START_ADDRESS + ${name.upper()}_SIZE)
+#define ${name.upper()}_IDX ${loop.index + len(ao_peripherals.items())}
 % if "yes" in peripheral['is_included']:
 #define ${name.upper()}_IS_INCLUDED
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
new file mode 100644
index 00000000..02a99da5
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu_memory.h.tpl
@@ -0,0 +1,29 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#ifndef COREV_MINI_MCU_MEMORY_H_
+#define COREV_MINI_MCU_MEMORY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+#include "core_v_mini_mcu.h"
+
+typedef struct memory_address {
+    unsigned int start;
+    unsigned int end;
+} xheep_memory_address_t;
+
+xheep_memory_address_t xheep_memory_regions[MEMORY_BANKS] = {
+% for bank in xheep.iter_ram_banks():
+    {.start = RAM${bank.name()}_START_ADDRESS, .end = RAM${bank.name()}_END_ADDRESS},
+% endfor
+};
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif  // __cplusplus
+
+#endif  // COREV_MINI_MCU_MEMORY_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c
index c9cd02d3..564abdcd 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.c
@@ -2,6 +2,10 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
 #include "handler.h"
 #include "csr.h"
 #include "stdasm.h"
@@ -110,3 +114,7 @@ __attribute__((weak)) void handler_ecall(void) {
   while (1) {
   }
 }
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.h
index 8f987be7..1aaacc3b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/handler.h
@@ -5,6 +5,10 @@
 #ifndef OPENTITAN_SW_DEVICE_LIB_HANDLER_H_
 #define OPENTITAN_SW_DEVICE_LIB_HANDLER_H_
 
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
 typedef enum exc_id {
   kInstMisa = 0,
   kInstAccFault = 1,
@@ -126,4 +130,9 @@ void handler_lsu_fault(void);
  */
 void handler_ecall(void);
 
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
+
 #endif  // OPENTITAN_SW_DEVICE_LIB_HANDLER_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h
index c2e885c0..9759edfb 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h
@@ -5,6 +5,11 @@
 #ifndef OPENTITAN_SW_DEVICE_LIB_RUNTIME_HART_H_
 #define OPENTITAN_SW_DEVICE_LIB_RUNTIME_HART_H_
 
+#ifdef __cplusplus
+extern "C" {
+#endif  // __cplusplus
+
+
 #include <stddef.h>
 #include <stdnoreturn.h>
 
@@ -24,4 +29,9 @@
  */
 inline void wait_for_interrupt(void) { asm volatile("wfi"); }
 
+
+#ifdef __cplusplus
+}
+#endif  // __cplusplus
+
 #endif  // OPENTITAN_SW_DEVICE_LIB_RUNTIME_HART_H_
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/heap.cpp b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/heap.cpp
new file mode 100644
index 00000000..d4c8fd8b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/heap.cpp
@@ -0,0 +1,60 @@
+/*
+* Copyright 2024 Anestis Athanasiadis
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*     http://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+//Additional heap functions required for C++
+
+#include <cstdlib>
+#include <new>
+
+void* operator new(size_t size) noexcept
+{
+    return malloc(size);
+}
+
+void operator delete(void *p) noexcept
+{
+    free(p);
+}
+
+void* operator new[](size_t size) noexcept
+{
+    return operator new(size); // Same as regular new
+}
+
+void operator delete[](void *p) noexcept
+{
+    operator delete(p); // Same as regular delete
+}
+
+void* operator new(size_t size, std::nothrow_t) noexcept
+{
+    return operator new(size); // Same as regular new
+}
+
+void operator delete(void *p,  std::nothrow_t) noexcept
+{
+    operator delete(p); // Same as regular delete
+}
+
+void* operator new[](size_t size, std::nothrow_t) noexcept
+{
+    return operator new(size); // Same as regular new
+}
+
+void operator delete[](void *p,  std::nothrow_t) noexcept
+{
+    operator delete(p); // Same as regular delete
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/init.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/init.c
index cfbf206a..ad29fca6 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/init.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/init.c
@@ -1,7 +1,16 @@
 // Copyright 2022 OpenHW Group
 // Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 int init()
 {
     return 0;
-}
\ No newline at end of file
+}
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c
index a9a7fcc2..8e516af0 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls.c
@@ -17,8 +17,13 @@
  * PERFORMANCE OF THIS SOFTWARE.
  */
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include <sys/stat.h>
-#include <string.h>
+#include <string.h> 
+#include <sys/reent.h>
 #include <newlib.h>
 #include <unistd.h>
 #include <reent.h>
@@ -46,6 +51,7 @@ int     _link (const char *__path1, const char *__path2);
 _off_t  _lseek (int __fildes, _off_t __offset, int __whence);
 ssize_t _read (int __fd, void *__buf, size_t __nbyte);
 void *  _sbrk (ptrdiff_t __incr);
+int     _brk(void *addr);
 int     _unlink (const char *__path);
 ssize_t _write (int __fd, const void *__buf, size_t __nbyte);
 int     _execve (const char *__path, char * const __argv[], char * const __envp[]);
@@ -259,9 +265,13 @@ ssize_t _write(int file, const void *ptr, size_t len)
         errno = ENOSYS;
         return -1;
     }
-
     return uart_write(&uart,(uint8_t *)ptr,len);
+}
+
 
+_ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t cnt)
+{
+    return _write(fd,buf,cnt);
 }
 
 extern char __heap_start[];
@@ -270,8 +280,12 @@ static char *brk = __heap_start;
 
 int _brk(void *addr)
 {
-    brk = addr;
-    return 0;
+    if (addr >= (void *)__heap_start && addr <= (void *)__heap_end) {
+        brk = addr;
+        return 0; 
+    } else {
+        return -1; 
+    }
 }
 
 void *_sbrk(ptrdiff_t incr)
@@ -279,13 +293,27 @@ void *_sbrk(ptrdiff_t incr)
     char *old_brk = brk;
 
     if (__heap_start == __heap_end) {
-        return NULL;
+        return NULL; 
     }
 
-    if ((brk += incr) < __heap_end) {
+    if (brk + incr < __heap_end && brk + incr >= __heap_start) {
         brk += incr;
     } else {
-        brk = __heap_end;
+        return (void *)-1; 
     }
     return old_brk;
 }
+
+int raise(int sig)
+{
+    return _kill(_getpid(), sig);
+}
+
+void abort(void)
+{
+    _exit(-1);
+}
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls_cpp.cpp b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls_cpp.cpp
new file mode 100644
index 00000000..3385fcb5
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/syscalls_cpp.cpp
@@ -0,0 +1,39 @@
+/*
+* Copyright 2024 Anestis Athanasiadis
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*     http://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+
+// This function is required to register the call for the destructor
+// of static object
+extern "C" int __aeabi_atexit(void *object, void (*destructor)(void *),void *dso_handle)
+{
+    static_cast<void>(object);
+    static_cast<void>(destructor);
+    static_cast<void>(dso_handle);
+    return 0;
+}
+
+void operator delete(void *,unsigned int)
+{
+}
+
+// Required when there is pure virtual function
+extern "C" void __cxa_pure_virtual()
+{
+    while (true) {}
+}
+
+
+void *__dso_handle = 0;
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c
new file mode 100644
index 00000000..67371531
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c
@@ -0,0 +1,100 @@
+// Copyright 2024 EPFL and Politecnico di Torino.
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: dma_sdk.c
+// Author: Michele Caon, Luigi Giuffrida
+// Date: 19/06/2023
+// Description: Utility functions for DMA peripheral.
+
+#include "dma_sdk.h"
+#include "dma.h"
+#include "hart.h"
+#include "handler.h"
+#include "fast_intr_ctrl.h"
+#include "core_v_mini_mcu.h"
+#include "csr.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+    /******************************/
+    /* ---- GLOBAL VARIABLES ---- */
+    /******************************/
+
+    volatile uint8_t dma_sdk_intr_flag;
+
+#define DMA_REGISTER_SIZE_BYTES sizeof(int)
+#define DMA_SELECTION_OFFSET_START 0
+
+/* Mask for direct register operations */
+#define DMA_CSR_REG_MIE_MASK ((1 << 19) | (1 << 11))
+
+    /**********************************/
+    /* ---- FUNCTION DEFINITIONS ---- */
+    /**********************************/
+
+    static __attribute__((always_inline)) void dma_start(dma *peri, uint32_t size, dma_data_type_t src_type)
+    {
+        peri->SIZE_D1 = (uint32_t)((size * DMA_DATA_TYPE_2_SIZE(src_type)) & DMA_SIZE_D1_SIZE_MASK);
+    }
+
+    // Initialize the DMA
+    void dma_sdk_init(void)
+    {
+        dma_init(NULL);
+
+        /* Enable global interrupts */
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+        /* Enable fast interrupts */
+        CSR_SET_BITS(CSR_REG_MIE, DMA_CSR_REG_MIE_MASK);
+
+        return;
+    }
+
+    void dma_copy(uint32_t dst_ptr, uint32_t src_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data)
+    {
+        volatile dma *the_dma = dma_peri(channel);
+        DMA_COPY(dst_ptr, src_ptr, size, src_type, dst_type, signed_data, the_dma);
+        dma_start(the_dma, size, src_type);
+        DMA_WAIT(channel);
+        return;
+    }
+
+    void dma_fill(uint32_t dst_ptr, uint32_t value_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data)
+    {
+        volatile dma *the_dma = dma_peri(channel);
+        DMA_FILL(dst_ptr, value_ptr, size, src_type, dst_type, signed_data, the_dma);
+        dma_start(the_dma, size, src_type);
+        DMA_WAIT(channel);
+        return;
+    }
+
+    void __attribute__ ((noinline)) dma_copy_async(uint32_t dst_ptr, uint32_t src_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data)
+    {
+        volatile dma *the_dma = dma_peri(channel);
+        DMA_COPY(dst_ptr, src_ptr, size, src_type, dst_type, signed_data, the_dma);
+        dma_start(the_dma, size, src_type);
+        return;
+    }
+
+    void __attribute__ ((noinline)) dma_fill_async(uint32_t dst_ptr, uint32_t value_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data)
+    {
+        volatile dma *the_dma = dma_peri(channel);
+        DMA_FILL(dst_ptr, value_ptr, size, src_type, dst_type, signed_data, the_dma);
+        dma_start(the_dma, size, src_type);
+        return;
+    }
+
+    void __attribute__ ((noinline)) dma_wait(uint8_t channel)
+    {
+        DMA_WAIT(channel);
+        return;
+    }
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.h
new file mode 100644
index 00000000..726024e0
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.h
@@ -0,0 +1,108 @@
+// Copyright 2024 EPFL and Politecnico di Torino.
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: dma_sdk.h
+// Author: Michele Caon, Luigi Giuffrida
+// Date: 19/06/2023
+// Description: DMA utility functions
+
+#ifndef DMA_SDK_H_
+#define DMA_SDK_H_
+
+#include <stdint.h>
+#include <stddef.h> // for size_t
+#include "csr.h"
+
+#include "dma.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif // __cplusplus
+
+#define INCREMENT(TYPE) ((TYPE == DMA_DATA_TYPE_BYTE) ? 1 : (TYPE == DMA_DATA_TYPE_HALF_WORD) ? 2 \
+                                                                                              : 4)
+
+#define DMA_COPY(DST, SRC, SIZE, SRC_TYPE, DST_TYPE, SIGNED, DMA_PERI)                        \
+    DMA_PERI->INTERRUPT_EN = (uint32_t)0x1;                                                   \
+    DMA_PERI->SRC_PTR = (uint32_t)SRC;                                                        \
+    DMA_PERI->DST_PTR = (uint32_t)DST;                                                        \
+    DMA_PERI->SRC_PTR_INC_D1 = (uint32_t)(INCREMENT(SRC_TYPE) & DMA_SRC_PTR_INC_D1_INC_MASK); \
+    DMA_PERI->DST_PTR_INC_D1 = (uint32_t)(INCREMENT(DST_TYPE) & DMA_DST_PTR_INC_D1_INC_MASK); \
+    DMA_PERI->MODE = (uint32_t)(DMA_TRANS_MODE_SINGLE & DMA_MODE_MODE_MASK);                  \
+    DMA_PERI->SRC_DATA_TYPE = (uint32_t)(SRC_TYPE & DMA_SRC_DATA_TYPE_DATA_TYPE_MASK);        \
+    DMA_PERI->DST_DATA_TYPE = (uint32_t)(DST_TYPE & DMA_DST_DATA_TYPE_DATA_TYPE_MASK);        \
+    DMA_PERI->SIGN_EXT = (uint32_t)SIGNED;
+
+#define DMA_FILL(DST, VALUE_PTR, SIZE, SRC_TYPE, DST_TYPE, SIGNED, DMA_PERI)                  \
+    DMA_PERI->INTERRUPT_EN = (uint32_t)0x1;                                                   \
+    DMA_PERI->SRC_PTR = (uint32_t)VALUE_PTR;                                                  \
+    DMA_PERI->DST_PTR = (uint32_t)DST;                                                        \
+    DMA_PERI->SRC_PTR_INC_D1 = (uint32_t)0;                                                   \
+    DMA_PERI->DST_PTR_INC_D1 = (uint32_t)(INCREMENT(DST_TYPE) & DMA_DST_PTR_INC_D1_INC_MASK); \
+    DMA_PERI->MODE = (uint32_t)(DMA_TRANS_MODE_SINGLE & DMA_MODE_MODE_MASK);                  \
+    DMA_PERI->SRC_DATA_TYPE = (uint32_t)(SRC_TYPE & DMA_SRC_DATA_TYPE_DATA_TYPE_MASK);        \
+    DMA_PERI->DST_DATA_TYPE = (uint32_t)(DST_TYPE & DMA_DST_DATA_TYPE_DATA_TYPE_MASK);        \
+    DMA_PERI->SIGN_EXT = (uint32_t)SIGNED;
+
+#define DMA_WAIT(CH)                          \
+    while (!dma_is_ready(CH))                 \
+    {                                         \
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8); \
+        if (dma_is_ready(CH) == 0)            \
+        {                                     \
+            wait_for_interrupt();             \
+        }                                     \
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);   \
+    }
+
+    /********************************/
+    /* ---- EXPORTED VARIABLES ---- */
+    /********************************/
+
+    extern volatile uint8_t dma_sdk_intr_flag;
+
+    /**
+     * @brief Initializes the DMA SDK.
+     *
+     * This function initializes the DMA SDK and prepares it for use.
+     */
+    void __attribute__((noinline)) dma_sdk_init(void);
+
+    /**
+     * @brief Copies data from source to destination using DMA.
+     *
+     * @param dst_ptr   Pointer to the destination memory location.
+     * @param src_ptr   Pointer to the source memory location.
+     * @param size      Size of the data to be copied in bytes.
+     * @param channel   DMA channel to be used for the transfer.
+     * @param src_type  Source variable type (byte, half-word, word).
+     * @param dst_type  Destination variable type (byte, half-word, word).
+     * @param signed_data  Indicates whether the data is signed or unsigned.
+     */
+    void __attribute__((noinline)) dma_copy(uint32_t dst_ptr, uint32_t src_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data);
+
+    /**
+     * @brief Fills a memory region with a specified value using DMA.
+     *
+     * @param dst_ptr   Pointer to the destination memory location.
+     * @param value_ptr Pointer to the value to be filled.
+     * @param size      Size of the memory region to be filled in bytes.
+     * @param channel   DMA channel to be used for the transfer.
+     * @param src_type  Source variable type (byte, half-word, word).
+     * @param dst_type  Destination variable type (byte, half-word, word).
+     * @param signed_data  Indicates whether the data is signed or unsigned.
+     */
+    void __attribute__((noinline)) dma_fill(uint32_t dst_ptr, uint32_t value_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data);
+
+    void __attribute__((noinline)) dma_copy_async(uint32_t dst_ptr, uint32_t src_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data);
+
+    void __attribute__((noinline)) dma_fill_async(uint32_t dst_ptr, uint32_t value_ptr, uint32_t size, uint8_t channel, dma_data_type_t src_type, dma_data_type_t dst_type, uint8_t signed_data);
+
+    void __attribute__((noinline)) dma_wait(uint8_t channel);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif /* DMA_SDK_H_ */
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.c
new file mode 100644
index 00000000..8c8a6a16
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.c
@@ -0,0 +1,1127 @@
+/*
+                              *******************
+******************************* C SOURCE FILE *****************************
+**                            *******************
+**
+** project  : X-HEEP
+** filename : spi_sdk.c
+** version  : 1
+** date     : 18/04/24
+**
+***************************************************************************
+**
+** Copyright (c) EPFL contributors.
+** All rights reserved.
+**
+***************************************************************************
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+/**
+* @file   spi_sdk.c
+* @date   18/04/24
+* @author Llorenç Muela
+* @brief  The Serial Peripheral Interface (SPI) SDK to set up and use the
+* SPI peripheral
+*/
+
+/****************************************************************************/
+/**                                                                        **/
+/**                            MODULES USED                                **/
+/**                                                                        **/
+/****************************************************************************/
+
+#include "spi_sdk.h"
+#include "spi_host.h"
+#include "spi_host_regs.h"
+#include "soc_ctrl_structs.h"
+#include "bitfield.h"
+#include "csr.h"
+
+/****************************************************************************/
+/**                                                                        **/
+/**                       DEFINITIONS AND MACROS                           **/
+/**                                                                        **/
+/****************************************************************************/
+
+#define DATA_MODE_CPHA_OFFS 0
+#define DATA_MODE_CPOL_OFFS 1
+
+#define SPI_MAX_IDX 2
+#define SPI_IDX_INVALID(idx) idx > SPI_MAX_IDX
+
+#define SYS_FREQ      (soc_ctrl_peri->SYSTEM_FREQUENCY_HZ)
+#define SPI_MIN_FREQ  (SYS_FREQ / (2 * 65535 + 2))           // 65535 = 2^16 - 1
+
+// Maximum length of data (in bytes) for a command segment (currently 2^24)
+#define MAX_COMMAND_LENGTH SPI_HOST_COMMAND_LEN_MASK
+#define BYTES_PER_WORD     4
+// Convert byte count to word count
+#define LEN_WORDS(bytes)   ((bytes / BYTES_PER_WORD) + (bytes % BYTES_PER_WORD ? 1 : 0))
+
+// Bitmasks for speed and direction relative to spi_mode_e
+#define DIR_SPD_MASK 0b11
+#define DIR_INDEX    0
+#define SPD_INDEX    2
+
+#define TRIGGERING_EVENTS (SPI_EVENT_IDLE | SPI_EVENT_READY | SPI_EVENT_TXWM | SPI_EVENT_RXWM)
+
+// The standard watermark for all transactions (seems reasonable)
+#define TXWM_DEFAULT (SPI_HOST_PARAM_TX_DEPTH / 4)  // Arbirarily chosen
+#define RXWM_DEFAULT (SPI_HOST_PARAM_RX_DEPTH - 12) // Arbirarily chosen
+
+#define NULL_CALLBACKS (spi_callbacks_t) {NULL, NULL, NULL, NULL}
+
+// SPI peripheral busy checks
+#define SPI_BUSY(peri)     (peri.state == SPI_STATE_BUSY)
+#define SPI_NOT_BUSY(peri) (peri.state != SPI_STATE_BUSY)
+
+// Check command length validity
+#define SPI_INVALID_LEN(len) (len == 0 || len > MAX_COMMAND_LENGTH)
+
+/**
+ * @brief Allows easy TX Transaction instantiation.
+ */
+#define SPI_TXN_TX(segment, txbuff, len) (spi_transaction_t) { \
+    .segments = segment, \
+    .seglen   = 1, \
+    .txbuffer = txbuff, \
+    .txlen    = len, \
+    .rxbuffer = NULL, \
+    .rxlen    = 0 \
+}
+
+/**
+ * @brief Allows easy RX Transaction instantiation.
+ */
+#define SPI_TXN_RX(segment, rxbuff, len) (spi_transaction_t) { \
+    .segments = segment, \
+    .seglen   = 1, \
+    .txbuffer = NULL, \
+    .txlen    = 0, \
+    .rxbuffer = rxbuff, \
+    .rxlen    = len \
+}
+
+/**
+ * @brief Allows easy BIDIR Transaction instantiation.
+ */
+#define SPI_TXN_BIDIR(segment, txbuff, rxbuff, len) (spi_transaction_t) { \
+    .segments = segment, \
+    .seglen   = 1, \
+    .txbuffer = txbuff, \
+    .txlen    = len, \
+    .rxbuffer = rxbuff, \
+    .rxlen    = len \
+}
+
+/**
+ * @brief Allows easy generic Transaction instantiation.
+ */
+#define SPI_TXN(segment, seg_len, txbuff, rxbuff) (spi_transaction_t) { \
+    .segments = segment, \
+    .seglen   = seg_len, \
+    .txbuffer = txbuff, \
+    .txlen    = 0, \
+    .rxbuffer = rxbuff, \
+    .rxlen    = 0 \
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/**                       TYPEDEFS AND STRUCTURES                          **/
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Transaction Structure. Holds all information relevant to a transaction.
+ */
+typedef struct {
+    const spi_segment_t* segments;  // Pointer to array/buffer of command segments
+    uint8_t              seglen;    // Size of the command segents array/buffer
+    const uint32_t*      txbuffer;  // Pointer to array/buffer of TX data
+    uint32_t             txlen;     // Size of TX array/buffer
+    uint32_t*            rxbuffer;  // Pointer to array/buffer for RX data
+    uint32_t             rxlen;     // Size of RX array/buffer
+} spi_transaction_t;
+
+/**
+ * @brief Structure to hold all relative information about a particular peripheral.
+ *  peripherals variable in this file holds an instance of this structure for every
+ *  SPI peripheral defined in the HAL. This is in order to store relevant information
+ *  of the peripheral current status, transaction info, and peripheral instance.
+ */
+typedef struct {
+    spi_host_t*       instance;  // Instance of peripheral defined in HAL
+    uint8_t           txwm;      // TX watermark for this particular peripheral
+    uint8_t           rxwm;      // RX watermark for this particular peripheral
+    uint32_t          last_id;   // ID of last used spi_t to avoid resetting slave
+    uint32_t          timeout;   // Timeout for blocking transactions in ms
+    spi_state_e       state;     // Current state of device
+    spi_transaction_t txn;       // Current transaction being processed
+    uint32_t          scnt;      // Counter to track segment to process
+    uint32_t          txcnt;     // Counter to track TX word being processed
+    uint32_t          rxcnt;     // Counter to track RX word being processed
+    spi_callbacks_t   callbacks; // Callback functions to call
+} spi_peripheral_t;
+
+/****************************************************************************/
+/**                                                                        **/
+/*                      PROTOTYPES OF LOCAL FUNCTIONS                       */
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Validates the idx and init variables of spi_t.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @return spi_codes_e information about error. SPI_CODE_OK if all went well
+ */
+spi_codes_e spi_check_valid(spi_t* spi);
+
+/**
+ * @brief Validates slave csid.
+ * 
+ * @param slave to validate
+ * @return spi_codes_e information about error. SPI_CODE_OK if all went well
+ */
+spi_codes_e spi_validate_slave(spi_slave_t slave);
+
+/**
+ * @brief Sets the slave configuration options and the slave CSID.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @return spi_codes_e information about error. SPI_CODE_OK if all went well
+ */
+spi_codes_e spi_set_slave(spi_t* spi);
+
+/**
+ * @brief Validation and configuration of device prior to any transaction.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @return spi_codes_e information about error. SPI_CODE_OK if all went well
+ */
+spi_codes_e spi_prepare_transfer(spi_t* spi);
+
+/**
+ * @brief Computes the true frequency that will be set based on the user desired 
+ *  frequency.
+ * 
+ * @param freq Frequency defined by user
+ * @return uint32_t True frequency after determining the SPI clk divider
+ */
+uint32_t spi_true_slave_freq(uint32_t freq);
+
+/**
+ * @brief Validates all the provided segments and counts the number of words for
+ *  TX and RX buffers.
+ * 
+ * @param segments An array of segments to validate
+ * @param segments_len The length of the array of segments
+ * @param tx_count Variable to store the counted TX words
+ * @param rx_count Variable to store the counted RX words
+ * @return true if all segments are valid
+ * @return false otherwise
+ */
+bool spi_validate_segments(const spi_segment_t* segments, uint32_t segments_len, 
+                           uint32_t* tx_count, uint32_t* rx_count);
+
+/**
+ * @brief Fills the TX FIFO until no more space or no more data.
+ * 
+ * @param peri Pointer to the spi_peripheral_t instance with the relevant data
+ * @return true if any word has been written to TX fifo
+ * @return false otherwise
+ */
+bool spi_fill_tx(spi_peripheral_t* peri);
+
+/**
+ * @brief Empties the RX FIFO.
+ * 
+ * @param peri Pointer to the spi_peripheral_t instance with the relevant data
+ * @return true if any word has been read to RX fifo
+ * @return false otherwise
+ */
+bool spi_empty_rx(spi_peripheral_t* peri);
+
+/**
+ * @brief Proceeds to initiate transaction once all tests passed.
+ * 
+ * @param peri Pointer to the relevant spi_peripheral_t instance
+ * @param spi Pointer to the spi_t that requested transaction
+ * @param txn Transaction data (segments, buffers, lengths)
+ * @param done_cb The callback to be called once transaction is over
+ * @param error_cb The callback to be called if a Hardware error occurs
+ */
+void spi_launch(spi_peripheral_t* peri, spi_t* spi, spi_transaction_t txn, 
+                spi_callbacks_t callbacks);
+
+/**
+ * @brief Issues a command segment and increments counter (post inc.).
+ *  Determines value of CSAAT bit based on if it is last segment of transaction 
+ *  or not.
+ * 
+ * @param peri Pointer to the relevant spi_peripheral_t instance
+ */
+void spi_wait_transaction_done(spi_peripheral_t* peri);
+
+/**
+ * @brief Issues a command segment and increments counter (post inc.).
+ *  Determines value of CSAAT bit based on if it is last segment of transaction 
+ *  or not.
+ * 
+ * @param peri Pointer to the relevant spi_peripheral_t instance
+ */
+void spi_issue_next_seg(spi_peripheral_t* peri);
+
+/**
+ * @brief Resets the entire peripheral, hardware included
+ * 
+ * @param peri Pointer to the relevant spi_peripheral_t instance
+ */
+void spi_reset_peri(spi_peripheral_t* peri);
+
+/**
+ * @brief Resets the transaction-related variables of the spi_peripheral_t to 
+ *  their initial values
+ * 
+ * @param peri Pointer to the relevant spi_peripheral_t instance
+ */
+void spi_reset_transaction(spi_peripheral_t* peri);
+
+/**
+ * @brief Function that gets called on each Event Interrupt. Handles all the logic
+ *  of a transacton since all transactions use the interrupt.
+ * 
+ * @param peri Pointer to the relevant spi_peripheral_t instance
+ * @param events Variable holding all the current events
+ */
+void spi_event_handler(spi_peripheral_t* peri, spi_event_e events);
+
+/**
+ * @brief Function that handles the harware errors. It is responsible of aborting
+ *  any current transaction, resetting variables and calling the error callback if any.
+ * 
+ * @param peri Pointer to the relevant spi_peripheral_t instance
+ * @param error Variable holding all the errors that occured
+ */
+void spi_error_handler(spi_peripheral_t* peri, spi_error_e error);
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED VARIABLES                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            GLOBAL VARIABLES                              */
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Global SDK spi_t instance counter to assign each instance a unique ID.
+ */
+static uint32_t global_id = 0;
+
+/**
+ * @brief Static variable representing each SPI peripheral (FLASH, HOST, HOST2)
+ *  We can have infinitely many spi_t variables but all reference one of these 
+ *  spi_peripheral_t. Each variable here holds all the relevant information about 
+ *  the current transaction the peripheral is executing.
+ */
+static volatile spi_peripheral_t peripherals[] = {
+    (spi_peripheral_t) {
+        .instance  = spi_flash,
+        .txwm      = TXWM_DEFAULT,
+        .rxwm      = RXWM_DEFAULT,
+        .last_id   = 0,
+        .timeout   = SPI_TIMEOUT_DEFAULT,
+        .state     = SPI_STATE_NONE,
+        .txn       = {0},
+        .scnt      = 0,
+        .txcnt     = 0,
+        .rxcnt     = 0,
+        .callbacks = {0}
+    },
+    (spi_peripheral_t) {
+        .instance  = spi_host1,
+        .txwm      = TXWM_DEFAULT,
+        .rxwm      = RXWM_DEFAULT,
+        .last_id   = 0,
+        .timeout   = SPI_TIMEOUT_DEFAULT,
+        .state     = SPI_STATE_NONE,
+        .txn       = {0},
+        .scnt      = 0,
+        .txcnt     = 0,
+        .rxcnt     = 0,
+        .callbacks = {0}
+    },
+    (spi_peripheral_t) {
+        .instance  = spi_host2,
+        .txwm      = TXWM_DEFAULT,
+        .rxwm      = RXWM_DEFAULT,
+        .last_id   = 0,
+        .timeout   = SPI_TIMEOUT_DEFAULT,
+        .state     = SPI_STATE_NONE,
+        .txn       = {0},
+        .scnt      = 0,
+        .txcnt     = 0,
+        .rxcnt     = 0,
+        .callbacks = {0}
+    }
+};
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED FUNCTIONS                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+spi_t spi_init(spi_idx_e idx, spi_slave_t slave) 
+{
+    // Make sure all parameters of the slave are valid.
+    spi_codes_e error = spi_validate_slave(slave);
+    // Check that the SPI peripheral identifier is valid.
+    if (SPI_IDX_INVALID(idx))       error |= SPI_CODE_IDX_INVAL;
+    // Since watermark is set here, not a good idea to allow for initialization.
+    // Anyways not very elegant to initialize while being busy... right?
+    if (SPI_BUSY(peripherals[idx])) error |= SPI_CODE_IS_BUSY;
+    if (error)
+        return (spi_t) {
+            .idx   = UINT32_MAX,
+            .id    = 0,
+            .init  = false,
+            .slave = (spi_slave_t) {0}
+        };
+    // Enable SPI peripheral. We do not check return value since we know here that
+    // it will never return an error.
+    spi_set_enable(peripherals[idx].instance, true);
+    spi_output_enable(peripherals[idx].instance, true);
+    // Enable all error interrupts so that the SPI peripheral doesn't get stuck if
+    // there is an error. And we don't check return value since we know it's error free.
+    spi_set_errors_enabled(peripherals[idx].instance, SPI_ERROR_IRQALL, true);
+    spi_enable_error_intr(peripherals[idx].instance, true);
+    // Set the watermarks for the specific peripheral
+    spi_set_tx_watermark(peripherals[idx].instance, peripherals[idx].txwm);
+    spi_set_rx_watermark(peripherals[idx].instance, peripherals[idx].rxwm);
+    // Just set a state so user can see it has been initialized somewhen.
+    peripherals[idx].state = SPI_STATE_INIT;
+    // Set the true frequency at which the SCK will be for that particular slave
+    // so the user can know the real frequency.
+    slave.freq = spi_true_slave_freq(slave.freq);
+    return (spi_t) {
+        .idx   = idx,
+        .id    = ++global_id, // Pre-increment because id 0 defined as invalid
+        .init  = true,
+        .slave = slave
+    };
+}
+
+void spi_deinit(spi_t* spi) 
+{
+    // Set all values to something that will prevent spi variable to be used.
+    spi->idx   = UINT32_MAX;
+    spi->id    = 0;
+    spi->init  = false;
+    spi->slave = (spi_slave_t) {0};
+}
+
+spi_codes_e spi_reset(spi_t* spi) 
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+    // Reset entire peripheral
+    spi_reset_peri(&peripherals[spi->idx]);
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_set_txwm(spi_t* spi, uint8_t watermark)
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+    // Do not change watermark if SPI is busy
+    if (SPI_BUSY(peripherals[spi->idx])) return SPI_CODE_IS_BUSY;
+    // Set the new value at hardware level
+    if (spi_set_tx_watermark(peripherals[spi->idx].instance, watermark))
+        return SPI_CODE_WM_EXCEEDS;
+    // Store the watermark if previous operation succeeded
+    peripherals[spi->idx].txwm = watermark;
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_get_txwm(spi_t* spi, uint8_t* watermark)
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+
+    *watermark = peripherals[spi->idx].txwm;
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_set_rxwm(spi_t* spi, uint8_t watermark)
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+    // Do not change watermark if SPI is busy
+    if (SPI_BUSY(peripherals[spi->idx])) return SPI_CODE_IS_BUSY;
+    // Set the new value at hardware level
+    if (spi_set_rx_watermark(peripherals[spi->idx].instance, watermark))
+        return SPI_CODE_WM_EXCEEDS;
+    // Store the watermark if previous operation succeeded
+    peripherals[spi->idx].rxwm = watermark;
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_get_rxwm(spi_t* spi, uint8_t* watermark)
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+
+    *watermark = peripherals[spi->idx].rxwm;
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_set_timeout(spi_t* spi, uint32_t timeout)
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+
+    peripherals[spi->idx].timeout = timeout;
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_get_timeout(spi_t* spi, uint32_t* timeout)
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+
+    *timeout = peripherals[spi->idx].timeout;
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_set_slave_freq(spi_t* spi, uint32_t freq)
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+    // Save current freq and change to new freq to check validity
+    const uint32_t old_freq = spi->slave.freq;
+    spi->slave.freq = freq;
+    error = spi_validate_slave(spi->slave);
+    if (error) {
+        // If not valid reset the frequency and return error
+        spi->slave.freq = old_freq;
+        return error;
+    }
+    // If valid set the true frequency and return OK
+    spi->slave.freq = spi_true_slave_freq(freq);
+    return SPI_CODE_OK;
+}
+
+spi_state_e spi_get_state(spi_t* spi) 
+{
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return SPI_STATE_ARG_INVAL; // The spi parameter passed is invalid
+
+    return peripherals[spi->idx].state;
+}
+
+spi_codes_e spi_transmit(spi_t* spi, const uint32_t* src_buffer, uint32_t len) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    // Check that length doesn't exceed maximum and is not 0
+    if (SPI_INVALID_LEN(len)) error |= SPI_CODE_TXN_LEN_INVAL;
+    if (error) return error;
+
+    // Create command segment for TX transaction
+    spi_segment_t     seg = SPI_SEG_TX(len);
+    // Create the transaction with the created segment
+    spi_transaction_t txn = SPI_TXN_TX(&seg, src_buffer, LEN_WORDS(len));
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. No callbacks since function is blocking.
+    spi_launch(&peripherals[spi->idx], spi, txn, NULL_CALLBACKS);
+
+    spi_wait_transaction_done(&peripherals[spi->idx]);
+    // while (SPI_BUSY(peripherals[spi->idx])) wait_for_interrupt();
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_receive(spi_t* spi, uint32_t* dest_buffer, uint32_t len) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    // Check that length doesn't exceed maximum and is not 0
+    if (SPI_INVALID_LEN(len)) error |= SPI_CODE_TXN_LEN_INVAL;
+    if (error) return error;
+
+    // Create command segment for RX transaction
+    spi_segment_t     seg = SPI_SEG_RX(len);
+    // Create the transaction with the created segment
+    spi_transaction_t txn = SPI_TXN_RX(&seg, dest_buffer, LEN_WORDS(len));
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. No callbacks since function is blocking.
+    spi_launch(&peripherals[spi->idx], spi, txn, NULL_CALLBACKS);
+
+    spi_wait_transaction_done(&peripherals[spi->idx]);
+    // while (SPI_BUSY(peripherals[spi->idx])) wait_for_interrupt();
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_transceive(spi_t* spi, const uint32_t* src_buffer, 
+                           uint32_t* dest_buffer, uint32_t len) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    // Check that length doesn't exceed maximum and is not 0
+    if (SPI_INVALID_LEN(len)) error |= SPI_CODE_TXN_LEN_INVAL;
+    if (error) return error;
+
+    // Create command segment for BIDIR transaction
+    spi_segment_t     seg = SPI_SEG_BIDIR(len);
+    // Create the transaction with the created segment
+    spi_transaction_t txn = SPI_TXN_BIDIR(&seg, src_buffer, dest_buffer, LEN_WORDS(len));
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. No callbacks since function is blocking.
+    spi_launch(&peripherals[spi->idx], spi, txn, NULL_CALLBACKS);
+
+    spi_wait_transaction_done(&peripherals[spi->idx]);
+    // while (SPI_BUSY(peripherals[spi->idx])) wait_for_interrupt();
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_execute(spi_t* spi, const spi_segment_t* segments, 
+                        uint32_t segments_len, const uint32_t* src_buffer, 
+                        uint32_t* dest_buffer) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    if (error) return error;
+
+    // Create the transaction with the provided segments
+    spi_transaction_t txn = SPI_TXN(segments, segments_len, src_buffer, dest_buffer);
+
+    // We check every segment for validity since they are defined by user.
+    // This function also counts the number of words of TX and RX the entire
+    // transaction is composed of.
+    if (!spi_validate_segments(txn.segments, txn.seglen, &txn.txlen, &txn.rxlen)) 
+        return SPI_CODE_SEGMENT_INVAL;
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. No callbacks since function is blocking.
+    spi_launch(&peripherals[spi->idx], spi, txn, NULL_CALLBACKS);
+
+    spi_wait_transaction_done(&peripherals[spi->idx]);
+    // while (SPI_BUSY(peripherals[spi->idx])) wait_for_interrupt();
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_transmit_nb(spi_t* spi, const uint32_t* src_buffer, uint32_t len, 
+                            spi_callbacks_t callbacks) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    // Check that length doesn't exceed maximum and is not 0
+    if (SPI_INVALID_LEN(len)) error |= SPI_CODE_TXN_LEN_INVAL;
+    if (error) return error;
+
+    // Create command segment for TX transaction
+    spi_segment_t     seg = SPI_SEG_TX(len);
+    // Create the transaction with the created segment
+    spi_transaction_t txn = SPI_TXN_TX(&seg, src_buffer, LEN_WORDS(len));
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. Here user callbacks are used because non-blocking function.
+    spi_launch(&peripherals[spi->idx], spi, txn, callbacks);
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_receive_nb(spi_t* spi, uint32_t* dest_buffer, uint32_t len, 
+                           spi_callbacks_t callbacks) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    // Check that length doesn't exceed maximum and is not 0
+    if (SPI_INVALID_LEN(len)) error |= SPI_CODE_TXN_LEN_INVAL;
+    if (error) return error;
+
+    // Create command segment for RX transaction
+    spi_segment_t     seg = SPI_SEG_RX(len);
+    // Create the transaction with the created segment
+    spi_transaction_t txn = SPI_TXN_RX(&seg, dest_buffer, LEN_WORDS(len));
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. Here user callbacks are used because non-blocking function.
+    spi_launch(&peripherals[spi->idx], spi, txn, callbacks);
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_transceive_nb(spi_t* spi, const uint32_t* src_buffer, 
+                              uint32_t* dest_buffer, uint32_t len, 
+                              spi_callbacks_t callbacks) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    // Check that length doesn't exceed maximum and is not 0
+    if (SPI_INVALID_LEN(len)) error |= SPI_CODE_TXN_LEN_INVAL;
+    if (error) return error;
+
+    // Create command segment for BIDIR transaction
+    spi_segment_t     seg = SPI_SEG_BIDIR(len);
+    // Create the transaction with the created segment
+    spi_transaction_t txn = SPI_TXN_BIDIR(&seg, src_buffer, dest_buffer, LEN_WORDS(len));
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. Here user callbacks are used because non-blocking function.
+    spi_launch(&peripherals[spi->idx], spi, txn, callbacks);
+
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_execute_nb(spi_t* spi, const spi_segment_t* segments, 
+                           uint32_t segments_len, const uint32_t* src_buffer, 
+                           uint32_t* dest_buffer, spi_callbacks_t callbacks) 
+{
+    // Make validity checks and set the slave at hardware level
+    spi_codes_e error = spi_prepare_transfer(spi);
+    if (error) return error;
+
+    // Create the transaction with the provided segments
+    spi_transaction_t txn = SPI_TXN(segments, segments_len, src_buffer, dest_buffer);
+
+    // We check every segment for validity since they are defined by user.
+    // This function also counts the number of words of TX and RX the entire
+    // transaction is composed of.
+    if (!spi_validate_segments(txn.segments, txn.seglen, &txn.txlen, &txn.rxlen)) 
+        return SPI_CODE_SEGMENT_INVAL;
+
+    // Launch the transaction. All data has been verified, launch doesn't check 
+    // anything. Here user callbacks are used because non-blocking function.
+    spi_launch(&peripherals[spi->idx], spi, txn, callbacks);
+
+    return SPI_CODE_OK;
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/*                            LOCAL FUNCTIONS                               */
+/**                                                                        **/
+/****************************************************************************/
+
+spi_codes_e spi_check_valid(spi_t* spi) 
+{
+    // Is SPI peripheral identifier valid?
+    if (SPI_IDX_INVALID(spi->idx)) return SPI_CODE_IDX_INVAL;
+    // Has the spi been initialized (i.e. base validity checks made)?
+    if (!spi->init)                return SPI_CODE_NOT_INIT;
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_validate_slave(spi_slave_t slave) 
+{
+    spi_codes_e error = SPI_CODE_OK;
+    // Is chip select line number a valid one?
+    if (SPI_CSID_INVALID(slave.csid)) error |= SPI_CODE_SLAVE_CSID_INVAL;
+    // Is the slave max frequency less than the minimum frequency?
+    if (slave.freq < SPI_MIN_FREQ)    error |= SPI_CODE_SLAVE_FREQ_INVAL;
+    return error;
+}
+
+spi_codes_e spi_set_slave(spi_t* spi) 
+{
+    // Compute the best clock divider
+    uint16_t clk_div = 0;
+    if (spi->slave.freq < SYS_FREQ / 2)
+    {
+        clk_div = (SYS_FREQ / spi->slave.freq - 2) / 2;
+        if (SYS_FREQ / (2 * clk_div + 2) > spi->slave.freq) clk_div++;
+    }
+    // Build the HAL configopts to be set based on our slave
+    spi_configopts_t config = {
+        .clkdiv   = clk_div,
+        .csnidle  = spi->slave.csn_idle,
+        .csntrail = spi->slave.csn_trail,
+        .csnlead  = spi->slave.csn_lead,
+        .fullcyc  = spi->slave.full_cycle,
+        .cpha     = bitfield_read(spi->slave.data_mode, BIT_MASK_1, DATA_MODE_CPHA_OFFS),
+        .cpol     = bitfield_read(spi->slave.data_mode, BIT_MASK_1, DATA_MODE_CPOL_OFFS)
+    };
+    // Set the configopts
+    spi_return_flags_e config_error = spi_set_configopts(peripherals[spi->idx].instance, 
+                                                         spi->slave.csid,
+                                                         spi_create_configopts(config));
+    // CSID is invalid! This can only happen if user didn't properly initialize spi_t!
+    if (config_error) return SPI_CODE_SLAVE_INVAL;
+    // We already made sure csid was valid by calling spi_set_configopts. And we know
+    // instance is not NULL by definition. Hence won't return any errors.
+    spi_set_csid(peripherals[spi->idx].instance, spi->slave.csid);
+    return SPI_CODE_OK;
+}
+
+spi_codes_e spi_prepare_transfer(spi_t* spi) 
+{
+    // Check the idx and init of spi_t parameter.
+    // Notice that we do not check for slave's validity. This is because we assume
+    // that the user properly initialized his spi_t and didn't change its slave.
+    // Anyway spi_set_slave will give an error if the slave is invalid. But user
+    // should follow guidelines!
+    spi_codes_e error = spi_check_valid(spi);
+    if (error) return error;
+
+    // If busy don't start a new transaction...
+    if (SPI_BUSY(peripherals[spi->idx])) return SPI_CODE_IS_BUSY;
+    // Check also at hardware level if busy, we don't know if maybe there is a
+    // problem somewhere
+    if (spi_get_active(peripherals[spi->idx].instance) == SPI_TRISTATE_TRUE) 
+        return SPI_CODE_NOT_IDLE;
+
+    // If the last spi instance was NOT the same as the current, slave may have
+    // changed, therefore set the "new" slave. Otherwise don't bother.
+    if (spi->id != peripherals[spi->idx].last_id)
+    {
+        error = spi_set_slave(spi);
+        if (error) return error;
+    }
+
+    return SPI_CODE_OK;
+}
+
+uint32_t spi_true_slave_freq(uint32_t freq) 
+{
+    // Compute the best clock divider
+    uint16_t clk_div = 0;
+    if (freq < SYS_FREQ / 2) 
+    {
+        clk_div = (SYS_FREQ / freq - 2) / 2;
+        if (SYS_FREQ / (2 * clk_div + 2) > freq) clk_div++;
+    }
+    // Based on the computed divider return the true frequency the SCK will be at
+    return SYS_FREQ / (2 * clk_div + 2);
+}
+
+bool spi_validate_segments(const spi_segment_t* segments, uint32_t segments_len, 
+                           uint32_t* tx_count, uint32_t* rx_count) 
+{
+    // Check that there are any segments
+    if (segments_len == 0) return false;
+
+    // Make sure our word counters start at 0
+    *tx_count = 0;
+    *rx_count = 0;
+
+    for (int i = 0; i < segments_len; i++)
+    {
+        // Check that speed and direction are compatible and valid.
+        // Unfortunately this check will be done twice since when we set the command
+        // through the HAL the check will be done again.
+        // The problem is that, since starting a full transaction before being sure
+        // that all segments are valid would be undesirable, we have to check each
+        // segment before initiating a transaction.
+        uint8_t direction = bitfield_read(segments[i].mode, DIR_SPD_MASK, DIR_INDEX);
+        uint8_t speed     = bitfield_read(segments[i].mode, DIR_SPD_MASK, SPD_INDEX);
+        if (!spi_validate_cmd(direction, speed)) return false;
+        // Translate bytes len to words len
+        uint32_t word_len = LEN_WORDS(segments[i].len);
+        // Increase corresponding counter. There are dummy cycles, hence we need to
+        // specifically check for the exact direction.
+        if (direction == SPI_DIR_TX_ONLY || direction == SPI_DIR_BIDIR) 
+            *tx_count += word_len;
+        if (direction == SPI_DIR_RX_ONLY || direction == SPI_DIR_BIDIR) 
+            *rx_count += word_len;
+    }
+
+    return true;
+}
+
+bool spi_fill_tx(spi_peripheral_t* peri) 
+{
+    // If we have a TX buffer and didn't exceed the count then fill the TX FIFO
+    if (peri->txn.txbuffer != NULL && peri->txcnt < peri->txn.txlen) {
+        // While there is still data to be fed and there wasn't an error from HAL
+        // continue. HAL error in this case means that the fifo is full since
+        // it's the only possibility.
+        while (
+            peri->txcnt < peri->txn.txlen 
+            && !spi_write_word(peri->instance, peri->txn.txbuffer[peri->txcnt])
+        ) peri->txcnt++; // Keep track of counter
+        return true;
+    }
+    return false;
+}
+
+bool spi_empty_rx(spi_peripheral_t* peri) 
+{
+    // If we have a RX buffer and didn't exceed the count then read from RX FIFO
+    if (peri->txn.rxbuffer != NULL && peri->rxcnt < peri->txn.rxlen) {
+        // While there is still data to be read and there wasn't an error from HAL
+        // continue. HAL error in this case means that the fifo is empty since
+        // it's the only possibility.
+        while (
+            peri->rxcnt < peri->txn.rxlen 
+            && !spi_read_word(peri->instance, &peri->txn.rxbuffer[peri->rxcnt])
+        ) peri->rxcnt++; // Keep track of counter
+        return true;
+    }
+    return false;
+}
+
+void spi_launch(spi_peripheral_t* peri, spi_t* spi, spi_transaction_t txn, 
+                spi_callbacks_t callbacks) 
+{
+    // All checks have been made, therefore there can't be any error here.
+    // This also means that we can safely set the state since we know we will
+    // proceed to launch without any doubt.
+    peri->state     = SPI_STATE_BUSY;
+    // Set all transaction data to our static peripheral variable
+    peri->txn       = txn;
+    // Indicate the callbacks that should be called
+    peri->callbacks = callbacks;
+
+    // Fill the TX fifo before starting so there is data once command launched
+    spi_fill_tx(peri);
+
+    // Enable event interrupts since they are enabled only during a transaction
+    spi_set_events_enabled(peri->instance, TRIGGERING_EVENTS, true);
+    spi_enable_evt_intr   (peri->instance, true);
+
+    // Wait for the SPI peripheral to be ready before writing a command segment.
+    spi_wait_for_ready(peri->instance);
+    // Write command segment. This immediately triggers the SPI peripheral into action.
+    spi_issue_next_seg(peri);
+}
+
+void spi_wait_transaction_done(spi_peripheral_t* peri) 
+{
+    // Convert ms timeout to clock ticks
+    uint64_t timeout_ticks = ((uint64_t) peri->timeout) * (SYS_FREQ / 1000);
+    uint32_t start[2];
+    uint32_t end[2];
+
+    // Enable tick counter
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    // Record start tick counter value
+    CSR_READ(CSR_REG_MCYCLE,  &start[0]);
+    CSR_READ(CSR_REG_MCYCLEH, &start[1]);
+
+    // Wait until transaction has finished or timed-out
+    do
+    {
+        // Read tick counter value
+        CSR_READ(CSR_REG_MCYCLE,  &end[0]);
+        CSR_READ(CSR_REG_MCYCLEH, &end[1]);
+        // If ticks elapsed exceed timeout ticks, cancel transaction and return
+        if (*((uint64_t*)end) - *((uint64_t*)start) > timeout_ticks)
+        {
+            // Fully reset spi peripheral to cancel transaction, empty fifos, etc.
+            spi_reset_peri(peri);
+            // Indicate to user the transaction has timed-out
+            peri->state = SPI_STATE_TIMEOUT;
+            break;
+        }
+        
+    } while (SPI_BUSY((*peri)));
+}
+
+void spi_issue_next_seg(spi_peripheral_t* peri) 
+{
+    const spi_segment_t seg = peri->txn.segments[peri->scnt];
+    peri->scnt++;
+    // Construct our word command to be passed to HAL
+    uint32_t cmd_reg = spi_create_command((spi_command_t) {
+        .len       = seg.len - 1, // -1 because of SPI Host IP specifications
+        .csaat     = peri->txn.seglen == peri->scnt ? false : true,
+        .speed     = bitfield_read(seg.mode, DIR_SPD_MASK, SPD_INDEX),
+        .direction = bitfield_read(seg.mode, DIR_SPD_MASK, DIR_INDEX),
+    });
+    // Since all checks were already made we do not need to check the result of function
+    spi_set_command(peri->instance, cmd_reg);
+}
+
+void spi_reset_peri(spi_peripheral_t* peri) 
+{
+    // Reset static peripheral variables
+    spi_reset_transaction(peri);
+    // Reset the SPI peripheral (at hardware level)
+    spi_sw_reset(peri->instance);
+    // Enable SPI peripheral. We do not check return value since we know here that
+    // it will never return an error.
+    spi_set_enable(peri->instance, true);
+    spi_output_enable(peri->instance, true);
+    // Enable all error interrupts so that the SPI peripheral doesn't get stuck if
+    // there is an error. And we don't check return value since we know it's error free.
+    spi_set_errors_enabled(peri->instance, SPI_ERROR_IRQALL, true);
+    spi_enable_error_intr(peri->instance, true);
+    // Set the watermarks for the specific peripheral.
+    spi_set_tx_watermark(peri->instance, peri->txwm);
+    spi_set_rx_watermark(peri->instance, peri->rxwm);
+    // Just reset the state.
+    peri->state = SPI_STATE_INIT;
+    // Force the next transaction to set the slave at hardware level
+    peri->last_id = 0;
+}
+
+void spi_reset_transaction(spi_peripheral_t* peri) 
+{
+    // Reset all variables relative to the transaction of the static peripheral
+    // instance
+    peri->scnt      = 0;
+    peri->txcnt     = 0;
+    peri->rxcnt     = 0;
+    peri->txn       = (spi_transaction_t) {0};
+    peri->callbacks = NULL_CALLBACKS;
+}
+
+void spi_event_handler(spi_peripheral_t* peri, spi_event_e events) 
+{
+    // Ready means it is ready to accept new command segments. So we have two
+    // possibilities if the device is ready:
+    //  1) It is ready but not idle
+    //  2) It is ready and idle
+    if (events & SPI_EVENT_READY) 
+    {
+        // If SPI is ready and there are still commands to execute, issue next command
+        if (peri->txn.segments != NULL && peri->scnt < peri->txn.seglen) 
+        {
+            spi_issue_next_seg(peri);
+        }
+        // If no more commands and SPI is idle, it means the transaction is over
+        else if (events & SPI_EVENT_IDLE) 
+        {
+            // Disable all event interrupts
+            spi_set_events_enabled(peri->instance, SPI_EVENT_ALL, false);
+            spi_enable_evt_intr   (peri->instance, false);
+            // Read the last data from the RX fifo
+            spi_empty_rx(peri);
+            // Set the state to Transaction is done (meaning successful)
+            peri->state = SPI_STATE_DONE;
+            // If there is a callback defined call it
+            if (peri->callbacks.done_cb != NULL) 
+            {
+                peri->callbacks.done_cb(peri->txn.txbuffer, peri->txcnt, 
+                                        peri->txn.rxbuffer, peri->rxcnt);
+            }
+            // Reset all transaction related variables
+            spi_reset_transaction(peri);
+            return;
+        }
+    }
+    if (events & SPI_EVENT_TXWM)
+    {
+        // TX watermark reached. Refill TX fifo if more data
+        // If there is a callback defined call it
+        if (spi_fill_tx(peri) && peri->callbacks.txwm_cb != NULL)
+        {
+            peri->callbacks.txwm_cb(peri->txn.txbuffer, peri->txcnt, 
+                                    peri->txn.rxbuffer, peri->rxcnt);
+        }
+    }
+    if (events & SPI_EVENT_RXWM)
+    {
+        // RX watermark reached. Empty RX fifo to get more data
+        // If there is a callback defined call it
+        if (spi_empty_rx(peri) && peri->callbacks.rxwm_cb != NULL)
+        {
+            peri->callbacks.rxwm_cb(peri->txn.txbuffer, peri->txcnt, 
+                                    peri->txn.rxbuffer, peri->rxcnt);
+        }
+    }
+}
+
+void spi_error_handler(spi_peripheral_t* peri, spi_error_e error) 
+{
+    // Disable event interrupts
+    spi_set_events_enabled(peri->instance, SPI_EVENT_ALL, false);
+    spi_enable_evt_intr   (peri->instance, false);
+    // If there is a callback defined invoke it
+    if (peri->callbacks.error_cb != NULL) 
+    {
+        peri->callbacks.error_cb(peri->txn.txbuffer, peri->txcnt, 
+                                 peri->txn.rxbuffer, peri->rxcnt);
+    }
+    spi_reset_peri(peri);
+    // Set the state to error
+    peri->state = SPI_STATE_ERROR;
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/*                               INTERRUPTS                                 */
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Implementation of the weak function of the HAL
+ */
+void spi_intr_handler_event_flash(spi_event_e events) 
+{
+    if (SPI_NOT_BUSY(peripherals[SPI_IDX_FLASH])) return;
+    spi_event_handler(&peripherals[SPI_IDX_FLASH], events);
+}
+
+/**
+ * @brief Implementation of the weak function of the HAL
+ */
+void spi_intr_handler_error_flash(spi_error_e errors) 
+{
+    if (SPI_NOT_BUSY(peripherals[SPI_IDX_FLASH])) return;
+    spi_error_handler(&peripherals[SPI_IDX_FLASH], errors);
+}
+
+/**
+ * @brief Implementation of the weak function of the HAL
+ */
+void spi_intr_handler_event_host(spi_event_e events) 
+{
+    if (SPI_NOT_BUSY(peripherals[SPI_IDX_HOST])) return;
+    spi_event_handler(&peripherals[SPI_IDX_HOST], events);
+}
+
+/**
+ * @brief Implementation of the weak function of the HAL
+ */
+void spi_intr_handler_error_host(spi_error_e errors) 
+{
+    if (SPI_NOT_BUSY(peripherals[SPI_IDX_HOST])) return;
+    spi_error_handler(&peripherals[SPI_IDX_HOST], errors);
+}
+
+/**
+ * @brief Implementation of the weak function of the HAL
+ */
+void spi_intr_handler_event_host2(spi_event_e events) 
+{
+    if (SPI_NOT_BUSY(peripherals[SPI_IDX_HOST_2])) return;
+    spi_event_handler(&peripherals[SPI_IDX_HOST_2], events);
+}
+
+/**
+ * @brief Implementation of the weak function of the HAL
+ */
+void spi_intr_handler_error_host2(spi_error_e errors) 
+{
+    if (SPI_NOT_BUSY(peripherals[SPI_IDX_HOST_2])) return;
+    spi_error_handler(&peripherals[SPI_IDX_HOST_2], errors);
+}
+
+/****************************************************************************/
+/**                                                                        **/
+/**                                EOF                                     **/
+/**                                                                        **/
+/****************************************************************************/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.h
new file mode 100644
index 00000000..28982b31
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/spi/spi_sdk.h
@@ -0,0 +1,576 @@
+/*
+                              *******************
+******************************* C SOURCE FILE *****************************
+**                            *******************
+**
+** project  : X-HEEP
+** filename : spi_sdk.h
+** version  : 1
+** date     : 18/04/24
+**
+***************************************************************************
+**
+** Copyright (c) EPFL contributors.
+** All rights reserved.
+**
+***************************************************************************
+*/
+
+/***************************************************************************/
+/***************************************************************************/
+/**
+* @file   spi_sdk.h
+* @date   18/04/24
+* @author Llorenç Muela
+* @brief  The Serial Peripheral Interface (SPI) SDK to set up and use the
+* SPI peripheral
+*/
+
+#ifndef _SDK_SPI_H_
+#define _SDK_SPI_H_
+
+/****************************************************************************/
+/**                                                                        **/
+/**                            MODULES USED                                **/
+/**                                                                        **/
+/****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/****************************************************************************/
+/**                                                                        **/
+/**                       DEFINITIONS AND MACROS                           **/
+/**                                                                        **/
+/****************************************************************************/
+
+// Chosen arbitrarily
+#define SPI_CSN_TIMES_DEFAULT 15
+// Default timeout for blocking transactions in milliseconds
+#define SPI_TIMEOUT_DEFAULT   100
+
+/**
+ * @brief Macro to create a Slave SPI device with standard parameters.
+ */
+#define SPI_SLAVE(cs_id, freq_max) (spi_slave_t) { \
+    .csid       = cs_id, \
+    .data_mode  = SPI_DATA_MODE_0, \
+    .full_cycle = false, \
+    .csn_lead   = SPI_CSN_TIMES_DEFAULT, \
+    .csn_trail  = SPI_CSN_TIMES_DEFAULT, \
+    .csn_idle   = SPI_CSN_TIMES_DEFAULT, \
+    .freq       = freq_max \
+}
+
+/**
+ * @brief Macro to instantiate a Dummy Segment
+ */
+#define SPI_SEG_DUMMY(cycles) (spi_segment_t) { \
+    .len  = cycles, \
+    .mode = SPI_MODE_DUMMY \
+}
+
+/**
+ * @brief Macro to instantiate a TX Segment
+ */
+#define SPI_SEG_TX(bytes) (spi_segment_t) { \
+    .len  = bytes, \
+    .mode = SPI_MODE_TX_STD \
+}
+
+/**
+ * @brief Macro to instantiate a RX Segment
+ */
+#define SPI_SEG_RX(bytes) (spi_segment_t) { \
+    .len  = bytes, \
+    .mode = SPI_MODE_RX_STD \
+}
+
+/**
+ * @brief Macro to instantiate a BIDIR Segment
+ */
+#define SPI_SEG_BIDIR(bytes) (spi_segment_t) { \
+    .len  = bytes, \
+    .mode = SPI_MODE_BIDIR \
+}
+
+/**
+ * @brief Macro to instantiate a Dual Speed TX Segment
+ */
+#define SPI_SEG_TX_DUAL(bytes) (spi_segment_t) { \
+    .len  = bytes, \
+    .mode = SPI_MODE_TX_DUAL \
+}
+
+/**
+ * @brief Macro to instantiate a Dual Speed RX Segment
+ */
+#define SPI_SEG_RX_DUAL(bytes) (spi_segment_t) { \
+    .len  = bytes, \
+    .mode = SPI_MODE_RX_DUAL \
+}
+
+/**
+ * @brief Macro to instantiate a Quad Speed TX Segment
+ */
+#define SPI_SEG_TX_QUAD(bytes) (spi_segment_t) { \
+    .len  = bytes, \
+    .mode = SPI_MODE_TX_QUAD \
+}
+
+/**
+ * @brief Macro to instantiate a Quad Speed RX Segment
+ */
+#define SPI_SEG_RX_QUAD(bytes) (spi_segment_t) { \
+    .len  = bytes, \
+    .mode = SPI_MODE_RX_QUAD \
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/**                                                                        **/
+/**                       TYPEDEFS AND STRUCTURES                          **/
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+* @brief SPI Peripheral IDX
+*/
+typedef enum {
+    SPI_IDX_FLASH       = 0,  // Identifier for the SPI FLASH peripheral
+    SPI_IDX_HOST        = 1,  // Identifier for the SPI HOST1 peripheral
+    SPI_IDX_HOST_2      = 2   // Identifier for the SPI HOST2 peripheral
+} spi_idx_e;
+
+typedef enum {
+    SPI_CODE_OK                 = 0x0000, // Everything Okay
+    SPI_CODE_BASE_ERROR         = 0x0001, // HAL complained (should never happen)
+    SPI_CODE_IDX_INVAL          = 0x0002, // The idx of the provided spi_t is not valid
+    SPI_CODE_WM_EXCEEDS         = 0x0004, // The provided watermark is too big
+    SPI_CODE_NOT_INIT           = 0x0008, // The provided spi_t was not initialized
+    SPI_CODE_SLAVE_CSID_INVAL   = 0x0010, // The csid of the slave is not valid
+    SPI_CODE_SLAVE_FREQ_INVAL   = 0x0020, // Max frequency of the slave is too low
+    SPI_CODE_NOT_IDLE           = 0x0040, // The SPI device is busy (but not from SDK)
+    SPI_CODE_SLAVE_INVAL        = 0x0080, // Something was wrong with the slave configuration
+    SPI_CODE_SEGMENT_INVAL      = 0x0100, // The spi_mode_e of the segment was invalid
+    SPI_CODE_IS_BUSY            = 0x0200, // The SPI device is busy
+    SPI_CODE_TXN_LEN_INVAL      = 0x0400, // The transaction length is 0 or too long
+    SPI_CODE_TIMEOUT_INVAL      = 0x0800  // The specified timeout is invalid
+} spi_codes_e;
+
+typedef enum {
+    SPI_DATA_MODE_0 = 0,     // cpol = 0, cpha = 0
+    SPI_DATA_MODE_1 = 1,     // cpol = 0, cpha = 1
+    SPI_DATA_MODE_2 = 2,     // cpol = 1, cpha = 0
+    SPI_DATA_MODE_3 = 3      // cpol = 1, cpha = 1
+} spi_datamode_e;
+
+typedef enum {
+    SPI_MODE_DUMMY   = 0,   // Dummy SCK command segment
+    SPI_MODE_RX_STD  = 1,   // Standard receive command segment
+    SPI_MODE_TX_STD  = 2,   // Standard transmit command segment
+    SPI_MODE_BIDIR   = 3,   // Standard bidirectional command segment
+    // 4 is same than DUMMY
+    SPI_MODE_RX_DUAL = 5,   // Dual speed receive command segment
+    SPI_MODE_TX_DUAL = 6,   // Dual speed transmit command segment
+    // 7 is invalid
+    // 8 is same than DUMMY
+    SPI_MODE_RX_QUAD = 9,   // Quad speed receive command segment
+    SPI_MODE_TX_QUAD = 10   // Quad speed transmit command segment
+    // everything > 10 is invalid
+} spi_mode_e;
+
+// State is useful to know if the peripheral is busy, but also very useful if a
+// blocking transaction was made and we want to check the result of the blocking
+// transation (i.e. error or success)
+typedef enum {
+    // Indicates SPI device was never initialized (should never happen!)
+    SPI_STATE_NONE      = 0x00,
+    // Indicates SPI device never executed a transaction
+    SPI_STATE_INIT      = 0x01,
+    // Indicates SPI device is currently processing a transaction
+    SPI_STATE_BUSY      = 0x02,
+    // Indicates SPI device has successfully executed a transaction
+    SPI_STATE_DONE      = 0x04,
+    // Indicates there was an error during transaction
+    SPI_STATE_ERROR     = 0x08,
+    // Indicates the transaction execution has timed-out
+    SPI_STATE_TIMEOUT   = 0x10,
+    // Indicates the argument passed to spi_get_state was not valid
+    SPI_STATE_ARG_INVAL = 0x20
+} spi_state_e;
+
+/**
+ * @brief Type defining the configuration of the slave device with whom to communicate
+ */
+typedef struct {
+    // The Chip Select line where device connected
+    uint8_t        csid       : 2;
+    // The data sampling and transmitting mode (polarity and phase)
+    spi_datamode_e data_mode  : 2;
+    // If 1 data is sampled a full cycle after shifting data out, instead of half cycle
+    bool           full_cycle : 1;
+    // The minimum number of sck half-cycles to hold cs_n high between commands
+    uint8_t        csn_idle   : 4;
+    // The number of half sck cycles, CSNTRAIL+1, to leave between last edge of sck 
+    // and the rising edge of cs_n
+    uint8_t        csn_trail  : 4;
+    // The number of half sck cycles, CSNLEAD+1, to leave between the falling edge 
+    // of cs_n and the first edge of sck
+    uint8_t        csn_lead   : 4;
+    // The maximum frequency in hertz of the slave
+    uint32_t       freq       : 32;
+} spi_slave_t;
+
+/**
+ * @brief Type defining a command segment
+ */
+typedef struct {
+    uint32_t   len  : 24;  // Length of data in bytes for the particular segment
+    spi_mode_e mode : 4;   // Communication mode (TX, BIDIR, RX_QUAD, ...)
+} spi_segment_t;
+
+// Event / Error interrupt callback  (txbuffer, txlen, rxbuffer, rxlen)
+typedef void (*spi_cb_t)(const uint32_t*, uint32_t, uint32_t*, uint32_t);
+
+/**
+ * @brief Structure holding all the callbacks for a transaction.
+ *        Each callback may be NULL if you don't want it to be called.
+ */
+typedef struct {
+    spi_cb_t done_cb;   // Called once transaction is done
+    spi_cb_t txwm_cb;   // Called each time TX watermark event is triggered
+    spi_cb_t rxwm_cb;   // Called each time RX watermark event is triggered
+    spi_cb_t error_cb;  // Called when there was an error during transaction
+} spi_callbacks_t;
+
+/**
+ * @brief Type holding Information to use SDK.
+ */
+typedef struct {
+    spi_idx_e   idx;   // The identifier for the desired SPI devide
+    uint32_t    id;    // spi_t instance ID
+    bool        init;  // Indicates if initialization was successful
+    spi_slave_t slave; // The slave with whom to communicate configuration 
+} spi_t;
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED VARIABLES                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          EXPORTED FUNCTIONS                            **/
+/**                                                                        **/
+/****************************************************************************/
+
+/**
+ * @brief Initialize desired SPI device and obtain structure to use SDK functions.
+ *        This method has to be called prior to any use of other functions of the SDK.
+ * 
+ *  Important: This method validates the provided slave and adapts its frequency
+ *  based on the MCU frequency and the SCK divider. If you do not create the spi_t
+ *  structure by calling this function the slave may be invalid resulting in errors.
+ * 
+ * @param idx spi_idx_e representing the SPI device
+ * @param slave spi_slave_t correctly configured slave SPI device to interact with
+ * @return spi_t structure to use SDK functions
+ */
+spi_t spi_init(spi_idx_e idx, spi_slave_t slave);
+
+/**
+ * @brief Uninitializes the spi by unsetting all fields.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ */
+void spi_deinit(spi_t* spi);
+
+/**
+ * @brief Completely reset the SPI device (clears all status, stops all transactions,
+ *        empties FIFOs)
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_reset(spi_t* spi);
+
+/**
+ * @brief Change the TX watermark of the specific SPI Host peripheral
+ *        Maximum is currently 72. Check SPI_HOST_PARAM_TX_DEPTH in HAL.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param watermark The desired new watermark
+ * @return SPI_CODE_IDX_INVAL  if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT   if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_WM_EXCEEDS if specified watermark is too high
+ * @return SPI_CODE_OK         if success
+ */
+spi_codes_e spi_set_txwm(spi_t* spi, uint8_t watermark);
+
+/**
+ * @brief Get the TX watermark of the specific SPI Host peripheral
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param watermark The current watermark will be stored in this variable
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_get_txwm(spi_t* spi, uint8_t* watermark);
+
+/**
+ * @brief Change the RX watermark of the specific SPI Host peripheral
+ *        Maximum is currently 64. Check SPI_HOST_PARAM_RX_DEPTH in HAL.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param watermark The desired new watermark
+ * @return SPI_CODE_IDX_INVAL  if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT   if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_WM_EXCEEDS if specified watermark is too high
+ * @return SPI_CODE_OK         if success
+ */
+spi_codes_e spi_set_rxwm(spi_t* spi, uint8_t watermark);
+
+/**
+ * @brief Get the RX watermark of the specific SPI Host peripheral
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param watermark The current watermark will be stored in this variable
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_get_rxwm(spi_t* spi, uint8_t* watermark);
+
+/**
+ * @brief Set the timeout in milliseconds for blocking transactions for the 
+ *        specific SPI Host peripheral.
+ *        Maximum is UINT32_MAX * 1000 / core_frequency.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param watermark The desired new watermark
+ * @return SPI_CODE_IDX_INVAL     if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT      if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_TIMEOUT_INVAL if the specified timout is too large
+ * @return SPI_CODE_OK            if success
+ */
+spi_codes_e spi_set_timeout(spi_t* spi, uint32_t timeout);
+
+/**
+ * @brief Get the timeout in milliseconds for blocking transactions for the 
+ *        specific SPI Host peripheral.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param timeout The current timeout will be stored in this variable
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_get_timeout(spi_t* spi, uint32_t* timeout);
+
+/**
+ * @brief Change the communication frequency of the slave
+ *        /!\ If the frequency is higher than the maximum frequency it will just
+ *            be capped (i.e. no error)
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param freq The new frequency the slave should be changed
+ * @return SPI_CODE_IDX_INVAL        if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT         if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_SLAVE_CSID_INVAL if slave's csid is invalid
+ * @return SPI_CODE_SLAVE_FREQ_INVAL if new frequency is too low
+ * @return SPI_CODE_OK               if success
+ */
+spi_codes_e spi_set_slave_freq(spi_t* spi, uint32_t freq);
+
+/**
+ * @brief Read the SPI current state.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @return SPI_STATE_NONE      : SPI device was never initialized (should never happen!)
+ * @return SPI_STATE_INIT      : SPI device never executed a transaction
+ * @return SPI_STATE_BUSY      : SPI device is currently processing a transaction
+ * @return SPI_STATE_DONE      : SPI device has successfully executed a transaction
+ * @return SPI_STATE_ERROR     : There was an error during transaction
+ * @return SPI_STATE_ARG_INVAL : The argument passed to this function was not valid
+ */
+spi_state_e spi_get_state(spi_t* spi);
+
+/**
+ * @brief Executes a TX command.
+ *        /!\ Caution: len is in bytes.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param src_buffer An initialized buffer/array with all the data to send
+ * @param len The size in bytes of the transaction (/!\ must be coherent with 
+ *            src_buffer size)
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_transmit(spi_t* spi, const uint32_t* src_buffer, uint32_t len);
+
+/**
+ * @brief Executes an RX command.
+ *        /!\ Caution: len is in bytes.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param dest_buffer An initialized buffer/array to store the received data
+ * @param len The size in bytes of the transaction (/!\ must be coherent with 
+ *            dest_buffer size)
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_receive(spi_t* spi, uint32_t* dest_buffer, uint32_t len);
+
+/**
+ * @brief Executes a Bidirectional (TX and RX) command.
+ *        /!\ Caution: len is in bytes and is for the TX as well as RX.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param src_buffer An initialized buffer/array with all the data to send
+ * @param dest_buffer An initialized buffer/array to store the received data
+ * @param len The size in bytes of the transaction (/!\ must be coherent with 
+ *            src_buffer and dest_buffer size)
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_transceive(spi_t* spi, const uint32_t* src_buffer, 
+                           uint32_t* dest_buffer, uint32_t len);
+
+/**
+ * @brief Executes a transacton composed of multiple command segments.
+ *        Each segment already contains the Information about the length and the 
+ *        src/dest buffer concerned. Therefore no need for length parameter here.
+ *        /!\ Caution: please be consistent with the length of src_buffer/dest_buffer
+ *                     and the lenghts specified for the segments.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param segments An array of command segments
+ * @param segments_len The size of segments array
+ * @param src_buffer An initialized buffer/array with all the data to send
+ * @param dest_buffer An initialized buffer/array to store the received data
+ * @return SPI_CODE_IDX_INVAL     if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT      if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_SEGMENT_INVAL if segments contains an invalid segment
+ * @return SPI_CODE_OK            if success
+ */
+spi_codes_e spi_execute(spi_t* spi, const spi_segment_t* segments, 
+                        uint32_t segments_len, const uint32_t* src_buffer, 
+                        uint32_t* dest_buffer);
+
+/**
+ * @brief Executes a TX command. This is Non-Blocking, the function will return 
+ *        immediately.
+ *        /!\ Caution: len is in bytes.
+ *
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param src_buffer An initialized buffer/array with all the data to send
+ * @param len The size in bytes of the transaction (/!\ must be coherent with 
+ *            src_buffer size)
+ * @param done_cb A callback function of type spi_cb_t that gets called when 
+ *                transaction is done
+ * @param error_cb A callback function of type spi_cb_t that gets called when there 
+ *                 is an error during transaction
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_transmit_nb(spi_t* spi, const uint32_t* src_buffer, uint32_t len, 
+                            spi_callbacks_t callbacks);
+
+/**
+ * @brief Executes an RX command. This is Non-Blocking, the function will return 
+ *        immediately.
+ *        /!\ Caution: len is in bytes.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param dest_buffer An initialized buffer/array to store the received data
+ * @param len The size in bytes of the transaction (/!\ must be coherent with 
+ *            dest_buffer size)
+ * @param done_cb A callback function of type spi_cb_t that gets called when 
+ *                transaction is done
+ * @param error_cb A callback function of type spi_cb_t that gets called when there 
+ *                 is an error during transaction
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_receive_nb(spi_t* spi, uint32_t* dest_buffer, uint32_t len, 
+                           spi_callbacks_t callbacks);
+
+/**
+ * @brief Executes a Bidirectional (TX and RX) command. This is Non-Blocking, the 
+ *        function will return immediately.
+ *        /!\ Caution: len is in bytes and is for the TX as well as RX.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param src_buffer An initialized buffer/array with all the data to send
+ * @param dest_buffer An initialized buffer/array to store the received data
+ * @param len The size in bytes of the transaction (/!\ must be coherent with 
+ *            src_buffer and dest_buffer size)
+ * @param done_cb A callback function of type spi_cb_t that gets called when 
+ *                transaction is done
+ * @param error_cb A callback function of type spi_cb_t that gets called when there 
+ *                 is an error during transaction
+ * @return SPI_CODE_IDX_INVAL if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT  if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_OK        if success
+ */
+spi_codes_e spi_transceive_nb(spi_t* spi, const uint32_t* src_buffer, 
+                              uint32_t* dest_buffer, uint32_t len, 
+                              spi_callbacks_t callbacks);
+
+/**
+ * @brief Executes a transacton composed of multiple command segments. This is 
+ *        Non-Blocking, the function will return immediately.
+ *        Each segment already contains the Information about the length and the 
+ *        src/dest buffer concerned. Therefore no need for length parameter here.
+ *        /!\ Caution: please be consistent with the length of src_buffer/dest_buffer
+ *                     and the lenghts specified for the segments.
+ * 
+ * @param spi Pointer to spi_t structure obtained through spi_init call
+ * @param segments An array of command segments
+ * @param segments_len The size of segments array
+ * @param src_buffer An initialized buffer/array with all the data to send
+ * @param dest_buffer An initialized buffer/array to store the received data
+ * @param done_cb A callback function of type spi_cb_t that gets called when 
+ *                transaction is done
+ * @param error_cb A callback function of type spi_cb_t that gets called when there 
+ *                 is an error during transaction
+ * @return SPI_CODE_IDX_INVAL     if spi.idx not valid
+ * @return SPI_CODE_NOT_INIT      if spi.init false (indicates if spi was initialized)
+ * @return SPI_CODE_SEGMENT_INVAL if segments contains an invalid segment
+ * @return SPI_CODE_OK            if success
+ */
+spi_codes_e spi_execute_nb(spi_t* spi, const spi_segment_t* segments, 
+                           uint32_t segments_len, const uint32_t* src_buffer, 
+                           uint32_t* dest_buffer, spi_callbacks_t callbacks);
+
+/****************************************************************************/
+/**                                                                        **/
+/**                          INLINE FUNCTIONS                              **/
+/**                                                                        **/
+/****************************************************************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _SDK_SPI_H_
+
+/****************************************************************************/
+/**                                                                        **/
+/**                                EOF                                     **/
+/**                                                                        **/
+/****************************************************************************/
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.c
new file mode 100644
index 00000000..3e4e2719
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.c
@@ -0,0 +1,142 @@
+// Copyright 2023 EPFL and Politecnico di Torino.
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: timer_sdk.c
+// Author: Michele Caon, Francesco Poluzzi
+// Date: 23/07/2024
+// Description: Timer functions
+
+#include <stdint.h>
+
+#include "timer_sdk.h"
+#include "csr.h"
+#include "soc_ctrl.h"
+
+
+/******************************/
+/* ---- GLOBAL VARIABLES ---- */
+/******************************/
+
+// Timer value
+int32_t hw_timer_value = 0;
+
+rv_timer_t timer;
+
+rv_timer_config_t timer_cfg = {
+    .hart_count = RV_TIMER_PARAM_N_HARTS,
+    .comparator_count = RV_TIMER_PARAM_N_TIMERS,
+};
+
+mmio_region_t timer_base = {
+    .base = (void *)RV_TIMER_AO_START_ADDRESS,
+};
+
+rv_timer_tick_params_t tick_params;
+
+
+/*************************************/
+/* ---- FUNCTION IMPLEMENTATION ---- */
+/*************************************/
+
+uint32_t timer_get_cycles()
+{
+    uint64_t cycle_count;
+    rv_timer_counter_read(&timer, 0, &cycle_count);
+    return (uint32_t)cycle_count;
+}
+
+void timer_irq_enable()
+{
+  rv_timer_irq_enable(&timer, 0, 0, kRvTimerEnabled);
+}
+
+void timer_irq_clear()
+{
+  rv_timer_irq_clear(&timer, 0, 0);
+}
+
+void timer_arm_start(uint32_t threshold)
+{
+    rv_timer_arm(&timer, 0, 0, threshold);
+    timer_start();
+}
+
+void timer_arm_stop()
+{
+    rv_timer_counter_set_enabled(&timer, 0, kRvTimerDisabled);
+}
+
+
+void timer_arm_set(uint32_t threshold)
+{
+    rv_timer_arm(&timer, 0, 0, threshold);
+}
+
+void timer_start()
+{
+    hw_timer_value = -timer_get_cycles();
+    rv_timer_counter_set_enabled(&timer, 0, kRvTimerEnabled);
+}
+
+void timer_reset()
+{  
+    hw_timer_value = 0;
+    rv_timer_reset(&timer);
+}
+
+uint32_t timer_stop()
+{
+    hw_timer_value += timer_get_cycles();
+    rv_timer_counter_set_enabled(&timer, 0, kRvTimerDisabled);
+    return  hw_timer_value;
+}
+
+// Initialize the timer
+void timer_cycles_init()
+{
+    // Get current Frequency
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz = soc_ctrl_get_frequency(&soc_ctrl);
+
+    // Initialize the timer
+    timer_reset();
+    rv_timer_init(timer_base, timer_cfg, &timer);
+    rv_timer_approximate_tick_params(freq_hz, freq_hz, &tick_params);
+    rv_timer_set_tick_params(&timer, 0, tick_params);
+}
+
+// Initialize the timer
+void timer_wait_us(uint32_t us)
+{
+    // Get current Frequency
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz = soc_ctrl_get_frequency(&soc_ctrl);
+
+    timer_cycles_init();
+    timer_irq_enable();
+    timer_arm_start(us*(freq_hz/1000000)-50); // 50 cycles for taking into account initialization        
+    asm volatile ("wfi");
+    timer_irq_clear();
+    return;
+}
+
+void enable_timer_interrupt()
+{
+    //enable timer interrupt
+    CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+    // Set mie.MEIE bit to one to enable machine-level timer interrupts
+    const uint32_t mask = 1 << 7;
+    CSR_SET_BITS(CSR_REG_MIE, mask);
+}
+
+float get_time_from_cycles(uint32_t cycles){
+    // Get current Frequency
+    soc_ctrl_t soc_ctrl;
+    soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+    uint32_t freq_hz = soc_ctrl_get_frequency(&soc_ctrl);
+
+    return (float)cycles/((float)freq_hz/1000000);
+}
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.h
new file mode 100644
index 00000000..154ef30b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/timer/timer_sdk.h
@@ -0,0 +1,121 @@
+
+// Copyright 2023 EPFL and Politecnico di Torino.
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: timer_sdk.h
+// Authors: Michele Caon, Luigi Giuffrida, Francesco Poluzzi
+// Date: 23/07/2024
+// Description: Execution time measurements utilities
+
+#ifndef TIMER_SDK_H_
+#define TIMER_SDK_H_
+
+#include <stdint.h>
+
+#include "csr.h"
+#include "gpio.h"
+#include "rv_timer.h"
+#include "rv_timer_regs.h"
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+
+#define FREQ_1MHz 1000000
+
+/******************************/
+/* ---- GLOBAL VARIABLES ---- */
+/******************************/
+
+// Timer value
+extern int32_t hw_timer_value;
+
+extern rv_timer_t timer;
+
+/********************************/
+/* ---- EXPORTED FUNCTIONS ---- */
+/********************************/
+
+/**
+ * @brief Get the current value of the HW timer
+ * 
+* @return int64_t Current value of the HW timer
+ */
+uint32_t timer_get_cycles();
+
+/**
+ * @brief Start the timer
+ * 
+ */
+void timer_start();
+
+/**
+ * @brief Stop and reset the timer to 0
+ * 
+ */
+void timer_reset();
+
+/**
+ * @brief Stop the HW timer
+ * 
+ * @return int64_t Elapsed time in clock cycles
+ */
+uint32_t timer_stop();
+
+/**
+ * @brief Initialize the timer for counting clock cycles
+ * @brief Initialize the timer for counting clock cycles
+ * 
+ */
+void timer_cycles_init();
+
+/**
+ * @brief Enable the timer IRQ
+ */
+void timer_irq_enable();
+
+/**
+ * @brief Clear the timer IRQ
+ */
+void timer_irq_clear();
+
+/**
+ * @brief Arms the timer to go off once the counter value is greater than or equal to threshold
+ * and starts the timer
+ */
+void timer_arm_start(uint32_t threshold);
+
+/**
+ * @brief Stop to output when timer is greater than or equal to threshold previously set
+ */
+void timer_arm_stop();
+
+/**
+ * @brief Set the timer to go off once the counter value is greater than or equal to threshold,
+ * without starting the timer
+ */
+void timer_arm_set(uint32_t threshold);
+
+/**
+ * @brief Enable the timer machine-level interrupts for X-Heep
+ */
+void enable_timer_interrupt();
+
+/**
+ * @brief Wait for a certain amount of microseconds. 
+ * You need to enable timer interrupts with enable_timer_interrupt() before using this function
+ */
+void timer_wait_us(uint32_t ms);
+
+/**
+ * @brief Enable the timer machine-level interrupts for X-Heep
+ */
+void enable_timer_interrupt();
+
+/**
+ * @brief Get the time taken to execute a certain number of cycles
+ * 
+ * @return float value representing the time taken in microseconds
+ */
+float get_time_from_cycles(uint32_t cycles);
+
+#endif /* TIMER_SDK_H_ */
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h b/hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h
index c1ef5c5c..072a31e0 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/target/nexys-a7-100t/x-heep.h
@@ -15,6 +15,7 @@ extern "C" {
 #define REFERENCE_CLOCK_Hz 15*1000*1000
 #define UART_BAUDRATE 9600
 #define TARGET_NEXYS_A7_100T 1
+#define TARGET_IS_FPGA 1
 
 /**
  * As the hw is configurable, we can have setups with different number of
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/target/pynq-z2/x-heep.h b/hw/vendor/esl_epfl_x_heep/sw/device/target/pynq-z2/x-heep.h
index 43cef0d4..2733e716 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/target/pynq-z2/x-heep.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/target/pynq-z2/x-heep.h
@@ -15,6 +15,7 @@ extern "C" {
 #define REFERENCE_CLOCK_Hz 15*1000*1000
 #define UART_BAUDRATE 9600
 #define TARGET_PYNQ_Z2 1
+#define TARGET_IS_FPGA 1
 
 /**
  * As the hw is configurable, we can have setups with different number of
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h b/hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h
index af1b4cd5..7c0b0602 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/target/zcu104/x-heep.h
@@ -14,6 +14,7 @@ extern "C" {
 #define REFERENCE_CLOCK_Hz 15*1000*1000
 #define UART_BAUDRATE 9600
 #define TARGET_ZCU104 1
+#define TARGET_IS_FPGA 1
 
 /**
  * As the hw is configurable, we can have setups with different number of
diff --git a/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl b/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
index 7403248d..b499b576 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/linker/link.ld.tpl
@@ -20,11 +20,9 @@ MEMORY
   /* Our testbench is a bit weird in that we initialize the RAM (thus
      allowing initialized sections to be placed there). Infact we dump all
      sections to ram. */
-  ram0 (rwxai) : ORIGIN = 0x${linker_onchip_code_start_address}, LENGTH = 0x${linker_onchip_code_size_address}
-  ram1 (rwxai) : ORIGIN = 0x${linker_onchip_data_start_address}, LENGTH = 0x${linker_onchip_data_size_address}
-% if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
-  ram_il (rwxai) : ORIGIN = 0x${linker_onchip_il_start_address}, LENGTH = 0x${linker_onchip_il_size_address}
-% endif
+  % for i, section in enumerate(xheep.iter_linker_sections()):
+    ram${i} (rwxai) : ORIGIN = ${f"{section.start:#08x}"}, LENGTH = ${f"{section.size:#08x}"}
+% endfor
 }
 
 /*
@@ -294,14 +292,16 @@ SECTIONS
    PROVIDE(__freertos_irq_stack_top = .);
   } >ram1
 
-% if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
-  .data_interleaved :
+% for i, section in enumerate(xheep.iter_linker_sections()):
+% if not section.name in ["code", "data"]:
+  .${section.name} :
   {
     . = ALIGN(4);
-    *(.xheep_data_interleaved)
+    *(.xheep_${section.name})
     . = ALIGN(4);
-  } >ram_il
+  } >ram${i}
 % endif
+% endfor
 
   /* Stabs debugging sections.  */
   .stab          0 : { *(.stab) }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl
index 8bd9e64e..dca5e456 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_exec.ld.tpl
@@ -8,7 +8,7 @@ ENTRY(_start)
 MEMORY
 {
     FLASH (rx)      : ORIGIN = 0x${flash_mem_start_address}, LENGTH = 0x${flash_mem_size_address}
-    RAM (xrw)       : ORIGIN = 0x${'{:08X}'.format(int(ram_start_address,16) + 4)}, LENGTH = 0x${'{:08X}'.format(int(ram_size_address,16) - 4)}
+    RAM (xrw)       : ORIGIN = 0x${f'{xheep.ram_start_address()+4:08X}'}, LENGTH = 0x${f'{xheep.ram_size_address()-4:08X}'}
 }
 
 SECTIONS {
diff --git a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl
index 541b2233..9e7b637f 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/linker/link_flash_load.ld.tpl
@@ -7,15 +7,13 @@ ENTRY(_start)
 
 MEMORY
 {
-    ram0 (rwxai) : ORIGIN = 0x${linker_onchip_code_start_address}, LENGTH = 0x${linker_onchip_code_size_address}
-    ram1 (rwxai) : ORIGIN = 0x${linker_onchip_data_start_address}, LENGTH = 0x${linker_onchip_data_size_address}
-    FLASH0 (rx)   : ORIGIN = 0x${linker_flash_code_start_address}, LENGTH = 0x${linker_onchip_code_size_address}
-    FLASH1 (rx)   : ORIGIN = 0x${linker_flash_data_start_address}, LENGTH = 0x${linker_onchip_data_size_address}
-  % if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
-    ram_il (rwxai) : ORIGIN = 0x${linker_onchip_il_start_address}, LENGTH = 0x${linker_onchip_il_size_address}
-    FLASH_il (rx)   : ORIGIN = 0x${linker_flash_il_start_address}, LENGTH = 0x${linker_onchip_il_size_address}
-  % endif
-    FLASH_left (rx)   : ORIGIN = 0x${linker_flash_left_start_address}, LENGTH = 0x${linker_flash_left_size_address}
+<%flash_end = 0%>
+% for i, section in enumerate(xheep.iter_linker_sections()):
+    ram${i} (rwxai) : ORIGIN = ${f"{section.start:#08x}"}, LENGTH = ${f"{section.size:#08x}"}
+    FLASH${i} (rx)  : ORIGIN = ${f"{section.start + int(flash_mem_start_address,16):#08x}"}, LENGTH = ${f"{section.size:#08x}"}
+<%flash_end = section.end%>
+% endfor
+    FLASH_left (rx) : ORIGIN = ${f"{flash_end + int(flash_mem_start_address,16):#08x}"}, LENGTH = ${f"{int(flash_mem_size_address,16) - flash_end:#08x}"}
 }
 
 
@@ -63,7 +61,9 @@ SECTIONS {
         KEEP (*(.text.spi_read_word*))
         KEEP (*(.text.memcpy))
         KEEP (*(.text.w25q128jw_read_standard)) /* as this function is used in the crt0, link it in the top, should be before 1024 Bytes loaded by the bootrom */
+        KEEP (*(.text.w25q128jw_read_standard.*)) /* sometimes the function is renamed as  w25q128jw_read_standard.part */
         *(.xheep_init_data_crt0) /* this global variables are used in the crt0 */
+        KEEP (*_bswapsi2*(.text)) /* this function is used in the w25q128jw_read_standard */
     } >ram0 AT >FLASH0
 
     /* The program code and other data goes into FLASH */
@@ -158,21 +158,23 @@ SECTIONS {
        PROVIDE(__freertos_irq_stack_top = .);
     } >ram1
 
-  % if ram_numbanks_cont > 1 and ram_numbanks_il > 0:
-    .data_interleaved : ALIGN_WITH_INPUT
+  % for i, section in enumerate(xheep.iter_linker_sections()):
+  % if not section.name in ["code", "data"]:
+    .${section.name} : ALIGN_WITH_INPUT
     {
-        PROVIDE(__data_interleaved_start = .);
-        _lma_data_interleaved_start = LOADADDR(.data_interleaved);
+        PROVIDE(__${section.name}_start = .);
+        _lma_${section.name}_start = LOADADDR(.${section.name});
         . = ALIGN(4);
-        *(.xheep_data_interleaved)
+        *(.xheep_${section.name})
         . = ALIGN(4);
-    } >ram_il AT >FLASH_il
+    } >ram${i} AT >FLASH${i}
 
    . = ALIGN(4);
-  _eddata_interleaved = .;
-  _lma_data_interleaved_end = _lma_data_interleaved_start + SIZEOF(.data_interleaved);
+  _ed${section.name} = .;
+  _lma_${section.name}_end = _lma_${section.name}_start + SIZEOF(.${section.name});
 
   % endif
+  % endfor
 
     .data_flash_only : ALIGN(256)
     {
diff --git a/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl b/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl
index a0f295a4..2aafa4e8 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl
+++ b/hw/vendor/esl_epfl_x_heep/tb/tb_util.svh.tpl
@@ -6,8 +6,8 @@
 // Task for loading 'mem' with SystemVerilog system task $readmemh()
 export "DPI-C" task tb_readHEX;
 export "DPI-C" task tb_loadHEX;
-% for bank in range(ram_numbanks):
-export "DPI-C" task tb_writetoSram${bank};
+% for bank in xheep.iter_ram_banks():
+export "DPI-C" task tb_writetoSram${bank.name()};
 % endfor
 export "DPI-C" task tb_getMemSize;
 export "DPI-C" task tb_set_exit_loop;
@@ -16,9 +16,7 @@ import core_v_mini_mcu_pkg::*;
 
 task tb_getMemSize;
   output int mem_size;
-  output int num_banks;
   mem_size  = core_v_mini_mcu_pkg::MEM_SIZE;
-  num_banks = core_v_mini_mcu_pkg::NUM_BANKS;
 endtask
 
 task tb_readHEX;
@@ -31,11 +29,11 @@ task tb_loadHEX;
   input string file;
   //whether to use debug to write to memories
   logic [7:0] stimuli[core_v_mini_mcu_pkg::MEM_SIZE];
-  int i, stimuli_counter, bank, NumBytes, NumBanks;
+  int i, stimuli_base, w_addr, NumBytes;
   logic [31:0] addr;
 
   tb_readHEX(file, stimuli);
-  tb_getMemSize(NumBytes, NumBanks);
+  tb_getMemSize(NumBytes);
 
 `ifndef VERILATOR
   for (i = 0; i < NumBytes; i = i + 4) begin
@@ -71,43 +69,34 @@ task tb_loadHEX;
   release x_heep_system_i.core_v_mini_mcu_i.debug_subsystem_i.dm_obi_top_i.master_wdata_o;
 
 `else
-
-  stimuli_counter = 0;
-% for bank in range(ram_numbanks_cont):
-  for (i = 0; i < NumBytes / NumBanks; i = i + 4) begin
-    tb_writetoSram${bank}(i / 4, stimuli[stimuli_counter+3], stimuli[stimuli_counter+2],
-                   stimuli[stimuli_counter+1], stimuli[stimuli_counter]);
-    stimuli_counter = stimuli_counter + 4;
+% for bank in xheep.iter_ram_banks():
+  for (i=${bank.start_address()}; i < ${bank.end_address()}; i = i + 4) begin
+    if (((i/4) & ${2**bank.il_level()-1}) == ${bank.il_offset()}) begin
+      w_addr = ((i/4) >> ${bank.il_level()}) % ${bank.size()//4};
+      tb_writetoSram${bank.name()}(w_addr, stimuli[i+3], stimuli[i+2],
+                                          stimuli[i+1], stimuli[i]);
+    end
   end
 % endfor
-% if ram_numbanks_il != 0:
-  for (i = 0; i < NumBytes / NumBanks; i = i + 4) begin
-% for bank in range(ram_numbanks_il):
-    tb_writetoSram${int(ram_numbanks_cont) + bank}(i / 4, stimuli[stimuli_counter+3], stimuli[stimuli_counter+2],
-                    stimuli[stimuli_counter+1], stimuli[stimuli_counter]);
-    stimuli_counter = stimuli_counter + 4;
-% endfor
-  end
-% endif
 
 `endif
 
 endtask
 
-% for bank in range(ram_numbanks):
-task tb_writetoSram${bank};
+% for bank in xheep.iter_ram_banks():
+task tb_writetoSram${bank.name()};
   input int addr;
   input [7:0] val3;
   input [7:0] val2;
   input [7:0] val1;
   input [7:0] val0;
 `ifdef VCS
-  force x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr] = {
+  force x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.ram${bank.name()}_i.tc_ram_i.sram[addr] = {
     val3, val2, val1, val0
   };
-  release x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr];
+  release x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.ram${bank.name()}_i.tc_ram_i.sram[addr];
 `else
-  x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.gen_sram[${bank}].ram_i.tc_ram_i.sram[addr] = {
+  x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_i.ram${bank.name()}_i.tc_ram_i.sram[addr] = {
     val3, val2, val1, val0
   };
 `endif
diff --git a/hw/vendor/esl_epfl_x_heep/tb/testharness.sv b/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
index 2a4c7040..9008beb4 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
@@ -88,6 +88,17 @@ module testharness #(
   logic iffifo_in_ready, iffifo_out_valid;
   logic iffifo_int_o;
 
+  // External DMA slots
+  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx;
+  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx;
+
+  assign ext_dma_slot_tx[0] = iffifo_in_ready;
+  assign ext_dma_slot_rx[0] = iffifo_out_valid;
+  if (core_v_mini_mcu_pkg::DMA_CH_NUM > 1) begin
+    assign ext_dma_slot_tx[core_v_mini_mcu_pkg::DMA_CH_NUM-1:1] = '0;
+    assign ext_dma_slot_rx[core_v_mini_mcu_pkg::DMA_CH_NUM-1:1] = '0;
+  end
+
   // External xbar master/slave and peripheral ports
   obi_req_t [EXT_XBAR_NMASTER_RND-1:0] ext_master_req;
   obi_req_t [EXT_XBAR_NMASTER_RND-1:0] heep_slave_req;
@@ -153,6 +164,7 @@ module testharness #(
     $display("%t: the parameter X_EXT is %x", $time, X_EXT);
     $display("%t: the parameter ZFINX is %x", $time, ZFINX);
     $display("%t: the parameter JTAG_DPI is %x", $time, JTAG_DPI);
+    $display("%t: the parameter EXT_DOMAINS is %x", $time, core_v_mini_mcu_pkg::EXTERNAL_DOMAINS);
     $display("%t: the parameter USE_EXTERNAL_DEVICE_EXAMPLE is %x", $time,
              USE_EXTERNAL_DEVICE_EXAMPLE);
     $display("%t: the parameter CLK_FREQUENCY is %d KHz", $time, CLK_FREQUENCY);
@@ -261,8 +273,9 @@ module testharness #(
       .external_subsystem_rst_no(external_subsystem_rst_n),
       .external_ram_banks_set_retentive_no(external_ram_banks_set_retentive_n),
       .external_subsystem_clkgate_en_no(external_subsystem_clkgate_en_n),
-      .ext_dma_slot_tx_i(iffifo_in_ready),
-      .ext_dma_slot_rx_i(iffifo_out_valid)
+      .ext_dma_slot_tx_i(ext_dma_slot_tx),
+      .ext_dma_slot_rx_i(ext_dma_slot_rx),
+      .ext_dma_stop_i('0)
   );
 
   // Testbench external bus
@@ -314,7 +327,7 @@ module testharness #(
   always_ff @(negedge clk_i) begin
     tb_cpu_subsystem_powergate_switch_ack_n[0] <= x_heep_system_i.cpu_subsystem_powergate_switch_n;
     tb_peripheral_subsystem_powergate_switch_ack_n[0] <= x_heep_system_i.peripheral_subsystem_powergate_switch_n;
-    tb_memory_subsystem_banks_powergate_switch_ack_n[0] <= x_heep_system_i.memory_subsystem_banks_powergate_switch_n;
+    tb_memory_subsystem_banks_powergate_switch_ack_n[0] <= x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_banks_powergate_switch_n;
     tb_external_subsystem_powergate_switch_ack_n[0] <= external_subsystem_powergate_switch_n;
     for (int i = 0; i < SWITCH_ACK_LATENCY; i++) begin
       tb_memory_subsystem_banks_powergate_switch_ack_n[i+1] <= tb_memory_subsystem_banks_powergate_switch_ack_n[i];
@@ -333,12 +346,12 @@ module testharness #(
 `ifndef VERILATOR
     force x_heep_system_i.core_v_mini_mcu_i.cpu_subsystem_powergate_switch_ack_ni = delayed_tb_cpu_subsystem_powergate_switch_ack_n;
     force x_heep_system_i.core_v_mini_mcu_i.peripheral_subsystem_powergate_switch_ack_ni = delayed_tb_peripheral_subsystem_powergate_switch_ack_n;
-    force x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_banks_powergate_switch_ack_ni = delayed_tb_memory_subsystem_banks_powergate_switch_ack_n;
+    force x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_banks_powergate_switch_ack_n = delayed_tb_memory_subsystem_banks_powergate_switch_ack_n;
     force external_subsystem_powergate_switch_ack_n = delayed_tb_external_subsystem_powergate_switch_ack_n;
 `else
     x_heep_system_i.cpu_subsystem_powergate_switch_ack_n = delayed_tb_cpu_subsystem_powergate_switch_ack_n;
     x_heep_system_i.peripheral_subsystem_powergate_switch_ack_n = delayed_tb_peripheral_subsystem_powergate_switch_ack_n;
-    x_heep_system_i.memory_subsystem_banks_powergate_switch_ack_n = delayed_tb_memory_subsystem_banks_powergate_switch_ack_n;
+    x_heep_system_i.core_v_mini_mcu_i.memory_subsystem_banks_powergate_switch_ack_n = delayed_tb_memory_subsystem_banks_powergate_switch_ack_n;
     external_subsystem_powergate_switch_ack_n = delayed_tb_external_subsystem_powergate_switch_ack_n;
 `endif
   end
@@ -456,6 +469,7 @@ module testharness #(
       ) dma_i (
           .clk_i,
           .rst_ni,
+          .ext_dma_stop_i('0),
           .reg_req_i(ext_periph_slv_req[testharness_pkg::MEMCOPY_CTRL_IDX]),
           .reg_rsp_o(ext_periph_slv_rsp[testharness_pkg::MEMCOPY_CTRL_IDX]),
           .dma_read_ch0_req_o(ext_master_req[testharness_pkg::EXT_MASTER0_IDX]),
diff --git a/hw/vendor/esl_epfl_x_heep/util/MakefileHelp b/hw/vendor/esl_epfl_x_heep/util/MakefileHelp
index dc5f2901..8e072d0a 100755
--- a/hw/vendor/esl_epfl_x_heep/util/MakefileHelp
+++ b/hw/vendor/esl_epfl_x_heep/util/MakefileHelp
@@ -1,8 +1,7 @@
 #!/bin/bash
-
-FILE=Makefile
 RULE_COLOR="$(tput setaf 6)"
 SECTION_COLOR="$(tput setaf 3)"
+SSECTION_COLOR="$(tput setaf 5)"
 VARIABLE_COLOR="$(tput setaf 2)"
 VALUE_COLOR="$(tput setaf 1)"
 CLEAR_STYLE="$(tput sgr0)"
@@ -17,13 +16,14 @@ echo ""
 
 TARGET_REGEX="^[a-zA-Z0-9%_\/%-]+:"
 SECTION_REGEX="^##\s*@section\s*(.*)$"
+SSECTION_REGEX="^##\s*@subsection\s*(.*)$"
 DOCBLOCK_REGEX="^##\s*(.*)$"
 PARAM_REGEX="@param\s+([a-zA-Z_]+)(=([^\s]+))?\s*(.*$)?"
 
 COMMENT=""
 PARAMS=""
 PARAMS_DOC=""
-cat $FILE | while read line
+cat $FILE_FOR_HELP | while read line
 do
     # do something with $line here
     if [[ ! -z $line ]]
@@ -31,7 +31,11 @@ do
         if [[ $line =~ $SECTION_REGEX ]]
         then
             SECTION_NAME=$(echo $line | sed -e "s/^##\s*@section\s*\(.*\)$/\1/g")
-            echo "$SECTION_COLOR$SECTION_NAME$CLEAR_STYLE:"
+            echo "$SECTION_COLOR$SECTION_NAME:$CLEAR_STYLE"
+        elif [[ $line =~ $SSECTION_REGEX ]]
+        then
+            SECTION_NAME=$(echo $line | sed -e "s/^##\s*@subsection\s*\(.*\)$/\1/g")
+            echo "$SSECTION_COLOR  $SECTION_NAME:$CLEAR_STYLE"
         elif [[ $line =~ $TARGET_REGEX ]]
         then
             # if there is no comment for this target, we don't display it in the docs to keep private targets hidden
diff --git a/hw/vendor/esl_epfl_x_heep/util/generate-makefile-help b/hw/vendor/esl_epfl_x_heep/util/generate-makefile-help
deleted file mode 100755
index 30e4893c..00000000
--- a/hw/vendor/esl_epfl_x_heep/util/generate-makefile-help
+++ /dev/null
@@ -1,2 +0,0 @@
-help:
-	util/MakefileHelp
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py b/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
index 5c86308f..31826540 100755
--- a/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
+++ b/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
@@ -18,6 +18,8 @@
 from mako.template import Template
 import collections
 from math import log2
+import x_heep_gen.load_config
+from x_heep_gen.system import BusType
 
 class Pad:
 
@@ -30,13 +32,25 @@ def remove_comma_io_interface(self):
 
   def create_pad_ring(self):
 
+    # Mapping dictionary from string to integer
+    mapping_dict = {
+        'top' : 'core_v_mini_mcu_pkg::TOP',
+        'right' : 'core_v_mini_mcu_pkg::RIGHT',
+        'bottom' : 'core_v_mini_mcu_pkg::BOTTOM',
+        'left' : 'core_v_mini_mcu_pkg::LEFT'
+    }
+
+    mapping = ''
+    if self.pad_mapping is not None:
+        mapping = ', .SIDE(' + mapping_dict[self.pad_mapping] + ')'
+
     self.interface = '    inout wire ' + self.name + '_io,\n'
 
     if self.pad_type == 'input':
         self.pad_ring_io_interface = '    inout wire ' + self.io_interface + ','
         self.pad_ring_ctrl_interface += '    output logic ' + self.signal_name + 'o,'
         self.pad_ring_instance = \
-            'pad_cell_input #(.PADATTR('+ str(self.attribute_bits) +')) ' + self.cell_name + ' ( \n' + \
+            'pad_cell_input #(.PADATTR('+ str(self.attribute_bits) +')' + mapping + ') ' + self.cell_name + ' ( \n' + \
             '   .pad_in_i(1\'b0),\n' + \
             '   .pad_oe_i(1\'b0),\n' + \
             '   .pad_out_o(' + self.signal_name + 'o),\n' + \
@@ -45,7 +59,7 @@ def create_pad_ring(self):
         self.pad_ring_io_interface = '    inout wire ' + self.io_interface + ','
         self.pad_ring_ctrl_interface += '    input logic ' + self.signal_name + 'i,'
         self.pad_ring_instance = \
-            'pad_cell_output #(.PADATTR('+ str(self.attribute_bits) +')) ' + self.cell_name + ' ( \n' + \
+            'pad_cell_output #(.PADATTR('+ str(self.attribute_bits) +')' + mapping + ') ' + self.cell_name + ' ( \n' + \
             '   .pad_in_i(' + self.signal_name + 'i),\n' + \
             '   .pad_oe_i(1\'b1),\n' + \
             '   .pad_out_o(),\n' + \
@@ -56,7 +70,7 @@ def create_pad_ring(self):
         self.pad_ring_ctrl_interface += '    output logic ' + self.signal_name + 'o,\n'
         self.pad_ring_ctrl_interface += '    input logic ' + self.signal_name + 'oe_i,'
         self.pad_ring_instance = \
-            'pad_cell_inout #(.PADATTR('+ str(self.attribute_bits) +')) ' + self.cell_name + ' ( \n' + \
+            'pad_cell_inout #(.PADATTR('+ str(self.attribute_bits) +')' + mapping + ') ' + self.cell_name + ' ( \n' + \
             '   .pad_in_i(' + self.signal_name + 'i),\n' + \
             '   .pad_oe_i(' + self.signal_name + 'oe_i),\n' + \
             '   .pad_out_o(' + self.signal_name + 'o),\n' + \
@@ -195,13 +209,14 @@ def create_pad_ring_bonding(self):
         self.pad_ring_bonding_bonding += '    .' + self.signal_name + 'oe_i(' + oe_internal_signals + '),'
         self.x_heep_system_interface += '    inout wire ' + self.signal_name + 'io,'
 
-  def __init__(self, name, cell_name, pad_type, index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, has_attribute, attribute_bits):
+  def __init__(self, name, cell_name, pad_type, pad_mapping, index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, has_attribute, attribute_bits):
 
     self.name = name
     self.cell_name = cell_name
     self.index = index
     self.localparam = 'PAD_' + name.upper()
     self.pad_type = pad_type
+    self.pad_mapping = pad_mapping
     self.pad_mux_list = pad_mux_list
 
     if('low' in pad_active):
@@ -285,12 +300,18 @@ def write_template(tpl_path, outdir, outfile, **kwargs):
 
 def main():
     parser = argparse.ArgumentParser(prog="mcugen")
-    parser.add_argument("--cfg",
+    parser.add_argument("--cfg_peripherals",
                         "-c",
                         metavar="file",
                         type=argparse.FileType('r'),
                         required=True,
                         help="A configuration file")
+    
+    parser.add_argument("--config",
+                        metavar="file",
+                        type=str,
+                        required=True,
+                        help="X-Heep general configuration")
 
     parser.add_argument("--pads_cfg",
                         "-pc",
@@ -380,7 +401,7 @@ def main():
         logging.basicConfig(level=logging.DEBUG)
 
     # Read HJSON description of System.
-    with args.cfg as file:
+    with args.cfg_peripherals as file:
         try:
             srcfull = file.read()
             obj = hjson.loads(srcfull, use_decimal=True)
@@ -404,47 +425,21 @@ def main():
 
     outfile = args.outfile
 
+    config_override = x_heep_gen.system.Override(None, None, None)
+
     if args.cpu != None and args.cpu != '':
         cpu_type = args.cpu
     else:
         cpu_type = obj['cpu_type']
 
     if args.bus != None and args.bus != '':
-        bus_type = args.bus
-    else:
-        bus_type = obj['bus_type']
+        config_override.bus_type = BusType(args.bus)
 
     if args.memorybanks != None and args.memorybanks != '':
-        ram_numbanks_cont = int(args.memorybanks)
-    else:
-        ram_numbanks_cont = int(obj['ram']['numbanks'])
+        config_override.numbanks = int(args.memorybanks)
 
     if args.memorybanks_il != None and args.memorybanks_il != '':
-        ram_numbanks_il = int(args.memorybanks_il)
-    else:
-        ram_numbanks_il = int(obj['ram']['numbanks_interleaved'])
-
-    if ram_numbanks_il != 0:
-        log_ram_numbanks_il = int(log2(ram_numbanks_il))
-
-        if not log2(ram_numbanks_il).is_integer():
-            exit("ram interleaved numbanks must be a power of 2 instead of " + str(ram_numbanks_il))
-    else:
-        log_ram_numbanks_il = 0
-
-    if ram_numbanks_il != 0 and bus_type == 'onetoM':
-        exit("bus type must be 'NtoM' instead 'onetoM' to access the interleaved memory banks in parallel" + str(args.bus))
-
-    if ram_numbanks_cont + ram_numbanks_il < 2 and ram_numbanks_cont + ram_numbanks_il > 16:
-        exit("ram numbanks must be between 2 and 16 instead of " + str(ram_numbanks_cont + ram_numbanks_il))
-    else:
-        ram_numbanks = ram_numbanks_cont + ram_numbanks_il
-
-    ram_start_address = string2int(obj['ram']['address'])
-    if int(ram_start_address,16) != 0:
-        exit("ram start address must be 0 instead of " + str(ram_start_address))
-
-    ram_size_address = '{:08X}'.format(ram_numbanks*32*1024)
+        config_override.numbanks_il = int(args.memorybanks_il)
 
     if args.external_domains != None and args.external_domains != '':
         external_domains = int(args.external_domains)
@@ -454,6 +449,12 @@ def main():
     if  external_domains > 32:
         exit("external_domains must be less than 32 instead of " + str(external_domains))
 
+
+
+    xheep = x_heep_gen.load_config.load_cfg_file(pathlib.PurePath(str(args.config)), config_override)
+
+
+
     debug_start_address = string2int(obj['debug']['address'])
     if int(debug_start_address, 16) < int('10000', 16):
         exit("debug start address must be greater than 0x10000")
@@ -503,7 +504,11 @@ def len_extracted_peripherals(peripherals):
 
     ao_peripherals = extract_peripherals(discard_path(obj['ao_peripherals']))
     ao_peripherals_count = len(ao_peripherals)
+    dma_ch_count = ao_peripherals["dma"]["num_channels"]
+    if int(dma_ch_count, 16) > int('256', 16) or int(dma_ch_count, 16) == 0:
+        exit("Number of DMA channels has to be between 0 and 256, excluded")
 
+    dma_ch_size = ao_peripherals["dma"]["ch_length"]
 
     peripheral_start_address = string2int(obj['peripherals']['address'])
     if int(peripheral_start_address, 16) < int('10000', 16):
@@ -519,47 +524,11 @@ def len_extracted_peripherals(peripherals):
     flash_mem_start_address  = string2int(obj['flash_mem']['address'])
     flash_mem_size_address  = string2int(obj['flash_mem']['length'])
 
-    linker_onchip_code_start_address  = string2int(obj['linker_script']['onchip_ls']['code']['address'])
-    linker_onchip_code_size_address  = string2int(obj['linker_script']['onchip_ls']['code']['lenght'])
-
-    if int(linker_onchip_code_size_address,16) < 32*1024:
-        exit("The code section must be at least 32KB, instead it is " + str(linker_onchip_code_size_address))
-
-    linker_onchip_data_start_address  = string2int(obj['linker_script']['onchip_ls']['data']['address'])
-    if (obj['linker_script']['onchip_ls']['data']['lenght'].split()[0].split(",")[0] == "whatisleft"):
-        if ram_numbanks_il == 0 or (ram_numbanks_cont == 1 and ram_numbanks_il > 0):
-            linker_onchip_data_size_address  = str('{:08X}'.format(int(ram_size_address,16) - int(linker_onchip_code_size_address,16)))
-        else:
-            linker_onchip_data_size_address  = str('{:08X}'.format(int(ram_size_address,16) - int(linker_onchip_code_size_address,16) - ram_numbanks_il*32*1024))
-    else:
-        if ram_numbanks_il == 0 or (ram_numbanks_cont == 1 and ram_numbanks_il > 0):
-            linker_onchip_data_size_address  = string2int(obj['linker_script']['onchip_ls']['data']['lenght'])
-        else:
-            linker_onchip_data_size_address  = str('{:08X}'.format(int(string2int(obj['linker_script']['onchip_ls']['data']['lenght']),16) - ram_numbanks_il*32*1024))
-
-    linker_onchip_il_start_address = str('{:08X}'.format(int(linker_onchip_data_start_address,16) + int(linker_onchip_data_size_address,16)))
-    linker_onchip_il_size_address = str('{:08X}'.format(ram_numbanks_il*32*1024))
-
     stack_size  = string2int(obj['linker_script']['stack_size'])
     heap_size  = string2int(obj['linker_script']['heap_size'])
 
 
-    linker_flash_code_start_address  = str('{:08X}'.format(int(linker_onchip_code_start_address,16) + int(flash_mem_start_address,16)))
-    linker_flash_data_start_address  = str('{:08X}'.format(int(linker_onchip_data_start_address,16) + int(flash_mem_start_address,16)))
-    linker_flash_il_start_address    = str('{:08X}'.format(int(linker_onchip_il_start_address,16)   + int(flash_mem_start_address,16)))
-
-    if ram_numbanks_il == 0 or (ram_numbanks_cont == 1 and ram_numbanks_il > 0):
-        linker_flash_left_start_address   = str('{:08X}'.format(int(linker_flash_data_start_address,16) + int(linker_onchip_data_size_address,16)))
-        linker_flash_left_size_address    = str('{:08X}'.format(int(flash_mem_size_address,16) - int(linker_onchip_code_size_address,16) - int(linker_onchip_data_size_address,16)))
-    else:
-        linker_flash_left_start_address   = str('{:08X}'.format(int(linker_flash_il_start_address,16) + int(linker_onchip_il_size_address,16)))
-        linker_flash_left_size_address    = str('{:08X}'.format(int(flash_mem_size_address,16) - int(linker_onchip_code_size_address,16) - int(linker_onchip_data_size_address,16) - int(linker_onchip_il_size_address,16)))
-
-
-    if ((int(linker_onchip_data_size_address,16) + int(linker_onchip_code_size_address,16)) > int(ram_size_address,16)):
-        exit("The code and data section must fit in the RAM size, instead they takes " + str(linker_onchip_data_size_address + linker_onchip_code_size_address))
-    
-    if ((int(stack_size,16) + int(heap_size,16)) > int(ram_size_address,16)):
+    if ((int(stack_size,16) + int(heap_size,16)) > xheep.ram_size_address()):
         exit("The stack and heap section must fit in the RAM size, instead they takes " + str(stack_size + heap_size))
 
 
@@ -610,7 +579,7 @@ def len_extracted_peripherals(peripherals):
 
         pad_name = key
         pad_num  = pads[key]['num']
-        pad_type = pads[key]['type']
+        pad_type = pads[key]['type'].strip(',')
 
         try:
             pad_offset = int(pads[key]['num_offset'])
@@ -621,6 +590,11 @@ def len_extracted_peripherals(peripherals):
             pad_active = pads[key]['active']
         except KeyError:
             pad_active = 'high'
+        
+        try:
+            pad_mapping = pads[key]['mapping'].strip(',')
+        except KeyError:
+            pad_mapping = None
 
         try:
             pad_mux_list_hjson = pads[key]['mux']
@@ -676,13 +650,13 @@ def len_extracted_peripherals(peripherals):
             except KeyError:
                 pad_skip_declaration_mux = False
 
-            p = Pad(pad_mux, '', pads[key]['mux'][pad_mux]['type'], 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits)
+            p = Pad(pad_mux, '', pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits)
             pad_mux_list.append(p)
 
         if pad_num > 1:
             for p in range(pad_num):
                 pad_cell_name = "pad_" + key + "_" + str(p+pad_offset) + "_i"
-                pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+                pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
                 if not pad_keep_internal:
                     pad_obj.create_pad_ring()
                 pad_obj.create_core_v_mini_mcu_ctrl()
@@ -701,7 +675,7 @@ def len_extracted_peripherals(peripherals):
 
         else:
             pad_cell_name = "pad_" + key + "_i"
-            pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+            pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
             if not pad_keep_internal:
                 pad_obj.create_pad_ring()
             pad_obj.create_core_v_mini_mcu_ctrl()
@@ -736,6 +710,11 @@ def len_extracted_peripherals(peripherals):
             except KeyError:
                 pad_active = 'high'
 
+            try:
+                pad_mapping = external_pads[key]['mapping']
+            except KeyError:
+                pad_mapping = None
+
             try:
                 pad_mux_list_hjson = external_pads[key]['mux']
             except KeyError:
@@ -782,13 +761,13 @@ def len_extracted_peripherals(peripherals):
                 except KeyError:
                     pad_skip_declaration_mux = False
 
-                p = Pad(pad_mux, '', external_pads[key]['mux'][pad_mux]['type'], 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits)
+                p = Pad(pad_mux, '', external_pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits)
                 pad_mux_list.append(p)
 
             if pad_num > 1:
                 for p in range(pad_num):
                     pad_cell_name = "pad_" + key + "_" + str(p+pad_offset) + "_i"
-                    pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+                    pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
                     pad_obj.create_pad_ring()
                     pad_obj.create_pad_ring_bonding()
                     pad_obj.create_internal_signals()
@@ -804,7 +783,7 @@ def len_extracted_peripherals(peripherals):
 
             else:
                 pad_cell_name = "pad_" + key + "_i"
-                pad_obj = Pad(pad_name, pad_cell_name, pad_type, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+                pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
                 pad_obj.create_pad_ring()
                 pad_obj.create_pad_ring_bonding()
                 pad_obj.create_internal_signals()
@@ -838,21 +817,17 @@ def len_extracted_peripherals(peripherals):
     total_pad_list.append(last_pad)
 
     kwargs = {
+        "xheep"                            : xheep,
         "cpu_type"                         : cpu_type,
-        "bus_type"                         : bus_type,
-        "ram_start_address"                : ram_start_address,
-        "ram_numbanks"                     : ram_numbanks,
-        "ram_numbanks_cont"                : ram_numbanks_cont,
-        "ram_numbanks_il"                  : ram_numbanks_il,
-        "log_ram_numbanks_il"              : log_ram_numbanks_il,
         "external_domains"                 : external_domains,
-        "ram_size_address"                 : ram_size_address,
         "debug_start_address"              : debug_start_address,
         "debug_size_address"               : debug_size_address,
         "ao_peripheral_start_address"      : ao_peripheral_start_address,
         "ao_peripheral_size_address"       : ao_peripheral_size_address,
         "ao_peripherals"                   : ao_peripherals,
         "ao_peripherals_count"             : ao_peripherals_count,
+        "dma_ch_count"                     : dma_ch_count,
+        "dma_ch_size"                      : dma_ch_size,
         "peripheral_start_address"         : peripheral_start_address,
         "peripheral_size_address"          : peripheral_size_address,
         "peripherals"                      : peripherals,
@@ -861,17 +836,6 @@ def len_extracted_peripherals(peripherals):
         "ext_slave_size_address"           : ext_slave_size_address,
         "flash_mem_start_address"          : flash_mem_start_address,
         "flash_mem_size_address"           : flash_mem_size_address,
-        "linker_flash_code_start_address"  : linker_flash_code_start_address,
-        "linker_flash_data_start_address"  : linker_flash_data_start_address,
-        "linker_flash_il_start_address"    : linker_flash_il_start_address,
-        "linker_flash_left_start_address"  : linker_flash_left_start_address,
-        "linker_flash_left_size_address"   : linker_flash_left_size_address,
-        "linker_onchip_code_start_address" : linker_onchip_code_start_address,
-        "linker_onchip_code_size_address"  : linker_onchip_code_size_address,
-        "linker_onchip_data_start_address" : linker_onchip_data_start_address,
-        "linker_onchip_data_size_address"  : linker_onchip_data_size_address,
-        "linker_onchip_il_start_address"   : linker_onchip_il_start_address,
-        "linker_onchip_il_size_address"    : linker_onchip_il_size_address,
         "stack_size"                       : stack_size,
         "heap_size"                        : heap_size,
         "plic_used_n_interrupts"           : plic_used_n_interrupts,
diff --git a/hw/vendor/esl_epfl_x_heep/util/structs_periph_gen.py b/hw/vendor/esl_epfl_x_heep/util/structs_periph_gen.py
index c737370c..79608eea 100644
--- a/hw/vendor/esl_epfl_x_heep/util/structs_periph_gen.py
+++ b/hw/vendor/esl_epfl_x_heep/util/structs_periph_gen.py
@@ -1,6 +1,9 @@
 import hjson
 import structs_gen
 
+# Path to the dma file
+dma_file_path = "./sw/device/lib/drivers/dma/dma_structs.h" 
+
 # Path to the header_structs template
 template_path = "./sw/device/lib/drivers/template.tpl"
 
@@ -40,6 +43,26 @@ def scan_peripherals(json_list):
                 add_peripheral(p, json_list[p]["path"])
 
 
+def format_dma_channels(file_path, new_string):
+    
+    try:
+        # Read the contents of the file
+        with open(file_path, 'r') as file:
+            content = file.read()
+        
+        # Replace 'DMA_START_ADDRESS' with 'new_address'
+        updated_content = content.replace('#define dma_peri ((volatile dma *) DMA_START_ADDRESS)', new_string)
+        
+        # Write the updated content back to the file
+        with open(file_path, 'w') as file:
+            file.write(updated_content)
+        
+        print("DMA channel has been successfully updated.")
+        
+    except FileNotFoundError:
+        print(f"The file {file_path} does not exist.")
+    except Exception as e:
+        print(f"An error occurred: {str(e)}")
 
     # for i in range(len(JSON_FILES)):
     #     print("{}\n{}\n{}\n\n\n".format(PERIPHERAL_NAMES[i], JSON_FILES[i], OUTPUT_FILES[i]))
@@ -64,4 +87,7 @@ def scan_peripherals(json_list):
                                 # "--peripheral_name", PERIPHERAL_NAMES[i],
                                 "--json_filename", JSON_FILES[i], 
                                 "--output_filename", OUTPUT_FILES[i]]
-                            )
\ No newline at end of file
+                            )
+    
+    new_string = "#define dma_peri(channel) ((volatile dma *) (DMA_START_ADDRESS + DMA_CH_SIZE * channel))"
+    format_dma_channels(dma_file_path, new_string)
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/util/test_all.sh b/hw/vendor/esl_epfl_x_heep/util/test_all.sh
index 60d45a28..dd0d0374 100755
--- a/hw/vendor/esl_epfl_x_heep/util/test_all.sh
+++ b/hw/vendor/esl_epfl_x_heep/util/test_all.sh
@@ -338,7 +338,7 @@ sed 's/is_included: "no",/is_included: "yes",/' -i mcu_cfg.hjson
 
 if [ $DEBUG -eq 0 ];	 then
 	# The MCU is generated with several memory banks to avoid example code not fitting.
-	make mcu-gen MEMORY_BANKS=3 EXTERNAL_DOMAINS=1
+	make mcu-gen X_HEEP_CFG=configs/testall.hjson EXTERNAL_DOMAINS=1
 
 	if [ "$SIMULATOR" != "none" ]; then
 	# Make the simualtion model
@@ -348,6 +348,14 @@ if [ $DEBUG -eq 0 ];	 then
 	echo -e "${WHITE}Building simulation model $SIM_MODEL_CMD ${RESET}"
 	echo -e ${LONG_W}
 
+	if [ "$OPT" == "1" ] && [ "$SIMULATOR" == "questasim" ]; then
+		# Perform optimization
+		SIM_MODEL_CMD=${SIM_MODEL_CMD}"-opt"
+		echo -e ${LONG_W}
+		echo -e "${WHITE}Optimizing simulation model ${RESET}"
+		echo -e ${LONG_W}
+	fi
+
 	make $SIM_MODEL_CMD
 	fi
 fi
diff --git a/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/__init__.py b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/__init__.py
new file mode 100644
index 00000000..c1a6b006
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/__init__.py
@@ -0,0 +1,4 @@
+from .system import XHeep
+from . import system
+from . import load_config
+from . import ram_bank
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/linker_section.py b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/linker_section.py
new file mode 100644
index 00000000..1f5fe468
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/linker_section.py
@@ -0,0 +1,80 @@
+from dataclasses import *
+from typing import Optional
+
+@dataclass
+class LinkerSection():
+    """
+    Object representing a section in the linker configuration.
+
+    If the end address is set to `None` it will be infered in the building process.
+    """
+
+    name: str
+    """
+    The name of the section
+    
+    The name can be anything that does not collide with section names used by the linker,
+    except code and data that are used to configure the size of the code and data part.
+    code and data do not only contain the actual .code and .data section but other related sections.
+    """
+
+    start: int
+    """The start address"""
+
+    end: Optional[int]
+    """The end address"""
+
+    def __post_init__(self):
+        self.check()
+
+    def check(self):
+        """
+        Does basic type checking and sanity checking.
+
+        - Checks the type of all members
+        - Checks that the name is not empty
+        - Checks that the start address and size are positive
+
+        :raise TypeError: when the type of a member is not the correct ine.
+        :raise ValueError: when the name is empty or start or size are negative
+        """
+        if type(self.name) is not str:
+            raise TypeError("name should be of type str")
+        if type(self.start) is not int:
+            raise TypeError("start should be of type int")
+        if type(self.end) is not int and self.end is not None:
+            raise TypeError("end should be of type int")
+        
+        if self.name == "":
+            raise ValueError("name should not be empty")
+        if self.start < 0:
+            raise ValueError("start address should be positif")
+        if self.end is not None and self.end <= self.start:
+            raise ValueError("end address should be bigger than the start address")
+
+    @staticmethod
+    def by_size(name: str, start: int, size: int) -> "LinkerSection":
+        """
+        Creates a Linker Section by it's size rather than end address.
+
+        :param str name: the name of the section
+        :param int start: the start address
+        :param int size: the size of the section
+        :return: the linker section
+        :rtype: LinkerSection
+        """
+        if type(name) is not str:
+            raise TypeError("name should be of type str")
+        if type(start) is not int:
+            raise TypeError("start should be of type int")
+        if type(size) is not int:
+            raise TypeError("size should be of type int")
+        
+        return LinkerSection(name, start, start + size)
+    
+    @property
+    def size(self) -> Optional[int]:
+        """The size in Bytes"""
+        if self.end is not None:
+            return self.end - self.start
+        return None
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/load_config.py b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/load_config.py
new file mode 100644
index 00000000..1c2da738
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/load_config.py
@@ -0,0 +1,293 @@
+import importlib
+from pathlib import PurePath
+from typing import List, Optional, Union
+import hjson
+
+from .linker_section import LinkerSection
+from .system import BusType, Override, XHeep
+
+def to_int(input) -> Union[int, None]:
+    if type(input) is int:
+        return input
+    
+    if type(input) is str:
+        base = 10
+        if len(input) >= 2:
+            if input[0:2].upper() == "0X":
+                base = 16
+                input = input[2:]
+            elif input[0:2] == "0o":
+                base = 8
+                input = input[2:]
+            elif input[0:2].upper() == "0b":
+                base = 2
+                input = input[2:]
+
+        return int(input, base)
+    return None
+
+
+def ram_list(l: "List[int]", entry):
+    """
+    Parses the hjson ram bank configuration in continuous mode.
+
+    :param List[int] l: the list where bank sizes in kiB should be added
+    :enrtry: the entry to be parsed. It should be a list an integer or an continuous dictionary
+    :raise RuntimeError: when an invalid configuration is processed.
+    """
+    if type(l) is not list:
+        raise TypeError("l should be of type list")
+    
+    if type(entry) is int:
+        l.append(entry)
+        return
+    
+    if type(entry) is list:
+        for i in entry:
+            ram_list(l, i)
+        return
+    
+    if type(entry) is hjson.OrderedDict:
+        num = 1
+        if "num" in entry:
+            if type(entry["num"]) is not int:
+                raise RuntimeError("if the num field is present in ram configuration it should be an integer")
+            num = entry["num"]
+        
+        if "sizes" in entry:
+            for _ in range(num):
+                ram_list(l, entry["sizes"])
+            return
+        else:
+            raise RuntimeError("dictionaries in continuous ram configuration sections should at least have a sizes entry")
+    
+    raise RuntimeError("entries in ram configuration should either be integer, lists, or dictionaries")
+
+
+
+def load_ram_configuration(system: XHeep, mem: hjson.OrderedDict):
+    """
+    Reads the whole ram configuration.
+
+    :param XHeep system: the system object where the ram should be added.
+    :param hjson.OrderedDict mem: The configuration part with the ram informations.
+    :raise TypeError: when arguments do not have the right type
+    :raise RuntimeError: when an invalid configuration is processed.
+    """
+    if not isinstance(system, XHeep):
+        raise TypeError("system should be an instance of XHeep object")
+    if type(mem) is not hjson.OrderedDict:
+        raise TypeError("mem should be of type hjson.OrderedDict")
+
+    for key, value in mem.items():
+        if type(value) is not hjson.OrderedDict:
+            raise RuntimeError("Ram configuration entries should be dictionaries")
+        
+        section_name = ""
+        if "auto_section" in value and value["auto_section"] == "auto":
+            section_name = key
+
+        t = "continuous"
+        if "type" in value:
+            t = value["type"]
+            if type(t) is not str:
+                raise RuntimeError("ram type should be a string")
+            if t != "continuous" and t != "interleaved":
+                raise RuntimeError(f"ram type should be continuous or interleaved not {t}")
+        
+        if t == "interleaved":
+            if "num" not in value or type(value["num"]) is not int:
+                raise RuntimeError("The num field is required for interleaved ram section and should be an integer")
+            
+            if "size" not in value or type(value["size"]) is not int:
+                raise RuntimeError("The size field is required for interleaved ram section and should be an integer")
+            
+            system.add_ram_banks_il(int(value["num"]), int(value["size"]), section_name)
+
+        elif t == "continuous":
+            banks: List[int] = []
+            ram_list(banks, value)
+            system.add_ram_banks(banks, section_name)
+
+
+
+def load_linker_config(system: XHeep, config: list):
+    """
+    Reads the whole linker section configuration.
+
+    :param XHeep system: the system object where the sections should be added.
+    :param hjson.OrderedDict mem: The configuration part with the section informations.
+    :raise TypeError: when arguments do not have the right type
+    :raise RuntimeError: when an invalid configuration is processed.
+    """
+    if type(config) is not list:
+        raise RuntimeError("Linker Section configuraiton should be a list.")
+    
+    for l in config:
+        if type(l) is not hjson.OrderedDict:
+            raise RuntimeError("Sections should be represented as Dictionaries")
+        if "name" not in l:
+            raise RuntimeError("All sections should have names")
+        
+        if "start" not in l:
+            raise RuntimeError("All sections should have a start")
+        
+        name = l["name"]
+        start = to_int(l["start"])
+
+        if type(name) is not str:
+            raise RuntimeError("Section names should be strings")
+        
+        if name == "":
+            raise RuntimeError("Section names should not be empty")
+        
+        if type(start) is not int:
+            raise RuntimeError("The start of a section should be an integer")
+        
+        if "size" in l and "end" in l:
+            raise RuntimeError("Each section should only specify end or size.")
+        
+        end = 0
+        if "size" in l:
+            size = to_int(l["size"])
+            if size is None:
+                raise RuntimeError("Section sizes should be an integer")
+            if size <= 0:
+                raise RuntimeError("Section sizes should be strictly positive")
+            end = start + size
+        
+        elif "end" in l:
+            end = to_int(l["end"])
+            if end is None:
+                raise RuntimeError("End address should be an integer")
+            if end <= start:
+                raise RuntimeError("Sections should end after their start")
+        else:
+            end = None
+        
+        system.add_linker_section(LinkerSection(name, start, end))
+
+
+
+
+def load_cfg_hjson(src: str, override: Optional[Override] = None) -> XHeep:
+    """
+    Loads the configuration passed as a hjson string and creates an object representing the mcu.
+
+    :param str src: configuration content
+    :param Optional[Override] override: configs to be overriden
+    :return: the object representing the mcu configuration
+    :rtype: XHeep
+    :raise RuntimeError: when and invalid configuration is passed or when the sanity checks failed
+    """
+    config = hjson.loads(src, parse_int=int, object_pairs_hook=hjson.OrderedDict)
+    mem_config = None
+    bus_config = None
+    ram_address_config = None
+    linker_config = None
+
+    for key, value in config.items():
+        if key == "ram_banks":
+            mem_config = value
+        elif key == "bus_type":
+            bus_config = value
+        elif key == "ram_address":
+            ram_address_config = value
+        elif key == "linker_sections":
+            linker_config = value
+
+    if mem_config is None:
+        raise RuntimeError("No memory configuration found")
+    if bus_config is None:
+        raise RuntimeError("No bus type configuration found")
+    
+    ram_start = 0
+    if ram_address_config is not None:
+        if type(ram_address_config) is not int:
+            RuntimeError("The ram_address should be an intger")
+        ram_start = ram_address_config
+
+    system = XHeep(BusType(bus_config), ram_start, override=override)
+    load_ram_configuration(system, mem_config)
+
+    if linker_config is not None:
+        load_linker_config(system, linker_config)
+
+    system.build()
+    if not system.validate():
+        raise RuntimeError("Could not validate system configuration")
+    return system
+
+
+
+def _chk_purep(f):
+    """
+    Helper to check the type is `PurePath`
+
+    :param f: object to check
+    :raise TypeError: when object is of wrong type.
+    """
+    if not isinstance(f, PurePath):
+        raise TypeError("parameter should be of type PurePath")
+
+
+
+def load_cfg_hjson_file(f: PurePath, override: Optional[Override] = None) -> XHeep:
+    """
+    Loads the configuration passed in the path as hjson and creates an object representing the mcu.
+
+    :param PurePath f: path of the configuration
+    :param Optional[Override] override: configs to be overriden
+    :return: the object representing the mcu configuration
+    :rtype: XHeep
+    :raise RuntimeError: when and invalid configuration is passed or when the sanity checks failed
+    """
+    _chk_purep(f)
+
+    with open(f, "r") as file:
+         return load_cfg_hjson(file.read(), override)
+    
+
+
+def load_cfg_script_file(f: PurePath) -> XHeep:
+    """
+    Executes the python file passed as argument to cinfigure the system.
+
+    This file should have a function config that takes no parameters and returns an instance (or subclass) of the XHeep type.
+    The script can import modules from the util directory.
+    The script should not have side effects as it is called multiple time in the current makefile.
+
+    :param PurePath f: path of the configuration
+    :return: the object representing the mcu configuration
+    :rtype: XHeep
+    :raise RuntimeError: when and invalid configuration is passed or when the sanity checks failed
+    """
+    _chk_purep(f)
+
+    spec = importlib.util.spec_from_file_location("configs._config", f)
+    mod = importlib.util.module_from_spec(spec)
+    spec.loader.exec_module(mod)
+
+    return mod.config()
+    
+
+
+def load_cfg_file(f: PurePath, override: Optional[Override] = None) -> XHeep:
+    """
+    Load the Configuration by extension type. It currently supports .hjson and .py
+
+    :param PurePath f: path of the configuration
+    :param Optional[Override] override: configs to be overriden
+    :return: the object representing the mcu configuration
+    :rtype: XHeep
+    :raise RuntimeError: when and invalid configuration is passed or when the sanity checks failed
+    """
+    _chk_purep(f)
+
+    if f.suffix == ".hjson":
+        return load_cfg_hjson_file(f, override)
+    
+    if f.suffix == ".py":
+        return load_cfg_script_file(f)
+    
+    raise RuntimeError(f"unsupported file extension {f.suffix}")
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/ram_bank.py b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/ram_bank.py
new file mode 100644
index 00000000..20f043eb
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/ram_bank.py
@@ -0,0 +1,133 @@
+from dataclasses import *
+
+def is_pow2(n: int) -> bool:
+    """
+    check if n is a power of two
+
+    :param int n: number to be checked
+    :return: True if n is a power of two
+    :rtype: bool
+    """
+    return n > 0 and (n & (n-1)) == 0
+
+
+
+class Bank():
+    """
+    Represents a ram bank
+
+    :param int size_k: size in kiB
+    :param int start_address: start address of the bank, in interleaved mode it should be the start address od the whole group
+    :param int map_idx: index in the global address map. Has to be unique. Interleaved mode banks should have consecutive indices.
+    :param int il_level: number of bits used for interleaving.
+    :param int il_offset: position in interleaved bank group if in any else 0. Should be consistent with map_idx.
+    :raise TypeError: when parameters don't have the right type.
+    :raise ValueError: when size_k isn't a power of two.
+    :raise ValueError: when start_address is not aligned on size.
+    :raise ValueError: when il_offset is to big for the given il_level().
+    """
+    def __init__(self, size_k: int, start_address: int, map_idx: int, il_level: int = 0, il_offset: int = 0):
+        if not type(size_k) is int:
+            raise TypeError("Bank size should be an int")
+        
+        if not type(start_address) is int:
+            raise TypeError("Start address should be an int")
+        
+        if not type(map_idx) is int:
+            raise TypeError("map_idx size should be an int")
+        
+        if not type(il_level) is int:
+            raise TypeError("il_level should be an int")
+        
+        if not type(il_offset) is int:
+            raise TypeError("il_offset size should be an int")
+        
+        self._size_k: int = size_k
+        self._start_address: int = start_address
+        self._map_idx: int = map_idx
+        self._il_level: int = il_level
+        self._il_offset: int = il_offset
+        
+        # check if power of 2
+        if not is_pow2(self._size_k):
+            raise ValueError(f"Bank size {self._size_k}kiB is not a positive power of two")
+        
+        if self._il_offset >= 2**self._il_level:
+            raise ValueError(f"il_offset is to big for an il_level of {self._il_level}")
+        
+        mask = 0b11
+        if not self._start_address & mask == 0:
+            raise ValueError(f"start_address is not aligned on word size")
+        
+
+        #TODO: Validate start address
+        
+        self._end_address = self._start_address + self._size_k*1024 * 2**self._il_level
+    
+    def size(self) -> int:
+        """
+        :return: the bank size in Bytes
+        :rtype: int
+        """
+        return self._size_k * 1024
+    
+    def name(self) -> str:
+        """
+        :return: the bank name
+        :rtype: str
+        """
+        return str(self._map_idx-1) #TODO: do something better
+    
+    def start_address(self) -> int:
+        """
+        :return: the start address
+        :rtype: int
+        """
+        return self._start_address
+    
+    def end_address(self) -> int:
+        """
+        :return: the end address
+        :rtype: int
+        """
+        return self._end_address
+    
+    def map_idx(self) -> int:
+        """
+        :return: the index used in global bus
+        :rtype: int
+        """
+        return self._map_idx
+    
+    def il_level(self) -> int:
+        """
+        :return: the number of bits used to choose the bank when it is in an interleaved group else 0
+        :rtype: int
+        """
+        return self._il_level
+    
+    def il_offset(self) -> int:
+        """
+        :return: the position of the bank in an interleaved group.
+        :rtype: int
+        """
+        return self._il_offset
+    
+@dataclass
+class ILRamGroup():
+    """
+    Dataclass to represent information about interleaved memory banks group.
+    """
+    
+    start: int
+    """start address of the group"""
+
+    size: int
+    """size of the group"""
+
+    n: int
+    """number of banks in the group"""
+
+    first_name: str
+    """name of the first bank"""
+    
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/system.py b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/system.py
new file mode 100644
index 00000000..09e4a855
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/util/x_heep_gen/system.py
@@ -0,0 +1,430 @@
+from copy import deepcopy
+from dataclasses import dataclass
+from typing import Generator, Iterable, List, Optional, Set, Union
+from enum import Enum
+from .ram_bank import Bank, is_pow2, ILRamGroup
+from .linker_section import LinkerSection
+
+class BusType(Enum):
+    """Enumeration of all supported bus types"""
+
+    onetoM = 'onetoM'
+    NtoM   = 'NtoM'
+
+
+@dataclass
+class Override():
+    """
+    Bundles information that can be overriden in the XHeep class.
+    """
+    bus_type: Optional[BusType]
+    numbanks: Optional[int]
+    numbanks_il: Optional[int]
+
+
+
+class XHeep():
+    """
+    This object represents the whole mcu.
+
+    An instance of this object is also passed to the mako templates.
+
+    :param BusType bus_type: The bus type chosen for this mcu.
+    :param int ram_start_address: The address of the first ram bank. For now only 0 is tested. Defaults to 0.
+    :param Optional[Override] override: configs to be overriden
+    :raise TypeError: when parameters are of incorrect type.
+    """
+
+    IL_COMPATIBLE_BUS_TYPES: "Set[BusType]" = set([BusType.NtoM])
+    """Constant set of bus types that support interleaved memory banks"""
+    
+    
+    
+    def __init__(self, bus_type: BusType, ram_start_address: int = 0, override: Optional[Override] = None):
+        if not type(bus_type) is BusType:
+            raise TypeError(f"XHeep.bus_type should be of type BusType not {type(self._bus_type)}")
+        if not type(ram_start_address) is int:
+            raise TypeError("ram_start_address should be of type int")
+
+        if ram_start_address != 0:
+            raise ValueError(f"ram start address must be 0 instead of {ram_start_address}")
+
+        self._bus_type: BusType = bus_type
+        if override is not None and override.bus_type is not None:
+            self._bus_type = override.bus_type
+
+
+        self._ram_start_address: int = ram_start_address
+        self._ram_banks: List[Bank] = []
+        self._ram_banks_il_idx: List[int] = []
+        self._ram_banks_il_groups: List[ILRamGroup] = []
+        self._il_banks_present: bool = False
+        self._ram_next_idx: int = 1
+        self._ram_next_addr: int = self._ram_start_address
+        self._linker_sections: List[LinkerSection] = []
+        self._used_section_names: Set[str] = set()
+
+        self._ignore_ram_continous: bool = False
+        self._ignore_ram_interleaved: bool = False
+
+        if override is not None and override.numbanks is not None:
+            self.add_ram_banks([32]*override.numbanks)
+            self._ignore_ram_continous = True
+        if override is not None and override.numbanks_il is not None:
+            self._ignore_ram_interleaved = True
+            self._override_numbanks_il = override.numbanks_il
+
+
+    def add_ram_banks(self, bank_sizes: "List[int]", section_name: str = ""):
+        """
+        Add ram banks in continuous address mode to the system.
+        The bank size should be a power of two and at least 1kiB.
+
+        :param List[int] bank_sizes: list of bank sizes in kiB that should be added to the system
+        :param str section_name: If not empty adds automatically a linker section for this banks. The names must be unique and not be used by the linker for other purposes.
+        :raise TypeError: when arguments are of wrong type
+        :raise ValueError: when banks have an incorrect size.
+        :raise ValueError: if the name was allready used for another section or the first and second are not code and data.
+        :raise ValueError: if bank_sizes list is empty
+        """
+
+        if self._ignore_ram_continous:
+            return
+
+        if not type(bank_sizes) == list:
+            raise TypeError("bank_sizes should be of type list")
+        if not type(section_name) == str:
+            raise TypeError("section_name should be of type str")
+        if len(bank_sizes) == 0:
+            raise ValueError("bank_sizes is empty")
+
+        banks: List[Bank] = []
+        for b in bank_sizes:
+            banks.append(Bank(b, self._ram_next_addr, self._ram_next_idx, 0, 0))
+            self._ram_next_addr = banks[-1]._end_address
+            self._ram_next_idx += 1
+        
+        if section_name != "":
+            self.add_linker_section_for_banks(banks, section_name)
+        # Add all new banks if no error was raised
+        self._ram_banks += banks
+
+    
+
+
+    def add_ram_banks_il(self, num: int, bank_size: int, section_name: str = "", ignore_ignore: bool = False):
+        """
+        Add ram banks in interleaved mode to the system.
+        The bank size should be a power of two and at least 1kiB,
+        the number of banks should also be a power of two.
+
+        :param int num: number of banks to add
+        :param int bank_size: size of the banks in kiB
+        :param str section_name: If not empty adds automatically a linker section for this banks. The names must be unique and not be used by the linker for other purposes.
+        :param bool ignore_ignore: Ignores the fact that an override was set. For internal uses to apply this override.
+        :raise TypeError: when arguments are of wrong type
+        :raise ValueError: when banks have an incorrect size or their number is not a power of two.
+        :raise ValueError: if the name was allready used for another section or the first and second are not code and data.
+        """
+        if self._ignore_ram_interleaved and not ignore_ignore:
+            return
+
+        if not self._bus_type in self.IL_COMPATIBLE_BUS_TYPES:
+            raise RuntimeError(f"This system has a {self._bus_type} bus, one of {self.IL_COMPATIBLE_BUS_TYPES} is required for interleaved memory")
+        if not type(num) == int:
+            raise TypeError("num should be of type int")
+        if not is_pow2(num):
+            raise ValueError(f"A power of two is required for the number of banks, got {num}")
+        if not type(section_name) == str:
+            raise TypeError("section_name should be of type str")
+
+        first_il = self.ram_numbanks()
+
+        banks: List[Bank] = []
+        for i in range(num):
+            banks.append(Bank(bank_size, self._ram_next_addr, self._ram_next_idx, num.bit_length()-1, i))
+            self._ram_next_idx += 1
+        
+        self._ram_next_addr = banks[-1]._end_address
+        
+        if section_name != "":
+            self.add_linker_section_for_banks(banks, section_name)
+        # Add all new banks if no error was raised
+        self._ram_banks += banks
+
+        indices = range(first_il, first_il + num)
+        self._ram_banks_il_idx += indices
+        self._ram_banks_il_groups.append(ILRamGroup(banks[0].start_address(), bank_size*num*1024, len(banks), banks[0].name()))
+        self._il_banks_present = True
+    
+
+
+    def add_linker_section_for_banks(self, banks: "List[Bank]", name: str):
+        """
+        Function to add linker sections coupled to some banks.
+        :param List[Bank] banks: list of banks that compose the section, assumed to be continuous in memory
+        :param str name: the name of the section.
+        :raise ValueError: if the name was allready used for another section or the first and second are not code and data.
+        """
+        if name in self._used_section_names:
+            raise ValueError("linker section names should be unique")
+        
+        self._used_section_names.add(name)
+        self._linker_sections.append(LinkerSection(name, banks[0].start_address(), banks[-1].end_address()))
+    
+    def add_linker_section(self, section: LinkerSection):
+        """
+        Function to add a linker section.
+        :param LinkerSection section: Linker section to add.
+        :param str name: the name of the section.
+        :raise ValueError: if the name was allready used for another section or the first and second are not code and data.
+        """
+
+        if not isinstance(section, LinkerSection):
+            raise TypeError("section should be an instance of LinkerSection")
+        
+        section.check()
+
+        if section.name in self._used_section_names:
+            raise ValueError("linker section names should be unique")
+
+        self._used_section_names.add(section.name)
+        self._linker_sections.append(deepcopy(section))
+        
+
+
+    def bus_type(self) -> BusType:
+        """
+        :return: the configured bus type
+        :rtype: BusType
+        """
+        return self._bus_type
+    
+    def ram_start_address(self) -> int:
+        """
+        :return: the address of the first ram bank.
+        :rtype: int
+        """
+        return self._ram_start_address
+
+    def ram_numbanks(self) -> int:
+        """
+        :return: the number of banks.
+        :rtype: int
+        """
+        return len(self._ram_banks)
+    
+
+
+    def ram_numbanks_il(self) -> int:
+        """
+        :return: the number of interleaved banks.
+        :rtype: int
+        """
+        return len(self._ram_banks_il_idx)
+    
+
+
+    def ram_numbanks_cont(self) -> int:
+        """
+        :return: the number of continuous banks.
+        :rtype: int
+        """
+        return self.ram_numbanks() - self.ram_numbanks_il()
+    
+
+
+    def validate(self) -> bool:
+        """
+        Does some basics checks on the configuration
+
+        This should be called before using the XHeep object to generate the project.
+
+        :return: the validity of the configuration
+        :rtype: bool
+        """
+        if not self.ram_numbanks() in range(2, 17):
+            print(f"The number of banks should be between 2 and 16 instead of {self.ram_numbanks()}") #TODO: clarify upper limit
+            return False
+        
+        if not ("code" in self._used_section_names and "data" in self._used_section_names):
+            print("The code and data sections are needed")
+            return False
+        
+        for l in self._linker_sections:
+            l.check()
+
+        ret = True
+        old_sec: Union[LinkerSection,None] = None
+
+        for i, sec in enumerate(self._linker_sections):
+            if i == 0 and sec.name != "code":
+                print("The first linker section sould be called code.")
+                ret = False
+            elif i == 1 and sec.name != "data":
+                print("The second linker section sould be called data.")
+                ret = False
+
+            if old_sec is not None:
+                if sec.start < old_sec.end:
+                    print(f"Section {sec.name} and {old_sec.name} overlap.")
+
+            start = sec.start
+            found_start = False
+            found_end = False
+            for b in self._ram_banks:
+                if found_start:
+                    if b.start_address() > start:
+                        print(f"Section {sec.name} has a memory hole starting at {start:#08X}")
+                        ret = False
+                        found_end = True
+                        break
+                    else:
+                        start = b.end_address()
+
+                if sec.start >= b.start_address() and sec.start < b.end_address():
+                    found_start = True
+                    start = b.end_address()
+                
+                if sec.end <= b.end_address() and sec.end > b.start_address():
+                    found_end = True
+                    break
+
+            if not found_start:
+                print(f"Section {sec.name} does not start in any ram bank.")
+                ret = False
+
+            if not found_end:
+                ret = False
+                print(f"Section {sec.name} does not end in any ram bank.")
+
+            old_sec = sec
+        
+        return ret
+    
+
+
+    def ram_size_address(self) -> int:
+        """
+        :return: the size of the addressable ram memory.
+        :rtype: int
+        """
+        size = 0
+        for bank in self._ram_banks:
+            size += bank.size()
+        return size
+    
+
+
+    def ram_il_size(self) -> int:
+        """
+        :return: the memory size of the interleaved sizes.
+        :rtype: int
+        """
+        size = 0
+        for i in self._ram_banks_il_idx:
+            size += self._ram_banks[i].size()
+        return size
+    
+
+
+    def iter_ram_banks(self) -> Iterable[Bank]:
+        """
+        :return: an iterator over all banks.
+        :rtype: Iterable[Bank]
+        """
+        return iter(self._ram_banks)
+
+
+
+    def iter_cont_ram_banks(self) -> Iterable[Bank]:
+        """
+        :return: an iterator over all continuous banks.
+        :rtype: Iterable[Bank]
+        """
+        m = map((lambda b: None if b[0] in self._ram_banks_il_idx else b[1]), enumerate(self._ram_banks))
+        return filter(None, m)
+    
+
+
+    def iter_il_ram_banks(self) -> Iterable[Bank]:
+        """
+        :return: an iterator over all interleaved banks.
+        :rtype: Iterable[Bank]
+        """
+        m = map((lambda b: None if not b[0] in self._ram_banks_il_idx else b[1]), enumerate(self._ram_banks))
+        return filter(None, m)
+
+
+
+    def has_il_ram(self) -> bool:
+        """
+        :return: `True` if the system has interleaved ram.
+        :rtype: bool
+        """
+        return self._il_banks_present
+    
+    
+
+    def iter_il_groups(self) -> Iterable[ILRamGroup]:
+        """
+        :return: an iterator over the interleaved ram bank groups.
+        :rtype: Iterable[ILRamGroup]
+        """
+        return iter(self._ram_banks_il_groups)
+    
+
+
+    def iter_linker_sections(self) -> Iterable[LinkerSection]:
+        """
+        :return: an iterator over the linker sections
+        :rtype: Iterable[LinkerSection]
+        """
+        return iter(self._linker_sections)
+    
+
+
+    def iter_bank_numwords(self) -> Generator[int, None, None]:
+        """
+        Iterates over the size of the ram banks in number of words.
+
+        :return: Generator over the sizes
+        :rtype: Generator[int, None, None]
+        """
+        sizes = set()
+        for b in self._ram_banks:
+            if b.size() not in sizes:
+                sizes.add(b.size())
+                yield b.size() // 4
+    
+    def build(self):
+        """
+        Makes the system ready to be used.
+
+        - Aplies the overrides for the interleaved memory as the normal memory needs to be configured first.
+        - Sorts the linker sections by starting address.
+        - Inferes the missing linker section ends with the start of the next section if present. If not it uses the end of the last memory bank.
+        """
+        if self._ignore_ram_interleaved:
+            sec_name = ""
+            if self.ram_numbanks() > 1:
+                sec_name = "data_interleaved"
+            self.add_ram_banks_il(self._override_numbanks_il, 32, sec_name, ignore_ignore=True) #Add automatically a section for compatibility purposes.
+
+
+        self._linker_sections.sort(key=lambda l: l.start)
+
+        old_sec: Optional[LinkerSection] = None
+        for sec in self._linker_sections:
+            if old_sec is not None:
+                old_sec.end = sec.start
+            
+            if sec.end is None:
+                old_sec = sec
+            else:
+                old_sec = None
+        if old_sec is not None:
+            if len(self._ram_banks) == 0:
+                raise RuntimeError("There is no ram bank to infere the end of a section")
+            old_sec.end = self._ram_banks[-1].end_address()
+        
\ No newline at end of file
diff --git a/hw/vendor/eslepfl_x_heep.lock.hjson b/hw/vendor/eslepfl_x_heep.lock.hjson
index e6880390..ee180557 100644
--- a/hw/vendor/eslepfl_x_heep.lock.hjson
+++ b/hw/vendor/eslepfl_x_heep.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/Luigi2898/x-heep.git
-    rev: 849539ddf996926f9b679837f3bc84c0799287bb
+    rev: 798fd6ffc9193b613f5a85f54a496bfcc149a07d
   }
 }
diff --git a/hw/vendor/eslepfl_x_heep.vendor.hjson b/hw/vendor/eslepfl_x_heep.vendor.hjson
index e60b27ec..5457cda2 100644
--- a/hw/vendor/eslepfl_x_heep.vendor.hjson
+++ b/hw/vendor/eslepfl_x_heep.vendor.hjson
@@ -8,7 +8,7 @@
 
   upstream: {
     url: "https://github.com/Luigi2898/x-heep.git",
-    rev: "849539ddf996926f9b679837f3bc84c0799287bb",
+    rev: "798fd6ffc9193b613f5a85f54a496bfcc149a07d",
   },
 
   patch_dir: "patches/esl_epfl_x_heep",

From 3bc56a8787be6a46aecbaac21f57d2166a2c6f2f Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Tue, 1 Oct 2024 13:08:46 +0200
Subject: [PATCH 17/27] fix makefile and .core files

---
 Makefile       | 2 --
 heepsilon.core | 2 --
 2 files changed, 4 deletions(-)

diff --git a/Makefile b/Makefile
index ef581b6d..5be58865 100644
--- a/Makefile
+++ b/Makefile
@@ -36,8 +36,6 @@ heepsilon-gen:
 # This is needed to be done after the X-HEEP mcu-gen because the test-bench to be used is the one from heepsilon, not the one from X-HEEP.
 mcu-gen: heepsilon-gen
 	$(MAKE) -f $(XHEEP_MAKE) EXTERNAL_DOMAINS=${EXTERNAL_DOMAINS} MEMORY_BANKS=${MEMORY_BANKS} $(MAKECMDGOALS)
-	cd hw/vendor/esl_epfl_x_heep &&\
-	$(PYTHON) util/mcu_gen.py --cfg mcu_cfg.hjson --pads_cfg pad_cfg.hjson  --outdir ../../../tb/ --memorybanks $(MEMORY_BANKS) --tpl-sv ../../../tb/tb_util.svh.tpl
 
 ## Builds (synthesis and implementation) the bitstream for the FPGA version using Vivado
 ## @param FPGA_BOARD=nexys-a7-100t,pynq-z2
diff --git a/heepsilon.core b/heepsilon.core
index 4970340e..bdd22079 100644
--- a/heepsilon.core
+++ b/heepsilon.core
@@ -118,12 +118,10 @@ filesets:
 
   ip-fpga-pynq-z2:
     files:
-    - hw/fpga/scripts/pynq-z2/set_board.tcl: { file_type: tclSource }
     - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
 
   ip-fpga-zcu104:
     files:
-    - hw/fpga/scripts/zcu104/set_board.tcl: { file_type: tclSource }
     - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
 
   fpga-arm-emulation:

From 62f41adac5741a9b68f0e0983ec73ad445480ab4 Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Tue, 1 Oct 2024 14:06:32 +0200
Subject: [PATCH 18/27] Fixing .core for heepsilon

---
 heepsilon.core | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/heepsilon.core b/heepsilon.core
index bdd22079..164cbe4d 100644
--- a/heepsilon.core
+++ b/heepsilon.core
@@ -13,6 +13,31 @@ filesets:
     - x-heep::packages
     - openhwgroup.org:systems:core-v-mini-mcu
     - eslepfl::cgra
+    - openhwgroup.org:ip:cv32e40p
+    - openhwgroup.org:ip:cv32e40x
+    - openhwgroup:cve2:cve2_top
+    - esl_epfl:ip:cv32e40px
+    - pulp-platform.org:ip:gpio
+    - pulp-platform.org::common_cells
+    - pulp-platform.org::cluster_interconnect
+    - pulp-platform.org::riscv_dbg
+    - pulp-platform.org::register_interface
+    - openhwgroup.org:ip:soc_ctrl
+    - lowrisc:ip:uart:0.1
+    - lowrisc:ip:rv_plic_example:0.1
+    - lowrisc:ip:rv_timer:0.1
+    - lowrisc:ip:spi_host:1.0
+    - lowrisc:ip:i2c:0.1
+    - yosyshq:picorv32_spimemio:0-r1
+    - x-heep:obi_spimemio:0.1.0
+    - x-heep:ip:boot_rom
+    - x-heep:ip:dma
+    - x-heep:ip:dma_subsystem
+    - x-heep:ip:i2s
+    - x-heep:ip:power_manager
+    - x-heep:ip:fast_intr_ctrl
+    - x-heep:ip:obi_fifo
+    - x-heep:ip:pdm2pcm
     files:
     - hw/rtl/heepsilon_pkg.sv
     - hw/rtl/heepsilon_top.sv
@@ -97,6 +122,8 @@ filesets:
     file_type: systemVerilogSource
 
   rtl-fpga:
+    depend:
+    - openhwgroup.org:systems:core-v-mini-mcu-fpga
     files:
     - hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
     - hw/fpga/sram_wrapper.sv
@@ -285,6 +312,7 @@ targets:
     - x_heep_system
     - files_rtl_generic # Already added by default?
     - rtl-fpga
+    - ip-fpga-pynq-z2
     - ip-fpga
     - xdc-fpga-pynq-z2
     - ext_bus
@@ -309,9 +337,14 @@ targets:
     - ext_bus
     parameters:
     - COREV_PULP=0
+    - FPU
+    - X_EXT
     - SYNTHESIS=true
+    - REMOVE_OBI_FIFO
     - FPGA_ZCU104=true
     tools:
       vivado:
         part: xczu7ev-ffvc1156-2-e
+        board_part: xilinx.com:zcu104:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_zcu104_board_files]
     toplevel: [xilinx_heepsilon_wrapper]
\ No newline at end of file

From 291475f93c7c505d5c03c4f0db9d7d865949a3b8 Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Tue, 1 Oct 2024 14:09:32 +0200
Subject: [PATCH 19/27] Fixing .core for heepsilon: adding parameters

---
 heepsilon.core | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/heepsilon.core b/heepsilon.core
index 164cbe4d..5731ab91 100644
--- a/heepsilon.core
+++ b/heepsilon.core
@@ -181,11 +181,33 @@ parameters:
   COREV_PULP:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables COREV_PULP custom RISC-V extension on the CV32E40P core. Admitted values: 1|0.
+    default: 0
+  FPU:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables RV32F RISC-V extension on the CV32E40P core. Admitted values: 1|0.
     default: 0
   JTAG_DPI:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables testbench JTAG DIPs. Admitted values: 1|0.
+    default: 0
+  X_EXT:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables CORE-V-XIF interface for the CV32E40X and CV32E40PX cores. Admitted values: 1|0.
     default: 0
+  USE_EXTERNAL_DEVICE_EXAMPLE:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables testbench modules compilation. Admitted values: 1|0.
+    default: 1
   USE_UPF:
     datatype: bool
     paramtype: vlogdefine

From c035b4f247efea37d45e650e068a27aca6f9656f Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Tue, 1 Oct 2024 14:11:36 +0200
Subject: [PATCH 20/27] Fixing .core for heepsilon: adding parameters v2

---
 heepsilon.core | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/heepsilon.core b/heepsilon.core
index 5731ab91..327af2f8 100644
--- a/heepsilon.core
+++ b/heepsilon.core
@@ -212,6 +212,11 @@ parameters:
     datatype: bool
     paramtype: vlogdefine
     default: false
+  REMOVE_OBI_FIFO:
+    datatype: bool
+    paramtype: vlogdefine
+    description: |
+      Remove the FIFO between the BUS and the peripherals subsystems
   SYNTHESIS:
     datatype: bool
     paramtype: vlogdefine

From 4780044ad2cdd3ad0ede9f90830d4ea30d480aa1 Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Thu, 3 Oct 2024 11:10:09 +0200
Subject: [PATCH 21/27] Update .core and xheep vendor

---
 heepsilon.core                        | 55 ---------------------------
 hw/vendor/eslepfl_x_heep.vendor.hjson |  2 +-
 2 files changed, 1 insertion(+), 56 deletions(-)

diff --git a/heepsilon.core b/heepsilon.core
index 327af2f8..b19142a3 100644
--- a/heepsilon.core
+++ b/heepsilon.core
@@ -13,31 +13,6 @@ filesets:
     - x-heep::packages
     - openhwgroup.org:systems:core-v-mini-mcu
     - eslepfl::cgra
-    - openhwgroup.org:ip:cv32e40p
-    - openhwgroup.org:ip:cv32e40x
-    - openhwgroup:cve2:cve2_top
-    - esl_epfl:ip:cv32e40px
-    - pulp-platform.org:ip:gpio
-    - pulp-platform.org::common_cells
-    - pulp-platform.org::cluster_interconnect
-    - pulp-platform.org::riscv_dbg
-    - pulp-platform.org::register_interface
-    - openhwgroup.org:ip:soc_ctrl
-    - lowrisc:ip:uart:0.1
-    - lowrisc:ip:rv_plic_example:0.1
-    - lowrisc:ip:rv_timer:0.1
-    - lowrisc:ip:spi_host:1.0
-    - lowrisc:ip:i2c:0.1
-    - yosyshq:picorv32_spimemio:0-r1
-    - x-heep:obi_spimemio:0.1.0
-    - x-heep:ip:boot_rom
-    - x-heep:ip:dma
-    - x-heep:ip:dma_subsystem
-    - x-heep:ip:i2s
-    - x-heep:ip:power_manager
-    - x-heep:ip:fast_intr_ctrl
-    - x-heep:ip:obi_fifo
-    - x-heep:ip:pdm2pcm
     files:
     - hw/rtl/heepsilon_pkg.sv
     - hw/rtl/heepsilon_top.sv
@@ -181,42 +156,15 @@ parameters:
   COREV_PULP:
     datatype: int
     paramtype: vlogparam
-    description: |
-      Enables COREV_PULP custom RISC-V extension on the CV32E40P core. Admitted values: 1|0.
-    default: 0
-  FPU:
-    datatype: int
-    paramtype: vlogparam
-    description: |
-      Enables RV32F RISC-V extension on the CV32E40P core. Admitted values: 1|0.
     default: 0
   JTAG_DPI:
     datatype: int
     paramtype: vlogparam
-    description: |
-      Enables testbench JTAG DIPs. Admitted values: 1|0.
-    default: 0
-  X_EXT:
-    datatype: int
-    paramtype: vlogparam
-    description: |
-      Enables CORE-V-XIF interface for the CV32E40X and CV32E40PX cores. Admitted values: 1|0.
     default: 0
-  USE_EXTERNAL_DEVICE_EXAMPLE:
-    datatype: int
-    paramtype: vlogparam
-    description: |
-      Enables testbench modules compilation. Admitted values: 1|0.
-    default: 1
   USE_UPF:
     datatype: bool
     paramtype: vlogdefine
     default: false
-  REMOVE_OBI_FIFO:
-    datatype: bool
-    paramtype: vlogdefine
-    description: |
-      Remove the FIFO between the BUS and the peripherals subsystems
   SYNTHESIS:
     datatype: bool
     paramtype: vlogdefine
@@ -364,10 +312,7 @@ targets:
     - ext_bus
     parameters:
     - COREV_PULP=0
-    - FPU
-    - X_EXT
     - SYNTHESIS=true
-    - REMOVE_OBI_FIFO
     - FPGA_ZCU104=true
     tools:
       vivado:
diff --git a/hw/vendor/eslepfl_x_heep.vendor.hjson b/hw/vendor/eslepfl_x_heep.vendor.hjson
index 5457cda2..655e0a58 100644
--- a/hw/vendor/eslepfl_x_heep.vendor.hjson
+++ b/hw/vendor/eslepfl_x_heep.vendor.hjson
@@ -8,7 +8,7 @@
 
   upstream: {
     url: "https://github.com/Luigi2898/x-heep.git",
-    rev: "798fd6ffc9193b613f5a85f54a496bfcc149a07d",
+    rev: "83f1563fd4894787167b27099006c8b1b042d3d1",
   },
 
   patch_dir: "patches/esl_epfl_x_heep",

From a28285bd9a0e1b50a7beb305fd2a26dd607d1f0b Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Thu, 3 Oct 2024 11:17:52 +0200
Subject: [PATCH 22/27] Re-vendorizing x-heep to last commit

---
 hw/vendor/esl_epfl_x_heep/Makefile            |    4 +-
 hw/vendor/esl_epfl_x_heep/configs/ci.hjson    |    4 +-
 .../configs/example_interleaved.hjson         |    4 +-
 .../esl_epfl_x_heep/configs/general.hjson     |    4 +-
 .../esl_epfl_x_heep/configs/testall.hjson     |    4 +-
 .../docs/source/How_to/eXtendingHEEP.md       |   10 +-
 .../docs/source/Peripherals/DMA.md            | 2293 +++++++++++++----
 .../docs/source/Verification/VerifHEEP.md     |  186 ++
 .../docs/source/images/dma_structure.png      |  Bin 0 -> 175192 bytes
 .../ao_peripheral_subsystem.sv                |  214 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv     |   92 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl |   78 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.vlt    |    2 +
 .../include/core_v_mini_mcu_pkg.sv.tpl        |   17 +-
 .../hw/core-v-mini-mcu/system_bus.sv.tpl      |   65 +-
 .../hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv |   16 +-
 .../esl_epfl_x_heep/hw/ip/dma/data/dma.hjson  |   17 +-
 hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core  |    4 +
 hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.vlt   |    5 +
 .../esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv      | 1404 +++-------
 .../hw/ip/dma/rtl/dma_obiread_addr_fsm.sv     |  168 ++
 .../hw/ip/dma/rtl/dma_obiread_fsm.sv          |  313 +++
 .../hw/ip/dma/rtl/dma_obiwrite_fsm.sv         |  358 +++
 .../hw/ip/dma/rtl/dma_padding_fsm.sv          |  339 +++
 .../hw/ip/dma/rtl/dma_reg_pkg.sv              |   67 +-
 .../hw/ip/dma/rtl/dma_reg_top.sv              |   10 +-
 .../hw/ip/dma_subsystem/dma_subsystem.core    |    1 +
 .../hw/ip/dma_subsystem/rtl/dma_NtoM_xbar.sv  |   71 +
 .../hw/ip/dma_subsystem/rtl/dma_subsystem.sv  |  205 +-
 .../data/power_manager.hjson.tpl              |   11 +
 .../power_manager/data/power_manager.sv.tpl   |    5 +
 .../hw/ip/power_manager/power_manager_gen.sh  |    0
 .../im2col_spc/data/im2col_spc.hjson          |  255 ++
 .../hw/ip_examples/im2col_spc/im2col_spc.core |   28 +
 .../hw/ip_examples/im2col_spc/im2col_spc.vlt  |   16 +
 .../ip_examples/im2col_spc/im2col_spc_gen.sh  |    8 +
 .../ip_examples/im2col_spc/rtl/dma_if_pkg.sv  |   26 +
 .../ip_examples/im2col_spc/rtl/im2col_spc.sv  |  623 +++++
 .../im2col_spc/rtl/im2col_spc_param_fsm.sv    |  551 ++++
 .../im2col_spc/rtl/im2col_spc_reg_pkg.sv      |  227 ++
 .../im2col_spc/rtl/im2col_spc_reg_top.sv      | 1182 +++++++++
 .../rtl/im2col_spc_regintfc_controller.sv     |   92 +
 .../hw/ip_examples/im2col_spc/rtl/pipe_reg.sv |   32 +
 .../hw/system/x_heep_system.sv.tpl            |   40 +-
 .../hw/vendor/esl_epfl_cv32e40px.lock.hjson   |    2 +-
 .../hw/vendor/esl_epfl_cv32e40px.vendor.hjson |    2 +-
 .../hw/vendor/esl_epfl_cv32e40px/README.md    |   14 +-
 .../rtl/cv32e40px_controller.sv               |   25 +-
 .../rtl/cv32e40px_id_stage.sv                 |   23 +-
 .../rtl/cv32e40px_x_disp.sv                   |   17 +-
 .../pulp_platform_register_interface.core     |    1 +
 hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson       |    2 +
 .../esl_epfl_x_heep/mcu_cfg_minimal.hjson     |    2 +
 hw/vendor/esl_epfl_x_heep/pad_cfg.hjson       |    8 +-
 .../examples/im2col_spc_verification.py       |  317 +++
 .../scripts/verification/examples/plotter.py  |  123 +
 .../scripts/verification/verifheep.py         |  498 ++++
 .../gen_stimuly.py                            |    5 +-
 .../example_data_processing_from_flash/main.c |    6 +
 .../matrices.h                                |  292 +--
 .../sw/applications/example_dma/main.c        |   40 +-
 .../sw/applications/example_dma_2d/main.c     |  213 +-
 .../applications/example_dma_2d/test_data.h   |    7 +-
 .../applications/example_dma_external/main.c  |   11 +-
 .../example_dma_multichannel/main.c           |   53 +-
 .../sw/applications/example_fft/data.h        |   80 +
 .../sw/applications/example_fft/datagen.py    |  204 ++
 .../sw/applications/example_fft/fft.h         |  331 +++
 .../sw/applications/example_fft/main.c        |  112 +
 .../sw/applications/example_i2s/main.c        |    6 +-
 .../sw/applications/example_iffifo/main.c     |   12 +-
 .../example_im2col/im2colGolden.c             |   72 -
 .../example_im2col/im2colGolden.h             |   31 -
 .../example_im2col/im2col_golden.c            |   20 +
 .../example_im2col/im2col_golden.h            |   14 +
 .../example_im2col/im2col_input.c             |   16 +
 .../example_im2col/im2col_input.h             |   27 +
 .../applications/example_im2col/im2col_lib.c  |  548 +++-
 .../applications/example_im2col/im2col_lib.h  |   78 +-
 .../sw/applications/example_im2col/main.c     |   94 +-
 .../applications/example_power_manager/main.c |   24 +-
 .../example_tensor_format_conv/main.c         |  288 +++
 .../esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c |   38 +-
 .../sw/device/bsp/w25q/w25q128jw.h            |    2 +-
 .../esl_epfl_x_heep/sw/device/lib/base/base.h |   16 +-
 .../sw/device/lib/base/bitfield.c             |   30 -
 .../sw/device/lib/base/bitfield.h             |   26 +-
 .../sw/device/lib/base/memory.c               |    3 -
 .../sw/device/lib/base/memory.h               |    4 +-
 .../esl_epfl_x_heep/sw/device/lib/base/mmio.c |   39 -
 .../esl_epfl_x_heep/sw/device/lib/base/mmio.h |   30 +-
 .../sw/device/lib/crt/crt0.S.tpl              |  306 +--
 .../sw/device/lib/drivers/dma/dma.c           |  113 +-
 .../sw/device/lib/drivers/dma/dma.h           |   14 +-
 .../sw/device/lib/drivers/dma/dma_regs.h      |    7 +-
 .../sw/device/lib/drivers/im2col_spc/im2col.c |  234 ++
 .../sw/device/lib/drivers/im2col_spc/im2col.h |   60 +
 .../lib/drivers/im2col_spc/im2col_spc_regs.h  |  188 ++
 .../device/lib/runtime/core_v_mini_mcu.h.tpl  |    1 +
 .../sw/device/lib/runtime/hart.h              |    2 +-
 .../sw/device/lib/sdk/dma/dma_sdk.c           |    2 +-
 hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv       |   41 +-
 hw/vendor/esl_epfl_x_heep/tb/tb.vlt           |    2 +
 hw/vendor/esl_epfl_x_heep/tb/testharness.sv   |  117 +-
 .../esl_epfl_x_heep/tb/testharness_pkg.sv     |   13 +-
 hw/vendor/esl_epfl_x_heep/util/mcu_gen.py     |  114 +-
 hw/vendor/esl_epfl_x_heep/util/test_all.sh    |    2 +-
 .../esl_epfl_x_heep/x-heep-tb-utils.core      |    2 +
 hw/vendor/eslepfl_x_heep.lock.hjson           |    2 +-
 109 files changed, 11083 insertions(+), 2994 deletions(-)
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/Verification/VerifHEEP.md
 create mode 100644 hw/vendor/esl_epfl_x_heep/docs/source/images/dma_structure.png
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_addr_fsm.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_fsm.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiwrite_fsm.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_padding_fsm.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_NtoM_xbar.sv
 mode change 100644 => 100755 hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/power_manager_gen.sh
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/data/im2col_spc.hjson
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.core
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.vlt
 create mode 100755 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc_gen.sh
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/dma_if_pkg.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_param_fsm.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_pkg.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_top.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_regintfc_controller.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/pipe_reg.sv
 create mode 100644 hw/vendor/esl_epfl_x_heep/scripts/verification/examples/im2col_spc_verification.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/scripts/verification/examples/plotter.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/scripts/verification/verifheep.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/data.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/datagen.py
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/fft.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/applications/example_tensor_format_conv/main.c
 delete mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.c
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.h
 create mode 100644 hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col_spc_regs.h

diff --git a/hw/vendor/esl_epfl_x_heep/Makefile b/hw/vendor/esl_epfl_x_heep/Makefile
index ca1a02b0..f65c4640 100644
--- a/hw/vendor/esl_epfl_x_heep/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/Makefile
@@ -98,7 +98,7 @@ environment.yml: python-requirements.txt
 ## @section Installation
 
 ## Generates mcu files core-v-mini-mcu files and build the design with fusesoc
-## @param CPU=[cv32e20(default),cv32e40p,cv32e40x]
+## @param CPU=[cv32e20(default),cv32e40p,cv32e40x,cv32e40px]
 ## @param BUS=[onetoM(default),NtoM]
 ## @param MEMORY_BANKS=[2(default) to (16 - MEMORY_BANKS_IL)]
 ## @param MEMORY_BANKS_IL=[0(default),2,4,8]
@@ -193,7 +193,7 @@ questasim-sim-opt-upf: questasim-sim
 	$(MAKE) -C build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-modelsim opt-upf
 
 ## VCS simulation
-## @param CPU=cv32e20(default),cv32e40p,cv32e40x
+## @param CPU=cv32e20(default),cv32e40p,cv32e40x,cv32e40px
 ## @param BUS=onetoM(default),NtoM
 vcs-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
diff --git a/hw/vendor/esl_epfl_x_heep/configs/ci.hjson b/hw/vendor/esl_epfl_x_heep/configs/ci.hjson
index 51a278b7..011fe3e8 100644
--- a/hw/vendor/esl_epfl_x_heep/configs/ci.hjson
+++ b/hw/vendor/esl_epfl_x_heep/configs/ci.hjson
@@ -13,11 +13,11 @@
             name: code
             start: 0
             #minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson b/hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson
index aac0801e..35d380c6 100644
--- a/hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson
+++ b/hw/vendor/esl_epfl_x_heep/configs/example_interleaved.hjson
@@ -30,11 +30,11 @@
             name: code
             start: 0
             // minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/configs/general.hjson b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
index f7040640..0afb35ef 100644
--- a/hw/vendor/esl_epfl_x_heep/configs/general.hjson
+++ b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
@@ -14,11 +14,11 @@
             name: code
             start: 0
             #minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/configs/testall.hjson b/hw/vendor/esl_epfl_x_heep/configs/testall.hjson
index 36828dc8..3e4bad9a 100644
--- a/hw/vendor/esl_epfl_x_heep/configs/testall.hjson
+++ b/hw/vendor/esl_epfl_x_heep/configs/testall.hjson
@@ -13,11 +13,11 @@
             name: code
             start: 0
             #minimum size for freeRTOS and clang
-            size: 0x00000D800
+            size: 0x00000E800
         },
         {
             name: data
-            start: 0x00000D800
+            start: 0x00000E800
         }
     ]
 }
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md
index 59c1b1e9..41e9bed7 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/How_to/eXtendingHEEP.md
@@ -2,14 +2,14 @@
 
 `X-HEEP` is meant to be extended with your own custom IPs. `X-HEEP` itself posseses a hardware-software framework capable of working standalone. If you want to extend it, you will need to merge your hardware and software with `X-HEEP`'s.
 
-For this purpose we support the [CORE-V-XIF](https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/intro.html) interface with the [cv32e40x](https://github.com/openhwgroup/cv32e40x) RISCV-CPU, and we expose master and slave ports to/from the bus.
+For this purpose we support the [CV-X-IF](https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/intro.html) interface with the [cv32e40x](https://github.com/openhwgroup/cv32e40x) or [cv32e40px](https://github.com/esl-epfl/cv32e40px) RISCV-CPU, and we expose master and slave ports to/from the bus.
 
-> `X-HEEP` currently uses the revision [`0.9.0`](https://github.com/openhwgroup/cv32e40x/commit/f17028f2369373d9443e4636f2826218e8d54e0f) of OpenHW Groups's `cv32e40x` core to implement the `CORE-V-XIF`. It is recommended to use the same revision in peripheral IPs to prevent conflicts during RTL compilation.
+> We recommend using the `cv32e40px` for pairing with your CV-X-IF compliant coprocessor. If you choose to use the `cv32e40x`, `X-HEEP` currently uses the revision [`0.9.0`](https://github.com/openhwgroup/cv32e40x/commit/f17028f2369373d9443e4636f2826218e8d54e0f). It is recommended to use the same revision in peripheral IPs to prevent conflicts during RTL compilation.
 
 Here you can find a list of `X-HEEP` based open-source examples. If you want to include your project in this list, please open an issue with a link to your repository.
 
 * [CGRA-X-HEEP](https://github.com/esl-epfl/cgra_x_heep): A CGRA loosely coupled with X-HEEP.
-* [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40x.
+* [F-HEEP](https://github.com/davidmallasen/F-HEEP): System integrating [fpu_ss](https://github.com/pulp-platform/fpu_ss) into X-HEEP via the eXtension interface and cv32e40px.
 * [KALIPSO](https://github.com/vlsi-lab/ntt_intt_kyber) and [KRONOS](https://github.com/vlsi-lab/keccak_integration/tree/keccak_xheep): Loosely-coupled, post-quantum cryptography accelerators for NTT/INTT and Keccak hash function integrated into X-HEEP.
 
 
@@ -98,7 +98,7 @@ To achieve this:
 
 * Create a new top-level repository (`BASE`) and vendorize (or add as git submodules) both your `CORE-V-XIF/OBI` compliant coprocessor/accelerator and `X-HEEP`.
 * Copy the `x-heep/hw/system/x_heep_system.sv` as your new top-level module. Then modify it as needed to include your co-processor and connect it to the `core_v_mini_mcu` with the `XIF`. The `XIF` SystemVerilog interface must be instantiated in the top-level module, where `X-HEEP` and your co-processor are connected. See the `X-HEEP` [testbench](./../../../tb/testharness.sv) as an example.
-* Before building software remember to run `make mcu-gen CPU=cv32e40x`.
+* Before building software remember to run `make mcu-gen CPU=cv32e40px`.
 
 To add this new top-level module to the simulation/synthesis flow you can extend the [FuseSoC](https://fusesoc.readthedocs.io/en/stable/user/index.html) support of `X-HEEP`.
 
@@ -328,7 +328,7 @@ include $(XHEEP_MAKE)
 * The `verilator-sim` rule will override the `X-HEEP` Makefile's one.
 * Any other target will be passed straight to `X-HEEP`'s Makefile. For example
 ```sh
-make mcu-gen CPU=cv32e40x
+make mcu-gen CPU=cv32e40px
 ```
 </details>
 
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md
index 6b57642f..a3b4d890 100644
--- a/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/Peripherals/DMA.md
@@ -1,589 +1,1914 @@
 
 # DMA
+
+## Introduction
+
 The **Direct Memory Access (DMA)** peripheral allows data transfers with reduced CPU interaction.
+
 It can perform *transactions* of data between peripherals and memory, or memory-to-memory (as a `memcpy` would).
+
 The CPU is required to configure the transaction, but once launched it is free to go to sleep, process the incoming data or do anything else.
-  
+
+This unit is capable of performing complex tasks that can significantly impact on the performance and power consumption of memory-intense applications. 
+It can be configured to perform *1D* or *2D* transactions and it can apply **zero padding** and perform **transpositions** on-the-fly, reducing the overhead of matrix operations.
+
 The DMA **Hardware Abstraction Layer (HAL)** facilitates the configuration of transactions from the users application. Furthermore, it adds an additional layer of safety checks to reduce the risk of faulty memory accesses, data override or infinite loops.
+
+
+The DMA **SDK**, on the other hand, offers user-friendly functions for essential *memcpy* and *fill* operations. It does not include the validation capabilities of the HAL nor the 2D and padding features, prioritizing performance at the cost of an increased risk of inconsistencies.
+
+
+<br>
+
+## Structural description
+
+![DMA subsystem structure](https://github.com/esl-epfl/x-heep/docs/images/dma_structure.png)
+
+<p  align="center">Figure 1: Structure of the DMA subsystem in X-Heep </p>
+
+#### DMA channels layout
+
+The DMA subsystem is composed of a parametrized number of control units called **channels**. 
+Each channel can be configured, by the CPU or by an external controller, to perform a *transaction*, independently of the state of other channels.
+
+N-channels are connected to a N-to-M bus that exposes M-master ports on the system bus. **Multiple channels** can thus perform multiple transactions in parallel, a feature that enables memory-intense applications to greatly increase their throuhput.
+
+There are several ways to connect N-channels to the system bus through M-master ports.
+
+e.g.
+Let's consider a DMA subsystem with N = 4 channels and M = 2 master ports.
+
+There are two possible solutions: 
+- CH0, CH1 connected to port 0 & CH2, CH3 connected to port 1
+- CH0, CH1, CH2 connected to port 0 & CH3 connected to port 1
+
+In order to specify one among these configurations, the user has to set the `num_channels_per_master_port` parameter in `mcu_cfg.hjson`, which defines the _maximum_ channels per master port ratio.
+
+The first configuration of the previous example has 2 channels per master port, so a channels per master port ratio of 2.
+On the other hand, the second solution has a ratio of 3: the first 3 channels are connected to port 0, while the remaining channel is connected to the remaining port 1.
+
+While the 1st solution is a general purpose, balanced configuration, the 2nd solution might be better suited for applications that need a low latency channel for high priority tasks.
+
+This mechanism guarantees **maximum flexibility**, enabling the user to adapt the DMA subsystem to its requirements, both in terms of area and performance.
+<br>
+
+#### Interrupts
+
+If enabled, a transaction interrupt is raised every time a DMA transaction is completed. However, due to architectural limitations, there is only a single transaction done signal for the entire DMA subsystem.
+
+To allow users to identify which channel raised the transaction interrupt, an **interrupt flag register** system has been developed. Here's how it works: when a DMA channel completes its transaction and the interrupt enable register is correctly set, the transaction **IFR** (Interrupt Flag Register) is set. This register is designed to be cleared automatically once read, which is convenient as it eliminates the need for an additional register write.
+
+The transaction interrupt handler leverages this mechanism to identify the channel that raised the interrupt. As soon as an IFR is read as high, it triggers the actual handler, which can be redefined by the user. An example of this mechanism at work is explained in [Example 7](#7-multichannel-mem2mem-transaction-focus-on-the-irq-handler).
+
+It is possible that a channel could raise an interrupt while the CPU is processing a previous interrupt from another channel. This is not an issue because the IFR will remain set until the CPU reads its content. However, this situation could introduce additional delay to the execution of the application.
+
+For this reason, the handler implemented by the user should be as brief as possible.
+
+#### Data FIFOs configuration
+
+Each DMA channel uses FIFOs to buffer the data to be read and written, which is crucial for mitigating the combined delays from the system bus and the Always On Peripheral Bus (**AOPB**). 
+
+The **size of the FIFOs is parametric** and is, by default, the same across all channels.
+
+Some applications can benefit from larger FIFOs because it allows for more values to be buffered in situations where the bus is heavily utilized or the target peripheral, such as the SPI, is too slow.
+On the other hand, other applications might not require such large FIFOs, so area can be saved by reducing its size.
+A hybrid system, where some channels have large FIFO sizes and others have smaller ones, could benefit both these types of applications.
+
+It is possible to specify the size of each DMA channel FIFOs in `dma_subsystem.sv`. 
+These are the steps to follow to take advantage this feature:
+
+- Uncomment `//'define EN_SET_FIFO_CH_SIZE;` to enable the mechanism
+- Adjust the parameters *LARGE_FIFO_CH_SIZE*, *MEDIUM_FIFO_CH_SIZE* and *SMALL_FIFO_CH_SIZE*. They define the size of a large, medium and small FIFOs.
+- Modify the parameter `typedef enum {L, M, S} fifo_ch_size_t;` to assign individual sizes to the FIFOs. The number of elements must reflect the number of DMA channels.
+
+e.g.
+
+Let's imagine to configure X-Heep to have 4 channels. These are the definitions of the sizes:
+- *LARGE_FIFO_CH_SIZE*: 10
+- *MEDIUM_FIFO_CH_SIZE*: 4
+- *SMALL_FIFO_CH_SIZE*: 2
+
+Now, let's set the first 2 channels, CH0 and CH1, to the large size, CH2 to small and CH3 to medium. This is the *fifo_ch_size_t* that would result from that configuration:
+
+<div style="text-align: center;">
+<pre style="display: inline-block; text-align: center;"><code>typedef enum {L, L, S, M} fifo_ch_size_t;</code></pre>
+</div>
+
+<br>
+
+#### Triggers
+
+In the case of memory-peripheral operations, it is common for the peripheral to have a reaction time that cannot match the system clock. For example, the SPI trasmits data with a period of circa 30 clock cycles. 
+
+This difference in response times creates the need for a **communication channel** between DMA subsystem and peripheral allowing the DMA operations to be suspended according to the peripheral state. These signals are called __triggers__. 
+
+They can be used both when the peripheral writes data using the DMA and when the DMA reads data from the peripheral.
+The DMA can be configured to respond to triggers by enabling the appropriate _slot_ via software, using the DMA HAL.
+
+<br>
+
+#### Tips for DMA-based accelerator developers
+
+The DMA subsystem has been developed with specific features to facilitate the creation of custom accelerators that can leverage it to improve memory-intense applications.
+
+- **Always-On Peripheral Bus** (AOPB): it exposes the register interface of the units in the Always-On subsystem to any Smart Peripheral Controller (SPC). 
+In the case of the DMA subsystem, this feature allows the developers to configure the DMA subsystem without any CPU action, reducing power consumption while at the same time increasing the performance and effectiveness of the accelerator. 
+Check out the _im2col SPC_ in the `\ip_examples` folder for a detailed example.
+<br>
+
+- **Triggers**: useful to synchronize the data streams to and from the accelerator.
+<br>
+
+- **Stop signal**: it can terminate a DMA transaction at any moment. It's particularly useful for accelerators that produce a large quantity of data, but with a variable trasfer size that cannot be known or computed beforehand. 
+A good example of such an accelerator is a level crossing subsampler, which writes sampled data only when they cross a specific threshold.
+<br>
+
+- **VerifHEEP**: this python library has been developed to test computational units and accelerators deployed on X-Heep. 
+It has been deployed succesfully to verify the _im2col SPC_ as it is expecially useful for data-driven accelerators.
+Additional documentation can be found in the **VerifHEEP documentation**, but in brief it includes methods to: 
+  - Generate random inputs and compute the corresponding golden results
+  - Launch synthesis & simulations on QuestaSim and Verilator
+  - Compile, program & launch applications on FPGA targets for a tenfold reduction in test and verification times
+  - Analyze the performance of the tests. 
+<br>
+
+### Registers description
+
+This section will describe every register of a DMA channel and their function.
+The complete addres of a DMA channel register is the following:
+
+<p style="text-align: center;"><code>DMA_START_ADDRESS + DMA_CH_SIZE * channel + REGISTER_OFFSET</code></p>
+
+The previous parameters, including the register offsets, can be found at `sw/device/lib/runtime/core_v_mini_mcu.h` and `sw/device/lib/drivers/dma/dma_regs.h`
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|-------------- 31 : 0 -------------|
+|-------------- PTR_IN -------------|</code></pre>
+</div>
+
+- **SRC_PTR_REG**
+  - _SW access_: rw
+  - _Description_: contains the pointer to the source, which could either be data stored in memory or a peripheral.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|-------------- 31 : 0 -------------|
+|------------- PTR_OUT -------------|</code></pre>
+</div>
+
+- **DST_PTR_REG**
+  - _SW access_: rw
+  - _Description_: contains the pointer to the destination, which could either be data stored in memory or a peripheral.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|-------------- 31 : 0 -------------|
+|------------- PTR_ADDR ------------|</code></pre>
+</div>
+
+- **ADDR_PTR_REG**
+  - _SW access_: rw
+  - _Description_: Used only with the [address mode](#transaction-modes) . It contains the pointer to the source, which in this case must data stored in memory.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 14 ----|---- 15 : 0 ----|
+|--- Reserved ----|----- SIZE -----|</code></pre>
+</div>
+
+- **SIZE_D1**
+  - _SW access_: rw
+  - _Description_: number of elements (not bytes) to be copied by the DMA channel along the first dimension, i.e. using the first counter. As soon as this register is written, the **transaction starts**.
+
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 14 ----|---- 15 : 0 ----|
+|--- Reserved ----|----- SIZE -----|</code></pre>
+</div>
+
+- **SIZE_D2**
+  - _SW access_: rw
+  - _Description_: number of elements (not bytes) to be copied by the DMA channel along the second dimension, i.e. using the second counter.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 2 ----|--- 1 ---|--- 0 ---|
+|--- Reserved ---|- WIN_DN |-- RDY --|</code></pre>
+</div>
+
+- **STATUS**
+  - _SW access_: ro
+  - _Description_: this register is used by the DMA to communicate the status of the transaction. READY is 0 when the DMA is busy performing the transaction, 1 otherwise.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 6 ----|---- 5 : 0 ----|
+|--- Reserved ---|----- INC -----|</code></pre>
+</div>
+
+- **SRC_PTR_INC_D1**
+  - _SW access_: rw
+  - _Description_: increment in bytes to apply to the source pointer for every copied element.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|--- 31 : 23 --|---- 22 : 0 ----|
+|-- Reserved --|------ INC -----|</code></pre>
+</div>
+
+- **SRC_PTR_INC_D2**
+  - _SW access_: rw
+  - _Description_: increment in bytes to apply to the source pointer every time a "row" is copied, in order to go to the new line. It's necessary only for 2D transactions. 
+  From an application perspective, this value has to be computed depending on the size of the input matrix and the 2D stride. Check the functional description paragraph for more information or [Example 4](#4-2d-mem2mem-transaction).
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 6 ----|---- 5 : 0 ----|
+|--- Reserved ---|----- INC -----|</code></pre>
+</div>
+
+- **DST_PTR_INC_D1**
+  - _SW access_: rw
+  - _Description_: increment in bytes to apply to the destination pointer for every copied element.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|--- 31 : 23 --|---- 22 : 0 ----|
+|-- Reserved --|------ INC -----|</code></pre>
+</div>
+
+- **DST_PTR_INC_D2**
+  - _SW access_: rw
+  - _Description_: increment in bytes to apply to the destination pointer every time a "row" is copied in order to go to the new line. It's necessary only for 2D transactions. 
+  From an application perspective, this value has to be computed depending on the size of the output matrix and the 2D stride. Check the functional description paragraph for more information.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 16 ----|---- 15 : 0 ----|
+|----- TX_TRG ----|---- RX_TRG ----|</code></pre>
+</div>
+
+- **SLOT**
+  - _SW access_: rw
+  - _Description_: identifies the triggers for which the DMA channel will stall in writing and/or reading operations.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 2 ----|---- 1 : 0 ----|
+|--- Reserved ---|---- DATA_T ---|</code></pre>
+</div>
+
+- **SRC_DATA_TYPE**
+  - _SW access_: rw
+  - _Description_: defines the source data type using this scheme:
+    - 0: _word_, i.e. 4 bytes
+    - 1: _half word_, i.e. 2 bytes
+    - 2 or 3: _byte_
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 2 ----|---- 1 : 0 ----|
+|--- Reserved ---|---- DATA_T ---|</code></pre>
+</div>
+
+- **DST_DATA_TYPE**
+  - _SW access_: rw
+  - _Description_: defines the destination data type using this scheme:
+    - 0: _word_, i.e. 4 bytes
+    - 1: _half word_, i.e. 2 bytes
+    - 2 or 3: _byte_
+    If wider than the source datatype and sign extension is enabled, the output data will be sign extended
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 1 ----|---- 0 : 0 ---|
+|--- Reserved ---|---- SGND ----|</code></pre>
+</div>
+
+- **SIGN_EXT**
+  - _SW access_: rw
+  - _Description_: enables the sign extension, which can be performed only if the output datatype is wider than the source datatype
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 2 ----|--- 1 : 0 ---|
+|--- Reserved ---|---- MODE ---|</code></pre>
+</div>
+
+- **MODE**
+  - _SW access_: rw
+  - _Description_: defines the operation mode of the DMA channel, following this scheme:
+    - 0: _linear mode_
+    - 1: _circular mode_
+    - 2: _address mode_
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 1 ----|---- 0 : 0 ----|
+|--- Reserved ---|--- DIM_CFG ---|</code></pre>
+</div>
+
+- **DIM_CONFIG**
+  - _SW access_: rw
+  - _Description_: defines the dimensionality of the transaction, i.e. if the transaction is 1D (DMA_DIM = 0) or if it is 2D (DMA_DIM = 1).
+
+  <hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 1 ----|--- 0 : 0 ---|
+|--- Reserved ---|---- INV ----|</code></pre>
+</div>
+
+- **DIM_INV**
+  - _SW access_: rw
+  - _Description_: enables the transposition of the input source, only with 2D transactions.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 6 ----|--- 5 : 0 ---|
+|--- Reserved ---|---- PAD ----|</code></pre>
+</div>
+
+- **PAD_TOP/BOTTOM/RIGHT/LEFT**
+  - _SW access_: rw
+  - _Description_: defines the size of the padding to be applied to the source, in data units.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 13 ---|--- 12 : 0 ---|
+|--- Reserved ---|---- W_SZ ----|</code></pre>
+</div>
+
+- **WINDOW_SIZE**
+  - _SW access_: rw
+  - _Description_: defines the size of the window to be copied.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 8 ----|---- 7 : 0 ---|
+|--- Reserved ---|---- W_CNT ---|</code></pre>
+</div>
+
+- **WINDOW_COUNT**
+  - _SW access_: ro
+  - _Description_: indicates the number of times the end of the window was reached since the beginning of the transaction.
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 2 ----|-- 1 ---|-- 0 ---|
+|--- Reserved ---|- W_DN -|- T_DN -|</code></pre>
+</div>
+
+- **INTERRUPT_EN**
+  - _SW access_: rw
+  - _Description_: enables the interrupt for window and/or transaction done.
+
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 1 ----|--- 0 : 0 ---|
+|--- Reserved ---|--- FLAG ----|</code></pre>
+</div>
+
+- **TRANSACTION_IFR**
+  - _SW access_: r0
+  - _Description_: interrupt flag register for transaction interrupts. It is set to '1' when the transaction interrupts are enabled and the transaction is completed. It is cleared when it's read by the CPU in the IRQ handler. This feature enables the handler to identify which channel raised the interrupt, as explained [here](#interrupts).
+
+<hr>
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>|---- 31 : 1 ----|--- 0 : 0 ---|
+|--- Reserved ---|--- FLAG ----|</code></pre>
+</div>
+
+- **WINDOW_IFR**
+  - _SW access_: r0
+  - _Description_: interrupt flag register for window interrupts. It is set to '1' when the window interrupts are enabled and the window is done. It is cleared when it's read by the CPU in the IRQ handler.
+
   
+## Functional description
+
+### Dictionary
+
+The implementation of the software layer introduced some concepts that need to be understood in order to make proper use of the DMA's functionalities.
+
   
-## Previous Definitions
-The implementation of this software layer introduced some concepts that need to be understood in order to make proper use of the DMA's functionalities .
-  
-### Transaction
-A transaction is an operation to be performed by the DMA. It implies copying bytes from a source pointer into a destination pointer. The transaction configuration can be loaded into the DMA registers once it has been cross-checked and it only starts when the size along the *first dimension* of the transaction is written in its corresponding register. The transaction is finished once the DMA has sent all its bytes (which not necessarily means they have been received by the final destination).
-Transactions cannot be stopped once they were launched.
-While a transaction is running, new transactions can be validated, but not launched or loaded into the DMA.
+
+#### Transaction
+
+A transaction is an operation to be performed by the DMA. It implies copying bytes from a source pointer into a destination pointer. 
+The transaction configuration can be cross-checked before loading it into the DMA registers to avoid potential issues. 
+The transaction starts only when the size of the *first dimension*, i.e. 1D, of the transaction is written in its corresponding register. The transaction is finished once the DMA has sent all its bytes (which not necessarily means they have been received by the final destination) or when the _external stop signal_ is asserted.
+
+While a transaction is running, new transactions can be validated, loaded and launched, provided they are not targeting the same DMA channel.
+
 Transactions can be re-launched automatically in `circular mode`.
-Once the transaction has finished, a status bit is changed (that can be monitored through polling) and a fast interrupt is triggered.
+
+Once the transaction has finished, a status bit is changed (that can be monitored through polling) and a fast interrupt is triggered. The channel that raised the interrupt is identified and it's passed to the the handler itself, which can be redefined by the user, as shown in [Example 7](#7-multichannel-mem2mem-transaction-focus-on-the-irq-handler) or in `example_dma_multichannel` in the application folder.
   
-### Source and destination
-Sources and destinations are the two pointers that will exchange data. Bytes will be copied from the source and into the destination address.
+
+#### Source and destination
+
+Sources and destinations are the two pointers that will exchange data. Bytes will be copied from the source and into the destination address. 
   
-### Data type
+
+#### Data type
+
 The DMA allows transactions in chunks of 1, 2 or 4 Bytes (`Byte`, `Half-Word` and `Word` respectively). The size in bytes of the chosen data type is called _data unit_ (usually abbreviated as `du`).
+
 For example, 16 bytes can be 16 data units if the data type is `Byte`, but 8 data units if the data type is `Half Word`.
-Source and destination can have different data types, if the destination type is wider than the source type, data can be sign extended.
-### Sign extension
-If specified (setting the bit in the corresponding register) and if the destination data type is wider than the source type, sign of the source data is extended to fill the size of the destination data type.
+Source and destination can have different data types and if the destination type is larger than the source type, data can be sign extended.
+
+#### Sign extension
+It can be enabled by setting the bit in the corresponding [register](#registers-description).
+If the destination data type is larger than the source type, the source data is sign extended to fill up the size of the destination data type.
+
+
+#### Dimensionality
 
-### Dimensionality
 The DMA can perform both **1D transactions** and **2D transactions**. 
-When set to perform 1D transactions, the DMA copies the defined number of elements from the source pointer to the destination pointer using a 1D increment.
-When set to perform 2D transactions, the DMA copies data from the source pointer to the destination pointer using both a 1D increment and an additional 2D increment. 
-In this way, two-dimensional data manipulations (e.g. matrix manipulations) can be performed in a single DMA transaction, greatly reducing the CPU time.
-### Increment
-In the 1D configuration, if source and/or destination data are not to be consecutively read/written, a certain increment can be defined.
-For instance, if you have an array of 4-bytes-words, but only want to copy the first 2 bytes of each word, you could define the transaction with a data type of half word, an increment of 2 data units in the source, and 1 data unit in the destination. This way, after each read operation the DMA will increment the read pointer in 4 bytes (2 data units), but the write pointer by only 2 bytes.
-In the 2D configuration, a second increment has to be set in order to enable the 2D transaction.
-In the context of matrix manipulation, the 2D increment is the number of words that the DMA has to "skip" to move to the next row.
-For instance, let's examine the extraction of a continuous 2x2 matrix from a 4x4 matrix, stored in a continuous 2x2 matrix.
-```
-| 3 | 5 | 7 | 9 |    
-| 2 | 4 | 6 | 8 | 	->  | 3 | 5 |
-| 1 | 3 | 5 | 7 | 	    | 2 | 4 |
-| 0 | 2 | 4 | 6 |
-```
-The total number of elements copied from the source is 4 elements. The increments are:
+In a 1D transaction, the DMA copies a certain number of elements from the source pointer to the destination pointer using a single increment.
+On the other hand, in a 2D transaction the DMA copies data from the source pointer to the destination pointer using two separate increments, which can be interpreted as a 1D and a 2D increment. 
+In this way, two-dimensional data manipulations, i.e. matrix manipulations, can be performed in a single DMA transaction.
+
+#### Increment
+
+In a 1D transaction, setting the increment appropriately can be leveraged to achieve non-contiguous read and/or write operations.
+
+For example, let's consider an array of 4 word-type elements. 
+To copy just the first 2 bytes of each word, follow these steps:
+
+- Set the datatype of the transaction to **half word**.
+- Set the source increment to **2 data units**.
+- Set the destination increment to **1 data unit**.
+
+After each reading operation, the DMA will increment the read pointer by 4 bytes (2 data units) and the write pointer by 2 bytes.
+
+In the case of 2D transactions, a second increment must be set to perform matrix manipulations. 
+The 2D increment can be interpreted as the number of words that the DMA has to "skip" to move to the next row of the matrix.
+
+For example, let's examine the extraction of a contiguous 2x2 matrix from a 4x4 matrix.
+
+		| 3 | 5 | 7 | 9 |               
+		| 2 | 4 | 6 | 8 |           ->           | 3 | 5 |
+		| 1 | 3 | 5 | 7 |                        | 2 | 4 |
+		| 0 | 2 | 4 | 6 |
+
+The total number of elements copied from the source is 4. 
+In order to achieve this result, these are the setup of the increments:
  - For the source:
 	- 1D increment set to 1 word 
 	- 2D increment set to 3 words
  - For the destination:
 	- 1D increment set to 1 word
 	- 2D increment set to 1 word
-By exploiting the 2D increment, it's possible to implement a non-continuous read and/or write by computing the correct 2D increment. Detailed formulas for the computation of 2D increments are reported in the *example_dma_2d* folder.
+
+Moreover, by exploiting the 2D increment, it is possible to implement a 2D non-continuous read and/or write.
+
+Detailed formulas for the computation of 2D increments are reported in the example application in the `\example_dma_2d` folder.
   
-### Zero padding
+#### Zero padding
 
-The DMA is capable of performing zero padding on the extracted data, both in 1D and 2D transactions.
-This is done by by setting four padding parameters:
-- **T**op				    
-- **B**ottom				     				
-- **L**eft				
-- **R**ight		
 
-e.g.
+The DMA is capable of performing zero padding on the extracted data, both in 1D and 2D transactions, within a single transaction.
+This is achieved by setting four padding parameters:
 
-```		
-| T | T | T | T | T |	
-| L | x | x | x | R |	
-| L | x | x | x | R |	
-| B | B | B | B | B |	
-```
-It's important to highlight the fact that the padding is performed (conceptually) only *after* the matrix has been extracted.
-Let's examine the previous 2x2 extraction example, adding a left and top padding of 1 word:
+- **T**op							    
+- **B**ottom				     					
+- **L**eft								
+- **R**ight							    
 
-```
-| 3 | 5 | 7 | 9 |      | 0 | 0 | 0 |
-| 2 | 4 | 6 | 8 |  ->  | 0 | 3 | 5 |
-| 1 | 3 | 5 | 7 |      | 0 | 2 | 4 |
-| 0 | 2 | 4 | 6 |
-```
+e.g. Let's consider a 2x3 matrix:
+		
+		| T | T | T | T | T |	
+		| L | x | x | x | R |	
+		| L | x | x | x | R |	
+		| B | B | B | B | B |	
+
+
+It's important to highlight that the padding is performed (conceptually) only *after* the matrix has been extracted.
+So the padding parameters refers only to the extracted matrix, not to the entire source matrix.
+
+Let's revisit the previous 2x2 extraction example, this time adding a left and top padding of 1 element:
+
+
+	| 3 | 5 | 7 | 9 |                        | 0 | 0 | 0 |
+	| 2 | 4 | 6 | 8 |           ->           | 0 | 3 | 5 |
+	| 1 | 3 | 5 | 7 |                        | 0 | 2 | 4 |
+	| 0 | 2 | 4 | 6 |
+
+
+#### Alignment
+
+When performing transactions with bytes, the DMA can read/write from any pointer. However, if the data type is larger, words should be aligned so the DMA can perform a read/write operation and affect only the chosen bytes. 
+If a word or half-word's pointer is not a multiple of 4 or 2 (respectively), the pointer is _misaligned_. In some cases the DMA HAL can overcome this problem by reducing the data type (which will reflect on an efficiency loss).
 
-### Alignment
-When doing transactions with bytes, the DMA can read/write from any pointer. However, if the data type is larger, words should be aligned so the DMA can perform a read/write operation and affect only the chosen bytes. If a word or half-word's pointer is not a multiple of 4 or 2 (respectively), the pointer is _misaligned_. In some cases the DMA HAL can overcome this problem reducing the data type (which will reflect on an efficiency loss).
-  
-### Environment
-An environment is a region of memory that can optionally be defined by the user to let the HAL know that it is allowed to read/write on that region. It is useful to make sure the DMA will not affect reserved memory regions.
-Right now, read and write permissions are not supported by environments, meaning that if it is defined, the DMA will be able to read AND write on it.
   
-### Triggers and Slots
-If the source or destination pointer is a peripheral, there are lines connecting the peripheral and the DMA that can be used to control the data flow (they behave as _triggers_). These lines are connected to _slots_ on the DMA and they allow/stop the DMA from reading/writing data.
+
+#### Environment
+
+An environment is a user-defined region of memory that informs the HAL of permissible read/write areas. This ensures that the DMA does not interfere with reserved memory regions.
+
+Read and write permissions are not supported by environments. If an environment is defined, the DMA will have both read and write access to it.
   
-### Target
-A target is either a region of memory or a peripheral to which the DMA will be able to read/write. When targets are pointing to memory, they can be assigned an environment to make sure that they will comply with memory restrictions.
-Targets include a pointer (a point in the memory, or the Rx/Tx buffer in case of peripherals), a size to be copied (if its going to be used as a source), a data type and an increment.
+
+#### Target
+
+A target is either a memory region or a peripheral that the DMA can read from or write to. When targets point to memory, they can be assigned an environment to ensure compliance with memory restrictions.
+
+Targets include:
+
+- A pointer (either a memory location or the Rx/Tx buffer for peripherals)
+- A size to be copied (if used as a source)
+- A data type
+- An increment
+
   
-### Configuration flags
+
+#### Configuration flags
+
 During the creation or configuration of environments, targets or transactions, there could be inconsistencies or threatening situations (like writing outside the boundaries of a defined region). To provide the user with information about this potentially harmful situations, configuration flags are set while creating each of these entities. They can be unmasked and checked.
+
 In some cases, when the threat is too risky, a _crucial error_ might be raised and the operation of the configuration is halted.
+
 If senseless configurations are input to functions, assertions may halt the whole program. This is reserved for extreme situations that mean the program was not properly coded (e.g. a slot value is provided and is not among the available ones).
+
   
-### Transaction modes
+
+#### Transaction modes
+
 There are three different transaction modes:
-**Single Mode:** The default mode, where the DMA will perform the copy from the source target to the destination, and trigger an interrupt once done.
-**Circular mode:** To take full advantage of the speed and transparency of the DMA, a _circular_ mode was implemented. When selected, the DMA will relaunch the exactly same transaction upon finishing. This cycle only stops if by the end of a transaction the _transaction mode_ was changed to _single_. The CPU receives a fast interrupt on every transaction finished.
+
+**Single Mode:** The default mode, where the DMA channel will perform the copy from the source target to the destination, and trigger an interrupt once done.
+
+**Circular mode:** It takes full advantage of the speed and transparency of the DMA. When selected, the DMA will relaunch the exact same transaction upon finishing. This cycle only stops if by the end of a transaction the _transaction mode_ was changed to _single_. The CPU receives a fast interrupt on every transaction finished.
+
 **Address Mode:** Instead of using the destination pointer and increment to decide where to copy information, an _address list_ must be provided, containing addresses for each data unit being copied. It is only carried out in _single_ mode. 
 In this mode it's possible to perform only 1D transactions.
+
   
-### Windows
-In order to process information as it arrives, the application can define a _window size_ (smaller than the _transaction size_. Every time the DMA has finished sending that given amount of information will trigger an interrupt through the PLIC.
+
+#### Windows
+
+In order to process information as it arrives, the application can define a _window size_ (smaller than the _transaction size_). Every time the DMA has finished sending that amount of information, it will trigger an interrupt through the PLIC.
+
 > :warning: If the window size is a multiple of the transaction size, upon finishing the transaction there will be first an interrupt for the whole transaction (through the FIC), and then an interrupt for the window (through the PLIC, which is slower).
+
   
   
-### Checks and Validations
+
+#### Checks and Validations
+
 The DMA HAL's interface functions perform two types of checks:
+
 *  **Sanity checks**: Make sure that each individual value passed as an argument is reasonable and belongs to the proper domain. This errors will raise an _assertion_ and, depending on how assertions are managed in the application, may result in the program crashing.
+
 *  **Integrity checks**: Arguments are cross-checked to make sure that they abide by the rules of the DMA. If configurations are incompatible, contradictory, or a risk for the programs integrity, warnings are raised through the _configuration flags_. In some special cases, a _critical error_ can be raised, which blocks the deployment of the configuration into the DMA registers.
+
   
+
 > :warning: Integrity checks can be disabled to speed up configuration time. Do this only if you have previously checked the configuration and are sure it will not cause any trouble.
+
   
+
 Checks and validations are performed during the transactions creation, loading and launching.
+
   
+
 A transaction is validated if it went through the creation-checks without raising critical errors.
+
   
-### End events
-The DMA considers a certain amount of bytes to have been transferred once it has sent them. It does not wait for a confirmation from the recipient. When a transaction/window is finished the DMA performs a series of event. These may include:
+
+#### End events
+
+The DMA considers a certain amount of bytes to have been transferred once it has sent them. It does not wait for a confirmation from the recipient, but can be interrupted at any time using the `ext_dma_stop` signal. 
+When a transaction/window is finished the DMA performs a series of events. These may include:
+
 * Changing its status register.
+
 * Raising a _transaction done_ interrupt.
+
 * Raising a _window done_ interrupt.
+
   
-The DMA HAL can follow up on these changes or let the application be in charge. For this purpose, three different types of _end events_ are defined:
+
+The DMA HAL can follow up on these changes or let the application be in charge of them. For this purpose, three different types of _end events_ are defined:
+
 *  **Polling**: The HAL will disable interrupts from the DMA. The application will need to frequently query the status of the DMA to know when a transaction has finished.
+
 *  **Interrupt**: Interrupts will be enabled. The _window done interrupt_ is enabled if a window size is provided.
+
 *  **Interrupt wait**: The DMA HAL will block the program in a `wfi()` state until the _transaction done interrupt_ is triggered.
+
+
+## Software stack: HAL and SDK
   
-  
-## Operation
-This section will explain the operation of the DMA through the DMA HAL.
-There is a DMA instance inside X-HEEP, but others can be connected outside through the bus (see the `example_external_peripheral` application in `sw/aplications/example_external_peripheral/main.c`). As long as the DMA instance is the same and the registers are memory mapped with the same structure, the DMA HAL can be used.
-  
-The DMA HAL adds an extra computational overhead to transactions in order to check the consistency of the transaction configurations. By-passing this layer (and the steps here described) is disadvised. For the efficiency-hungry applications, doing at least one pass with the whole validation process is recommended. The HAL allows to load and launch transactions with minimum overhead afterwards.
-  
-The following explanation makes use of Figure 1.
-  
-![DMA HAL-HW + addresses](https://github.com/esl-epfl/x-heep/assets/54960111/3092faa5-c72c-4cd9-a4d4-4c87de63d1c7)
-<p  align="center">Figure 1: Example operation of the DMA and its HAL</p>
-  
----
-  
-The use of the DMA starts with the application creating a set of targets (<span  style="color:red">**a**</span>) . In the figure, the source target is a peripheral connected to an SPI and to the DMA. The address of the reception FIFO (_Rx FIFO_) of this SPI is `0x70` (<span  style="color:red">**b**</span>) . The destination target is a region of memory of address `0x16` (<span  style="color:red">**c**</span>). It is located inside an environment that spans from `0x12` to `0x35`. Any number of environments and targets can be created, and not used.
-  
-Additionally, in the application the transaction is created. The _operation mode_ and _window size_ are selected.
-  
-The application calls the validation function of the HAL. If the configurations do not raise a critical flag, it then calls the loading function. By doing so, the desired values are written into their corresponding registers (<span  style="color:red">**d**</span>). The only register that is not immediately written is the _transaction size_, as it is the one responsible for launching the transaction when changed from zero to a non-zero value. It is only written once the application calls the launching function (<span  style="color:red">**e**</span>).
-  
-Note that there could be some changes between the configuration input in the application and the values written in the registers. For example, a _window size_ of 2 refers to _2 data units_ (i.e. 2 half-words, as such is the data type of the source in Figure 1); however, when writing on the register, this is translated to bytes, so 4 is written instead.
-  
-Once launched, the transaction will execute completely (it cannot be stopped). Upon finishing, it will check the _operation mode_ and _transaction size_ registers. If any of both is non-zero, it will relaunch. Note that the selecting _circular mode_ during the configuration loading does not launch the transaction (despite what step (<span  style="color:red">**f**</span>) might suggest, which is only illustrative).
-  
-  
-Once the transaction is launched, the DMA will take care of copying as many data units as were requested from the source target (<span  style="color:red">**g**</span>), and pasting them into the destination target (<span  style="color:red">**h**</span>). The data width of the transaction is determined by the _data type_ of the source target (<span  style="color:red">**i**</span>). However, this might be changed (for a smaller width) in case of misalignment. It is possible to reject changes by the DMA HAL and raise an error in case of misalignments instead.
-  
-The selected slot will query the state of a trigger from the peripheral (<span  style="color:red">**j**</span>). In case the peripheral's FIFO is empty/full (for reception/transmission respectively), the transaction is paused until the trigger enables it again.
-  
-The source and destination increments will determine the amount of steps the pointer should jump after every read and write, respectively. For peripherals it should always be zero (as it should always take the first element of the FIFO).
-  
-The DMA will consider a data unit was transferred once it is sent (<span  style="color:red">**k**</span>). It does not wait for an acknowledge by the destination target.
-  
-The _interrupts_ register controls whether the events triggered by the DMA upon finishing a window or a whole transaction should be propagated as interrupts (<span  style="color:red">**l**</span>).
-  
-Every time _window size_ data units have been transferred the window count is incremented and a PLIC interrupt is triggered (if enabled) (<span  style="color:red">**m**</span>).
-  
-Every time a transaction is finished a FIC interrupt is triggered and the restart condition is evaluated (<span  style="color:red">**f**</span>).
-  
-If the window size is a multiple of the transaction size, upon finishing the transaction there will be first an interrupt for the whole transaction (through the FIC), and then an interrupt for the window (through the PLIC, which is slower).
-  
-  
-The DMA HAL has weak implementations to handle each interrupt. It is up to the application to do something useful with this. the HAL will only forward the interrupt (<span  style="color:red">**n**</span>).
-  
-> :warning: If the window size is too small (i.e. the time the DMA requires to make the copy is smaller than the time required to attend the interrupt handling), data might be lost. The HAL implements a warning in case the transaction-window size ratio is to small. The warning can be re-configured to an appropriate threshold by overriding a weak implementation. The user should do its own testing and choose this threshold accordingly. The same type of issue might be found on circular mode. The user should be sure it can attend an interrupt before the next one occurs. There is no warning from the HAL in this case.
-  
-The same result from this example could have been achieved by setting the transaction mode to _address_. It requires an array of destination addresses (<span  style="color:red">**p**</span>) that must be provided as the destination target pointer. Instead of copying information to that pointer, the DMA will read from there and copy the information into the addresses stored in each word (<span  style="color:red">**o**</span>).
-This use case is very impractical as it doubles the memory usage. It is intended to be used along In-Memory-Computing architectures and algorithms.
-  
-## Usage
-This section will explain a basic usage of the DMA as a `memcpy`, and a slightly more complex situation involving a peripheral connected via an SPI.
-  
-### Basic application
-This example will provide a simplified code for copying data from one region of memory to another. For a real implementation please refer to the `dma_example` application in `sw/applications/dma_example/main.c`.
-  
-The objective of this app would be to copy the content of an array into another.
-  
----
-  
-Start the application by calling
-```C
-dma_init( NULL );
-```
-  
-This will reset the DMA registers. The `NULL` parameter tells the HAL that the devices internal DMA is to be used.
-  
-The most basic implementation requires the creation of **two targets** and a **transaction** relating them both.
-  
-A target will include the information of the source or destination pointer and the characteristics of the expected transaction.
-  
-Theoretically, there is no required difference between a _source_ and _destination_ target. They will only be differentiated once the transaction is created. Eventually, they could be interchanged from one transaction to the next. In this example they will be given explicit names and will take different arguments for the sake of clarity.
-  
-```C
-static dma_target_t tgt_src = {
-				.ptr        = copy_buffer,
-				.inc_du     = 1,
-				.size_du    = sizeof(copy_buffer),
-				.type       = DMA_DATA_TYPE_WORD
-				};
-```
-  
-Here, `ptr = copy_buffer` is a `uint32_t` pointer from where the information will be extracted. `inc_du = 1` is telling the DMA that for each word copied, the pointer should be incremented by 1 unit, therefore words will be copied consecutively without gaps.
-  
-This configuration is implicitly initializing the rest of the target configurations as zero (as of [C99](https://gcc.gnu.org/onlinedocs/gcc/Designated-Inits.html)). This means that:
-* No environment is set.
-* Data type is set to _word_ (32-bits).
-* The trigger is set to _memory_ (vs. a peripheral).
+Like every other computational unit in X-Heep, a DMA transaction can be set up and launched using direct register writes. This method achieves minimal overhead and optimal performance, as thoroughly documented in `sw/applications/example_dma_2d` and `sw/applications/example_dma_multichannel`. 
+
+However, this strategy carries **significant risks**. For instance, the transaction starts immediately after writing to the size register, so the order of register writes must be strictly followed. If the code is compiled with aggressive optimization flags, these write operations might be reordered, potentially compromising the DMA functionality. Additionally, errors in setting the transaction size or increments can lead to memory corruption.
+
+Given the criticality of DMA operations and the potential for destructive errors, direct register writes should be approached with utmost _caution_. To mitigate these risks and ease the application development, two software stacks have been developed:
+
+- **HAL**: Provides functions for initializing DMA channels, validating and correcting issues within the targets, loading and launching transactions.
+<br>
+
+- **SDK**: Offers user-friendly functions for basic but essential *memcpy* and *fill* operations. It does not include the validation capabilities of the HAL nor the 2D and padding features, prioritizing performance at the cost of an increased risk of failure.
+
+### DMA HAL
+
+This section will include a brief overview of the functionalities offered by the DMA HAL. For more practical example, please refer to the next chapter, _"Usecases and examples"_.
+
+Let's start with the structures that enable users to define a DMA transaction and its targets, defined in `dma.h`:
+
+> :warning: Remember to declare these structure as **global**, i.e. outside the main() function, or **static** if they need to be local. This is **critical** as it ensures that the fields that are not needed are initialized correctly.
+
+#### <i> dma_target_t </i>
+
+The dma_target_t structure represents a target for a DMA transaction, either as a source or a destination. It encapsulates the parameters required to define a memory region or a peripheral for DMA operations. Furthermore, control parameters can be added to prevent the DMA from reading/writing outside the boundaries of the target.
+
+#### <i> dma_trans_t </i>
+
+The dma_trans_t structure defines a DMA transaction, encapsulating all the necessary parameters and configurations required to perform a DMA operation. Each member of the structure is designed to handle specific aspects of the transaction, from source and destination targets to increments, transaction sizes, data types, and operational modes.
+<br>
+Let's examine the main functions to be called in order to correctly perform a DMA transaction.
+
+#### <i> dma_init() </i>
+
+*Purpose*:
+The dma_init function initializes the DMA subsystem by cresetting transaction structures and clearing DMA registers of each channel.
+
+*Parameters*:
+- dma *dma_peri: Pointer to the DMA peripheral. If this pointer is provided, it uses the given DMA peripheral; otherwise (NULL), it uses the integrated DMA peripheral.
+
+#### <i> dma_validate_transaction() </i>
+
+_Purpose_:
+The dma_validate_transaction function ensures the configuration of a DMA transaction is correct, checking for potential issues that could prevent the transaction from executing properly. It performs sanity checks, verifies target configurations, and addresses any alignment, increment, padding, trigger, and mode inconsistencies.
+
+_Parameters_:
+- dma_trans_t *p_trans: Pointer to the DMA transaction structure that contains the transaction configuration.
+- dma_en_realign_t p_enRealign: Flag indicating whether realignment is enabled.
+- dma_perf_checks_t p_check: Flag indicating whether integrity checks should be performed.
+
+_Return Values_:
+- dma_config_flags_t: Configuration flags indicating the status of the transaction validation. They provide information about the validity of the transaction and any detected errors or warnings.
+
+#### <i> dma_load_transaction() </i>
+
+_Purpose_:
+The dma_load_transaction function configures and loads a DMA transaction into a DMA channel. It checks for critical errors defined by the validation function, ensures no other transaction is running, and sets various parameters such as interrupts, pointers, increments, padding, and operation modes by writing in the correct registers. The only register that is not written is the 
+SIZE_D1 register so it doesn't launch the transaction.
+
+_Parameters_:
+- dma_trans_t *p_trans: Pointer to the DMA transaction structure that contains the configuration for the transaction.
+
+_Return Values_:
+- DMA_CONFIG_OK: Indicates that the transaction was successfully loaded.
+- DMA_CONFIG_CRITICAL_ERROR: Indicates that the transaction contains a critical error and cannot be loaded.
+- DMA_CONFIG_TRANS_OVERRIDE: Indicates that another transaction is currently running and cannot be overridden.
+
+#### <i> dma_launch() </i>
+
+_Purpose_:
+The dma_launch function initiates a DMA transaction that has been previously configured and loaded into a DMA channel. It ensures the transaction is valid, checks for any ongoing transactions, and then starts the new transaction. If the end event is set to wait for an interrupt, the function will block until the interrupt is received.
+
+_Parameters_:
+- dma_trans_t *p_trans: Pointer to the DMA transaction structure that contains the configuration for the transaction.
+
+_Return Values_:
+- DMA_CONFIG_OK: Indicates that the transaction was successfully launched.
+- DMA_CONFIG_CRITICAL_ERROR: Indicates that the transaction could not be launched due to a critical error.
+- DMA_CONFIG_TRANS_OVERRIDE: Indicates that another transaction is currently running and cannot be overridden.
+
+#### <i> fic_irq_dma() </i>
+
+_Purpose_:
+The *fic_irq_dma* function is called whenever one of the DMA channels raises the fast interrupt line, signaling the FIC (Fast Interrupt Controller) that a transaction has completed. As thoroughly explained in Example 7 of the next section, this function identifies the channel that triggered the interrupt and calls a handler function, *dma_intr_handler_trans_done()*, passing the channel ID. 
+
+This function can be redefined by the user to perform specific actions, provided that the computational load of these tasks is kept to a minimum.
+
+_Parameters_: 
+- None
+
+_Return Values_:
+- None (void type)
+
+<br>
+
+#### <i> handler_irq_dma() </i>
+
+_Purpose_:
+The *handler_irq_dma* function is very similar to *fic_irq_dma*, but its called whenever one of the DMA channels triggers a window donw interrupt, i.e. the transaction has copied N elements. Just like the previous one, this function identifies the channel that triggered the interrupt and calls a handler function, *dma_intr_handler_window_done()*, passing the channel ID. 
+
+_Parameters_: 
+- None
+
+_Return Values_:
+- None (void type)
+
+<br>
+
+## Usecases and examples
+
+This section will examine and explain several use cases in detail to provide users with a comprehensive understanding of the DMA subsystem and how to leverage it to enhance their application's performance.
+
+These examples focus on the use of the DMA HAL and the padding and multichannel capabilities of the DMA. The DMA SDK is straightforward enough to be fully understood through the structural and operational descriptions provided in the previous sections.
+
+Here is a brief overview of the examples:
+
+1) Simple mem2mem transaction, i.e., 1D memcpy 
+2) Simple mem2mem transaction with address mode
+3) Sign extension
+4) 2D mem2mem transaction, i.e., 2D memcpy
+5) Matrix transposition
+6) Matrix zero padding
+7) Multichannel mem2mem transaction, focusing on the IRQ handler
+8) Multichannel flash2mem transaction using the SPI FLASH
+
+The complete code for these examples can be found in `sw/applications/example_dma`, `sw/applications/example_dma_2d`, `sw/applications/example_dma_multichannel` and `sw/applications/example_dma_sdk`. These applications offer both verification and performance estimation modes, enabling users to verify the DMA and measure the application's execution time.
+
+The user is strongly incouraged to look at these applications, as well as any other application that employs the DMA, to gain insight in practical examples of the use of this peripheral. Some aspects or specific usecases might in fact not be present in this guide and could be found in the applications.
+
+> :warning: If you have any relevant questions about the DMA or other topics, feel free to open a _question_ on our GitHub repository page!
+
+<br>
+
+### 1. Simple mem2mem transaction
+
+The goal of this example is to develop a function that copies the content of a source array to a destination array.
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+The first step is to define the source and destination target structs, as well as the transaction structs.
+
+> :warning: Declare the targets and the transaction structs globally to ensure that the fields unused in this example are automatically initialized to zero. 
+This practice prevents unintentional data corruption or unexpected behavior during the DMA transaction.
+
+In this example, an array of six 32-bit words is used. 
+The data type for both the source and destination is specified in the `.type` field of their respective dma_target_t structures.
+Since the data is stored in RAM, the trigger, `.trig`, will be the default one, i.e. *DMA_TRIG_MEMORY*. 
+
+In this example, a 4-element array will be extracted from the 6-element source. The size of the transaction, which is the number of elements to be copied, is specified in `.size_d1_du`. 
+
+The transaction mode will be set to single mode, so the `.mode` field will be configured as *DMA_TRANS_MODE_SINGLE*.
+Finally, let's set the end event, `.end`, to *DMA_TRANS_END_INTR_WAIT*, to leave the HAL to wait for the interrupt.
+
 ```C
-static dma_target_t tgt_dst = {
-                                .ptr        = copy_buffer,
-                                .inc_du     = 1,
-                                .size_du    = sizeof(copy_buffer),
-                                .type       = DMA_DATA_TYPE_WORD
-                                };
+
+  int size = 4;
+  uint32_t src[6] = {0x12345678, 0x76543210, 0xfedcba98, 0x579a6f90, 0x657d5bee, 0x758ee41f};
+  uint32_t dst[4];
+
+  dma_target_t tgt_src = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .type = DMA_DATA_TYPE_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst = {
+    .ptr = (uint8_t *) dst,
+    .inc_d1_du = 1,
+    .type = DMA_DATA_TYPE_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans = {
+    .src = &tgt_src,
+    .dst = &tgt_dst,
+    .size_d1_du = size,
+    .src_addr = NULL,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .end = DMA_TRANS_END_INTR_WAIT,
+  };
+
 ```
-Both destination and source targets have to contain a data type (they can be different) and size in data units (they should be the same).
-Finally, a transaction is created to relate both targets:
+
+#### Perform validation, loading and launching
+
+This second step is also the final one! The only thing left to do is to perform the __validation__ of the transaction, __load__ the parameters, and __launch__ of it. For convenience, let's put these calls inside a dedicated function, called *run_dma_trans()*.
+
+The *DMA_ENABLE_REALIGN* flag signals the HAL to perform realignment when necessary. Similarly, the *DMA_PERFORMS_CHECKS_INTEGRITY* flag instructs the HAL to perform integrity checks.
+
+The return values of these HAL calls will be stored and returned to check for any potential issues.
+
+``` C
+
+dma_config_flags_t run_dma_trans(dma_trans_t *trans)
+{
+  dma_config_flags_t res;
   
-```C
-static  dma_trans_t trans = {
-				.src = &tgt_src,
-				.dst = &tgt_dst,
-				};
+  res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_load_transaction(&trans);
+  res |= dma_launch(&trans);
+
+  return res;
+} 
+    
 ```
-  
-This will also imply some configurations set to zero:
-* Mode is set to singular (only one transaction will be executed).
-* There will be no window interrupts.
-* The application will have to do polling to know when the transaction has finished.
-  
-The transaction can now be created (some extra configurations are computed from the targets), loaded into the DMA and launched.
-  
-```C
-dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
-dma_load_transaction( &trans );
-dma_launch( &trans );
-  
+
+The datatype *dma_config_flags_t* is defined in the HAL header and is provided below for convenience:
+ 
+``` C
+
+typedef enum
+{
+    DMA_CONFIG_OK               = 0x0000, /*!< DMA transfer was successfully
+    configured. */
+    DMA_CONFIG_SRC              = 0x0001, /*!< An issue was encountered in the
+    source arrangement.  */
+    DMA_CONFIG_DST              = 0x0002, /*!< An issue was encountered in the
+    destination arrangement. */
+    DMA_CONFIG_MISALIGN         = 0x0004, /*!< An arrangement is misaligned. */
+    DMA_CONFIG_OVERLAP          = 0x0008, /*!< The increment is smaller than the
+     data type size. */
+    DMA_CONFIG_DISCONTINUOUS    = 0x0010, /*!< The increment is larger than the
+    data type size. */
+    DMA_CONFIG_OUTBOUNDS        = 0x0020, /*!< The operation goes beyond the
+    memory boundaries. */
+    DMA_CONFIG_INCOMPATIBLE     = 0x0040, /*!< Different arguments result in
+    incompatible requests. */
+    DMA_CONFIG_WINDOW_SIZE      = 0x0080, /*!< A small window size might result
+    in loss of syncronism. If the processing of the window takes longer than the
+    time it takes to the DMA to finish the next window, the application will not
+    be able to cope. Although "how small is too small" is highly dependent on
+    the length of the processing, this flag will be raised when the transaction
+    and window size ratio is smaller than an arbitrarily chosen ratio as a mere
+    reminder. This value can be overriden buy means of defining a non-weak
+    implementation of the dma_window_ratio_warning_threshold function. */
+    DMA_CONFIG_TRANS_OVERRIDE   = 0x0100, /*!< A transaction is running. Its
+    values cannot be modified, nor can it be re-launched. */
+    DMA_CONFIG_CRITICAL_ERROR   = 0x0200, /*!< This flag determines the function
+    will return without the DMA performing any actions. */
+} dma_config_flags_t;
+
 ```
+
+Now, the function can be called inside the `main` function, and the flags should be checked to ensure the transaction was executed correctly.
+
+``` C
+
+...
+
+int main()
+{
+  dma_init(NULL);
   
-When creating the transaction, the two last parameters are allowing the DMA to perform integrity checks and try some fixes (at the expense of efficiency) if misalignments are found.
-  
-As there will be no interrupts set, the application has to check by itself the status of the transaction.
-  
-```C
-while( ! dma_is_ready() ){}
-// The transaction has finished!
+  dma_config_flags_t result = run_dma_trans();
+
+  if (result != 0)
+  {
+    printf("Error! DMA transaction failed with code: %d\n", result);
+    return 1;
+  } else {
+    printf("Success!\n");
+    return 0;
+  }
+}
+
 ```
-  
-  
-### Complete Application
-The objective of this example is to show various special cases, precautions and considerations that can be taken. For a real example refer to the `spi_flash_write` application in `sw/applications/spi_flash_write/main.c`.
-  
-This example will copy every other byte from a buffer in RAM to a FLASH connected via an SPI to the DMA. Then, it will copy information from an SPI peripheral continuously into a small buffer.
-  
-This explanation assumes you have read the previous example.
-  
----
-  
-Start the application by calling
+<br>
+
+### 2. Simple mem2mem transaction with address mode
+
+The goal of this example is to develop a function that copies the content of a source array to a destination array using the address mode.
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+Just like in example 1., the first step is to define the source and destination target structs, as well as the transaction structs.
+
+This time, the address mode will be used. The DMA channel will use the content of an array as destination pointers, instead of computing them itself. These addresses will be generated in the *main()* as showed later on.
+
 ```C
-dma_init( NULL );
+
+  int size = 4;
+  uint32_t src[6] = {0x12345678, 0x76543210, 0xfedcba98, 0x579a6f90, 0x657d5bee, 0x758ee41f};
+  uint32_t dst[size];
+  uint32_t addr[6];
+
+  dma_target_t tgt_src = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .type = DMA_DATA_TYPE_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst = {
+    .ptr = (uint8_t *) dst,
+    .inc_d1_du = 1,
+    .type = DMA_DATA_TYPE_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_target_t tgt_addr = {
+    .ptr = (uint8_t *) addr,
+    .inc_d1_du = 1,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans = {
+    .src = &tgt_src,
+    .dst = &tgt_dst,
+    .src_addr = &tgt_addr;
+    .size_d1_du = size,
+    .src_addr = NULL,
+    .mode = DMA_TRANS_MODE_ADDR,
+    .win_du = 0,
+    .end = DMA_TRANS_END_INTR_WAIT,
+  };
+
 ```
+
+#### Perform validation, loading and launching
+
+Once again, only two steps! Time to perform the __validation__ of the transaction, __load__ the parameters, and __launch__ of it. 
+Let's put these calls inside a dedicated function, called *run_dma_addr_trans()* and launch it in the *main()*. Finally, let's add a simple for loop to print out the result, i.e. the extracted matrix.
+
+``` C
+
+dma_config_flags_t run_dma_addr_trans(dma_trans_t *trans)
+{
+  dma_config_flags_t res;
   
-The first source target will be pointing to a `uint16_t` buffer in memory. Data will be copied in chunks of 1 byte. For every half-word (16 bits), the only the second half (second 8 bits) will be copied.
+  res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_load_transaction(&trans);
+  res |= dma_launch(&trans);
+
+  return res;
+} 
+
+...
+
+int main()
+{
+  dma_init(NULL);
+
+  // Data setup for address mode
+  for (int i = 0; i < 6; i++)
+  {
+    addr[i] = &src[i];
+  }
   
-```C
-static  dma_target_t tgt1= {
-				.ptr = (uint8_t*)(copy_buffer + 1),
-				.inc_du = 2,
-				.size_du = sizeof(copy_buffer),
-				.type = DMA_DATA_TYPE_BYTE,
-				};
+  dma_config_flags_t result = run_dma_addr_trans();
+
+  if (result != 0)
+  {
+    printf("Error! DMA transaction failed with code: %d\n", result);
+    return 1;
+  } else {
+    printf("Success!\n");
+    return 0;
+  }
+}
+
 ```
-  
-To start copying information from the second byte of `copy_buffer`, the source pointer is set to the address of `copy_buffer` plus one byte.
-In order to copy one byte and skip another, the data type is set to byte, and the increment is set to two data units (i.e. two bytes). As for every half-word of the buffer a data unit will be copied, the transaction size is the same as the size of the `copy_buffer`.
-  
-  
-The second target will point to the address of the SPI FLASH transmission FIFO. On this example, this value was already computed and stored in a constant `ADDRESS_SPI_FLASH_TX_FIFO`.
-  
-  
+<br>
+
+### 3. Sign extension
+
+The goal of this example is to develop a function that transforms an array of bytes in an array of words, performing sign extension when necessary.
+
+Many examples of sign extensions are present in *TEST_SINGLE* in `example_dma`.
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+First step: define the source and destination target structs, as well as the transaction structs. This time, it's important to pay attention to the data types and ensure that the sign extension feature is enabled.
+
+
 ```C
-static  uint32_t *spi_flash_fifo_tx = ADDRESS_SPI_FLASH_TX_FIFO;
-  
-  
-static  dma_target_t tgt2= {
-				.inc_du = 0,
-				.trig = DMA_TRIG_SLOT_SPI_FLASH_TX,
-				};
-tgt2.ptr = spi_flash_fifo_tx;
+
+  #define SIZE 6
+  uint8_t src[SIZE] = {0xe7, 0x32, 0x89, 0x0a, 0x12, 0xfd}; // {-25, 50, -119, 18, -3}
+  uint32_t dst[SIZE];
+
+  dma_target_t tgt_src = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .type = DMA_DATA_TYPE_BYTE,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst = {
+    .ptr = (uint8_t *) dst,
+    .inc_d1_du = 1,
+    .type = DMA_DATA_TYPE_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans = {
+    .src = &tgt_src,
+    .dst = &tgt_dst,
+    .size_d1_du = size,
+    .src_addr = NULL,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .sign_ext = 1; // This flag enables sign extension!
+    .end = DMA_TRANS_END_INTR_WAIT,
+  };
+
 ```
+
+#### Perform validation, loading and launching
+
+Once again, only two steps! Time to perform the __validation__ of the transaction, __load__ the parameters, and __launch__ of it. 
+Let's put these calls inside a dedicated function, called *run_dma_signext_trans()* and launch it in the *main()*. Finally, let's add a simple for loop to print out the result.
+
+``` C
+
+dma_config_flags_t run_dma_signext_trans(dma_trans_t *trans)
+{
+  dma_config_flags_t res;
   
-Because structure initializers need to be constants, the pointer value (which is a non-constant variable) needs to be initialized outside the designated initializer.
-  
-  
-There is no need to assign a value of transaction size or data type. By default, the DMA will use the source's values. The data type could eventually be modified by the HAL if there is a misalignment and `DMA_ENABLE_REALIGN` is set when creating the transaction.
-  
-The increment needs to be set to zero as the pointer should always be set to the FIFO address.
-  
-Because the SPI FLASH transmission FIFO has a line connected to slot number 4 (codified as a `1` in the fourth bit of the `trig` element) to let the DMA know if the FIFO is full, a trigger is set in that position by passing `.trig = DMA_TRIG_SLOT_SPI_FLASH_TX`.
-  
+  res = dma_validate_transaction(trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_load_transaction(trans);
+  res |= dma_launch(trans);
+
+  return res;
+} 
+
+...
+
+int main()
+{
+  dma_init(NULL);
   
-The transaction is formed by selecting the source and destination targets
+  dma_config_flags_t result = run_dma_signext_trans(&trans);
+
+  if (result != 0)
+  {
+    printf("Error! DMA transaction failed with code: %d\n", result);
+    return 1;
+  } else {
+    printf("Success!\n");
+    
+    for (int i=0; i<SIZE; i++){
+      printf("%x ", dst[i]);
+    }
+    printf("\n");
+
+    return 0;
+  }
   
-```C
-static  dma_trans_t trans = {
-				.src = &tgt1,
-				.dst = &tgt2,
-				.end = DMA_TRANS_END_INTR,
-				};
+}
+
 ```
-  
-To enable interrupts, the end event is set to `DMA_TRANS_END_INTR`.
-  
-  
-To create the transaction allowing the DMA to perform necessary realignments and integrity checks such arguments are passed to the creation function along with a pointer to the transaction.
-  
+
+### 4. 2D mem2mem transaction
+
+The goal of this example is to develop a function that extracts a submatrix from a source matrix and copies it to a destination matrix.
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+Just like in example 1., the first step is to define the source and destination target structs, as well as the transaction structs.
+
+This time, a few parameters are changed. Let's imagine that the source is now a 4x4 matrix, and we want to extract the top-left 2x2 matrix from it. For the sake of variation, this time we will use a half-word data type.
+
+Let's compute the 2D increment needed to extract the submatrix. The following formula applies in this case, as the submatrix is being extracted with a stride of 1 and without any padding.
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: left;"><code>SRC_INC_D2 = SIZE_IN_D1 - (SIZE_EXTR_D1 - 1)</code></pre>
+</div>
+
+In this case, the source 2D increment will be 3 data units. On the other hand, the destination increment will always be 1 when the destination stride is 1.
+
+Finally, set the dimensionality flag to 1 to configure it for 2D transactions.
+
 ```C
-dma_config_flags_t res;
-res = dma_validate_transaction( &trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+
+  #define SIZE_IN_D1 4
+  #define SIZE_IN_D2 4
+  #define SIZE_EXTR_D1 2
+  #define SIZE_EXTR_D2 2
+  #define SRC_INC_D2 = SIZE_IN_D1 - (SIZE_EXTR_D1 - 1)
+  #define DST_INC_D2 = 1
+
+  uint16_t src[SIZE_IN_D1*SIZE_IN_D2] = {
+    0x1234, 0x7654, 0xfedc, 0xffff,
+    0x5912, 0xabcd, 0xcdef, 0xfafa,
+    0x579a, 0x657d, 0x758e, 0xabba,
+    0xa1a1, 0xc3c3, 0xb2b2, 0xf4f4
+    };
+  uint16_t dst[SIZE_EXTR_D1*SIZE_EXTR_D2];
+
+  dma_target_t tgt_src = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .inc_d2_du = SRC_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst = {
+    .ptr = (uint8_t *) dst,
+    .inc_d1_du = 1,
+    .inc_d2_du = DST_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans_2d = {
+    .src = &tgt_src,
+    .dst = &tgt_dst,
+    .src_addr = NULL,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .dim = DMA_DIM_CONF_2D, // This is the dimensionality flag!
+    .size_d1_du = SIZE_EXTR_D1,
+    .size_d2_du = SIZE_EXTR_D2,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .end = DMA_TRANS_END_INTR_WAIT,
+  };
+
 ```
-  
-The result variable `res` contains configuration flags that can be used to check that no errors or warnings were raised. These are codified as bits in the 16-bit `res` variable.
-If only one flag was raised, the value of `res` will be equal to it. Otherwise, they can be checked by selecting individual bits, with inequalities, or comparing the result to a bitwise-or of flags.
-  
+
+<br>
+
+### 5. Matrix transposition
+
+The goal of this example is to develop a function that extracts a submatrix from a source matrix, transpose it and copies it to a destination matrix.
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+Once again, the first step is to define the source and destination target structs, as well as the transaction structs.
+
+Let's use the same formula as in example 2 to extract a 2x2 matrix from a 4x4 source matrix. So in this case too, the source 2D increment will be 3 data units, while the destination increment will be 1.
+
+To perform the transposition, we simply need to set a specific tag in the transaction struct, *.dim_inv*.
+
 ```C
-if( res == DMA_CONFIG_OK ) // Everything was ok.
-if( res & DMA_CONFIG_CRITICAL_ERROR ) // A critical error was found. It has to be fixed or the transaction will not be loaded.
-if( res >= DMA_CONFIG_OVERLAP && res =< DMA_CONFIG_TRANS_OVERRIDE ) // One or more warning flags were raised between those two.
-if( res & ( DMA_CONFIG_SRC | DMA_CONFIG_DST) ) // Either one of the flags was raised.
+
+  #define SIZE_IN_D1 4
+  #define SIZE_IN_D2 4
+  #define SIZE_EXTR_D1 2
+  #define SIZE_EXTR_D2 2
+  #define SRC_INC_D2 = SIZE_IN_D1 - (SIZE_EXTR_D1 - 1)
+  #define DST_INC_D2 = 1
+
+  uint16_t src[SIZE_IN_D1*SIZE_IN_D2] = {
+    0x1234, 0x7654, 0xfedc, 0xffff,
+    0x5912, 0xabcd, 0xcdef, 0xfafa,
+    0x579a, 0x657d, 0x758e, 0xabba,
+    0xa1a1, 0xc3c3, 0xb2b2, 0xf4f4
+    };
+  uint16_t dst[SIZE_EXTR_D1*SIZE_EXTR_D2];
+
+  dma_target_t tgt_src = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .inc_d2_du = SRC_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst = {
+    .ptr = (uint8_t *) dst,
+    .inc_d1_du = 1,
+    .inc_d2_du = DST_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans_2d = {
+    .src = &tgt_src,
+    .dst = &tgt_dst,
+    .src_addr = NULL,
+    .size_d1_du = SIZE_EXTR_D1,
+    .size_d2_du = SIZE_EXTR_D2,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .dim = DMA_DIM_CONF_2D,
+    .dim_inv = 1; // This is the transposition flag!
+    .end = DMA_TRANS_END_INTR_WAIT,
+  };
+
 ```
+
+#### Perform validation, loading and launching
+
+Once again, only two steps! Time to perform the __validation__ of the transaction, __load__ the parameters, and __launch__ of it. 
+Let's put these calls inside a dedicated function, called *run_dma_2d_transp_trans()* and launch it in the *main()*. Finally, let's add a simple for loop to print out the result, i.e. the extracted matrix.
+
+``` C
+
+dma_config_flags_t run_dma_2d_transp_trans(dma_trans_t *trans)
+{
+  dma_config_flags_t res;
   
-The transaction can then be loaded into the DMA registers by calling the load function
-```C
-res = dma_load_transaction( &trans );
-```
+  res = dma_validate_transaction(trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_load_transaction(trans);
+  res |= dma_launch(trans);
+
+  return res;
+} 
+
+...
+
+int main()
+{
+  dma_init(NULL);
   
-and launched
-```C
-res = dma_load_transaction( &trans );
-```
+  dma_config_flags_t result = run_dma_2d_transp_trans(&trans);
+
+  if (result != 0)
+  {
+    printf("Error! 2D DMA transaction failed with code: %d\n", result);
+    return 1;
+  } else {
+    printf("Success!\n");
+    
+    for (int i=0; i<SIZE_EXTR_D2; i++){
+      for (int j=0; j<SIZE_EXTR_D1; j++){
+        printf("%x ", dst[i * SIZE_EXTR_D1 + j]);
+      }
+      printf("\n\r");
+    }
+
+    return 0;
+  }
+
   
-Because the DMA will raise an interrupt as soon as it has sent all of its information, it is recommended to wait for the SPI interrupt.
-```C
-while( spi_intr_flag == 0 ) {
-	wait_for_interrupt();
 }
+    
 ```
-  
-If something is to be done as soon as the DMA finishes (like preparing a new transaction) it can be triggered by the interrupt attention routine:
+
+#### Non-square matrix transposition
+
+Working with a square matrix is straightforward, but how could the DMA be leveraged to extract a non-square matrix and transpose it on the fly?
+
+Let's revise the current example. With non-square matrices, the increment changes. The 1D increment will be equal to the stride on d1, which, in this example, is 1.
+The 2D increment, on the other hand, is the number of elements along the d2 axis that the source read pointer must "jump" to move to the next column, starting from the header. A special register called *trsp_src_ptr_reg* holds the position of the first element of a given column within the array. Once a column has been copied, this pointer is increased by the 2D increment, which must be equal to the 2D size of the input, multiplied by the 2D input stride. 
+
 ```C
-void  dma_intr_handler_trans_done() {
-// Raise a flag to trigger an action
-}
+
+  #define SIZE_IN_D1 4
+  #define SIZE_IN_D2 4
+  #define SIZE_EXTR_D1 3
+  #define SIZE_EXTR_D2 2
+  #define SRC_INC_D2 = SIZE_IN_D1
+  #define DST_INC_D2 = 1
+
+  uint16_t src[SIZE_IN_D1*SIZE_IN_D2] = {
+    0x1234, 0x7654, 0xfedc, 0xffff,
+    0x5912, 0xabcd, 0xcdef, 0xfafa,
+    0x579a, 0x657d, 0x758e, 0xabba,
+    0xa1a1, 0xc3c3, 0xb2b2, 0xf4f4
+    };
+  uint16_t dst[SIZE_EXTR_D1*SIZE_EXTR_D2];
+
+  dma_target_t tgt_src = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .inc_d2_du = SRC_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst = {
+    .ptr = (uint8_t *) dst,
+    .inc_d1_du = 1,
+    .inc_d2_du = DST_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans_2d = {
+    .src = &tgt_src,
+    .dst = &tgt_dst,
+    .src_addr = NULL,
+    .size_d1_du = SIZE_EXTR_D1,
+    .size_d2_du = SIZE_EXTR_D2,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .dim = DMA_DIM_CONF_2D,
+    .win_du = 0,
+    .dim_inv = 1; // This is the transposition flag!
+    .end = DMA_TRANS_END_INTR_WAIT,
+  };
+
 ```
-This function is a strong implementation defined in the application of the weak one in `dma.c`.
-  
-  
-During this transaction
-* The DMA grabbed the first byte of from the pointer (i.e. the second of the buffer, letter `B` in the chart below).
-* Sent it to the SPI, where it will be treated as a 32-bit word.
-* The flash stored the byte wherever it was configured to.
-* The source pointer was increased by two data units (i.e. two bytes) to point letter `D` from the chart.
-* The DMA grabbed that byte and sent it to the SPI.
-* The process went on until the the last byte (letter `L`) is sent to the SPI.
-  
-  
-<style  type="text/css">
-.tg {border-collapse:collapse;border-spacing:0;}
-.tg  td{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;
-overflow:hidden;padding:10px  5px;word-break:normal;}
-.tg  th{border-color:black;border-style:solid;border-width:1px;font-family:Arial, sans-serif;font-size:14px;
-font-weight:normal;overflow:hidden;padding:10px  5px;word-break:normal;}
-.tg  .tg-wp8o{border-color:#000000;text-align:center;vertical-align:top}
-</style>
-<table  class="tg">
-<thead>
-<tr>
-<td  class="tg-wp8o"  colspan="4">RAM</td>
-<td  class="tg-wp8o"  rowspan="5"></td>
-<td  class="tg-wp8o"  colspan="4">FLASH</td>
-</tr>
-<tr>
-<td  class="tg-wp8o">A</td>
-<td  class="tg-wp8o">B</td>
-<td  class="tg-wp8o">C</td>
-<td  class="tg-wp8o">D</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">B</td>
-</tr>
-<tr>
-<td  class="tg-wp8o">E</td>
-<td  class="tg-wp8o">F</td>
-<td  class="tg-wp8o">G</td>
-<td  class="tg-wp8o">H</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">D</td>
-</tr>
-<tr>
-<td  class="tg-wp8o">I</td>
-<td  class="tg-wp8o">J</td>
-<td  class="tg-wp8o">K</td>
-<td  class="tg-wp8o">L</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">0</td>
-<td  class="tg-wp8o">F</td>
-</tr>
-<tr>
-<td  class="tg-wp8o">.</td>
-<td  class="tg-wp8o">.</td>
-<td  class="tg-wp8o">.</td>
-<td  class="tg-wp8o">.</td>
-<td  class="tg-wp8o">.</td>
-<td  class="tg-wp8o">.</td>
-<td  class="tg-wp8o">.</td>
-<td  class="tg-wp8o">.</td>
-</tr>
-</thead>
-</table>
-  
-  
----
-  
-  
-For the second part of this example, the targets will be modified and their role switched.
-  
-The source of the data will be a peripheral connected to the SPI, which will be continuously sending information in half-word format, in streams of 4096 bytes (2048 half-words). Every 1024 half-words there should be a `MILESTONE-CHARACTER`, if there is not, the data flow should be stopped.
-  
+
+The rest of the code remains unchanged w.r.t. the square matrix example.
+
+<br>
+
+### 6. Matrix zero padding
+
+The goal of this example is to develop a function that extracts a submatrix from a source matrix, applies zero padding on it and copies it to a destination matrix.
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+Once again, the first step is to define the source and destination target structs, as well as the transaction structs.
+
+Let's use the same formula as in example 2 to extract a 2x2 matrix from a 4x4 source matrix. So in this case too, the source 2D increment will be 3 data units, while the destination increment will be 1.
+
+As thoroughly explained in [the functional description](#zero-padding), the padding is performed on the fly but is conceptually applied to the extracted matrix, not to the entire input matrix. In this example, a right padding of 1 and a top padding of 2 will be applied. Since the padding modifies the size of the output, the output dimensions will need to be adjusted accordingly. The formula used are the same used in `example_dma_2d`.
+
 ```C
-tgt2.ptr = spi_peripheral_fifo_rx;
-tgt2.size_du = 2048;
-tgt2.type = DMA_DATA_TYPE_HALF_WORD;
-tgt2.trig = DMA_TRIG_SLOT_SPI_RX;
+
+  #define SIZE_IN_D1 4
+  #define SIZE_IN_D2 4
+  #define SIZE_EXTR_D1 2
+  #define SIZE_EXTR_D2 2
+  #define TOP_PAD 2
+  #define RIGHT_PAD 1
+  #define LEFT_PAD 0
+  #define RIGHT_PAD 0
+    
+  #define OUT_D1_PAD ( SIZE_EXTR_D1 + LEFT_PAD + RIGHT_PAD )
+  #define OUT_D2_PAD ( SIZE_EXTR_D2 + TOP_PAD + BOTTOM_PAD )
+  #define OUT_DIM_1D ( OUT_D1_PAD  )
+  #define OUT_DIM_2D ( OUT_D1_PAD * OUT_D2_PAD )
+
+  #define SRC_INC_D2 = SIZE_IN_D1 - (SIZE_EXTR_D1 - 1)
+  #define DST_INC_D2 = 1
+
+  uint16_t src[SIZE_IN_D1*SIZE_IN_D2] = {
+    0x1234, 0x7654, 0xfedc, 0xffff,
+    0x5912, 0xabcd, 0xcdef, 0xfafa,
+    0x579a, 0x657d, 0x758e, 0xabba,
+    0xa1a1, 0xc3c3, 0xb2b2, 0xf4f4
+    };
+  uint16_t dst[OUT_DIM_1D*OUT_DIM_2D];
+
+  dma_target_t tgt_src = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .inc_d2_du = SRC_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst = {
+    .ptr = (uint8_t *) dst,
+    .inc_d1_du = 1,
+    .inc_d2_du = DST_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans_2d = {
+    .src = &tgt_src,
+    .dst = &tgt_dst,
+    .src_addr = NULL,
+    .size_d1_du = SIZE_EXTR_D1,
+    .size_d2_du = SIZE_EXTR_D2,
+    .pad_top_du     = TOP_PAD,
+    .pad_bottom_du  = BOTTOM_PAD,
+    .pad_left_du    = LEFT_PAD,
+    .pad_right_du   = RIGHT_PAD,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .dim = DMA_DIM_CONF_2D,
+    .end = DMA_TRANS_END_INTR_WAIT,
+  };
+
 ```
+
+#### Perform validation, loading and launching
+
+Once again, only two steps! Time to perform the __validation__ of the transaction, __load__ the parameters, and __launch__ of it. 
+Let's put these calls inside a dedicated function, called *run_dma_2d_pad_trans()* and launch it in the *main()*. Finally, let's add a simple for loop to print out the result.
+
+``` C
+
+dma_config_flags_t run_dma_2d_pad_trans(dma_trans_t *trans)
+{
+  dma_config_flags_t res;
   
-The source pointer is set to the reception FIFO of the SPI, and the appropriate slot is chosen.
-The increment is kept in zero.
+  res = dma_validate_transaction(trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_load_transaction(trans);
+  res |= dma_launch(trans);
+
+  return res;
+} 
+
+...
+
+int main()
+{
+  dma_init(NULL);
   
-The destination pointer will be given by a function.
+  dma_config_flags_t result = run_dma_2d_pad_trans(&trans);
+
+  if (result != 0)
+  {
+    printf("Error! 2D DMA transaction failed with code: %d\n", result);
+    return 1;
+  } else {
+    printf("Success!\n");
+    
+    for (int i=0; i<OUT_DIM_2D; i++){
+      for (int j=0; j<OUT_DIM_1D; j++){
+        printf("%x ", dst[i * SIZE_EXTR_1D + j]);
+      }
+      printf("\n\r");
+    }
+
+    return 0;
+  }
   
-```C
-tgt1.ptr = (uint8_t*) myApp_getDestination();
+}
+
 ```
-  
-To guarantee that the result of this function will not cause the DMA to write in undesired regions of memory, an environment can be created.
-It requires two pointers to the first and last byte where the DMA will be authorized to make any action.
+
+### 7. Multichannel mem2mem transaction, focus on the IRQ handler
+
+The goal of this example is to develop a function that extracts two submatrices from a source matrix at the same time and copies it to two destination matrices.
+
+> :warning: Make sure to configure X-Heep to have at least two DMA channels!
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+Just like in previous examples, the first step is to define the source and destination target structs, as well as the transaction structs.
+
+Using the same formula as in example 2 to extract a 2x2 matrix from a 4x4 source matrix, the source 2D increment will be 3 data units, while the destination increment will be 1.
+
+Let's use the DMA CH0 to copy the {0x1234, 0x7654, 0x5912, 0xabcd} 2x2 matrix and the DMA CH1 to copy the {0x758e, 0xabba, 0xb2b2, 0xf4f4} matrix. These channels will copy the extracted matrices to two different destinations, *dst_ch0* and *dst_ch1*. Each transaction struct should have its _.ch_ field set accordingly.
+
+Finally, let's set the end event to *DMA_TRANS_END_INTR* to handle manually the interrupt event.
+
 ```C
-static  dma_env_t safe_zone = {
-				.start = ADDRESS_START_OF_SAFE_ZONE,
-				.end = ADDRESS_END_OF_SAFE_ZONE,
-};
+
+  #define SIZE_IN_D1 4
+  #define SIZE_IN_D2 4
+  #define SIZE_EXTR_D1 2
+  #define SIZE_EXTR_D2 2
+  #define SRC_INC_D2 = SIZE_IN_D1 - (SIZE_EXTR_D1 - 1)
+  #define DST_INC_D2 = 1
+
+  uint16_t src[SIZE_IN_D1*SIZE_IN_D2] = {
+    0x1234, 0x7654, 0xfedc, 0xffff,
+    0x5912, 0xabcd, 0xcdef, 0xfafa,
+    0x579a, 0x657d, 0x758e, 0xabba,
+    0xa1a1, 0xc3c3, 0xb2b2, 0xf4f4
+    };
+  uint16_t dst_ch0[SIZE_EXTR_D1*SIZE_EXTR_D2], dst_ch1[SIZE_EXTR_D1*SIZE_EXTR_D2];
+
+  dma_target_t tgt_src_ch0 = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .inc_d2_du = SRC_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_src_ch1 = {
+    .ptr = (uint8_t *) &src[10], // This is the address of the "0x758e" element
+    .inc_d1_du = 1,
+    .inc_d2_du = SRC_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst_ch0 = {
+    .ptr = (uint8_t *) dst_ch0,
+    .inc_d1_du = 1,
+    .inc_d2_du = DST_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_target_t tgt_dst_ch1 = {
+    .ptr = (uint8_t *) dst_ch1,
+    .inc_d1_du = 1,
+    .inc_d2_du = DST_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans_2d_ch0 = {
+    .src = &tgt_src,
+    .dst = &tgt_dst_ch0,
+    .src_addr = NULL,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .dim = DMA_DIM_CONF_2D,
+    .size_d1_du = SIZE_EXTR_D1,
+    .size_d2_du = SIZE_EXTR_D2,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .end = DMA_TRANS_END_INTR,
+    .ch = 0 // This flag specifies the channel used to run the transaction!
+  };
+
+  dma_trans_t trans_2d_ch1 = {
+    .src = &tgt_src,
+    .dst = &tgt_dst_ch1,
+    .src_addr = NULL,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .dim = DMA_DIM_CONF_2D,
+    .size_d1_du = SIZE_EXTR_D1,
+    .size_d2_du = SIZE_EXTR_D2,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .end = DMA_TRANS_END_INTR,
+    .ch = 1 // This flag specifies the channel used to run the transaction!
+  };
+
 ```
-  
-The environment can be assigned to the target.
+
+#### IRQ handler
+
+Due to hardware limitations, there is just a **single fast interrupt** line dedicated to the DMA subsystem. In order to identify which channel raised the interrupt line, the DMA HAL performs a check on the IFR of each channel.
+As soon as an IFR is read high, the HAL calls a weak implementation of the interrupt handler, called **dma_intr_handler_trans_done()** and it passed the channel ID.
+After the call, the loop continues to look for interrupts in other channels, and then returns.
+
+There is, however, an **additional level of customization** provided by the HAL. 
+It's possible to set an index to differentiate between low and high priority channels by setting *DMA_HP_INTR_INDEX* in `dma.h`. In other words, when a channel whose ID is lower or equal to that index raises an interrupt, the *handler_irq_dma()* calls the user-defined IRQ handler and then returns, instead of compleating the loop.
+This means that low ID channels, i.e. high priority channels, have a higher probability of being serviced that the rest of the channels.
+
+However, this feature could cause low priority channels to never be serviced if the high priority interrupts are raised at a faster frequency and the user-defined handler executes long and complex operations.
+
+There are two solutions to this problem:
+- Use the **universal good design practice** of minimizing the tasks to perform in the IRQ handler.
+- Set *DMA_NUM_HP_INTR* to limit the number of consecutive IRQ handler calls that high priority channels can make without checking for low priority interrupts.
+
+This mechanism is reported from `dma.c` here below:
+
 ```C
-tgt1.env = &safe_zone;
-tgt1.inc_du = 1;
+
+void fic_irq_dma(void)
+{
+    /* 
+     * Find out which channel raised the interrupt and call
+     * either the weak implementation provided in this module,
+     * or the non-weak implementation.
+     */
+    
+    for (int i = 0; i < DMA_CH_NUM; i++)
+    {
+        if (dma_subsys_per[i].peri->TRANSACTION_IFR == 1)
+        {
+            dma_subsys_per[i].intrFlag = 1;
+            dma_intr_handler_trans_done(i);
+
+            #ifdef DMA_HP_INTR_INDEX
+            /* 
+             * If the channel that raised the interrupt is among the high priority channels,
+             * return to break the loop. 
+             */
+
+            #ifdef DMA_NUM_HP_INTR
+
+            if (i <= DMA_HP_INTR_INDEX && dma_hp_tr_intr_counter < DMA_NUM_HP_INTR)
+            {
+                dma_hp_tr_intr_counter++;
+                return;
+            }
+            else if (i > DMA_HP_INTR_INDEX)
+            {
+                dma_hp_tr_intr_counter = 0;
+            }
+
+            #else
+
+            if (i <= DMA_HP_INTR_INDEX)
+            {
+                return;
+            }
+            #endif
+
+            #endif
+        }
+    }
+    return;
+}
+
 ```
-  
-Size and data type is up to the source, and the rest of the configurations are inherited from the last transaction.
-  
-The transaction is conformed as:
-```C
-window_size_du = 1024;
-  
-trans.src = &tgt2;
-trans.dst = &tgt1;
-trans.mode = DMA_TRANS_MODE_CIRCULAR;
-trans.win_du = window_size_du;
-  
+
+Everything that has been explained in this paragraph is true for the **window count interrupts** too.
+
+In this example, none of these additional functionalities are necessary, as the IRQ handler will be used to simply set a flag. 
+A detailed explaination of how these mechanisms work was still necessary, since they are very useful in a variety of applications.
+
+Let's redefine *dma_intr_handler_trans_done()* to set some flags:
+
+``` C
+char intr_ch0_flag = 0;
+char intr_ch1_flag = 0;
+
+/* Strong transaction ISR implementation */
+void dma_intr_handler_trans_done(uint8_t channel)
+{
+    if (channel == 0){
+      intr_ch0_flag = 1;
+    } else {
+      intr_ch1_flag = 1;
+    }
+    return;
+}
+
 ```
-  
-Meaning that the information will start to flow into the target 1 from target 2, and every 1024 half-words transferred the application will get an interrupt to check if the `MILESTONE_SYMBOL` is present. Upon finishing the transaction, it shall start again to refill the buffer as it was set in `CIRCULAR_MODE`.
-  
-The amount of times the buffer was filled will be updated on every _transaction done_ interrupt.
-```C
-void  dma_intr_handler_trans_done() {
-	transaction_count++;
+
+#### Perform validation, loading and launching
+
+Once again, only two steps! Time to perform the __validation__ of the transaction, __load__ the parameters, and __launch__ of it. 
+Let's put these calls inside a dedicated function, called *run_dma_2d_multi_trans()* and launch it in the *main()*. Finally, let's add a simple for loop to print out the result and to check on the interrupt flags.
+
+Last but not least, **wait for CH1** to finish its transaction and raise the interrupt. Since both transactions has identical size there is no risk of the first one finishing before the other, so it's safe to assume that CH1 will be the last to terminate.
+
+``` C
+
+dma_config_flags_t run_dma_2d_multi_trans(dma_trans_t *trans_ch0, dma_trans_t *trans_ch1)
+{
+  dma_config_flags_t res;
+  
+  res = dma_validate_transaction(trans_ch0, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_validate_transaction(trans_ch1, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_load_transaction(trans_ch0);
+  res |= dma_load_transaction(trans_ch1);
+  res |= dma_launch(trans_ch0);
+  res |= dma_launch(trans_ch1);
+
+  return res;
+} 
+
+...
+
+int main()
+{
+  dma_init(NULL);
+
+  dma_config_flags_t result = run_dma_2d_multi_trans(&trans);
+
+  // Wait for CH1 to finish
+  while (!dma_is_ready(1))                   
+    {                                         
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8); 
+        if (dma_is_ready(1) == 0)              
+        {                                     
+            wait_for_interrupt();             
+        }                                     
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);   
+    }
+
+  if (result != 0)
+  {
+    printf("Error! 2D DMA transaction failed with code: %d\n", result);
+    return 1;
+  } else {
+    printf("Success!\n");
+    
+    printf("Output CH0:\n\r");
+    for (int i=0; i<SIZE_EXTR_D2; i++){
+      for (int j=0; j<SIZE_EXTR_D1; j++){
+        printf("%x ", dst_ch0[i * SIZE_EXTR_D1 + j]);
+      }
+      printf("\n\r");
+    }
+    
+    printf("\n\r");
+
+    printf("Output CH1:\n\r");
+    for (int i=0; i<SIZE_EXTR_D2; i++){
+      for (int j=0; j<SIZE_EXTR_D1; j++){
+        printf("%x ", dst_ch1[i * SIZE_EXTR_D1 + j]);
+      }
+      printf("\n\r");
+    }
+
+    printf("IF:\n\rCH0: %d - CH1: %d\n\r", intr_ch0_flag, intr_ch1_flag);
+
+    return 0;
+  }
 }
+
 ```
-  
-The search for the `MILESTONE_SYMBOL` can be done inside the _window done_ interrupt handling.
+
+<br>
+
+### 8. Multichannel flash2mem transaction using the SPI FLASH
+
+The goal of this example is to develop a function that performs:
+- A matrix extraction from a source matrix stored in the FLASH
+- A matrix extraction from a source matrix stored in the RAM
+These operations are performed using CH0 and CH1 in parallel.
+
+> :warning: This example can be executed only on QuestaSim or FPGA targets with the appropriate compilation flags.
+Checkout the SPI documentation or `example_dma_multichannel` for additional information.
+
+> :warning: Make sure to configure X-Heep to have at least two DMA channels! 
+
+Let's start!
+
+#### Setting targets & transaction structs
+
+Just like in previous examples, the first step is to define the source and destination target structs, as well as the transaction structs. This time we only need to set up the CH1 transaction, as for the 
+
+Most of this example is similar to the previous one, but particular care is required for the setup of FLASH stored data. In x-Heep, this is achieved by using the directive:
+
+<p style="text-align: center;"><code>__attribute__((section(".xheep_data_flash_only")))</code></p>
+
 ```C
-void  dma_intr_handler_window_done() {
-	/* The current window is obtained. The count is zero when no windows have yet been written. When it is set to one, the window zero is ready. */
-	window_count = dma_get_window_count() -1;
-	/* The pointer to the symbol is obtained from the destination pointer + the amount of half-words that have been written. this assumes the symbol is on the first element of each chunk.*/
-	address = (uint16_t *)trans.dst->ptr + window_count*window_size_du;
-	symbol = *address;
-	if( symbol != MILESTONE_SYMBOL ){
-		/* If the symbol was not the expected one, future transactions should not be carried out.*/
-		dma_stop_circular();
-		/* The number of the first window with error is saved to analyze it later.*/
-		error_window = error_window == 0 ? window_count : error_window;
-	}
-}
+
+  #define SIZE_IN_D1 4
+  #define SIZE_IN_D2 4
+  #define SIZE_EXTR_D1 2
+  #define SIZE_EXTR_D2 2
+  #define SRC_INC_D2 = SIZE_IN_D1 - (SIZE_EXTR_D1 - 1)
+  #define DST_INC_D2 = 1
+
+  uint16_t __attribute__((section(".xheep_data_flash_only"))) src_flash[SIZE_IN_D1*SIZE_IN_D2] = {
+    0x1234, 0x7654, 0xfedc, 0xffff,
+    0x5912, 0xabcd, 0xcdef, 0xfafa,
+    0x579a, 0x657d, 0x758e, 0xabba,
+    0xa1a1, 0xc3c3, 0xb2b2, 0xf4f4
+    };
+
+  uint16_t src[SIZE_IN_D1*SIZE_IN_D2] = {
+    0x1111, 0x2222, 0x3333, 0xfccf,
+    0x4444, 0x5555, 0x6666, 0xfbba,
+    0x7777, 0x8888, 0x9999, 0xadda,
+    0x1010, 0x1212, 0x4142, 0xfca4
+    };
+
+  uint16_t dst_ch0[SIZE_EXTR_D1*SIZE_EXTR_D2], dst_ch1[SIZE_EXTR_D1*SIZE_EXTR_D2];
+
+  dma_target_t tgt_src_ch1 = {
+    .ptr = (uint8_t *) src,
+    .inc_d1_du = 1,
+    .inc_d2_du = SRC_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,   
+  };
+
+  dma_target_t tgt_dst_ch1 = {
+    .ptr = (uint8_t *) dst_ch1,
+    .inc_d1_du = 1,
+    .inc_d2_du = DST_INC_D2,
+    .type = DMA_DATA_TYPE_HALF_WORD,
+    .trig = DMA_TRIG_MEMORY,    
+  };
+
+  dma_trans_t trans_2d_ch1 = {
+    .src = &tgt_src,
+    .dst = &tgt_dst_ch1,
+    .src_addr = NULL,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .dim = DMA_DIM_CONF_2D,
+    .size_d1_du = SIZE_EXTR_D1,
+    .size_d2_du = SIZE_EXTR_D2,
+    .mode = DMA_TRANS_MODE_SINGLE,
+    .win_du = 0,
+    .end = DMA_TRANS_END_INTR,
+    .ch = 1 // This flag specifies the channel used to run the transaction!
+  };
+
 ```
-> :warning: Interrupt attention routines are advised to be kept as short as possible. This example is merely illustrative.
-  
-Once the `dma_stop_circular()` function is called, the DMA will still finish the transaction it is currently executing (which could be a whole transaction if the faulty window was the last one). It is important to save valuable information that might be overridden by the ongoing transaction (like the faulty window number).
-  
-  
-## Testing
-This section will describe the available example application in X-HEEP using the DMA, and will outline the testing that needs to be performed in order to validate its proper operation.
-  
-  
-### Available Applications
-  
-There are 6 applications using the DMA:
-*  `dma_example`: Tests memory-to-memory transfer, the blocking of transactions while another one is in progress, and window interrupts.
-*  `example_external_peripheral`: Tests the use of the DMA HAL one a DMA instance external to X-HEEP. Only available for simulation.
-*  `example_virtual_flash`: Tests the transfer to/from an external flash through the DMA.
-*  `spi_flash_write`: Tests the transfer to/from the flash. Tests circular mode. Not available on FPGA if linker is `flash-exec`. Should be used with `mcu gen BUS=NtoM CPU=cv32e40p` to test circular mode.
-*  `spi_host_dma_exampe`: Test the transfer of data through the SPI host. Not available on Verilator.
-*  `spi_host_dma_power_gate_example`: Test the transfer of data through the SPI host. Not available on Verilator.
-  
-  
-## 😎 X-pert Zone:
-  
-If you know what you are doing and want to minimize the overhead of using the DMA, you can try by-passing the HAL and writing directly on the configuration registers.
-  
-```c
-/* We will copy a set of 25 half-words of 16 bits into a buffer of 32-bit words.
-Each word in the destination buffer will have its 16 MSB set to 0, and the 16 LSB with the corresponding value from the source.*/
-#define HALF_WORDS_TO_COPY 25
-static  uint16_t  src_buffer[HALF_WORDS_TO_COPY]; // The source buffer
-static  uint32_t  dst_buffer[HALF_WORDS_TO_COPY]; // The destination buffer
-  
-/* Set the DMA's control block's peripheral structure to point to the address defined in core_v_mini_mcu.h */
-dma_cb.peri = dma_peri;
-/* Activate interrupts*/
-dma_cb.peri->INTERRUPT_EN |= INTR_EN_TRANS_DONE;
-/* Set the source and destination pointers*/
-dma_cb.peri->SRC_PTR = (uint16_t*) source_buffer;
-dma_cb.peri->DST_PTR = (uint32_t*) dst_buffer;
-  
-/* Set the source increment as 2 bytes (because the source buffer is uint16_t).
-Set the destination increment as 4 bytes (because the destination buffer is uint32_t).
-We write 1026 = 0000 0100 0000 0010,
-as the first 8 LSB refer to the source, and the next 8 bits for the destination. */
-dma_cb.peri->PTR_INC = (uint32_t) 1026;
-  
-/* Make sure that the DMA will point to memory.*/
-dma_cb.peri->SLOT = DMA_TRIG_MEMORY;
-  
-/* Set the data transfer type as half-words.*/
-dma_cb.peri->TYPE = DMA_DATA_TYPE_HALF_WORD;
-  
-/* Set the transaction size, this will launch the transaction.
-If you want to restart the same transaction again, just run from here.*/
-dma_cb.peri->SIZE = HALF_WORDS_TO_COPY;
-  
-/* Go to sleep until the DMA finishes.*/
-while( dma_cb.peri->STATUS == 0 ) {
-	/* Disable the interrupts MSTATUS to avoid going to sleep AFTER the interrupt
-	was triggered.*/
-	CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-	/* If the transaction has not yet finished, go to sleep*/
-	if (dma_cb.peri->STATUS == 0) {
-		/* If a interrupt happened before, the core would still wake-up,
-		but will not jump to the interrupt handler MSTATUS is not re-set. */
-		{ asm  volatile("wfi"); }
-	}
-	/* Restore the interrupts. */
-	CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+#### Set up of the SPI FLASH
+
+There are just a few step to follow to correctly set up the SPI for the FLASH transaction.
+
+The first step is the initialization of the *soc_ctrl*, followed by the pick of the correct SPI device, based on the target, and the bridge set up.
+
+> :warning: Remember to use *flash_load* when compiling the software!
+
+```C
+void SPI_setup(){
+
+  soc_ctrl_t soc_ctrl;
+  soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
+
+  /* Pick the correct spi device based on simulation type */
+  spi_host_t *spi;
+
+  #ifndef USE_SPI_FLASH
+  spi = spi_host1;
+  #else
+  spi = spi_flash;
+  #endif
+
+  /* Init SPI host and SPI<->Flash bridge parameters */
+  if (w25q128jw_init(spi) != FLASH_OK)
+  {
+      PRINTF("Error initializing the flash SPI\n\r");
+      return EXIT_FAILURE;
+  }
 }
-  
-  
 ```
+
+#### Perform validation, loading and launching
+
+Once the SPI has been set up, the next step it's time to perform the __validation__ of the transaction, __load__ the parameters, and __launch__ of it. 
+
+As for the SPI, there is a function defined in `w25q.c` that simplifies the operation:
+
+<p style="text-align: center;"><code>w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_init_dma, uint8_t no_sanity_checks)</code></p>
+
+
+The flags *no_wait_init_dma* and *no_sanity_checks* are necessary for running the application, as they prevent the DMA from being reset or using a blocking wait for its interrupt. However, the function is quite handy since it takes care of everything else.
+Note that the *w25q128jw_read_standard_dma()* uses **CH0**!
+
+**Suggestion:** To further understand how to interface the DMA with the SPI, study the functions in `w25q.c` that employ it.
+
+As usual, let's put these calls inside a dedicated function, called *run_dma_2d_spi_trans()* and launch it in the *main()*. Finally, let's add a simple for loop to print out the result and to check on the interrupt flags.
+
+Last but not least, **wait for CH0** to finish its transaction and raise the interrupt, since the SPI will always be slower than a standard DMA transaction of equal size.
+
+``` C
+
+dma_config_flags_t run_dma_2d_spi_trans(dma_trans_t *trans_ch0, dma_trans_t *trans_ch1)
+{
+  dma_config_flags_t res;
+  
+  res |= dma_validate_transaction(trans_ch1, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+  res |= dma_load_transaction(trans_ch1);
+  res |= dma_launch(trans_ch1);
+
+  return res;
+} 
+
+...
+
+int main()
+{
+  dma_init(NULL);
+
+  dma_config_flags_t result = run_dma_2d_multi_trans(&trans);
+
+  /* Start the reading process from the SPI, avoiding both sanity checks and waiting for the DMA to finish */
+  w25q_error_codes_t status = w25q128jw_read_standard_dma(TEST_DATA_FLASH_PTR, copied_test_data_flash, TEST_DATA_FLASH_SIZE*4, 1, 1);
+  if (status != FLASH_OK)
+  {
+      PRINTF("Error reading from flash\n\r");
+      return EXIT_FAILURE;
+  }
+
+  // Wait for CH1 to finish
+  while (!dma_is_ready(1))                   
+    {                                         
+        CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8); 
+        if (dma_is_ready(1) == 0)              
+        {                                     
+            wait_for_interrupt();             
+        }                                     
+        CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);   
+    }
+
+  if (result != 0)
+  {
+    printf("Error! 2D DMA transaction failed with code: %d\n", result);
+    return 1;
+  } else {
+    printf("Success!\n");
+    
+    printf("Output CH0:\n\r");
+    for (int i=0; i<SIZE_EXTR_D2; i++){
+      for (int j=0; j<SIZE_EXTR_D1; j++){
+        printf("%x ", dst_ch0[i * SIZE_EXTR_D1 + j]);
+      }
+      printf("\n\r");
+    }
+    
+    printf("\n\r");
+
+    printf("Output CH1:\n\r");
+    for (int i=0; i<SIZE_EXTR_D2; i++){
+      for (int j=0; j<SIZE_EXTR_D1; j++){
+        printf("%x ", dst_ch1[i * SIZE_EXTR_D1 + j]);
+      }
+      printf("\n\r");
+    }
+
+    return 0;
+  }
+}
+
+```
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/Verification/VerifHEEP.md b/hw/vendor/esl_epfl_x_heep/docs/source/Verification/VerifHEEP.md
new file mode 100644
index 00000000..13ffd94e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/docs/source/Verification/VerifHEEP.md
@@ -0,0 +1,186 @@
+# VerifHeep
+
+## Introduction
+
+**VerifHeep** is a Python library designed to provide various methods for implementing a verification and testing environment tailored specifically for X-Heep.
+
+In particular, VerifHeep enables **on FPGA** verification, testing and performance estimation, offering a tenfold speed improvement compared to traditional simulation tools like Verilator or QuestaSim. 
+This library employs a _software-based_ verification approach, meaning it conducts its tests by compiling a specific software application, running it on the target unit, and analyzing the results. The user is required to develop an application that can test and verify the target unit and display the data in accordance with specific formats.
+
+This library has been developed with a focus on verifying and characterizing external accelerators, such as the _im2col Smart Peripheral Controller_ (SPC). 
+In fact, the `scripts/examples` folder contains the verification environment for this very accelerator, `im2col_spc_verification.py`, along with `im2col_spc_plotter.py` to plot the acquired data. 
+Users are encouraged to refer to this file as a real-world example of how to use the library and can use it as starting point to develop their own verification environment.
+
+> :warning: Make sure to follow the preliminary steps explained in `im2col_spc_verification.py` in order to test it!
+
+This guide aims to address any questions that might arise from studying the *im2col_spc* example. It provides a detailed explanation of each method in VerifHeep, along with the parameters required for its proper functioning.
+
+> :bulb: The FPGA synthesis must be performed with the **Xilinx scan chains** enabled, as these will be used to load the program. 
+Additionally, the EPFL programmer will be used for serial communication with the board. Without these two lines of communication, it would be impossible to load the program and read the serial stream.
+
+## Methods description
+
+#### <i> __init__ </i>
+
+_Purpose_:
+The initialization function is used to create the VerifHeep object. During this process, it's required to indicate the target of the verification and its directory. Furthermore, an optimization flag can be set when synthesis or simulation module building will be performed.
+
+_Parameters_:
+- **target**: Indicated the target of the verification environment, must be one of the following: 
+  - `pynq-z2`
+  - `questasim`
+  - `verilator`
+- **xheep_dir**: Sets the directory of the X-Heep project, necessary to run scripts.
+- **opt_en**: By default set to _false_, this flag indicates whether optimization should be performed when building the simulation model. Available **only** with QuestaSim!
+
+#### <i> compileModel </i>
+
+_Purpose_:
+This method is used to compile a simulation model for both Verilator and QuestaSim, i.e. run _make mcu-gen_, provided they are properly installed on the host system.
+
+_Parameters_:
+- **mem_banks**: By default set to 6, this flag indicates how many memory banks will be included in the X-Heep model. No interleaved banks are supported.
+- **cpu**: By default set to `cv32e40px`, this flags indicates which CPU will be included in the model.
+- **bus**: By default set to `1toN`, this flag indicates the bus type.
+
+#### <i> buildModel </i>
+
+_Purpose_:
+This method is used to either build a simulation model for Verilator or QuestaSim or to synthesize the project with Xilinx Vivado, provided they are properly installed on the host system.
+
+_Parameters_:
+- **mem_banks**: By default set to *6*, this flag indicates how many memory banks will be included. No interleaved banks are supported.
+- **cpu**: By default set to `cv32e40px`, this flags indicates which CPU will be included.
+- **bus**: By default set to `1toN`, this flag indicates the bus type.
+
+#### <i> serialBegin </i>
+
+_Purpose_:
+This method is used to set up the serial communication with the _pynq-z2_ FPGA board.
+
+> :bulb: **Tip:** Checkout which USB port is connected to the _pynq-z2_ by running a simple hello world (no flash load since the scan chains are used). 
+Set the USB port parameter of the verification environment as a global variable to quickly modify it. Its value might change!
+
+_Parameters_:
+- **port**: Indicates the USB port connected to the EPFL programmer for the pynq-z2.
+- **baudrate**: Indicates the connection speed, usually set to 9600.
+
+_Return value_:
+- **Outcome of the connection**, which is _False_ for unsuccessful.
+
+#### <i> setupDeb </i>
+
+_Purpose_:
+This method is used to set up the GDB debugger. It creates a process on which the debug communication will be run, thus making this function conveniently non-blocking. 
+
+> :warning: This method should obviously be called at the beginning of the verification process, but not only then! Empirical evidence suggests **resetting the debug connection** approximately **every 100 iterations** to ensure reliable operation.
+
+_Parameters_:
+None
+
+#### <i> stopDeb </i>
+
+_Purpose_:
+This method is used to close the debugger. Useful both at the end of a script or during the cyclical reset of the debug connection, as explained before. 
+
+_Parameters_:
+None
+
+#### <i> genInputDataset </i>
+
+_Purpose_:
+This method is used to generate random data that the application can use to perform verification. It's possible to set the range of the data, the dimension of the array, the datatype and its variable identifier. In addition, it's possible to obtain a single _.h_ file or both a _.c_ and a _.h_ file.
+
+_Parameters_:
+- **dataset_size**: Indicates the size of the input array to be generated.
+- **parameters**: This optional argument is a *dictionary* of parameters that might be useful for the application. It has *no impact on the value generation* but it will be written in the *.h* file.
+- **row_size**: By default set to *0*, this parameter is used to organize the array in the case of matrix generation. In other words, every *row_size* words, the matrix will have a new line. 
+- **range_min** / **range_max**: These are used to set the range of the random data. They can be both negative and float, if the datatype supports it.
+- **dataset_dir**: Indicates the directory in which the generated file will be saved, including the name of the file itself.
+- **dataset_dir_c**: By default *empty*, when set to a directory it forces the method to generate both a _.c_ and a _.h_, the first with the data definition and the second with its declaration.
+- **dataset_name**: Indicates the name of the dataset.
+- **datatype**: By default set to *uint32_t*, indicates the datatype of the array to be generated.
+
+#### <i> genGoldenResult </i>
+
+_Purpose_:
+This method is used to generate golden data from an input dataset, enabling applications to verify the functionality of a unit or accelerator. This feature is performed by a user-defined function, passed as a parameter, which processes the input data.
+
+Similar to input generation, users can specify the data range, array dimensions, data type, and variable identifier. Additionally, the output can be configured to produce either a single _.h_ file or both a _.c_ and a _.h_ file.
+
+_Parameters_:
+- **function**: This function is the one used by the method to generate the golden results.
+- **golden_size**: Indicates the size of the output array to be computed.
+- **parameters**:This optional argument is a *dictionary* of parameters that might be useful for the application. It has no impact on the golden result computation but it will be written in the *.h* file.
+- **row_size**: By default set to *0*, this parameter is used to organize the array in the case of matrix generation. In other words, every *row_size* words, the matrix will have a new line. 
+- **range_min** / **range_max**: These are used to set the range of the random data. They can be both negative and float, if the datatype supports it.
+- **golden_dir**: Indicates the directory in which the generated file will be saved, including the name of the file itself.
+- **golden_dir_c**: By default *empty*, when set to a directory it forces the method to generate both a _.c_ and a _.h_, the first with the data definition and the second with its declaration.
+- **input_dir**: Indicates the input data used to generate the golden result.
+- **golden_name**: Indicates the name of the golden result array.
+- **output_datatype**: By default set to *uint32_t*, indicates the datatype of the array to be computed.
+
+#### <i> modifyFile </i>
+
+_Purpose_:
+This method is simple yet very useful in particular situations. It allows the user to modify a row with a replacement of its choice. It can be used to modify _#define_ that could change the behaviour of the application.
+
+For example, the im2col SPC verification example makes use of this feature twice. The first time it modifies the format of the output of the application to be adherent to the verification procedure (which by default it is not).
+The second time it reduces the verification times, by avoiding to repeat unnecessary tests.
+
+_Parameters_:
+- **file_dir**: Indicates the directory of the file that the user wants to modify.
+- **pattern**: Indicates the pattern to look for in the file, using the library **re**.
+- **replacement**: Indicates the row that will be put in place instead of the pattern found.
+
+#### <i> chronoStart/chronoStop </i>
+
+_Purpose_:This method is used to track the execution time of an iteration and, by extension, to estimate the total execution time of the verification process.
+
+_Parameters_:
+None
+
+#### <i> chronoExecutionEst </i>
+
+_Purpose_:This method estimates the total execution time of the verification process, assuming the verification consists of a loop with N iterations. It requires that the `_chronoStart_` method is called at the beginning and the `_chronoStop_` method is called at the end of each iteration.
+
+_Parameters_:
+- **loop_size**: Size of the loop, i.e. number of iterations of the entire verification process. If it's composed of nested loops, the total number of iterations is obtained by multiplying the size of each loop.
+
+_Return value_:
+- **Remaining time**, a _dictionary_:
+  - _"hours"_
+  - _"minutes"_
+  - _"seconds"_
+
+#### <i> launchTest </i>
+
+_Purpose_:
+This method is crucial in the verification process, as it's in charge of compiling the application, loading it on the FPGA using the scan chains and GDB, waiting for the results and storing then in *self.results*.
+
+Its important to note that this method expects a **specific output format** from the application, which needs to be strictly respected otherwise the whole verification would be disrupted.
+By default, this is the format expected:
+
+<div style="text-align: center;">
+  <pre style="display: inline-block; text-align: center;"><code> test_id:cycles:outcome
+  ...
+  & </code></pre>
+</div>
+
+An application can send N lines composed of:
+- **test_id**: the ID of the test being performed. A single application can test multiple aspects or features, so different tests can be performed in a single run. In the **im2col_spc** application, this is exactly what happens: three different tests are perfomed each run.
+- **cycles**: the number of cycles needed by the system to perform that specific test. In order to keep track of the execution cycles, a `timer_sdk` has been developed. Please refer to `example_timer_sdk` for a practical implementation.
+- **outcome**: the outcome of the verification performed by the application itself. For example, the application might set up the DMA to perform a transaction and then check that the result corresponds to the golden result.
+
+Each of these fields can be **left blank** or with whatever ASCII character, but the format has to be followed nonetheless. For example, one could be interested only in verify its design, avoiding the performance estimation. In such case, _cycles_ could be always set to _0_.
+
+At the end of the run, the application **must send the end character** `&`.
+
+If needed, the format of the data sent by the application can be modified by changing the _pattern_ parameter.
+
+_Parameters_:
+- **example_name**: Name of the example folder in X-Heep sw/application. e.g. For the DMA verification, this field would have been *example_dma*.
+- **input_size**: This field will be appended to the data obtained by the simulation, not mandatory but might be useful for data processing.
+- **pattern**: By default set to *test_id:cycles:outcome*. It can be changed by the user, with **caution**.
+- **en_timeout_term**: By default set to _False_, if enabled it terminates the application in case that the board doesn't reply in time.
+
diff --git a/hw/vendor/esl_epfl_x_heep/docs/source/images/dma_structure.png b/hw/vendor/esl_epfl_x_heep/docs/source/images/dma_structure.png
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literal 0
HcmV?d00001

diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
index dd9246df..f054c37b 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
@@ -7,15 +7,20 @@ module ao_peripheral_subsystem
   import reg_pkg::*;
   import power_manager_pkg::*;
 #(
+    parameter AO_SPC_NUM = 0,
     //do not touch these parameters
+    parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
     parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
     parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT
 ) (
     input logic clk_i,
     input logic rst_ni,
 
-    input  obi_req_t  slave_req_i,
-    output obi_resp_t slave_resp_o,
+    input  reg_req_t slave_req_i,
+    output reg_rsp_t slave_resp_o,
+
+    input  reg_req_t [AO_SPC_NUM_RND-1:0] spc2ao_req_i,
+    output reg_rsp_t [AO_SPC_NUM_RND-1:0] ao2spc_resp_o,
 
     // SOC CTRL
     input  logic        boot_select_i,
@@ -62,14 +67,14 @@ module ao_peripheral_subsystem
     output logic rv_timer_1_intr_o,
 
     // DMA
-    output obi_req_t  dma_read_ch0_req_o,
-    input  obi_resp_t dma_read_ch0_resp_i,
-    output obi_req_t  dma_write_ch0_req_o,
-    input  obi_resp_t dma_write_ch0_resp_i,
-    output obi_req_t  dma_addr_ch0_req_o,
-    input  obi_resp_t dma_addr_ch0_resp_i,
-    output logic      dma_done_intr_o,
-    output logic      dma_window_intr_o,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_read_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_read_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_write_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_write_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_addr_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_addr_resp_i,
+    output logic                                                      dma_done_intr_o,
+    output logic                                                      dma_window_intr_o,
 
     // External PADs
     output reg_req_t pad_req_o,
@@ -104,21 +109,32 @@ module ao_peripheral_subsystem
     output reg_req_t ext_peripheral_slave_req_o,
     input  reg_rsp_t ext_peripheral_slave_resp_i,
 
-    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
-    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i,
+    // SPC interface
+    input  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
+    input  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i,
+    input  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
+    output logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_done_o
 
-    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i
 );
 
   import core_v_mini_mcu_pkg::*;
   import tlul_pkg::*;
-  import rv_plic_reg_pkg::*;
 
+  localparam DMA_GLOBAL_TRIGGER_SLOT_NUM = 5;
+  localparam DMA_EXT_TRIGGER_SLOT_NUM = core_v_mini_mcu_pkg::DMA_CH_NUM * 2;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* NOTE: Additional xbars signals defined in the xbar generate statement */
+
+  /* Peripheral register inteface */
   reg_pkg::reg_req_t peripheral_req;
   reg_pkg::reg_rsp_t peripheral_rsp;
-
   reg_pkg::reg_req_t [core_v_mini_mcu_pkg::AO_PERIPHERALS-1:0] ao_peripheral_slv_req;
   reg_pkg::reg_rsp_t [core_v_mini_mcu_pkg::AO_PERIPHERALS-1:0] ao_peripheral_slv_rsp;
+  logic [AO_PERIPHERALS_PORT_SEL_WIDTH-1:0] peripheral_select;
 
   tlul_pkg::tl_h2d_t rv_timer_tl_h2d;
   tlul_pkg::tl_d2h_t rv_timer_tl_d2h;
@@ -126,53 +142,71 @@ module ao_peripheral_subsystem
   tlul_pkg::tl_h2d_t uart_tl_h2d;
   tlul_pkg::tl_d2h_t uart_tl_d2h;
 
-  logic [AO_PERIPHERALS_PORT_SEL_WIDTH-1:0] peripheral_select;
-
+  /* SPI memory signals */
   logic use_spimemio;
-
   logic spi_flash_rx_valid;
   logic spi_flash_tx_ready;
 
+  /* GPIOs signals */
   logic [23:0] intr_gpio_unused;
   logic [23:0] cio_gpio_unused;
   logic [23:0] cio_gpio_en_unused;
 
+  /* DMA signals */
+  logic dma_clk_gate_en_n[core_v_mini_mcu_pkg::DMA_CH_NUM-1:0];
+  power_manager_out_t dma_subsystem_pwr_ctrl[core_v_mini_mcu_pkg::DMA_CH_NUM-1:0];
+  logic [DMA_GLOBAL_TRIGGER_SLOT_NUM-1:0] dma_global_trigger_slots;
+  logic [DMA_EXT_TRIGGER_SLOT_NUM-1:0] dma_ext_trigger_slots;
+  obi_pkg::obi_req_t slave_fifoout_req;
+  obi_pkg::obi_resp_t slave_fifoout_resp;
+  reg_req_t perconv2regdemux_req;
+  reg_rsp_t regdemux2perconv_resp;
+
+  /*_________________________________________________________________________________________________________________________________ */
 
-  obi_pkg::obi_req_t slave_fifo_req_sel;
-  obi_pkg::obi_resp_t slave_fifo_resp_sel;
+  /* Signal assignment */
 
+  /* Peripheral demuxed register interface */
   assign ext_peripheral_slave_req_o = ao_peripheral_slv_req[core_v_mini_mcu_pkg::EXT_PERIPHERAL_IDX];
   assign ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::EXT_PERIPHERAL_IDX] = ext_peripheral_slave_resp_i;
+  assign pad_req_o = ao_peripheral_slv_req[core_v_mini_mcu_pkg::PAD_CONTROL_IDX];
+  assign ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::PAD_CONTROL_IDX] = pad_resp_i;
 
-`ifdef REMOVE_OBI_FIFO
+  assign dma_global_trigger_slots[0] = spi_rx_valid_i;
+  assign dma_global_trigger_slots[1] = spi_tx_ready_i;
+  assign dma_global_trigger_slots[2] = spi_flash_rx_valid;
+  assign dma_global_trigger_slots[3] = spi_flash_tx_ready;
+  assign dma_global_trigger_slots[4] = i2s_rx_valid_i;
 
-  assign slave_fifo_req_sel = slave_req_i;
-  assign slave_resp_o       = slave_fifo_resp_sel;
+  generate
+    for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_CH_NUM; i++) begin : dma_trigger_slots_gen
+      assign dma_ext_trigger_slots[2*i]   = ext_dma_slot_tx_i[i];
+      assign dma_ext_trigger_slots[2*i+1] = ext_dma_slot_rx_i[i];
+    end
+  endgenerate
 
-`else
+  /* DMA clock gating */
+  generate
+    for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_CH_NUM; i++) begin : dma_clk_gate_gen
+      assign dma_clk_gate_en_n[i] = dma_subsystem_pwr_ctrl[i].clkgate_en_n;
+    end
+  endgenerate
 
-  obi_pkg::obi_req_t  slave_fifoin_req;
-  obi_pkg::obi_resp_t slave_fifoin_resp;
+  /*_________________________________________________________________________________________________________________________________ */
 
-  obi_pkg::obi_req_t  slave_fifoout_req;
-  obi_pkg::obi_resp_t slave_fifoout_resp;
+  /* Module instantiation */
 
+  /* System bus to AO OBI FIFO */
   obi_fifo obi_fifo_i (
       .clk_i,
       .rst_ni,
-      .producer_req_i (slave_fifoin_req),
-      .producer_resp_o(slave_fifoin_resp),
+      .producer_req_i (slave_req_i),
+      .producer_resp_o(slave_resp_o),
       .consumer_req_o (slave_fifoout_req),
       .consumer_resp_i(slave_fifoout_resp)
   );
 
-  assign slave_fifo_req_sel = slave_fifoout_req;
-  assign slave_fifoout_resp = slave_fifo_resp_sel;
-  assign slave_fifoin_req   = slave_req_i;
-  assign slave_resp_o       = slave_fifoin_resp;
-
-`endif
-
+  /* Peripheral to register interface converter*/
   periph_to_reg #(
       .req_t(reg_pkg::reg_req_t),
       .rsp_t(reg_pkg::reg_rsp_t),
@@ -180,28 +214,65 @@ module ao_peripheral_subsystem
   ) periph_to_reg_i (
       .clk_i,
       .rst_ni,
-      .req_i(slave_fifo_req_sel.req),
-      .add_i(slave_fifo_req_sel.addr),
-      .wen_i(~slave_fifo_req_sel.we),
-      .wdata_i(slave_fifo_req_sel.wdata),
-      .be_i(slave_fifo_req_sel.be),
+      .req_i(slave_fifoout_req.req),
+      .add_i(slave_fifoout_req.addr),
+      .wen_i(~slave_fifoout_req.we),
+      .wdata_i(slave_fifoout_req.wdata),
+      .be_i(slave_fifoout_req.be),
       .id_i('0),
-      .gnt_o(slave_fifo_resp_sel.gnt),
-      .r_rdata_o(slave_fifo_resp_sel.rdata),
+      .gnt_o(slave_fifoout_resp.gnt),
+      .r_rdata_o(slave_fifoout_resp.rdata),
       .r_opc_o(),
       .r_id_o(),
-      .r_valid_o(slave_fifo_resp_sel.rvalid),
+      .r_valid_o(slave_fifoout_resp.rvalid),
       .reg_req_o(peripheral_req),
       .reg_rsp_i(peripheral_rsp)
   );
 
+  /* SPC crossbar & FIFOs */
+  generate
+    if (AO_SPC_NUM_RND > 0) begin
+      /* Assign the bus port to the first input port of the AOPB */
+      reg_req_t [AO_SPC_NUM_RND:0] packet_req;
+      reg_rsp_t [AO_SPC_NUM_RND:0] packet_rsp;
+
+      assign packet_req[0]  = peripheral_req;
+      assign peripheral_rsp = packet_rsp[0];
+
+      for (genvar i = 0; i < AO_SPC_NUM_RND; i++) begin : gen_spc
+        assign packet_req[i+1]  = spc2ao_req_i[i];
+        assign ao2spc_resp_o[i] = packet_rsp[i+1];
+      end
+
+      reg_mux #(
+          .NoPorts(AO_SPC_NUM_RND + 1),
+          .req_t  (reg_pkg::reg_req_t),
+          .rsp_t  (reg_pkg::reg_rsp_t),
+          .AW     (32),
+          .DW     (32)
+      ) reg_mux_i (
+          .clk_i,
+          .rst_ni,
+          .in_req_i (packet_req),
+          .in_rsp_o (packet_rsp),
+          .out_req_o(perconv2regdemux_req),
+          .out_rsp_i(regdemux2perconv_resp)
+      );
+
+    end else begin
+      assign perconv2regdemux_req = peripheral_req;
+      assign peripheral_rsp = regdemux2perconv_resp;
+    end
+  endgenerate
+
+  /* Address decoder for the peripheral registers */
   addr_decode #(
       .NoIndices(core_v_mini_mcu_pkg::AO_PERIPHERALS),
       .NoRules(core_v_mini_mcu_pkg::AO_PERIPHERALS),
       .addr_t(logic [31:0]),
       .rule_t(addr_map_rule_pkg::addr_map_rule_t)
   ) i_addr_decode_soc_regbus_periph_xbar (
-      .addr_i(peripheral_req.addr),
+      .addr_i(perconv2regdemux_req.addr),
       .addr_map_i(core_v_mini_mcu_pkg::AO_PERIPHERALS_ADDR_RULES),
       .idx_o(peripheral_select),
       .dec_valid_o(),
@@ -210,6 +281,7 @@ module ao_peripheral_subsystem
       .default_idx_i('0)
   );
 
+  /* Register demux */
   reg_demux #(
       .NoPorts(core_v_mini_mcu_pkg::AO_PERIPHERALS),
       .req_t  (reg_pkg::reg_req_t),
@@ -218,8 +290,8 @@ module ao_peripheral_subsystem
       .clk_i,
       .rst_ni,
       .in_select_i(peripheral_select),
-      .in_req_i(peripheral_req),
-      .in_rsp_o(peripheral_rsp),
+      .in_req_i(perconv2regdemux_req),
+      .in_rsp_o(regdemux2perconv_resp),
       .out_req_o(ao_peripheral_slv_req),
       .out_rsp_i(ao_peripheral_slv_rsp)
   );
@@ -239,11 +311,13 @@ module ao_peripheral_subsystem
       .exit_value_o
   );
 
+  /* Boot ROM */
   boot_rom boot_rom_i (
       .reg_req_i(ao_peripheral_slv_req[core_v_mini_mcu_pkg::BOOTROM_IDX]),
       .reg_rsp_o(ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::BOOTROM_IDX])
   );
 
+  /* SPI subsystem */
   spi_subsystem spi_subsystem_i (
       .clk_i,
       .rst_ni,
@@ -267,6 +341,7 @@ module ao_peripheral_subsystem
       .spi_flash_tx_ready_o(spi_flash_tx_ready)
   );
 
+  /* Power manager */
   power_manager #(
       .reg_req_t(reg_pkg::reg_req_t),
       .reg_rsp_t(reg_pkg::reg_rsp_t)
@@ -285,7 +360,8 @@ module ao_peripheral_subsystem
       .cpu_subsystem_pwr_ctrl_i,
       .peripheral_subsystem_pwr_ctrl_i,
       .memory_subsystem_pwr_ctrl_i,
-      .external_subsystem_pwr_ctrl_i
+      .external_subsystem_pwr_ctrl_i,
+      .dma_subsystem_pwr_ctrl_o(dma_subsystem_pwr_ctrl)
   );
 
   reg_to_tlul #(
@@ -314,25 +390,6 @@ module ao_peripheral_subsystem
       .intr_timer_expired_1_0_o(rv_timer_1_intr_o)
   );
 
-  parameter DMA_GLOBAL_TRIGGER_SLOT_NUM = 5;
-  parameter DMA_EXT_TRIGGER_SLOT_NUM = core_v_mini_mcu_pkg::DMA_CH_NUM * 2;
-
-  logic [DMA_GLOBAL_TRIGGER_SLOT_NUM-1:0] dma_global_trigger_slots;
-  logic [DMA_EXT_TRIGGER_SLOT_NUM-1:0] dma_ext_trigger_slots;
-
-  assign dma_global_trigger_slots[0] = spi_rx_valid_i;
-  assign dma_global_trigger_slots[1] = spi_tx_ready_i;
-  assign dma_global_trigger_slots[2] = spi_flash_rx_valid;
-  assign dma_global_trigger_slots[3] = spi_flash_tx_ready;
-  assign dma_global_trigger_slots[4] = i2s_rx_valid_i;
-
-  generate
-    for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_CH_NUM; i++) begin : dma_trigger_slots_gen
-      assign dma_ext_trigger_slots[2*i]   = ext_dma_slot_tx_i[i];
-      assign dma_ext_trigger_slots[2*i+1] = ext_dma_slot_rx_i[i];
-    end
-  endgenerate
-
   dma_subsystem #(
       .reg_req_t(reg_pkg::reg_req_t),
       .reg_rsp_t(reg_pkg::reg_rsp_t),
@@ -343,24 +400,23 @@ module ao_peripheral_subsystem
   ) dma_subsystem_i (
       .clk_i,
       .rst_ni,
+      .clk_gate_en_ni(dma_clk_gate_en_n),
       .reg_req_i(ao_peripheral_slv_req[core_v_mini_mcu_pkg::DMA_IDX]),
       .reg_rsp_o(ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::DMA_IDX]),
-      .dma_read_ch0_req_o,
-      .dma_read_ch0_resp_i,
-      .dma_write_ch0_req_o,
-      .dma_write_ch0_resp_i,
-      .dma_addr_ch0_req_o,
-      .dma_addr_ch0_resp_i,
+      .dma_read_req_o,
+      .dma_read_resp_i,
+      .dma_write_req_o,
+      .dma_write_resp_i,
+      .dma_addr_req_o,
+      .dma_addr_resp_i,
       .global_trigger_slot_i(dma_global_trigger_slots),
       .ext_trigger_slot_i(dma_ext_trigger_slots),
       .ext_dma_stop_i(ext_dma_stop_i),
       .dma_done_intr_o(dma_done_intr_o),
-      .dma_window_intr_o(dma_window_intr_o)
+      .dma_window_intr_o(dma_window_intr_o),
+      .dma_done_o(dma_done_o)
   );
 
-  assign pad_req_o = ao_peripheral_slv_req[core_v_mini_mcu_pkg::PAD_CONTROL_IDX];
-  assign ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::PAD_CONTROL_IDX] = pad_resp_i;
-
   fast_intr_ctrl #(
       .reg_req_t(reg_pkg::reg_req_t),
       .reg_rsp_t(reg_pkg::reg_rsp_t)
@@ -373,6 +429,7 @@ module ao_peripheral_subsystem
       .fast_intr_o
   );
 
+  /* GPIO subsystem */
   gpio #(
       .reg_req_t(reg_pkg::reg_req_t),
       .reg_rsp_t(reg_pkg::reg_rsp_t)
@@ -406,6 +463,7 @@ module ao_peripheral_subsystem
       .reg_rsp_o(ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::UART_IDX])
   );
 
+  /* UART */
   uart uart_i (
       .clk_i,
       .rst_ni,
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
index 4cfb3d9d..3ebc1e77 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
@@ -11,8 +11,10 @@ module core_v_mini_mcu
     parameter ZFINX = 0,
     parameter EXT_XBAR_NMASTER = 0,
     parameter X_EXT = 0,  // eXtension interface in cv32e40x
+    parameter AO_SPC_NUM = 0,
     parameter EXT_HARTS = 0,
     //do not touch these parameters
+    parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
     parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
     parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
     parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT,
@@ -285,19 +287,22 @@ module core_v_mini_mcu
     input  obi_req_t  [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_req_i,
     output obi_resp_t [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_resp_o,
 
+    input  reg_req_t [AO_SPC_NUM_RND-1:0] ext_ao_peripheral_slave_req_i,
+    output reg_rsp_t [AO_SPC_NUM_RND-1:0] ext_ao_peripheral_slave_resp_o,
+
     // External slave ports
-    output obi_req_t  ext_core_instr_req_o,
-    input  obi_resp_t ext_core_instr_resp_i,
-    output obi_req_t  ext_core_data_req_o,
-    input  obi_resp_t ext_core_data_resp_i,
-    output obi_req_t  ext_debug_master_req_o,
-    input  obi_resp_t ext_debug_master_resp_i,
-    output obi_req_t  ext_dma_read_ch0_req_o,
-    input  obi_resp_t ext_dma_read_ch0_resp_i,
-    output obi_req_t  ext_dma_write_ch0_req_o,
-    input  obi_resp_t ext_dma_write_ch0_resp_i,
-    output obi_req_t  ext_dma_addr_ch0_req_o,
-    input  obi_resp_t ext_dma_addr_ch0_resp_i,
+    output obi_req_t ext_core_instr_req_o,
+    input obi_resp_t ext_core_instr_resp_i,
+    output obi_req_t ext_core_data_req_o,
+    input obi_resp_t ext_core_data_resp_i,
+    output obi_req_t ext_debug_master_req_o,
+    input obi_resp_t ext_debug_master_resp_i,
+    output obi_req_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_req_o,
+    input obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_resp_i,
+    output obi_req_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_req_o,
+    input obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_resp_i,
+    output obi_req_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_req_o,
+    input obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_resp_i,
 
     input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
 
@@ -325,8 +330,10 @@ module core_v_mini_mcu
 
     output logic [31:0] exit_value_o,
 
-    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
-    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i
+    // External SPC interface
+    input  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
+    input  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i,
+    output logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_done_o
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -355,12 +362,12 @@ module core_v_mini_mcu
   obi_resp_t core_data_resp;
   obi_req_t debug_master_req;
   obi_resp_t debug_master_resp;
-  obi_req_t dma_read_ch0_req;
-  obi_resp_t dma_read_ch0_resp;
-  obi_req_t dma_write_ch0_req;
-  obi_resp_t dma_write_ch0_resp;
-  obi_req_t dma_addr_ch0_req;
-  obi_resp_t dma_addr_ch0_resp;
+  obi_req_t [0:0] dma_read_req;
+  obi_resp_t [0:0] dma_read_resp;
+  obi_req_t [0:0] dma_write_req;
+  obi_resp_t [0:0] dma_write_resp;
+  obi_req_t [0:0] dma_addr_req;
+  obi_resp_t [0:0] dma_addr_resp;
 
   // ram signals
   obi_req_t [core_v_mini_mcu_pkg::NUM_BANKS-1:0] ram_slave_req;
@@ -568,12 +575,12 @@ module core_v_mini_mcu
       .core_data_resp_o(core_data_resp),
       .debug_master_req_i(debug_master_req),
       .debug_master_resp_o(debug_master_resp),
-      .dma_read_ch0_req_i(dma_read_ch0_req),
-      .dma_read_ch0_resp_o(dma_read_ch0_resp),
-      .dma_write_ch0_req_i(dma_write_ch0_req),
-      .dma_write_ch0_resp_o(dma_write_ch0_resp),
-      .dma_addr_ch0_req_i(dma_addr_ch0_req),
-      .dma_addr_ch0_resp_o(dma_addr_ch0_resp),
+      .dma_read_req_i(dma_read_req),
+      .dma_read_resp_o(dma_read_resp),
+      .dma_write_req_i(dma_write_req),
+      .dma_write_resp_o(dma_write_resp),
+      .dma_addr_req_i(dma_addr_req),
+      .dma_addr_resp_o(dma_addr_resp),
       .ext_xbar_master_req_i(ext_xbar_master_req_i),
       .ext_xbar_master_resp_o(ext_xbar_master_resp_o),
       .ram_req_o(ram_slave_req),
@@ -592,12 +599,12 @@ module core_v_mini_mcu
       .ext_core_data_resp_i(ext_core_data_resp_i),
       .ext_debug_master_req_o(ext_debug_master_req_o),
       .ext_debug_master_resp_i(ext_debug_master_resp_i),
-      .ext_dma_read_ch0_req_o(ext_dma_read_ch0_req_o),
-      .ext_dma_read_ch0_resp_i(ext_dma_read_ch0_resp_i),
-      .ext_dma_write_ch0_req_o(ext_dma_write_ch0_req_o),
-      .ext_dma_write_ch0_resp_i(ext_dma_write_ch0_resp_i),
-      .ext_dma_addr_ch0_req_o(ext_dma_addr_ch0_req_o),
-      .ext_dma_addr_ch0_resp_i(ext_dma_addr_ch0_resp_i)
+      .ext_dma_read_req_o(ext_dma_read_req_o),
+      .ext_dma_read_resp_i(ext_dma_read_resp_i),
+      .ext_dma_write_req_o(ext_dma_write_req_o),
+      .ext_dma_write_resp_i(ext_dma_write_resp_i),
+      .ext_dma_addr_req_o(ext_dma_addr_req_o),
+      .ext_dma_addr_resp_i(ext_dma_addr_resp_i)
   );
 
   memory_subsystem #(
@@ -613,11 +620,15 @@ module core_v_mini_mcu
       .set_retentive_ni(memory_subsystem_banks_set_retentive_n)
   );
 
-  ao_peripheral_subsystem ao_peripheral_subsystem_i (
+  ao_peripheral_subsystem #(
+      .AO_SPC_NUM(AO_SPC_NUM)
+  ) ao_peripheral_subsystem_i (
       .clk_i,
       .rst_ni(rst_ni && debug_reset_n),
       .slave_req_i(ao_peripheral_slave_req),
       .slave_resp_o(ao_peripheral_slave_resp),
+      .spc2ao_req_i(ext_ao_peripheral_slave_req_i),
+      .ao2spc_resp_o(ext_ao_peripheral_slave_resp_o),
       .boot_select_i,
       .execute_from_flash_i,
       .exit_valid_o,
@@ -646,12 +657,12 @@ module core_v_mini_mcu
       .external_subsystem_pwr_ctrl_i(external_subsystem_pwr_ctrl_in),
       .rv_timer_0_intr_o(rv_timer_intr[0]),
       .rv_timer_1_intr_o(rv_timer_intr[1]),
-      .dma_read_ch0_req_o(dma_read_ch0_req),
-      .dma_read_ch0_resp_i(dma_read_ch0_resp),
-      .dma_write_ch0_req_o(dma_write_ch0_req),
-      .dma_write_ch0_resp_i(dma_write_ch0_resp),
-      .dma_addr_ch0_req_o(dma_addr_ch0_req),
-      .dma_addr_ch0_resp_i(dma_addr_ch0_resp),
+      .dma_read_req_o(dma_read_req),
+      .dma_read_resp_i(dma_read_resp),
+      .dma_write_req_o(dma_write_req),
+      .dma_write_resp_i(dma_write_resp),
+      .dma_addr_req_o(dma_addr_req),
+      .dma_addr_resp_i(dma_addr_resp),
       .dma_done_intr_o(dma_done_intr),
       .dma_window_intr_o(dma_window_intr),
       .spi_flash_intr_event_o(spi_flash_intr),
@@ -680,7 +691,8 @@ module core_v_mini_mcu
       .ext_peripheral_slave_resp_i,
       .ext_dma_slot_tx_i,
       .ext_dma_slot_rx_i,
-      .ext_dma_stop_i
+      .ext_dma_stop_i,
+      .dma_done_o
   );
 
   peripheral_subsystem peripheral_subsystem_i (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
index cb571752..aedf2e2c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
@@ -11,8 +11,10 @@ module core_v_mini_mcu
     parameter ZFINX = 0,
     parameter EXT_XBAR_NMASTER = 0,
     parameter X_EXT = 0,  // eXtension interface in cv32e40x
+    parameter AO_SPC_NUM = 0,
     parameter EXT_HARTS = 0,
     //do not touch these parameters
+    parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
     parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
     parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
     parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT,
@@ -39,6 +41,9 @@ ${pad.core_v_mini_mcu_interface}
     input  obi_req_t  [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_req_i,
     output obi_resp_t [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_resp_o,
 
+    input reg_req_t  [AO_SPC_NUM_RND-1:0] ext_ao_peripheral_slave_req_i,
+    output reg_rsp_t [AO_SPC_NUM_RND-1:0] ext_ao_peripheral_slave_resp_o,
+
     // External slave ports
     output obi_req_t  ext_core_instr_req_o,
     input  obi_resp_t ext_core_instr_resp_i,
@@ -46,12 +51,12 @@ ${pad.core_v_mini_mcu_interface}
     input  obi_resp_t ext_core_data_resp_i,
     output obi_req_t  ext_debug_master_req_o,
     input  obi_resp_t ext_debug_master_resp_i,
-    output obi_req_t  ext_dma_read_ch0_req_o,
-    input  obi_resp_t ext_dma_read_ch0_resp_i,
-    output obi_req_t  ext_dma_write_ch0_req_o,
-    input  obi_resp_t ext_dma_write_ch0_resp_i,
-    output obi_req_t  ext_dma_addr_ch0_req_o,
-    input  obi_resp_t ext_dma_addr_ch0_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_resp_i,
 
     input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
 
@@ -79,8 +84,10 @@ ${pad.core_v_mini_mcu_interface}
 
     output logic [31:0] exit_value_o,
 
+    // External SPC interface
     input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx_i,
-    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx_i,
+    output logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_done_o
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -109,12 +116,12 @@ ${pad.core_v_mini_mcu_interface}
   obi_resp_t core_data_resp;
   obi_req_t debug_master_req;
   obi_resp_t debug_master_resp;
-  obi_req_t dma_read_ch0_req;
-  obi_resp_t dma_read_ch0_resp;
-  obi_req_t dma_write_ch0_req;
-  obi_resp_t dma_write_ch0_resp;
-  obi_req_t dma_addr_ch0_req;
-  obi_resp_t dma_addr_ch0_resp;
+  obi_req_t [${int(num_dma_master_ports)-1}:0]dma_read_req;
+  obi_resp_t [${int(num_dma_master_ports)-1}:0]dma_read_resp;
+  obi_req_t [${int(num_dma_master_ports)-1}:0]dma_write_req;
+  obi_resp_t [${int(num_dma_master_ports)-1}:0]dma_write_resp;
+  obi_req_t [${int(num_dma_master_ports)-1}:0]dma_addr_req;
+  obi_resp_t [${int(num_dma_master_ports)-1}:0]dma_addr_resp;
 
   // ram signals
   obi_req_t [core_v_mini_mcu_pkg::NUM_BANKS-1:0] ram_slave_req;
@@ -318,12 +325,12 @@ ${pad.core_v_mini_mcu_interface}
       .core_data_resp_o(core_data_resp),
       .debug_master_req_i(debug_master_req),
       .debug_master_resp_o(debug_master_resp),
-      .dma_read_ch0_req_i(dma_read_ch0_req),
-      .dma_read_ch0_resp_o(dma_read_ch0_resp),
-      .dma_write_ch0_req_i(dma_write_ch0_req),
-      .dma_write_ch0_resp_o(dma_write_ch0_resp),
-      .dma_addr_ch0_req_i(dma_addr_ch0_req),
-      .dma_addr_ch0_resp_o(dma_addr_ch0_resp),
+      .dma_read_req_i(dma_read_req),
+      .dma_read_resp_o(dma_read_resp),
+      .dma_write_req_i(dma_write_req),
+      .dma_write_resp_o(dma_write_resp),
+      .dma_addr_req_i(dma_addr_req),
+      .dma_addr_resp_o(dma_addr_resp),
       .ext_xbar_master_req_i(ext_xbar_master_req_i),
       .ext_xbar_master_resp_o(ext_xbar_master_resp_o),
       .ram_req_o(ram_slave_req),
@@ -342,12 +349,12 @@ ${pad.core_v_mini_mcu_interface}
       .ext_core_data_resp_i(ext_core_data_resp_i),
       .ext_debug_master_req_o(ext_debug_master_req_o),
       .ext_debug_master_resp_i(ext_debug_master_resp_i),
-      .ext_dma_read_ch0_req_o(ext_dma_read_ch0_req_o),
-      .ext_dma_read_ch0_resp_i(ext_dma_read_ch0_resp_i),
-      .ext_dma_write_ch0_req_o(ext_dma_write_ch0_req_o),
-      .ext_dma_write_ch0_resp_i(ext_dma_write_ch0_resp_i),
-      .ext_dma_addr_ch0_req_o(ext_dma_addr_ch0_req_o),
-      .ext_dma_addr_ch0_resp_i(ext_dma_addr_ch0_resp_i)
+      .ext_dma_read_req_o(ext_dma_read_req_o),
+      .ext_dma_read_resp_i(ext_dma_read_resp_i),
+      .ext_dma_write_req_o(ext_dma_write_req_o),
+      .ext_dma_write_resp_i(ext_dma_write_resp_i),
+      .ext_dma_addr_req_o(ext_dma_addr_req_o),
+      .ext_dma_addr_resp_i(ext_dma_addr_resp_i)
   );
 
   memory_subsystem #(
@@ -363,11 +370,15 @@ ${pad.core_v_mini_mcu_interface}
       .set_retentive_ni(memory_subsystem_banks_set_retentive_n)
   );
 
-  ao_peripheral_subsystem ao_peripheral_subsystem_i (
+  ao_peripheral_subsystem #(
+      .AO_SPC_NUM(AO_SPC_NUM)
+  ) ao_peripheral_subsystem_i (
       .clk_i,
       .rst_ni(rst_ni && debug_reset_n),
       .slave_req_i(ao_peripheral_slave_req),
       .slave_resp_o(ao_peripheral_slave_resp),
+      .spc2ao_req_i(ext_ao_peripheral_slave_req_i),
+      .ao2spc_resp_o(ext_ao_peripheral_slave_resp_o),
       .boot_select_i,
       .execute_from_flash_i,
       .exit_valid_o,
@@ -394,12 +405,12 @@ ${pad.core_v_mini_mcu_interface}
       .external_subsystem_pwr_ctrl_i(external_subsystem_pwr_ctrl_in),
       .rv_timer_0_intr_o(rv_timer_intr[0]),
       .rv_timer_1_intr_o(rv_timer_intr[1]),
-      .dma_read_ch0_req_o(dma_read_ch0_req),
-      .dma_read_ch0_resp_i(dma_read_ch0_resp),
-      .dma_write_ch0_req_o(dma_write_ch0_req),
-      .dma_write_ch0_resp_i(dma_write_ch0_resp),
-      .dma_addr_ch0_req_o(dma_addr_ch0_req),
-      .dma_addr_ch0_resp_i(dma_addr_ch0_resp),
+      .dma_read_req_o(dma_read_req),
+      .dma_read_resp_i(dma_read_resp),
+      .dma_write_req_o(dma_write_req),
+      .dma_write_resp_i(dma_write_resp),
+      .dma_addr_req_o(dma_addr_req),
+      .dma_addr_resp_i(dma_addr_resp),
       .dma_done_intr_o(dma_done_intr),
       .dma_window_intr_o(dma_window_intr),
       .spi_flash_intr_event_o(spi_flash_intr),
@@ -428,7 +439,8 @@ ${pad.core_v_mini_mcu_interface}
       .ext_peripheral_slave_resp_i,
       .ext_dma_slot_tx_i,
       .ext_dma_slot_rx_i,
-      .ext_dma_stop_i
+      .ext_dma_stop_i,
+      .dma_done_o
   );
 
   peripheral_subsystem peripheral_subsystem_i (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.vlt b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.vlt
index e1493802..11f96091 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.vlt
@@ -8,6 +8,7 @@ lint_off -rule UNUSED -file "*/core_v_mini_mcu.sv" -match "*"
 lint_off -rule UNUSED -file "*/cpu_subsystem.sv" -match "Signal is not used: 'apu*'*"
 lint_off -rule UNDRIVEN -file "*/memory_subsystem.sv" -match "Bits of signal are not driven: 'ram*_resp_o'[32]*"
 lint_off -rule UNOPTFLAT -file "*/system_xbar.sv" -match "Signal unoptimizable*"
+lint_off -rule UNOPTFLAT -file "*/ao_peripheral_subsystem.sv" -match "*"
 lint_off -rule UNOPTFLAT -file "*/xbar_varlat_one_to_n.sv" -match "Signal unoptimizable: Feedback to clock or circular logic: *"
 lint_off -rule UNOPTFLAT -file "*/xbar_varlat_n_to_one.sv" -match "Signal unoptimizable: Feedback to clock or circular logic: *"
 lint_off -rule UNUSED -file "*/reg_to_tlul.sv" -match "Bits of signal are not used: 'tl_i'*"
@@ -28,3 +29,4 @@ lint_off -rule LITENDIAN -file "*/x_heep_system.sv" -match "*"
 lint_off -rule WIDTH -file "*/ao_peripheral_subsystem.sv" -match "Input port connection 'reg_req_i' expects 70 bits on the pin connection, but pin connection's SEL generates 34 bits.*"
 lint_off -rule UNDRIVEN -file "*ip/power_manager/rtl/power_manager.sv" -match "Signal is not driven: 'external_ram_banks_set_retentive*'"
 lint_off -rule UNDRIVEN -file "*ip/power_manager/rtl/power_manager.sv" -match "Signal is not driven: 'external_subsystem_clkgate_en*'"
+lint_off -rule UNUSED -file "*vendor/pulp_platform_register_interface/src/reg_mux.sv" -match "*"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
index ba99d50f..00ffc025 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl
@@ -38,11 +38,11 @@ package core_v_mini_mcu_pkg;
   localparam logic [31:0] CORE_INSTR_IDX = 0;
   localparam logic [31:0] CORE_DATA_IDX = 1;
   localparam logic [31:0] DEBUG_MASTER_IDX = 2;
-  localparam logic [31:0] DMA_READ_CH0_IDX = 3;
-  localparam logic [31:0] DMA_WRITE_CH0_IDX = 4;
-  localparam logic [31:0] DMA_ADDR_CH0_IDX = 5;
+  localparam logic [31:0] DMA_READ_P0_IDX = 3;
+  localparam logic [31:0] DMA_WRITE_P0_IDX = 4;
+  localparam logic [31:0] DMA_ADDR_P0_IDX = 5;
 
-  localparam SYSTEM_XBAR_NMASTER = 6;
+  localparam SYSTEM_XBAR_NMASTER = ${3 + int(num_dma_master_ports)*3};
 
   // Internal slave memory map and index
   // -----------------------------------
@@ -139,7 +139,14 @@ package core_v_mini_mcu_pkg;
   // ---------------------
   localparam AO_PERIPHERALS = ${ao_peripherals_count};
   localparam DMA_CH_NUM = ${dma_ch_count};
-
+  localparam DMA_CH_SIZE = 32'h${dma_ch_size};
+  localparam DMA_NUM_MASTER_PORTS = ${num_dma_master_ports};
+% if int(num_dma_master_ports) > 1:
+  localparam int DMA_XBAR_MASTERS [DMA_NUM_MASTER_PORTS] = '{${dma_xbar_masters_array[::-1]}};
+% else:
+  localparam int DMA_XBAR_MASTERS [DMA_NUM_MASTER_PORTS] = '{${dma_xbar_masters_array}};
+% endif
+  
 % for peripheral, addr in ao_peripherals.items():
   localparam logic [31:0] ${peripheral.upper()}_START_ADDRESS = AO_PERIPHERAL_START_ADDRESS + 32'h${addr["offset"]};
   localparam logic [31:0] ${peripheral.upper()}_SIZE = 32'h${addr["length"]};
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl
index 19bb8622..221ec067 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/system_bus.sv.tpl
@@ -37,14 +37,14 @@ module system_bus
     input  obi_req_t  debug_master_req_i,
     output obi_resp_t debug_master_resp_o,
 
-    input  obi_req_t  dma_read_ch0_req_i,
-    output obi_resp_t dma_read_ch0_resp_o,
+    input  obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_read_req_i,
+    output obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_read_resp_o,
 
-    input  obi_req_t  dma_write_ch0_req_i,
-    output obi_resp_t dma_write_ch0_resp_o,
+    input  obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_write_req_i,
+    output obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_write_resp_o,
 
-    input  obi_req_t  dma_addr_ch0_req_i,
-    output obi_resp_t dma_addr_ch0_resp_o,
+    input  obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_addr_req_i,
+    output obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_addr_resp_o,
 
     // External master ports
     input  obi_req_t  [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_req_i,
@@ -76,14 +76,14 @@ module system_bus
     output obi_req_t  ext_debug_master_req_o,
     input  obi_resp_t ext_debug_master_resp_i,
 
-    output obi_req_t  ext_dma_read_ch0_req_o,
-    input  obi_resp_t ext_dma_read_ch0_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_resp_i,
 
-    output obi_req_t  ext_dma_write_ch0_req_o,
-    input  obi_resp_t ext_dma_write_ch0_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_resp_i,
 
-    output obi_req_t  ext_dma_addr_ch0_req_o,
-    input  obi_resp_t ext_dma_addr_ch0_resp_i
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_resp_i
 );
 
   import core_v_mini_mcu_pkg::*;
@@ -119,9 +119,12 @@ module system_bus
   assign int_master_req[core_v_mini_mcu_pkg::CORE_INSTR_IDX] = core_instr_req_i;
   assign int_master_req[core_v_mini_mcu_pkg::CORE_DATA_IDX] = core_data_req_i;
   assign int_master_req[core_v_mini_mcu_pkg::DEBUG_MASTER_IDX] = debug_master_req_i;
-  assign int_master_req[core_v_mini_mcu_pkg::DMA_READ_CH0_IDX] = dma_read_ch0_req_i;
-  assign int_master_req[core_v_mini_mcu_pkg::DMA_WRITE_CH0_IDX] = dma_write_ch0_req_i;
-  assign int_master_req[core_v_mini_mcu_pkg::DMA_ADDR_CH0_IDX] = dma_addr_ch0_req_i;
+
+  % for i in range(int(num_dma_master_ports)):
+  assign int_master_req[${3+i*3}]  = dma_read_req_i[${i}];
+  assign int_master_req[${4+i*3}] = dma_write_req_i[${i}];
+  assign int_master_req[${5+i*3}]  = dma_addr_req_i[${i}];
+  % endfor
 
   // Internal + external master requests
   generate
@@ -142,10 +145,13 @@ module system_bus
   assign core_instr_resp_o = int_master_resp[core_v_mini_mcu_pkg::CORE_INSTR_IDX];
   assign core_data_resp_o = int_master_resp[core_v_mini_mcu_pkg::CORE_DATA_IDX];
   assign debug_master_resp_o = int_master_resp[core_v_mini_mcu_pkg::DEBUG_MASTER_IDX];
-  assign dma_read_ch0_resp_o = int_master_resp[core_v_mini_mcu_pkg::DMA_READ_CH0_IDX];
-  assign dma_write_ch0_resp_o = int_master_resp[core_v_mini_mcu_pkg::DMA_WRITE_CH0_IDX];
-  assign dma_addr_ch0_resp_o = int_master_resp[core_v_mini_mcu_pkg::DMA_ADDR_CH0_IDX];
 
+  % for i in range(int(num_dma_master_ports)):
+  assign dma_read_resp_o[${i}] = int_master_resp[${3+i*3}];
+  assign dma_write_resp_o[${i}] = int_master_resp[${4+i*3}];
+  assign dma_addr_resp_o[${i}] = int_master_resp[${5+i*3}];
+  % endfor
+  
   // External master responses
   if (EXT_XBAR_NMASTER == 0) begin
     assign ext_xbar_master_resp_o = '0;
@@ -169,9 +175,14 @@ module system_bus
   assign ext_core_instr_req_o = demux_xbar_req[CORE_INSTR_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
   assign ext_core_data_req_o = demux_xbar_req[CORE_DATA_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
   assign ext_debug_master_req_o = demux_xbar_req[DEBUG_MASTER_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
-  assign ext_dma_read_ch0_req_o = demux_xbar_req[DMA_READ_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
-  assign ext_dma_write_ch0_req_o = demux_xbar_req[DMA_WRITE_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
-  assign ext_dma_addr_ch0_req_o = demux_xbar_req[DMA_ADDR_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX];
+  generate
+    for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS; i++) begin : gen_ext_dma_master_req_map
+      assign ext_dma_read_req_o[i] = demux_xbar_req[core_v_mini_mcu_pkg::DMA_READ_P0_IDX+3*i][DEMUX_XBAR_EXT_SLAVE_IDX];
+      assign ext_dma_write_req_o[i] = demux_xbar_req[core_v_mini_mcu_pkg::DMA_WRITE_P0_IDX+3*i][DEMUX_XBAR_EXT_SLAVE_IDX];
+      assign ext_dma_addr_req_o[i] = demux_xbar_req[core_v_mini_mcu_pkg::DMA_ADDR_P0_IDX+3*i][DEMUX_XBAR_EXT_SLAVE_IDX];
+    end
+  endgenerate
+  
 
   // Internal slave responses
   assign int_slave_resp[core_v_mini_mcu_pkg::ERROR_IDX] = error_slave_resp;
@@ -187,10 +198,14 @@ module system_bus
   assign demux_xbar_resp[CORE_INSTR_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_core_instr_resp_i;
   assign demux_xbar_resp[CORE_DATA_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_core_data_resp_i;
   assign demux_xbar_resp[DEBUG_MASTER_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_debug_master_resp_i;
-  assign demux_xbar_resp[DMA_READ_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_read_ch0_resp_i;
-  assign demux_xbar_resp[DMA_WRITE_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_write_ch0_resp_i;
-  assign demux_xbar_resp[DMA_ADDR_CH0_IDX][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_addr_ch0_resp_i;
-
+  generate
+    for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS; i++) begin : gen_ext_dma_master_resp_map
+      assign demux_xbar_resp[core_v_mini_mcu_pkg::DMA_READ_P0_IDX+3*i][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_read_resp_i[i];
+      assign demux_xbar_resp[core_v_mini_mcu_pkg::DMA_WRITE_P0_IDX+3*i][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_write_resp_i[i];
+      assign demux_xbar_resp[core_v_mini_mcu_pkg::DMA_ADDR_P0_IDX+3*i][DEMUX_XBAR_EXT_SLAVE_IDX] = ext_dma_addr_resp_i[i];
+    end
+  endgenerate
+  
 `ifndef SYNTHESIS
   always_ff @(posedge clk_i, negedge rst_ni) begin : check_out_of_bound
     if (rst_ni) begin
diff --git a/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv b/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
index fc9c53fb..343bda8e 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
@@ -133,16 +133,18 @@ module xilinx_core_v_mini_mcu_wrapper
       .ext_core_data_resp_i('0),
       .ext_debug_master_req_o(),
       .ext_debug_master_resp_i('0),
-      .ext_dma_read_ch0_req_o(),
-      .ext_dma_read_ch0_resp_i('0),
-      .ext_dma_write_ch0_req_o(),
-      .ext_dma_write_ch0_resp_i('0),
-      .ext_dma_addr_ch0_req_o(),
-      .ext_dma_addr_ch0_resp_i('0),
+      .ext_dma_read_req_o(),
+      .ext_dma_read_resp_i('0),
+      .ext_dma_write_req_o(),
+      .ext_dma_write_resp_i('0),
+      .ext_dma_addr_req_o(),
+      .ext_dma_addr_resp_i('0),
       .ext_peripheral_slave_req_o(),
       .ext_peripheral_slave_resp_i('0),
+      .ext_ao_peripheral_req_i('0),
+      .ext_ao_peripheral_resp_o(),
       .external_subsystem_powergate_switch_no(),
-      .external_subsystem_powergate_switch_ack_ni(),
+      .external_subsystem_powergate_switch_ack_ni('0),
       .external_subsystem_powergate_iso_no(),
       .external_subsystem_rst_no(),
       .external_ram_banks_set_retentive_no(),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson
index 58f6d3a0..4f144c61 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/data/dma.hjson
@@ -34,7 +34,7 @@
       ]
     },
     { name:     "SIZE_D1",
-      desc:     "Number of bytes to copy from, defined with respect to the first dimension - Once a value is written, the copy starts",
+      desc:     "Number of elements to copy from, defined with respect to the first dimension - Once a value is written, the copy starts",
       swaccess: "rw",
       hwaccess: "hro",
       hwqe:     "true", // enable `qe` latched signal of software write pulse
@@ -44,10 +44,9 @@
       ]
     },
     { name:     "SIZE_D2",
-      desc:     "Number of bytes to copy from, defined with respect to the second dimension",
+      desc:     "Number of elements to copy from, defined with respect to the second dimension",
       swaccess: "rw",
       hwaccess: "hro",
-      hwqe:     "true", // enable `qe` latched signal of software write pulse
       // Dimensioned to 16 bits to allow for 64kB transfers on 2D
       fields: [
         { bits: "15:0", name: "SIZE", desc: "DMA counter D2" }
@@ -118,7 +117,7 @@
     { name:     "SLOT",
       desc:     '''The DMA will wait for the signal 
                    connected to the selected trigger_slots to be high
-                   on the read and write side respectivly''',
+                   on the read and write side respectively''',
       swaccess: "rw",
       hwaccess: "hro",
       resval:   0,
@@ -185,6 +184,7 @@
       desc:     '''Set the operational mode of the DMA''',
       swaccess: "rw",
       hwaccess: "hro",
+      resval:        0,
       fields: [
         { bits: "1:0", name: "MODE",
           desc: "DMA operation mode",
@@ -218,7 +218,6 @@
       desc:     '''Set the top padding''',
       swaccess: "rw",
       hwaccess: "hro",
-      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
       resval:   0,
       fields: [
         { bits: "5:0", name: "PAD", desc: "Top margin padding (2D)"}
@@ -228,7 +227,6 @@
       desc:     '''Set the bottom padding''',
       swaccess: "rw",
       hwaccess: "hro",
-      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
       resval:   0,
       fields: [
         { bits: "5:0", name: "PAD", desc: "Bottom margin padding (2D)"}
@@ -238,7 +236,6 @@
       desc:     '''Set the right padding''',
       swaccess: "rw",
       hwaccess: "hro",
-      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
       resval:   0,
       fields: [
         { bits: "5:0", name: "PAD", desc: "Right margin padding (1D/2D)"}
@@ -248,7 +245,6 @@
       desc:     '''Set the left padding''',
       swaccess: "rw",
       hwaccess: "hro",
-      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
       resval:   0,
       fields: [
         { bits: "5:0", name: "PAD", desc: "Left margin padding (1D/2D)"}
@@ -259,6 +255,7 @@
                   Set to 0 to disable.''',
       swaccess: "rw",
       hwaccess: "hro",
+      resval:        0,
       fields: [
         { bits: "12:0", name: "WINDOW_SIZE", desc: ""}
       ]
@@ -267,7 +264,6 @@
       desc:    '''Number of times the end of the window was reached since the beginning.
                   Reset at start''',
       swaccess: "ro",
-      // hwext: "true",
       hwaccess: "hrw",
       resval: 0,
       fields: [
@@ -279,6 +275,7 @@
                   (Only the interrupt with the lowest id will be triggered)''',
       swaccess: "rw",
       hwaccess: "hro",
+      resval:        0,
       fields: [
         { bits: "0", name: "TRANSACTION_DONE", desc: "Enables transaction done interrupt" }
         { bits: "1", name: "WINDOW_DONE", desc: "Enables window done interrupt" }
@@ -306,5 +303,5 @@
         { bits: "0", name: "FLAG", desc: "Set for window done interrupt" }
       ]
     }
-   ]
+  ]
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core
index 86255b7a..0bf343e7 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.core
@@ -14,6 +14,10 @@ filesets:
     files:
     - rtl/dma_reg_pkg.sv
     - rtl/dma_reg_top.sv
+    - rtl/dma_padding_fsm.sv
+    - rtl/dma_obiread_fsm.sv
+    - rtl/dma_obiread_addr_fsm.sv
+    - rtl/dma_obiwrite_fsm.sv
     - rtl/dma.sv
     file_type: systemVerilogSource
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.vlt b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.vlt
index 1034666a..70cee9b4 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.vlt
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/dma.vlt
@@ -7,8 +7,13 @@
 lint_off -rule DECLFILENAME -file "*/dma_reg_top.sv"
 
 lint_off -rule WIDTH -file "*/rtl/dma_reg_top.sv" -match "Operator ASSIGNW expects *"
+lint_off -rule WIDTH -file "*/rtl/dma.sv" -match "Operator ASSIGNW expects *"
  
 lint_off -rule UNUSED -file "*/rtl/dma.sv" -match "Signal is not used: 'data_out_rvalid'"
 lint_off -rule UNUSED -file "*/rtl/dma.sv" -match "Signal is not used: 'data_out_rdata'"
 
+lint_off -rule UNUSED -file "*/rtl/dma_obiread_fsm.sv" -match "Bits of signal are not used: *"
+lint_off -rule UNUSED -file "*/rtl/dma_obiwrite_fsm.sv" -match "Bits of signal are not used: *"
+lint_off -rule UNUSED -file "*/rtl/dma_obiread_addr_fsm.sv" -match "Bits of signal are not used: *"
+lint_off -rule UNUSED -file "*/rtl/dma_padding_fsm.sv" -match "Bits of signal are not used: *"
 lint_off -rule UNUSED -file "*/rtl/dma.sv" -match "Bits of signal are not used: *"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv
index 4bfe0219..923b5a1f 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma.sv
@@ -1,11 +1,11 @@
 /*
- * Copyright 2022 EPFL
+ * Copyright 2024 EPFL
  * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
  * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *  
+ * Info: Direct Memory Access (DMA) channel module.
  */
 
-/* DMA assume a read request is not granted before previous request rvalid is asserted */
-
 module dma #(
     parameter int unsigned FIFO_DEPTH = 4,
     parameter type reg_req_t = logic,
@@ -16,156 +16,125 @@ module dma #(
 ) (
     input logic clk_i,
     input logic rst_ni,
+    input logic clk_gate_en_ni,
 
     input logic ext_dma_stop_i,
 
     input  reg_req_t reg_req_i,
     output reg_rsp_t reg_rsp_o,
 
-    output obi_req_t  dma_read_ch0_req_o,
-    input  obi_resp_t dma_read_ch0_resp_i,
+    output obi_req_t  dma_read_req_o,
+    input  obi_resp_t dma_read_resp_i,
 
-    output obi_req_t  dma_write_ch0_req_o,
-    input  obi_resp_t dma_write_ch0_resp_i,
+    output obi_req_t  dma_write_req_o,
+    input  obi_resp_t dma_write_resp_i,
 
-    output obi_req_t  dma_addr_ch0_req_o,
-    input  obi_resp_t dma_addr_ch0_resp_i,
+    output obi_req_t  dma_addr_req_o,
+    input  obi_resp_t dma_addr_resp_i,
 
     input logic [SLOT_NUM-1:0] trigger_slot_i,
 
     output dma_done_intr_o,
-    output dma_window_intr_o
+    output dma_window_intr_o,
+
+    output dma_done_o
 );
 
   import dma_reg_pkg::*;
 
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Parameter definition */
+
   localparam int unsigned LastFifoUsage = FIFO_DEPTH - 1;
   localparam int unsigned Addr_Fifo_Depth = (FIFO_DEPTH > 1) ? $clog2(FIFO_DEPTH) : 1;
 
-  dma_reg2hw_t                       reg2hw;
-  dma_hw2reg_t                       hw2reg;
-
-  logic        [               31:0] src_ptr_reg;
-  logic        [               31:0] read_ptr_reg;
-  logic        [               31:0] addr_ptr_reg;
-  logic        [               31:0] read_ptr_valid_reg;
-  logic        [               31:0] write_ptr_reg;
-  logic        [               31:0] write_address;
-  logic        [               31:0] dma_addr_cnt;
-  logic        [                2:0] dma_src_cnt_du;
-  logic        [                2:0] dma_dst_cnt_du;
-  logic                              dma_start;
-  logic                              dma_done;
-  logic                              dma_window_event;
-
-  logic                              window_done_q;
-
-  logic        [Addr_Fifo_Depth-1:0] fifo_usage;
-  logic                              fifo_alm_full;
-
-  logic        [Addr_Fifo_Depth-1:0] fifo_addr_usage;
-  logic                              fifo_addr_alm_full;
-
-  logic                              data_in_req;
-  logic                              data_in_we;
-  logic        [                3:0] data_in_be;
-  logic        [               31:0] data_in_addr;
-  logic                              data_in_gnt;
-  logic                              data_in_rvalid;
-  logic        [               31:0] data_in_rdata;
-
-  logic                              data_addr_in_req;
-  logic                              data_addr_in_we;
-  logic        [                3:0] data_addr_in_be;
-  logic        [               31:0] data_addr_in_addr;
-  logic                              data_addr_in_gnt;
-  logic                              data_addr_in_rvalid;
-  logic        [               31:0] data_addr_in_rdata;
-
-  logic                              data_out_req;
-  logic                              data_out_we;
-  logic        [                3:0] data_out_be;
-  logic        [               31:0] data_out_addr;
-  logic        [               31:0] data_out_wdata;
-  logic                              data_out_gnt;
-  logic                              data_out_rvalid;
-  logic        [               31:0] data_out_rdata;
-
-  /* Sign extension signals */
-  logic                              sign_extend;
-
-  /* 2D signals */
-
-  /* Dimensionality configuration */
-  logic                              dma_conf_1d;  // Dimensionality configuration: 0-> 1D, 1-> 2D
-  logic                              dma_conf_2d;  // Dimensionality configuration: 0-> 1D, 1-> 2D
-
-  /* Counters */
-  logic        [               16:0] dma_src_cnt_d1;  // d1 src counter
-  logic        [               16:0] dma_src_cnt_d2;  // d2 src counter
-  logic        [               16:0] dma_dst_cnt_d1;  // d2 dst counter
-
-  /* Increments */
-  logic        [                5:0] dma_src_d1_inc;  // d1 source increment
-  logic        [               22:0] dma_src_d2_inc;  // d2 source increment
-  logic        [                5:0] dma_dst_d1_inc;  // d1 destination increment
-  logic        [               22:0] dma_dst_d2_inc;  // d2 destination increment
-
-  /* Flags */
-  logic                              pad_fifo_on;  // Padding flag for FIFO
-  logic                              pad_cnt_on;  // Padding flag for counters
-  logic                              read_ptr_update_sel;  // Select the read pointer update source
-
-  /* Padding FSM conditions */
-  logic                              idle_to_left_ex;
-  logic                              idle_to_top_ex;
-  logic                              idle_to_right_ex;
-  logic                              idle_to_bottom_ex;
-  logic                              top_ex_to_top_dn;
-  logic                              top_ex_to_left_ex;
-  logic                              top_dn_to_right_ex;
-  logic                              top_dn_to_bottom_ex;
-  logic                              top_dn_to_idle;
-  logic                              left_ex_to_left_dn;
-  logic                              left_dn_to_left_ex;
-  logic                              left_dn_to_right_ex;
-  logic                              left_dn_to_bottom_ex;
-  logic                              left_dn_to_idle;
-  logic                              right_ex_to_right_dn;
-  logic                              right_ex_to_left_ex;
-  logic                              right_dn_to_right_ex;
-  logic                              right_dn_to_idle;
-  logic                              right_ex_to_bottom_ex;
-  logic                              bottom_ex_to_idle;
-
-  /* Padding synchronization signals */
-  logic                              data_in_rvalid_virt;
-  logic                              data_in_rvalid_virt_n;
-  logic                              data_in_rvalid_virt_n_n;
-  logic                              data_in_gnt_virt;
-  logic                              data_in_gnt_virt_n;
-  logic                              data_in_gnt_virt_n_n;
+  /*_________________________________________________________________________________________________________________________________ */
 
-  /* Interrupt Flag Register signals */
-  logic                              transaction_ifr;
-  logic                              dma_done_intr_n;
-  logic                              dma_done_intr;
-  logic                              window_ifr;
-  logic                              dma_window_intr;
-  logic                              dma_window_intr_n;
+  /* Signals declaration */
 
-  /* FIFO signals */
-  logic                              fifo_flush;
-  logic                              fifo_full;
-  logic                              fifo_empty;
+  /* Gated clock */
+  logic clk_cg;
+
+  /* Registers */
+  dma_reg2hw_t reg2hw;
+  dma_hw2reg_t hw2reg;
+
+  /* General signals */
+  logic dma_padding_fsm_on;
+  logic padding_fsm_done;
+
+  logic dma_start;
+  logic dma_done;
+  logic dma_window_event;
+
+  logic window_done_q;
+
+  logic data_in_req;
+  logic data_in_we;
+  logic [3:0] data_in_be;
+  logic [31:0] data_in_addr;
+  logic data_in_gnt;
+  logic data_in_rvalid;
+  logic [31:0] data_in_rdata;
 
-  logic                              fifo_addr_flush;
-  logic                              fifo_addr_full;
-  logic fifo_addr_empty, fifo_addr_empty_check;
+  logic data_addr_in_req;
+  logic data_addr_in_we;
+  logic [3:0] data_addr_in_be;
+  logic [31:0] data_addr_in_addr;
+  logic data_addr_in_gnt;
+  logic data_addr_in_rvalid;
+  logic [31:0] data_addr_in_rdata;
 
+  logic data_out_req;
+  logic data_out_we;
+  logic [3:0] data_out_be;
+  logic [31:0] data_out_addr;
+  logic [31:0] data_out_wdata;
+  logic data_out_gnt;
+  logic data_out_rvalid;
+  logic [31:0] data_out_rdata;
+
+  /* Interrupt Flag Register signals */
+  logic transaction_ifr;
+  logic dma_done_intr_n;
+  logic dma_done_intr;
+  logic window_ifr;
+  logic dma_window_intr;
+  logic dma_window_intr_n;
+
+  /* FIFO signals */
+  logic [Addr_Fifo_Depth-1:0] read_fifo_usage;
+  logic [Addr_Fifo_Depth-1:0] read_addr_fifo_usage;
+  logic [Addr_Fifo_Depth-1:0] write_fifo_usage;
+
+  logic fifo_flush;
+  logic read_fifo_full;
+  logic read_fifo_empty;
+  logic read_fifo_alm_full;
+  logic read_fifo_pop;
+  logic [31:0] read_fifo_input;
+  logic [31:0] read_fifo_output;
+
+  logic read_addr_fifo_full;
+  logic read_addr_fifo_empty;
+  logic read_addr_fifo_alm_full;
+  logic [31:0] read_addr_fifo_output;
+
+  logic write_fifo_full;
+  logic write_fifo_empty;
+  logic write_fifo_alm_full;
+  logic write_fifo_push;
+  logic write_fifo_pop;
+  logic [31:0] write_fifo_input;
+  logic [31:0] write_fifo_output;
+
+  /* Trigger signals */
   logic wait_for_rx;
   logic wait_for_tx;
 
+  /* Datatypes */
   typedef enum logic [1:0] {
     DMA_DATA_TYPE_WORD,
     DMA_DATA_TYPE_HALF_WORD,
@@ -173,21 +142,8 @@ module dma #(
     DMA_DATA_TYPE_BYTE_
   } dma_data_type_t;
 
-  dma_data_type_t        dst_data_type;
-  dma_data_type_t        src_data_type;
-
-  logic           [31:0] fifo_input;
-  logic           [31:0] fifo_addr_input;
-  logic           [31:0] fifo_output;
-  logic           [31:0] fifo_addr_output;
-
-  logic           [ 3:0] byte_enable_out;
-
-  logic                  circular_mode;
-  logic                  address_mode;
-
-  logic                  dma_start_pending;
 
+  /* FSM states */
   enum {
     DMA_READY,
     DMA_STARTING,
@@ -195,173 +151,195 @@ module dma #(
   }
       dma_state_q, dma_state_d;
 
-  /* Padding FSM states */
-
-  enum {
-    PAD_IDLE,
-    TOP_PAD_EXEC,
-    LEFT_PAD_EXEC,
-    RIGHT_PAD_EXEC,
-    BOTTOM_PAD_EXEC,
-    TOP_PAD_DONE,
-    LEFT_PAD_DONE,
-    RIGHT_PAD_DONE,
-    BOTTOM_PAD_DONE
-  }
-      pad_state_q, pad_state_d, pad_state_x;
-
-  enum logic {
-    DMA_READ_FSM_IDLE,
-    DMA_READ_FSM_ON
-  }
-      dma_read_fsm_state, dma_read_fsm_n_state, dma_read_addr_fsm_state, dma_read_addr_fsm_n_state;
+  logic circular_mode;
+  logic address_mode;
 
-  enum logic {
-    DMA_WRITE_FSM_IDLE,
-    DMA_WRITE_FSM_ON
-  }
-      dma_write_fsm_state, dma_write_fsm_n_state;
+  logic dma_start_pending;
 
-  logic [Addr_Fifo_Depth-1:0] outstanding_req, outstanding_addr_req;
   logic [31:0] window_counter;
 
-  assign dma_read_ch0_req_o.req = data_in_req && ~pad_fifo_on;
-  assign dma_read_ch0_req_o.we = data_in_we;
-  assign dma_read_ch0_req_o.be = data_in_be;
-  assign dma_read_ch0_req_o.addr = data_in_addr;
-  assign dma_read_ch0_req_o.wdata = 32'h0;
+  /*_________________________________________________________________________________________________________________________________ */
 
-  assign data_in_gnt = dma_read_ch0_resp_i.gnt || (data_in_gnt_virt & pad_fifo_on);
-  assign data_in_rvalid = dma_read_ch0_resp_i.rvalid || (data_in_rvalid_virt & pad_fifo_on);
-  assign data_in_rdata = dma_read_ch0_resp_i.rdata;
+  /* Module instantiation */
 
-  assign dma_addr_ch0_req_o.req = data_addr_in_req;
-  assign dma_addr_ch0_req_o.we = data_addr_in_we;
-  assign dma_addr_ch0_req_o.be = data_addr_in_be;
-  assign dma_addr_ch0_req_o.addr = data_addr_in_addr;
-  assign dma_addr_ch0_req_o.wdata = 32'h0;
+  /* Clock gating cell */
 
-  assign data_addr_in_gnt = dma_addr_ch0_resp_i.gnt;
-  assign data_addr_in_rvalid = dma_addr_ch0_resp_i.rvalid;
-  assign data_addr_in_rdata = dma_addr_ch0_resp_i.rdata;
+`ifndef FPGA_SYNTHESIS
+`ifndef VERILATOR
+  tc_clk_gating clk_gating_cell (
+      .clk_i,
+      .en_i(clk_gate_en_ni),
+      .test_en_i(1'b0),
+      .clk_o(clk_cg)
+  );
 
-  assign dma_write_ch0_req_o.req = data_out_req;
-  assign dma_write_ch0_req_o.we = data_out_we;
-  assign dma_write_ch0_req_o.be = data_out_be;
-  assign dma_write_ch0_req_o.addr = data_out_addr;
-  assign dma_write_ch0_req_o.wdata = data_out_wdata;
+`else
+  assign clk_cg = clk_i & clk_gate_en_ni;
+`endif
 
-  assign data_out_gnt = dma_write_ch0_resp_i.gnt;
-  assign data_out_rvalid = dma_write_ch0_resp_i.rvalid;
-  assign data_out_rdata = dma_write_ch0_resp_i.rdata;
+`else
+  assign clk_cg = clk_i & clk_gate_en_ni;
+`endif
 
-  assign dma_done_intr = transaction_ifr;
-  assign dma_window_intr = window_ifr;
 
-  assign dma_done_intr_o = dma_done_intr_n;
-  assign hw2reg.transaction_ifr.d = transaction_ifr;
-  assign dma_window_intr_o = dma_window_intr_n;
-  assign hw2reg.window_ifr.d = window_ifr;
 
-  assign dst_data_type = dma_data_type_t'(reg2hw.dst_data_type.q);
-  assign src_data_type = dma_data_type_t'(reg2hw.src_data_type.q);
+  /* Read FIFO */
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH),
+      .FALL_THROUGH(1'b1)
+  ) dma_read_fifo_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(read_fifo_full),
+      .empty_o(read_fifo_empty),
+      .usage_o(read_fifo_usage),
+      // as long as the queue is not full we can push new data
+      .data_i(read_fifo_input),
+      .push_i(data_in_rvalid),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(read_fifo_output),
+      .pop_i(read_fifo_pop)
+  );
 
-  assign hw2reg.status.ready.d = (dma_state_q == DMA_READY);
+  /* Read address mode FIFO */
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH),
+      .FALL_THROUGH(1'b1)
+  ) dma_read_addr_fifo_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(read_addr_fifo_full),
+      .empty_o(read_addr_fifo_empty),
+      .usage_o(read_addr_fifo_usage),
+      // as long as the queue is not full we can push new data
+      .data_i(data_addr_in_rdata),
+      .push_i(data_addr_in_rvalid),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(read_addr_fifo_output),
+      .pop_i(write_fifo_pop && address_mode)  // not an error!
+  );
 
-  assign hw2reg.status.window_done.d = window_done_q;
+  /* Write FIFO */
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH),
+      .FALL_THROUGH(1'b1)
+  ) dma_write_fifo_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(write_fifo_full),
+      .empty_o(write_fifo_empty),
+      .usage_o(write_fifo_usage),
+      // as long as the queue is not full we can push new data
+      .data_i(write_fifo_input),
+      .push_i(write_fifo_push),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(write_fifo_output),
+      .pop_i(write_fifo_pop)
+  );
 
-  assign circular_mode = reg2hw.mode.q == 1;
-  assign address_mode = reg2hw.mode.q == 2;
+  dma_reg_top #(
+      .reg_req_t(reg_req_t),
+      .reg_rsp_t(reg_rsp_t)
+  ) dma_reg_top_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg_req_i,
+      .reg_rsp_o,
+      .reg2hw,
+      .hw2reg,
+      .devmode_i(1'b1)
+  );
 
-  /* DMA Dimensionality configuration flags */
-  assign dma_conf_1d = reg2hw.dim_config.q == 0;
-  assign dma_conf_2d = reg2hw.dim_config.q == 1;
-
-  /* DMA read pointer source selection */
-  assign read_ptr_update_sel = reg2hw.dim_inv.q;
-
-  /* DMA 2D increment */
-  assign dma_src_d2_inc = reg2hw.src_ptr_inc_d2.q;
-  assign dma_src_d1_inc = reg2hw.src_ptr_inc_d1.q;
-  assign dma_dst_d2_inc = reg2hw.dst_ptr_inc_d2.q;
-  assign dma_dst_d1_inc = reg2hw.dst_ptr_inc_d1.q;
-
-  /* Sign extend flag */
-
-  assign sign_extend = reg2hw.sign_ext.q & ( (src_data_type[1] & ~dst_data_type[1]) | ((src_data_type[1] == dst_data_type[1]) & (src_data_type[0] & ~dst_data_type[0])));
-
-  /* Padding FSM conditions assignments */
-
-  assign idle_to_top_ex = {|reg2hw.pad_top.q == 1'b1 && dma_start == 1'b1};
-  assign idle_to_left_ex = {
-    |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b1 && dma_start == 1'b1
-  };
-  assign idle_to_right_ex = {
-    |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 
-                      && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
-  };
-  assign idle_to_bottom_ex = {
-    |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 
-                      && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
-  };
-  assign top_ex_to_top_dn = {
-    dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
-  };
-  assign top_ex_to_left_ex = {
-    dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b1
-  };
-  assign top_dn_to_right_ex = {
-    |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
-  };
-  assign top_dn_to_bottom_ex = {
-    |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
-  };
-  assign top_dn_to_idle = {
-    |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0
-  };
-  assign left_ex_to_left_dn = {
-    dma_src_cnt_d1 == ({1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
-  };
-  assign left_dn_to_left_ex = {
-    dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({14'h0, dma_dst_cnt_du} + {11'h0, reg2hw.pad_bottom.q}) && |reg2hw.pad_right.q == 1'b0
-  };
-  assign left_dn_to_right_ex = {
-    |reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
-  };
-  assign left_dn_to_bottom_ex = {
-    |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
-  };
-  assign left_dn_to_idle = {
-    |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0
-  };
-  assign right_ex_to_right_dn = {
-    dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
-  };
-  assign right_ex_to_left_ex = {
-    dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b1
-  };
-  assign right_ex_to_bottom_ex = {
-    |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
-  };
-  assign right_dn_to_right_ex = {
-    dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
-  };
-  assign right_dn_to_idle = {|reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0};
-  assign bottom_ex_to_idle = {
-    dma_src_cnt_d1 == {14'h0, dma_dst_cnt_du} && dma_src_cnt_d2 == {14'h0, dma_dst_cnt_du}
-  };
-
-  assign write_address = address_mode ? fifo_addr_output : write_ptr_reg;
+  /* Read FSM */
+  dma_obiread_fsm dma_obiread_fsm_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg2hw_i(reg2hw),
+      .dma_start_i(dma_start),
+      .dma_done_i(dma_done),
+      .ext_dma_stop_i,
+      .read_fifo_full_i(read_fifo_full),
+      .read_fifo_alm_full_i(read_fifo_alm_full),
+      .wait_for_rx_i(wait_for_rx),
+      .data_in_gnt_i(data_in_gnt),
+      .data_in_rvalid_i(data_in_rvalid),
+      .data_in_rdata_i(data_in_rdata),
+      .fifo_input_o(read_fifo_input),
+      .data_in_req_o(data_in_req),
+      .data_in_we_o(data_in_we),
+      .data_in_be_o(data_in_be),
+      .data_in_addr_o(data_in_addr),
+      .read_fifo_flush_o(fifo_flush)
+  );
 
-  assign wait_for_rx = |(reg2hw.slot.rx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i));
-  assign wait_for_tx = |(reg2hw.slot.tx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i));
+  /* Read address FSM */
+  dma_obiread_addr_fsm dma_obiread_addr_fsm_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg2hw_i(reg2hw),
+      .dma_start_i(dma_start),
+      .ext_dma_stop_i,
+      .read_fifo_addr_full_i(read_addr_fifo_full),
+      .read_fifo_addr_alm_full_i(read_addr_fifo_alm_full),
+      .address_mode_i(address_mode),
+      .data_in_gnt_i(data_addr_in_gnt),
+      .data_addr_in_req_o(data_addr_in_req),
+      .data_addr_in_we_o(data_addr_in_we),
+      .data_addr_in_be_o(data_addr_in_be),
+      .data_addr_in_addr_o(data_addr_in_addr)
+  );
 
-  assign fifo_addr_empty_check = fifo_addr_empty && address_mode;
+  /* DMA padding FSM */
+  dma_padding_fsm dma_padding_fsm_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg2hw_i(reg2hw),
+      .dma_padding_fsm_on_i(dma_padding_fsm_on),
+      .dma_start_i(dma_start),
+      .read_fifo_empty_i(read_fifo_empty),
+      .write_fifo_full_i(write_fifo_full),
+      .write_fifo_alm_full_i(write_fifo_alm_full),
+      .data_read_i(read_fifo_output),
+      .padding_fsm_done_o(padding_fsm_done),
+      .write_fifo_push_o(write_fifo_push),
+      .read_fifo_pop_o(read_fifo_pop),
+      .data_write_o(write_fifo_input)
+  );
+
+  /* Write FSM */
+  dma_obiwrite_fsm dma_obiwrite_fsm_i (
+      .clk_i(clk_cg),
+      .rst_ni,
+      .reg2hw_i(reg2hw),
+      .dma_start_i(dma_start),
+      .write_fifo_empty_i(write_fifo_empty),
+      .read_addr_fifo_empty_i(read_addr_fifo_empty),
+      .fifo_output_i(write_fifo_output),
+      .wait_for_tx_i(wait_for_tx),
+      .address_mode_i(address_mode),
+      .padding_fsm_done_i(padding_fsm_done),
+      .fifo_addr_output_i(read_addr_fifo_output),
+      .data_out_gnt_i(data_out_gnt),
+      .data_out_req_o(data_out_req),
+      .data_out_we_o(data_out_we),
+      .data_out_be_o(data_out_be),
+      .data_out_addr_o(data_out_addr),
+      .data_out_wdata_o(data_out_wdata),
+      .dma_done_o(dma_done)
+  );
 
-  assign fifo_alm_full = (fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
-  assign fifo_addr_alm_full = (fifo_addr_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
+  /*_________________________________________________________________________________________________________________________________ */
 
-  assign dma_start = (dma_state_q == DMA_STARTING);
+  /* FSMs instantiation */
 
   //
   // Main DMA state machine
@@ -393,7 +371,7 @@ module dma #(
   end
 
   /* Update DMA state */
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_cg, negedge rst_ni) begin
     if (~rst_ni) begin
       dma_state_q <= DMA_READY;
     end else begin
@@ -402,7 +380,7 @@ module dma #(
   end
 
   /* DMA pulse start when dma_start register is written */
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_start
+  always_ff @(posedge clk_cg or negedge rst_ni) begin : proc_dma_start
     if (~rst_ni) begin
       dma_start_pending <= 1'b0;
     end else begin
@@ -414,560 +392,8 @@ module dma #(
     end
   end
 
-  /*/ Store input data pointer and increment everytime read request is granted */
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_in_reg
-    if (~rst_ni) begin
-      read_ptr_reg <= '0;
-    end else begin
-      if (dma_start == 1'b1) begin
-        read_ptr_reg <= reg2hw.src_ptr.q;
-      end else if (data_in_gnt == 1'b1) begin
-        if (dma_conf_1d == 1'b1) begin
-          /* Increase the pointer by the amount written in ptr_inc */
-          read_ptr_reg <= read_ptr_reg + {26'h0, dma_src_d1_inc};
-        end else if (dma_conf_2d == 1'b1 && pad_cnt_on == 1'b0) begin
-          if (read_ptr_update_sel == 1'b0) begin
-            if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
-              /* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d1)*data_unit */
-              read_ptr_reg <= read_ptr_reg + {9'h0, dma_src_d2_inc};
-            end else begin
-              read_ptr_reg <= read_ptr_reg + {26'h0, dma_src_d1_inc}; /* Increment of the d1 increment (stride) */
-            end
-          end else begin
-            if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
-              /* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d2)*data_unit */
-              read_ptr_reg <= src_ptr_reg;
-            end else begin
-              read_ptr_reg <= read_ptr_reg + {9'h0, dma_src_d2_inc}; /* Increment of the d1 increment (stride) */
-            end
-          end
-        end
-      end
-    end
-  end
-
-  /* 
-   * Store input data pointer in source_ptr_reg and increment it every time read request is granted, 
-   * if the d1 has finished reading and the read pointer update is set to 1'b1 
-   */
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_src_ptr_reg
-    if (~rst_ni) begin
-      src_ptr_reg <= '0;
-    end else begin
-      if (dma_start == 1'b1) begin
-        src_ptr_reg <= reg2hw.src_ptr.q + {26'h0, dma_src_d1_inc};
-      end else if (data_in_gnt == 1'b1 && dma_conf_2d == 1'b1 && pad_cnt_on == 1'b0 && read_ptr_update_sel == 1'b1 &&
-                    (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1)) begin
-        src_ptr_reg <= src_ptr_reg + {26'h0, dma_src_d1_inc};
-      end
-    end
-  end
-
-  // Store address data pointer and increment everytime read request is granted - only in address mode
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_addr_reg
-    if (~rst_ni) begin
-      addr_ptr_reg <= '0;
-    end else begin
-      if (dma_start == 1'b1 && address_mode) begin
-        addr_ptr_reg <= reg2hw.addr_ptr.q;
-      end else if (data_addr_in_gnt == 1'b1 && address_mode) begin
-        addr_ptr_reg <= addr_ptr_reg + 32'h4;  //always continuos in 32b
-      end
-    end
-  end
-
-  // Only update read_ptr_valid_reg when the data is stored in the fifo.
-  // Since every input grant is followed by a rvalid, the read_ptr_valid_reg is a mere sample of the read_ptr_reg
-  // synched with the rvalid signal.
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_valid_in_reg
-    if (~rst_ni) begin
-      read_ptr_valid_reg <= '0;
-    end else begin
-      if (dma_start == 1'b1) begin
-        read_ptr_valid_reg <= reg2hw.src_ptr.q;
-      end else if (data_in_rvalid == 1'b1) begin
-        read_ptr_valid_reg <= read_ptr_reg;
-      end
-    end
-  end
-
-  // Store output data pointer and increment everytime write request is granted
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_out_reg
-    if (~rst_ni) begin
-      write_ptr_reg <= '0;
-    end else begin
-      if (dma_start == 1'b1) begin
-        write_ptr_reg <= reg2hw.dst_ptr.q;
-      end else if (data_out_gnt == 1'b1) begin
-        if (dma_conf_1d == 1'b1) begin
-          write_ptr_reg <= write_ptr_reg + {26'h0, dma_dst_d1_inc};
-        end else if (dma_conf_2d == 1'b1) begin
-          if (dma_dst_cnt_d1 == {14'h0, dma_dst_cnt_du}) begin
-            // In this case, the d1 is finished, so we need to increment the pointer by sizeof(d1)*data_unit*strides
-            write_ptr_reg <= write_ptr_reg + {9'h0, dma_dst_d2_inc};
-          end else begin
-            write_ptr_reg <= write_ptr_reg + {26'h0, dma_dst_d1_inc}; // Increment just of one du, since we need to increase the 1d
-          end
-        end
-      end
-    end
-  end
-
-  // Store dma transfer size and decrement it everytime input data rvalid is asserted.
-  // Perform additional checks for 2D DMA
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_src_cnt_reg
-    if (~rst_ni) begin
-      dma_src_cnt_d1 <= '0;
-      dma_src_cnt_d2 <= '0;
-    end else begin
-      if (dma_start == 1'b1) begin
-        dma_src_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
-        dma_src_cnt_d2 <= {1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_top.q} + {11'h0, reg2hw.pad_bottom.q};
-      end else if (data_in_gnt == 1'b1) begin
-        if (dma_conf_1d == 1'b1) begin
-          // 1D case
-          dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_src_cnt_du};
-        end else if (dma_conf_2d == 1'b1) begin
-          // 2D case
-          if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du}) begin
-            // In this case, the d1 is finished, so we need to decrement the d2 size and reset the d2 size
-            dma_src_cnt_d2 <= dma_src_cnt_d2 - {14'h0, dma_src_cnt_du};
-            dma_src_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
-          end else begin
-            // In this case, the d1 isn't finished, so we need to decrement the d1 size
-            dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_src_cnt_du};
-          end
-        end
-      end
-    end
-  end
-
-  // Store dma transfer size and decrement it everytime input data write request is granted.
-  // The need for two separate counters for reading and writing operations is due to the lack of synchronization between them.
-  // Since the check on the read side is done on the rvalid signal, we need only an additional counter, for d1.
-  // Performs additional checks for 2D DMA.
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_dst_cnt_reg
-    if (~rst_ni) begin
-      dma_dst_cnt_d1 <= '0;
-    end else begin
-      if (dma_start == 1'b1) begin
-        dma_dst_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
-      end else if (data_out_gnt == 1'b1) begin
-        if (dma_conf_1d == 1'b1) begin
-          // 1D case
-          dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_dst_cnt_du};
-        end else if (dma_conf_2d == 1'b1) begin
-          // 2D case
-          if (dma_dst_cnt_d1 == {14'h0, dma_dst_cnt_du}) begin
-            // In this case, the d1 is finished, so we need to reset the d2 size
-            dma_dst_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
-          end else begin
-            // In this case, the d1 isn't finished, so we need to decrement the d1 size
-            dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_dst_cnt_du};
-          end
-        end
-      end
-    end
-  end
-
-  // Store dma transfer size for the address port
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_addr_cnt_reg
-    if (~rst_ni) begin
-      dma_addr_cnt <= '0;
-    end else begin
-      if (dma_start == 1'b1 && address_mode) begin
-        dma_addr_cnt <= {16'h0, reg2hw.size_d1.q};
-      end else if (data_addr_in_gnt == 1'b1 && address_mode) begin
-        dma_addr_cnt <= dma_addr_cnt - 32'h4;  //address always 32b
-      end
-    end
-  end
-
-  always_comb begin
-    case (dst_data_type)
-      DMA_DATA_TYPE_WORD: dma_dst_cnt_du = 3'h4;
-      DMA_DATA_TYPE_HALF_WORD: dma_dst_cnt_du = 3'h2;
-      DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: dma_dst_cnt_du = 3'h1;
-    endcase
-  end
-
-  always_comb begin
-    case (src_data_type)
-      DMA_DATA_TYPE_WORD: dma_src_cnt_du = 3'h4;
-      DMA_DATA_TYPE_HALF_WORD: dma_src_cnt_du = 3'h2;
-      DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: dma_src_cnt_du = 3'h1;
-    endcase
-  end
-
-  always_comb begin : proc_byte_enable_out
-    case (dst_data_type)  // Data type 00 Word, 01 Half word, 11,10 byte
-      DMA_DATA_TYPE_WORD: byte_enable_out = 4'b1111;  // Writing a word (32 bits)
-
-      DMA_DATA_TYPE_HALF_WORD: begin  // Writing a half-word (16 bits)
-        case (write_address[1])
-          1'b0: byte_enable_out = 4'b0011;
-          1'b1: byte_enable_out = 4'b1100;
-        endcase
-        ;  // case(write_address[1:0])
-      end
-
-      DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: begin  // Writing a byte (8 bits)
-        case (write_address[1:0])
-          2'b00: byte_enable_out = 4'b0001;
-          2'b01: byte_enable_out = 4'b0010;
-          2'b10: byte_enable_out = 4'b0100;
-          2'b11: byte_enable_out = 4'b1000;
-        endcase
-        ;  // case(write_address[1:0])
-      end
-    endcase
-    ;  // case (dst_data_type)
-  end
-
-  // Output data shift
-  always_comb begin : proc_output_data
-
-    data_out_wdata[7:0]   = fifo_output[7:0];
-    data_out_wdata[15:8]  = fifo_output[15:8];
-    data_out_wdata[23:16] = fifo_output[23:16];
-    data_out_wdata[31:24] = fifo_output[31:24];
-
-    case (write_address[1:0])
-      2'b00: begin
-        if (sign_extend) begin
-          case ({
-            src_data_type, dst_data_type
-          })
-            {DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD} : ;
-            {
-              DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD
-            } :
-            data_out_wdata[31:16] = {16{fifo_output[15]}};
-            {
-              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_WORD
-            }, {
-              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_WORD
-            } :
-            data_out_wdata[31:8] = {24{fifo_output[7]}};
-            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
-            {
-              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
-            }, {
-              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
-            } :
-            data_out_wdata[15:8] = {8{fifo_output[7]}};
-            default: ;
-          endcase
-        end else begin
-          case ({
-            src_data_type, dst_data_type
-          })
-            {DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD} : ;
-            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD} : data_out_wdata[31:16] = 16'b0;
-            {
-              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_WORD
-            }, {
-              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_WORD
-            } :
-            data_out_wdata[31:8] = 24'b0;
-            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
-            {
-              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
-            }, {
-              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
-            } :
-            data_out_wdata[15:8] = 8'b0;
-            default: ;
-          endcase
-        end
-      end
-      2'b01: data_out_wdata[15:8] = fifo_output[7:0];  // Writing a byte, no need for sign extension
-      2'b10: begin  // Writing a half-word or a byte
-        data_out_wdata[23:16] = fifo_output[7:0];
-        data_out_wdata[31:24] = fifo_output[15:8];
-
-        if (sign_extend) begin
-          case ({
-            src_data_type, dst_data_type
-          })
-            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
-            {
-              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
-            }, {
-              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
-            } :
-            data_out_wdata[31:24] = {8{fifo_output[7]}};
-            default: ;
-          endcase
-        end else begin
-          case ({
-            src_data_type, dst_data_type
-          })
-            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
-            {
-              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
-            }, {
-              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
-            } :
-            data_out_wdata[31:24] = 8'b0;
-            default: ;
-          endcase
-        end
-      end
-      2'b11:
-      data_out_wdata[31:24] = fifo_output[7:0];  // Writing a byte, no need for sign extension
-    endcase
-  end
-
-
-  assign fifo_addr_input = data_addr_in_rdata;  //never misaligned, always 32b
-
-  // Input data shift: shift the input data to be on the LSB of the fifo
-  always_comb begin : proc_input_data
-
-    if (pad_fifo_on) begin
-      fifo_input = 32'h0;
-    end else begin
-      fifo_input[7:0]   = data_in_rdata[7:0];
-      fifo_input[15:8]  = data_in_rdata[15:8];
-      fifo_input[23:16] = data_in_rdata[23:16];
-      fifo_input[31:24] = data_in_rdata[31:24];
-
-      case (read_ptr_valid_reg[1:0])
-        2'b00: ;
-        2'b01: fifo_input[7:0] = data_in_rdata[15:8];
-
-        2'b10: begin
-          fifo_input[7:0]  = data_in_rdata[23:16];
-          fifo_input[15:8] = data_in_rdata[31:24];
-        end
-
-        2'b11: fifo_input[7:0] = data_in_rdata[31:24];
-      endcase
-    end
-  end
-
-  // FSM state update
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_fsm_state
-    if (~rst_ni) begin
-      dma_read_fsm_state <= DMA_READ_FSM_IDLE;
-      dma_write_fsm_state <= DMA_WRITE_FSM_IDLE;
-      dma_read_addr_fsm_state <= DMA_READ_FSM_IDLE;
-      outstanding_req <= '0;
-      outstanding_addr_req <= '0;
-    end else begin
-      dma_read_fsm_state <= dma_read_fsm_n_state;
-      dma_write_fsm_state <= dma_write_fsm_n_state;
-      dma_read_addr_fsm_state <= dma_read_addr_fsm_n_state;
-
-      outstanding_req <= outstanding_req + (data_in_req && data_in_gnt) - data_in_rvalid;
-
-      if (address_mode)
-        outstanding_addr_req <= outstanding_addr_req + (data_addr_in_req && data_addr_in_gnt) - data_addr_in_rvalid;
-
-    end
-  end
-
-  /* Padding synchronization signal generation 
-   * When the pad_fifo_on is asserted, this logic mimics the behaviour of the data_in_rvalid and data_in_gnt signals
-   * coming from the memory. This is done in order to keep the read/write operations working even without an
-   * actual response from memory, reducing power consumptionnby avoiding unnecessary memory accesses.
-   */
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pad_sync_signal
-    if (~rst_ni) begin
-      data_in_rvalid_virt <= 1'b0;
-      data_in_rvalid_virt_n <= 1'b1;
-      data_in_rvalid_virt_n_n <= 1'b0;
-      data_in_gnt_virt <= 1'b1;
-      data_in_gnt_virt_n <= 1'b0;
-      data_in_gnt_virt_n_n <= 1'b0;
-    end else begin
-      if (data_in_req == 1'b1 && pad_fifo_on == 1'b1) begin
-        data_in_rvalid_virt <= data_in_rvalid_virt_n;
-        data_in_rvalid_virt_n <= data_in_rvalid_virt_n_n;
-        data_in_rvalid_virt_n_n <= data_in_rvalid;
-        data_in_gnt_virt <= data_in_gnt_virt_n;
-        data_in_gnt_virt_n <= data_in_gnt_virt_n_n;
-        data_in_gnt_virt_n_n <= data_in_gnt;
-      end else begin
-        data_in_rvalid_virt <= 1'b0;
-        data_in_rvalid_virt_n <= 1'b1;
-        data_in_rvalid_virt_n_n <= 1'b0;
-        data_in_gnt_virt <= 1'b1;
-        data_in_gnt_virt_n <= 1'b0;
-        data_in_gnt_virt_n_n <= 1'b0;
-      end
-    end
-  end
-
-  // Padding FSM state update
-  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pad_state
-    if (~rst_ni) begin
-      pad_state_q <= PAD_IDLE;
-      pad_state_x <= PAD_IDLE;
-    end else if (dma_conf_2d == 1'b1) begin
-      if (dma_start == 1'b1 && |reg2hw.pad_top.q == 1'b1) begin
-        pad_state_q <= TOP_PAD_EXEC;
-        pad_state_x <= TOP_PAD_EXEC;
-      end else if (dma_start == 1'b1 && |reg2hw.pad_left.q == 1'b1) begin
-        pad_state_q <= LEFT_PAD_EXEC;
-        pad_state_x <= LEFT_PAD_EXEC;
-      end else begin
-        pad_state_x <= pad_state_d;
-        if (data_in_rvalid == 1'b1) begin
-          pad_state_q <= pad_state_x;
-        end
-      end
-    end
-  end
-
-  // Pad fifo flag logic
-  always_comb begin : proc_pad_fifo_on
-    if (dma_conf_2d == 1'b1) begin
-      case (pad_state_q)
-        TOP_PAD_EXEC, LEFT_PAD_EXEC, RIGHT_PAD_EXEC, BOTTOM_PAD_EXEC: pad_fifo_on = 1'b1;
-
-        default: pad_fifo_on = 1'b0;
-      endcase
-    end else begin
-      pad_fifo_on = 1'b0;
-    end
-  end
-
-  // Pad counter flag logic
-  always_comb begin : proc_pad_cnt_on
-    case (pad_state_q)
-      PAD_IDLE: begin
-        if (idle_to_right_ex || idle_to_bottom_ex || idle_to_left_ex || idle_to_top_ex) begin
-          pad_cnt_on = 1'b1;
-        end else begin
-          pad_cnt_on = pad_fifo_on;
-        end
-      end
-
-      TOP_PAD_DONE: begin
-        if (top_dn_to_right_ex) begin
-          pad_cnt_on = 1'b1;
-        end else begin
-          pad_cnt_on = pad_fifo_on;
-        end
-      end
-
-      LEFT_PAD_DONE: begin
-        if (left_dn_to_right_ex) begin
-          pad_cnt_on = 1'b1;
-        end else begin
-          pad_cnt_on = pad_fifo_on;
-        end
-      end
-
-      RIGHT_PAD_DONE: begin
-        if (right_dn_to_right_ex) begin
-          pad_cnt_on = 1'b1;
-        end else begin
-          pad_cnt_on = pad_fifo_on;
-        end
-      end
-
-      RIGHT_PAD_EXEC: begin
-        if (right_ex_to_right_dn || right_ex_to_left_ex) begin
-          pad_cnt_on = 1'b0;
-        end else begin
-          pad_cnt_on = pad_fifo_on;
-        end
-      end
-
-      default: pad_cnt_on = pad_fifo_on;
-    endcase
-  end
-
-  // Padding FSM logic
-  always_comb begin : proc_pad_fsm_logic
-    if (dma_conf_1d == 1'b1) begin
-      pad_state_d = PAD_IDLE;
-    end else begin
-      if (dma_start == 1'b1 && |reg2hw.pad_top.q == 1'b1) begin
-        pad_state_d = TOP_PAD_EXEC;
-      end else if (dma_start == 1'b1 && |reg2hw.pad_left.q == 1'b1) begin
-        pad_state_d = LEFT_PAD_EXEC;
-      end else begin
-        pad_state_d = pad_state_x;
-      end
-    end
-
-    unique case (pad_state_x)
-      PAD_IDLE: begin
-        if (idle_to_top_ex) begin
-          pad_state_d = TOP_PAD_EXEC;
-        end else if (idle_to_left_ex) begin
-          pad_state_d = LEFT_PAD_EXEC;
-        end else if (idle_to_right_ex) begin
-          pad_state_d = RIGHT_PAD_EXEC;
-        end else if (idle_to_bottom_ex) begin
-          pad_state_d = BOTTOM_PAD_EXEC;
-        end
-      end
-
-      TOP_PAD_EXEC: begin
-        if (top_ex_to_left_ex) begin
-          pad_state_d = LEFT_PAD_EXEC;
-        end else if (top_ex_to_top_dn) begin
-          pad_state_d = TOP_PAD_DONE;
-        end
-      end
-      TOP_PAD_DONE: begin
-        if (top_dn_to_right_ex) begin
-          pad_state_d = RIGHT_PAD_EXEC;
-        end else if (top_dn_to_bottom_ex) begin
-          pad_state_d = BOTTOM_PAD_EXEC;
-        end else if (top_dn_to_idle) begin
-          pad_state_d = PAD_IDLE;
-        end
-      end
-      LEFT_PAD_EXEC: begin
-        if (left_ex_to_left_dn) begin
-          pad_state_d = LEFT_PAD_DONE;
-        end
-      end
-      LEFT_PAD_DONE: begin
-        if (left_dn_to_right_ex) begin
-          pad_state_d = RIGHT_PAD_EXEC;
-        end else if (left_dn_to_bottom_ex) begin
-          pad_state_d = BOTTOM_PAD_EXEC;
-        end else if (left_dn_to_left_ex) begin
-          pad_state_d = LEFT_PAD_EXEC;
-        end else if (left_dn_to_idle) begin
-          pad_state_d = PAD_IDLE;
-        end
-      end
-      RIGHT_PAD_EXEC: begin
-        if (right_ex_to_right_dn) begin
-          pad_state_d = RIGHT_PAD_DONE;
-        end else if (right_ex_to_left_ex) begin
-          pad_state_d = LEFT_PAD_EXEC;
-        end else if (right_ex_to_bottom_ex) begin
-          pad_state_d = BOTTOM_PAD_EXEC;
-        end
-      end
-      RIGHT_PAD_DONE: begin
-        if (right_dn_to_idle) begin
-          pad_state_d = PAD_IDLE;
-        end else if (right_dn_to_right_ex) begin
-          pad_state_d = RIGHT_PAD_EXEC;
-        end
-      end
-      BOTTOM_PAD_EXEC: begin
-        if (bottom_ex_to_idle) begin
-          pad_state_d = PAD_IDLE;
-        end
-      end
-    endcase
-  end
-
   /* Transaction IFR update */
-  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_transaction_ifr
+  always_ff @(posedge clk_cg, negedge rst_ni) begin : proc_ff_transaction_ifr
     if (~rst_ni) begin
       transaction_ifr <= '0;
     end else if (reg2hw.interrupt_en.transaction_done.q == 1'b1) begin
@@ -982,7 +408,7 @@ module dma #(
   end
 
   /* Delayed transaction interrupt signals */
-  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_intr
+  always_ff @(posedge clk_cg, negedge rst_ni) begin : proc_ff_intr
     if (~rst_ni) begin
       dma_done_intr_n <= '0;
     end else begin
@@ -991,7 +417,7 @@ module dma #(
   end
 
   /* Window IFR update */
-  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_window_ifr
+  always_ff @(posedge clk_cg, negedge rst_ni) begin : proc_ff_window_ifr
     if (~rst_ni) begin
       window_ifr <= '0;
     end else if (reg2hw.interrupt_en.window_done.q == 1'b1) begin
@@ -1006,7 +432,7 @@ module dma #(
   end
 
   /* Delayed window interrupt signals */
-  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_window_intr
+  always_ff @(posedge clk_cg, negedge rst_ni) begin : proc_ff_window_intr
     if (~rst_ni) begin
       dma_window_intr_n <= '0;
     end else begin
@@ -1014,211 +440,8 @@ module dma #(
     end
   end
 
-  // Read master FSM
-  always_comb begin : proc_dma_read_fsm_logic
-
-    dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
-
-    data_in_req = '0;
-    data_in_we = '0;
-    data_in_be = '0;
-    data_in_addr = '0;
-
-    fifo_flush = 1'b0;
-
-    unique case (dma_read_fsm_state)
-
-      DMA_READ_FSM_IDLE: begin
-        // Wait for start signal
-        if (dma_start == 1'b1) begin
-          dma_read_fsm_n_state = DMA_READ_FSM_ON;
-          fifo_flush = 1'b1;
-        end else begin
-          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
-        end
-      end
-      // Read one word
-      DMA_READ_FSM_ON: begin
-        // If all input data read exit
-        if (ext_dma_stop_i == 1'b0) begin
-          if (dma_conf_1d == 1'b1) begin
-            // 1D DMA case
-            if (|dma_src_cnt_d1 == 1'b0) begin
-              dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
-            end else begin
-              dma_read_fsm_n_state = DMA_READ_FSM_ON;
-              // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
-              if (fifo_full == 1'b0 && fifo_alm_full == 1'b0 && wait_for_rx == 1'b0) begin
-                data_in_req  = 1'b1;
-                data_in_we   = 1'b0;
-                data_in_be   = 4'b1111;  // always read all bytes
-                data_in_addr = read_ptr_reg;
-              end
-            end
-          end else if (dma_conf_2d == 1'b1) begin
-            // 2D DMA case: exit only if both 1d and 2d counters are at 0
-            if (dma_src_cnt_d1 == {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q} && |dma_src_cnt_d2 == 1'b0) begin
-              dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
-            end else begin
-              // The read operation is the same in both cases
-              dma_read_fsm_n_state = DMA_READ_FSM_ON;
-              // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
-              if (fifo_full == 1'b0 && fifo_alm_full == 1'b0 && wait_for_rx == 1'b0) begin
-                data_in_req  = 1'b1;
-                data_in_we   = 1'b0;
-                data_in_be   = 4'b1111;  // always read all bytes
-                data_in_addr = read_ptr_reg;
-              end
-            end
-          end
-        end else begin
-          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
-        end
-      end
-    endcase
-  end
-
-  // Read address master FSM
-  always_comb begin : proc_dma_addr_read_fsm_logic
-
-    dma_read_addr_fsm_n_state = DMA_READ_FSM_IDLE;
-
-    data_addr_in_req = '0;
-    data_addr_in_we = '0;
-    data_addr_in_be = '0;
-    data_addr_in_addr = '0;
-
-    fifo_addr_flush = 1'b0;
-
-    unique case (dma_read_addr_fsm_state)
-
-      DMA_READ_FSM_IDLE: begin
-        // Wait for start signal
-        if (dma_start == 1'b1 && address_mode) begin
-          dma_read_addr_fsm_n_state = DMA_READ_FSM_ON;
-          fifo_addr_flush = 1'b1;
-        end else begin
-          dma_read_addr_fsm_n_state = DMA_READ_FSM_IDLE;
-        end
-      end
-      // Read one word
-      DMA_READ_FSM_ON: begin
-        // If all input data read exit
-        if (|dma_addr_cnt == 1'b0) begin
-          dma_read_addr_fsm_n_state = DMA_READ_FSM_IDLE;
-        end else begin
-          dma_read_addr_fsm_n_state = DMA_READ_FSM_ON;
-          // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
-          if (fifo_addr_full == 1'b0 && fifo_addr_alm_full == 1'b0) begin
-            data_addr_in_req  = 1'b1;
-            data_addr_in_we   = 1'b0;
-            data_addr_in_be   = 4'b1111;  // always read all bytes
-            data_addr_in_addr = addr_ptr_reg;
-          end
-        end
-      end
-    endcase
-  end
-
-  // Write master FSM
-  always_comb begin : proc_dma_write_fsm_logic
-
-    dma_write_fsm_n_state = DMA_WRITE_FSM_IDLE;
-    dma_done = 1'b0;
-
-    data_out_req = '0;
-    data_out_we = '0;
-    data_out_be = '0;
-    data_out_addr = '0;
-
-    unique case (dma_write_fsm_state)
-
-      DMA_WRITE_FSM_IDLE: begin
-        // Wait for start signal
-        if (dma_start == 1'b1) begin
-          dma_write_fsm_n_state = DMA_WRITE_FSM_ON;
-        end else begin
-          dma_write_fsm_n_state = DMA_WRITE_FSM_IDLE;
-        end
-      end
-      // Read one word
-      DMA_WRITE_FSM_ON: begin
-        // If all input data read exit
-        if (fifo_empty == 1'b1 && dma_read_fsm_state == DMA_READ_FSM_IDLE) begin
-          dma_done = outstanding_req == '0 && outstanding_addr_req == '0;
-          // If all input data has been read (dma_read_fsm_state == DMA_READ_FSM_IDLE, set when all data has been read) 
-          // and all requests have been granted, (outstanding_req == 0) then we are done
-          dma_write_fsm_n_state = dma_done ? DMA_WRITE_FSM_IDLE : DMA_WRITE_FSM_ON;
-        end else begin
-          dma_write_fsm_n_state = DMA_WRITE_FSM_ON;
-          // Wait if fifo is empty or if the SPI TX is not ready for new data (only in SPI mode 2).
-          if (fifo_empty == 1'b0 && wait_for_tx == 1'b0 && fifo_addr_empty_check == 1'b0) begin
-            data_out_req  = 1'b1;
-            data_out_we   = 1'b1;
-            data_out_be   = byte_enable_out;
-            data_out_addr = write_address;
-          end
-        end
-      end
-    endcase
-  end
-
-  fifo_v3 #(
-      .DEPTH(FIFO_DEPTH)
-  ) dma_fifo_i (
-      .clk_i,
-      .rst_ni,
-      .flush_i(fifo_flush),
-      .testmode_i(1'b0),
-      // status flags
-      .full_o(fifo_full),
-      .empty_o(fifo_empty),
-      .usage_o(fifo_usage),
-      // as long as the queue is not full we can push new data
-      .data_i(fifo_input),
-      .push_i(data_in_rvalid),
-      // as long as the queue is not empty we can pop new elements
-      .data_o(fifo_output),
-      .pop_i(data_out_gnt)
-  );
-
-  fifo_v3 #(
-      .DEPTH(FIFO_DEPTH)
-  ) dma_addr_fifo_i (
-      .clk_i,
-      .rst_ni,
-      .flush_i(fifo_addr_flush),
-      .testmode_i(1'b0),
-      // status flags
-      .full_o(fifo_addr_full),
-      .empty_o(fifo_addr_empty),
-      .usage_o(fifo_addr_usage),
-      // as long as the queue is not full we can push new data
-      .data_i(fifo_addr_input),
-      .push_i(data_addr_in_rvalid),
-      // as long as the queue is not empty we can pop new elements
-      .data_o(fifo_addr_output),
-      .pop_i(data_out_gnt && address_mode)
-  );
 
-  dma_reg_top #(
-      .reg_req_t(reg_req_t),
-      .reg_rsp_t(reg_rsp_t)
-  ) dma_reg_top_i (
-      .clk_i,
-      .rst_ni,
-      .reg_req_i,
-      .reg_rsp_o,
-      .reg2hw,
-      .hw2reg,
-      .devmode_i(1'b1)
-  );
-
-  // WINDOW EVENT
-  // Count gnt write transaction and generate event pulse if WINDOW_SIZE is reached
-  assign dma_window_event = |reg2hw.window_size.q &  data_out_gnt & (window_counter + 'h1 >= {19'h0, reg2hw.window_size.q});
-
-  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_dma_window_cnt
+  always_ff @(posedge clk_cg, negedge rst_ni) begin : proc_dma_window_cnt
     if (~rst_ni) begin
       window_counter <= 'h0;
     end else begin
@@ -1251,7 +474,7 @@ module dma #(
   // update window_done flag
   // set on dma_window_event
   // reset on read
-  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_dma_window_done
+  always_ff @(posedge clk_cg, negedge rst_ni) begin : proc_dma_window_done
     if (~rst_ni) begin
       window_done_q <= 1'b0;
     end else begin
@@ -1260,5 +483,84 @@ module dma #(
     end
   end
 
+  always_ff @(posedge clk_cg, negedge rst_ni) begin
+    if (~rst_ni) begin
+      dma_padding_fsm_on <= 1'b0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        dma_padding_fsm_on <= 1'b1;
+      end else if (dma_done == 1'b1) begin
+        dma_padding_fsm_on <= 1'b0;
+      end
+    end
+  end
+
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  assign dma_done_o = dma_done;
+  assign dma_start = (dma_state_q == DMA_STARTING);
+
+  /* OBI signals */
+  assign dma_read_req_o.req = data_in_req;
+  assign dma_read_req_o.we = data_in_we;
+  assign dma_read_req_o.be = data_in_be;
+  assign dma_read_req_o.addr = data_in_addr;
+  assign dma_read_req_o.wdata = 32'h0;
+
+  assign data_in_gnt = dma_read_resp_i.gnt;
+  assign data_in_rvalid = dma_read_resp_i.rvalid;
+  assign data_in_rdata = dma_read_resp_i.rdata;
+
+  assign dma_addr_req_o.req = data_addr_in_req;
+  assign dma_addr_req_o.we = data_addr_in_we;
+  assign dma_addr_req_o.be = data_addr_in_be;
+  assign dma_addr_req_o.addr = data_addr_in_addr;
+  assign dma_addr_req_o.wdata = 32'h0;
+
+  assign data_addr_in_gnt = dma_addr_resp_i.gnt;
+  assign data_addr_in_rvalid = dma_addr_resp_i.rvalid;
+  assign data_addr_in_rdata = dma_addr_resp_i.rdata;
+
+  assign dma_write_req_o.req = data_out_req;
+  assign dma_write_req_o.we = data_out_we;
+  assign dma_write_req_o.be = data_out_be;
+  assign dma_write_req_o.addr = data_out_addr;
+  assign dma_write_req_o.wdata = data_out_wdata;
+
+  assign data_out_gnt = dma_write_resp_i.gnt;
+  assign data_out_rvalid = dma_write_resp_i.rvalid;
+  assign data_out_rdata = dma_write_resp_i.rdata;
+
+  /* FIFO signals */
+  assign write_fifo_pop = (dma_state_q == DMA_RUNNING) & data_out_gnt; // @TOD0: check if this is correct
+
+  assign dma_done_intr = transaction_ifr;
+  assign dma_done_intr_o = dma_done_intr_n;
+  assign dma_window_intr = window_ifr;
+  assign dma_window_intr_o = dma_window_intr_n;
+
+  assign hw2reg.transaction_ifr.d = transaction_ifr;
+  assign hw2reg.window_ifr.d = window_ifr;
+
+  assign hw2reg.status.ready.d = (dma_state_q == DMA_READY);
+  assign hw2reg.status.window_done.d = window_done_q;
+
+  assign circular_mode = reg2hw.mode.q == 1;
+  assign address_mode = reg2hw.mode.q == 2;
+
+  assign wait_for_rx = |(reg2hw.slot.rx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i));
+  assign wait_for_tx = |(reg2hw.slot.tx_trigger_slot.q[SLOT_NUM-1:0] & (~trigger_slot_i));
+
+  assign read_fifo_alm_full = (read_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
+  assign read_addr_fifo_alm_full = (read_addr_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
+  assign write_fifo_alm_full = (write_fifo_usage == LastFifoUsage[Addr_Fifo_Depth-1:0]);
+
+
+  // WINDOW EVENT
+  // Count gnt write transaction and generate event pulse if WINDOW_SIZE is reached
+  assign dma_window_event = |reg2hw.window_size.q &  data_out_gnt & (window_counter + 'h1 >= {19'h0, reg2hw.window_size.q});
 
 endmodule : dma
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_addr_fsm.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_addr_fsm.sv
new file mode 100644
index 00000000..7eb3e635
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_addr_fsm.sv
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Reading FSM for DMA channel in address mode, controls the input FIFO.
+ */
+
+module dma_obiread_addr_fsm
+  import dma_reg_pkg::*;
+#(
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input dma_reg2hw_t reg2hw_i,
+    input logic dma_start_i,
+    input logic ext_dma_stop_i,
+    input logic read_fifo_addr_full_i,
+    input logic read_fifo_addr_alm_full_i,
+    input logic address_mode_i,
+    input logic data_in_gnt_i,
+    output logic data_addr_in_req_o,
+    output logic data_addr_in_we_o,
+    output logic [3:0] data_addr_in_be_o,
+    output logic [31:0] data_addr_in_addr_o
+);
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Parameter definition */
+
+  import dma_reg_pkg::*;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* Registers */
+  dma_reg2hw_t reg2hw;
+
+  /* Control signals */
+  logic dma_start;
+  logic ext_dma_stop;
+
+  enum logic {
+    DMA_READ_FSM_IDLE,
+    DMA_READ_FSM_ON
+  }
+      dma_read_addr_fsm_state, dma_read_addr_fsm_n_state;
+
+  logic fifo_addr_full;
+  logic fifo_addr_alm_full;
+
+  logic data_addr_in_gnt;
+  logic data_addr_in_req;
+  logic data_addr_in_we;
+  logic [3:0] data_addr_in_be;
+  logic [31:0] data_addr_in_addr;
+
+  logic address_mode;
+  logic [31:0] addr_ptr_reg;
+  logic [31:0] dma_addr_cnt;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* FSMs instantiation */
+
+  // Store address data pointer and increment everytime read request is granted - only in address mode
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_addr_reg
+    if (~rst_ni) begin
+      addr_ptr_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1 && address_mode) begin
+        addr_ptr_reg <= reg2hw.addr_ptr.q;
+      end else if (data_addr_in_gnt == 1'b1 && address_mode) begin
+        addr_ptr_reg <= addr_ptr_reg + 32'h4;  //always continuos in 32b
+      end
+    end
+  end
+
+  // Store dma transfer size for the address port
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_addr_cnt_reg
+    if (~rst_ni) begin
+      dma_addr_cnt <= '0;
+    end else begin
+      if (dma_start == 1'b1 && address_mode) begin
+        dma_addr_cnt <= {16'h0, reg2hw.size_d1.q};
+      end else if (data_addr_in_gnt == 1'b1 && address_mode) begin
+        dma_addr_cnt <= dma_addr_cnt - 1;  //address always 32b
+      end
+    end
+  end
+
+  // FSM state update
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_fsm_state
+    if (~rst_ni) begin
+      dma_read_addr_fsm_state <= DMA_READ_FSM_IDLE;
+    end else begin
+      dma_read_addr_fsm_state <= dma_read_addr_fsm_n_state;
+    end
+  end
+
+  // Read address master FSM
+  always_comb begin : proc_dma_addr_read_fsm_logic
+
+    dma_read_addr_fsm_n_state = DMA_READ_FSM_IDLE;
+
+    data_addr_in_req = '0;
+    data_addr_in_we = '0;
+    data_addr_in_be = '0;
+    data_addr_in_addr = '0;
+
+
+    unique case (dma_read_addr_fsm_state)
+
+      DMA_READ_FSM_IDLE: begin
+        // Wait for start signal
+        if (dma_start == 1'b1 && address_mode) begin
+          dma_read_addr_fsm_n_state = DMA_READ_FSM_ON;
+        end else begin
+          dma_read_addr_fsm_n_state = DMA_READ_FSM_IDLE;
+        end
+      end
+      // Read one word
+      DMA_READ_FSM_ON: begin
+        if (ext_dma_stop == 1'b0) begin
+          // If all input data read exit
+          if (|dma_addr_cnt == 1'b0) begin
+            dma_read_addr_fsm_n_state = DMA_READ_FSM_IDLE;
+          end else begin
+            dma_read_addr_fsm_n_state = DMA_READ_FSM_ON;
+            // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
+            if (fifo_addr_full == 1'b0 && fifo_addr_alm_full == 1'b0) begin
+              data_addr_in_req  = 1'b1;
+              data_addr_in_we   = 1'b0;
+              data_addr_in_be   = 4'b1111;  // always read all bytes
+              data_addr_in_addr = addr_ptr_reg;
+            end
+          end
+        end else begin
+          dma_read_addr_fsm_n_state = DMA_READ_FSM_IDLE;
+        end
+      end
+    endcase
+  end
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  /* Renaming */
+  assign address_mode = address_mode_i;
+  assign reg2hw = reg2hw_i;
+  assign data_addr_in_gnt = data_in_gnt_i;
+  assign fifo_addr_full = read_fifo_addr_full_i;
+  assign fifo_addr_alm_full = read_fifo_addr_alm_full_i;
+  assign dma_start = dma_start_i;
+  assign ext_dma_stop = ext_dma_stop_i;
+  assign data_addr_in_be_o = data_addr_in_be;
+  assign data_addr_in_addr_o = data_addr_in_addr;
+  assign data_addr_in_req_o = data_addr_in_req;
+  assign data_addr_in_we_o = data_addr_in_we;
+
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_fsm.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_fsm.sv
new file mode 100644
index 00000000..15103796
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiread_fsm.sv
@@ -0,0 +1,313 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Reading FSM for DMA channel, controls the input FIFO.
+ */
+
+module dma_obiread_fsm
+  import dma_reg_pkg::*;
+#(
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input dma_reg2hw_t reg2hw_i,
+    input logic dma_start_i,
+    input logic dma_done_i,
+    input logic ext_dma_stop_i,
+    input logic read_fifo_full_i,
+    input logic read_fifo_alm_full_i,
+    input logic wait_for_rx_i,
+    input logic data_in_gnt_i,
+    input logic data_in_rvalid_i,
+    input logic [31:0] data_in_rdata_i,
+
+    output logic [31:0] fifo_input_o,
+    output logic data_in_req_o,
+    output logic data_in_we_o,
+    output logic [3:0] data_in_be_o,
+    output logic [31:0] data_in_addr_o,
+    output logic read_fifo_flush_o
+);
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Parameter definition */
+
+  import dma_reg_pkg::*;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* Registers */
+  dma_reg2hw_t reg2hw;
+
+  enum logic {
+    DMA_READ_FSM_IDLE,
+    DMA_READ_FSM_ON
+  }
+      dma_read_fsm_state, dma_read_fsm_n_state;
+
+  logic data_in_gnt;
+  logic fifo_full;
+  logic fifo_alm_full;
+  logic fifo_flush;
+  logic dma_start;
+  logic ext_dma_stop;
+  logic read_ptr_update_sel;
+  logic dma_conf_1d;
+  logic dma_conf_2d;
+  logic data_in_rvalid;
+
+  logic wait_for_rx;
+
+  logic [16:0] dma_src_cnt_d1;
+  logic [16:0] dma_src_cnt_d2;
+
+  logic [31:0] trsp_src_ptr_reg;
+  logic [31:0] read_ptr_reg;
+
+  logic data_in_req;
+  logic data_in_we;
+  logic [3:0] data_in_be;
+  logic [31:0] data_in_addr;
+  logic [31:0] data_in_rdata;
+
+  logic [31:0] read_ptr_valid_reg;
+  logic [31:0] dma_src_d1_inc;
+  logic [31:0] dma_src_d2_inc;
+
+  /* FIFO signals */
+  logic [31:0] fifo_input;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* FSMs instantiation */
+
+  /* Sign extension of the increments */
+  always_comb begin
+    dma_src_d1_inc = {{26{reg2hw.src_ptr_inc_d1.q[5]}}, reg2hw.src_ptr_inc_d1.q};
+    dma_src_d2_inc = {{9{reg2hw.src_ptr_inc_d2.q[22]}}, reg2hw.src_ptr_inc_d2.q};
+  end
+
+  /* Counters for the reading fsm */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_src_cnt_reg
+    if (~rst_ni) begin
+      dma_src_cnt_d1 <= '0;
+      dma_src_cnt_d2 <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        dma_src_cnt_d1 <= {1'h0, reg2hw.size_d1.q};
+        dma_src_cnt_d2 <= {1'h0, reg2hw.size_d2.q};
+      end else if (dma_done_i == 1'b1) begin
+        dma_src_cnt_d1 <= '0;
+        dma_src_cnt_d2 <= '0;
+      end else if (data_in_gnt == 1'b1) begin
+        if (dma_conf_1d == 1'b1) begin
+          // 1D case
+          dma_src_cnt_d1 <= dma_src_cnt_d1 - 1;
+        end else if (dma_conf_2d == 1'b1) begin
+          // 2D case
+          if (dma_src_cnt_d1 == 1) begin
+            // In this case, the d1 is finished, so we need to decrement the d2 size and reset the d2 size
+            dma_src_cnt_d2 <= dma_src_cnt_d2 - 1;
+            dma_src_cnt_d1 <= {1'h0, reg2hw.size_d1.q};
+          end else begin
+            // In this case, the d1 isn't finished, so we need to decrement the d1 size
+            dma_src_cnt_d1 <= dma_src_cnt_d1 - 1;
+          end
+        end
+      end
+    end
+  end
+
+  /* 
+   * Store input data pointer in source_ptr_reg and increment it every time read request is granted, 
+   * if the d1 has finished reading and the read pointer update is set to 1'b1 
+   */
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_src_ptr_reg
+    if (~rst_ni) begin
+      trsp_src_ptr_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        trsp_src_ptr_reg <= reg2hw.src_ptr.q + dma_src_d1_inc;
+      end else if (data_in_gnt == 1'b1 && dma_conf_2d == 1'b1 && read_ptr_update_sel == 1'b1 &&
+                    (dma_src_cnt_d1 == 1 && |dma_src_cnt_d2 == 1'b1)) begin
+        trsp_src_ptr_reg <= trsp_src_ptr_reg + dma_src_d1_inc;
+      end
+    end
+  end
+
+  /* Store input data pointer and increment everytime read request is granted */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_in_reg
+    if (~rst_ni) begin
+      read_ptr_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        read_ptr_reg <= reg2hw.src_ptr.q;
+      end else if (data_in_gnt == 1'b1) begin
+        if (dma_conf_1d == 1'b1) begin
+          /* Increase the pointer by the amount written in ptr_inc */
+          read_ptr_reg <= read_ptr_reg + dma_src_d1_inc;
+        end else if (dma_conf_2d == 1'b1) begin
+          if (read_ptr_update_sel == 1'b0) begin
+            if (dma_src_cnt_d1 == 1 && |dma_src_cnt_d2 == 1'b1) begin
+              /* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d1)*data_unit */
+              read_ptr_reg <= read_ptr_reg + dma_src_d2_inc;
+            end else begin
+              read_ptr_reg <= read_ptr_reg + dma_src_d1_inc; /* Increment of the d1 increment (stride) */
+            end
+          end else begin
+            /* In this case, perform the transposition */
+            if (dma_src_cnt_d1 == 1 && |dma_src_cnt_d2 == 1'b1) begin
+              /* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d1)*data_unit */
+              read_ptr_reg <= trsp_src_ptr_reg;
+            end else begin
+              read_ptr_reg <= read_ptr_reg + dma_src_d2_inc; /* Increment of the d2 increment (stride) */
+            end
+          end
+        end
+      end
+    end
+  end
+
+  // FSM state update
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_fsm_state
+    if (~rst_ni) begin
+      dma_read_fsm_state <= DMA_READ_FSM_IDLE;
+    end else begin
+      dma_read_fsm_state <= dma_read_fsm_n_state;
+    end
+  end
+
+  // Read master FSM
+  always_comb begin : proc_dma_read_fsm_logic
+
+    dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+
+    data_in_req = '0;
+    data_in_we = '0;
+    data_in_be = '0;
+    data_in_addr = '0;
+
+    fifo_flush = 1'b0;
+
+    unique case (dma_read_fsm_state)
+
+      DMA_READ_FSM_IDLE: begin
+        // Wait for start signal
+        if (dma_start == 1'b1) begin
+          dma_read_fsm_n_state = DMA_READ_FSM_ON;
+        end else begin
+          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+        end
+      end
+      // Read one word
+      DMA_READ_FSM_ON: begin
+        // If all input data read exit
+        if (ext_dma_stop == 1'b0) begin
+          if (dma_conf_1d == 1'b1) begin
+            // 1D DMA case
+            if (|dma_src_cnt_d1 == 1'b0) begin
+              dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+            end else begin
+              dma_read_fsm_n_state = DMA_READ_FSM_ON;
+              // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
+              if (fifo_full == 1'b0 && fifo_alm_full == 1'b0 && wait_for_rx == 1'b0) begin
+                data_in_req  = 1'b1;
+                data_in_we   = 1'b0;
+                data_in_be   = 4'b1111;  // always read all bytes
+                data_in_addr = read_ptr_reg;
+              end
+            end
+          end else if (dma_conf_2d == 1'b1) begin
+            // 2D DMA case: exit only if both 1d and 2d counters are at 0
+            if (dma_src_cnt_d1 == {1'h0, reg2hw.size_d1.q} && |dma_src_cnt_d2 == 1'b0) begin
+              dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+            end else begin
+              // The read operation is the same in both cases
+              dma_read_fsm_n_state = DMA_READ_FSM_ON;
+              // Wait if fifo is full, almost full (last data), or if the SPI RX does not have valid data (only in SPI mode 1).
+              if (fifo_full == 1'b0 && fifo_alm_full == 1'b0 && wait_for_rx == 1'b0) begin
+                data_in_req  = 1'b1;
+                data_in_we   = 1'b0;
+                data_in_be   = 4'b1111;  // always read all bytes
+                data_in_addr = read_ptr_reg;
+              end
+            end
+          end
+        end else begin
+          dma_read_fsm_n_state = DMA_READ_FSM_IDLE;
+        end
+      end
+    endcase
+  end
+
+  // Only update read_ptr_valid_reg when the data is stored in the fifo.
+  // Since every input grant is followed by a rvalid, the read_ptr_valid_reg is a mere sample of the read_ptr_reg
+  // synched with the rvalid signal.
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_valid_in_reg
+    if (~rst_ni) begin
+      read_ptr_valid_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        read_ptr_valid_reg <= reg2hw.src_ptr.q;
+      end else if (data_in_rvalid == 1'b1) begin
+        read_ptr_valid_reg <= read_ptr_reg;
+      end
+    end
+  end
+
+  // Input data shift: shift the input data to be on the LSB of the fifo
+  always_comb begin : proc_input_data
+
+    fifo_input[7:0]   = data_in_rdata[7:0];
+    fifo_input[15:8]  = data_in_rdata[15:8];
+    fifo_input[23:16] = data_in_rdata[23:16];
+    fifo_input[31:24] = data_in_rdata[31:24];
+
+    case (read_ptr_valid_reg[1:0])
+      2'b00: ;
+      2'b01: fifo_input[7:0] = data_in_rdata[15:8];
+
+      2'b10: begin
+        fifo_input[7:0]  = data_in_rdata[23:16];
+        fifo_input[15:8] = data_in_rdata[31:24];
+      end
+
+      2'b11: fifo_input[7:0] = data_in_rdata[31:24];
+    endcase
+  end
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  /* Renaming */
+  assign reg2hw = reg2hw_i;
+  assign data_in_gnt = data_in_gnt_i;
+  assign fifo_full = read_fifo_full_i;
+  assign fifo_alm_full = read_fifo_alm_full_i;
+  assign dma_start = dma_start_i;
+  assign ext_dma_stop = ext_dma_stop_i;
+  assign read_ptr_update_sel = reg2hw.dim_inv.q;
+  assign dma_conf_1d = reg2hw.dim_config.q == 0;
+  assign dma_conf_2d = reg2hw.dim_config.q == 1;
+  assign data_in_be_o = data_in_be;
+  assign data_in_addr_o = data_in_addr;
+  assign data_in_req_o = data_in_req;
+  assign data_in_we_o = data_in_we;
+  assign read_fifo_flush_o = fifo_flush;
+  assign wait_for_rx = wait_for_rx_i;
+  assign data_in_rvalid = data_in_rvalid_i;
+  assign data_in_rdata = data_in_rdata_i;
+  assign fifo_input_o = fifo_input;
+
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiwrite_fsm.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiwrite_fsm.sv
new file mode 100644
index 00000000..5b83c400
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_obiwrite_fsm.sv
@@ -0,0 +1,358 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Writing FSM for DMA channel, process data coming out of the output FIFO. Performs the sign extension if needed.
+ */
+
+module dma_obiwrite_fsm
+  import dma_reg_pkg::*;
+#(
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input dma_reg2hw_t reg2hw_i,
+    input logic dma_start_i,
+    input logic write_fifo_empty_i,
+    input logic read_addr_fifo_empty_i,
+    input logic [31:0] fifo_output_i,
+    input logic wait_for_tx_i,
+    input logic address_mode_i,
+    input logic padding_fsm_done_i,
+    input logic data_out_gnt_i,
+    input logic [31:0] fifo_addr_output_i,
+
+    output logic data_out_req_o,
+    output logic data_out_we_o,
+    output logic [3:0] data_out_be_o,
+    output logic [31:0] data_out_addr_o,
+    output logic [31:0] data_out_wdata_o,
+    output logic dma_done_o
+);
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Parameter definition */
+
+  import dma_reg_pkg::*;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* Registers */
+  dma_reg2hw_t reg2hw;
+
+  logic dma_conf_1d;
+  logic dma_conf_2d;
+  logic dma_done;
+  logic address_mode;
+  logic dma_start;
+
+  enum logic {
+    DMA_WRITE_FSM_IDLE,
+    DMA_WRITE_FSM_ON
+  }
+      dma_write_fsm_state, dma_write_fsm_n_state;
+
+  typedef enum logic [1:0] {
+    DMA_DATA_TYPE_WORD,
+    DMA_DATA_TYPE_HALF_WORD,
+    DMA_DATA_TYPE_BYTE,
+    DMA_DATA_TYPE_BYTE_
+  } dma_data_type_t;
+
+  dma_data_type_t dst_data_type;
+  dma_data_type_t src_data_type;
+
+  logic data_out_req;
+  logic data_out_we;
+  logic data_out_gnt;
+  logic [3:0] data_out_be;
+  logic [31:0] data_out_addr;
+  logic [31:0] data_out_wdata;
+  logic [31:0] write_address;
+  logic [31:0] write_ptr_reg;
+  logic [3:0] byte_enable_out;
+
+  logic [31:0] dma_dst_d1_inc;
+  logic [31:0] dma_dst_d2_inc;
+  logic [16:0] dma_dst_cnt_d1;
+
+  logic wait_for_tx;
+
+  /* Sign extension signals */
+  logic sign_extend;
+
+  /* FIFO signals */
+  logic write_fifo_empty;
+  logic read_addr_fifo_empty;
+  logic [31:0] fifo_output;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* FSMs instantiation */
+
+  /* Sign extension of the increments */
+  always_comb begin
+    dma_dst_d1_inc = {{26{reg2hw.dst_ptr_inc_d1.q[5]}}, reg2hw.dst_ptr_inc_d1.q};
+    dma_dst_d2_inc = {{9{reg2hw.dst_ptr_inc_d2.q[22]}}, reg2hw.dst_ptr_inc_d2.q};
+  end
+
+  /* Counters for the reading fsm */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_dma_dst_cnt_reg
+    if (~rst_ni) begin
+      dma_dst_cnt_d1 <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        dma_dst_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
+      end else if (dma_done == 1'b1) begin
+        dma_dst_cnt_d1 <= '0;
+      end else if (data_out_gnt == 1'b1) begin
+        if (dma_conf_1d == 1'b1) begin
+          // 1D case
+          dma_dst_cnt_d1 <= dma_dst_cnt_d1 - 1;
+        end else if (dma_conf_2d == 1'b1) begin
+          // 2D case
+          if (dma_dst_cnt_d1 == 1) begin
+            // In this case, the d1 is finished, so we need to reset the d2 size
+            dma_dst_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
+          end else begin
+            // In this case, the d1 isn't finished, so we need to decrement the d1 size
+            dma_dst_cnt_d1 <= dma_dst_cnt_d1 - 1;
+          end
+        end
+      end
+    end
+  end
+
+  /* Determine the byte enable depending on the datatype */
+  always_comb begin : proc_byte_enable_out
+    case (dst_data_type)  // Data type 00 Word, 01 Half word, 11,10 byte
+      DMA_DATA_TYPE_WORD: byte_enable_out = 4'b1111;  // Writing a word (32 bits)
+
+      DMA_DATA_TYPE_HALF_WORD: begin  // Writing a half-word (16 bits)
+        case (write_ptr_reg[1])
+          1'b0: byte_enable_out = 4'b0011;
+          1'b1: byte_enable_out = 4'b1100;
+        endcase
+        ;  // case(write_ptr_reg[1:0])
+      end
+
+      DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: begin  // Writing a byte (8 bits)
+        case (write_ptr_reg[1:0])
+          2'b00: byte_enable_out = 4'b0001;
+          2'b01: byte_enable_out = 4'b0010;
+          2'b10: byte_enable_out = 4'b0100;
+          2'b11: byte_enable_out = 4'b1000;
+        endcase
+        ;  // case(write_ptr_reg[1:0])
+      end
+    endcase
+    ;  // case (dst_data_type)
+  end
+
+  /* Store output data pointer and increment everytime write request is granted */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_ptr_out_reg
+    if (~rst_ni) begin
+      write_ptr_reg <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        write_ptr_reg <= reg2hw.dst_ptr.q;
+      end else if (data_out_gnt == 1'b1) begin
+        if (dma_conf_1d == 1'b1) begin
+          write_ptr_reg <= write_ptr_reg + dma_dst_d1_inc;
+        end else if (dma_conf_2d == 1'b1) begin
+          if (dma_dst_cnt_d1 == 1) begin
+            // In this case, the d1 is finished, so we need to increment the pointer by sizeof(d1)*data_unit*strides
+            write_ptr_reg <= write_ptr_reg + dma_dst_d2_inc;
+          end else begin
+            write_ptr_reg <= write_ptr_reg + dma_dst_d1_inc; // Increment just of one du, since we need to increase the 1d
+          end
+        end
+      end
+    end
+  end
+
+  /* FSM state update */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_fsm_state
+    if (~rst_ni) begin
+      dma_write_fsm_state <= DMA_WRITE_FSM_IDLE;
+    end else begin
+      dma_write_fsm_state <= dma_write_fsm_n_state;
+    end
+  end
+
+  /* Write master FSM */
+  always_comb begin : proc_dma_write_fsm_logic
+
+    dma_write_fsm_n_state = DMA_WRITE_FSM_IDLE;
+    dma_done = 1'b0;
+
+    data_out_req = '0;
+    data_out_we = '0;
+    data_out_be = '0;
+    data_out_addr = '0;
+
+    unique case (dma_write_fsm_state)
+
+      DMA_WRITE_FSM_IDLE: begin
+        // Wait for start signal
+        if (dma_start == 1'b1) begin
+          dma_write_fsm_n_state = DMA_WRITE_FSM_ON;
+        end else begin
+          dma_write_fsm_n_state = DMA_WRITE_FSM_IDLE;
+        end
+      end
+      // Read one word
+      DMA_WRITE_FSM_ON: begin
+        // If all input data read exit
+        if (padding_fsm_done_i == 1'b1 && write_fifo_empty == 1'b1) begin
+          dma_done = (write_fifo_empty == 1'b1);
+          // If all input data has been processed and written, exit, otherwise finish storing the data
+          dma_write_fsm_n_state = dma_done ? DMA_WRITE_FSM_IDLE : DMA_WRITE_FSM_ON;
+        end else begin
+          dma_write_fsm_n_state = DMA_WRITE_FSM_ON;
+          // Wait if write fifo is empty or if the SPI TX is not ready for new data (only in SPI mode 2).
+          if (write_fifo_empty == 1'b0 && wait_for_tx == 1'b0 && (read_addr_fifo_empty && address_mode) == 1'b0) begin
+            data_out_req  = 1'b1;
+            data_out_we   = 1'b1;
+            data_out_be   = byte_enable_out;
+            data_out_addr = write_address;
+          end
+        end
+      end
+    endcase
+  end
+
+  /* Perform the data shift */
+  always_comb begin : proc_output_data
+
+    data_out_wdata[7:0]   = fifo_output[7:0];
+    data_out_wdata[15:8]  = fifo_output[15:8];
+    data_out_wdata[23:16] = fifo_output[23:16];
+    data_out_wdata[31:24] = fifo_output[31:24];
+
+    case (write_ptr_reg[1:0])
+      2'b00: begin
+        if (sign_extend) begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD} : ;
+            {
+              DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD
+            } :
+            data_out_wdata[31:16] = {16{fifo_output[15]}};
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_WORD
+            } :
+            data_out_wdata[31:8] = {24{fifo_output[7]}};
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[15:8] = {8{fifo_output[7]}};
+            default: ;
+          endcase
+        end else begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD} : ;
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD} : data_out_wdata[31:16] = 16'b0;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_WORD
+            } :
+            data_out_wdata[31:8] = 24'b0;
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[15:8] = 8'b0;
+            default: ;
+          endcase
+        end
+      end
+      2'b01: data_out_wdata[15:8] = fifo_output[7:0];  // Writing a byte, no need for sign extension
+      2'b10: begin  // Writing a half-word or a byte
+        data_out_wdata[23:16] = fifo_output[7:0];
+        data_out_wdata[31:24] = fifo_output[15:8];
+
+        if (sign_extend) begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[31:24] = {8{fifo_output[7]}};
+            default: ;
+          endcase
+        end else begin
+          case ({
+            src_data_type, dst_data_type
+          })
+            {DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD} : ;
+            {
+              DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD
+            }, {
+              DMA_DATA_TYPE_BYTE_, DMA_DATA_TYPE_HALF_WORD
+            } :
+            data_out_wdata[31:24] = 8'b0;
+            default: ;
+          endcase
+        end
+      end
+      2'b11:
+      data_out_wdata[31:24] = fifo_output[7:0];  // Writing a byte, no need for sign extension
+    endcase
+  end
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  /* Renaming */
+  assign dma_start = dma_start_i;
+  assign reg2hw = reg2hw_i;
+  assign data_out_gnt = data_out_gnt_i;
+  assign dma_done_o = dma_done;
+  assign dst_data_type = dma_data_type_t'(reg2hw.dst_data_type.q);
+  assign src_data_type = dma_data_type_t'(reg2hw.src_data_type.q);
+  assign data_out_wdata_o = data_out_wdata;
+  assign write_fifo_empty = write_fifo_empty_i;
+  assign fifo_output = fifo_output_i;
+  assign wait_for_tx = wait_for_tx_i;
+  assign data_out_be_o = data_out_be;
+  assign data_out_addr_o = data_out_addr;
+  assign data_out_req_o = data_out_req;
+  assign data_out_we_o = data_out_we;
+  assign read_addr_fifo_empty = read_addr_fifo_empty_i;
+  assign address_mode = address_mode_i;
+  assign dma_conf_1d = reg2hw.dim_config.q == 0;
+  assign dma_conf_2d = reg2hw.dim_config.q == 1;
+
+  /* Write address */
+  assign write_address = address_mode ? fifo_addr_output_i : write_ptr_reg;
+
+  /* Sign extension */
+  assign sign_extend = reg2hw.sign_ext.q & ( (src_data_type[1] & ~dst_data_type[1]) | ((src_data_type[1] == dst_data_type[1]) & (src_data_type[0] & ~dst_data_type[0])));
+
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_padding_fsm.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_padding_fsm.sv
new file mode 100644
index 00000000..d16c0bf3
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_padding_fsm.sv
@@ -0,0 +1,339 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Padding FSM for DMA channel.
+ */
+
+module dma_padding_fsm
+  import dma_reg_pkg::*;
+#(
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input dma_reg2hw_t reg2hw_i,
+    input logic dma_padding_fsm_on_i,
+    input logic dma_start_i,
+    input logic read_fifo_empty_i,
+    input logic write_fifo_full_i,
+    input logic write_fifo_alm_full_i,
+    input logic [31:0] data_read_i,
+
+    output logic padding_fsm_done_o,
+    output logic write_fifo_push_o,
+    output logic read_fifo_pop_o,
+    output logic [31:0] data_write_o
+);
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Parameter definition */
+
+  import dma_reg_pkg::*;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* Registers */
+  dma_reg2hw_t reg2hw;
+
+  /* General signals */
+  logic read_fifo_en;
+  logic write_fifo_en;
+  logic pad_on;
+  logic read_fifo_empty;
+  logic write_fifo_full;
+  logic write_fifo_alm_full;
+  logic dma_start;
+  logic [16:0] dma_cnt_d1;
+  logic [16:0] dma_cnt_d2;
+  logic dma_conf_1d;
+  logic dma_conf_2d;
+
+  /* Padding FSM states */
+  enum {
+    PAD_IDLE,
+    TOP_PAD_EXEC,
+    LEFT_PAD_EXEC,
+    RIGHT_PAD_EXEC,
+    BOTTOM_PAD_EXEC,
+    TOP_PAD_DONE,
+    LEFT_PAD_DONE,
+    RIGHT_PAD_DONE,
+    BOTTOM_PAD_DONE
+  }
+      pad_state_q, pad_state_d;
+
+  /* Padding FSM conditions */
+  logic idle_to_left_ex;
+  logic idle_to_top_ex;
+  logic idle_to_right_ex;
+  logic idle_to_bottom_ex;
+  logic top_ex_to_top_dn;
+  logic top_ex_to_left_ex;
+  logic top_dn_to_right_ex;
+  logic top_dn_to_bottom_ex;
+  logic top_dn_to_idle;
+  logic left_ex_to_left_dn;
+  logic left_dn_to_left_ex;
+  logic left_dn_to_right_ex;
+  logic left_dn_to_bottom_ex;
+  logic left_dn_to_idle;
+  logic right_ex_to_right_dn;
+  logic right_ex_to_left_ex;
+  logic right_dn_to_right_ex;
+  logic right_dn_to_idle;
+  logic right_ex_to_idle;
+  logic right_ex_to_bottom_ex;
+  logic bottom_ex_to_idle;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Module instantiation */
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* FSMs instantiation */
+
+  /* Padding FSM state update */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_pad_state
+    if (~rst_ni) begin
+      pad_state_q <= PAD_IDLE;
+    end else begin
+      /* Advance in the FSM only if the write FIFO is available */
+      if (write_fifo_en == 1'b1 && dma_padding_fsm_on_i == 1'b1 && padding_fsm_done_o == 1'b0) begin
+        pad_state_q <= pad_state_d;
+      end
+    end
+  end
+
+  /* Padding FSM logic */
+  always_comb begin : proc_pad_fsm_logic
+    pad_state_d = pad_state_q;
+
+    unique case (pad_state_q)
+      PAD_IDLE: begin
+        /* If the padding is done, stay idle */
+        if (padding_fsm_done_o == 1'b1) begin
+          pad_state_d = PAD_IDLE;
+        end else begin
+          if (idle_to_top_ex) begin
+            pad_state_d = TOP_PAD_EXEC;
+          end else if (idle_to_left_ex) begin
+            pad_state_d = LEFT_PAD_EXEC;
+          end else if (idle_to_right_ex) begin
+            pad_state_d = RIGHT_PAD_EXEC;
+          end else if (idle_to_bottom_ex) begin
+            pad_state_d = BOTTOM_PAD_EXEC;
+          end
+        end
+      end
+
+      TOP_PAD_EXEC: begin
+        if (top_ex_to_left_ex) begin
+          pad_state_d = LEFT_PAD_EXEC;
+        end else if (top_ex_to_top_dn) begin
+          pad_state_d = TOP_PAD_DONE;
+        end
+      end
+      TOP_PAD_DONE: begin
+        if (top_dn_to_right_ex) begin
+          pad_state_d = RIGHT_PAD_EXEC;
+        end else if (top_dn_to_bottom_ex) begin
+          pad_state_d = BOTTOM_PAD_EXEC;
+        end else if (top_dn_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end
+      end
+      LEFT_PAD_EXEC: begin
+        if (left_ex_to_left_dn) begin
+          pad_state_d = LEFT_PAD_DONE;
+        end
+      end
+      LEFT_PAD_DONE: begin
+        if (left_dn_to_right_ex) begin
+          pad_state_d = RIGHT_PAD_EXEC;
+        end else if (left_dn_to_bottom_ex) begin
+          pad_state_d = BOTTOM_PAD_EXEC;
+        end else if (left_dn_to_left_ex) begin
+          pad_state_d = LEFT_PAD_EXEC;
+        end else if (left_dn_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end
+      end
+      RIGHT_PAD_EXEC: begin
+        if (right_ex_to_right_dn) begin
+          pad_state_d = RIGHT_PAD_DONE;
+        end else if (right_ex_to_left_ex) begin
+          pad_state_d = LEFT_PAD_EXEC;
+        end else if (right_ex_to_bottom_ex) begin
+          pad_state_d = BOTTOM_PAD_EXEC;
+        end else if (right_ex_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end
+      end
+      RIGHT_PAD_DONE: begin
+        if (right_dn_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end else if (right_dn_to_right_ex) begin
+          pad_state_d = RIGHT_PAD_EXEC;
+        end
+      end
+      BOTTOM_PAD_EXEC: begin
+        if (bottom_ex_to_idle) begin
+          pad_state_d = PAD_IDLE;
+        end
+      end
+    endcase
+  end
+
+  /* Data transfer */
+  always_comb begin : proc_data_transfer
+    data_write_o = '0;
+    write_fifo_push_o = 1'b0;
+    read_fifo_pop_o = 1'b0;
+
+    if (dma_padding_fsm_on_i == 1'b1 && padding_fsm_done_o == 1'b0) begin
+      /* 
+       * If we need to pad, there is no need to wait for the read fifo to have some values.
+       * If we don't have to pad, we need to wait for the read fifo to be not empty.
+       * In both cases, we need to wait for the write fifo to have some space.
+       */
+      if (pad_on == 1'b1 & write_fifo_en == 1'b1) begin
+        write_fifo_push_o = 1'b1;
+      end else if (read_fifo_en == 1'b1 & write_fifo_en == 1'b1) begin
+        data_write_o = data_read_i;
+        write_fifo_push_o = 1'b1;
+        read_fifo_pop_o = 1'b1;
+      end
+    end
+  end
+
+  /* Counters for the padding fsm */
+  always_ff @(posedge clk_i or negedge rst_ni) begin : proc_cnt
+    if (~rst_ni) begin
+      dma_cnt_d1 <= '0;
+      dma_cnt_d2 <= '0;
+    end else begin
+      if (dma_start == 1'b1) begin
+        dma_cnt_d1 <= ({1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q});
+        dma_cnt_d2 <= {1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_top.q} + {11'h0, reg2hw.pad_bottom.q};
+      end else if (padding_fsm_done_o == 1'b1) begin
+        dma_cnt_d1 <= '0;
+        dma_cnt_d2 <= '0;
+      end else if ((dma_padding_fsm_on_i == 1'b1 && padding_fsm_done_o == 1'b0) & 
+                   ((pad_on == 1'b1 & write_fifo_en == 1'b1) || 
+                   (read_fifo_en == 1'b1 & write_fifo_en == 1'b1))) begin
+        if (dma_conf_1d == 1'b1) begin
+          // 1D case
+          dma_cnt_d1 <= dma_cnt_d1 - 1;
+        end else if (dma_conf_2d == 1'b1) begin
+          // 2D case
+          if (dma_cnt_d1 == 1) begin
+            // In this case, the d1 is finished, so we need to decrement the d2 size and reset the d2 size
+            dma_cnt_d2 <= dma_cnt_d2 - 1;
+            dma_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
+          end else begin
+            // In this case, the d1 isn't finished, so we need to decrement the d1 size
+            dma_cnt_d1 <= dma_cnt_d1 - 1;
+          end
+        end
+      end
+    end
+  end
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  /* Renaming */
+  assign read_fifo_empty = read_fifo_empty_i;
+  assign write_fifo_full = write_fifo_full_i;
+  assign write_fifo_alm_full = write_fifo_alm_full_i;
+  assign dma_start = dma_start_i;
+  assign reg2hw = reg2hw_i;
+  assign dma_conf_1d = reg2hw.dim_config.q == 0;
+  assign dma_conf_2d = reg2hw.dim_config.q == 1;
+
+  /* Padding flag */
+  assign pad_on = (pad_state_q != PAD_IDLE && pad_state_q != TOP_PAD_DONE && pad_state_q != LEFT_PAD_DONE && pad_state_q != RIGHT_PAD_DONE && pad_state_q != BOTTOM_PAD_DONE);
+
+  /* Read FIFO pop signal */
+  assign read_fifo_en = (read_fifo_empty == 1'b0);
+
+  /* Write FIFO push signal */
+  assign write_fifo_en = (write_fifo_full == 1'b0 && write_fifo_alm_full == 1'b0);
+
+  /* Padding done signal */
+  assign padding_fsm_done_o = ((dma_conf_2d == 1'b1 && |dma_cnt_d2 == 1'b0 && dma_padding_fsm_on_i == 1'b1)
+                                | (dma_conf_1d == 1'b1 && |dma_cnt_d1 == 1'b0 && dma_padding_fsm_on_i == 1'b1));
+
+  /* Padding FSM conditions assignments */
+  assign idle_to_top_ex = {|reg2hw.pad_top.q == 1'b1 && dma_padding_fsm_on_i == 1'b1};
+  assign idle_to_left_ex = {
+    |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b1 && dma_padding_fsm_on_i == 1'b1
+  };
+  assign idle_to_right_ex = {
+    write_fifo_push_o == 1'b1 && |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 
+                      && dma_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + 1)
+  };
+  assign idle_to_bottom_ex = {
+    write_fifo_push_o == 1'b1 && |reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 
+                      && dma_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + 1) && dma_cnt_d1 == 1
+  };
+  assign top_ex_to_top_dn = {
+    write_fifo_push_o == 1'b1 && dma_cnt_d2 == ( {1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + 1) && dma_cnt_d1 == 1 && |reg2hw.pad_left.q == 1'b0
+  };
+  assign top_ex_to_left_ex = {
+    write_fifo_push_o == 1'b1 && dma_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + 1) && dma_cnt_d1 == 1 && |reg2hw.pad_left.q == 1'b1
+  };
+  assign top_dn_to_right_ex = {
+    write_fifo_push_o == 1'b1 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 && dma_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + 1)
+  };
+  assign top_dn_to_bottom_ex = {
+    write_fifo_push_o == 1'b1 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + 1) && dma_cnt_d1 == 1
+  };
+  assign top_dn_to_idle = {
+    |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && dma_cnt_d2 == 1 && dma_cnt_d1 == 1
+  };
+  assign left_ex_to_left_dn = {
+    write_fifo_push_o == 1'b1 && dma_cnt_d1 == ({1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_right.q} + 1)
+  };
+  assign left_dn_to_left_ex = {
+    write_fifo_push_o == 1'b1 && dma_cnt_d1 == 1 && dma_cnt_d2 != (1'b1 + {11'h0, reg2hw.pad_bottom.q}) && |reg2hw.pad_right.q == 1'b0
+  };
+  assign left_dn_to_right_ex = {
+    write_fifo_push_o == 1'b1 && |reg2hw.pad_right.q == 1'b1 && dma_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + 1)
+  };
+  assign left_dn_to_bottom_ex = {
+    write_fifo_push_o == 1'b1 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + 1) && dma_cnt_d1 == 1
+  };
+  assign left_dn_to_idle = {
+    |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && dma_cnt_d2 == 1 && dma_cnt_d1 == 1
+  };
+  assign right_ex_to_right_dn = {
+    write_fifo_push_o == 1'b1 && dma_cnt_d1 == 1 && dma_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + 1) && |reg2hw.pad_left.q == 1'b0
+  };
+  assign right_ex_to_left_ex = {
+    write_fifo_push_o == 1'b1 && dma_cnt_d1 == 1 && dma_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + 1) && |reg2hw.pad_left.q == 1'b1
+  };
+  assign right_ex_to_bottom_ex = {
+    write_fifo_push_o == 1'b1 && |reg2hw.pad_bottom.q == 1'b1 && dma_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + 1) && dma_cnt_d1 == 1
+  };
+  assign right_dn_to_right_ex = {
+    write_fifo_push_o == 1'b1 && dma_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + 1) && |reg2hw.pad_left.q == 1'b0
+  };
+  assign right_dn_to_idle = {|reg2hw.pad_bottom.q == 1'b0 && dma_cnt_d2 == 1 && dma_cnt_d1 == 1};
+  assign bottom_ex_to_idle = {dma_cnt_d1 == 1 && dma_cnt_d2 == 1 && dma_cnt_d1 == 1};
+
+  assign right_ex_to_idle = {|reg2hw.pad_bottom.q == 1'b0 && dma_cnt_d2 == 1 && dma_cnt_d1 == 1};
+
+
+
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv
index f2fe4761..4e98968c 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_pkg.sv
@@ -24,10 +24,7 @@ package dma_reg_pkg;
     logic        qe;
   } dma_reg2hw_size_d1_reg_t;
 
-  typedef struct packed {
-    logic [15:0] q;
-    logic        qe;
-  } dma_reg2hw_size_d2_reg_t;
+  typedef struct packed {logic [15:0] q;} dma_reg2hw_size_d2_reg_t;
 
   typedef struct packed {
     struct packed {
@@ -65,25 +62,13 @@ package dma_reg_pkg;
 
   typedef struct packed {logic q;} dma_reg2hw_dim_inv_reg_t;
 
-  typedef struct packed {
-    logic [5:0] q;
-    logic       qe;
-  } dma_reg2hw_pad_top_reg_t;
+  typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_top_reg_t;
 
-  typedef struct packed {
-    logic [5:0] q;
-    logic       qe;
-  } dma_reg2hw_pad_bottom_reg_t;
+  typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_bottom_reg_t;
 
-  typedef struct packed {
-    logic [5:0] q;
-    logic       qe;
-  } dma_reg2hw_pad_right_reg_t;
+  typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_right_reg_t;
 
-  typedef struct packed {
-    logic [5:0] q;
-    logic       qe;
-  } dma_reg2hw_pad_left_reg_t;
+  typedef struct packed {logic [5:0] q;} dma_reg2hw_pad_left_reg_t;
 
   typedef struct packed {logic [12:0] q;} dma_reg2hw_window_size_reg_t;
 
@@ -120,27 +105,27 @@ package dma_reg_pkg;
 
   // Register -> HW type
   typedef struct packed {
-    dma_reg2hw_src_ptr_reg_t src_ptr;  // [287:256]
-    dma_reg2hw_dst_ptr_reg_t dst_ptr;  // [255:224]
-    dma_reg2hw_addr_ptr_reg_t addr_ptr;  // [223:192]
-    dma_reg2hw_size_d1_reg_t size_d1;  // [191:175]
-    dma_reg2hw_size_d2_reg_t size_d2;  // [174:158]
-    dma_reg2hw_status_reg_t status;  // [157:154]
-    dma_reg2hw_src_ptr_inc_d1_reg_t src_ptr_inc_d1;  // [153:148]
-    dma_reg2hw_src_ptr_inc_d2_reg_t src_ptr_inc_d2;  // [147:125]
-    dma_reg2hw_dst_ptr_inc_d1_reg_t dst_ptr_inc_d1;  // [124:119]
-    dma_reg2hw_dst_ptr_inc_d2_reg_t dst_ptr_inc_d2;  // [118:96]
-    dma_reg2hw_slot_reg_t slot;  // [95:64]
-    dma_reg2hw_src_data_type_reg_t src_data_type;  // [63:62]
-    dma_reg2hw_dst_data_type_reg_t dst_data_type;  // [61:60]
-    dma_reg2hw_sign_ext_reg_t sign_ext;  // [59:59]
-    dma_reg2hw_mode_reg_t mode;  // [58:57]
-    dma_reg2hw_dim_config_reg_t dim_config;  // [56:56]
-    dma_reg2hw_dim_inv_reg_t dim_inv;  // [55:55]
-    dma_reg2hw_pad_top_reg_t pad_top;  // [54:48]
-    dma_reg2hw_pad_bottom_reg_t pad_bottom;  // [47:41]
-    dma_reg2hw_pad_right_reg_t pad_right;  // [40:34]
-    dma_reg2hw_pad_left_reg_t pad_left;  // [33:27]
+    dma_reg2hw_src_ptr_reg_t src_ptr;  // [282:251]
+    dma_reg2hw_dst_ptr_reg_t dst_ptr;  // [250:219]
+    dma_reg2hw_addr_ptr_reg_t addr_ptr;  // [218:187]
+    dma_reg2hw_size_d1_reg_t size_d1;  // [186:170]
+    dma_reg2hw_size_d2_reg_t size_d2;  // [169:154]
+    dma_reg2hw_status_reg_t status;  // [153:150]
+    dma_reg2hw_src_ptr_inc_d1_reg_t src_ptr_inc_d1;  // [149:144]
+    dma_reg2hw_src_ptr_inc_d2_reg_t src_ptr_inc_d2;  // [143:121]
+    dma_reg2hw_dst_ptr_inc_d1_reg_t dst_ptr_inc_d1;  // [120:115]
+    dma_reg2hw_dst_ptr_inc_d2_reg_t dst_ptr_inc_d2;  // [114:92]
+    dma_reg2hw_slot_reg_t slot;  // [91:60]
+    dma_reg2hw_src_data_type_reg_t src_data_type;  // [59:58]
+    dma_reg2hw_dst_data_type_reg_t dst_data_type;  // [57:56]
+    dma_reg2hw_sign_ext_reg_t sign_ext;  // [55:55]
+    dma_reg2hw_mode_reg_t mode;  // [54:53]
+    dma_reg2hw_dim_config_reg_t dim_config;  // [52:52]
+    dma_reg2hw_dim_inv_reg_t dim_inv;  // [51:51]
+    dma_reg2hw_pad_top_reg_t pad_top;  // [50:45]
+    dma_reg2hw_pad_bottom_reg_t pad_bottom;  // [44:39]
+    dma_reg2hw_pad_right_reg_t pad_right;  // [38:33]
+    dma_reg2hw_pad_left_reg_t pad_left;  // [32:27]
     dma_reg2hw_window_size_reg_t window_size;  // [26:14]
     dma_reg2hw_window_count_reg_t window_count;  // [13:6]
     dma_reg2hw_interrupt_en_reg_t interrupt_en;  // [5:4]
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv
index a4004830..ea7897c0 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma/rtl/dma_reg_top.sv
@@ -278,7 +278,7 @@ module dma_reg_top #(
       .d ('0),
 
       // to internal hardware
-      .qe(reg2hw.size_d2.qe),
+      .qe(),
       .q (reg2hw.size_d2.q),
 
       // to register interface (read)
@@ -661,7 +661,7 @@ module dma_reg_top #(
       .d ('0),
 
       // to internal hardware
-      .qe(reg2hw.pad_top.qe),
+      .qe(),
       .q (reg2hw.pad_top.q),
 
       // to register interface (read)
@@ -688,7 +688,7 @@ module dma_reg_top #(
       .d ('0),
 
       // to internal hardware
-      .qe(reg2hw.pad_bottom.qe),
+      .qe(),
       .q (reg2hw.pad_bottom.q),
 
       // to register interface (read)
@@ -715,7 +715,7 @@ module dma_reg_top #(
       .d ('0),
 
       // to internal hardware
-      .qe(reg2hw.pad_right.qe),
+      .qe(),
       .q (reg2hw.pad_right.q),
 
       // to register interface (read)
@@ -742,7 +742,7 @@ module dma_reg_top #(
       .d ('0),
 
       // to internal hardware
-      .qe(reg2hw.pad_left.qe),
+      .qe(),
       .q (reg2hw.pad_left.q),
 
       // to register interface (read)
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core
index 1fa1b17b..d611de9d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/dma_subsystem.core
@@ -13,6 +13,7 @@ filesets:
       - pulp-platform.org::common_cells
     files:
     - rtl/dma_subsystem.sv
+    - rtl/dma_NtoM_xbar.sv
     file_type: systemVerilogSource
 
 targets:
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_NtoM_xbar.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_NtoM_xbar.sv
new file mode 100644
index 00000000..b1a4f39f
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_NtoM_xbar.sv
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch> 
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Generated N-to-M crossbar.
+ *       This module has been developed to be used in the DMA subsystem, in which it is not possible to use an NtoM crossbar.
+ *       The problem is that each slave port of the DMA xbar is actually a master port of the system bus. The DMA xbar slave ports 
+ *       cannot be indexed by the master's request address because they all perform the same function, they all can read/write 
+ *       to/from the same memory spaces.
+ *       This module is a workaround to this problem, as it is composed by a number of N-to-1 crossbars, each for a different slave
+ *       (which would be a system bus master port).
+ *       The amount of masters per crossbar is defined by the parameter NUM_MASTERS_PER_XBAR.
+ *       It is thus possible, from an application point of view, to use channels that are guaranteed to have a dedicated master port,
+ *       reducing the need for additional arbitration logic.
+ */
+
+module dma_NtoM_xbar #(
+    parameter int unsigned XBAR_NMASTER = 4,
+    parameter int unsigned XBAR_MSLAVE  = 2
+) (
+    input logic clk_i,
+    input logic rst_ni,
+
+    // Master ports
+    input  obi_pkg::obi_req_t  [XBAR_NMASTER-1:0] master_req_i,
+    output obi_pkg::obi_resp_t [XBAR_NMASTER-1:0] master_resp_o,
+
+    // slave ports
+    output obi_pkg::obi_req_t  [XBAR_MSLAVE-1:0] slave_req_o,
+    input  obi_pkg::obi_resp_t [XBAR_MSLAVE-1:0] slave_resp_i
+);
+  import obi_pkg::*;
+  import core_v_mini_mcu_pkg::*;
+
+  /* Generation of the crossbars */
+  generate
+    xbar_varlat_n_to_one #(
+        .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[0])
+    ) xbar_i (
+        .clk_i(clk_i),
+        .rst_ni(rst_ni),
+        .master_req_i(master_req_i[core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[0]-1:0]),
+        .master_resp_o(master_resp_o[core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[0]-1:0]),
+        .slave_req_o(slave_req_o[0]),
+        .slave_resp_i(slave_resp_i[0])
+    );
+
+    for (genvar i = 1; i < XBAR_MSLAVE; i++) begin : gen_xbar
+      if (core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i] == 1) begin
+        assign slave_req_o[i] = master_req_i[i+core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[0]-1];
+        assign master_resp_o[i+core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[0]-1] = slave_resp_i[i];
+      end else begin
+        xbar_varlat_n_to_one #(
+            .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i])
+        ) xbar_i (
+            .clk_i(clk_i),
+            .rst_ni(rst_ni),
+            .master_req_i(master_req_i[core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i] + core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i-1]-1:core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i-1]]),
+            .master_resp_o(master_resp_o[core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i] + core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i-1]-1:core_v_mini_mcu_pkg::DMA_XBAR_MASTERS[i-1]]),
+            .slave_req_o(slave_req_o[i]),
+            .slave_resp_i(slave_resp_i[i])
+        );
+      end
+    end
+  endgenerate
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv
index 22274b69..6ac3df37 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/dma_subsystem/rtl/dma_subsystem.sv
@@ -3,7 +3,8 @@
  * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
  * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
  *
- * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch> 
+ *                         <tommaso.terzano@gmail.com>
  *  
  * Info: DMA subsystem, it instantiates 1 to 8 DMA channels and manages the data transfers.
  */
@@ -19,18 +20,19 @@ module dma_subsystem #(
 ) (
     input logic clk_i,
     input logic rst_ni,
+    input logic clk_gate_en_ni [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0],
 
     input  reg_req_t reg_req_i,
     output reg_rsp_t reg_rsp_o,
 
-    output obi_req_t  dma_read_ch0_req_o,
-    input  obi_resp_t dma_read_ch0_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_read_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_read_resp_i,
 
-    output obi_req_t  dma_write_ch0_req_o,
-    input  obi_resp_t dma_write_ch0_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_write_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_write_resp_i,
 
-    output obi_req_t  dma_addr_ch0_req_o,
-    input  obi_resp_t dma_addr_ch0_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_addr_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] dma_addr_resp_i,
 
     input logic [GLOBAL_SLOT_NUM-1:0] global_trigger_slot_i,
     input logic [EXT_SLOT_NUM-1:0] ext_trigger_slot_i,
@@ -38,13 +40,41 @@ module dma_subsystem #(
     input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_stop_i,
 
     output dma_done_intr_o,
-    output dma_window_intr_o
+    output dma_window_intr_o,
+
+    output logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_done_o
 );
 
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Imports and parameters */
 
   import obi_pkg::*;
   import reg_pkg::*;
 
+  /* 
+   * It's possible to define individually the sizes of each DMA channel's FIFOs.
+   * For example, a FIFO_CH_ARRAY like this {L, M, M, S} means that CH0 will be small,
+   * CH1 and CH2 will be medium and CH3 will be large.
+   *
+   * This is useful in applications that require different bandwidths for different channels.
+   * To enable this functionality, decomment EN_SET_FIFO_CH_SIZE and set the desired sizes.
+   */
+
+  //`define EN_SET_FIFO_CH_SIZE;
+
+  `ifdef EN_SET_FIFO_CH_SIZE 
+
+  localparam int unsigned LARGE_FIFO_CH_SIZE = 8;
+  localparam int unsigned MEDIUM_FIFO_CH_SIZE = 4;
+  localparam int unsigned SMALL_FIFO_CH_SIZE = 2;
+
+  typedef enum {L, M, S} fifo_ch_size_t;
+
+  localparam fifo_ch_size_t FIFO_CH_ARRAY [core_v_mini_mcu_pkg::DMA_CH_NUM] = '{L, M, M, S};
+
+  `endif
+
   /*_________________________________________________________________________________________________________________________________ */
 
   /* Signals declaration */
@@ -74,73 +104,136 @@ module dma_subsystem #(
   /* DMA modules */
   generate
     for (genvar i = 0; i < core_v_mini_mcu_pkg::DMA_CH_NUM; i++) begin : dma_i_gen
+
+      /* FIFO size assignment */
+      localparam int fifo_size = 
+      `ifdef EN_SET_FIFO_CH_SIZE
+        (FIFO_CH_ARRAY[i] == L) ? LARGE_FIFO_CH_SIZE :
+        ((FIFO_CH_ARRAY[i] == M) ? MEDIUM_FIFO_CH_SIZE : SMALL_FIFO_CH_SIZE);
+      `else
+        4;
+      `endif
+
       dma #(
           .reg_req_t (reg_pkg::reg_req_t),
           .reg_rsp_t (reg_pkg::reg_rsp_t),
           .obi_req_t (obi_pkg::obi_req_t),
           .obi_resp_t(obi_pkg::obi_resp_t),
-          .SLOT_NUM  (GLOBAL_SLOT_NUM + 2)
+          .SLOT_NUM  (GLOBAL_SLOT_NUM + 2),
+          .FIFO_DEPTH (fifo_size)
       ) dma_i (
           .clk_i,
           .rst_ni,
+          .clk_gate_en_ni(clk_gate_en_ni[i]),
           .ext_dma_stop_i(ext_dma_stop_i[i]),
           .reg_req_i(submodules_req[i]),
           .reg_rsp_o(submodules_rsp[i]),
-          .dma_read_ch0_req_o(xbar_read_req[i]),
-          .dma_read_ch0_resp_i(xbar_read_resp[i]),
-          .dma_write_ch0_req_o(xbar_write_req[i]),
-          .dma_write_ch0_resp_i(xbar_write_resp[i]),
-          .dma_addr_ch0_req_o(xbar_address_req[i]),
-          .dma_addr_ch0_resp_i(xbar_address_resp[i]),
+          .dma_read_req_o(xbar_read_req[i]),
+          .dma_read_resp_i(xbar_read_resp[i]),
+          .dma_write_req_o(xbar_write_req[i]),
+          .dma_write_resp_i(xbar_write_resp[i]),
+          .dma_addr_req_o(xbar_address_req[i]),
+          .dma_addr_resp_i(xbar_address_resp[i]),
           .trigger_slot_i({
             ext_trigger_slot_i[2*i+1], ext_trigger_slot_i[2*i], global_trigger_slot_i
           }),
           .dma_done_intr_o(dma_trans_done[i]),
-          .dma_window_intr_o(dma_window_done[i])
+          .dma_window_intr_o(dma_window_done[i]),
+          .dma_done_o(dma_done_o[i])
       );
     end
   endgenerate
 
 
   generate
-    if (core_v_mini_mcu_pkg::DMA_CH_NUM > 1) begin : xbar_varlat_n_to_one_gen
+    if (core_v_mini_mcu_pkg::DMA_CH_NUM > 1) begin : xbar_varlat_gen
 
       /* Register interface routing signals */
       logic [core_v_mini_mcu_pkg::DMA_CH_PORT_SEL_WIDTH-1:0] submodules_select;
 
-      /* Read, write & address mode operations xbar*/
-      xbar_varlat_n_to_one #(
-          .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
-      ) xbar_read_i (
-          .clk_i        (clk_i),
-          .rst_ni       (rst_ni),
-          .master_req_i (xbar_read_req),
-          .master_resp_o(xbar_read_resp),
-          .slave_req_o  (dma_read_ch0_req_o),
-          .slave_resp_i (dma_read_ch0_resp_i)
-      );
-
-      xbar_varlat_n_to_one #(
-          .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
-      ) xbar_write_i (
-          .clk_i        (clk_i),
-          .rst_ni       (rst_ni),
-          .master_req_i (xbar_write_req),
-          .master_resp_o(xbar_write_resp),
-          .slave_req_o  (dma_write_ch0_req_o),
-          .slave_resp_i (dma_write_ch0_resp_i)
-      );
-
-      xbar_varlat_n_to_one #(
-          .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
-      ) xbar_address_i (
-          .clk_i        (clk_i),
-          .rst_ni       (rst_ni),
-          .master_req_i (xbar_address_req),
-          .master_resp_o(xbar_address_resp),
-          .slave_req_o  (dma_addr_ch0_req_o),
-          .slave_resp_i (dma_addr_ch0_resp_i)
-      );
+      if (core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS > 1 && core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS != core_v_mini_mcu_pkg::DMA_CH_NUM) begin : xbar_n_to_m_gen
+
+        /* Read, write & address mode operations xbar*/
+        dma_NtoM_xbar #(
+            .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM),
+            .XBAR_MSLAVE(core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS)
+        ) xbar_read_i (
+            .clk_i(clk_i),
+            .rst_ni(rst_ni),
+            .master_req_i(xbar_read_req),
+            .master_resp_o(xbar_read_resp),
+            .slave_req_o(dma_read_req_o),
+            .slave_resp_i(dma_read_resp_i)
+        );
+
+        dma_NtoM_xbar #(
+            .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM),
+            .XBAR_MSLAVE(core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS)
+        ) xbar_write_i (
+            .clk_i(clk_i),
+            .rst_ni(rst_ni),
+            .master_req_i(xbar_write_req),
+            .master_resp_o(xbar_write_resp),
+            .slave_req_o(dma_write_req_o),
+            .slave_resp_i(dma_write_resp_i)
+        );
+
+        dma_NtoM_xbar #(
+            .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM),
+            .XBAR_MSLAVE(core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS)
+        ) xbar_address_i (
+            .clk_i(clk_i),
+            .rst_ni(rst_ni),
+            .master_req_i(xbar_address_req),
+            .master_resp_o(xbar_address_resp),
+            .slave_req_o(dma_addr_req_o),
+            .slave_resp_i(dma_addr_resp_i)
+        );
+      end else if (core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS > 1 && core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS == core_v_mini_mcu_pkg::DMA_CH_NUM) begin : xbar_n_to_n_gen
+        for (genvar i = 0 ; i < core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS; i++) begin
+          assign dma_read_req_o[i] = xbar_read_req[i];
+          assign xbar_read_resp[i] = dma_read_resp_i[i];
+          assign dma_write_req_o[i] = xbar_write_req[i];
+          assign xbar_write_resp[i] = dma_write_resp_i[i];
+          assign dma_addr_req_o[i] = xbar_address_req[i];
+          assign xbar_address_resp[i] = dma_addr_resp_i[i];
+        end
+
+      end else begin : xbar_n_to_1_gen
+        /* Read, write & address mode operations xbar*/
+        xbar_varlat_n_to_one #(
+            .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
+        ) xbar_read_i (
+            .clk_i        (clk_i),
+            .rst_ni       (rst_ni),
+            .master_req_i (xbar_read_req),
+            .master_resp_o(xbar_read_resp),
+            .slave_req_o  (dma_read_req_o[0]),
+            .slave_resp_i (dma_read_resp_i[0])
+        );
+
+        xbar_varlat_n_to_one #(
+            .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
+        ) xbar_write_i (
+            .clk_i        (clk_i),
+            .rst_ni       (rst_ni),
+            .master_req_i (xbar_write_req),
+            .master_resp_o(xbar_write_resp),
+            .slave_req_o  (dma_write_req_o[0]),
+            .slave_resp_i (dma_write_resp_i[0])
+        );
+
+        xbar_varlat_n_to_one #(
+            .XBAR_NMASTER(core_v_mini_mcu_pkg::DMA_CH_NUM)
+        ) xbar_address_i (
+            .clk_i        (clk_i),
+            .rst_ni       (rst_ni),
+            .master_req_i (xbar_address_req),
+            .master_resp_o(xbar_address_resp),
+            .slave_req_o  (dma_addr_req_o[0]),
+            .slave_resp_i (dma_addr_resp_i[0])
+        );
+      end
 
       /* Internal address decoder */
       addr_decode #(
@@ -176,12 +269,12 @@ module dma_subsystem #(
     end else begin
 
       /* Bus ports routing in the case of a single DMA */
-      assign dma_read_ch0_req_o = xbar_read_req[0];
-      assign xbar_read_resp[0] = dma_read_ch0_resp_i;
-      assign dma_write_ch0_req_o = xbar_write_req[0];
-      assign xbar_write_resp[0] = dma_write_ch0_resp_i;
-      assign dma_addr_ch0_req_o = xbar_address_req[0];
-      assign xbar_address_resp[0] = dma_addr_ch0_resp_i;
+      assign dma_read_req_o[0] = xbar_read_req[0];
+      assign xbar_read_resp[0] = dma_read_resp_i[0];
+      assign dma_write_req_o[0] = xbar_write_req[0];
+      assign xbar_write_resp[0] = dma_write_resp_i[0];
+      assign dma_addr_req_o[0] = xbar_address_req[0];
+      assign xbar_address_resp[0] = dma_addr_resp_i[0];
       assign submodules_req[0] = reg_req_i;
       assign reg_rsp_o = submodules_rsp[0];
     end
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl
index 0d336255..6c564b96 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.hjson.tpl
@@ -223,6 +223,17 @@
       ]
     }
 
+% for channel in range(int(dma_ch_count)):
+    { name:     "DMA_CH${channel}_CLK_GATE",
+      desc:     "Clock-gates the DMA CH${channel}",
+      resval:   "0x00000000"
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0", name: "DMA_CH${channel}_CLK_GATE", desc: "Clock-gates the DMA CH${channel}" }
+      ]
+    }
+% endfor
 
 % for bank in xheep.iter_ram_banks():
     { name:     "RAM_${bank.name()}_CLK_GATE",
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl
index 0e126670..a6abf35d 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/data/power_manager.sv.tpl
@@ -49,6 +49,7 @@ module power_manager import power_manager_pkg::*; #(
     output power_manager_out_t peripheral_subsystem_pwr_ctrl_o,
     output power_manager_out_t memory_subsystem_pwr_ctrl_o[core_v_mini_mcu_pkg::NUM_BANKS-1:0],
     output power_manager_out_t external_subsystem_pwr_ctrl_o[EXT_DOMAINS_RND-1:0],
+    output power_manager_out_t dma_subsystem_pwr_ctrl_o[core_v_mini_mcu_pkg::DMA_CH_NUM-1:0],
 
     // Power Manager input signals
     input power_manager_in_t cpu_subsystem_pwr_ctrl_i,
@@ -131,6 +132,10 @@ module power_manager import power_manager_pkg::*; #(
   assign memory_subsystem_pwr_ctrl_o[${bank.name()}].clkgate_en_n = ~reg2hw.ram_${bank.name()}_clk_gate.q;
 % endfor
 
+% for channel in range(int(dma_ch_count)):
+  assign dma_subsystem_pwr_ctrl_o[${channel}].clkgate_en_n = ~reg2hw.dma_ch${channel}_clk_gate.q;
+% endfor
+
 % if external_domains != 0:
 % for ext in range(external_domains):
     assign external_subsystem_pwr_ctrl_o[${ext}].pwrgate_en_n = external_subsystem_powergate_switch_n[${ext}];
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/power_manager_gen.sh b/hw/vendor/esl_epfl_x_heep/hw/ip/power_manager/power_manager_gen.sh
old mode 100644
new mode 100755
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/data/im2col_spc.hjson b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/data/im2col_spc.hjson
new file mode 100644
index 00000000..0319c03b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/data/im2col_spc.hjson
@@ -0,0 +1,255 @@
+// Copyright EPFL contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{ name: "im2col_spc",
+  clock_primary: "clk_i",
+  bus_interfaces: [
+    { protocol: "reg_iface", direction: "device" }
+  ],
+  regwidth: "32",
+  registers: [
+    { name:     "SRC_PTR",
+      desc:     "Input data pointer (word aligned)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "PTR_IN", desc: "Input data pointer (word aligned)" }
+      ]
+    },
+    { name:     "DST_PTR",
+      desc:     "Output data pointer (word aligned)",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "31:0", name: "PTR_OUT", desc: "Output data pointer (word aligned)" }
+      ]
+    },
+    { name:     "IW",
+      desc:     "Image width",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "15:0", name: "SIZE", desc: "Image width" }
+      ]
+    },
+    { name:     "IH",
+      desc:     "Image heigth",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "15:0", name: "SIZE", desc: "Image heigth" }
+      ]
+    },
+    { name:     "FW",
+      desc:     "Filter width",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "7:0", name: "SIZE", desc: "Filter width" }
+      ]
+    },
+    { name:     "FH",
+      desc:     "Filter heigth",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "7:0", name: "SIZE", desc: "Filter heigth" }
+      ]
+    },
+    { name:     "BATCH",
+      desc:     "Batch number",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "7:0", name: "SIZE", desc: "Batch size" }
+      ]
+    },
+    { name:     "NUM_CH",
+      desc:     "Number of channels. When written, the im2col will start executing",
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true",
+      fields: [
+        { bits: "7:0", name: "NUM", desc: "Number of channels" }
+      ]
+    },
+    { name:     "CH_COL",
+      desc:     "Number of iterations to perform",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "15:0", name: "NUM", desc: "Number of iterations" }
+      ]
+    },
+    { name:     "N_PATCHES_W",
+      desc:     "Number of patches along W",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "15:0", name: "NUM", desc: "Number of patches" }
+      ]
+    },
+    { name:     "N_PATCHES_H",
+      desc:     "Number of patches along H",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "15:0", name: "NUM", desc: "Number of patches" }
+      ]
+    },
+    { name:     "ADPT_PAD_RIGHT",
+      desc:     "Adapted right padded region",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "7:0", name: "SIZE", desc: "Size of the adapted padded region" }
+      ]
+    },
+    { name:     "ADPT_PAD_BOTTOM",
+      desc:     "Adapted bottom padded region",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "7:0", name: "SIZE", desc: "Size of the adapted padded region" }
+      ]
+    },
+    { name:     "LOG_STRIDES_D1",
+      desc:     "Logarithmic number of strides along D1, set to 1 for no stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "3:0", name: "SIZE", desc: "Stride size" }
+      ]
+    },
+    { name:     "LOG_STRIDES_D2",
+      desc:     "Logarithmic number of strides along D2, set to 1 for no stride",
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "3:0", name: "SIZE", desc: "Stride size" }
+      ]
+    },
+    { name:     "STATUS",
+      desc:     '''Status bit is set to one when the im2col SPC is ready''',
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext: "true",
+      hwre:     "true", // enable `re` latched signal of software read pulse
+      resval:   1,
+      fields: [
+        { bits: "0", name: "READY", desc: "SPC is done"},
+      ]
+    },
+    { name:     "SLOT",
+      desc:     '''The DMA will wait for the signal 
+                   connected to the selected trigger_slots to be high
+                   on the read and write side respectivly''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:   0,
+      fields: [
+        { bits: "15:0", name: "RX_TRIGGER_SLOT",
+          desc: "Slot selection mask"
+        },
+        { bits: "31:16", name: "TX_TRIGGER_SLOT",
+          desc: "Slot selection mask"
+        }
+      ]
+    },
+    { name:     "DATA_TYPE",
+      desc:     '''Width/type of the data to transfer''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:   0,
+      fields: [
+        { bits: "1:0", name: "DATA_TYPE", 
+          desc: "Data type",
+          enum: [
+            { value: "0", name: "DMA_32BIT_WORD", desc: "Transfers 32 bits"},
+            { value: "1", name: "DMA_16BIT_WORD", desc: "Transfers 16 bits"},
+            { value: "2", name: "DMA_8BIT_WORD" , desc: "Transfers  8 bits"},
+            { value: "3", name: "DMA_8BIT_WORD_2",desc: "Transfers  8 bits"},
+          ]
+        }
+      ]
+    },
+    { name:     "PAD_TOP",
+      desc:     '''Set the top padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Top margin padding (2D)"}
+      ]
+    },
+    { name:     "PAD_BOTTOM",
+      desc:     '''Set the bottom padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Bottom margin padding (2D)"}
+      ]
+    },
+    { name:     "PAD_RIGHT",
+      desc:     '''Set the right padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Right margin padding (1D/2D)"}
+      ]
+    },
+    { name:     "PAD_LEFT",
+      desc:     '''Set the left padding''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      hwqe:     "true", // enable `qe` latched signal of software write pulse: used to trigger the padding
+      resval:   0,
+      fields: [
+        { bits: "5:0", name: "PAD", desc: "Left margin padding (1D/2D)"}
+      ]
+    },
+    { name:    "INTERRUPT_EN",
+      desc:    '''Interrupt Enable Register''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      fields: [
+        { bits: "0", name: "EN", desc: "Enables operation done interrupt" }
+      ]
+    },
+    { name:    "SPC_IFR",
+      desc:    '''Interrupt Flag Register for the SPC operation''',
+      swaccess: "ro",
+      hwaccess: "hrw",
+      hwext:    "true",
+      hwre:     "true", // latched signal of software write pulse
+      resval:        0,
+      fields: [
+        { bits: "0", name: "FLAG", desc: "Set for operation done interrupt" }
+      ]
+    },
+    { name:    "SPC_CH_MASK",
+      desc:    '''Mask that defines which DMA channel the SPC can access''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:        1,
+      fields: [
+        { bits: "31:0", name: "MASK", desc: "Mask of DMA channel" }
+      ]
+    },
+    { name:    "SPC_CH_OFFSET",
+      desc:    '''Offset of the DMA channel the SPC can access''',
+      swaccess: "rw",
+      hwaccess: "hro",
+      resval:        1,
+      fields: [
+        { bits: "31:0", name: "OFF", desc: "Offset of DMA channels" }
+      ]
+    }
+   ]
+}
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.core b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.core
new file mode 100644
index 00000000..e196ccac
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.core
@@ -0,0 +1,28 @@
+CAPI=2:
+
+name: "example:ip:im2col_spc"
+description: "im2col smart peripheral controller"
+
+# Copyright 2024 OpenHW Group
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+filesets:
+  files_rtl:
+    depend:
+      - pulp-platform.org::common_cells
+      - x-heep:ip:dma
+    files:
+    - rtl/im2col_spc_reg_pkg.sv
+    - rtl/im2col_spc_reg_top.sv
+    - rtl/dma_if_pkg.sv
+    - rtl/pipe_reg.sv
+    - rtl/im2col_spc_regintfc_controller.sv
+    - rtl/im2col_spc_param_fsm.sv
+    - rtl/im2col_spc.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+    - files_rtl
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.vlt b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.vlt
new file mode 100644
index 00000000..1106245e
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc.vlt
@@ -0,0 +1,16 @@
+// Copyright 2022 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+`verilator_config
+
+lint_off -rule DECLFILENAME -file "*/im2col_spc_reg_top.sv"
+
+lint_off -rule WIDTH -file "*/rtl/im2col_spc_reg_top.sv" -match "Operator ASSIGNW expects *"
+ 
+lint_off -rule UNUSED -file "*/rtl/im2col_spc.sv" -match "Signal is not used: 'data_out_rvalid'"
+lint_off -rule UNUSED -file "*/rtl/im2col_spc.sv" -match "Signal is not used: 'data_out_rdata'"
+
+lint_off -rule UNUSED -file "*/rtl/im2col_spc.sv" -match "Bits of signal are not used: *"
+lint_off -rule UNUSED -file "*/rtl/im2col_spc_param_fsm.sv" -match "Bits of signal are not used: *"
+lint_off -rule UNUSED -file "*/rtl/im2col_spc_regintfc_controller.sv" -match "Bits of signal are not used: *"
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc_gen.sh b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc_gen.sh
new file mode 100755
index 00000000..c8050ec6
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/im2col_spc_gen.sh
@@ -0,0 +1,8 @@
+# Copyright EPFL contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+echo "Generating RTL"
+${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py -r -t rtl data/im2col_spc.hjson
+echo "Generating SW"
+${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py --cdefines -o ../../../sw/device/lib/drivers/im2col_spc/im2col_spc_regs.h data/im2col_spc.hjson
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/dma_if_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/dma_if_pkg.sv
new file mode 100644
index 00000000..fd9ceb56
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/dma_if_pkg.sv
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: This module defines the interface structure for the DMA registers.
+ */
+
+package dma_if_pkg;
+
+  typedef struct packed {
+    logic [31:0] input_ptr;
+    logic [31:0] output_ptr;
+    logic [22:0] in_inc_d2;
+    logic [7:0]  n_zeros_top;
+    logic [7:0]  n_zeros_bottom;
+    logic [7:0]  n_zeros_left;
+    logic [7:0]  n_zeros_right;
+    logic [15:0] size_du_d1;
+    logic [15:0] size_du_d2;
+  } dma_if_t;
+
+endpackage
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc.sv
new file mode 100644
index 00000000..be59baa2
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc.sv
@@ -0,0 +1,623 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Im2col accelerator implemented as a Smart Peripheral Controller. 
+ *       It accesses the DMA channels to perform the matrix manipulation operation known as 
+ *       "image to column" (im2col), which enables efficient CNN inference by transforming 
+ *       the input tensor to use the GEMM library.
+ */
+
+module im2col_spc
+  import obi_pkg::*;
+  import reg_pkg::*;
+#(
+) (
+    input logic clk_i,
+    input logic rst_ni,
+
+    input  reg_rsp_t aopb2im2col_resp_i,
+    output reg_req_t im2col2aopb_req_o,
+
+    input  reg_req_t reg_req_i,
+    output reg_rsp_t reg_rsp_o,
+
+    input logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_done_i,
+    output logic im2col_spc_done_int_o
+);
+
+  import core_v_mini_mcu_pkg::*;
+  import dma_if_pkg::*;
+  import im2col_spc_reg_pkg::*;
+  import dma_reg_pkg::*;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Parameter definition */
+
+  /* FIFO dimension */
+  localparam FIFO_DEPTH = 8;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* General status signal */
+  enum {
+    READY,
+    BUSY
+  } im2col_status;
+
+  /* Control Unit signals */
+  logic im2col_start;
+  logic im2col_fsms_done;
+  logic im2col_done;
+
+  /* Interrupt management signals */
+  logic im2col_spc_ifr;
+
+  /* DMA FIFO signals */
+  logic fifo_flush;
+  logic fifo_full;
+  logic fifo_empty;
+  dma_if_t fifo_input;
+  logic fifo_push;
+  dma_if_t fifo_output;
+  logic fifo_pop;
+  logic [$clog2(FIFO_DEPTH)-1:0] fifo_usage;
+
+  /* DMA interface unit signals */
+  logic im2col_param_done;
+  logic dma_ch_free;
+  logic dma_ch_first_write;
+  logic [31:0] dma_ch_en_mask;
+  logic [31:0] dma_ch_offset;
+  logic [31:0] dma_addr;
+  logic [31:0] dma_wdata;
+  logic dma_if_loaded;
+  logic dma_regintfc_start;
+  logic dma_regintfc_done;
+
+  /* Regtool signals */
+  im2col_spc_reg2hw_t reg2hw;
+  im2col_spc_hw2reg_t hw2reg;
+
+  enum {
+    READY_IF_CU,
+    IDLE_IF_CU,
+    GET_TRANSACTION,
+    LOAD_TRANSACTION
+  }
+      dma_if_cu_q, dma_if_cu_d;
+
+  enum {
+    IDLE_IF_LOAD,
+    WRITE_DIMENSIONALITY,
+    WRITE_SLOTS,
+    WRITE_SRC_DATATYPE,
+    WRITE_DST_DATATYPE,
+    WRITE_TOP_PAD,
+    WRITE_BOTTOM_PAD,
+    WRITE_LEFT_PAD,
+    WRITE_RIGHT_PAD,
+    WRITE_INPUT_PTR,
+    WRITE_OUTPUT_PTR,
+    WRITE_INC_SRC_D1,
+    WRITE_INC_SRC_D2,
+    WRITE_INC_DST_D1,
+    WRITE_INC_DST_D2,
+    WRITE_SIZE_D2,
+    WRITE_SIZE_D1,
+    DONE
+  }
+      dma_if_cu_load_q, dma_if_cu_load_d;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Module instantiation */
+
+  /* Regtool top module */
+  im2col_spc_reg_top #(
+      .reg_req_t(reg_req_t),
+      .reg_rsp_t(reg_rsp_t)
+  ) im2col_spc_reg_top_i (
+      .clk_i,
+      .rst_ni,
+      .reg_req_i,
+      .reg_rsp_o,
+      .reg2hw,
+      .hw2reg,
+      .devmode_i(1'b1)
+  );
+
+  /* DMA FIFO */
+  fifo_v3 #(
+      .DEPTH(FIFO_DEPTH),
+      .FALL_THROUGH(1'b1),
+      .dtype(dma_if_t)
+  ) dma_fifo_i (
+      .clk_i,
+      .rst_ni,
+      .flush_i(fifo_flush),
+      .testmode_i(1'b0),
+      // status flags
+      .full_o(fifo_full),
+      .empty_o(fifo_empty),
+      .usage_o(fifo_usage),
+      // as long as the queue is not full we can push new data
+      .data_i(fifo_input),
+      .push_i(fifo_push),
+      // as long as the queue is not empty we can pop new elements
+      .data_o(fifo_output),
+      .pop_i(fifo_pop)
+  );
+
+  /* Parameter FSM */
+  im2col_spc_param_fsm im2col_spc_param_fsm_i (
+      .clk_i,
+      .rst_ni,
+      .reg2hw_i(reg2hw),
+      .im2col_done_i(im2col_done),
+      .im2col_start_i(im2col_start),
+      .fifo_full_i(fifo_full),
+      .fifo_push_o(fifo_push),
+      .im2col_param_done_o(im2col_param_done),
+      .fifo_input_o(fifo_input)
+  );
+
+  /* Register interface control FSM */
+  im2col_spc_regintfc_controller im2col_spc_regintfc_controller_i (
+      .clk_i,
+      .rst_ni,
+      .addr_i(dma_addr),
+      .wdata_i(dma_wdata),
+      .start_i(dma_regintfc_start),
+      .aopb_resp_i(aopb2im2col_resp_i),
+      .aopb_req_o(im2col2aopb_req_o),
+      .done_o(dma_regintfc_done)
+  );
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* FSMs instantiation */
+
+  /* General status */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_im2col_status
+    if (!rst_ni) begin
+      im2col_status <= READY;
+    end else begin
+      if (im2col_done == 1'b1) begin
+        im2col_status <= READY;
+      end else if (im2col_start == 1'b1) begin
+        im2col_status <= BUSY;
+      end
+    end
+  end
+
+  /* DMA interface unit state transition logic */
+  always_comb begin : proc_comb_dma_if_fsm
+
+    unique case (dma_if_cu_d)
+      IDLE_IF_CU: begin
+        if (fifo_empty == 1'b0 && im2col_fsms_done == 1'b0 && dma_ch_free == 1'b1) begin
+          dma_if_cu_q = GET_TRANSACTION;
+        end else begin
+          dma_if_cu_q = IDLE_IF_CU;
+        end
+      end
+
+      GET_TRANSACTION: begin
+        if (fifo_empty == 1'b0 && dma_ch_free == 1'b1) begin
+          dma_if_cu_q = LOAD_TRANSACTION;
+        end else begin
+          dma_if_cu_q = IDLE_IF_CU;
+        end
+      end
+
+      LOAD_TRANSACTION: begin
+        if (dma_if_loaded == 1'b1) begin
+          if (im2col_fsms_done == 1'b0 && dma_ch_free == 1'b1) begin
+            dma_if_cu_q = GET_TRANSACTION;
+          end else begin
+            dma_if_cu_q = IDLE_IF_CU;
+          end
+        end else begin
+          dma_if_cu_q = LOAD_TRANSACTION;
+        end
+      end
+
+      default: begin
+        dma_if_cu_q = IDLE_IF_CU;
+      end
+    endcase
+  end
+
+  /* DMA interface unit state transition ff */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_dma_if_fsm
+    if (!rst_ni) begin
+      dma_if_cu_d <= IDLE_IF_CU;
+    end else begin
+      dma_if_cu_d <= dma_if_cu_q;
+    end
+  end
+
+  /* DMA interface unit transaction loading state transition logic */
+  always_comb begin : proc_comb_dma_if_trans_load_fsm
+    unique case (dma_if_cu_load_d)
+      IDLE_IF_LOAD: begin
+        if (dma_if_cu_d == GET_TRANSACTION && im2col_fsms_done == 1'b0 && dma_ch_free == 1'b1) begin
+          if (dma_ch_first_write == 1'b0) begin
+            dma_if_cu_load_q = WRITE_DIMENSIONALITY;
+          end else begin
+            dma_if_cu_load_q = WRITE_TOP_PAD;
+          end
+        end else begin
+          dma_if_cu_load_q = IDLE_IF_LOAD;
+        end
+      end
+
+      WRITE_DIMENSIONALITY: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_SLOTS;
+        end else if (dma_if_cu_d == IDLE_IF_CU) begin
+          dma_if_cu_load_q = IDLE_IF_LOAD;
+        end else begin
+          dma_if_cu_load_q = WRITE_DIMENSIONALITY;
+        end
+      end
+
+      WRITE_SLOTS: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_SRC_DATATYPE;
+        end else if (dma_if_cu_d == IDLE_IF_CU) begin
+          dma_if_cu_load_q = IDLE_IF_LOAD;
+        end else begin
+          dma_if_cu_load_q = WRITE_SLOTS;
+        end
+      end
+
+      WRITE_SRC_DATATYPE: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_DST_DATATYPE;
+        end else begin
+          dma_if_cu_load_q = WRITE_SRC_DATATYPE;
+        end
+      end
+
+      WRITE_DST_DATATYPE: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_TOP_PAD;
+        end else begin
+          dma_if_cu_load_q = WRITE_DST_DATATYPE;
+        end
+      end
+
+      WRITE_TOP_PAD: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_BOTTOM_PAD;
+        end else begin
+          dma_if_cu_load_q = WRITE_TOP_PAD;
+        end
+      end
+
+      WRITE_BOTTOM_PAD: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_LEFT_PAD;
+        end else begin
+          dma_if_cu_load_q = WRITE_BOTTOM_PAD;
+        end
+      end
+
+      WRITE_LEFT_PAD: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_RIGHT_PAD;
+        end else begin
+          dma_if_cu_load_q = WRITE_LEFT_PAD;
+        end
+      end
+
+      WRITE_RIGHT_PAD: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_INPUT_PTR;
+        end else begin
+          dma_if_cu_load_q = WRITE_RIGHT_PAD;
+        end
+      end
+
+      WRITE_INPUT_PTR: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_OUTPUT_PTR;
+        end else begin
+          dma_if_cu_load_q = WRITE_INPUT_PTR;
+        end
+      end
+
+      WRITE_OUTPUT_PTR: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_INC_SRC_D1;
+        end else begin
+          dma_if_cu_load_q = WRITE_OUTPUT_PTR;
+        end
+      end
+
+      WRITE_INC_SRC_D1: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_INC_SRC_D2;
+        end else begin
+          dma_if_cu_load_q = WRITE_INC_SRC_D1;
+        end
+      end
+
+      WRITE_INC_SRC_D2: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_INC_DST_D1;
+        end else begin
+          dma_if_cu_load_q = WRITE_INC_SRC_D2;
+        end
+      end
+
+      WRITE_INC_DST_D1: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_INC_DST_D2;
+        end else begin
+          dma_if_cu_load_q = WRITE_INC_DST_D1;
+        end
+      end
+
+      WRITE_INC_DST_D2: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_SIZE_D2;
+        end else begin
+          dma_if_cu_load_q = WRITE_INC_DST_D2;
+        end
+      end
+
+      WRITE_SIZE_D2: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = WRITE_SIZE_D1;
+        end else begin
+          dma_if_cu_load_q = WRITE_SIZE_D2;
+        end
+      end
+
+      WRITE_SIZE_D1: begin
+        if (dma_regintfc_done == 1'b1) begin
+          dma_if_cu_load_q = DONE;
+        end else begin
+          dma_if_cu_load_q = WRITE_SIZE_D1;
+        end
+      end
+
+      DONE: begin
+        dma_if_cu_load_q = IDLE_IF_LOAD;
+      end
+
+      default: begin
+        dma_if_cu_load_q = IDLE_IF_LOAD;
+      end
+
+    endcase
+  end
+
+  always_comb begin : proc_comb_dma_if_trans_load_fsm_regintfc
+    dma_if_loaded = 1'b0;
+    dma_regintfc_start = 1'b0;
+    fifo_pop = 1'b0;
+    dma_wdata = '0;
+    dma_addr = '0;
+
+    unique case (dma_if_cu_load_d)
+      IDLE_IF_LOAD: begin
+      end
+
+      WRITE_DIMENSIONALITY: begin
+        dma_wdata = 32'h1;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_DIM_CONFIG_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_SLOTS: begin
+        dma_wdata = {reg2hw.slot.tx_trigger_slot.q, reg2hw.slot.rx_trigger_slot.q};
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_SLOT_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_SRC_DATATYPE: begin
+        dma_wdata = {30'h0, reg2hw.data_type.q} & 32'h3;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_SRC_DATA_TYPE_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_DST_DATATYPE: begin
+        dma_wdata = {30'h0, reg2hw.data_type.q} & 32'h3;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_DST_DATA_TYPE_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_TOP_PAD: begin
+        dma_wdata = {24'h0, fifo_output.n_zeros_top};
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_PAD_TOP_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_BOTTOM_PAD: begin
+        dma_wdata = {24'h0, fifo_output.n_zeros_bottom};
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_PAD_BOTTOM_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_LEFT_PAD: begin
+        dma_wdata = {24'h0, fifo_output.n_zeros_left};
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_PAD_LEFT_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_RIGHT_PAD: begin
+        dma_wdata = {24'h0, fifo_output.n_zeros_right};
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_PAD_RIGHT_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_INPUT_PTR: begin
+        dma_wdata = fifo_output.input_ptr;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_SRC_PTR_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_OUTPUT_PTR: begin
+        dma_wdata = fifo_output.output_ptr;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_DST_PTR_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_INC_SRC_D1: begin
+        dma_wdata = (1 << {28'h0, reg2hw.log_strides_d1.q}) << (2 - reg2hw.data_type.q) & 32'h3f;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_SRC_PTR_INC_D1_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_INC_SRC_D2: begin
+        dma_wdata = {9'h0, fifo_output.in_inc_d2} << (2 - reg2hw.data_type.q) & 32'h7fffff;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_SRC_PTR_INC_D2_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_INC_DST_D1: begin
+        dma_wdata = (4 >> reg2hw.data_type.q) & 32'h3f;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_DST_PTR_INC_D1_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_INC_DST_D2: begin
+        dma_wdata = (4 >> reg2hw.data_type.q) & 32'h7fffff;
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_DST_PTR_INC_D2_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_SIZE_D2: begin
+        dma_wdata = {16'h0, fifo_output.size_du_d2};
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_SIZE_D2_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      WRITE_SIZE_D1: begin
+        dma_wdata = {16'h0, fifo_output.size_du_d1};
+        dma_addr = dma_ch_offset + {25'h0, dma_reg_pkg::DMA_SIZE_D1_OFFSET};
+        dma_regintfc_start = 1'b1;
+      end
+
+      DONE: begin
+        dma_if_loaded = 1'b1;
+        fifo_pop = 1'b1;
+      end
+    endcase
+  end
+
+  /* DMA interface unit transaction loading state transition ff */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_dma_if_trans_load_dq
+    if (!rst_ni) begin
+      dma_if_cu_load_d <= IDLE_IF_LOAD;
+    end else begin
+      dma_if_cu_load_d <= dma_if_cu_load_q;
+    end
+  end
+
+  /* Channel tracker */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_control_unit
+    if (!rst_ni) begin
+      dma_ch_free <= 1'b1;
+      dma_ch_first_write <= 1'b0;
+    end else begin
+      /* Set the dma_ch_free when im2col starts or when a transaction is finished */
+      if (im2col_start == 1'b1) begin
+        dma_ch_first_write <= 1'b0;
+        dma_ch_free <= 1'b1;
+      end
+
+      if (|(dma_ch_en_mask[core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] & dma_done_i) == 1'b1) begin
+        dma_ch_free <= 1'b1;
+      end
+
+      /* Clear the ch free flag only if the next state won't be the IDLE state */
+      if (dma_if_cu_d == GET_TRANSACTION && dma_if_cu_q != IDLE_IF_CU) begin
+        dma_ch_first_write <= 1'b1;
+        dma_ch_free <= 1'b0;
+      end
+    end
+  end
+
+  /* FIFO reset */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_fifo_reset
+    if (!rst_ni) begin
+      fifo_flush <= 1'b1;
+    end else begin
+      fifo_flush <= 1'b0;
+    end
+  end
+
+  /* Transaction IFR update */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_spc_ifr
+    if (~rst_ni) begin
+      im2col_spc_ifr <= '0;
+    end else if (reg2hw.interrupt_en.q == 1'b1) begin
+      // Enter here only if the im2col_done interrupt is enabled
+      if (im2col_done == 1'b1) begin
+        im2col_spc_ifr <= 1'b1;
+      end else if (reg2hw.spc_ifr.re == 1'b1) begin
+        // If the IFR bit is read, we must clear the transaction_ifr
+        im2col_spc_ifr <= 1'b0;
+      end
+    end
+  end
+
+  /* Global fsm done signal update logic */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_spc_done
+    if (!rst_ni) begin
+      im2col_fsms_done <= 1'b0;
+    end else begin
+      if (im2col_done == 1'b1) begin
+        im2col_fsms_done <= 1'b0;
+      end else if (dma_if_cu_load_d == DONE && im2col_param_done == 1'b1 && fifo_usage == 1) begin
+        im2col_fsms_done <= 1'b1;
+      end
+    end
+  end
+
+  /* Global done signal update logic */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_done
+    if (!rst_ni) begin
+      im2col_done <= 1'b0;
+    end else begin
+      if (im2col_fsms_done == 1'b1 && dma_ch_free == 1'b1) begin
+        im2col_done <= 1'b1;
+      end else begin
+        im2col_done <= 1'b0;
+      end
+    end
+  end
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  /* Start signal assignment */
+  assign im2col_start = (reg2hw.num_ch.qe == 1'b1);
+
+  /* Transaction loading process */
+  assign hw2reg.status.d = im2col_status == READY;
+
+  /* Interrupt management */
+  assign hw2reg.spc_ifr.d = im2col_spc_ifr;
+  assign im2col_spc_done_int_o = im2col_spc_ifr;
+
+  /* DMA channels mask register */
+  assign dma_ch_en_mask = reg2hw.spc_ch_mask.q;
+
+  /* DMA channel offset */
+  assign dma_ch_offset = reg2hw.spc_ch_offset.q;
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_param_fsm.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_param_fsm.sv
new file mode 100644
index 00000000..2bd1d190
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_param_fsm.sv
@@ -0,0 +1,551 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Parameter FSM of the im2col accelerator.
+ */
+
+module im2col_spc_param_fsm
+  import im2col_spc_reg_pkg::*;
+  import dma_if_pkg::*;
+(
+    input logic clk_i,
+    input logic rst_ni,
+    input im2col_spc_reg2hw_t reg2hw_i,
+    input logic im2col_done_i,
+    input logic fifo_full_i,
+    input logic im2col_start_i,
+    output logic fifo_push_o,
+    output logic im2col_param_done_o,
+    output dma_if_t fifo_input_o
+
+);
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signals declaration */
+
+  /* Register interface */
+  im2col_spc_reg2hw_t reg2hw;
+
+  /* 
+   * Every "comp" state refers to variable computations that precede the DMA call in the 
+   * loop, while any "param" state refers to the DMA parameters computation that follows the DMA call.
+   */
+  enum {
+    IDLE,
+    N_ZEROS_PRECOMP,
+    ZEROS_COND_EVAL,
+    N_ZEROS_COMP_1,
+    N_ZEROS_COMP_2,
+    N_ZEROS_COMP_3,
+    OUT_PTR_UPDATE,
+    IM_OFFSET_UPDATE,
+    INDEX_COMP_1,
+    INDEX_COMP_2,
+    INDEX_COMP_3,
+    START_DMA_RUN
+  }
+      param_state_q, param_state_d;
+
+  /* Parameters computation signals */
+  logic [7:0] w_offset;
+  logic [7:0] h_offset;
+  logic [7:0] im_c;
+  logic [7:0] im_row;
+  logic [7:0] im_col;
+  logic [7:0] fw_min_w_offset;
+  logic [7:0] fh_min_h_offset;
+  logic [7:0] n_zeros_left;
+  logic [7:0] n_zeros_right;
+  logic [7:0] n_zeros_top;
+  logic [7:0] n_zeros_bottom;
+  logic [15:0] size_transfer_1d;
+  logic [15:0] size_transfer_2d;
+  logic [31:0] index;
+  logic [31:0] h_offset_counter;
+  logic [31:0] im_c_counter;
+  logic [15:0] ch_col_counter;
+  logic [7:0] batch_counter;
+  logic [31:0] input_data_ptr;
+  logic [31:0] output_data_ptr;
+  logic [31:0] source_inc_d2;
+  logic [31:0] out_data_ptr_inc;
+  logic left_zero_cond;
+  logic top_zero_cond;
+  logic right_zero_cond;
+  logic bottom_zero_cond;
+  logic [7:0] n_zeros_left_std;
+  logic [7:0] n_zeros_top_std;
+  logic [7:0] n_zeros_right_std;
+  logic [7:0] n_zeros_bottom_std;
+
+  /* Pipelining control signals */
+  logic output_data_ptr_en;
+  logic im_offset_en;
+  logic batch_inc_en;
+  logic batch_rst;
+  logic zeros_phase1_en;
+  logic zeros_phase2_en;
+  logic zeros_rst;
+  logic output_data_ptr_rst;
+  logic pipe_rst;
+
+  /* Status signals */
+  logic im2col_param_done;
+  logic im2col_done;
+  logic im2col_start;
+  logic fifo_push;
+  logic fifo_full;
+
+  /* Pipelining signals */
+  logic [7:0] n_zeros_left_comp1_n;
+  logic [7:0] n_zeros_top_comp1_n;
+  logic [7:0] n_zeros_right_comp1_n;
+  logic [7:0] n_zeros_bottom_comp1_n;
+  logic [7:0] n_zeros_left_comp1;
+  logic [7:0] n_zeros_top_comp1;
+  logic [7:0] n_zeros_right_comp1;
+  logic [7:0] n_zeros_bottom_comp1;
+  logic [31:0] index_comp1_n;
+  logic [31:0] index_comp2_n;
+  logic [31:0] index_comp3_n;
+  logic [31:0] index_comp4_n;
+  logic [31:0] index_comp1;
+  logic [31:0] index_comp2;
+  logic [31:0] index_comp3;
+  logic [31:0] index_comp4;
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* FSMs instantiation */
+
+  /* Parameter computation state transition ff */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_param_state_dq
+    if (!rst_ni) begin
+      param_state_d <= IDLE;
+    end else begin
+      param_state_d <= param_state_q;
+    end
+  end
+
+  /* Parameter computation done signal update */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_param_done
+    if (!rst_ni) begin
+      im2col_param_done <= 1'b0;
+    end else begin
+      if (im2col_done == 1'b1) begin
+        im2col_param_done <= 1'b0;
+      end else if (ch_col_counter == (reg2hw.ch_col.q - 1) && batch_counter == reg2hw.batch.q) begin
+        im2col_param_done <= 1'b1;
+      end
+    end
+  end
+
+  /* Parameter computation state transition FSM */
+  always_comb begin : proc_comb_param_state_fsm
+    fifo_push = 1'b0;
+    batch_inc_en = 1'b0;
+    batch_rst = 1'b0;
+    output_data_ptr_en = 1'b0;
+    im_offset_en = 1'b0;
+    zeros_phase1_en = 1'b0;
+    zeros_phase2_en = 1'b0;
+    zeros_rst = 1'b0;
+    output_data_ptr_rst = 1'b0;
+
+    unique case (param_state_d)
+
+      IDLE: begin
+        batch_rst = 1'b1;
+        zeros_rst = 1'b1;
+        output_data_ptr_rst = 1'b1;
+        if (im2col_start == 1'b1) begin
+          param_state_q = N_ZEROS_PRECOMP;
+        end else begin
+          param_state_q = IDLE;
+        end
+      end
+
+      /* Cycle needed to precompute parts of both the zero condition and the number of zero computations
+       * and to reduce the datapath for FPGA targets. Every signal is identical to the IDLE state.
+       * @Tod0: is this really necessary?
+       */
+      N_ZEROS_PRECOMP: begin
+        batch_rst = 1'b1;
+        zeros_rst = 1'b1;
+        output_data_ptr_rst = 1'b1;
+        param_state_q = ZEROS_COND_EVAL;
+      end
+
+      ZEROS_COND_EVAL: begin
+        if (im2col_param_done == 1'b1) begin
+          param_state_q = IDLE;
+        end else begin
+          param_state_q = N_ZEROS_COMP_1;
+        end
+      end
+
+      N_ZEROS_COMP_1: begin
+        zeros_phase1_en = 1'b1;
+        param_state_q   = N_ZEROS_COMP_2;
+      end
+
+      N_ZEROS_COMP_2: begin
+        zeros_phase2_en = 1'b1;
+        param_state_q   = N_ZEROS_COMP_3;
+      end
+
+      N_ZEROS_COMP_3: begin
+        zeros_phase2_en = 1'b1;
+        param_state_q   = INDEX_COMP_1;
+      end
+
+      INDEX_COMP_1: begin
+        param_state_q = INDEX_COMP_2;
+      end
+
+      INDEX_COMP_2: begin
+        param_state_q = INDEX_COMP_3;
+      end
+
+      INDEX_COMP_3: begin
+        if (fifo_full == 1'b0) begin
+          param_state_q = START_DMA_RUN;
+        end else begin
+          param_state_q = INDEX_COMP_3;
+        end
+      end
+
+      OUT_PTR_UPDATE: begin
+        batch_inc_en = 1'b1;
+        output_data_ptr_en = 1'b1;
+        if (batch_counter == reg2hw.batch.q - 1) begin
+          param_state_q = IM_OFFSET_UPDATE;
+        end else begin
+          param_state_q = ZEROS_COND_EVAL;
+        end
+      end
+
+      IM_OFFSET_UPDATE: begin
+        batch_rst = 1'b1;
+        im_offset_en = 1'b1;
+        param_state_q = ZEROS_COND_EVAL;
+      end
+
+      START_DMA_RUN: begin
+        fifo_push = 1'b1;
+        param_state_q = OUT_PTR_UPDATE;
+      end
+
+      default: begin
+        param_state_q = IDLE;
+      end
+
+    endcase
+  end
+
+  /* Number of zeros computation */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_zeros_phase1_comp
+    if (!rst_ni) begin
+      fw_min_w_offset <= '0;
+      fh_min_h_offset <= '0;
+    end else begin
+      if (zeros_phase1_en == 1'b1) begin
+        fw_min_w_offset <= reg2hw.fw.q - 1 - w_offset;
+        fh_min_h_offset <= reg2hw.fh.q - 1 - h_offset;
+      end else if (zeros_rst == 1'b1) begin
+        fw_min_w_offset <= '0;
+        fh_min_h_offset <= '0;
+      end
+    end
+  end
+
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_zeros_phase2_comp
+    if (!rst_ni) begin
+      n_zeros_left <= '0;
+      n_zeros_right <= '0;
+      n_zeros_top <= '0;
+      n_zeros_bottom <= '0;
+    end else begin
+      if (zeros_phase2_en == 1'b1) begin
+        /* Left zeros computation */
+        if (w_offset >= {2'h0, reg2hw.pad_left.q}) begin
+          n_zeros_left <= 0;
+        end else begin
+          n_zeros_left <= n_zeros_left_std + {7'h0, left_zero_cond};  // Sum a 1 if the condition is true
+        end
+
+        /* Top zeros computation */
+        if (h_offset >= {2'h0, reg2hw.pad_top.q}) begin
+          n_zeros_top <= 0;
+        end else begin
+          n_zeros_top <= n_zeros_top_std + {7'h0, top_zero_cond};
+        end
+
+        /* Right zeros computation */
+        if (fw_min_w_offset >= {2'h0, reg2hw.pad_right.q} || reg2hw.adpt_pad_right.q == 0) begin
+          n_zeros_right <= 0;
+        end else begin
+          n_zeros_right <= n_zeros_right_std + {7'h0, right_zero_cond};
+        end
+
+        /* Bottom zeros computation */
+        if (fh_min_h_offset >= {2'h0, reg2hw.pad_bottom.q} || reg2hw.adpt_pad_bottom.q == 0) begin
+          n_zeros_bottom <= 0;
+        end else begin
+          n_zeros_bottom <= n_zeros_bottom_std + {7'h0, bottom_zero_cond};
+        end
+      end else if (zeros_rst == 1'b1) begin
+        n_zeros_left <= '0;
+        n_zeros_right <= '0;
+        n_zeros_top <= '0;
+        n_zeros_bottom <= '0;
+      end
+    end
+  end
+
+
+  /* Batch counter */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_batch_counter
+    if (!rst_ni) begin
+      batch_counter <= '0;
+    end else begin
+      if (batch_inc_en == 1'b1) begin
+        batch_counter <= batch_counter + 1;
+      end else if (batch_rst == 1'b1) begin
+        batch_counter <= '0;
+      end
+    end
+  end
+
+  /* w_offset counter */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_w_offset_counter
+    if (!rst_ni) begin
+      w_offset <= '0;
+    end else begin
+      if (im2col_param_done == 1'b1) begin
+        w_offset <= '0;
+      end else if (im_offset_en == 1'b1) begin
+        if (w_offset == reg2hw.fw.q - 1) begin
+          w_offset <= '0;
+        end else begin
+          w_offset <= w_offset + 1;
+        end
+      end
+    end
+  end
+
+  /* h_offset counter */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_h_offset_counter
+    if (!rst_ni) begin
+      h_offset <= '0;
+      h_offset_counter <= '0;
+    end else begin
+      if (im2col_param_done == 1'b1) begin
+        h_offset <= '0;
+        h_offset_counter <= '0;
+      end else if (im_offset_en == 1'b1) begin
+        if (h_offset_counter == {24'h0, reg2hw.fw.q} - 1) begin
+          h_offset_counter <= '0;
+          if (h_offset == reg2hw.fh.q - 1) begin
+            h_offset <= '0;
+          end else begin
+            h_offset <= h_offset + 1;
+          end
+        end else begin
+          h_offset_counter <= h_offset_counter + 1;
+        end
+      end
+    end
+  end
+
+  /* im_c counter */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_im_c_counter
+    if (!rst_ni) begin
+      im_c <= '0;
+      im_c_counter <= '0;
+    end else begin
+      if (im2col_param_done == 1'b1) begin
+        im_c <= '0;
+        im_c_counter <= '0;
+      end else if (im_offset_en == 1'b1) begin
+        if (im_c_counter == {24'h0, reg2hw.fh.q} * {24'h0, reg2hw.fw.q} - 1) begin
+          im_c_counter <= '0;
+          im_c <= im_c + 1;
+        end else begin
+          im_c_counter <= im_c_counter + 1;
+        end
+      end
+    end
+  end
+
+  /* ch_col counter */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_ch_col_counter
+    if (!rst_ni) begin
+      ch_col_counter <= '0;
+    end else begin
+      if (im2col_param_done == 1'b1) begin
+        ch_col_counter <= '0;
+      end else if (im_offset_en == 1'b1) begin
+        if (ch_col_counter == reg2hw.ch_col.q - 1) begin
+          ch_col_counter <= '0;
+        end else begin
+          ch_col_counter <= ch_col_counter + 1;
+        end
+      end
+    end
+  end
+
+  /* Output data pointer counter */
+  always_ff @(posedge clk_i, negedge rst_ni) begin : proc_ff_output_data_ptr
+    if (!rst_ni) begin
+      output_data_ptr <= reg2hw.dst_ptr.q;
+    end else begin
+      if (output_data_ptr_en == 1'b1) begin
+        output_data_ptr <= output_data_ptr + out_data_ptr_inc;
+      end else if (output_data_ptr_rst == 1'b1) begin
+        output_data_ptr <= reg2hw.dst_ptr.q;
+      end
+    end
+  end
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Modules instantiation */
+
+  /* Pipeline modules */
+  pipe_reg #(
+      .WIDTH(8)
+  ) pipe_reg_left_zeros (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (n_zeros_left_comp1_n),
+      .data_out(n_zeros_left_comp1)
+  );
+
+  pipe_reg #(
+      .WIDTH(8)
+  ) pipe_reg_top_zeros (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (n_zeros_top_comp1_n),
+      .data_out(n_zeros_top_comp1)
+  );
+
+  pipe_reg #(
+      .WIDTH(8)
+  ) pipe_reg_right_zeros (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (n_zeros_right_comp1_n),
+      .data_out(n_zeros_right_comp1)
+  );
+
+  pipe_reg #(
+      .WIDTH(8)
+  ) pipe_reg_bottom_zeros (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (n_zeros_bottom_comp1_n),
+      .data_out(n_zeros_bottom_comp1)
+  );
+
+  pipe_reg #(
+      .WIDTH(32)
+  ) pipe_reg_index_comp1 (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (index_comp1_n),
+      .data_out(index_comp1)
+  );
+
+  pipe_reg #(
+      .WIDTH(32)
+  ) pipe_reg_index_comp2 (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (index_comp2_n),
+      .data_out(index_comp2)
+  );
+
+  pipe_reg #(
+      .WIDTH(32)
+  ) pipe_reg_index_comp3 (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (index_comp3_n),
+      .data_out(index_comp3)
+  );
+
+  pipe_reg #(
+      .WIDTH(32)
+  ) pipe_reg_index_comp4 (
+      .clk_i,
+      .rst_ni  (pipe_rst),
+      .data_in (index_comp4_n),
+      .data_out(index_comp4)
+  );
+
+
+  /*_________________________________________________________________________________________________________________________________ */
+
+  /* Signal assignments */
+
+  assign im_row = h_offset - {2'h0, reg2hw.pad_top.q};  // im_row = h_offset - TOP_PAD;
+  assign im_col = w_offset - {2'h0, reg2hw.pad_left.q};  // im_col = w_offset - LEFT_PAD;
+
+  assign n_zeros_left_comp1_n = ({2'h0, reg2hw.pad_left.q} - w_offset);
+  assign n_zeros_left_std = n_zeros_left_comp1 >> {4'h0, reg2hw.log_strides_d1.q};
+
+  assign n_zeros_top_comp1_n = ({2'h0, reg2hw.pad_top.q} - h_offset);
+  assign n_zeros_top_std = n_zeros_top_comp1 >> {4'h0, reg2hw.log_strides_d2.q};
+
+  assign n_zeros_right_comp1_n = (reg2hw.adpt_pad_right.q - fw_min_w_offset);
+  assign n_zeros_right_std = n_zeros_right_comp1 >> {4'h0, reg2hw.log_strides_d1.q};
+
+  assign n_zeros_bottom_comp1_n = (reg2hw.adpt_pad_bottom.q - fh_min_h_offset);
+  assign n_zeros_bottom_std = n_zeros_bottom_comp1 >> {4'h0, reg2hw.log_strides_d2.q};
+
+  assign size_transfer_1d = reg2hw.n_patches_w.q - {8'h0, n_zeros_left} - {8'h0, n_zeros_right};
+  assign size_transfer_2d = reg2hw.n_patches_h.q - {8'h0, n_zeros_top} - {8'h0, n_zeros_bottom};
+
+  assign index_comp1_n = ({24'h0, batch_counter} * {24'h0, reg2hw.num_ch.q} + {24'h0, im_c});
+  assign index_comp2_n = index_comp1 * {16'h0, reg2hw.ih.q};
+  assign index_comp3_n = (index_comp2 + ({{24{im_row[7]}}, im_row} + ({24'h0, n_zeros_top} << {4'h0, reg2hw.log_strides_d2.q})));
+  assign index_comp4_n = index_comp3 * {16'h0, reg2hw.iw.q} + {{24{im_col[7]}}, im_col};
+  assign index = index_comp4 + ({24'h0, n_zeros_left} << {24'h0, reg2hw.log_strides_d1.q});
+
+  assign source_inc_d2 = (({16'h0, reg2hw.iw.q} << {24'h0, reg2hw.log_strides_d2.q}) - (({16'h0, size_transfer_1d} - 1) << {24'h0, reg2hw.log_strides_d1.q}));
+  assign input_data_ptr = reg2hw.src_ptr.q + (index << (2 - reg2hw.data_type.q));
+  assign out_data_ptr_inc = ({16'h0, reg2hw.n_patches_h.q} * {16'h0, reg2hw.n_patches_w.q}) << (2 - reg2hw.data_type.q);
+
+  assign left_zero_cond = |((n_zeros_left_comp1) & ((1 << {reg2hw.log_strides_d1.q}) - 1));
+  assign top_zero_cond = |((n_zeros_top_comp1) & ((1 << {reg2hw.log_strides_d2.q}) - 1));
+  assign right_zero_cond = |((n_zeros_right_comp1) & ((1 << {reg2hw.log_strides_d1.q}) - 1));
+  assign bottom_zero_cond = |((n_zeros_bottom_comp1) & ((1 << {reg2hw.log_strides_d2.q}) - 1));
+
+  assign pipe_rst = (rst_ni && param_state_d != IDLE);
+
+  /* Output signals */
+  assign im2col_param_done_o = im2col_param_done;
+  assign reg2hw = reg2hw_i;
+  assign im2col_done = im2col_done_i;
+  assign im2col_start = im2col_start_i;
+  assign fifo_push_o = fifo_push;
+  assign fifo_full = fifo_full_i;
+
+  assign fifo_input_o.input_ptr = input_data_ptr;
+  assign fifo_input_o.output_ptr = output_data_ptr;
+  assign fifo_input_o.in_inc_d2 = source_inc_d2[22:0];
+  assign fifo_input_o.n_zeros_top = n_zeros_top;
+  assign fifo_input_o.n_zeros_bottom = n_zeros_bottom;
+  assign fifo_input_o.n_zeros_left = n_zeros_left;
+  assign fifo_input_o.n_zeros_right = n_zeros_right;
+  assign fifo_input_o.size_du_d1 = size_transfer_1d;
+  assign fifo_input_o.size_du_d2 = size_transfer_2d;
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_pkg.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_pkg.sv
new file mode 100644
index 00000000..2db852b7
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_pkg.sv
@@ -0,0 +1,227 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package im2col_spc_reg_pkg;
+
+  // Address widths within the block
+  parameter int BlockAw = 7;
+
+  ////////////////////////////
+  // Typedefs for registers //
+  ////////////////////////////
+
+  typedef struct packed {logic [31:0] q;} im2col_spc_reg2hw_src_ptr_reg_t;
+
+  typedef struct packed {logic [31:0] q;} im2col_spc_reg2hw_dst_ptr_reg_t;
+
+  typedef struct packed {logic [15:0] q;} im2col_spc_reg2hw_iw_reg_t;
+
+  typedef struct packed {logic [15:0] q;} im2col_spc_reg2hw_ih_reg_t;
+
+  typedef struct packed {logic [7:0] q;} im2col_spc_reg2hw_fw_reg_t;
+
+  typedef struct packed {logic [7:0] q;} im2col_spc_reg2hw_fh_reg_t;
+
+  typedef struct packed {logic [7:0] q;} im2col_spc_reg2hw_batch_reg_t;
+
+  typedef struct packed {
+    logic [7:0] q;
+    logic       qe;
+  } im2col_spc_reg2hw_num_ch_reg_t;
+
+  typedef struct packed {logic [15:0] q;} im2col_spc_reg2hw_ch_col_reg_t;
+
+  typedef struct packed {logic [15:0] q;} im2col_spc_reg2hw_n_patches_w_reg_t;
+
+  typedef struct packed {logic [15:0] q;} im2col_spc_reg2hw_n_patches_h_reg_t;
+
+  typedef struct packed {logic [7:0] q;} im2col_spc_reg2hw_adpt_pad_right_reg_t;
+
+  typedef struct packed {logic [7:0] q;} im2col_spc_reg2hw_adpt_pad_bottom_reg_t;
+
+  typedef struct packed {logic [3:0] q;} im2col_spc_reg2hw_log_strides_d1_reg_t;
+
+  typedef struct packed {logic [3:0] q;} im2col_spc_reg2hw_log_strides_d2_reg_t;
+
+  typedef struct packed {
+    logic q;
+    logic re;
+  } im2col_spc_reg2hw_status_reg_t;
+
+  typedef struct packed {
+    struct packed {logic [15:0] q;} rx_trigger_slot;
+    struct packed {logic [15:0] q;} tx_trigger_slot;
+  } im2col_spc_reg2hw_slot_reg_t;
+
+  typedef struct packed {logic [1:0] q;} im2col_spc_reg2hw_data_type_reg_t;
+
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } im2col_spc_reg2hw_pad_top_reg_t;
+
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } im2col_spc_reg2hw_pad_bottom_reg_t;
+
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } im2col_spc_reg2hw_pad_right_reg_t;
+
+  typedef struct packed {
+    logic [5:0] q;
+    logic       qe;
+  } im2col_spc_reg2hw_pad_left_reg_t;
+
+  typedef struct packed {logic q;} im2col_spc_reg2hw_interrupt_en_reg_t;
+
+  typedef struct packed {
+    logic q;
+    logic re;
+  } im2col_spc_reg2hw_spc_ifr_reg_t;
+
+  typedef struct packed {logic [31:0] q;} im2col_spc_reg2hw_spc_ch_mask_reg_t;
+
+  typedef struct packed {logic [31:0] q;} im2col_spc_reg2hw_spc_ch_offset_reg_t;
+
+  typedef struct packed {logic d;} im2col_spc_hw2reg_status_reg_t;
+
+  typedef struct packed {logic d;} im2col_spc_hw2reg_spc_ifr_reg_t;
+
+  // Register -> HW type
+  typedef struct packed {
+    im2col_spc_reg2hw_src_ptr_reg_t src_ptr;  // [331:300]
+    im2col_spc_reg2hw_dst_ptr_reg_t dst_ptr;  // [299:268]
+    im2col_spc_reg2hw_iw_reg_t iw;  // [267:252]
+    im2col_spc_reg2hw_ih_reg_t ih;  // [251:236]
+    im2col_spc_reg2hw_fw_reg_t fw;  // [235:228]
+    im2col_spc_reg2hw_fh_reg_t fh;  // [227:220]
+    im2col_spc_reg2hw_batch_reg_t batch;  // [219:212]
+    im2col_spc_reg2hw_num_ch_reg_t num_ch;  // [211:203]
+    im2col_spc_reg2hw_ch_col_reg_t ch_col;  // [202:187]
+    im2col_spc_reg2hw_n_patches_w_reg_t n_patches_w;  // [186:171]
+    im2col_spc_reg2hw_n_patches_h_reg_t n_patches_h;  // [170:155]
+    im2col_spc_reg2hw_adpt_pad_right_reg_t adpt_pad_right;  // [154:147]
+    im2col_spc_reg2hw_adpt_pad_bottom_reg_t adpt_pad_bottom;  // [146:139]
+    im2col_spc_reg2hw_log_strides_d1_reg_t log_strides_d1;  // [138:135]
+    im2col_spc_reg2hw_log_strides_d2_reg_t log_strides_d2;  // [134:131]
+    im2col_spc_reg2hw_status_reg_t status;  // [130:129]
+    im2col_spc_reg2hw_slot_reg_t slot;  // [128:97]
+    im2col_spc_reg2hw_data_type_reg_t data_type;  // [96:95]
+    im2col_spc_reg2hw_pad_top_reg_t pad_top;  // [94:88]
+    im2col_spc_reg2hw_pad_bottom_reg_t pad_bottom;  // [87:81]
+    im2col_spc_reg2hw_pad_right_reg_t pad_right;  // [80:74]
+    im2col_spc_reg2hw_pad_left_reg_t pad_left;  // [73:67]
+    im2col_spc_reg2hw_interrupt_en_reg_t interrupt_en;  // [66:66]
+    im2col_spc_reg2hw_spc_ifr_reg_t spc_ifr;  // [65:64]
+    im2col_spc_reg2hw_spc_ch_mask_reg_t spc_ch_mask;  // [63:32]
+    im2col_spc_reg2hw_spc_ch_offset_reg_t spc_ch_offset;  // [31:0]
+  } im2col_spc_reg2hw_t;
+
+  // HW -> register type
+  typedef struct packed {
+    im2col_spc_hw2reg_status_reg_t  status;   // [1:1]
+    im2col_spc_hw2reg_spc_ifr_reg_t spc_ifr;  // [0:0]
+  } im2col_spc_hw2reg_t;
+
+  // Register offsets
+  parameter logic [BlockAw-1:0] IM2COL_SPC_SRC_PTR_OFFSET = 7'h0;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_DST_PTR_OFFSET = 7'h4;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_IW_OFFSET = 7'h8;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_IH_OFFSET = 7'hc;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_FW_OFFSET = 7'h10;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_FH_OFFSET = 7'h14;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_BATCH_OFFSET = 7'h18;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_NUM_CH_OFFSET = 7'h1c;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_CH_COL_OFFSET = 7'h20;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_N_PATCHES_W_OFFSET = 7'h24;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_N_PATCHES_H_OFFSET = 7'h28;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_ADPT_PAD_RIGHT_OFFSET = 7'h2c;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_ADPT_PAD_BOTTOM_OFFSET = 7'h30;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_LOG_STRIDES_D1_OFFSET = 7'h34;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_LOG_STRIDES_D2_OFFSET = 7'h38;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_STATUS_OFFSET = 7'h3c;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_SLOT_OFFSET = 7'h40;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_DATA_TYPE_OFFSET = 7'h44;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_PAD_TOP_OFFSET = 7'h48;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_PAD_BOTTOM_OFFSET = 7'h4c;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_PAD_RIGHT_OFFSET = 7'h50;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_PAD_LEFT_OFFSET = 7'h54;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_INTERRUPT_EN_OFFSET = 7'h58;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_SPC_IFR_OFFSET = 7'h5c;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_SPC_CH_MASK_OFFSET = 7'h60;
+  parameter logic [BlockAw-1:0] IM2COL_SPC_SPC_CH_OFFSET_OFFSET = 7'h64;
+
+  // Reset values for hwext registers and their fields
+  parameter logic [0:0] IM2COL_SPC_STATUS_RESVAL = 1'h1;
+  parameter logic [0:0] IM2COL_SPC_STATUS_READY_RESVAL = 1'h1;
+  parameter logic [0:0] IM2COL_SPC_SPC_IFR_RESVAL = 1'h0;
+  parameter logic [0:0] IM2COL_SPC_SPC_IFR_FLAG_RESVAL = 1'h0;
+
+  // Register index
+  typedef enum int {
+    IM2COL_SPC_SRC_PTR,
+    IM2COL_SPC_DST_PTR,
+    IM2COL_SPC_IW,
+    IM2COL_SPC_IH,
+    IM2COL_SPC_FW,
+    IM2COL_SPC_FH,
+    IM2COL_SPC_BATCH,
+    IM2COL_SPC_NUM_CH,
+    IM2COL_SPC_CH_COL,
+    IM2COL_SPC_N_PATCHES_W,
+    IM2COL_SPC_N_PATCHES_H,
+    IM2COL_SPC_ADPT_PAD_RIGHT,
+    IM2COL_SPC_ADPT_PAD_BOTTOM,
+    IM2COL_SPC_LOG_STRIDES_D1,
+    IM2COL_SPC_LOG_STRIDES_D2,
+    IM2COL_SPC_STATUS,
+    IM2COL_SPC_SLOT,
+    IM2COL_SPC_DATA_TYPE,
+    IM2COL_SPC_PAD_TOP,
+    IM2COL_SPC_PAD_BOTTOM,
+    IM2COL_SPC_PAD_RIGHT,
+    IM2COL_SPC_PAD_LEFT,
+    IM2COL_SPC_INTERRUPT_EN,
+    IM2COL_SPC_SPC_IFR,
+    IM2COL_SPC_SPC_CH_MASK,
+    IM2COL_SPC_SPC_CH_OFFSET
+  } im2col_spc_id_e;
+
+  // Register width information to check illegal writes
+  parameter logic [3:0] IM2COL_SPC_PERMIT[26] = '{
+      4'b1111,  // index[ 0] IM2COL_SPC_SRC_PTR
+      4'b1111,  // index[ 1] IM2COL_SPC_DST_PTR
+      4'b0011,  // index[ 2] IM2COL_SPC_IW
+      4'b0011,  // index[ 3] IM2COL_SPC_IH
+      4'b0001,  // index[ 4] IM2COL_SPC_FW
+      4'b0001,  // index[ 5] IM2COL_SPC_FH
+      4'b0001,  // index[ 6] IM2COL_SPC_BATCH
+      4'b0001,  // index[ 7] IM2COL_SPC_NUM_CH
+      4'b0011,  // index[ 8] IM2COL_SPC_CH_COL
+      4'b0011,  // index[ 9] IM2COL_SPC_N_PATCHES_W
+      4'b0011,  // index[10] IM2COL_SPC_N_PATCHES_H
+      4'b0001,  // index[11] IM2COL_SPC_ADPT_PAD_RIGHT
+      4'b0001,  // index[12] IM2COL_SPC_ADPT_PAD_BOTTOM
+      4'b0001,  // index[13] IM2COL_SPC_LOG_STRIDES_D1
+      4'b0001,  // index[14] IM2COL_SPC_LOG_STRIDES_D2
+      4'b0001,  // index[15] IM2COL_SPC_STATUS
+      4'b1111,  // index[16] IM2COL_SPC_SLOT
+      4'b0001,  // index[17] IM2COL_SPC_DATA_TYPE
+      4'b0001,  // index[18] IM2COL_SPC_PAD_TOP
+      4'b0001,  // index[19] IM2COL_SPC_PAD_BOTTOM
+      4'b0001,  // index[20] IM2COL_SPC_PAD_RIGHT
+      4'b0001,  // index[21] IM2COL_SPC_PAD_LEFT
+      4'b0001,  // index[22] IM2COL_SPC_INTERRUPT_EN
+      4'b0001,  // index[23] IM2COL_SPC_SPC_IFR
+      4'b1111,  // index[24] IM2COL_SPC_SPC_CH_MASK
+      4'b1111  // index[25] IM2COL_SPC_SPC_CH_OFFSET
+  };
+
+endpackage
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_top.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_top.sv
new file mode 100644
index 00000000..a364f98c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_reg_top.sv
@@ -0,0 +1,1182 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+
+`include "common_cells/assertions.svh"
+
+module im2col_spc_reg_top #(
+    parameter type reg_req_t = logic,
+    parameter type reg_rsp_t = logic,
+    parameter int AW = 7
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input reg_req_t reg_req_i,
+    output reg_rsp_t reg_rsp_o,
+    // To HW
+    output im2col_spc_reg_pkg::im2col_spc_reg2hw_t reg2hw,  // Write
+    input im2col_spc_reg_pkg::im2col_spc_hw2reg_t hw2reg,  // Read
+
+
+    // Config
+    input devmode_i  // If 1, explicit error return for unmapped register access
+);
+
+  import im2col_spc_reg_pkg::*;
+
+  localparam int DW = 32;
+  localparam int DBW = DW / 8;  // Byte Width
+
+  // register signals
+  logic           reg_we;
+  logic           reg_re;
+  logic [ AW-1:0] reg_addr;
+  logic [ DW-1:0] reg_wdata;
+  logic [DBW-1:0] reg_be;
+  logic [ DW-1:0] reg_rdata;
+  logic           reg_error;
+
+  logic addrmiss, wr_err;
+
+  logic [DW-1:0] reg_rdata_next;
+
+  // Below register interface can be changed
+  reg_req_t reg_intf_req;
+  reg_rsp_t reg_intf_rsp;
+
+
+  assign reg_intf_req = reg_req_i;
+  assign reg_rsp_o = reg_intf_rsp;
+
+
+  assign reg_we = reg_intf_req.valid & reg_intf_req.write;
+  assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
+  assign reg_addr = reg_intf_req.addr;
+  assign reg_wdata = reg_intf_req.wdata;
+  assign reg_be = reg_intf_req.wstrb;
+  assign reg_intf_rsp.rdata = reg_rdata;
+  assign reg_intf_rsp.error = reg_error;
+  assign reg_intf_rsp.ready = 1'b1;
+
+  assign reg_rdata = reg_rdata_next;
+  assign reg_error = (devmode_i & addrmiss) | wr_err;
+
+
+  // Define SW related signals
+  // Format: <reg>_<field>_{wd|we|qs}
+  //        or <reg>_{wd|we|qs} if field == 1 or 0
+  logic [31:0] src_ptr_qs;
+  logic [31:0] src_ptr_wd;
+  logic src_ptr_we;
+  logic [31:0] dst_ptr_qs;
+  logic [31:0] dst_ptr_wd;
+  logic dst_ptr_we;
+  logic [15:0] iw_qs;
+  logic [15:0] iw_wd;
+  logic iw_we;
+  logic [15:0] ih_qs;
+  logic [15:0] ih_wd;
+  logic ih_we;
+  logic [7:0] fw_qs;
+  logic [7:0] fw_wd;
+  logic fw_we;
+  logic [7:0] fh_qs;
+  logic [7:0] fh_wd;
+  logic fh_we;
+  logic [7:0] batch_qs;
+  logic [7:0] batch_wd;
+  logic batch_we;
+  logic [7:0] num_ch_qs;
+  logic [7:0] num_ch_wd;
+  logic num_ch_we;
+  logic [15:0] ch_col_qs;
+  logic [15:0] ch_col_wd;
+  logic ch_col_we;
+  logic [15:0] n_patches_w_qs;
+  logic [15:0] n_patches_w_wd;
+  logic n_patches_w_we;
+  logic [15:0] n_patches_h_qs;
+  logic [15:0] n_patches_h_wd;
+  logic n_patches_h_we;
+  logic [7:0] adpt_pad_right_qs;
+  logic [7:0] adpt_pad_right_wd;
+  logic adpt_pad_right_we;
+  logic [7:0] adpt_pad_bottom_qs;
+  logic [7:0] adpt_pad_bottom_wd;
+  logic adpt_pad_bottom_we;
+  logic [3:0] log_strides_d1_qs;
+  logic [3:0] log_strides_d1_wd;
+  logic log_strides_d1_we;
+  logic [3:0] log_strides_d2_qs;
+  logic [3:0] log_strides_d2_wd;
+  logic log_strides_d2_we;
+  logic status_qs;
+  logic status_re;
+  logic [15:0] slot_rx_trigger_slot_qs;
+  logic [15:0] slot_rx_trigger_slot_wd;
+  logic slot_rx_trigger_slot_we;
+  logic [15:0] slot_tx_trigger_slot_qs;
+  logic [15:0] slot_tx_trigger_slot_wd;
+  logic slot_tx_trigger_slot_we;
+  logic [1:0] data_type_qs;
+  logic [1:0] data_type_wd;
+  logic data_type_we;
+  logic [5:0] pad_top_qs;
+  logic [5:0] pad_top_wd;
+  logic pad_top_we;
+  logic [5:0] pad_bottom_qs;
+  logic [5:0] pad_bottom_wd;
+  logic pad_bottom_we;
+  logic [5:0] pad_right_qs;
+  logic [5:0] pad_right_wd;
+  logic pad_right_we;
+  logic [5:0] pad_left_qs;
+  logic [5:0] pad_left_wd;
+  logic pad_left_we;
+  logic interrupt_en_qs;
+  logic interrupt_en_wd;
+  logic interrupt_en_we;
+  logic spc_ifr_qs;
+  logic spc_ifr_re;
+  logic [31:0] spc_ch_mask_qs;
+  logic [31:0] spc_ch_mask_wd;
+  logic spc_ch_mask_we;
+  logic [31:0] spc_ch_offset_qs;
+  logic [31:0] spc_ch_offset_wd;
+  logic spc_ch_offset_we;
+
+  // Register instances
+  // R[src_ptr]: V(False)
+
+  prim_subreg #(
+      .DW      (32),
+      .SWACCESS("RW"),
+      .RESVAL  (32'h0)
+  ) u_src_ptr (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(src_ptr_we),
+      .wd(src_ptr_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.src_ptr.q),
+
+      // to register interface (read)
+      .qs(src_ptr_qs)
+  );
+
+
+  // R[dst_ptr]: V(False)
+
+  prim_subreg #(
+      .DW      (32),
+      .SWACCESS("RW"),
+      .RESVAL  (32'h0)
+  ) u_dst_ptr (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(dst_ptr_we),
+      .wd(dst_ptr_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.dst_ptr.q),
+
+      // to register interface (read)
+      .qs(dst_ptr_qs)
+  );
+
+
+  // R[iw]: V(False)
+
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_iw (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(iw_we),
+      .wd(iw_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.iw.q),
+
+      // to register interface (read)
+      .qs(iw_qs)
+  );
+
+
+  // R[ih]: V(False)
+
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_ih (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(ih_we),
+      .wd(ih_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.ih.q),
+
+      // to register interface (read)
+      .qs(ih_qs)
+  );
+
+
+  // R[fw]: V(False)
+
+  prim_subreg #(
+      .DW      (8),
+      .SWACCESS("RW"),
+      .RESVAL  (8'h0)
+  ) u_fw (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(fw_we),
+      .wd(fw_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.fw.q),
+
+      // to register interface (read)
+      .qs(fw_qs)
+  );
+
+
+  // R[fh]: V(False)
+
+  prim_subreg #(
+      .DW      (8),
+      .SWACCESS("RW"),
+      .RESVAL  (8'h0)
+  ) u_fh (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(fh_we),
+      .wd(fh_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.fh.q),
+
+      // to register interface (read)
+      .qs(fh_qs)
+  );
+
+
+  // R[batch]: V(False)
+
+  prim_subreg #(
+      .DW      (8),
+      .SWACCESS("RW"),
+      .RESVAL  (8'h0)
+  ) u_batch (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(batch_we),
+      .wd(batch_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.batch.q),
+
+      // to register interface (read)
+      .qs(batch_qs)
+  );
+
+
+  // R[num_ch]: V(False)
+
+  prim_subreg #(
+      .DW      (8),
+      .SWACCESS("RW"),
+      .RESVAL  (8'h0)
+  ) u_num_ch (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(num_ch_we),
+      .wd(num_ch_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.num_ch.qe),
+      .q (reg2hw.num_ch.q),
+
+      // to register interface (read)
+      .qs(num_ch_qs)
+  );
+
+
+  // R[ch_col]: V(False)
+
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_ch_col (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(ch_col_we),
+      .wd(ch_col_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.ch_col.q),
+
+      // to register interface (read)
+      .qs(ch_col_qs)
+  );
+
+
+  // R[n_patches_w]: V(False)
+
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_n_patches_w (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(n_patches_w_we),
+      .wd(n_patches_w_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.n_patches_w.q),
+
+      // to register interface (read)
+      .qs(n_patches_w_qs)
+  );
+
+
+  // R[n_patches_h]: V(False)
+
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_n_patches_h (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(n_patches_h_we),
+      .wd(n_patches_h_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.n_patches_h.q),
+
+      // to register interface (read)
+      .qs(n_patches_h_qs)
+  );
+
+
+  // R[adpt_pad_right]: V(False)
+
+  prim_subreg #(
+      .DW      (8),
+      .SWACCESS("RW"),
+      .RESVAL  (8'h0)
+  ) u_adpt_pad_right (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(adpt_pad_right_we),
+      .wd(adpt_pad_right_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.adpt_pad_right.q),
+
+      // to register interface (read)
+      .qs(adpt_pad_right_qs)
+  );
+
+
+  // R[adpt_pad_bottom]: V(False)
+
+  prim_subreg #(
+      .DW      (8),
+      .SWACCESS("RW"),
+      .RESVAL  (8'h0)
+  ) u_adpt_pad_bottom (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(adpt_pad_bottom_we),
+      .wd(adpt_pad_bottom_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.adpt_pad_bottom.q),
+
+      // to register interface (read)
+      .qs(adpt_pad_bottom_qs)
+  );
+
+
+  // R[log_strides_d1]: V(False)
+
+  prim_subreg #(
+      .DW      (4),
+      .SWACCESS("RW"),
+      .RESVAL  (4'h0)
+  ) u_log_strides_d1 (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(log_strides_d1_we),
+      .wd(log_strides_d1_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.log_strides_d1.q),
+
+      // to register interface (read)
+      .qs(log_strides_d1_qs)
+  );
+
+
+  // R[log_strides_d2]: V(False)
+
+  prim_subreg #(
+      .DW      (4),
+      .SWACCESS("RW"),
+      .RESVAL  (4'h0)
+  ) u_log_strides_d2 (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(log_strides_d2_we),
+      .wd(log_strides_d2_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.log_strides_d2.q),
+
+      // to register interface (read)
+      .qs(log_strides_d2_qs)
+  );
+
+
+  // R[status]: V(True)
+
+  prim_subreg_ext #(
+      .DW(1)
+  ) u_status (
+      .re (status_re),
+      .we (1'b0),
+      .wd ('0),
+      .d  (hw2reg.status.d),
+      .qre(reg2hw.status.re),
+      .qe (),
+      .q  (reg2hw.status.q),
+      .qs (status_qs)
+  );
+
+
+  // R[slot]: V(False)
+
+  //   F[rx_trigger_slot]: 15:0
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_slot_rx_trigger_slot (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(slot_rx_trigger_slot_we),
+      .wd(slot_rx_trigger_slot_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.slot.rx_trigger_slot.q),
+
+      // to register interface (read)
+      .qs(slot_rx_trigger_slot_qs)
+  );
+
+
+  //   F[tx_trigger_slot]: 31:16
+  prim_subreg #(
+      .DW      (16),
+      .SWACCESS("RW"),
+      .RESVAL  (16'h0)
+  ) u_slot_tx_trigger_slot (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(slot_tx_trigger_slot_we),
+      .wd(slot_tx_trigger_slot_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.slot.tx_trigger_slot.q),
+
+      // to register interface (read)
+      .qs(slot_tx_trigger_slot_qs)
+  );
+
+
+  // R[data_type]: V(False)
+
+  prim_subreg #(
+      .DW      (2),
+      .SWACCESS("RW"),
+      .RESVAL  (2'h0)
+  ) u_data_type (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(data_type_we),
+      .wd(data_type_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.data_type.q),
+
+      // to register interface (read)
+      .qs(data_type_qs)
+  );
+
+
+  // R[pad_top]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_top (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_top_we),
+      .wd(pad_top_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_top.qe),
+      .q (reg2hw.pad_top.q),
+
+      // to register interface (read)
+      .qs(pad_top_qs)
+  );
+
+
+  // R[pad_bottom]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_bottom (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_bottom_we),
+      .wd(pad_bottom_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_bottom.qe),
+      .q (reg2hw.pad_bottom.q),
+
+      // to register interface (read)
+      .qs(pad_bottom_qs)
+  );
+
+
+  // R[pad_right]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_right (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_right_we),
+      .wd(pad_right_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_right.qe),
+      .q (reg2hw.pad_right.q),
+
+      // to register interface (read)
+      .qs(pad_right_qs)
+  );
+
+
+  // R[pad_left]: V(False)
+
+  prim_subreg #(
+      .DW      (6),
+      .SWACCESS("RW"),
+      .RESVAL  (6'h0)
+  ) u_pad_left (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(pad_left_we),
+      .wd(pad_left_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(reg2hw.pad_left.qe),
+      .q (reg2hw.pad_left.q),
+
+      // to register interface (read)
+      .qs(pad_left_qs)
+  );
+
+
+  // R[interrupt_en]: V(False)
+
+  prim_subreg #(
+      .DW      (1),
+      .SWACCESS("RW"),
+      .RESVAL  (1'h0)
+  ) u_interrupt_en (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(interrupt_en_we),
+      .wd(interrupt_en_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.interrupt_en.q),
+
+      // to register interface (read)
+      .qs(interrupt_en_qs)
+  );
+
+
+  // R[spc_ifr]: V(True)
+
+  prim_subreg_ext #(
+      .DW(1)
+  ) u_spc_ifr (
+      .re (spc_ifr_re),
+      .we (1'b0),
+      .wd ('0),
+      .d  (hw2reg.spc_ifr.d),
+      .qre(reg2hw.spc_ifr.re),
+      .qe (),
+      .q  (reg2hw.spc_ifr.q),
+      .qs (spc_ifr_qs)
+  );
+
+
+  // R[spc_ch_mask]: V(False)
+
+  prim_subreg #(
+      .DW      (32),
+      .SWACCESS("RW"),
+      .RESVAL  (32'h1)
+  ) u_spc_ch_mask (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(spc_ch_mask_we),
+      .wd(spc_ch_mask_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.spc_ch_mask.q),
+
+      // to register interface (read)
+      .qs(spc_ch_mask_qs)
+  );
+
+
+  // R[spc_ch_offset]: V(False)
+
+  prim_subreg #(
+      .DW      (32),
+      .SWACCESS("RW"),
+      .RESVAL  (32'h1)
+  ) u_spc_ch_offset (
+      .clk_i (clk_i),
+      .rst_ni(rst_ni),
+
+      // from register interface
+      .we(spc_ch_offset_we),
+      .wd(spc_ch_offset_wd),
+
+      // from internal hardware
+      .de(1'b0),
+      .d ('0),
+
+      // to internal hardware
+      .qe(),
+      .q (reg2hw.spc_ch_offset.q),
+
+      // to register interface (read)
+      .qs(spc_ch_offset_qs)
+  );
+
+
+
+
+  logic [25:0] addr_hit;
+  always_comb begin
+    addr_hit = '0;
+    addr_hit[0] = (reg_addr == IM2COL_SPC_SRC_PTR_OFFSET);
+    addr_hit[1] = (reg_addr == IM2COL_SPC_DST_PTR_OFFSET);
+    addr_hit[2] = (reg_addr == IM2COL_SPC_IW_OFFSET);
+    addr_hit[3] = (reg_addr == IM2COL_SPC_IH_OFFSET);
+    addr_hit[4] = (reg_addr == IM2COL_SPC_FW_OFFSET);
+    addr_hit[5] = (reg_addr == IM2COL_SPC_FH_OFFSET);
+    addr_hit[6] = (reg_addr == IM2COL_SPC_BATCH_OFFSET);
+    addr_hit[7] = (reg_addr == IM2COL_SPC_NUM_CH_OFFSET);
+    addr_hit[8] = (reg_addr == IM2COL_SPC_CH_COL_OFFSET);
+    addr_hit[9] = (reg_addr == IM2COL_SPC_N_PATCHES_W_OFFSET);
+    addr_hit[10] = (reg_addr == IM2COL_SPC_N_PATCHES_H_OFFSET);
+    addr_hit[11] = (reg_addr == IM2COL_SPC_ADPT_PAD_RIGHT_OFFSET);
+    addr_hit[12] = (reg_addr == IM2COL_SPC_ADPT_PAD_BOTTOM_OFFSET);
+    addr_hit[13] = (reg_addr == IM2COL_SPC_LOG_STRIDES_D1_OFFSET);
+    addr_hit[14] = (reg_addr == IM2COL_SPC_LOG_STRIDES_D2_OFFSET);
+    addr_hit[15] = (reg_addr == IM2COL_SPC_STATUS_OFFSET);
+    addr_hit[16] = (reg_addr == IM2COL_SPC_SLOT_OFFSET);
+    addr_hit[17] = (reg_addr == IM2COL_SPC_DATA_TYPE_OFFSET);
+    addr_hit[18] = (reg_addr == IM2COL_SPC_PAD_TOP_OFFSET);
+    addr_hit[19] = (reg_addr == IM2COL_SPC_PAD_BOTTOM_OFFSET);
+    addr_hit[20] = (reg_addr == IM2COL_SPC_PAD_RIGHT_OFFSET);
+    addr_hit[21] = (reg_addr == IM2COL_SPC_PAD_LEFT_OFFSET);
+    addr_hit[22] = (reg_addr == IM2COL_SPC_INTERRUPT_EN_OFFSET);
+    addr_hit[23] = (reg_addr == IM2COL_SPC_SPC_IFR_OFFSET);
+    addr_hit[24] = (reg_addr == IM2COL_SPC_SPC_CH_MASK_OFFSET);
+    addr_hit[25] = (reg_addr == IM2COL_SPC_SPC_CH_OFFSET_OFFSET);
+  end
+
+  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0;
+
+  // Check sub-word write is permitted
+  always_comb begin
+    wr_err = (reg_we &
+              ((addr_hit[ 0] & (|(IM2COL_SPC_PERMIT[ 0] & ~reg_be))) |
+               (addr_hit[ 1] & (|(IM2COL_SPC_PERMIT[ 1] & ~reg_be))) |
+               (addr_hit[ 2] & (|(IM2COL_SPC_PERMIT[ 2] & ~reg_be))) |
+               (addr_hit[ 3] & (|(IM2COL_SPC_PERMIT[ 3] & ~reg_be))) |
+               (addr_hit[ 4] & (|(IM2COL_SPC_PERMIT[ 4] & ~reg_be))) |
+               (addr_hit[ 5] & (|(IM2COL_SPC_PERMIT[ 5] & ~reg_be))) |
+               (addr_hit[ 6] & (|(IM2COL_SPC_PERMIT[ 6] & ~reg_be))) |
+               (addr_hit[ 7] & (|(IM2COL_SPC_PERMIT[ 7] & ~reg_be))) |
+               (addr_hit[ 8] & (|(IM2COL_SPC_PERMIT[ 8] & ~reg_be))) |
+               (addr_hit[ 9] & (|(IM2COL_SPC_PERMIT[ 9] & ~reg_be))) |
+               (addr_hit[10] & (|(IM2COL_SPC_PERMIT[10] & ~reg_be))) |
+               (addr_hit[11] & (|(IM2COL_SPC_PERMIT[11] & ~reg_be))) |
+               (addr_hit[12] & (|(IM2COL_SPC_PERMIT[12] & ~reg_be))) |
+               (addr_hit[13] & (|(IM2COL_SPC_PERMIT[13] & ~reg_be))) |
+               (addr_hit[14] & (|(IM2COL_SPC_PERMIT[14] & ~reg_be))) |
+               (addr_hit[15] & (|(IM2COL_SPC_PERMIT[15] & ~reg_be))) |
+               (addr_hit[16] & (|(IM2COL_SPC_PERMIT[16] & ~reg_be))) |
+               (addr_hit[17] & (|(IM2COL_SPC_PERMIT[17] & ~reg_be))) |
+               (addr_hit[18] & (|(IM2COL_SPC_PERMIT[18] & ~reg_be))) |
+               (addr_hit[19] & (|(IM2COL_SPC_PERMIT[19] & ~reg_be))) |
+               (addr_hit[20] & (|(IM2COL_SPC_PERMIT[20] & ~reg_be))) |
+               (addr_hit[21] & (|(IM2COL_SPC_PERMIT[21] & ~reg_be))) |
+               (addr_hit[22] & (|(IM2COL_SPC_PERMIT[22] & ~reg_be))) |
+               (addr_hit[23] & (|(IM2COL_SPC_PERMIT[23] & ~reg_be))) |
+               (addr_hit[24] & (|(IM2COL_SPC_PERMIT[24] & ~reg_be))) |
+               (addr_hit[25] & (|(IM2COL_SPC_PERMIT[25] & ~reg_be)))));
+  end
+
+  assign src_ptr_we = addr_hit[0] & reg_we & !reg_error;
+  assign src_ptr_wd = reg_wdata[31:0];
+
+  assign dst_ptr_we = addr_hit[1] & reg_we & !reg_error;
+  assign dst_ptr_wd = reg_wdata[31:0];
+
+  assign iw_we = addr_hit[2] & reg_we & !reg_error;
+  assign iw_wd = reg_wdata[15:0];
+
+  assign ih_we = addr_hit[3] & reg_we & !reg_error;
+  assign ih_wd = reg_wdata[15:0];
+
+  assign fw_we = addr_hit[4] & reg_we & !reg_error;
+  assign fw_wd = reg_wdata[7:0];
+
+  assign fh_we = addr_hit[5] & reg_we & !reg_error;
+  assign fh_wd = reg_wdata[7:0];
+
+  assign batch_we = addr_hit[6] & reg_we & !reg_error;
+  assign batch_wd = reg_wdata[7:0];
+
+  assign num_ch_we = addr_hit[7] & reg_we & !reg_error;
+  assign num_ch_wd = reg_wdata[7:0];
+
+  assign ch_col_we = addr_hit[8] & reg_we & !reg_error;
+  assign ch_col_wd = reg_wdata[15:0];
+
+  assign n_patches_w_we = addr_hit[9] & reg_we & !reg_error;
+  assign n_patches_w_wd = reg_wdata[15:0];
+
+  assign n_patches_h_we = addr_hit[10] & reg_we & !reg_error;
+  assign n_patches_h_wd = reg_wdata[15:0];
+
+  assign adpt_pad_right_we = addr_hit[11] & reg_we & !reg_error;
+  assign adpt_pad_right_wd = reg_wdata[7:0];
+
+  assign adpt_pad_bottom_we = addr_hit[12] & reg_we & !reg_error;
+  assign adpt_pad_bottom_wd = reg_wdata[7:0];
+
+  assign log_strides_d1_we = addr_hit[13] & reg_we & !reg_error;
+  assign log_strides_d1_wd = reg_wdata[3:0];
+
+  assign log_strides_d2_we = addr_hit[14] & reg_we & !reg_error;
+  assign log_strides_d2_wd = reg_wdata[3:0];
+
+  assign status_re = addr_hit[15] & reg_re & !reg_error;
+
+  assign slot_rx_trigger_slot_we = addr_hit[16] & reg_we & !reg_error;
+  assign slot_rx_trigger_slot_wd = reg_wdata[15:0];
+
+  assign slot_tx_trigger_slot_we = addr_hit[16] & reg_we & !reg_error;
+  assign slot_tx_trigger_slot_wd = reg_wdata[31:16];
+
+  assign data_type_we = addr_hit[17] & reg_we & !reg_error;
+  assign data_type_wd = reg_wdata[1:0];
+
+  assign pad_top_we = addr_hit[18] & reg_we & !reg_error;
+  assign pad_top_wd = reg_wdata[5:0];
+
+  assign pad_bottom_we = addr_hit[19] & reg_we & !reg_error;
+  assign pad_bottom_wd = reg_wdata[5:0];
+
+  assign pad_right_we = addr_hit[20] & reg_we & !reg_error;
+  assign pad_right_wd = reg_wdata[5:0];
+
+  assign pad_left_we = addr_hit[21] & reg_we & !reg_error;
+  assign pad_left_wd = reg_wdata[5:0];
+
+  assign interrupt_en_we = addr_hit[22] & reg_we & !reg_error;
+  assign interrupt_en_wd = reg_wdata[0];
+
+  assign spc_ifr_re = addr_hit[23] & reg_re & !reg_error;
+
+  assign spc_ch_mask_we = addr_hit[24] & reg_we & !reg_error;
+  assign spc_ch_mask_wd = reg_wdata[31:0];
+
+  assign spc_ch_offset_we = addr_hit[25] & reg_we & !reg_error;
+  assign spc_ch_offset_wd = reg_wdata[31:0];
+
+  // Read data return
+  always_comb begin
+    reg_rdata_next = '0;
+    unique case (1'b1)
+      addr_hit[0]: begin
+        reg_rdata_next[31:0] = src_ptr_qs;
+      end
+
+      addr_hit[1]: begin
+        reg_rdata_next[31:0] = dst_ptr_qs;
+      end
+
+      addr_hit[2]: begin
+        reg_rdata_next[15:0] = iw_qs;
+      end
+
+      addr_hit[3]: begin
+        reg_rdata_next[15:0] = ih_qs;
+      end
+
+      addr_hit[4]: begin
+        reg_rdata_next[7:0] = fw_qs;
+      end
+
+      addr_hit[5]: begin
+        reg_rdata_next[7:0] = fh_qs;
+      end
+
+      addr_hit[6]: begin
+        reg_rdata_next[7:0] = batch_qs;
+      end
+
+      addr_hit[7]: begin
+        reg_rdata_next[7:0] = num_ch_qs;
+      end
+
+      addr_hit[8]: begin
+        reg_rdata_next[15:0] = ch_col_qs;
+      end
+
+      addr_hit[9]: begin
+        reg_rdata_next[15:0] = n_patches_w_qs;
+      end
+
+      addr_hit[10]: begin
+        reg_rdata_next[15:0] = n_patches_h_qs;
+      end
+
+      addr_hit[11]: begin
+        reg_rdata_next[7:0] = adpt_pad_right_qs;
+      end
+
+      addr_hit[12]: begin
+        reg_rdata_next[7:0] = adpt_pad_bottom_qs;
+      end
+
+      addr_hit[13]: begin
+        reg_rdata_next[3:0] = log_strides_d1_qs;
+      end
+
+      addr_hit[14]: begin
+        reg_rdata_next[3:0] = log_strides_d2_qs;
+      end
+
+      addr_hit[15]: begin
+        reg_rdata_next[0] = status_qs;
+      end
+
+      addr_hit[16]: begin
+        reg_rdata_next[15:0]  = slot_rx_trigger_slot_qs;
+        reg_rdata_next[31:16] = slot_tx_trigger_slot_qs;
+      end
+
+      addr_hit[17]: begin
+        reg_rdata_next[1:0] = data_type_qs;
+      end
+
+      addr_hit[18]: begin
+        reg_rdata_next[5:0] = pad_top_qs;
+      end
+
+      addr_hit[19]: begin
+        reg_rdata_next[5:0] = pad_bottom_qs;
+      end
+
+      addr_hit[20]: begin
+        reg_rdata_next[5:0] = pad_right_qs;
+      end
+
+      addr_hit[21]: begin
+        reg_rdata_next[5:0] = pad_left_qs;
+      end
+
+      addr_hit[22]: begin
+        reg_rdata_next[0] = interrupt_en_qs;
+      end
+
+      addr_hit[23]: begin
+        reg_rdata_next[0] = spc_ifr_qs;
+      end
+
+      addr_hit[24]: begin
+        reg_rdata_next[31:0] = spc_ch_mask_qs;
+      end
+
+      addr_hit[25]: begin
+        reg_rdata_next[31:0] = spc_ch_offset_qs;
+      end
+
+      default: begin
+        reg_rdata_next = '1;
+      end
+    endcase
+  end
+
+  // Unused signal tieoff
+
+  // wdata / byte enable are not always fully used
+  // add a blanket unused statement to handle lint waivers
+  logic unused_wdata;
+  logic unused_be;
+  assign unused_wdata = ^reg_wdata;
+  assign unused_be = ^reg_be;
+
+  // Assertions for Register Interface
+  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+
+endmodule
+
+module im2col_spc_reg_top_intf #(
+    parameter  int AW = 7,
+    localparam int DW = 32
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    REG_BUS.in regbus_slave,
+    // To HW
+    output im2col_spc_reg_pkg::im2col_spc_reg2hw_t reg2hw,  // Write
+    input im2col_spc_reg_pkg::im2col_spc_hw2reg_t hw2reg,  // Read
+    // Config
+    input devmode_i  // If 1, explicit error return for unmapped register access
+);
+  localparam int unsigned STRB_WIDTH = DW / 8;
+
+  `include "register_interface/typedef.svh"
+  `include "register_interface/assign.svh"
+
+  // Define structs for reg_bus
+  typedef logic [AW-1:0] addr_t;
+  typedef logic [DW-1:0] data_t;
+  typedef logic [STRB_WIDTH-1:0] strb_t;
+  `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)
+
+  reg_bus_req_t s_reg_req;
+  reg_bus_rsp_t s_reg_rsp;
+
+  // Assign SV interface to structs
+  `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
+  `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
+
+
+
+  im2col_spc_reg_top #(
+      .reg_req_t(reg_bus_req_t),
+      .reg_rsp_t(reg_bus_rsp_t),
+      .AW(AW)
+  ) i_regs (
+      .clk_i,
+      .rst_ni,
+      .reg_req_i(s_reg_req),
+      .reg_rsp_o(s_reg_rsp),
+      .reg2hw,  // Write
+      .hw2reg,  // Read
+      .devmode_i
+  );
+
+endmodule
+
+
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_regintfc_controller.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_regintfc_controller.sv
new file mode 100644
index 00000000..6fa9092f
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/im2col_spc_regintfc_controller.sv
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Register interface ontroller to comunicate with the AOPB.
+ */
+
+module im2col_spc_regintfc_controller
+  import reg_pkg::*;
+(
+    input logic clk_i,
+    input logic rst_ni,
+    input logic [31:0] addr_i,
+    input logic [31:0] wdata_i,
+    input logic start_i,
+    input reg_rsp_t aopb_resp_i,
+    output reg_req_t aopb_req_o,
+    output logic done_o
+);
+
+  /* General status signal */
+  enum {
+    IDLE,
+    WAITING_READY,
+    SENDING,
+    DONE
+  }
+      im2col_status_q, im2col_status_d;
+
+  always_comb begin
+    unique case (im2col_status_d)
+      IDLE: begin
+        if (start_i == 1'b1) begin
+          im2col_status_q = SENDING;
+        end else begin
+          im2col_status_q = IDLE;
+        end
+      end
+
+      SENDING: begin
+        im2col_status_q = WAITING_READY;
+      end
+
+      WAITING_READY: begin
+        if (aopb_resp_i.ready == 1'b1) begin
+          im2col_status_q = DONE;
+        end else begin
+          im2col_status_q = WAITING_READY;
+        end
+      end
+
+      DONE: begin
+        im2col_status_q = IDLE;
+      end
+    endcase
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      im2col_status_d <= IDLE;
+    end else begin
+      im2col_status_d <= im2col_status_q;
+    end
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      aopb_req_o.valid <= 1'b0;
+      aopb_req_o.write <= 1'b0;
+      aopb_req_o.wstrb <= 4'b1111;
+      aopb_req_o.addr  <= '0;
+      aopb_req_o.wdata <= '0;
+    end else begin
+      if (im2col_status_d == SENDING) begin
+        aopb_req_o.valid <= 1'b1;
+        aopb_req_o.write <= 1'b1;
+        aopb_req_o.wstrb <= 4'b1111;
+        aopb_req_o.addr  <= addr_i;
+        aopb_req_o.wdata <= wdata_i;
+      end else if (im2col_status_q == DONE) begin
+        aopb_req_o.valid <= 1'b0;
+      end
+    end
+  end
+
+  assign done_o = (im2col_status_d == DONE);
+
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/pipe_reg.sv b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/pipe_reg.sv
new file mode 100644
index 00000000..b819a941
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/hw/ip_examples/im2col_spc/rtl/pipe_reg.sv
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2024 EPFL
+ * Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+ * SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ * Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ * Info: Generic pipe register
+ */
+
+module pipe_reg #(
+    parameter WIDTH = 8
+) (
+    input logic clk_i,
+    input logic rst_ni,
+    input logic [WIDTH-1:0] data_in,
+    output logic [WIDTH-1:0] data_out
+);
+
+  logic [WIDTH-1:0] reg_data;
+
+  always_ff @(posedge clk_i, negedge rst_ni) begin
+    if (!rst_ni) begin
+      reg_data <= '0;
+    end else begin
+      reg_data <= data_in;
+    end
+  end
+
+  assign data_out = reg_data;
+endmodule
diff --git a/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl b/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
index e77bd1b4..2a01983e 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
+++ b/hw/vendor/esl_epfl_x_heep/hw/system/x_heep_system.sv.tpl
@@ -11,7 +11,9 @@ module x_heep_system
     parameter ZFINX = 0,
     parameter EXT_XBAR_NMASTER = 0,
     parameter X_EXT = 0,  // eXtension interface in cv32e40x
+    parameter AO_SPC_NUM = 0,
     //do not touch these parameters
+    parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
     parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
     parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
     parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT
@@ -29,13 +31,16 @@ module x_heep_system
     input  obi_resp_t ext_core_data_resp_i,
     output obi_req_t  ext_debug_master_req_o,
     input  obi_resp_t ext_debug_master_resp_i,
-    output obi_req_t  ext_dma_read_ch0_req_o,
-    input  obi_resp_t ext_dma_read_ch0_resp_i,
-    output obi_req_t  ext_dma_write_ch0_req_o,
-    input  obi_resp_t ext_dma_write_ch0_resp_i,
-    output obi_req_t  ext_dma_addr_ch0_req_o,
-    input  obi_resp_t ext_dma_addr_ch0_resp_i,
-
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_read_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_write_resp_i,
+    output obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_req_o,
+    input  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] ext_dma_addr_resp_i,
+
+    input reg_req_t  [AO_SPC_NUM_RND-1:0] ext_ao_peripheral_req_i,
+    output reg_rsp_t [AO_SPC_NUM_RND-1:0] ext_ao_peripheral_resp_o,
+    
     output reg_req_t ext_peripheral_slave_req_o,
     input  reg_rsp_t ext_peripheral_slave_resp_i,
 
@@ -60,6 +65,9 @@ module x_heep_system
     if_xif.cpu_mem_result xif_mem_result_if,
     if_xif.cpu_result     xif_result_if,
 
+    // External SPC interface
+    output logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_done_o,
+
 % for pad in total_pad_list:
 ${pad.x_heep_system_interface}
 % endfor
@@ -112,6 +120,7 @@ ${pad.internal_signals}
     .ZFINX(ZFINX),
     .EXT_XBAR_NMASTER(EXT_XBAR_NMASTER),
     .X_EXT(X_EXT),
+    .AO_SPC_NUM(AO_SPC_NUM),
     .EXT_HARTS(EXT_HARTS)
   ) core_v_mini_mcu_i (
 
@@ -130,18 +139,20 @@ ${pad.core_v_mini_mcu_bonding}
     .pad_resp_i(pad_resp),
     .ext_xbar_master_req_i,
     .ext_xbar_master_resp_o,
+    .ext_ao_peripheral_slave_req_i(ext_ao_peripheral_req_i),
+    .ext_ao_peripheral_slave_resp_o(ext_ao_peripheral_resp_o),
     .ext_core_instr_req_o,
     .ext_core_instr_resp_i,
     .ext_core_data_req_o,
     .ext_core_data_resp_i,
     .ext_debug_master_req_o,
     .ext_debug_master_resp_i,
-    .ext_dma_read_ch0_req_o,
-    .ext_dma_read_ch0_resp_i,
-    .ext_dma_write_ch0_req_o,
-    .ext_dma_write_ch0_resp_i,
-    .ext_dma_addr_ch0_req_o,
-    .ext_dma_addr_ch0_resp_i,
+    .ext_dma_read_req_o,
+    .ext_dma_read_resp_i,
+    .ext_dma_write_req_o,
+    .ext_dma_write_resp_i,
+    .ext_dma_addr_req_o,
+    .ext_dma_addr_resp_i,
     .ext_dma_stop_i,
     .ext_peripheral_slave_req_o,
     .ext_peripheral_slave_resp_i,
@@ -160,7 +171,8 @@ ${pad.core_v_mini_mcu_bonding}
     .external_subsystem_clkgate_en_no,
     .exit_value_o,
     .ext_dma_slot_tx_i,
-    .ext_dma_slot_rx_i
+    .ext_dma_slot_rx_i,
+    .dma_done_o
   );
 
   pad_ring pad_ring_i (
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
index 2871b8ed..e307c5ae 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/cv32e40px.git
-    rev: 15b9dd6077513342cf44e6853a5fc33098f2e73b
+    rev: 10b08065c50d44b5355c1535cb8f740e68e4f106
   }
 }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
index d0e289ae..4fc67fa6 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/cv32e40px.git",
-    rev: "15b9dd6077513342cf44e6853a5fc33098f2e73b",
+    rev: "10b08065c50d44b5355c1535cb8f740e68e4f106",
   },
 
   exclude_from_upstream: [
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/README.md b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/README.md
index 0b23f841..2272b680 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/README.md
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/README.md
@@ -1,8 +1,8 @@
 [![Build Status](https://travis-ci.com/pulp-platform/riscv.svg?branch=master)](https://travis-ci.com/pulp-platform/riscv)
 
-# OpenHW Group CORE-V CV32E40P RISC-V IP
+# OpenHW Group CORE-V CV32E40PX RISC-V IP
 
-CV32E40P is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements
+CV32E40PX is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements
 the RV32IM\[F|Zfinx\]C instruction set architecture, and the PULP custom extensions for achieving
 higher code density, performance, and energy efficiency \[[1](https://doi.org/10.1109/TVLSI.2017.2654506)\], \[[2](https://doi.org/10.1109/PATMOS.2017.8106976)\].
 It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA.
@@ -14,12 +14,12 @@ when it has been contributed to [OpenHW Group](https://www.openhwgroup.org/).
 
 ## Documentation
 
-The CV32E40P user manual can be found in the _docs_ folder and it is
+The CV32E40PX user manual can be found in the _docs_ folder and it is
 captured in reStructuredText, rendered to html using [Sphinx](https://docs.readthedocs.io/en/stable/intro/getting-started-with-sphinx.html).
 These documents are viewable using readthedocs and can be viewed [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/).
 
 ## Verification
-The verification environment for the CV32E40P is _not_ in this Repository.  There is a small, simple testbench here which is
+The verification environment for the CV32E40PX is _not_ in this Repository.  There is a small, simple testbench here which is
 useful for experimentation only and should not be used to validate any changes to the RTL prior to pushing to the master
 branch of this repo.
 
@@ -31,7 +31,7 @@ The Makefiles supported in the **core-v-verif** project automatically clone the
 ## Changelog
 
 A changelog is generated automatically in the documentation from the individual pull requests.
-In order to enable automatic changelog generation within the CV32E40P documentation, the committer is required to label each pull request
+In order to enable automatic changelog generation within the CV32E40PX documentation, the committer is required to label each pull request
 that touches any file in 'rtl' (or any of its subdirectories) with *Component:RTL* and label each pull request that touches any file in
 'docs' (or any of its subdirectories) with *Component:Doc*. Pull requests that are not labeled or labeled with *ignore-for-release* are
 ignored for the changelog generation.
@@ -40,7 +40,7 @@ Only the person who actually performs the merge can add these labels (you need c
 1 label is applied and therefore pull requests that touches both RTL and documentation files in the same pull request are not allowed.
 
 ## Constraints
-Example synthesis constraints for the CV32E40P are provided.
+Example synthesis constraints for the CV32E40PX are provided.
 
 ## Contributing
 
@@ -71,7 +71,7 @@ Run `./util/format-verible` to format all the files.
 
 ## Issues and Troubleshooting
 
-If you find any problems or issues with CV32E40P or the documentation, please check out the [issue
+If you find any problems or issues with CV32E40PX or the documentation, please check out the [issue
  tracker](https://github.com/openhwgroup/cv32e40p/issues) and create a new issue if your problem is
 not yet tracked.
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
index e9807a38..19e21067 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
@@ -110,6 +110,10 @@ module cv32e40px_controller import cv32e40px_pkg::*;
 
   output logic        apu_stall_o,
 
+  // X-IF signals
+  output logic        x_branch_or_async_taken_o,
+  output logic        x_control_illegal_reset_o,
+
   // jump/branch signals
   input  logic        branch_taken_ex_i,          // branch taken signal from EX ALU
   input  logic [1:0]  ctrl_transfer_insn_in_id_i,               // jump is being calculated in ALU
@@ -240,7 +244,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
   logic debug_req_q;
   logic debug_req_pending;
 
-  // qualify wfi vs nosleep locally 
+  // qualify wfi vs nosleep locally
   logic wfi_active;
 
 
@@ -327,6 +331,9 @@ module cv32e40px_controller import cv32e40px_pkg::*;
     // ensures that the target is kept constant even if pc_id is no more HWLP_END
     hwlp_targ_addr_o        = ((hwlp_start1_leq_pc && hwlp_end1_geq_pc) && !(hwlp_start0_leq_pc && hwlp_end0_geq_pc)) ? hwlp_start_addr_i[1] : hwlp_start_addr_i[0];
 
+    x_branch_or_async_taken_o = 1'b0;
+    x_control_illegal_reset_o = 1'b0;
+
     unique case (ctrl_fsm_cs)
       // We were just reset, wait for fetch_enable
       RESET:
@@ -438,6 +445,8 @@ module cv32e40px_controller import cv32e40px_pkg::*;
             pc_mux_o      = PC_BRANCH;
             pc_set_o      = 1'b1;
 
+            x_branch_or_async_taken_o = 1'b1;
+
             // if we want to debug, flush the pipeline
             // the current_pc_if will take the value of the next instruction to
             // be executed (NPC)
@@ -496,6 +505,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                 halt_id_o         = 1'b1;
                 ctrl_fsm_ns       = DBG_FLUSH;
                 debug_req_entry_n = 1'b1;
+                x_branch_or_async_taken_o = 1'b1;
               end
             else if (irq_req_ctrl_i && ~debug_mode_q)
               begin
@@ -511,6 +521,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                 exc_pc_mux_o      = EXC_PC_IRQ;
                 exc_cause_o       = irq_id_ctrl_i;
                 csr_irq_sec_o     = irq_sec_ctrl_i;
+                x_branch_or_async_taken_o = 1'b1;
 
                 // IRQ interface
                 irq_ack_o         = 1'b1;
@@ -534,6 +545,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                   halt_id_o         = 1'b0;
                   ctrl_fsm_ns       = id_ready_i ? FLUSH_EX : DECODE;
                   illegal_insn_n    = 1'b1;
+                  x_control_illegal_reset_o = 1'b1;
 
                 end else begin
 
@@ -679,6 +691,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                         illegal_insn_i | ecall_insn_i:
                         begin
                             ctrl_fsm_ns = FLUSH_EX;
+                            x_control_illegal_reset_o = illegal_insn_i;
                         end
 
                         (~ebrk_force_debug_mode & ebrk_insn_i):
@@ -728,6 +741,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                 halt_id_o         = 1'b1;
                 ctrl_fsm_ns       = DBG_FLUSH;
                 debug_req_entry_n = 1'b1;
+                x_branch_or_async_taken_o = 1'b1;
              end
             else if (irq_req_ctrl_i && ~debug_mode_q)
               begin
@@ -743,6 +757,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                 exc_pc_mux_o      = EXC_PC_IRQ;
                 exc_cause_o       = irq_id_ctrl_i;
                 csr_irq_sec_o     = irq_sec_ctrl_i;
+                x_branch_or_async_taken_o = 1'b1;
 
                 // IRQ interface
                 irq_ack_o         = 1'b1;
@@ -768,6 +783,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                   halt_id_o         = 1'b1;
                   ctrl_fsm_ns       = FLUSH_EX;
                   illegal_insn_n    = 1'b1;
+                  x_control_illegal_reset_o = 1'b1;
 
                 end else begin
 
@@ -865,6 +881,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
                         illegal_insn_i | ecall_insn_i:
                         begin
                             ctrl_fsm_ns = FLUSH_EX;
+                            x_control_illegal_reset_o = illegal_insn_i;
                         end
 
                         (~ebrk_force_debug_mode & ebrk_insn_i):
@@ -1207,7 +1224,7 @@ module cv32e40px_controller import cv32e40px_pkg::*;
         exc_pc_mux_o      = EXC_PC_DBD;
         csr_save_cause_o  = 1'b1;
         debug_csr_save_o  = 1'b1;
-        if (debug_force_wakeup_q) 
+        if (debug_force_wakeup_q)
             debug_cause_o = DBG_CAUSE_HALTREQ;
         else if (debug_single_step_i)
             debug_cause_o = DBG_CAUSE_STEP; // pri 0
@@ -1479,7 +1496,7 @@ endgenerate
 
   assign debug_wfi_no_sleep_o = debug_mode_q || debug_req_pending || debug_single_step_i || trigger_match_i || COREV_CLUSTER;
 
-  // Gate off wfi 
+  // Gate off wfi
   assign wfi_active = wfi_i & ~debug_wfi_no_sleep_o;
 
   // sticky version of debug_req (must be on clk_ungated_i such that incoming pulse before core is enabled is not missed)
@@ -1600,7 +1617,7 @@ endgenerate
 
   // Ensure DBG_TAKEN_IF can only be enterred if in single step mode or woken
   // up from sleep by debug_req_i
-         
+
   a_single_step_dbg_taken_if : assert property (@(posedge clk)  disable iff (!rst_n)  (ctrl_fsm_ns==DBG_TAKEN_IF) |-> ((~debug_mode_q && debug_single_step_i) || debug_force_wakeup_n));
 
   // Ensure DBG_FLUSH state is only one cycle. This implies that cause is either trigger, debug_req_entry, or ebreak
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
index 9f1f668b..883b5ff1 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
@@ -436,6 +436,8 @@ module cv32e40px_id_stage
   // X-Interface
   logic illegal_insn;
   logic x_illegal_insn;
+  logic x_branch_or_async_taken;
+  logic x_control_illegal_reset;
   logic [4:0] waddr_id;
   logic [4:0] waddr_ex;
   logic [4:0] waddr_wb;
@@ -1124,7 +1126,7 @@ module cv32e40px_id_stage
           .mem_instr_waddr_ex_i(regfile_waddr_ex_o[4:0]),
           .mem_instr_we_ex_i   (regfile_we_ex_o),
           .regs_used_i         (regs_used),
-          .branch_or_jump_i    (pc_set_o),
+          .branch_or_jump_i    (x_branch_or_async_taken),
           .instr_valid_i       (instr_valid_i),
           .x_rs_addr_i         (x_rs_addr),
           .x_ex_fwd_o          (x_ex_fwd),
@@ -1136,14 +1138,15 @@ module cv32e40px_id_stage
           .wb_ready_i      (wb_ready_i),
 
           // additional status signals
-          .x_stall_o           (x_stall),
-          .x_illegal_insn_o    (x_illegal_insn),
-          .x_illegal_insn_dec_i(illegal_insn_dec),
-          .id_ready_i          (id_ready_o),
-          .ex_valid_i          (ex_valid_i),
-          .ex_ready_i          (ex_ready_i),
-          .current_priv_lvl_i  (current_priv_lvl_i),
-          .data_req_dec_i      (data_req_id)
+          .x_stall_o                (x_stall),
+          .x_illegal_insn_o         (x_illegal_insn),
+          .x_illegal_insn_dec_i     (illegal_insn_dec),
+          .x_control_illegal_reset_i(x_control_illegal_reset),
+          .id_ready_i               (id_ready_o),
+          .ex_valid_i               (ex_valid_i),
+          .ex_ready_i               (ex_ready_i),
+          .current_priv_lvl_i       (current_priv_lvl_i),
+          .data_req_dec_i           (data_req_id)
       );
 
 
@@ -1445,6 +1448,8 @@ module cv32e40px_id_stage
       .apu_write_dep_i        (apu_write_dep_i),
 
       .apu_stall_o(apu_stall),
+      .x_branch_or_async_taken_o(x_branch_or_async_taken),
+      .x_control_illegal_reset_o(x_control_illegal_reset),
 
       // jump/branch control
       .branch_taken_ex_i          (branch_taken_ex),
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
index dc890797..f326b3f9 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/esl_epfl_cv32e40px/rtl/cv32e40px_x_disp.sv
@@ -90,6 +90,7 @@ module cv32e40px_x_disp
     output logic x_stall_o,
     output logic x_illegal_insn_o,
     input logic x_illegal_insn_dec_i,
+    input logic x_control_illegal_reset_i,
     input logic id_ready_i,
     input logic ex_valid_i,
     input logic ex_ready_i,
@@ -108,6 +109,7 @@ module cv32e40px_x_disp
   logic x_if_memory_instr;
   logic illegal_forwarding_prevention;
   logic x_issue_illegal;
+  logic x_illegal_insn_q, x_illegal_insn_n;
 
   // issue interface
   assign x_issue_valid_o = x_illegal_insn_dec_i & ~branch_or_jump_i & ~instr_offloaded_q & instr_valid_i & ~illegal_forwarding_prevention;
@@ -182,7 +184,7 @@ module cv32e40px_x_disp
       assign x_wb_fwd_o[3] = (x_rs_addr_i[0] | 5'b00001) == waddr_wb_i & we_wb_i & ex_valid_i & x_issue_resp_dualread_i[0];
       assign x_wb_fwd_o[4] = (x_rs_addr_i[1] | 5'b00001) == waddr_wb_i & we_wb_i & ex_valid_i & x_issue_resp_dualread_i[1];
       assign x_wb_fwd_o[5] = (x_rs_addr_i[2] | 5'b00001) == waddr_wb_i & we_wb_i & ex_valid_i & x_issue_resp_dualread_i[2];
-      assign dep = ~x_illegal_insn_o & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0]))
+      assign dep = ~x_illegal_insn_n & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0]))
                                   |     (regs_used_i[1] & scoreboard_q[x_rs_addr_i[1]] & (x_result_rd_i != x_rs_addr_i[1]))
                                   |     (regs_used_i[2] & scoreboard_q[x_rs_addr_i[2]] & (x_result_rd_i != x_rs_addr_i[2]))
                                   |     (((regs_used_i[0] & x_issue_resp_dualread_i[0]) & scoreboard_q[x_rs_addr_i[0] | 5'b00001] & (x_result_rd_i != (x_rs_addr_i[0] | 5'b00001))) & x_issue_resp_dualread_i[0])
@@ -195,7 +197,7 @@ module cv32e40px_x_disp
       assign x_wb_fwd_o[0] = x_rs_addr_i[0] == waddr_wb_i & we_wb_i & ex_valid_i;
       assign x_wb_fwd_o[1] = x_rs_addr_i[1] == waddr_wb_i & we_wb_i & ex_valid_i;
       assign x_wb_fwd_o[2] = x_rs_addr_i[2] == waddr_wb_i & we_wb_i & ex_valid_i;
-      assign dep = ~x_illegal_insn_o & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0]))
+      assign dep = ~x_illegal_insn_n & ((regs_used_i[0] & scoreboard_q[x_rs_addr_i[0]] & (x_result_rd_i != x_rs_addr_i[0]))
                                   |     (regs_used_i[1] & scoreboard_q[x_rs_addr_i[1]] & (x_result_rd_i != x_rs_addr_i[1]))
                                   |     (regs_used_i[2] & scoreboard_q[x_rs_addr_i[2]] & (x_result_rd_i != x_rs_addr_i[2])));
     end
@@ -247,11 +249,12 @@ module cv32e40px_x_disp
   // illegal instruction assignment
   assign x_issue_illegal = x_illegal_insn_dec_i & ~instr_offloaded_q & instr_valid_i;
   always_comb begin
-    x_illegal_insn_o = 1'b0;
+    x_illegal_insn_n = 1'b0;
     if (x_issue_illegal & x_issue_ready_i & ~x_issue_resp_accept_i) begin
-      x_illegal_insn_o = 1'b1;
+      x_illegal_insn_n = 1'b1;
     end
   end
+  assign x_illegal_insn_o = x_illegal_insn_q;
 
   // scoreboard and status signal register
   always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -260,11 +263,17 @@ module cv32e40px_x_disp
       instr_offloaded_q <= 1'b0;
       id_q              <= '0;
       mem_counter_q     <= '0;
+      x_illegal_insn_q  <= 1'b0;
     end else begin
       scoreboard_q      <= scoreboard_d;
       instr_offloaded_q <= instr_offloaded_d;
       id_q              <= id_d;
       mem_counter_q     <= mem_counter_d;
+      if (x_control_illegal_reset_i) begin
+        x_illegal_insn_q <= 1'b0;
+      end else begin
+        x_illegal_insn_q <= x_illegal_insn_n;
+      end
     end
   end
 
diff --git a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_register_interface.core b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_register_interface.core
index b7883672..383b7eac 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_register_interface.core
+++ b/hw/vendor/esl_epfl_x_heep/hw/vendor/pulp_platform_register_interface.core
@@ -14,6 +14,7 @@ filesets:
     - pulp_platform_register_interface/src/reg_intf.sv
     - pulp_platform_register_interface/src/periph_to_reg.sv
     - pulp_platform_register_interface/src/reg_demux.sv
+    - pulp_platform_register_interface/src/reg_mux.sv
     - pulp_platform_register_interface/src/reg_to_tlul.sv
     file_type: systemVerilogSource
 
diff --git a/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson b/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
index df55d160..316750e1 100644
--- a/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
+++ b/hw/vendor/esl_epfl_x_heep/mcu_cfg.hjson
@@ -42,6 +42,8 @@
             length:  0x00010000,
             ch_length:    0x100,
             num_channels:   0x1,
+            num_master_ports: 0x1,
+            num_channels_per_master_port: 0x1,
             path:    "./hw/ip/dma/data/dma.hjson"
         },
         power_manager: {
diff --git a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
index 0be257d7..d496c274 100644
--- a/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
+++ b/hw/vendor/esl_epfl_x_heep/mcu_cfg_minimal.hjson
@@ -42,6 +42,8 @@
             length:  0x00010000,
             ch_length:    0x100,
             num_channels:   0x1,
+            num_master_ports: 0x1,
+            num_channels_per_master_port: 0x1,
             path:    "./hw/ip/dma/data/dma.hjson"
         },
         power_manager: {
diff --git a/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson b/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson
index 1cfa8c79..b0720c2e 100644
--- a/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson
+++ b/hw/vendor/esl_epfl_x_heep/pad_cfg.hjson
@@ -8,7 +8,7 @@
 // The pads contains the list of all the pads available in the design.
 // Each pad is defined by its name and can have the following attributes:
 //    num: <number> (mandatory) - the number of pads of this type
-//    type: <input|output|inout> (mandatory) - the type of the pad
+//    type: <input|output|inout|supply> (mandatory) - the type of the pad
 //    num_offset: <number> (optional) - the offset to the first pad of this type (default 0)
 //    mapping: <top|right|bottom|left> (optional) - the mapping of the pad in the design. Useful for ASICs (default top)
 //    active: <low|high> (optional) - the active level of the pad (default high)
@@ -16,6 +16,12 @@
 //    mux: <dict> (optional) - the muxing options for the pad
 //    skip_declaration: <True|False> (optional) - skip the declaration of the pad in the top level (default False)
 //    keep_internal: <True|False> (optional) - keep the pad internal to the design (default False)
+//    layout_attributes: (optional) - collection of attributes related to the physical (ASIC) layout of the pads
+//        index: (mandatory) index of the pad on its side of the I/O ring
+//        orient: (optional) <R0|R90|R180|R270|MX|MX90|MY|MY90> - orientation of the pad
+//        cell: (mandatory for type "supply") <valid name of cell in the desired tech. library> - specific cell to use if not a default pad cell (ex. for VDD/VSS pads)
+//        offset: (optional) <float> - offset from edge (in um)
+//        skip: (optional) <float> - distance from neighboring pad (in um)
 // 
 // Add this field at the same level of pads (not inside) if you want to define PADs attributes
 //    attributes: {
diff --git a/hw/vendor/esl_epfl_x_heep/scripts/verification/examples/im2col_spc_verification.py b/hw/vendor/esl_epfl_x_heep/scripts/verification/examples/im2col_spc_verification.py
new file mode 100644
index 00000000..93fe9d6b
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/scripts/verification/examples/im2col_spc_verification.py
@@ -0,0 +1,317 @@
+#
+#     Copyright EPFL contributors.
+#     Licensed under the Apache License, Version 2.0, see LICENSE for details.
+#     SPDX-License-Identifier: Apache-2.0
+#
+#     Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+#                             <tommaso.terzano@gmail.com>
+#
+#     Info: This is a usecase of the VerifHeep tool. It generates a dataset for the im2col function 
+#           and the golden result, then it runs the test on the PYNQ-Z2 board and stores the results 
+#           in a file. The data can be then read and plotted using the plotter.py script.
+#           
+#           In order to be run, these steps has to be followed:
+#           0. Set the X-Heep configuration to have 4 channels,
+#              while there are no limits on the number of master ports
+#           1. Run this command to include Verifheep: 
+#               export PYTHONPATH="$PYTHONPATH:/<X-Heep project directory in your system>/scripts/verification"
+#           2. Perform the synthesis with Vivado and to program the FPGA with the bitstream
+#           3. Connect the board using GDB by running X-Heep script "make openOCD_bscan". Close Vivado to avoid conflicts
+#
+
+import re
+import time
+import verifheep
+from tqdm import tqdm
+import curses
+import torch
+import torch.nn.functional as F
+import numpy as np
+
+# Define the USB port to which the board is connected. Useful because the port may change
+USBport = 2
+
+# Define the parameters for the test
+
+datatype = "uint8_t"
+range_max = 255
+
+num_masters = 4 # Number of DMA CH
+num_slaves = 2 # Number of BUS master ports
+max_masters_per_slave = 2 # Maximum number of DMA CH per BUS master port
+
+batch_max = 4
+batch_min = 1
+
+channels_max = 4
+channels_min = 1
+
+im_h_max = 11
+im_h_min = 10
+
+im_w_max = 11
+im_w_min = 10
+
+ker_h_max = 5
+ker_h_min = 3
+
+ker_w_max = 5
+ker_w_min = 3
+
+pad_top_max = 2
+pad_top_min = 1
+pad_bottom_max = 2
+pad_bottom_min = 1
+pad_left_max = 2
+pad_left_min = 1
+pad_right_max = 2
+pad_right_min = 1
+
+stride_d1_max = 2
+stride_d1_min = 1
+stride_d2_max = 2
+stride_d2_min = 1
+
+# Calculate the total number of iterations
+total_iterations = ((stride_d2_max - stride_d2_min) * (stride_d1_max - stride_d1_min) *
+                    (pad_right_max - pad_right_min) * (pad_left_max - pad_left_min) *
+                    (pad_bottom_max - pad_bottom_min) * (pad_top_max - pad_top_min) *
+                    (ker_w_max - ker_w_min) * (ker_h_max - ker_h_min) *
+                    (im_w_max - im_w_min) * (im_h_max - im_h_min) *
+                    (channels_max - channels_min) * (batch_max - batch_min))
+
+# Define the patterns to be used for modifying the im2col_lib.h file
+spc_mask_pattern = re.compile(r'#define SPC_CH_MASK 0b\d+')
+start_id_pattern = re.compile(r'#define START_ID \d+')
+test_en_pattern = re.compile(r'#define TEST_EN \d+')
+
+# Define the arrays to store the data
+im2col_cpu_array = []
+im2col_dma_2d_C_array = []
+im2col_spc_array = []
+
+# Function to generate the input dataset for the im2col test to be passed to the VerifHeep tool
+def im2col_function(input_array, parameters):
+  
+    # Extract parameters
+    batch_size = parameters['BATCH']
+    channels = parameters['CH']
+    image_height = parameters['IH']
+    image_width = parameters['IW']
+    top_pad = parameters['TOP_PAD']
+    bottom_pad = parameters['BOTTOM_PAD']
+    left_pad = parameters['LEFT_PAD']
+    right_pad = parameters['RIGHT_PAD']
+    stride_d1 = parameters['STRIDE_D1']
+    stride_d2 = parameters['STRIDE_D2']
+    (filter_height, filter_width) = (parameters['FH'], parameters['FW'])
+    kernel_size = (filter_height, filter_width)
+
+    # Convert the input array into a PyTorch tensor with the correct shape
+    input_tensor = torch.tensor(input_array).view(batch_size, channels, image_height, image_width)
+
+    dilation = 1
+    # Ensure kernel_size, stride, padding, and dilation are tuples
+    if isinstance(kernel_size, int):
+        kernel_size = (kernel_size, kernel_size)
+    if isinstance(dilation, int):
+        dilation = (dilation, dilation)
+
+    # Adjust padding format for F.pad (expects pad_left, pad_right, pad_top, pad_bottom)
+    padding_format = (left_pad, right_pad, top_pad, bottom_pad)
+
+    # Apply zero padding
+    padded_input = F.pad(input_tensor, padding_format, "constant", 0)
+
+    # Unfold the padded input tensor
+    unfolded = padded_input.unfold(2, kernel_size[0], stride_d2).unfold(3, kernel_size[1], stride_d1)
+    unfolded = unfolded.permute(0, 2, 3, 1, 4, 5)
+
+    # Reshape to get the 2D tensor where each row is a flattened receptive field
+    channel_dim = padded_input.size(1)
+    unfolded_tensor = unfolded.contiguous().view(-1, channel_dim * kernel_size[0] * kernel_size[1]).t()
+
+    # Convert the PyTorch tensor to a NumPy array and then to a list (simple array)
+    unfolded_array = unfolded_tensor.numpy().flatten().tolist()
+
+    return unfolded_array, ""
+
+
+# Initialize the VerifHeep tool
+im2colVer = verifheep.VerifHeep("pynq-z2", "../../../")
+
+# Connect to the pynq-z2 board
+print("Connecting to the board...")
+serial_status = im2colVer.serialBegin(f"/dev/ttyUSB{USBport}", 9600)
+if not serial_status:
+    print("Error connecting to the board")
+    exit(1)
+else:
+    print("Connected!\n")
+    time.sleep(1)
+
+# Set up the debug interface
+im2colVer.setUpDeb()
+
+def main(stdscr):
+
+  # Initialize the progress bar
+  progress_bar = tqdm(total=total_iterations, desc="Overall Progress", ncols=100, unit=" iter",
+                   bar_format='{desc}: {percentage:.2f}%|{bar}| {n_fmt}/{total_fmt}')
+
+  iteration = 1
+  started = False
+  counter = 10
+
+  # Set CH0 to be the SPC channel
+  mask = "0001"
+  im2colVer.modifyFile("../../../sw/applications/example_im2col/im2col_lib.h", spc_mask_pattern, f'#define SPC_CH_MASK 0b{mask}')
+  
+  # Set the correct output format by setting the TEST_EN define
+  im2colVer.modifyFile("../../../sw/applications/example_im2col/im2col_lib.h", test_en_pattern, f'#define TEST_EN 1')
+                                                  
+  curses.curs_set(0)
+  for j in range(batch_min, batch_max):
+      im2col_cpu = []
+      im2col_dma_2d_C = []
+      im2col_spc = []
+      for k in range(channels_min, channels_max):
+          
+          for l in range(im_h_min, im_h_max):
+
+              for m in range(im_w_min, im_w_max):
+
+                  for n in range(ker_h_min, ker_h_max):
+
+                      for o in range(ker_w_min, ker_w_max):
+                          
+                          for p in range(pad_top_min, pad_top_max):
+
+                              for q in range(pad_bottom_min, pad_bottom_max):
+
+                                  for r in range(pad_left_min, pad_left_max):
+
+                                      for s in range(pad_right_min, pad_right_max):
+
+                                          for t in range(stride_d1_min, stride_d1_max):
+
+                                              for u in range(stride_d2_min, stride_d2_max):
+                                                  
+                                                  # Start the chrono
+                                                  if started and counter == 0:
+                                                    im2colVer.stopDeb()
+                                                    im2colVer.setUpDeb()
+                                                    counter = 10
+                                                  elif not started:
+                                                    im2colVer.setUpDeb()
+                                                    started = True
+                                                    counter -= 1
+                                                  else:                                                      
+                                                    counter -= 1
+                                                  
+                                                  im2colVer.chronoStart()
+
+                                                  # Generate the input dataset and the golden result
+                                                  n_patches_h = (l + p + q - n) // u + 1
+                                                  n_patches_w = (m + s + r - o) // t + 1
+                                                  OH = o * n * k * j # Number of rows in a column -> size of a column
+                                                  OW = n_patches_h * n_patches_w # Numver of columns in a row -> size of a row
+                                                  input_size = k * l * m * j
+                                                  golden_size = OH * OW
+
+                                                  parameters = {
+                                                      'IH': l,
+                                                      'IW': m,
+                                                      'CH': k,
+                                                      'BATCH': j,
+                                                      'FH': n,
+                                                      'FW': o,
+                                                      'TOP_PAD': p,
+                                                      'BOTTOM_PAD': q,
+                                                      'LEFT_PAD': r,
+                                                      'RIGHT_PAD': s,
+                                                      'STRIDE_D1': t,
+                                                      'STRIDE_D2': u
+                                                  }
+                                                  
+                                                  im2colVer.genInputDataset(input_size, row_size=m, range_max=range_max, dataset_dir_c="../../../sw/applications/example_im2col/im2col_input.c", 
+                                                                            dataset_dir="../../../sw/applications/example_im2col/im2col_input.h", parameters=parameters, dataset_name="input_image_nchw",
+                                                                            datatype=datatype)
+                                                  
+                                                  im2colVer.genGoldenResult(im2col_function, golden_size, parameters, row_size=OW, golden_dir="../../../sw/applications/example_im2col/im2col_golden.h", 
+                                                                            golden_dir_c="../../../sw/applications/example_im2col/im2col_golden.c", input_dataset_dir="../../../sw/applications/example_im2col/im2col_input.c",
+                                                                            golden_name="golden_im2col_nchw",
+                                                                            output_datatype=datatype)
+                                                                                                  
+                                                  im2colVer.modifyFile("../../../sw/applications/example_im2col/im2col_lib.h", start_id_pattern, f'#define START_ID 0')
+                                                  
+                                                  # Launch the test
+                                                  im2colVer.launchTest("example_im2col", input_size=j*k*l*m)
+
+                                                  # Format the parameters of the current run and store them for plots
+                                                  for test in im2colVer.results:
+                                                      string = f'CH_SPC: 1, B: {j}, C: {k}, H: {l}, W: {m}, FH: {n}, FW: {o}, PT: {p}, PB: {q}, PL: {r}, PR: {s}, S1: {t}, S2: {u}, cycles: {test["Cycles"]}'
+                                                      
+                                                      if int(test["ID"]) == 0:
+                                                          im2col_cpu.append(string)
+                                                      elif int(test["ID"]) == 1:
+                                                          im2col_dma_2d_C.append(string)
+                                                      elif int(test["ID"]) == 2:
+                                                          im2col_spc.append(string)
+                                                  
+                                                  # Stop the chrono and calculate the remaining time of the verification
+                                                  im2colVer.clearResults()
+                                                  im2colVer.chronoStop()
+                                                  time_rem = im2colVer.chronoExecutionEst(((stride_d2_max - stride_d2_min) * (stride_d1_max - stride_d1_min) * (pad_right_max - pad_right_min) * (pad_left_max - pad_left_min) * (pad_bottom_max - pad_bottom_min) * (pad_top_max - pad_top_min) * (ker_w_max - ker_w_min) * (ker_h_max - ker_h_min) * (im_w_max - im_w_min) * (im_h_max - im_h_min) * (channels_max - channels_min) * (batch_max - batch_min)))
+                                                  
+                                                  # Update the progress bar
+                                                  message = (
+                                                      f"Batch size:    {j:>5}\n"
+                                                      f"Input channels:{k:>5}\n"
+                                                      f"Image height:  {l:>5}\n"
+                                                      f"Image width:   {m:>5}\n"
+                                                      f"Kernel height: {n:>5}\n"
+                                                      f"Kernel width:  {o:>5}\n"
+                                                      f"Pad top:       {p:>5}\n"
+                                                      f"Pad bottom:    {q:>5}\n"
+                                                      f"Pad left:      {r:>5}\n"
+                                                      f"Pad right:     {s:>5}\n"
+                                                      f"Stride d1:     {t:>5}\n"
+                                                      f"Stride d2:     {u:>5}\n"
+                                                      f"Remaining time:{time_rem['hours']:>2}h:{time_rem['minutes']:>2}m:{time_rem['seconds']:.2f}s\n"
+                                                  )
+
+                                                  iteration += 1
+                                                  progress_bar.update(1)
+                                                  
+                                                  stdscr.addstr(1, 0, message)
+                                                  stdscr.refresh()
+
+      im2col_cpu_array.append(im2col_cpu)
+      im2col_dma_2d_C_array.append(im2col_dma_2d_C)
+      im2col_spc_array.append(im2col_spc)
+
+  # Stop the debug interface and close the progress bar
+  im2colVer.stopDeb()
+  progress_bar.close()
+
+  # Write the data to a file
+  with open('im2col_data.txt', 'w') as file:
+      file.write("im2col_cpu:\n")
+      for value in im2col_cpu_array:
+          file.write(f"{value}\n")
+      file.write("\n")
+      
+      file.write("im2col_dma_2d_C:\n")
+      for value in im2col_dma_2d_C_array:
+          file.write(f"{value}\n")
+      file.write("\n")
+      
+      file.write("im2col_spc:\n")
+      for value in im2col_spc_array:
+          file.write(f"{value}\n")
+      file.write("\n")
+
+  print("Data acquired!\n")
+
+curses.wrapper(main)
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/scripts/verification/examples/plotter.py b/hw/vendor/esl_epfl_x_heep/scripts/verification/examples/plotter.py
new file mode 100644
index 00000000..3a012aa6
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/scripts/verification/examples/plotter.py
@@ -0,0 +1,123 @@
+#
+#     Copyright EPFL contributors.
+#     Licensed under the Apache License, Version 2.0, see LICENSE for details.
+#     SPDX-License-Identifier: Apache-2.0
+#
+#     Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+#                             <tommaso.terzano@gmail.com>
+#
+#     Info: Plotter script for im2col spc verification data.
+#
+
+import matplotlib.pyplot as plt
+import pandas as pd
+import ast
+import numpy as np
+
+# Function to parse data from string to dictionary
+def parse_data(data):
+    results = []
+    for item in data:
+        # Split each item by ', ' to get key-value pairs
+        pairs = item.split(', ')
+        # Create a dictionary from the pairs
+        result_dict = {}
+        for pair in pairs:
+            key, value = pair.split(': ')
+            # Convert value to integer
+            result_dict[key] = int(value)
+        results.append(result_dict)
+    return results
+
+# Function to add loop_size field
+def add_loop_size(data):
+    for entry in data:
+        # Calculate the number of patches, i.e. the number the filter can fit along one dimension during convolution
+        n_patches_h = int((entry['H'] - entry['FH']  + entry['PT'] + entry['PB']) / entry['S2']) + 1
+        n_patches_w = int((entry['W'] - entry['FW']  + entry['PR'] + entry['PL']) / entry['S1']) + 1
+        # Calculate the dimensions of the output matrix
+        OH = entry['FW'] * entry['FH'] * entry['C'] * entry['B'] # Number of rows in a column -> size of a column
+        OW = n_patches_h * n_patches_w # Number of columns in a row -> size of a row
+        entry['loop_size'] = OH*OW
+    return data
+
+# Read and parse data from file
+def read_data(file_path):
+    with open(file_path, 'r') as file:
+        lines = file.readlines()
+    
+    im2col_cpu = []
+    im2col_dma_2d_C = []
+    im2col_spc = []
+    
+    current_section = None
+    for line in lines:
+        line = line.strip()
+        if line.startswith("im2col_cpu:"):
+            current_section = im2col_cpu
+        elif line.startswith("im2col_dma_2d_C:"):
+            current_section = im2col_dma_2d_C
+        elif line.startswith("im2col_spc:"):
+            current_section = im2col_spc
+        elif line:
+            if current_section is not None:
+                current_section.append(line.strip("[]'"))
+
+    return im2col_cpu, im2col_dma_2d_C, im2col_spc
+
+# Path to the file containing the data
+file_path = 'im2col_data.txt'
+
+# Read data from the file
+im2col_cpu_array, im2col_dma_2d_C_array, im2col_spc_array = read_data(file_path)
+
+# Elaborate the data
+parsed_1ch_CPU = parse_data(ast.literal_eval("'"+im2col_cpu_array[0]+"'"))
+parsed_1ch_DMA = parse_data(ast.literal_eval("'"+im2col_dma_2d_C_array[0]+"'"))
+parsed_1ch_spc = parse_data(ast.literal_eval("'"+im2col_spc_array[0]+"'"))
+
+add_loop_size(parsed_1ch_CPU)
+add_loop_size(parsed_1ch_DMA)
+add_loop_size(parsed_1ch_spc)
+
+df_1ch_CPU = pd.DataFrame(parsed_1ch_CPU)
+df_1ch_DMA = pd.DataFrame(parsed_1ch_DMA)
+df_1ch_spc = pd.DataFrame(parsed_1ch_spc)
+
+# Plot the data
+plt.figure(0, figsize=(12, 8))
+
+# Scatter plots
+plt.scatter(df_1ch_CPU['loop_size'], df_1ch_CPU['cycles'], color='blue', label='1ch CPU', alpha=1)
+plt.scatter(df_1ch_DMA['loop_size'], df_1ch_DMA['cycles'], color='red', label='1ch DMA', alpha=1)
+plt.scatter(df_1ch_spc['loop_size'], df_1ch_spc['cycles'], color='green', label='1ch SPC', alpha=1)
+
+# Trendline plots
+p_cpu = np.polyfit(df_1ch_CPU['loop_size'],df_1ch_CPU['cycles'],  1)
+trendline_cpu = np.polyval(p_cpu, df_1ch_CPU['loop_size'])
+
+p_dma = np.polyfit(df_1ch_DMA['loop_size'], df_1ch_DMA['cycles'], 1)
+trendline_dma = np.polyval(p_dma, df_1ch_DMA['loop_size'])
+
+p_spc = np.polyfit(df_1ch_spc['loop_size'], df_1ch_spc['cycles'], 1)
+trendline_spc = np.polyval(p_spc, df_1ch_spc['loop_size'])
+
+plt.plot(df_1ch_CPU['loop_size'], trendline_cpu, color='blue', linestyle='-', alpha=0.6)
+plt.plot(df_1ch_DMA['loop_size'], trendline_dma, color='red', linestyle='-', alpha=0.6)
+plt.plot(df_1ch_spc['loop_size'], trendline_spc, color='green', linestyle='-', alpha=0.6)
+
+
+# Title and labels
+plt.title('Loop Size vs Cycles')
+plt.xlabel('Loop Size')
+plt.ylabel('Cycles')
+plt.grid(True)
+
+# Legend
+plt.legend()
+
+# Save plot
+plt.savefig('plot.png')  
+
+# Show plot
+plt.show()
diff --git a/hw/vendor/esl_epfl_x_heep/scripts/verification/verifheep.py b/hw/vendor/esl_epfl_x_heep/scripts/verification/verifheep.py
new file mode 100644
index 00000000..8cf07ebd
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/scripts/verification/verifheep.py
@@ -0,0 +1,498 @@
+#
+#     Copyright EPFL contributors.
+#     Licensed under the Apache License, Version 2.0, see LICENSE for details.
+#     SPDX-License-Identifier: Apache-2.0
+#
+#     Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+#                             <tommaso.terzano@gmail.com>
+#
+#     Info: This library can be used to implement a software-based verification of X-Heep on a variety of targets,
+#           including Verilator, QuestaSim and FPGA (pynq-z2), using gdb and OpenOCD. 
+#           Some useful information:
+#
+#           1) In order to enable the elaboration of the outcome of a test, the SW testbench should produce data using
+#              the following format:
+#              - 1st line to n line: "<ID>:<cycles>:<outcome>"
+#              - last line: "&"
+#              Of course it is not mandatory to count the cycles, or to provide an outcome, or even to use different IDs.
+#              The crucial thing is to use the format, even if only one of its fields is relevant for your usecase.
+#
+#           2) The library provides methods to generate a random input dataset + a golden output dataset
+#              using a provided function. 
+#              This is particularly useful for data-processing applications and accelerators, but could be used to test other
+#              units with some workarounds.
+#              If the function returns a dictionary of parameters that might be useful for the application (if not, return None), 
+#              they will be written in the same header file as the golden output.
+#              The application has to be written in order to use an external output, defined in a header file, 
+#              and to compare it against a golden output, also defined in a header. 
+#              Both the name and directories of these datasets can be provided as arguments.
+#              It is also possible to generate a golden result starting from a custom input dataset, provided that it was produced
+#              using the same structure.#              
+#
+#           3) The library provides methods to estimate the remaining time of the execution of a loop, based on the average duration
+#              of the iterations that have already been executed. 
+#              This is useful to estimate the remaining time of the execution of a multi-iteration test.
+#           
+
+import subprocess
+import re
+import time
+import serial
+import pexpect
+import threading
+import queue
+import random
+import os
+
+# Set this to True to enable debugging prints
+DEBUG_MODE = False
+
+def PRINT_DEB(*args, **kwargs):
+    if DEBUG_MODE:
+        print(*args, **kwargs)
+
+class VerifHeep:
+    def __init__(self, target, xheep_dir, opt_en=False):
+        self.target = target
+        if target not in ['verilator', 'questasim', 'pynq-z2']:
+            raise Exception(f'Target {target} not supported. Choose one among:\n- verilator\n- questasim (with optional optimization)\n- pynq-z2\n')
+        if (target != 'pynq-z2' and opt_en) or (target != 'verilator' and opt_en):
+            raise Exception(f'Target {target} not supported with {opt_en}. Choose one among:\n- verilator\n- questasim (with optional optimization)\n- pynq-z2\n')
+
+        self.opt_en = opt_en
+        self.xheep_dir = xheep_dir
+        self.results = []
+        self.it_times = []
+
+    def resetAll(self):
+        self.results = []
+        self.it_times = []
+        if self.ser.is_open:
+          self.ser.close()
+        self.ser = None
+        self.serial_queue = None
+        self.serial_thread = None
+        self.gdb = None
+        self.xheep_dir = None
+
+    def clearResults(self):
+        self.results = []
+
+    # Synthesis & Simulation methods
+    
+    def compileModel(self, mem_banks=6, cpu="cv32e40px", bus="1toN"):
+        mcu_gen_cmd = f"cd {self.xheep_dir} ; make mcu-gen MEMORY_BANKS={mem_banks} CPU={cpu} BUS={bus}"
+        subprocess.run(mcu_gen_cmd, shell=True, capture_output=True, text=True)
+        if ("ERROR" in mcu_gen_cmd.stderr) or ("error" in mcu_gen_cmd.stderr):
+            print(mcu_gen_cmd.stderr)
+            exit(1)
+    
+    def buildModel(self):
+        if self.target == 'verilator':
+            cmd = f'cd {self.xheep_dir} ; make verilator-sim FUSESOC_PARAM=--JTAG_DPI=1'
+        elif self.target == 'questasim' and self.opt_en:
+            cmd = f'cd {self.xheep_dir} ; make questasim-sim-opt FUSESOC_PARAM=--JTAG_DPI=1'
+        elif self.target == 'questasim' and not self.opt_en:
+            cmd = f'cd {self.xheep_dir} ; make questasim-sim'
+        elif self.target == 'pynq-z2':
+            cmd = f"cd {self.xheep_dir} ; make vivado-fpga FPGA_BOARD={self.target} FUSESOC_FLAGS=--flag=use_bscane_xilinx"
+        result_synth = subprocess.run(cmd, shell=True, capture_output=True, text=True, executable="/bin/bash")
+        if ("ERROR" in result_synth.stderr) or ("error" in result_synth.stderr):
+            print(result_synth.stderr)
+            exit(1)
+
+    # FPGA programming & debugging methods
+    
+    def serialBegin(self, port, baudrate):
+        try:
+            self.ser = serial.Serial(port, baudrate, timeout=1)
+            self.serial_queue = queue.Queue()
+            
+            if self.ser.is_open:
+                print("Connection successful")
+                return True
+            else:
+                print("Failed to open the connection")
+                return False
+        except serial.SerialException as e:
+            print(f"Serial exception: {e}")
+            return False
+        except Exception as e:
+            print(f"An error occurred: {e}")
+            return False
+
+    def setUpDeb(self):
+        gdb_cmd = f"""
+        cd {self.xheep_dir}
+        $RISCV/bin/riscv32-unknown-elf-gdb ./sw/build/main.elf
+        """
+        self.gdb = pexpect.spawn(f"/bin/bash -c '{gdb_cmd}'")
+        self.gdb.expect('(gdb)')
+        self.gdb.sendline('set remotetimeout 2000')
+        self.gdb.expect('(gdb)')
+        self.gdb.sendline('target remote localhost:3333')
+        self.gdb.expect('(gdb)')
+
+        if self.gdb.isalive():
+            PRINT_DEB("GDB process is still running.")
+        else:
+            PRINT_DEB("GDB process has terminated.")
+            if self.gdb.exitstatus is not None:
+                print(f"GDB exit status: {self.gdb.exitstatus}")
+            if self.gdb.signalstatus is not None:
+                print(f"GDB terminated by signal: {self.gdb.signalstatus}")
+            exit(1)
+            
+    def stopDeb(self):
+        self.gdb.sendcontrol('c')
+        self.gdb.terminate()
+
+    def launchTest(self, example_name, input_size=0, pattern=r'(\d+):(\d+):(\d+)', en_timeout_term=False):
+        PRINT_DEB(f"Running test {example_name} with input size {input_size}...")
+
+        # Check that the serial connection is still open
+        if not self.ser.is_open:
+            print("Error: Serial port is not open!")
+            exit(1) 
+
+        # Set up the serial communication thread and attach it the serial queue
+        self.serial_thread = threading.Thread(target=SerialReceiver, args=(self.ser, self.serial_queue,))
+
+        # Start the serial thread
+        self.serial_thread.start()
+
+        # Compile the application
+        if self.target == 'verilator' or self.target == 'questasim':
+          app_compile_run_com = f"cd {self.xheep_dir} ; make app PROJECT={example_name}"
+        else:
+          app_compile_run_com = f"cd {self.xheep_dir} ; make app PROJECT={example_name} TARGET={self.target}"
+
+        result_compilation = subprocess.run(app_compile_run_com, shell=True, capture_output=True, text=True)
+
+        if ("Error" in result_compilation.stderr) or ("error" in result_compilation.stderr):
+            print(result_compilation.stderr)
+            return
+        else:
+            PRINT_DEB("Compilation successful!")
+        
+        # Run the testbench with gdb
+        self.gdb.sendline('load')
+        self.gdb.expect('(gdb)')
+
+        try:
+          output = self.gdb.read_nonblocking(size=100, timeout=1)
+          PRINT_DEB("Current gdb output:", output)
+        except pexpect.TIMEOUT:
+          PRINT_DEB("No new output from GDB.")
+
+        # Set a breakpoint at the exit and wait for it
+        self.gdb.sendline('b _exit')
+        self.gdb.expect('(gdb)')
+        self.gdb.sendline('continue')
+        try:
+          self.gdb.expect('Breakpoint', timeout=600)
+        except pexpect.TIMEOUT:
+          print("Timeout! Program didn't answer in time, exiting...")
+          self.gdb.terminate()
+          if en_timeout_term:
+            exit(1)
+          return
+        
+        # Wait for serial to finish
+        self.serial_thread.join()
+
+        # Recover the lines
+        lines = []
+        while not self.serial_queue.empty():
+            lines.append(self.serial_queue.get())
+
+        # Analyse the results
+        pattern = re.compile(pattern)  
+        test_id = None
+        for line in lines:
+            match = pattern.search(line)
+            if match:
+                test_id = match.group(1)
+                cycle_count = match.group(2)
+                outcome = match.group(3)
+                self.results.append({ "ID" : test_id, "Cycles": cycle_count, "Outcome": outcome, "Input size": input_size })
+
+    def dumpResults(self, filename="results.txt"):
+        with open(filename, 'w') as f:
+            for result in self.results:
+                f.write(result + '\n')
+
+    # Performance estimation methods
+    
+    def chronoStart(self):
+        self.start_time = time.time()
+    
+    def chronoStop(self):
+        self.end_time = time.time()
+        self.it_times.append(self.end_time - self.start_time)
+        return self.end_time - self.start_time
+    
+    def chronoExecutionEst(self, loop_size):
+        avg_duration = sum(self.it_times) / len(self.it_times)
+        remaining_it = loop_size - len(self.it_times)
+        remaining_time_raw = remaining_it * avg_duration
+        remaining_time = {}
+        remaining_time["hours"], remainder = divmod(remaining_time_raw, 3600)
+        remaining_time["minutes"], remaining_time["seconds"] = divmod(remainder, 60)
+        return remaining_time
+    
+    # Data generation methods
+
+    def genInputDataset(self, dataset_size, parameters="", row_size=0, range_min=0, range_max=1, dataset_dir="input_dataset.h", dataset_dir_c="", dataset_name="input_dataset", datatype="uint32_t"):
+        
+        if dataset_dir_c == "":
+          with open(dataset_dir, 'w') as f:
+            # Add license
+            f.write(f"#ifndef {dataset_name.upper()}_H\n")
+            f.write(f"#define {dataset_name.upper()}_H\n\n")
+            license = "/*\n\tCopyright EPFL contributors.\n\tLicensed under the Apache License, Version 2.0, see LICENSE for details.\n\tSPDX-License-Identifier: Apache-2.0\n*/\n\n"
+            f.write(license)
+            f.write(f"#include <stdint.h>\n\n")
+
+            # Write the parameters, if there are any
+            if parameters:
+                for key, value in parameters.items():
+                    f.write(f"#define {key} {value}\n")
+
+            # Vector declaration
+            f.write(f"const {datatype} {dataset_name}[{dataset_size}] = " + "{\n")
+            
+            # Generate the random vector
+            for i in range(dataset_size):
+                if 'float' in datatype:
+                    value = random.uniform(range_min, range_max)  # float
+                elif 'uint' in datatype:
+                    if ('8' in datatype or '16' in datatype or '32' in datatype) and range_min >= 0 and range_max > 0:
+                        value = random.randint(range_min, range_max)
+                    else:
+                        print("Error: invalid datatype. Choose one among:\n- float\n- u/int8_t\n- u/int16_t\n- u/int32_t\n")
+                        exit(1)
+                elif 'int' in datatype:
+                    if ('8' in datatype or '16' in datatype or '32' in datatype):
+                        value = random.randint(range_min, range_max)
+                    else:
+                        print("Error: invalid datatype. Choose one among:\n- float\n- u/int8_t\n- u/int16_t\n- u/int32_t\n")
+                        exit(1)
+                else:
+                  print("Error: invalid datatype. Choose one among:\n- float\n- u/int8_t\n- u/int16_t\n- u/int32_t\n")
+                  exit(1)
+
+                if i < dataset_size - 1:
+                    f.write(f" {value},")
+                else:
+                    f.write(f" {value}")
+              
+                if row_size > 0 and (i + 1) % row_size == 0:
+                  f.write("\n")
+            
+            # Close the file
+            f.write("};\n\n")
+            f.write(f"#endif // {dataset_name.upper()}_H\n")
+        else:
+          with open(dataset_dir_c, 'w') as f:
+            # Add license
+            license = "/*\n\tCopyright EPFL contributors.\n\tLicensed under the Apache License, Version 2.0, see LICENSE for details.\n\tSPDX-License-Identifier: Apache-2.0\n*/\n\n"
+            f.write(license)
+            f.write(f'#include "{os.path.basename(dataset_dir)}"\n\n')
+            
+            # Vector declaration
+            f.write(f"const {datatype} {dataset_name}[{dataset_size}] = " + "{\n")
+            
+            # Generate the random vector
+            for i in range(dataset_size):
+                if 'float' in datatype:
+                    value = random.uniform(range_min, range_max)  # float
+                elif 'uint' in datatype:
+                    if ('8' in datatype or '16' in datatype or '32' in datatype) and range_min >= 0 and range_max > 0:
+                        value = random.randint(range_min, range_max)
+                    else:
+                        print("Error: invalid datatype. Choose one among:\n- float\n- u/int8_t\n- u/int16_t\n- u/int32_t\n")
+                        exit(1)
+                elif 'int' in datatype:
+                    if ('8' in datatype or '16' in datatype or '32' in datatype):
+                        value = random.randint(range_min, range_max)
+                    else:
+                        print("Error: invalid datatype. Choose one among:\n- float\n- u/int8_t\n- u/int16_t\n- u/int32_t\n")
+                        exit(1)
+                else:
+                  print("Error: invalid datatype. Choose one among:\n- float\n- u/int8_t\n- u/int16_t\n- u/int32_t\n")
+                  exit(1)
+
+                if i < dataset_size - 1:
+                    f.write(f" {value},")
+                else:
+                    f.write(f" {value}")
+              
+                if row_size > 0 and (i + 1) % row_size == 0:
+                  f.write("\n")
+              
+            # Close the file
+            f.write("};\n\n")
+          
+          with open(dataset_dir, 'w') as f:
+            # Add license
+            f.write(f"#ifndef {dataset_name.upper()}_H\n")
+            f.write(f"#define {dataset_name.upper()}_H\n\n")
+            license = "/*\n\tCopyright EPFL contributors.\n\tLicensed under the Apache License, Version 2.0, see LICENSE for details.\n\tSPDX-License-Identifier: Apache-2.0\n*/\n\n"
+            f.write(license)
+            f.write(f"#include <stdint.h>\n\n")
+
+            # Write the parameters, if there are any
+            if parameters:
+                for key, value in parameters.items():
+                    f.write(f"#define {key} {value}\n")
+            
+            f.write("\n")
+
+            # Vector declaration
+            f.write(f"extern const {datatype} {dataset_name}[{dataset_size}];\n\n")
+            
+            # Close the file
+            f.write(f"#endif // {dataset_name.upper()}_H\n")
+
+    def genGoldenResult(self, function, golden_size, parameters, row_size=0, output_datatype="uint32_t",  input_dataset_dir="input_dataset.h", golden_dir_c="", golden_dir="golden_output.h", golden_name = "golden_output"):
+        
+        # Recover the input dataset
+        with open(input_dataset_dir, 'r') as f:
+            content = f.read()
+
+        # Use regular expressions to find the array data
+        pattern = re.compile(r"{(.*?)}", re.DOTALL)
+        match = pattern.search(content)
+
+        if not match:
+            raise ValueError("No array data found in the file.")
+
+        array_data = match.group(1)
+        # Remove extra whitespace and split the string into individual values
+        array_data = array_data.replace('\n', '').replace(' ', '')
+        values = array_data.split(',')
+
+        # Convert values to the appropriate type
+        if "float" in content:
+            values = [float(value) for value in values]
+        elif "uint8_t" in content or "uint16_t" in content or "uint32_t" in content:
+            values = [int(value) for value in values]
+        elif "int8_t" in content or "int16_t" in content or "int32_t" in content:
+            values = [int(value) for value in values]
+
+        # Generate the golden result
+        (golden_values, output_parameters) = function(values, parameters)
+
+        if golden_dir_c == "":
+          with open(golden_dir, 'w') as f:
+            # Write the golden result to a file
+            f.write(f"#ifndef {golden_name.upper()}_H\n")
+            f.write(f"#define {golden_name.upper()}_H\n\n")
+            license = "/*\n\tCopyright EPFL contributors.\n\tLicensed under the Apache License, Version 2.0, see LICENSE for details.\n\tSPDX-License-Identifier: Apache-2.0\n*/\n\n"
+            f.write(license)
+            f.write(f"#include <stdint.h>\n\n")
+
+            # Write the parameters that could have been returned from the function
+            if output_parameters:
+              for key, value in output_parameters.items():
+                  f.write(f"#define {key} {value}\n")
+            
+            f.write("\n")
+
+            # Vector declaration
+            f.write(f"const {output_datatype} {golden_name}[{golden_size}] = " + "{\n")
+
+            for i in range(golden_size):
+              if i < golden_size - 1:
+                f.write(f" {golden_values[i]},")
+              else:
+                f.write(f" {golden_values[i]}")
+              
+              if row_size > 0 and (i + 1) % row_size == 0:
+                f.write("\n")
+
+            # Close the file
+            f.write("};\n\n")
+            f.write(f"#endif // {golden_name.upper()}_H\n")
+        else:
+          with open(golden_dir_c, 'w') as f:
+            # Write the golden result to a file
+            license = "/*\n\tCopyright EPFL contributors.\n\tLicensed under the Apache License, Version 2.0, see LICENSE for details.\n\tSPDX-License-Identifier: Apache-2.0\n*/\n\n"
+            f.write(license)
+            f.write(f'#include "{os.path.basename(golden_dir)}"\n\n')
+            
+            # Vector declaration
+            f.write(f"const {output_datatype} {golden_name}[{golden_size}] = " + "{\n")
+
+            for i in range(golden_size):
+              if i < golden_size - 1:
+                f.write(f" {golden_values[i]},")
+              else:
+                f.write(f" {golden_values[i]}")
+                
+              if row_size > 0 and (i + 1) % row_size == 0:
+                f.write("\n")
+
+            # Close the file
+            f.write("};\n\n")
+
+          with open(golden_dir, 'w') as f:
+            # Write the golden result to a file
+            f.write(f"#ifndef {golden_name.upper()}_H\n")
+            f.write(f"#define {golden_name.upper()}_H\n\n")
+            license = "/*\n\tCopyright EPFL contributors.\n\tLicensed under the Apache License, Version 2.0, see LICENSE for details.\n\tSPDX-License-Identifier: Apache-2.0\n*/\n\n"
+            f.write(license)
+            f.write(f"#include <stdint.h>\n\n")
+
+            # Write the parameters that could have been returned from the function
+            if output_parameters:
+              for key, value in output_parameters.items():
+                  f.write(f"#define {key} {value}\n")
+
+            # Vector declaration
+            f.write(f"extern const {output_datatype} {golden_name}[{golden_size}];\n\n")
+
+            # Close the file
+            f.write(f"#endif // {golden_name.upper()}_H\n")
+
+    def modifyFile(self, file_dir, pattern, replacement):
+        
+        with open(file_dir, 'r') as f:
+          content = f.read()
+
+        # Replace the pattern with the replacement
+        new_content = re.sub(pattern, replacement, content)
+
+        with open(file_dir, 'w') as f:
+          f.write(new_content)
+
+# Serial communication thread
+
+def SerialReceiver(ser, serial_queue, endword="&"):
+    try:
+        if not ser.is_open:
+            raise serial.SerialException("Serial port not open")
+        
+        received = False
+        while not received:
+            # Read the data from the serial port
+            line = ser.readline().decode('utf-8').rstrip()
+            serial_queue.put(line)
+            PRINT_DEB(f">: {line}")
+            if line:
+                if endword in line:
+                    received = True
+                    PRINT_DEB(f"Received {endword}: end of serial transmission thread")
+                    return
+                elif "ERROR" in line:
+                    print("FAILED VERIFICATION!")
+                    exit(1)
+    except serial.SerialException as e:
+        print(f"Serial exception: {e}")
+    except Exception as e:
+        print(f"An error occurred: {e}")
+    except KeyboardInterrupt:
+        print("Keyboard interruption")
+    finally:
+        pass
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py
index 5a4a6cd2..4486daad 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/gen_stimuly.py
@@ -38,9 +38,9 @@ def write_arr_flash_only(f, name, arr, ctype, size):
 f.write('#ifndef MATRICES_H_\n')
 f.write('#define MATRICES_H_\n')
 f.write('// This file is automatically generated\n')
+f.write('#ifdef FLASH_LOAD\n')
 
-
-SIZE  = 64
+SIZE  = 32
 RANGE = 10
 
 m_a   = []
@@ -59,6 +59,7 @@ def write_arr_flash_only(f, name, arr, ctype, size):
 write_arr(f, 'B',   B, 'int32_t', SIZE)
 write_arr(f, 'C',   C, 'int32_t', SIZE)
 
+f.write('#endif\n')
 f.write('#define MATRIX_SIZE %d\n' % SIZE)
 
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c
index 01f7dab7..8785dcef 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/main.c
@@ -43,6 +43,10 @@ int32_t buffer_data[MATRIX_SIZE*TILING_ROWS] = {0};
 int32_t output_matrix[MATRIX_SIZE*MATRIX_SIZE] = {0};
 
 int main(int argc, char *argv[]) {
+#ifndef FLASH_LOAD
+    PRINTF("This application is meant to run with the FLASH_LOAD linker script\n");
+    return EXIT_SUCCESS;
+#else
 
     soc_ctrl_t soc_ctrl;
     soc_ctrl.base_addr = mmio_region_from_addr((uintptr_t)SOC_CTRL_START_ADDRESS);
@@ -84,4 +88,6 @@ int main(int argc, char *argv[]) {
     }
     PRINTF("All tests passed!\n");
     return EXIT_SUCCESS;
+
+#endif
 }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h
index 323d1a06..59dc4443 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_data_processing_from_flash/matrices.h
@@ -1,206 +1,112 @@
 #ifndef MATRICES_H_
 #define MATRICES_H_
 // This file is automatically generated
+#ifdef FLASH_LOAD
 int32_t __attribute__((section(".xheep_data_flash_only"))) __attribute__ ((aligned (16)))A[] = {
-8,0,9,3,0,0,7,3,4,4,4,0,5,1,9,3,9,1,0,4,1,1,9,4,6,9,8,1,3,3,2,6,5,6,8,7,4,3,3,1,1,9,8,9,6,3,1,6,4,3,6,1,9,0,6,7,5,0,6,5,1,5,6,2,
-3,1,8,2,9,8,1,3,0,2,4,6,6,5,7,1,5,5,5,8,6,5,4,9,2,6,7,1,7,2,5,0,9,9,7,6,2,1,6,5,4,9,5,3,1,5,6,9,3,4,4,1,1,7,2,5,8,0,6,4,3,1,8,2,
-3,8,8,0,7,5,1,9,1,2,2,2,0,6,4,6,2,4,7,6,0,9,9,8,5,1,9,5,9,8,2,2,7,7,7,5,9,0,3,4,5,3,9,0,2,2,0,7,2,3,1,1,5,5,3,6,4,4,3,7,5,6,0,4,
-9,4,4,2,0,4,3,5,7,5,7,5,3,6,5,4,5,7,4,2,4,0,2,8,6,8,4,0,1,3,8,5,4,8,5,1,6,0,7,6,3,1,1,6,2,5,4,9,4,9,5,1,3,7,0,1,0,2,6,3,8,0,1,6,
-3,7,8,9,5,1,7,5,5,8,9,7,2,1,2,1,0,3,5,5,3,0,3,0,8,3,3,5,6,3,7,2,2,6,6,1,7,1,7,6,7,1,7,2,0,6,5,1,7,6,6,4,6,3,7,2,1,0,5,9,1,1,1,1,
-4,5,6,7,5,3,5,0,2,9,1,7,1,5,6,6,8,8,1,4,5,8,5,2,5,8,8,5,9,5,2,5,6,4,1,2,9,7,1,1,0,6,9,1,2,2,6,3,7,6,6,1,2,0,1,1,8,9,7,0,4,9,0,3,
-5,9,0,0,6,3,8,2,4,5,2,9,1,4,4,8,9,3,5,7,1,6,8,8,7,9,3,7,7,4,8,4,9,6,3,1,5,0,6,7,9,6,9,6,4,9,0,6,0,2,1,4,9,4,7,6,0,1,8,2,8,4,2,9,
-5,0,0,9,3,7,3,3,8,4,2,0,1,9,5,5,0,0,4,9,8,7,1,3,3,4,3,0,0,3,3,0,2,5,1,8,6,0,2,0,4,2,3,2,9,5,5,2,8,9,4,2,9,7,7,8,8,3,8,9,3,9,1,9,
-6,8,4,2,5,3,3,5,1,0,0,8,1,3,9,9,5,5,9,0,5,9,8,2,4,1,4,3,0,6,7,9,9,2,1,8,1,5,1,9,6,3,9,5,0,1,3,6,4,7,5,0,4,6,3,1,4,9,2,1,8,2,8,5,
-9,8,5,1,8,0,0,0,1,5,2,6,2,3,2,6,6,7,3,6,6,3,5,9,8,8,1,7,4,4,1,2,0,2,4,3,0,0,5,5,3,8,6,1,4,6,4,8,5,9,7,9,8,1,0,9,8,1,9,6,4,4,0,2,
-1,6,0,4,7,8,1,6,8,8,9,4,7,8,1,3,5,4,1,2,8,3,6,4,2,0,1,9,3,9,6,9,2,2,3,3,2,7,1,0,2,8,9,9,9,8,7,4,2,9,4,8,2,0,9,0,3,2,5,6,4,9,3,1,
-0,9,9,8,5,4,5,4,1,9,3,3,0,1,6,3,8,6,6,6,3,8,5,7,8,9,4,1,8,2,6,0,5,3,6,7,1,9,8,7,9,0,5,5,3,7,0,1,2,9,4,3,8,3,2,6,1,0,5,5,6,0,4,8,
-8,6,2,6,1,4,4,2,0,3,9,8,9,3,1,8,2,9,5,9,9,4,6,0,9,9,9,4,8,7,7,4,4,1,7,9,9,7,3,2,1,6,5,6,5,4,7,9,0,1,0,5,6,9,1,5,1,1,7,5,8,6,7,6,
-7,6,5,8,6,2,3,1,2,8,3,9,5,9,3,9,8,8,2,4,7,0,7,4,1,1,9,8,9,7,4,9,3,4,8,3,6,1,1,7,4,9,7,6,8,3,9,1,2,8,2,1,1,6,0,1,2,1,2,2,2,1,0,1,
-3,2,7,7,9,2,1,4,0,0,4,4,4,1,4,3,2,1,1,6,4,0,4,6,2,4,9,1,1,3,6,9,0,0,0,0,4,4,6,7,5,9,0,4,1,7,7,0,5,9,4,5,4,1,9,1,3,0,8,4,9,1,8,3,
-9,9,3,9,1,9,4,5,3,6,0,5,8,4,3,9,0,2,7,6,1,9,7,4,0,0,9,4,1,6,3,6,7,9,3,9,4,6,6,1,1,7,0,8,0,3,1,0,5,9,3,9,4,7,7,1,1,7,7,1,1,0,2,1,
-0,8,7,7,8,0,9,0,4,3,9,1,3,8,3,8,4,2,1,2,2,9,0,2,4,6,1,3,1,8,9,0,1,7,9,0,1,7,2,3,7,7,7,0,0,1,4,4,8,4,8,7,8,9,9,8,9,3,1,6,5,4,5,2,
-6,1,9,3,1,9,0,6,0,0,1,5,3,0,0,4,7,7,2,4,8,8,9,3,8,8,9,4,5,3,8,4,1,2,7,5,4,4,9,3,7,5,2,9,4,5,0,3,2,3,7,2,2,8,7,1,4,4,9,2,1,7,7,6,
-6,3,0,2,7,7,2,8,8,7,1,6,8,1,5,6,7,7,7,4,9,8,4,8,7,6,0,8,0,9,8,0,8,8,1,4,7,8,7,3,3,9,8,6,5,7,8,9,0,8,6,6,7,4,8,3,6,0,2,8,3,9,3,1,
-5,9,0,5,3,9,5,4,6,8,4,9,9,6,8,2,5,8,0,1,3,8,5,9,8,3,1,4,9,0,9,8,1,6,6,9,9,5,0,4,9,4,2,5,3,0,2,9,8,1,6,3,7,3,8,2,9,9,9,6,0,7,4,5,
-7,0,7,7,1,7,7,3,2,5,4,5,7,5,7,2,8,7,2,0,2,8,3,9,7,5,1,0,5,8,7,2,1,9,2,3,3,7,7,1,4,3,2,2,8,3,0,7,4,6,1,5,0,3,6,5,0,9,4,2,3,1,5,0,
-9,4,2,7,3,2,5,8,5,1,7,2,1,9,1,6,7,3,7,0,2,7,9,4,3,1,9,6,1,3,2,5,9,9,1,9,0,5,4,2,3,3,3,3,1,7,2,2,9,9,8,4,1,1,1,1,6,6,5,4,0,3,1,2,
-1,9,3,6,6,3,4,9,3,4,2,2,4,3,5,4,0,6,5,1,1,1,2,7,9,4,0,0,3,7,1,8,9,0,7,7,1,3,7,7,5,7,9,7,0,0,8,1,9,0,3,9,3,9,0,8,4,5,4,5,6,0,9,4,
-5,6,4,1,1,8,9,4,3,2,5,9,5,4,5,6,9,4,1,7,1,3,0,0,5,9,5,2,3,2,5,5,7,2,2,9,3,1,2,8,5,0,1,0,8,9,2,9,3,4,6,9,5,4,7,4,7,9,6,1,0,8,2,8,
-5,3,4,4,8,1,5,5,2,4,2,1,1,5,6,3,2,4,9,1,1,5,3,1,3,3,8,0,4,8,8,4,7,0,1,1,6,2,1,0,8,2,0,4,4,4,5,4,0,7,7,8,5,5,0,0,0,1,8,8,7,4,7,9,
-1,7,2,6,1,6,7,6,2,9,6,2,5,7,7,8,1,5,7,3,3,4,9,8,7,6,5,5,2,8,7,8,7,1,6,0,5,2,2,4,2,3,3,2,0,0,3,4,5,2,2,9,2,9,7,7,9,5,9,0,1,5,3,0,
-7,4,1,9,4,5,0,6,7,4,1,2,7,4,0,8,8,3,7,0,5,3,2,2,4,2,7,0,0,5,0,4,6,9,6,2,2,4,5,3,4,4,2,8,7,3,9,4,5,8,5,2,9,4,1,3,2,9,2,2,4,3,9,8,
-6,7,8,8,8,8,9,1,1,5,0,5,5,4,2,0,3,0,4,2,1,0,2,6,2,8,1,4,1,6,8,0,0,5,1,3,8,0,2,3,6,6,3,3,4,8,9,2,8,3,1,3,7,2,1,4,9,9,4,4,3,1,2,1,
-0,9,9,6,9,3,9,7,5,3,9,3,0,2,9,6,2,2,5,6,8,2,9,6,8,3,6,7,4,4,3,8,6,1,2,6,6,0,9,0,0,9,3,9,9,8,4,8,6,8,0,6,1,3,0,8,4,3,5,3,0,6,2,2,
-1,7,1,4,3,5,6,3,7,2,3,1,6,3,5,2,9,3,7,0,6,9,6,5,3,9,6,0,2,3,1,0,6,2,5,8,2,3,0,0,0,4,3,9,4,6,3,5,2,0,3,8,8,2,8,2,5,6,9,7,3,2,9,9,
-5,5,4,0,2,4,0,4,5,2,7,6,6,8,5,3,5,5,2,7,3,8,7,5,5,3,6,0,8,6,3,1,7,4,7,1,0,4,3,0,7,9,5,0,6,0,7,3,3,8,2,5,1,4,4,1,6,4,2,5,5,6,8,0,
-8,5,9,6,7,9,8,2,9,1,5,1,0,5,9,6,1,9,8,7,6,9,1,0,1,2,8,4,7,4,5,6,9,1,5,8,7,2,4,3,8,3,8,9,0,6,3,1,6,5,7,0,3,1,3,8,5,7,0,8,8,2,7,3,
-7,2,8,3,9,8,9,1,6,5,0,4,5,7,3,9,9,0,9,9,2,6,4,3,3,3,3,9,5,5,7,4,2,4,7,2,3,5,5,9,8,6,3,1,5,7,6,8,9,4,1,8,8,5,4,9,0,7,5,4,5,3,6,9,
-0,4,8,3,0,9,2,7,1,2,8,5,6,2,8,5,2,0,4,8,2,5,8,2,0,5,7,8,8,0,8,9,3,7,9,5,4,9,4,2,6,9,7,1,5,4,6,3,2,6,3,9,8,4,1,0,1,6,2,0,5,3,7,6,
-6,4,6,1,0,7,3,4,6,2,7,1,3,9,0,5,5,4,7,0,0,3,4,8,2,6,6,9,9,0,2,6,5,9,9,7,7,0,6,2,2,7,8,3,8,6,0,4,7,7,0,9,2,2,1,5,1,8,2,3,7,7,1,9,
-0,4,2,8,9,7,3,4,1,5,3,3,0,6,4,1,1,8,1,4,9,6,4,0,8,0,2,7,2,2,1,2,8,3,2,3,7,5,9,1,7,8,5,5,6,2,0,0,1,4,3,5,2,8,4,2,7,7,0,5,7,3,4,0,
-1,7,4,5,1,3,9,1,8,2,3,7,0,2,9,3,5,3,3,9,2,6,0,5,7,4,9,7,9,6,9,6,4,1,5,3,7,3,0,2,3,9,7,7,8,2,5,8,4,0,8,3,3,0,4,3,0,5,7,3,7,3,9,7,
-4,5,5,0,8,1,5,7,8,1,2,5,8,3,0,6,2,9,6,4,5,5,6,6,0,3,8,0,2,0,9,9,1,7,9,4,8,8,7,5,8,1,5,0,0,4,7,1,2,0,2,0,6,7,8,0,1,3,4,0,8,6,9,5,
-6,6,9,6,5,1,2,7,1,6,5,5,5,7,2,8,3,5,6,0,8,7,6,9,3,8,8,8,5,3,4,8,5,6,9,2,7,5,7,3,1,7,2,2,9,6,1,9,2,4,4,3,9,2,5,1,6,7,7,2,9,8,6,0,
-9,4,4,3,0,3,4,7,1,0,8,4,8,3,1,4,2,5,9,0,0,1,8,5,1,9,3,0,8,9,9,7,4,2,0,3,7,5,8,8,9,1,6,8,3,2,1,6,7,1,6,9,5,9,9,3,5,2,3,4,7,2,1,1,
-4,8,0,1,3,6,6,2,5,2,7,2,5,5,7,0,6,4,6,4,8,0,6,4,0,3,6,7,9,7,4,6,8,9,8,7,8,5,0,5,4,5,4,2,8,6,7,8,2,2,0,8,6,4,3,9,7,1,2,3,5,2,5,2,
-8,7,0,9,4,4,0,7,5,9,1,8,7,6,9,3,5,6,8,7,8,8,6,9,4,8,6,1,2,8,5,1,1,3,3,3,6,2,8,0,7,3,1,3,2,4,1,1,3,5,6,1,0,9,7,7,7,9,3,4,3,3,6,7,
-3,2,8,4,1,0,4,9,4,2,9,5,7,0,9,0,7,8,1,1,8,9,9,3,4,0,7,9,1,4,7,7,9,6,1,8,1,4,1,2,1,6,8,5,8,9,5,1,2,4,3,2,4,6,9,0,6,7,0,8,5,5,2,4,
-2,8,7,9,4,3,4,7,0,1,6,9,2,4,9,0,4,2,4,7,6,2,7,7,6,1,5,7,0,2,4,8,4,9,0,1,4,0,1,5,4,9,1,6,8,6,7,9,6,7,6,5,2,0,1,7,1,0,8,0,1,2,5,2,
-0,6,8,8,3,3,5,7,1,1,7,5,2,6,2,0,4,2,7,0,7,9,6,9,1,8,4,3,5,7,1,9,3,3,0,5,6,2,0,5,1,6,8,0,1,2,0,6,7,7,9,6,5,6,2,6,9,4,2,7,4,9,6,8,
-3,3,9,1,5,2,9,1,4,4,8,9,3,8,1,4,7,9,0,2,4,8,4,5,6,0,7,4,8,9,6,9,9,3,4,9,6,2,2,6,4,0,5,2,5,3,2,3,4,1,3,4,1,9,5,4,9,3,0,3,4,1,2,8,
-4,2,0,9,7,5,7,2,9,0,8,6,0,1,5,6,8,3,4,7,5,9,2,0,8,7,6,6,7,1,3,5,3,7,6,2,1,8,2,0,4,1,6,9,3,0,5,7,1,1,6,8,3,4,1,2,7,6,5,6,6,1,1,2,
-6,3,5,8,4,9,2,0,9,7,5,4,3,5,7,0,5,7,7,4,4,0,5,3,4,6,0,0,2,2,7,7,0,5,7,2,6,5,3,5,9,9,4,1,6,7,7,3,4,8,6,6,1,1,7,1,3,4,4,4,4,2,1,1,
-7,1,2,0,5,9,2,1,3,9,3,7,4,9,5,1,6,5,7,2,0,5,2,4,8,0,5,2,6,6,7,9,8,7,7,8,5,2,4,6,9,3,4,8,8,1,3,4,5,2,2,7,3,9,2,8,8,8,8,8,1,4,1,4,
-8,6,3,2,5,1,1,0,9,9,9,8,3,9,5,4,6,2,0,0,4,6,7,1,0,0,0,2,5,2,5,4,9,1,1,5,6,7,6,0,6,4,3,6,5,2,8,7,3,4,0,7,5,4,6,8,8,9,9,6,2,3,2,9,
-0,4,9,6,2,5,0,6,0,6,2,0,5,9,7,9,9,7,9,7,3,0,9,7,9,2,5,0,7,5,7,6,7,7,9,9,1,7,1,6,1,3,9,3,6,4,4,9,8,9,6,4,8,5,8,1,5,9,2,5,4,7,2,7,
-1,1,3,6,0,1,9,3,5,0,5,0,0,3,0,3,7,7,5,7,5,8,0,4,9,8,8,2,3,7,1,9,8,3,2,1,4,7,8,4,3,7,6,0,2,7,6,2,4,6,2,4,9,2,5,0,0,0,7,5,3,5,7,1,
-7,5,9,1,5,8,8,6,5,1,8,4,3,2,1,9,7,8,1,2,3,5,6,0,6,1,0,3,7,9,1,3,0,2,0,5,4,7,3,9,3,4,6,6,6,8,2,0,4,8,3,1,1,2,0,6,9,9,9,8,3,4,7,7,
-4,9,4,5,0,9,6,5,5,2,5,5,5,5,1,9,4,9,8,1,5,2,9,8,1,9,9,0,0,7,4,8,7,1,8,8,7,3,3,2,2,4,5,0,1,2,3,6,9,0,0,2,1,5,5,7,7,0,7,6,5,5,7,6,
-9,1,9,3,8,2,2,9,7,9,4,9,5,2,6,5,5,3,7,2,8,8,7,7,9,2,1,4,0,2,2,8,8,5,9,9,0,5,2,1,5,5,3,3,7,0,7,3,5,9,8,2,6,0,3,7,8,8,4,6,6,3,3,3,
-0,8,6,6,5,9,4,8,7,8,4,8,3,8,7,9,4,4,5,5,6,0,9,4,9,2,8,7,0,1,2,5,3,6,1,9,2,7,4,6,4,7,9,5,6,0,4,1,1,2,6,5,2,1,1,9,6,2,0,8,0,4,7,5,
-8,5,6,2,3,3,9,4,4,1,9,2,7,0,6,8,1,5,6,7,3,9,9,4,5,6,9,6,7,9,0,2,8,5,1,3,9,2,8,3,5,3,9,2,5,6,3,7,0,2,4,8,2,8,4,2,2,1,8,9,2,1,7,4,
-3,8,3,6,2,1,1,6,1,1,7,9,3,4,5,4,8,7,2,3,9,8,8,1,8,0,8,5,8,1,1,2,2,3,9,5,6,1,0,3,1,5,2,1,6,4,4,7,0,4,9,8,7,6,6,9,6,3,0,6,7,6,3,5,
-2,1,9,4,2,4,3,9,1,9,0,9,9,2,2,1,5,2,2,9,2,4,6,2,3,3,4,0,0,8,8,4,6,2,2,5,6,7,5,6,1,3,9,7,0,1,2,2,5,9,2,1,3,1,8,8,1,3,6,9,6,0,9,2,
-5,4,8,8,6,8,9,1,7,6,2,0,7,8,6,1,0,6,9,2,7,6,8,1,3,6,2,1,5,1,0,4,9,1,5,2,4,4,4,5,6,4,4,6,8,5,6,7,8,5,3,1,3,3,6,9,6,0,0,8,1,8,8,6,
-9,0,5,0,9,6,4,8,3,9,9,8,2,8,0,0,9,5,2,1,2,0,1,5,2,1,9,6,3,8,7,0,1,0,9,1,0,1,6,0,8,7,4,5,6,4,5,6,5,9,5,8,9,4,2,0,8,2,6,5,4,5,4,5,
-8,7,5,6,8,4,8,2,4,6,5,0,2,1,1,0,8,3,0,0,6,7,6,5,5,7,0,9,4,2,1,0,8,1,5,0,4,5,5,1,4,6,6,5,5,2,2,7,9,8,6,6,4,3,9,5,7,6,5,8,5,7,7,3,
-2,4,8,3,7,6,5,0,3,8,0,4,8,7,6,3,6,0,3,2,8,7,4,6,2,1,6,3,5,7,5,1,5,3,8,9,9,3,0,7,2,6,7,5,5,7,3,3,9,7,6,3,6,4,3,2,5,3,5,0,1,2,7,3,
-6,0,1,2,3,9,7,8,4,6,3,8,3,0,5,2,9,1,9,6,9,6,2,1,0,6,0,1,2,5,6,4,9,8,9,4,1,2,6,6,4,7,1,2,7,3,7,9,9,2,6,0,4,4,2,5,0,0,4,6,2,4,8,0,
+9,2,4,0,5,0,6,4,3,9,7,8,0,8,9,0,3,2,4,0,5,8,3,4,0,4,9,8,3,6,4,7,
+5,7,3,4,1,8,5,7,7,3,1,0,5,8,5,5,4,1,8,0,1,6,7,8,4,1,1,6,2,1,2,6,
+0,7,7,6,4,7,2,9,9,1,2,9,7,6,1,8,1,1,6,5,0,6,3,3,7,6,6,4,2,7,2,6,
+7,6,3,7,3,3,5,0,2,8,2,1,8,7,1,4,5,5,9,4,0,9,9,1,9,9,0,9,0,9,1,9,
+1,1,5,0,3,4,0,2,5,4,2,3,2,8,0,4,3,8,1,2,0,2,2,7,2,7,4,6,8,1,4,7,
+0,8,7,7,4,2,5,3,0,7,0,3,9,1,9,3,9,2,4,8,0,7,2,0,6,2,9,7,8,5,0,8,
+3,9,3,0,1,1,7,8,2,7,9,4,2,6,9,2,4,1,8,3,9,8,3,4,5,4,8,0,2,4,9,0,
+2,0,6,7,4,3,3,1,8,4,6,7,5,3,9,9,6,1,8,4,4,2,5,6,7,6,2,6,4,2,1,5,
+7,3,0,8,6,6,2,8,6,9,6,8,4,0,0,5,5,5,0,4,4,0,9,8,9,9,8,2,2,0,1,0,
+5,6,2,7,4,9,2,8,8,2,2,4,0,9,0,9,7,2,6,6,7,3,7,8,3,7,1,0,0,0,6,1,
+5,4,8,7,5,3,3,1,2,5,6,0,3,9,6,4,7,3,1,2,0,8,6,2,4,5,1,9,5,0,8,8,
+6,9,0,7,0,3,8,6,6,8,4,3,1,7,8,2,4,4,2,3,3,8,3,9,5,4,3,9,4,5,9,6,
+7,0,0,7,0,8,6,7,1,1,3,9,7,7,0,7,0,9,8,3,6,4,9,1,3,9,0,3,6,0,1,0,
+6,9,9,6,3,5,9,4,1,3,8,2,9,6,5,9,1,3,1,4,1,8,7,6,3,2,9,1,1,5,0,2,
+5,2,8,5,3,4,7,8,6,7,0,1,0,4,7,5,6,0,8,6,9,9,5,9,7,3,2,8,5,3,6,5,
+1,4,4,1,6,7,0,8,6,8,6,7,8,2,3,6,6,1,0,1,2,0,6,4,5,1,2,2,3,7,7,3,
+0,3,6,7,5,4,1,2,8,1,9,3,6,5,5,3,7,5,4,1,3,2,3,0,8,5,5,2,6,9,1,7,
+8,6,9,3,9,4,1,9,1,4,8,7,5,2,5,0,7,7,9,5,2,9,8,9,5,7,6,5,1,6,1,0,
+2,8,6,6,7,3,0,9,3,5,5,9,2,0,2,3,9,9,3,0,0,4,5,1,2,6,5,0,6,0,6,3,
+9,8,1,1,0,2,2,4,3,7,4,8,9,8,5,0,8,4,6,6,7,4,5,4,1,9,1,9,1,3,5,2,
+0,8,2,2,5,3,0,2,2,4,5,3,4,1,2,3,7,7,0,2,6,8,5,7,5,1,6,5,8,2,8,4,
+9,8,4,3,3,7,9,8,3,5,9,8,6,1,5,3,2,8,8,2,3,0,1,4,4,1,7,3,1,0,6,1,
+6,6,1,4,4,3,1,7,9,3,6,8,2,4,4,7,6,6,0,8,6,7,6,0,0,2,9,7,4,7,2,1,
+2,3,7,1,3,2,4,7,8,8,9,2,0,1,7,9,4,5,9,4,5,6,2,3,6,0,7,9,4,5,8,2,
+9,2,8,2,2,5,3,6,1,2,4,3,2,3,7,6,7,9,2,4,4,3,7,1,1,0,9,2,6,3,4,9,
+1,9,7,1,7,2,2,1,0,3,0,2,3,0,9,6,4,0,4,9,5,3,9,0,5,3,0,7,9,5,8,4,
+1,7,6,5,4,4,6,0,7,7,4,7,8,3,8,1,6,4,2,0,6,5,6,4,7,3,6,9,8,2,5,0,
+3,4,3,8,0,4,2,8,9,8,9,9,1,8,3,1,8,0,9,7,8,3,3,1,3,0,3,2,7,4,0,7,
+8,6,3,2,3,9,7,5,3,2,0,2,7,2,8,8,4,3,6,9,7,7,6,6,3,1,2,7,6,5,9,0,
+4,1,2,9,4,5,5,2,8,1,6,7,7,0,4,0,4,4,0,8,0,5,8,5,5,5,0,9,3,3,1,7,
+9,7,0,5,1,4,6,0,2,7,5,8,5,6,5,4,8,2,4,2,9,2,2,4,6,0,2,0,3,0,6,8,
+7,3,4,2,4,1,3,7,1,9,8,0,6,0,1,4,8,9,0,6,8,2,2,7,8,5,6,5,2,8,7,7,
 };
 
 const int32_t B[] = {
-1,1,9,1,9,6,7,6,2,8,2,8,5,6,3,0,2,4,0,1,7,5,9,1,7,4,7,3,2,2,8,0,3,1,3,7,1,9,2,5,6,5,2,3,7,1,6,3,3,2,1,4,2,4,8,9,4,0,8,3,6,4,0,9,
-6,1,6,9,1,4,3,4,2,3,4,8,0,0,1,2,7,7,9,6,1,5,8,7,6,7,1,8,0,2,7,1,4,5,7,4,2,7,6,0,0,1,7,9,0,4,3,8,8,9,4,3,4,7,6,3,4,0,8,9,5,1,1,7,
-3,3,4,7,0,4,1,5,2,1,2,5,6,6,1,4,4,2,8,7,5,4,0,5,8,1,7,2,3,4,7,7,6,3,1,5,6,2,8,5,7,8,7,7,9,3,5,9,9,1,1,1,6,8,5,5,9,7,9,5,8,9,0,9,
-2,9,2,2,4,4,6,7,4,7,4,2,4,2,7,2,2,2,9,6,7,2,1,5,0,9,5,2,8,6,8,6,2,7,8,2,0,1,0,2,9,0,3,9,9,6,9,2,1,7,1,1,4,6,7,9,8,8,5,3,1,1,8,5,
-2,2,8,2,0,6,7,3,0,1,2,0,5,2,6,9,3,5,2,0,9,7,6,7,2,5,2,3,0,6,0,4,5,1,6,4,7,8,0,1,0,7,1,6,6,5,4,7,2,3,0,3,8,0,7,4,5,0,3,8,6,3,5,0,
-9,1,3,8,5,9,4,9,0,2,9,7,1,1,0,8,4,7,8,5,3,2,3,0,9,8,3,7,5,8,8,5,9,5,6,5,2,7,3,3,7,2,2,7,0,0,4,9,8,8,0,6,0,9,3,9,6,5,7,0,8,2,2,3,
-4,3,2,5,2,0,4,6,7,1,5,1,6,4,1,0,4,6,1,1,3,8,8,9,1,1,9,9,7,5,0,8,5,5,9,0,4,1,7,5,2,2,7,8,5,1,1,0,0,2,0,1,7,9,2,0,3,7,7,8,6,9,4,0,
-6,0,4,1,4,2,0,2,5,4,0,6,9,9,1,1,8,7,5,0,3,3,8,6,1,1,3,1,9,2,4,6,2,5,6,6,8,4,6,1,3,0,7,1,3,3,0,3,3,2,7,4,6,0,6,7,7,7,0,4,9,4,9,4,
-1,9,5,5,4,5,7,7,2,4,9,4,6,0,3,5,2,6,8,0,3,0,5,5,1,6,9,2,6,9,7,3,8,0,6,1,0,0,4,4,2,3,3,7,8,1,7,4,7,0,9,2,1,4,2,7,0,3,0,7,7,7,4,0,
-5,0,9,9,7,4,0,5,7,3,7,5,2,4,4,9,5,4,5,7,5,1,2,1,3,8,8,5,1,6,6,3,9,8,1,1,9,4,7,9,8,8,4,5,0,9,5,3,0,3,5,7,4,2,5,5,2,9,9,7,7,9,2,3,
-4,9,9,2,5,3,1,7,6,2,5,2,5,9,3,1,1,9,0,3,1,1,2,5,0,7,6,0,4,0,0,5,5,9,8,4,1,0,9,8,9,7,1,5,8,5,7,1,1,3,7,1,3,4,7,8,7,8,8,5,2,7,5,5,
-0,9,7,2,6,8,5,7,0,3,6,9,1,2,5,7,7,2,9,6,6,9,7,1,0,6,6,4,3,3,7,1,8,0,7,2,8,9,2,1,0,1,7,9,5,7,6,8,5,4,0,1,7,9,8,9,0,5,4,9,8,5,5,9,
-9,9,3,4,5,3,7,5,7,3,3,2,1,5,7,5,0,8,4,5,8,9,4,3,9,8,2,6,3,9,3,1,3,6,5,3,9,0,8,4,5,5,5,9,4,0,9,6,0,4,4,6,2,5,8,2,0,9,0,0,0,0,7,9,
-4,9,3,6,2,7,0,5,9,6,9,4,8,6,2,1,9,0,2,2,6,9,5,0,5,8,7,6,3,8,6,9,8,9,8,2,8,2,9,4,2,7,2,6,6,9,0,1,9,8,9,0,0,5,3,5,8,7,9,1,4,9,8,1,
-3,5,1,8,4,8,7,4,0,4,9,8,0,8,6,7,0,7,9,1,6,6,4,8,2,0,8,9,7,8,9,0,1,4,2,0,9,4,9,5,3,0,4,0,6,8,2,0,3,9,7,4,8,3,4,9,4,6,9,6,2,9,9,6,
-5,2,1,9,2,2,6,4,4,3,4,4,6,0,2,9,0,8,4,6,3,4,1,6,6,5,4,4,5,0,0,3,4,4,1,1,4,9,8,0,1,6,2,6,1,3,7,3,4,1,5,9,0,1,9,2,7,3,6,7,1,4,7,7,
-7,7,9,0,8,0,2,4,2,3,7,5,7,4,2,0,8,8,3,7,1,4,7,2,7,9,4,3,0,8,1,6,9,8,6,0,3,4,7,8,8,6,7,1,7,9,9,9,6,0,3,9,4,8,8,3,8,9,5,0,4,4,4,7,
-7,8,3,4,5,8,1,6,7,5,2,0,9,5,9,7,1,8,6,4,4,9,3,8,6,2,8,3,0,7,6,5,9,6,5,8,0,9,8,7,4,4,1,1,8,7,8,7,2,2,8,8,3,1,9,2,2,5,8,6,3,3,7,8,
-1,3,6,6,2,8,8,1,2,5,2,4,8,3,8,5,0,8,4,9,9,3,4,4,3,6,6,7,3,3,8,5,0,9,6,9,0,2,5,8,9,3,1,0,8,8,4,4,3,5,9,8,6,1,2,0,9,4,2,9,4,0,0,1,
-8,1,7,6,0,2,2,7,6,0,1,7,6,9,0,9,7,8,4,9,6,2,4,3,3,8,8,8,5,6,3,2,2,7,1,7,8,6,6,1,4,0,8,3,5,0,0,3,5,2,3,4,2,4,9,2,1,0,4,3,3,2,0,5,
-3,8,0,3,8,6,8,3,8,8,7,2,5,4,6,5,5,8,2,8,8,1,4,0,8,9,3,2,0,9,7,2,9,4,6,2,5,0,2,5,9,1,7,7,9,9,4,5,3,7,6,3,3,9,4,8,5,4,6,4,0,8,8,2,
-0,0,8,9,8,3,3,9,7,2,6,9,2,9,4,6,8,3,8,7,7,6,4,7,8,5,8,6,1,3,0,2,2,9,4,8,0,1,3,6,4,2,9,2,1,4,7,0,3,8,5,6,6,1,6,2,0,0,2,4,1,4,4,4,
-6,8,7,2,1,9,3,3,8,5,8,2,7,5,9,8,5,6,5,9,8,6,3,2,7,1,1,2,7,6,7,1,1,6,8,5,0,8,4,4,3,6,8,1,7,6,0,9,2,6,0,2,2,8,6,2,6,9,7,3,3,3,5,4,
-6,0,5,0,9,4,5,1,9,8,1,4,5,7,2,2,9,0,3,7,3,2,9,2,6,5,3,7,2,6,1,3,1,5,7,1,4,6,0,6,4,9,1,5,0,1,8,0,5,9,8,5,2,1,0,7,3,2,5,8,1,7,5,3,
-0,5,8,3,4,8,3,3,6,1,2,9,6,8,3,6,6,9,8,1,5,2,0,9,6,7,1,7,6,3,0,9,0,3,5,6,2,4,2,8,2,7,5,7,6,5,2,2,0,2,8,9,3,6,7,6,1,5,2,9,0,1,7,5,
-9,0,0,5,5,8,3,0,9,7,6,8,5,7,2,4,9,8,2,2,8,3,1,6,5,1,8,6,2,0,8,5,5,8,0,3,1,8,0,0,6,8,4,1,4,1,5,0,0,9,0,0,2,2,3,3,1,8,6,6,3,7,1,3,
-6,6,0,9,4,8,7,5,0,3,1,4,0,1,1,2,8,7,4,4,8,3,1,1,6,3,7,9,2,0,8,9,6,5,8,7,0,8,8,6,3,4,9,1,5,0,9,8,8,2,0,4,2,5,7,0,7,5,1,6,5,8,6,9,
-9,6,7,5,2,9,9,1,7,1,0,4,4,9,5,8,9,3,2,8,4,0,7,3,5,8,2,6,2,1,7,0,5,0,1,9,3,2,7,7,4,1,6,4,9,6,3,5,6,8,2,5,3,9,1,5,3,2,7,1,9,1,2,8,
-1,0,7,9,9,1,7,7,0,5,6,8,6,8,7,4,9,6,3,7,9,3,2,5,2,4,6,7,8,9,7,5,6,9,7,4,3,7,0,1,7,1,1,7,8,4,9,8,7,1,0,2,6,8,4,9,1,9,1,3,9,7,4,5,
-1,9,7,9,0,0,4,3,2,4,4,8,0,6,1,8,8,2,0,9,0,7,0,5,4,8,9,8,7,7,8,5,9,2,6,2,2,9,6,7,1,1,1,7,7,4,3,0,8,5,5,0,1,1,0,9,3,8,3,0,9,3,8,7,
-4,7,5,5,2,4,5,1,3,4,6,7,7,4,3,0,7,7,8,4,0,3,4,9,0,4,6,6,4,3,9,5,5,5,2,6,2,1,8,0,8,5,0,8,2,5,7,2,6,4,3,4,7,4,3,5,0,0,1,3,0,6,7,4,
-1,7,8,7,4,6,1,9,2,1,3,1,4,5,8,6,8,0,2,8,8,7,6,5,5,4,3,7,0,0,3,6,7,8,2,4,0,0,7,0,8,0,8,7,1,2,1,5,4,0,6,9,4,6,0,4,0,6,6,4,6,2,3,8,
-3,2,5,5,6,6,0,8,2,5,8,5,8,9,8,6,6,2,5,0,4,4,5,9,6,3,9,5,7,6,1,6,2,6,5,8,2,2,4,1,0,6,2,1,9,7,9,5,9,7,8,3,1,2,1,0,7,5,4,4,6,4,5,8,
-1,4,1,3,8,8,1,0,5,0,2,4,8,3,4,0,7,0,0,9,6,6,0,3,8,3,2,8,2,3,5,5,4,9,5,3,7,9,8,6,6,3,4,6,7,7,3,1,1,5,4,2,0,9,5,1,4,5,4,0,8,2,4,8,
-5,4,4,9,9,1,0,6,9,8,4,6,0,3,8,9,4,9,5,6,2,7,0,5,7,8,0,3,7,0,1,3,1,4,7,4,7,6,3,4,7,2,4,8,9,2,4,1,7,1,9,9,5,5,4,0,5,4,5,8,6,8,1,2,
-9,0,0,2,7,4,2,1,3,1,7,3,6,2,5,9,3,8,5,5,8,8,2,9,3,5,2,6,9,3,0,4,3,7,8,3,7,2,6,5,8,2,9,7,1,1,9,0,8,5,8,0,1,3,1,5,9,8,1,9,1,9,2,9,
-6,7,5,6,2,5,7,6,0,9,5,7,4,3,0,6,1,8,7,9,5,7,2,8,1,5,4,3,4,7,4,7,5,0,0,4,2,8,0,2,9,9,5,1,7,3,0,7,3,3,3,0,9,7,6,8,5,6,0,2,1,5,3,5,
-7,7,8,2,6,6,6,8,2,9,8,3,7,5,7,9,2,1,4,8,0,4,7,6,1,7,1,0,8,3,5,7,9,1,0,9,5,9,6,6,7,1,8,1,5,6,9,6,0,1,2,9,9,7,8,2,5,8,6,1,5,2,9,3,
-1,7,5,1,6,1,4,2,8,5,1,7,0,3,0,4,1,3,2,8,0,3,6,1,8,9,4,1,7,1,2,0,3,8,7,8,1,6,9,6,5,7,6,3,3,3,9,8,2,1,0,6,6,2,4,2,5,0,8,2,6,4,6,3,
-2,6,1,2,4,1,3,3,9,5,8,6,2,1,4,7,7,3,1,6,4,3,2,5,8,9,9,6,5,0,0,3,1,1,4,2,7,6,4,8,9,8,1,5,6,7,0,3,3,6,4,8,8,8,8,9,3,8,3,5,5,4,4,5,
-2,3,0,1,6,0,0,1,6,3,0,9,6,8,9,5,1,4,0,7,0,5,5,2,2,8,5,1,8,2,9,9,1,9,4,5,9,6,6,5,9,2,7,6,4,4,5,2,9,5,4,6,8,4,0,7,6,1,5,3,0,9,5,1,
-2,5,4,4,4,8,2,8,8,6,6,9,6,4,1,7,7,8,1,6,8,7,9,4,2,4,1,4,2,0,5,8,8,9,6,9,7,6,1,0,9,7,1,5,2,0,7,7,3,4,5,1,0,7,3,1,5,4,4,9,6,1,0,8,
-2,6,8,2,6,9,8,4,3,6,5,9,8,0,0,6,7,1,8,4,0,1,8,1,2,8,2,2,2,8,1,6,1,5,9,8,9,5,6,3,2,1,4,2,9,3,2,0,9,6,8,8,3,3,7,6,7,0,0,4,8,4,0,6,
-9,8,0,2,7,2,8,4,0,6,1,8,3,9,8,4,0,0,6,3,0,5,9,8,0,6,8,5,1,9,7,5,4,8,5,5,1,4,3,2,4,5,5,0,5,5,3,8,0,2,5,2,1,3,1,6,1,6,8,2,8,4,1,3,
-1,0,1,5,5,2,9,9,4,1,0,0,3,6,4,0,8,5,0,6,2,9,4,5,6,2,8,8,5,5,6,0,7,4,6,3,6,9,6,1,4,3,5,4,0,3,2,6,6,5,8,1,5,7,3,0,4,5,4,8,0,0,5,4,
-5,7,1,4,4,4,2,7,3,2,7,7,8,6,5,1,1,0,3,1,4,6,7,3,7,1,6,3,7,5,6,6,8,4,9,1,2,7,3,0,2,8,8,3,9,3,7,2,8,5,0,9,4,5,1,3,4,6,6,8,6,9,7,7,
-1,4,8,6,7,9,7,5,6,7,4,2,0,5,4,8,2,2,4,3,4,2,3,7,2,0,4,9,6,9,1,2,6,3,2,0,4,9,9,4,9,7,7,8,4,3,4,7,8,4,9,1,9,3,1,3,4,2,5,6,2,2,8,6,
-3,5,9,4,5,9,7,1,6,7,7,3,1,9,3,2,8,5,7,7,8,1,7,7,0,0,2,3,7,3,6,8,6,3,7,6,6,3,6,0,1,9,9,3,0,9,2,2,3,0,2,6,3,3,2,8,5,6,2,6,9,6,7,0,
-6,5,6,4,9,5,8,1,4,2,1,7,0,7,2,9,7,7,3,8,3,2,3,7,0,0,2,7,6,7,0,6,6,8,4,9,8,5,6,3,4,4,7,0,6,6,8,2,0,4,8,2,4,2,6,0,9,7,0,9,5,2,4,1,
-4,5,1,2,4,3,7,7,9,5,0,7,3,2,0,8,4,1,6,5,9,8,8,1,2,3,4,0,2,4,0,3,2,6,1,0,9,2,2,3,4,0,7,3,3,0,4,7,7,1,2,9,7,8,5,5,6,3,4,1,8,9,3,5,
-1,2,9,2,1,6,5,1,5,7,5,0,2,6,5,7,6,6,8,9,1,8,3,3,6,8,2,3,0,7,8,0,9,9,8,9,7,6,1,8,8,3,7,5,5,7,6,5,5,9,0,8,6,3,1,9,5,6,2,3,4,9,2,7,
-5,1,9,8,5,2,6,7,8,7,1,2,1,1,6,8,0,0,1,0,4,3,1,8,3,4,1,8,4,7,3,3,0,3,6,7,7,5,6,3,0,7,6,7,9,3,9,4,1,9,1,2,1,8,8,9,6,6,1,0,8,9,8,6,
-9,4,9,5,4,3,6,1,2,9,8,6,9,1,4,4,6,0,3,6,4,6,5,0,4,2,0,1,6,8,2,6,4,6,5,5,6,8,6,8,8,2,9,9,2,9,7,4,9,3,1,3,2,1,2,2,5,8,2,2,4,2,7,0,
-5,1,3,4,8,7,2,7,3,2,1,4,0,0,4,8,5,6,6,7,9,0,7,6,0,8,1,2,3,0,5,9,1,3,6,1,8,2,7,1,7,5,9,5,1,9,5,9,1,8,5,0,8,2,9,0,8,1,6,9,1,5,1,8,
-4,6,2,3,5,2,7,1,6,9,9,5,2,6,1,3,6,3,3,3,7,6,5,1,4,6,2,3,0,6,0,7,4,6,0,1,9,1,5,3,3,7,3,9,0,2,8,8,8,1,1,9,0,9,7,5,3,8,8,6,7,4,0,9,
-7,8,8,4,4,9,3,1,1,5,2,7,5,6,2,2,9,3,0,8,1,7,1,8,5,5,3,0,9,9,6,4,6,0,4,2,3,6,2,8,4,8,4,9,9,6,1,0,0,0,6,1,9,7,7,2,8,4,7,8,4,4,6,2,
-2,4,9,4,4,3,2,9,1,4,5,2,2,4,1,9,0,0,8,0,1,5,8,5,9,0,8,3,7,8,3,3,2,1,9,5,6,0,7,6,2,1,8,4,4,4,3,2,9,3,2,8,4,1,6,3,6,2,1,4,3,0,0,5,
-9,4,8,3,1,9,6,4,0,9,7,7,6,3,9,4,0,3,2,2,1,9,0,6,5,2,0,7,8,3,3,4,6,0,6,0,0,5,7,8,3,4,6,5,8,2,7,8,9,7,9,0,8,1,9,8,5,7,4,4,9,8,5,7,
-3,3,3,1,4,2,9,1,7,3,7,7,9,2,7,3,1,8,6,3,6,2,0,2,0,7,6,9,6,1,9,6,2,3,7,0,1,6,7,0,0,5,8,1,0,2,2,5,8,3,3,4,1,6,8,9,3,8,0,9,2,1,6,6,
-0,7,1,3,6,0,7,0,3,9,4,1,5,2,6,3,7,6,1,3,8,4,6,3,3,4,6,6,0,6,5,6,3,6,9,4,4,0,0,8,0,5,3,7,4,0,9,4,2,2,9,1,8,7,5,3,8,6,1,9,9,8,9,0,
-4,8,3,0,7,6,1,6,3,7,6,5,0,1,3,4,7,3,7,0,7,8,2,8,4,0,3,3,3,2,6,3,9,1,2,6,5,6,1,7,2,8,8,5,8,0,1,4,3,8,4,4,5,6,3,4,2,9,1,7,4,0,4,5,
-8,4,8,6,5,5,1,2,2,9,9,2,4,7,0,1,1,8,6,2,9,1,7,0,8,9,3,2,6,9,1,4,6,6,2,8,1,6,7,3,0,7,7,4,3,9,3,5,6,5,6,5,8,9,5,3,1,0,9,5,4,6,7,6,
-7,8,3,7,7,2,5,3,4,1,7,3,8,0,0,5,2,3,6,4,5,2,0,3,3,3,1,2,6,1,1,1,4,7,6,0,4,9,1,2,8,5,0,3,3,2,5,0,1,4,5,9,0,3,6,8,2,2,4,1,2,3,7,3,
-9,5,2,1,0,7,2,1,3,5,2,3,0,5,6,2,2,9,0,4,1,6,5,3,0,4,8,2,2,1,2,1,2,2,1,7,7,2,0,3,4,7,3,6,8,0,9,0,0,8,3,2,0,4,6,7,9,6,0,1,7,1,7,6,
+1,2,5,3,4,3,8,1,6,3,8,5,5,9,8,5,2,6,0,2,1,4,0,0,5,8,8,6,0,8,5,9,
+9,6,7,8,4,9,6,2,9,4,8,6,1,2,1,4,7,8,7,5,8,2,8,8,0,9,1,6,8,7,0,1,
+3,5,5,0,0,0,6,4,1,1,9,6,6,5,2,7,4,2,0,6,8,4,2,9,1,0,5,9,5,2,8,3,
+2,6,0,3,6,4,3,4,5,7,8,3,1,5,0,6,3,8,9,2,8,2,8,8,8,8,0,6,6,1,9,3,
+8,9,3,8,7,7,5,2,2,7,0,4,0,1,1,4,1,2,7,1,8,9,5,7,9,6,3,1,0,8,1,4,
+6,6,6,6,7,7,4,7,8,8,8,0,7,8,1,2,8,7,0,4,1,7,1,6,1,5,8,9,1,0,7,5,
+3,7,2,3,7,6,5,8,7,5,6,5,3,3,3,3,8,4,7,3,0,2,0,0,0,5,9,9,3,2,4,8,
+5,2,9,1,0,8,4,4,7,4,9,3,9,3,5,0,4,4,5,9,9,5,7,7,7,7,0,1,8,7,7,3,
+8,0,4,2,1,7,3,0,4,8,0,2,6,1,4,9,1,0,2,4,2,8,6,1,5,0,4,0,5,6,2,3,
+5,6,8,5,0,5,4,2,8,6,0,5,4,1,3,9,5,0,6,7,1,4,8,2,5,3,4,5,4,0,7,7,
+1,2,9,1,9,2,2,0,8,4,3,9,2,7,3,2,7,7,5,1,1,7,3,9,8,8,9,1,5,1,7,3,
+4,7,8,2,3,8,2,3,7,4,0,5,0,1,4,1,3,8,8,6,6,3,8,9,0,0,5,9,0,1,1,5,
+2,9,2,2,0,1,9,4,6,1,7,5,0,1,1,3,9,6,1,4,4,9,2,8,1,3,0,4,0,6,9,6,
+6,2,2,1,2,4,3,0,6,7,8,4,0,7,3,7,1,1,7,6,8,1,7,5,7,7,7,7,9,3,9,5,
+8,0,9,5,9,2,4,5,6,7,8,5,9,3,2,7,4,8,0,7,1,4,4,1,4,0,4,5,7,4,0,1,
+1,9,4,6,3,6,0,8,2,0,4,0,9,5,6,3,4,9,0,0,5,3,2,8,3,2,4,5,9,6,9,7,
+1,9,9,4,4,6,0,1,2,6,3,0,2,0,1,4,0,0,8,4,1,3,4,6,7,5,3,6,2,0,2,9,
+7,9,6,5,4,4,4,0,5,8,6,5,9,6,0,6,6,9,9,9,2,7,6,1,7,0,2,0,7,8,8,4,
+3,1,9,6,2,5,0,5,4,3,8,3,3,9,2,7,8,7,1,3,6,7,1,6,5,3,0,6,9,4,1,3,
+8,5,0,0,4,3,2,2,4,5,8,0,9,1,5,3,5,9,5,6,7,6,7,5,6,1,1,6,4,8,2,5,
+9,6,3,7,2,6,0,1,0,9,0,2,7,2,6,1,8,0,0,3,3,5,5,1,6,4,0,8,7,9,0,2,
+6,7,9,2,5,1,2,5,3,8,0,1,4,4,9,4,2,6,6,6,2,7,5,2,8,6,2,1,5,5,4,9,
+5,4,9,8,7,7,8,0,0,7,9,5,4,8,6,6,1,3,7,8,2,9,0,5,2,6,0,1,8,9,4,2,
+5,7,0,6,8,0,4,2,8,7,4,2,5,4,8,2,7,7,7,8,1,6,6,8,4,5,6,3,2,7,5,4,
+9,4,1,7,6,0,1,3,3,7,2,3,6,7,5,4,3,2,3,5,7,2,3,1,8,1,7,2,3,6,6,8,
+5,8,8,4,8,5,1,5,8,4,6,4,6,0,6,5,7,7,1,1,7,7,4,5,8,4,0,7,2,3,6,9,
+2,3,9,0,0,6,2,8,1,4,0,8,5,5,6,2,1,0,2,1,7,3,1,9,7,6,8,8,0,3,1,4,
+1,3,9,6,2,6,3,7,3,4,1,8,5,0,3,1,0,3,5,5,7,4,2,5,1,4,3,5,4,8,5,5,
+2,9,0,3,0,8,1,0,0,7,3,9,1,7,9,8,0,2,7,0,8,2,0,9,9,3,7,9,7,9,0,8,
+2,8,9,6,9,4,7,8,3,0,4,8,0,0,1,1,3,0,9,0,3,6,6,3,2,2,5,8,0,3,4,2,
+8,9,0,2,3,4,7,5,0,8,1,1,3,5,5,6,8,0,7,5,7,0,8,3,4,7,4,2,2,6,6,0,
+4,8,8,4,0,9,2,5,9,0,6,9,6,9,7,0,3,2,4,2,0,7,6,9,5,8,0,2,7,7,1,6,
 };
 
 const int32_t C[] = {
-1223,1282,1286,1163,1319,1270,1192,1100,1142,1261,1291,1367,1260,1311,985,1232,1313,1316,1148,1320,1277,1275,1145,1199,1157,1203,1225,1211,1177,1281,1164,1239,1209,1454,1377,1145,1189,1335,1306,1108,1302,1233,1421,1194,1339,1065,1322,1063,1169,979,1109,1155,976,1341,1258,1173,1250,1486,1204,1322,1273,1303,1130,1377,
-1184,1267,1312,1237,1443,1455,1188,1232,1260,1222,1312,1451,1244,1331,1078,1464,1396,1375,1279,1437,1466,1272,1208,1262,1248,1352,1314,1335,1209,1309,1263,1277,1264,1509,1546,1222,1369,1428,1334,1090,1392,1323,1378,1303,1411,1190,1443,1195,1305,1244,1177,1218,1132,1317,1370,1300,1356,1338,1210,1421,1310,1349,1236,1435,
-1162,1146,1395,1317,1216,1378,1119,1124,1091,1251,1202,1479,1236,1287,1005,1364,1472,1348,1223,1445,1362,1273,1148,1252,1226,1323,1226,1294,1205,1235,1192,1299,1135,1351,1441,1303,1192,1422,1313,1142,1138,1213,1390,1262,1400,1148,1242,1149,1390,1197,1230,1127,1164,1269,1347,1231,1377,1294,1109,1386,1400,1285,1202,1375,
-1085,1269,1161,1032,1288,1306,1093,1075,1208,1217,1133,1354,1087,1180,994,1148,1230,1282,1151,1255,1213,1176,1122,1190,1027,1230,1284,1184,1022,1073,1237,1162,1222,1300,1273,1038,1101,1271,1263,1053,1266,1276,1277,1185,1288,1092,1256,1066,1070,1100,1139,1110,1041,1201,1214,1307,1153,1334,1146,1282,1220,1292,1202,1281,
-953,1262,1262,1113,1165,1134,1165,1034,1155,1150,1092,1340,1127,1129,991,1264,1190,1241,1146,1305,1178,1086,1038,1146,925,1348,1187,1146,1084,1170,1147,1201,1109,1331,1327,1101,1191,1195,1240,1088,1269,1097,1275,1367,1394,1097,1289,1092,1121,1008,1014,1078,1185,1328,1277,1274,1192,1304,1097,1331,1288,1287,1139,1227,
-1201,1282,1518,1325,1281,1510,1265,1336,1105,1327,1407,1443,1225,1295,1066,1483,1340,1349,1354,1403,1371,1315,1151,1265,1189,1335,1343,1363,1137,1399,1248,1254,1465,1378,1333,1240,1131,1468,1371,1139,1253,1175,1496,1213,1473,1246,1402,1272,1330,1226,1126,1186,1212,1376,1462,1329,1229,1447,1227,1339,1347,1301,1240,1524,
-1377,1419,1524,1328,1441,1503,1332,1263,1372,1402,1486,1771,1459,1449,1219,1424,1629,1493,1295,1539,1427,1451,1453,1399,1276,1583,1497,1480,1279,1354,1389,1403,1376,1571,1552,1346,1348,1654,1440,1173,1324,1504,1554,1499,1542,1332,1499,1277,1431,1402,1203,1382,1206,1560,1479,1448,1313,1516,1372,1582,1508,1404,1374,1553,
-1180,1190,1170,1150,1253,1280,1261,1120,1132,1291,1259,1295,1148,1178,936,1279,1199,1307,1136,1266,1352,1219,1137,1104,1051,1323,1299,1210,1202,1416,1149,1190,1192,1345,1331,1059,1264,1186,1238,1078,1212,1136,1433,1338,1238,1081,1314,980,1253,1209,1241,996,1074,1264,1301,1235,1360,1275,1076,1355,1130,1254,1272,1195,
-1159,1328,1348,1187,1256,1466,1220,1187,1064,1249,1357,1457,1216,1173,1179,1494,1289,1263,1350,1375,1310,1373,1248,1356,1142,1296,1226,1265,1158,1135,1179,1185,1210,1338,1376,1222,1213,1348,1378,1129,1272,1097,1444,1236,1363,1248,1324,1170,1316,1302,1266,1319,1195,1216,1356,1352,1313,1320,1173,1359,1298,1234,1253,1485,
-1134,1192,1510,1136,1287,1364,1271,1096,1336,1308,1148,1414,1194,1245,1032,1431,1381,1276,1130,1384,1336,1264,1240,1175,1239,1336,1183,1249,1064,1289,1208,1102,1247,1302,1428,1224,1265,1470,1235,1161,1156,1305,1444,1343,1369,1177,1340,1132,1237,1177,1092,1239,1110,1324,1379,1318,1259,1278,1188,1466,1312,1262,1205,1355,
-1266,1520,1489,1292,1362,1379,1379,1383,1309,1375,1416,1341,1262,1346,1139,1468,1367,1283,1245,1376,1341,1328,1405,1194,1162,1568,1256,1316,1109,1523,1281,1251,1550,1493,1500,1225,1303,1342,1463,1098,1279,1224,1440,1471,1384,1199,1433,1338,1395,1243,1313,1311,1093,1536,1311,1466,1223,1480,1327,1313,1491,1332,1396,1461,
-1324,1267,1330,1251,1403,1288,1188,1214,1312,1302,1313,1591,1341,1331,1203,1456,1421,1408,1342,1529,1301,1337,1204,1372,1206,1499,1416,1278,1280,1291,1305,1313,1258,1588,1452,1262,1314,1473,1316,1285,1467,1271,1521,1386,1488,1250,1570,1182,1258,1285,1140,1369,1305,1405,1438,1359,1400,1532,1314,1458,1338,1451,1351,1364,
-1508,1591,1551,1501,1560,1630,1454,1467,1378,1516,1488,1608,1383,1444,1297,1613,1483,1759,1421,1635,1655,1449,1270,1550,1260,1637,1451,1499,1405,1380,1486,1452,1522,1566,1612,1445,1283,1683,1534,1209,1565,1462,1665,1582,1626,1309,1625,1376,1302,1344,1358,1280,1260,1595,1679,1500,1399,1654,1363,1613,1365,1399,1545,1702,
-1128,1402,1315,1329,1340,1389,1269,1399,1237,1236,1196,1382,1177,1206,1166,1486,1421,1321,1176,1538,1402,1373,1244,1194,1180,1494,1352,1365,1053,1302,1324,1224,1425,1421,1437,1106,1273,1479,1411,1069,1432,1156,1353,1414,1474,1224,1352,1368,1351,1155,1216,1164,1160,1468,1376,1301,1283,1407,1340,1365,1333,1314,1222,1562,
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-1238,1391,1654,1282,1535,1583,1349,1371,1349,1438,1396,1503,1400,1483,1352,1670,1451,1452,1393,1511,1507,1553,1343,1431,1373,1456,1367,1364,1333,1462,1290,1251,1432,1511,1557,1338,1462,1445,1472,1429,1484,1300,1658,1546,1579,1316,1561,1295,1411,1270,1516,1399,1360,1430,1484,1458,1469,1569,1336,1635,1471,1468,1405,1548,
-1328,1454,1420,1339,1301,1584,1286,1280,1242,1267,1371,1399,1361,1255,1125,1574,1424,1452,1350,1505,1338,1342,1278,1317,1284,1571,1323,1374,1275,1421,1342,1274,1397,1487,1589,1303,1386,1468,1493,1298,1385,1243,1476,1502,1498,1285,1414,1261,1274,1307,1370,1280,1183,1533,1502,1422,1490,1479,1370,1480,1419,1377,1417,1481,
-1222,1364,1443,1416,1382,1408,1431,1338,1335,1312,1306,1510,1331,1404,1159,1485,1364,1526,1255,1513,1490,1320,1246,1408,1261,1466,1481,1469,1303,1305,1353,1331,1239,1519,1619,1349,1219,1522,1492,1206,1306,1366,1531,1346,1561,1139,1528,1252,1285,1321,1207,1237,1181,1438,1533,1434,1404,1478,1258,1462,1425,1431,1400,1589,
-1207,1377,1473,1278,1359,1422,1204,1284,1197,1383,1316,1329,1130,1287,1145,1371,1422,1446,1296,1427,1422,1393,1162,1300,1248,1385,1149,1205,1164,1347,1224,1188,1328,1362,1530,1244,1269,1378,1281,1228,1304,1222,1561,1470,1516,1302,1417,1272,1254,1233,1184,1200,1226,1510,1500,1344,1353,1468,1197,1424,1285,1343,1358,1503,
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-1276,1309,1326,1354,1357,1323,1325,1275,1202,1251,1403,1463,1174,1212,1064,1536,1341,1326,1305,1491,1351,1375,1168,1253,1217,1436,1278,1363,1195,1441,1184,1246,1358,1420,1478,1120,1412,1381,1337,1141,1416,1238,1449,1368,1412,1217,1425,1182,1378,1282,1199,1218,1140,1381,1329,1357,1345,1478,1152,1357,1294,1417,1230,1416,
-1071,1204,1308,1204,1446,1269,1175,1132,1209,1188,1315,1368,1169,1283,1042,1331,1380,1409,1113,1452,1307,1186,1166,1205,1120,1335,1265,1279,1207,1236,1194,1144,1336,1483,1401,1154,1251,1352,1293,1073,1423,1138,1343,1257,1280,1237,1323,1077,1118,1105,1228,1177,1158,1301,1205,1194,1234,1343,1162,1376,1295,1242,1234,1213,
+626,710,934,522,553,696,511,517,688,718,560,731,575,571,626,583,521,524,662,600,565,671,612,693,694,657,622,732,588,660,550,698,
+616,645,731,564,502,644,490,470,667,680,719,509,583,616,528,565,548,587,556,617,536,654,521,680,566,627,474,602,672,664,614,628,
+701,813,830,551,536,751,510,601,719,675,721,610,631,579,569,570,606,679,645,612,779,749,676,890,664,603,515,742,656,698,698,702,
+673,881,915,687,647,702,579,576,754,709,789,684,600,648,575,664,622,678,731,631,648,805,630,737,716,692,479,726,688,747,760,836,
+493,654,551,399,352,537,342,336,499,559,464,494,484,465,473,479,398,425,518,466,503,526,468,623,559,434,430,509,488,560,520,562,
+625,851,830,548,496,693,490,583,639,664,687,682,589,513,521,598,531,611,675,586,688,664,594,830,679,582,483,784,622,671,557,745,
+746,716,855,542,589,661,488,508,667,781,628,601,617,576,599,603,697,587,635,644,637,632,648,686,710,667,571,720,680,664,567,624,
+640,762,784,595,601,662,430,512,653,719,658,591,652,581,566,638,583,671,577,578,624,729,578,793,695,523,528,718,668,672,634,713,
+673,794,767,596,609,711,493,433,701,789,613,562,653,555,595,576,587,654,660,624,637,731,617,769,749,629,545,652,535,687,691,736,
+725,758,687,581,580,722,448,434,655,794,716,400,654,595,574,595,619,651,617,624,656,676,654,739,697,662,473,674,683,690,671,654,
+623,787,751,530,549,631,508,464,616,730,669,617,566,619,556,646,501,562,667,593,626,632,586,740,705,677,522,637,662,670,687,706,
+778,843,849,634,661,755,579,564,805,872,708,678,679,622,661,669,659,670,813,728,653,681,758,730,743,754,617,740,724,781,696,749,
+571,742,688,522,524,667,442,434,628,696,726,505,585,625,541,546,612,723,571,568,605,671,483,670,627,552,442,688,640,666,691,696,
+624,809,802,541,632,630,606,573,716,672,792,657,615,638,569,581,653,730,637,609,630,718,556,832,627,687,621,756,645,678,746,708,
+795,847,844,662,612,741,523,592,679,882,736,601,790,659,722,695,658,630,689,739,705,754,678,760,788,677,578,801,778,836,680,792,
+594,745,710,520,483,639,508,428,582,620,532,523,502,455,453,498,533,472,594,551,550,639,581,720,547,521,487,571,488,582,605,559,
+602,751,765,526,559,641,439,453,596,658,614,648,522,559,457,576,513,523,618,477,607,692,566,760,714,541,517,650,594,603,599,633,
+764,888,1043,671,739,725,630,545,781,841,819,716,705,662,639,668,693,796,778,776,759,907,690,911,826,722,595,773,667,813,734,792,
+601,788,781,490,467,699,444,383,587,678,580,550,519,506,463,565,505,581,679,575,642,614,608,775,671,576,420,579,569,591,559,603,
+680,776,863,573,549,696,541,441,736,739,698,607,582,499,563,602,649,657,655,676,626,709,659,704,642,641,465,747,612,721,628,718,
+637,807,668,542,482,616,431,388,504,725,456,543,515,500,541,507,510,499,667,556,560,600,569,699,649,579,459,550,550,694,504,590,
+645,722,796,531,548,686,546,505,745,707,698,621,624,625,495,560,716,709,601,627,602,658,568,732,605,629,610,706,580,649,643,637,
+666,766,882,533,548,773,492,482,608,752,593,617,650,506,588,561,497,627,698,601,657,718,652,751,711,610,534,700,635,749,583,672,
+698,754,897,585,547,703,473,574,610,766,590,644,741,610,603,652,624,597,637,642,671,707,625,745,737,581,607,685,730,741,654,670,
+575,751,808,490,472,680,495,468,562,651,700,625,677,663,568,547,503,569,575,575,542,647,501,728,656,590,536,676,629,698,575,648,
+662,763,664,590,513,643,476,457,452,639,616,548,557,477,511,562,506,532,572,527,648,593,514,676,552,499,392,658,616,741,443,555,
+721,837,803,621,577,710,547,501,634,844,592,683,576,537,555,684,602,586,701,658,667,691,607,761,668,585,597,771,623,716,619,709,
+652,692,831,503,477,770,400,407,698,752,659,621,574,604,561,613,554,570,686,599,636,679,684,801,749,628,522,755,730,626,561,674,
+756,877,768,653,637,725,601,597,644,823,769,555,732,625,645,631,709,729,645,679,665,740,595,728,652,645,575,802,676,855,659,728,
+591,730,693,507,594,617,491,434,649,686,622,574,556,495,510,511,502,640,653,571,524,724,555,692,606,543,451,577,510,663,588,662,
+627,749,660,541,495,651,442,399,662,695,583,533,512,588,532,539,598,559,592,538,485,554,589,647,607,624,528,691,574,609,532,664,
+683,909,809,598,581,661,541,501,678,728,621,660,702,562,606,543,666,567,704,625,603,735,670,734,776,657,553,664,576,775,709,741,
 };
 
-#define MATRIX_SIZE 64
+#endif
+#define MATRIX_SIZE 32
 #endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
index 6ed19c0c..6ee5797b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma/main.c
@@ -20,9 +20,9 @@
 #define TEST_ADDRESS_MODE_EXTERNAL_DEVICE
 
 #define TEST_DATA_SIZE 16
-#define TEST_DATA_LARGE 1024
+#define TEST_DATA_LARGE 256
 #define TRANSACTIONS_N 3         // Only possible to perform one transaction at a time, others should be blocked
-#define TEST_WINDOW_SIZE_DU 1024 // if put at <=71 the isr is too slow to react to the interrupt
+#define TEST_WINDOW_SIZE_DU 256 // if put at <=71 the isr is too slow to react to the interrupt
 
 #if TEST_DATA_LARGE < 2 * TEST_DATA_SIZE
 #errors("TEST_DATA_LARGE must be at least 2*TEST_DATA_SIZE")
@@ -112,22 +112,20 @@ dma_data_type_t C_type_2_dma_type(int C_type)
     }                                                                                       \
     if (errors != 0)                                                                        \
     {                                                                                       \
-        PRINTF("DMA failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b); \
+        PRINTF("DMA failure: %d errors out of %d elements checked\n\r", errors, trans.size_d1_du); \
         return EXIT_FAILURE;                                                                \
     }
 
 #define INIT_TEST(signed, data_size, dma_src_type, dma_dst_type) \
     tgt_src.ptr = (uint8_t *)src;                                \
-    tgt_src.inc_du = 1;                                          \
+    tgt_src.inc_d1_du = 1;                                          \
     tgt_src.inc_d2_du = 0;                                       \
-    tgt_src.size_du = data_size;                                 \
     tgt_src.trig = DMA_TRIG_MEMORY;                              \
     tgt_src.type = dma_src_type;                                 \
     tgt_src.env = NULL;                                          \
     tgt_dst.ptr = (uint8_t *)dst;                                \
-    tgt_dst.inc_du = 1;                                          \
+    tgt_dst.inc_d1_du = 1;                                          \
     tgt_dst.inc_d2_du = 0;                                       \
-    tgt_dst.size_du = data_size;                                 \
     tgt_dst.trig = DMA_TRIG_MEMORY;                              \
     tgt_dst.type = dma_dst_type;                                 \
     tgt_dst.env = NULL;                                          \
@@ -136,6 +134,7 @@ dma_data_type_t C_type_2_dma_type(int C_type)
     trans.src_addr = &tgt_addr;                                  \
     trans.src_type = dma_src_type;                               \
     trans.dst_type = dma_dst_type;                               \
+    trans.size_d1_du = data_size;                                \
     trans.mode = DMA_TRANS_MODE_SINGLE;                          \
     trans.win_du = 0;                                            \
     trans.sign_ext = signed;                                     \
@@ -248,8 +247,7 @@ int main(int argc, char *argv[])
     dma_target_t tgt_dst;
     dma_target_t tgt_addr = {
         .ptr = (uint8_t *)test_addr_4B_PTR,
-        .inc_du = 1,
-        .size_du = TEST_DATA_SIZE,
+        .inc_d1_du = 1,
         .trig = DMA_TRIG_MEMORY,
     };
 
@@ -265,20 +263,19 @@ int main(int argc, char *argv[])
 
     // Initialize the DMA for the next tests
     tgt_src.ptr = (uint8_t *)test_data_4B;
-    tgt_src.inc_du = 1;
-    tgt_src.size_du = TEST_DATA_SIZE;
+    tgt_src.inc_d1_du = 1;
     tgt_src.trig = DMA_TRIG_MEMORY;
     tgt_src.type = DMA_DATA_TYPE_WORD;
 
     tgt_dst.ptr = (uint8_t *)copied_data_4B;
-    tgt_dst.inc_du = 1;
-    tgt_dst.size_du = TEST_DATA_LARGE;
+    tgt_dst.inc_d1_du = 1;
     tgt_dst.trig = DMA_TRIG_MEMORY;
     tgt_dst.type = DMA_DATA_TYPE_WORD;
 
     trans.src = &tgt_src;
     trans.dst = &tgt_dst;
     trans.src_addr = &tgt_addr;
+    trans.size_d1_du = TEST_DATA_SIZE;
     trans.src_type = DMA_DATA_TYPE_WORD;
     trans.dst_type = DMA_DATA_TYPE_WORD;
     trans.mode = DMA_TRANS_MODE_SINGLE;
@@ -306,7 +303,7 @@ int main(int argc, char *argv[])
 
     PRINTF(">> Finished transaction. \n\r");
 
-    for (uint32_t i = 0; i < trans.size_b >> 2; i++)
+    for (uint32_t i = 0; i < trans.size_d1_du; i++)
     {
         if (copied_data_4B[i * 2] != test_data_4B[i])
         {
@@ -321,11 +318,10 @@ int main(int argc, char *argv[])
     }
     else
     {
-        PRINTF("DMA address mode failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b);
+        PRINTF("DMA address mode failure: %d errors out of %d elements checked\n\r", errors, trans.size_d1_du);
         return EXIT_FAILURE;
     }
 
-    trans.mode = DMA_TRANS_MODE_SINGLE;
 
 #endif // TEST_ADDRESS_MODE
 
@@ -362,7 +358,7 @@ int main(int argc, char *argv[])
 
     PRINTF(">> Finished transaction. \n\r");
 
-    for (uint32_t i = 0; i < trans.size_b >> 2; i++)
+    for (uint32_t i = 0; i < trans.size_d1_du; i++)
     {
         if (ext_copied_data_4B[i * 2] != test_data_4B[i])
         {
@@ -377,7 +373,7 @@ int main(int argc, char *argv[])
     }
     else
     {
-        PRINTF("DMA address mode in external memory failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b);
+        PRINTF("DMA address mode in external memory failure: %d errors out of %d elements checked\n\r", errors, trans.size_d1_du);
         return EXIT_FAILURE;
     }
 
@@ -400,12 +396,10 @@ int main(int argc, char *argv[])
     }
 
     tgt_src.ptr = (uint8_t *)test_data_large;
-    tgt_src.size_du = TEST_DATA_LARGE;
-    tgt_dst.size_du = TEST_DATA_LARGE;
+    trans.size_d1_du = TEST_DATA_LARGE;
+    trans.mode = DMA_TRANS_MODE_SINGLE;
 
-    // trans.end = DMA_TRANS_END_INTR_WAIT; // This option makes no sense, because the launch is blocking the program until the trans finishes.
     trans.end = DMA_TRANS_END_INTR;
-    // trans.end = DMA_TRANS_END_POLLING;
 
     res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
     PRINTF("tran: %u \t%s\n\r", res, res == DMA_CONFIG_OK ? "Ok!" : "Error!");
@@ -477,7 +471,7 @@ int main(int argc, char *argv[])
     }
 
     tgt_src.ptr = (uint8_t *)test_data_large;
-    tgt_src.size_du = TEST_DATA_LARGE;
+    trans.size_d1_du = TEST_DATA_LARGE;
 
     tgt_src.type = DMA_DATA_TYPE_WORD;
     tgt_dst.type = DMA_DATA_TYPE_WORD;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c
index 0a5651c1..6805defa 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/main.c
@@ -4,6 +4,7 @@
  *  SPDX-License-Identifier: Apache-2.0
  *
  *  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
  *  
  *  Info: Example application of matrix manipulation by exploiting the 2D DMA.
  *        In this code, there are some optional features:
@@ -43,8 +44,8 @@
 /* Parameters */
 
 /* Size of the extracted matrix (including strides on the input, excluding strides on the outputs) */
-#define SIZE_EXTR_D1 10
-#define SIZE_EXTR_D2 10
+#define SIZE_EXTR_D1 3
+#define SIZE_EXTR_D2 3
 
 /* Set strides of the input ad output matrix */
 #define STRIDE_IN_D1 1
@@ -72,6 +73,12 @@
 /* Transposition example def */
 #define TRANSPOSITION_EN 1
 
+/* Enables test format */
+#define TEST_EN 0
+
+/* Define the input datatype */
+typedef uint32_t dma_input_data_type;
+
 /* Pointer increments computation */
 #define SRC_INC_D1 STRIDE_IN_D1
 #define DST_INC_D1 STRIDE_OUT_D1
@@ -131,23 +138,19 @@ int main()
     #if EN_PERF
 
     /* Reset the counter to evaluate the performance of the DMA */
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    timer_cycles_init();
+
     #endif
 
     tgt_src.ptr = (uint8_t *) test_data;
-    tgt_src.inc_du = SRC_INC_D1;
+    tgt_src.inc_d1_du = SRC_INC_D1;
     tgt_src.inc_d2_du = SRC_INC_D2;
-    tgt_src.size_du = SIZE_EXTR_D1;
-    tgt_src.size_d2_du = SIZE_EXTR_D2;
     tgt_src.trig = DMA_TRIG_MEMORY;
     tgt_src.type = DMA_DATA_TYPE;
     
     tgt_dst.ptr = (uint8_t *)  copied_data_2D_DMA;
-    tgt_dst.inc_du = DST_INC_D1;
+    tgt_dst.inc_d1_du = DST_INC_D1;
     tgt_dst.inc_d2_du = DST_INC_D2;
-    tgt_dst.size_du = OUT_D1_PAD_STRIDE;
-    tgt_dst.size_d2_du = OUT_D2_PAD_STRIDE;
     tgt_dst.trig = DMA_TRIG_MEMORY;
     tgt_dst.type = DMA_DATA_TYPE;
 
@@ -159,11 +162,15 @@ int main()
     trans.pad_bottom_du  = BOTTOM_PAD,
     trans.pad_left_du    = LEFT_PAD,
     trans.pad_right_du   = RIGHT_PAD,
+    trans.size_d1_du     = SIZE_EXTR_D1;
+    trans.size_d2_du     = SIZE_EXTR_D2;
     trans.win_du         = 0,
     trans.end            = DMA_TRANS_END_INTR;
-    
+
     dma_init(NULL);
     
+    timer_start();
+    
     #if EN_PERF
 
     res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
@@ -181,7 +188,6 @@ int main()
     #endif
 
     while( ! dma_is_ready(0)) {
-        #if !EN_PERF
         /* Disable_interrupts */
         /* This does not prevent waking up the core as this is controlled by the MIP register */
         
@@ -191,18 +197,16 @@ int main()
             /* From here the core wakes up even if we did not jump to the ISR */
         }
         CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-        #endif
     }
 
     #if EN_PERF    
 
     /* Read the cycles count after the DMA run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+    cycles_dma = timer_stop();
 
     /* Reset the performance counter to evaluate the CPU performance */
-    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    timer_cycles_init();    
+    timer_start();
     #endif
 
     #if EN_VERIF
@@ -266,10 +270,12 @@ int main()
     #if EN_PERF
 
     /* Read the cycles count after the CPU run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
-    PRINTF("DMA cycles: %d\n\r", cycles_dma);
-    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
-    PRINTF("\n\r");
+    cycles_cpu = timer_stop();
+    
+    #if TEST_EN == 0
+    PRINTF("Total number of cycles CPU: [%d]\n\r", cycles_cpu);
+    PRINTF("Total number of cycles DMA: [%d]\n\r", cycles_dma);
+    #endif
 
     #endif
 
@@ -285,11 +291,21 @@ int main()
     }
 
     if (passed) {
-        PRINTF("Success test 0\n\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 0 PASSED!\n\r\n\r");
+        #else
+        PRINTF("0a:%d:0\n\r", cycles_cpu);   
+        PRINTF("0b:%d:0\n\r", cycles_dma);               
+        #endif
     } 
     else 
     {
-        PRINTF("Fail test 0\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 0 FAILED\n\r");
+        #else
+        PRINTF("0a:%d:1\n\r", cycles_cpu); 
+        PRINTF("0b:%d:1\n\r", cycles_dma); 
+        #endif
         return EXIT_FAILURE;
     }
     #endif
@@ -317,20 +333,17 @@ int main()
     #if EN_PERF
 
     /* Reset the counter to evaluate the performance of the DMA */
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    timer_cycles_init();
     #endif
 
     tgt_src.ptr            = (uint8_t *) test_data;
-    tgt_src.inc_du         = SRC_INC_TRSP_D1;
+    tgt_src.inc_d1_du      = SRC_INC_TRSP_D1;
     tgt_src.inc_d2_du      = SRC_INC_TRSP_D2;
-    tgt_src.size_du        = SIZE_EXTR_D1;
-    tgt_src.size_d2_du     = SIZE_EXTR_D2;
     tgt_src.trig           = DMA_TRIG_MEMORY;
     tgt_src.type           = DMA_DATA_TYPE;
 
     tgt_dst.ptr            = (uint8_t *) copied_data_2D_DMA;
-    tgt_dst.inc_du         = DST_INC_D1;
+    tgt_dst.inc_d1_du      = DST_INC_D1;
     tgt_dst.inc_d2_du      = DST_INC_D2;
     tgt_dst.trig           = DMA_TRIG_MEMORY;
 
@@ -343,11 +356,15 @@ int main()
     trans.pad_left_du    = LEFT_PAD;
     trans.pad_right_du   = RIGHT_PAD;
     trans.dim_inv        = TRANSPOSITION_EN;
+    trans.size_d1_du     = SIZE_EXTR_D1;
+    trans.size_d2_du     = SIZE_EXTR_D2;
     trans.win_du         = 0,
     trans.end            = DMA_TRANS_END_INTR;
     
     dma_init(NULL);
     
+    timer_start();
+    
     #if EN_PERF
 
     res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
@@ -365,7 +382,6 @@ int main()
     #endif
 
     while( ! dma_is_ready(0)) {
-        #if !EN_PERF
         /* Disable_interrupts */
         /* This does not prevent waking up the core as this is controlled by the MIP register */
         
@@ -375,18 +391,16 @@ int main()
             /* From here the core wakes up even if we did not jump to the ISR */
         }
         CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-        #endif
     }
 
     #if EN_PERF    
 
     /* Read the cycles count after the DMA run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+    cycles_dma = timer_stop();
 
     /* Reset the performance counter to evaluate the CPU performance */
-    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    timer_cycles_init();
+    timer_start();
     #endif
 
     #if EN_VERIF
@@ -450,10 +464,11 @@ int main()
     #if EN_PERF
 
     /* Read the cycles count after the CPU run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
-    PRINTF("DMA cycles: %d\n\r", cycles_dma);
-    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
-    PRINTF("\n\r");
+    cycles_cpu = timer_stop();
+    #if TEST_EN == 0
+    PRINTF("Total number of cycles CPU: [%d]\n\r", cycles_cpu);
+    PRINTF("Total number of cycles DMA: [%d]\n\r", cycles_dma);
+    #endif
 
     #endif
 
@@ -469,11 +484,21 @@ int main()
     }
 
     if (passed) {
-        PRINTF("Success test 1\n\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 1 PASSED!\n\r\n\r");
+        #else
+        PRINTF("1a:%d:0\n\r", cycles_cpu);  
+        PRINTF("1b:%d:0\n\r", cycles_dma);                
+        #endif
     } 
     else 
     {
-        PRINTF("Fail test 1\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 1 FAILED\n\r");
+        #else
+        PRINTF("1a:%d:1\n\r", cycles_cpu);
+        PRINTF("1b:%d:1\n\r", cycles_dma);  
+        #endif
         return EXIT_FAILURE;
     }
     #endif
@@ -496,20 +521,17 @@ int main()
     #if EN_PERF
 
     /* Reset the counter to evaluate the performance of the DMA */
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    timer_cycles_init();
     #endif
 
     tgt_src.ptr            = (uint8_t *) test_data;
-    tgt_src.inc_du         = SRC_INC_D1;
-    tgt_src.size_du        = SIZE_EXTR_D1;
+    tgt_src.inc_d1_du      = SRC_INC_D1;
     tgt_src.inc_d2_du      = 0;
-    tgt_src.size_d2_du     = 0;
     tgt_src.trig           = DMA_TRIG_MEMORY;
     tgt_src.type           = DMA_DATA_TYPE;
 
     tgt_dst.ptr            = (uint8_t *) copied_data_1D_DMA;
-    tgt_dst.inc_du         = DST_INC_D1;
+    tgt_dst.inc_d1_du      = DST_INC_D1;
     tgt_dst.inc_d2_du      = 0;
     tgt_dst.trig           = DMA_TRIG_MEMORY;
 
@@ -523,9 +545,13 @@ int main()
     trans.pad_right_du   = RIGHT_PAD;
     trans.dim_inv        = 0;
     trans.win_du         = 0;
+    trans.size_d1_du     = SIZE_EXTR_D1;
+    trans.size_d2_du     = 0;
     trans.end            = DMA_TRANS_END_INTR;
 
     dma_init(NULL);
+
+    timer_start();
     
     #if EN_PERF
 
@@ -544,7 +570,6 @@ int main()
     #endif
 
     while( ! dma_is_ready(0)) {
-        #if !EN_PERF
         /* Disable_interrupts */
         
         CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
@@ -552,18 +577,16 @@ int main()
             wait_for_interrupt();
         }
         CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-        #endif
     }
 
     #if EN_PERF
 
     /* Read the cycles count after the DMA run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+    cycles_dma = timer_stop();
 
     /* Reset the performance counter to evaluate the CPU performance */
-    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    timer_cycles_init();
+    timer_start();
     #endif
 
     #if EN_VERIF
@@ -605,11 +628,12 @@ int main()
     #if EN_PERF
 
     /* Read the cycles count after the CPU run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+    cycles_cpu = timer_stop();
+    #if TEST_EN == 0
+    PRINTF("Total number of cycles CPU: [%d]\n\r", cycles_cpu);
+    PRINTF("Total number of cycles DMA: [%d]\n\r", cycles_dma);
+    #endif
 
-    PRINTF("DMA cycles: %d\n\r", cycles_dma);
-    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
-    PRINTF("\n\r");
     #endif
 
     #if EN_VERIF
@@ -622,11 +646,21 @@ int main()
     }
 
     if (passed) {
-        PRINTF("Success test 2\n\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 2 PASSED!\n\r\n\r");
+        #else
+        PRINTF("2a:%d:0\n\r", cycles_cpu);  
+        PRINTF("2b:%d:0\n\r", cycles_dma);                
+        #endif
     } 
     else 
     {
-        PRINTF("Fail test 2\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 2 FAILED\n\r");
+        #else
+        PRINTF("2a:%d:1\n\r", cycles_cpu);
+        PRINTF("2b:%d:1\n\r", cycles_dma);  
+        #endif
         return EXIT_FAILURE;
     }
     #endif
@@ -655,13 +689,14 @@ int main()
     #if EN_PERF
 
     /* Reset the counter to evaluate the performance of the DMA */
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    timer_cycles_init();
     #endif
 
     /* The DMA is initialized (i.e. Any current transaction is cleaned.) */
     dma_init(NULL);
 
+    timer_start();
+
     /* Enable the DMA interrupt logic */
     write_register( 0x1,
                     DMA_INTERRUPT_EN_REG_OFFSET,
@@ -731,25 +766,25 @@ int main()
                     peri );
 
     /* Padding configuration */
-    write_register( TOP_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+    write_register( TOP_PAD,
                     DMA_PAD_TOP_REG_OFFSET,
                     DMA_PAD_TOP_PAD_MASK,
                     DMA_PAD_TOP_PAD_OFFSET,
                     peri );
 
-    write_register( RIGHT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+    write_register( RIGHT_PAD,
                     DMA_PAD_RIGHT_REG_OFFSET,
                     DMA_PAD_RIGHT_PAD_MASK,
                     DMA_PAD_RIGHT_PAD_OFFSET,
                     peri );
 
-    write_register( LEFT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+    write_register( LEFT_PAD,
                     DMA_PAD_LEFT_REG_OFFSET,
                     DMA_PAD_LEFT_PAD_MASK,
                     DMA_PAD_LEFT_PAD_OFFSET,
                     peri );
 
-    write_register( BOTTOM_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+    write_register( BOTTOM_PAD,
                     DMA_PAD_BOTTOM_REG_OFFSET,
                     DMA_PAD_BOTTOM_PAD_MASK,
                     DMA_PAD_BOTTOM_PAD_OFFSET,
@@ -757,20 +792,19 @@ int main()
 
     /* Set the sizes */
 
-    write_register( SIZE_EXTR_D2 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+    write_register( SIZE_EXTR_D2,
                     DMA_SIZE_D2_REG_OFFSET,
                     DMA_SIZE_D2_SIZE_MASK,
                     DMA_SIZE_D2_SIZE_OFFSET,
                     peri );
 
-    write_register( SIZE_EXTR_D1 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+    write_register( SIZE_EXTR_D1,
                     DMA_SIZE_D1_REG_OFFSET,
                     DMA_SIZE_D1_SIZE_MASK,
                     DMA_SIZE_D1_SIZE_OFFSET,
                     peri );
 
     while( ! dma_is_ready(0)) {
-        #if !EN_PERF
         /* Disable_interrupts */
         /* This does not prevent waking up the core as this is controlled by the MIP register */
         
@@ -780,18 +814,16 @@ int main()
             /* From here the core wakes up even if we did not jump to the ISR */
         }
         CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
-        #endif
     }
 
     #if EN_PERF
 
     /* Read the cycles count after the DMA run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+    cycles_dma = timer_stop();
 
     /* Reset the performance counter to evaluate the CPU performance */
-    CSR_SET_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-    CSR_WRITE(CSR_REG_MCYCLE, 0);
-    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    timer_cycles_init();
+    timer_start();
     #endif
 
     #if EN_VERIF
@@ -856,35 +888,42 @@ int main()
     #if EN_PERF
 
     /* Read the cycles count after the CPU run */
-    CSR_READ(CSR_REG_MCYCLE, &cycles_cpu);
+    cycles_cpu = timer_stop();
+    #if TEST_EN == 0
+    PRINTF("Total number of cycles CPU: [%d]\n\r", cycles_cpu);
+    PRINTF("Total number of cycles DMA: [%d]\n\r", cycles_dma);
+    #endif
 
-    PRINTF("DMA cycles: %d\n\r", cycles_dma);
-    PRINTF("CPU cycles: %d \n\r", cycles_cpu);
-    PRINTF("\n\r");
     #endif
 
     #if EN_VERIF
     
     /* Verify that the DMA and the CPU outputs are the same */
-    for (int i = 0; i < OUT_D2_PAD_STRIDE; i++) {
-        for (int j = 0; j < OUT_D1_PAD_STRIDE; j++) {
-            if (copied_data_2D_DMA[i * OUT_D1_PAD_STRIDE + j] != copied_data_2D_CPU[i * OUT_D1_PAD_STRIDE + j]) {
-                passed = 0;
-            }
-        }
-    }
-
     if (passed) {
-        PRINTF("Success test 3\n\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 3 PASSED!\n\r\n\r");
+        #else
+        PRINTF("3a:%d:0\n\r", cycles_cpu);  
+        PRINTF("3b:%d:0\n\r", cycles_dma);                
+        #endif
     } 
     else 
     {
-        PRINTF("Fail test 3\n\r");
+        #if TEST_EN == 0
+        PRINTF("TEST 3 FAILED\n\r");
+        #else
+        PRINTF("3a:%d:1\n\r", cycles_cpu);
+        PRINTF("3b:%d:1\n\r", cycles_dma);  
+        #endif
         return EXIT_FAILURE;
     }
     #endif
 
     #endif
 
+    #if TEST_EN
+    PRINTF("&\n\r");
+    #endif
+
     return EXIT_SUCCESS;
 }
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h
index d1232223..66dcc52a 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_2d/test_data.h
@@ -5,12 +5,7 @@
 #define SIZE_IN_D2 25
 #define DMA_DATA_TYPE DMA_DATA_TYPE_WORD
 
-/* Change the input datatype depending on the DMA_DATA_TYPE
- * The test data has been generated using byte as datatype, so it's possible to use both uint8_t, uint16_t and uint32_t
- */
-typedef uint32_t dma_input_data_type;
-
-dma_input_data_type test_data[SIZE_IN_D1 * SIZE_IN_D2] = {
+uint32_t test_data[SIZE_IN_D1 * SIZE_IN_D2] = {
     93 ,178 ,28 ,23 ,5 ,231 ,211 ,236 ,45 ,196 ,55 ,124 ,113 ,188 ,36 ,43 ,147 ,111 ,254 ,126 ,145 ,83 ,77 ,7 ,126,
     92 ,179 ,157 ,41 ,64 ,7 ,105 ,93 ,176 ,196 ,171 ,42 ,251 ,175 ,120 ,63 ,134 ,56 ,233 ,0 ,189 ,133 ,71 ,226 ,9,
     252 ,214 ,243 ,177 ,205 ,75 ,100 ,165 ,160 ,42 ,112 ,71 ,238 ,208 ,62 ,1 ,113 ,87 ,116 ,212 ,107 ,165 ,214 ,239 ,151,
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c
index e73f84af..24d8429c 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_external/main.c
@@ -51,20 +51,19 @@ int main(int argc, char *argv[])
 
     static dma_target_t tgt_src = {
                                 .ptr        = test_data,
-                                .inc_du     = 1,
-                                .size_du    = TEST_DATA_SIZE,
+                                .inc_d1_du     = 1,
                                 .trig       = DMA_TRIG_MEMORY,
                                 .type       = DMA_DATA_TYPE_WORD,
                                 };
     static dma_target_t tgt_dst = {
                                 .ptr        = copied_data,
-                                .inc_du     = 1,
-                                .size_du    = TEST_DATA_SIZE,
+                                .inc_d1_du     = 1,
                                 .trig       = DMA_TRIG_MEMORY,
                                 };
     static dma_trans_t trans = {
                                 .src        = &tgt_src,
                                 .dst        = &tgt_dst,
+                                .size_d1_du    = TEST_DATA_SIZE,
                                 .mode       = DMA_TRANS_MODE_SINGLE,
                                 .win_du      = 0,
                                 .end        = DMA_TRANS_END_INTR,
@@ -94,7 +93,7 @@ int main(int argc, char *argv[])
     }
     PRINTF(">> Finished transaction. \n\r");
 
-    for(uint32_t i = 0; i < trans.size_b; i++ ) {
+    for(uint32_t i = 0; i < trans.size_d1_du; i++ ) {
         if ( ((uint8_t*)copied_data)[i] != ((uint8_t*)test_data)[i] ) {
             PRINTF("ERROR [%d]: %04x != %04x\n\r", i, ((uint8_t*)copied_data)[i], ((uint8_t*)test_data)[i]);
             errors++;
@@ -105,7 +104,7 @@ int main(int argc, char *argv[])
         PRINTF("External DMA success\n\r");
         return EXIT_SUCCESS;
     } else {
-        PRINTF("External DMA failure: %d errors out of %d bytes checked\n\r", errors, trans.size_b );
+        PRINTF("External DMA failure: %d errors out of %d elements checked\n\r", errors, trans.size_d1_du );
         return EXIT_FAILURE;
     }
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c
index 2e7f2bc8..8bff88ba 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_dma_multichannel/main.c
@@ -4,6 +4,7 @@
  *  SPDX-License-Identifier: Apache-2.0
  *
  *  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
  *  
  *  Info: Example application of matrix manipulation by exploiting the multichannel feature of the DMA subsystem.
  *        This code is capable of testing the following features:
@@ -32,7 +33,7 @@
  * 
  *  DISCLAIMER:
  *  When using the default memory configuration (64kB), pay attention to the dimensions of the output matrices.
- *  When executing TEST_ID_4 on QuestaSim, make sure to enable the SPI FLASH.
+ *  When executing TEST_ID_3 on QuestaSim, make sure to enable the SPI FLASH.
  * 
  *  Enable one or more of the following tests by defining the correct TEST_ID_* macro:
  *  
@@ -136,7 +137,7 @@
 
 #if TARGET_SIM && PRINTF_IN_SIM
         #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-#elif TARGET_IS_FPGA && PRINTF_IN_FPGA
+#elif TARGET_PYNQ_Z2 && PRINTF_IN_FPGA
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
 #else
     #define PRINTF(...)
@@ -333,25 +334,25 @@ int main()
                         dma_peri(i) );
         
         /* Padding configuration */
-        write_register( TOP_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+        write_register( TOP_PAD,
                         DMA_PAD_TOP_REG_OFFSET,
                         DMA_PAD_TOP_PAD_MASK,
                         DMA_PAD_TOP_PAD_OFFSET,
                         dma_peri(i) );
         
-        write_register( RIGHT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+        write_register( RIGHT_PAD,
                         DMA_PAD_RIGHT_REG_OFFSET,
                         DMA_PAD_RIGHT_PAD_MASK,
                         DMA_PAD_RIGHT_PAD_OFFSET,
                         dma_peri(i) );
         
-        write_register( LEFT_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+        write_register( LEFT_PAD,
                         DMA_PAD_LEFT_REG_OFFSET,
                         DMA_PAD_LEFT_PAD_MASK,
                         DMA_PAD_LEFT_PAD_OFFSET,
                         dma_peri(i) );
         
-        write_register( BOTTOM_PAD * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+        write_register( BOTTOM_PAD,
                         DMA_PAD_BOTTOM_REG_OFFSET,
                         DMA_PAD_BOTTOM_PAD_MASK,
                         DMA_PAD_BOTTOM_PAD_OFFSET,
@@ -368,13 +369,13 @@ int main()
     for (int i=0; i<DMA_CH_NUM; i++)
     {
         /* Set the sizes to start the transaction */
-        write_register( SIZE_EXTR_D2 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+        write_register( SIZE_EXTR_D2,
                         DMA_SIZE_D2_REG_OFFSET,
                         DMA_SIZE_D2_SIZE_MASK,
                         DMA_SIZE_D2_SIZE_OFFSET,
                         dma_peri(i) );
         
-        write_register( SIZE_EXTR_D1 * DMA_DATA_TYPE_2_SIZE( DMA_DATA_TYPE),
+        write_register( SIZE_EXTR_D1,
                         DMA_SIZE_D1_REG_OFFSET,
                         DMA_SIZE_D1_SIZE_MASK,
                         DMA_SIZE_D1_SIZE_OFFSET,
@@ -543,22 +544,22 @@ int main()
     dma_init(NULL);
 
     tgt_src.ptr            = (uint8_t *) test_data;
-    tgt_src.inc_du         = SRC_INC_D1;
+    tgt_src.inc_d1_du         = SRC_INC_D1;
     tgt_src.inc_d2_du      = SRC_INC_D2;
-    tgt_src.size_du        = SIZE_EXTR_D1;
-    tgt_src.size_d2_du     = SIZE_EXTR_D2;
     tgt_src.trig           = DMA_TRIG_MEMORY;
     tgt_src.type           = DMA_DATA_TYPE;
 
     for (int c=0; c<DMA_CH_NUM; c++)
     { 
         tgt_dst[c].ptr            = (uint8_t *) copied_data_2D_DMA[c];
-        tgt_dst[c].inc_du         = DST_INC_D1;
+        tgt_dst[c].inc_d1_du         = DST_INC_D1;
         tgt_dst[c].inc_d2_du      = DST_INC_D2;
         tgt_dst[c].trig           = DMA_TRIG_MEMORY;
 
         trans[c].src            = &tgt_src;
         trans[c].dst            = &tgt_dst[c];
+        trans[c].size_d1_du     = SIZE_EXTR_D1;
+        trans[c].size_d2_du     = SIZE_EXTR_D2;
         trans[c].mode           = DMA_TRANS_MODE_SINGLE;
         trans[c].dim            = DMA_DIM_CONF_2D;
         trans[c].pad_top_du     = TOP_PAD;
@@ -754,18 +755,14 @@ int main()
     #endif
 
     tgt_src.ptr            = (uint8_t *) test_data;
-    tgt_src.inc_du         = SRC_INC_D1;
+    tgt_src.inc_d1_du         = SRC_INC_D1;
     tgt_src.inc_d2_du      = SRC_INC_D2;
-    tgt_src.size_du        = SIZE_EXTR_D1;
-    tgt_src.size_d2_du     = SIZE_EXTR_D2;
     tgt_src.trig           = DMA_TRIG_MEMORY;
     tgt_src.type           = DMA_DATA_TYPE;
 
     tgt_src_trsp.ptr            = (uint8_t *) test_data;
-    tgt_src_trsp.inc_du         = SRC_INC_TRSP_D1;
+    tgt_src_trsp.inc_d1_du         = SRC_INC_TRSP_D1;
     tgt_src_trsp.inc_d2_du      = SRC_INC_TRSP_D2;
-    tgt_src_trsp.size_du        = SIZE_EXTR_D1;
-    tgt_src_trsp.size_d2_du     = SIZE_EXTR_D2;
     tgt_src_trsp.trig           = DMA_TRIG_MEMORY;
     tgt_src_trsp.type           = DMA_DATA_TYPE;
 
@@ -777,7 +774,7 @@ int main()
     for (int c=0; c<DMA_CH_NUM; c++)
     { 
         tgt_dst[c].ptr            = (uint8_t *) copied_data_2D_DMA[c];
-        tgt_dst[c].inc_du         = DST_INC_D1;
+        tgt_dst[c].inc_d1_du         = DST_INC_D1;
         tgt_dst[c].inc_d2_du      = DST_INC_D2;
         tgt_dst[c].trig           = DMA_TRIG_MEMORY;
 
@@ -785,6 +782,8 @@ int main()
         {
             trans[c].src            = &tgt_src;
             trans[c].dst            = &tgt_dst[c];
+            trans[c].size_d1_du     = SIZE_EXTR_D1;
+            trans[c].size_d2_du     = SIZE_EXTR_D2;
             trans[c].mode           = DMA_TRANS_MODE_SINGLE;
             trans[c].dim            = DMA_DIM_CONF_2D;
             trans[c].pad_top_du     = TOP_PAD;
@@ -800,6 +799,8 @@ int main()
         {
             trans[c].src            = &tgt_src_trsp;
             trans[c].dst            = &tgt_dst[c];
+            trans[c].size_d1_du     = SIZE_EXTR_D1;
+            trans[c].size_d2_du     = SIZE_EXTR_D2;
             trans[c].mode           = DMA_TRANS_MODE_SINGLE;
             trans[c].dim            = DMA_DIM_CONF_2D;
             trans[c].pad_top_du     = TOP_PAD;
@@ -1058,20 +1059,20 @@ int main()
     dma_init(NULL);
 
     tgt_src.ptr            = (uint8_t *) test_data;
-    tgt_src.inc_du         = SRC_INC_D1;
+    tgt_src.inc_d1_du         = SRC_INC_D1;
     tgt_src.inc_d2_du      = SRC_INC_D2;
-    tgt_src.size_du        = SIZE_EXTR_D1;
-    tgt_src.size_d2_du     = SIZE_EXTR_D2;
     tgt_src.trig           = DMA_TRIG_MEMORY;
     tgt_src.type           = DMA_DATA_TYPE;
 
     tgt_dst[1].ptr            = (uint8_t *) copied_data_2D_DMA[1];
-    tgt_dst[1].inc_du         = DST_INC_D1;
+    tgt_dst[1].inc_d1_du         = DST_INC_D1;
     tgt_dst[1].inc_d2_du      = DST_INC_D2;
     tgt_dst[1].trig           = DMA_TRIG_MEMORY;
 
     trans[1].src            = &tgt_src;
     trans[1].dst            = &tgt_dst[1];
+    trans[1].size_d1_du     = SIZE_EXTR_D1;
+    trans[1].size_d2_du     = SIZE_EXTR_D2;
     trans[1].mode           = DMA_TRANS_MODE_SINGLE;
     trans[1].dim            = DMA_DIM_CONF_2D;
     trans[1].pad_top_du     = TOP_PAD;
@@ -1131,14 +1132,14 @@ int main()
     PRINTF("laun: %u \t%s\n\r", res_launch, res_launch == DMA_CONFIG_OK ?  "Ok!" : "Error!");
     #endif
 
-    /* Wait for CH1 to end */
-    while(!dma_is_ready(1)) {
+    /* Wait for CH0 to end, since the SPI will be slower than the DMA */
+    while(!dma_is_ready(0)) {
         #if !EN_PERF
         /* Disable_interrupts */
         /* This does not prevent waking up the core as this is controlled by the MIP register */
         
         CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
-        if ( dma_is_ready(1) == 0 ) {
+        if ( dma_is_ready(0) == 0 ) {
             wait_for_interrupt();
             /* From here the core wakes up even if we did not jump to the ISR */
         }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/data.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/data.h
new file mode 100644
index 00000000..dc65b63d
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/data.h
@@ -0,0 +1,80 @@
+// This file is automatically generated
+// Type " python datagen.py " in the terminal to generate the data.h file. Configuration parameters can be changed in the datagen.py file.
+
+#ifndef DATA_H_
+#define DATA_H_
+
+#define FFT_LEN 16
+#define DECIMAL_BITS 10
+
+int16_t A[32] = {
+    0xfff6, 0x0008, 0x0000, 0x0003, 0x0000, 0x0000, 0xfff9, 0x0004, 0xfff9, 0xfffe, 0xfffb, 0x0003, 0xffff, 0x0006, 0xfffb, 0x0000, 0xfff8, 0x0009, 0xfffd, 0x0006, 0xfffa, 0x0009, 0x0007, 0xfffa, 0x0009, 0x0000, 0xfff7, 0x0009, 0x0004, 0x0003, 0x0001, 0x0007
+};
+
+int16_t R[32] = {
+    0xffd6, 0x003e, 0x0003, 0x001d, 0xffea, 0x0015, 0xfffe, 0xffe9, 0x0006, 0x0009, 0xffd6, 0x0024, 0xffdc, 0xfffb, 0x000d, 0xffe8, 0x0000, 0x0009, 0xfffe, 0xfff0, 0xfff0, 0x0023, 0xffec, 0x0004, 0xffe2, 0xffec, 0x0018, 0x000d, 0xfffa, 0x0019, 0x000e, 0xffe6
+};
+
+int16_t W_radix2[32] = {
+    0x0400,
+    0x0000,
+    0x03b2,
+    0xfe78,
+    0x02d4,
+    0xfd2c,
+    0x0188,
+    0xfc4e,
+    0x0000,
+    0xfc00,
+    0xfe78,
+    0xfc4e,
+    0xfd2c,
+    0xfd2c,
+    0xfc4e,
+    0xfe78,
+    0xfc00,
+    0x0000,
+    0xfc4e,
+    0x0188,
+    0xfd2c,
+    0x02d4,
+    0xfe78,
+    0x03b2,
+    0x0000,
+    0x0400,
+    0x0188,
+    0x03b2,
+    0x02d4,
+    0x02d4,
+    0x03b2,
+    0x0188
+};
+
+int16_t W_radix4[24] = {
+    0x0400,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x03fb,
+    0xff9c,
+    0x03ec,
+    0xff38,
+    0x03d4,
+    0xfed7,
+    0x03ec,
+    0xff38,
+    0x03b2,
+    0xfe78,
+    0x0353,
+    0xfdc7,
+    0x03d4,
+    0xfed7,
+    0x0353,
+    0xfdc7,
+    0x028a,
+    0xfce8
+};
+
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/datagen.py b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/datagen.py
new file mode 100644
index 00000000..03659f75
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/datagen.py
@@ -0,0 +1,204 @@
+#!/usr/bin/env python
+
+## Copyright 2024 EPFL
+## Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# Author: Francesco Poluzzi
+# This script generates the data.h file for the example_fft application, that contains the FFT input and the golden output.
+# type " python datagen.py " in the terminal from the example_fft application folder to generate the data.h file.
+
+import sys
+import random
+import numpy as np
+
+# CONFIGURABLE PARAMETERS
+SIZE  = 16
+decimal_bits = 10
+seed = 9
+
+def format_matrix(matrix: np.ndarray, name: str) -> str:
+    # Ensure the matrix is int16 (signed 16-bit integer)
+    if matrix.dtype != np.int16:
+        raise ValueError("Input matrix must be of dtype int16")
+    
+    num_bits = matrix.dtype.itemsize * 8
+    array_ctype = "int16_t"
+    
+    # Convert each element to its 2's complement hexadecimal representation
+    rows = []
+    for row in matrix:
+        row = np.atleast_1d(row)  # Ensure row is array-like for iteration
+        # Format each element as a 16-bit signed integer in hex format
+        hex_values = [f"{element if element >= 0 else (1 << num_bits) + element:#06x}" for element in row]
+        rows.append(hex_values)
+
+    # Format the matrix into a C-style array
+    matrix_contents = f"{array_ctype} {name}[{matrix.size}] = {{\n"
+    if len(rows) > 1:
+        matrix_contents += ',\n'.join([f"    {', '.join(row)}" for row in rows])
+    else:
+        matrix_contents += f"    {', '.join(rows[0])}"
+    matrix_contents += '\n};\n\n'
+
+    return matrix_contents
+
+
+def generate_fft_twiddle_factors_radix2(N):
+    # Number of twiddle factors is N
+    num_twiddle_factors = N
+
+    # Generate the angles for the twiddle factors
+    angles = np.linspace(0, -2 * np.pi, num_twiddle_factors, endpoint=False)
+
+    # Compute the real and imaginary parts
+    real_parts = np.cos(angles)
+    imaginary_parts = np.sin(angles)
+
+    # Concatenate real and imaginary parts
+    twiddle_factors = np.empty(2 * num_twiddle_factors)
+    twiddle_factors[0::2] = real_parts
+    twiddle_factors[1::2] = imaginary_parts
+
+    return twiddle_factors
+
+import numpy as np
+
+def generate_fft_twiddle_factors_radix4(N):
+    # Ensure N is divisible by 4 for Radix-4 FFT
+    if N % 4 != 0:
+        raise ValueError("N must be a multiple of 4 for Radix-4 FFT")
+
+    num_twiddle_groups = N // 4
+    angles_k1 = np.linspace(0, -2 * np.pi / N, num_twiddle_groups, endpoint=False)
+    angles_k2 = 2 * angles_k1  # Corresponds to W_N^{2k}
+    angles_k3 = 3 * angles_k1  # Corresponds to W_N^{3k}
+    real_parts_k1 = np.cos(angles_k1)
+    imag_parts_k1 = np.sin(angles_k1)
+    real_parts_k2 = np.cos(angles_k2)
+    imag_parts_k2 = np.sin(angles_k2)
+    real_parts_k3 = np.cos(angles_k3)
+    imag_parts_k3 = np.sin(angles_k3)
+    twiddle_factors = np.empty(6 * num_twiddle_groups)
+    twiddle_factors[0::6] = real_parts_k1
+    twiddle_factors[1::6] = imag_parts_k1
+    twiddle_factors[2::6] = real_parts_k2
+    twiddle_factors[3::6] = imag_parts_k2
+    twiddle_factors[4::6] = real_parts_k3
+    twiddle_factors[5::6] = imag_parts_k3
+
+    return twiddle_factors
+
+
+def write_arr(f, name, arr, ctype, size):
+    f.write("const " + ctype + " " + name + "[2*FFT_LEN] = {\n")
+
+    for row in arr:
+        for elem in row[:-1]:
+            f.write('%d,' % (elem))
+        f.write('%d,\n' % (row[-1]))
+
+    f.write('};\n\n')
+    return
+
+def generate_random_matrix(num_channels, length, decimal_bits):
+    """
+    Generate a random matrix with num_channels rows and length columns.
+    """
+    
+    real_part = np.random.uniform(-0.01, 0.01, (num_channels, length)) #* (2**(-decimal_bits))
+    imag_part = np.random.uniform(-0.01, 0.01, (num_channels, length)) #* (2**(-decimal_bits))
+    
+    matrix = real_part + 1j * imag_part
+    
+    return matrix
+
+def perform_fft(matrix):
+    """
+    Perform FFT on each row of the matrix and return the result matrix.
+    """
+    return np.fft.fft(matrix, axis=1)
+
+def convert_to_fixed_point(matrix, decimal_places=8):
+    """
+    Convert the matrix to fixed-point format with a specified number of decimal bits.
+    Each element in the output matrix is of type 'int16'.
+    """
+    # Scaling factor for conversion
+    scaling_factor = 1 << decimal_places  # 2^decimal_bits (256 for Q1.8 format)
+
+    # Convert to fixed-point representation
+    real_part = np.real(matrix) * scaling_factor
+    imag_part = np.imag(matrix) * scaling_factor
+    
+    # Clip values to ensure they fit within the range of int16
+    real_part = np.clip(real_part, -32768, 32767)
+    imag_part = np.clip(imag_part, -32768, 32767)
+    
+    # Convert to int16
+    real_part = real_part.astype(np.int16)
+    imag_part = imag_part.astype(np.int16)
+    
+    # Combine real and imaginary parts into a single matrix
+    fixed_point_matrix = np.empty((matrix.shape[0], matrix.shape[1] * 2), dtype=np.int16)
+    fixed_point_matrix[:, 0::2] = real_part
+    fixed_point_matrix[:, 1::2] = imag_part
+    
+    return fixed_point_matrix
+
+def convert_to_fixed_point_twiddles(array, decimal_bits=8):
+    # The input 'array' is a 1D array with interleaved real and imaginary parts
+    fixed_point_array = np.empty_like(array, dtype=np.int16)
+
+    # Scale and convert to fixed-point for real and imaginary parts
+    scale_factor = 1 << decimal_bits
+    fixed_point_array = np.round(array * scale_factor).astype(np.int16)
+
+    return fixed_point_array
+
+################################################################################
+f = open('data.h', 'w')
+f.write('// This file is automatically generated\n// Type " python datagen.py " in the terminal to generate the data.h file. Configuration parameters can be changed in the datagen.py file.\n')
+f.write('\n#ifndef DATA_H_\n')
+f.write('#define DATA_H_\n\n')
+
+np.random.seed(seed)
+
+# Generate random input
+input = generate_random_matrix(1, SIZE, decimal_bits)
+
+# Perform FFT
+fft_output = perform_fft(input)
+
+# Comput twiddles
+twiddles_radix2 = generate_fft_twiddle_factors_radix2(SIZE)
+twiddles_radix4 = generate_fft_twiddle_factors_radix4(SIZE)
+
+# Convert FFT result to fixed-point format
+R = convert_to_fixed_point(fft_output, decimal_bits)
+A = convert_to_fixed_point(input, decimal_bits)
+W_radix2 = convert_to_fixed_point_twiddles(twiddles_radix2, decimal_bits)
+W_radix4 = convert_to_fixed_point_twiddles(twiddles_radix4, decimal_bits)
+
+print("Input:")
+print(input)
+print("A (fixed point) :")
+print(A*2**-decimal_bits)
+print("FFT output:")
+print(fft_output)
+print("R (fixed point):")
+print(R*2**-decimal_bits)
+print("Twiddles Radix-2 (fixed point):")
+print([hex(x) for x in W_radix2.flatten()])  # Print in hexadecimal format
+print("Twiddles Radix-4 (fixed point):")
+print([hex(x) for x in W_radix4.flatten()])  # Print in hexadecimal format
+
+f.write('#define FFT_LEN %d\n' % SIZE)
+f.write('#define DECIMAL_BITS %d\n\n' % decimal_bits)
+
+f.write(format_matrix( A, 'A'))
+f.write(format_matrix( R, 'R'))
+f.write(format_matrix( W_radix2, 'W_radix2'))
+f.write(format_matrix( W_radix4, 'W_radix4'))
+
+f.write('#endif')
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/fft.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/fft.h
new file mode 100644
index 00000000..6d079bda
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/fft.h
@@ -0,0 +1,331 @@
+// Copyright 2024 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: fft.h
+// Author: Francesco Poluzzi
+// Date: 04/09/2024
+// Description: FFT-related functions for X-Heep 
+
+#ifndef FFT_H
+#define FFT_H
+
+#include <stdio.h>
+#include <stdint.h>
+#include <math.h>
+#include "data.h"
+
+#define PI 3.14159265358979323846
+
+uint8_t log_floor(uint16_t N, uint8_t base) {
+    if (N == 0) {
+        return 0; // Log of 0 is undefined, return 0 for safety
+    }
+    uint8_t log_val = 0;
+
+    if (base == 2) {
+        while (N >>= 1) { // Right shift by 1 bit (equivalent to dividing by 2)
+            log_val++;
+        }
+    } else if (base == 4) {
+        while (N >= 4) {  // Right shift by 2 bits (equivalent to dividing by 4)
+            N >>= 2;
+            log_val++;
+        }
+    }
+    return log_val;
+}
+
+bool is_power_of(uint16_t N, uint8_t base) {
+    if (N == 0) {
+        return false; 
+    }
+    if (base == 2) {
+        return (N & (N - 1)) == 0;
+    } else if (base == 4) {
+        return (N & (N - 1)) == 0 && (N & 0x5555) != 0;
+    }
+    return false;  
+}
+
+// Function to perform bit reversal based on radix (base)
+uint16_t bit_reversal(uint16_t n, uint8_t num_bits, uint8_t base) {
+    uint16_t result = 0;
+
+    // Calculate the number of bits to shift based on the base
+    uint8_t shiftamt = (base == 2) ? 1 : 2;  // Shift by 1 for Radix-2, by 2 for Radix-4
+    uint16_t mask = base - 1;  // Mask is 1 for Radix-2, 3 for Radix-4
+
+    // Perform the bit reversal by repeatedly shifting and applying the mask
+    for (uint8_t i = 0; i < num_bits; i++) {
+        result <<= shiftamt;    // Shift result to the left by `shiftamt` bits
+        result |= n & mask;     // Add the masked bits from `n` to `result`
+        n >>= shiftamt;         // Shift `n` to the right by `shiftamt` bits
+    }
+
+    return result;
+}
+
+// Function to generate bit-reversed sequence
+void get_bit_reversed_seq(uint16_t *seq, uint16_t N, uint8_t num_bits, uint8_t base) {
+    for (uint16_t i = 0; i < N; i++) {
+        seq[i] = bit_reversal(i, num_bits, base);
+    }
+}
+
+void compute_twiddle_factors_radix2(int16_t* twiddle_factors, uint32_t N, uint8_t decimal_bits) {
+    for (uint16_t j = 0; j < N / 2; j++) {
+        float angle = -2.0 * PI * j / N;
+        twiddle_factors[2 * j] = (int16_t)(cos(angle) * (1 << decimal_bits));   // Real part in Q1.8 format
+        twiddle_factors[2 * j + 1] = (int16_t)(sin(angle) * (1 << decimal_bits)); // Imaginary part in Q1.8 format
+    } 
+}
+
+void compute_twiddle_factors_radix4(int16_t *twiddle_factors, uint16_t N, int16_t decimal_bits) {
+    // Twiddle factor for radix-4 FFT
+    // N is the FFT size, which must be a power of 4
+    // twiddle_factors is the output array where real and imaginary parts are interleaved
+    uint16_t twiddle_count = N / 4; // Radix-4 FFT needs twiddles for N/4 size
+
+    for (uint16_t k = 0; k < twiddle_count; k++) {
+        // Compute the real and imaginary parts of W_N^k = e^(-2*pi*i*k/N)
+        double angle = -2.0 * PI * k / N;
+        double real_part = cos(angle);
+        double imag_part = sin(angle);
+
+        // Convert to fixed-point with the specified number of decimal bits
+        int16_t real_fixed = (int16_t)(real_part * (1 << decimal_bits));
+        int16_t imag_fixed = (int16_t)(imag_part * (1 << decimal_bits));
+
+        // Store the values in the interleaved array
+        twiddle_factors[2 * k] = real_fixed;      // Real part
+        twiddle_factors[2 * k + 1] = imag_fixed;  // Imaginary part
+    }
+}
+
+void __attribute__((noinline, aligned(4))) iterative_FFT_radix2(int16_t *x, int16_t *X, uint16_t N, int16_t *twiddle_factors, int16_t decimal_bits,
+                           int16_t *w_real_fixed, int16_t *w_imag_fixed, int16_t *xrev, int16_t *bit_reversed_seq) {  
+
+    // Perform bit reversal on the input array
+    uint8_t num_bits = log_floor(N, 2);
+
+    for (uint16_t i = 0; i < N; i++) {
+        // Access real and imaginary parts independently
+        xrev[2 * i] = x[2 * bit_reversed_seq[i]];         // Real part
+        xrev[2 * i + 1] = x[2 * bit_reversed_seq[i] + 1]; // Imaginary part
+    }
+
+    // Stage 0 unrolled: simple additions and subtractions
+    for (uint16_t i = 0; i < N; i += 2) {
+        // Access real and imaginary parts for two points independently
+        int16_t a_real = xrev[2 * i];
+        int16_t a_imag = xrev[2 * i + 1];
+        int16_t b_real = xrev[2 * (i + 1)];
+        int16_t b_imag = xrev[2 * (i + 1) + 1];
+
+        // No twiddle factor for the first stage (equivalent to multiplying by 1 + 0j)
+        xrev[2 * i] = a_real + b_real;
+        xrev[2 * i + 1] = a_imag + b_imag;
+        xrev[2 * (i + 1)] = a_real - b_real;
+        xrev[2 * (i + 1) + 1] = a_imag - b_imag;
+    }
+
+    // FFT processing for remaining stages
+    uint16_t stage_count = num_bits;
+    uint16_t twiddle_step = N/2;
+
+    for (uint16_t stage = 1, step = 4; stage < stage_count; stage++, step *= 2) {
+        uint16_t halfstep = step / 2;
+        twiddle_step /= 2;
+
+        for (uint16_t j = 0; j < halfstep; j++) {
+            // Access precomputed twiddle factors from the interleaved array
+            w_real_fixed[j] = twiddle_factors[2 * (j * twiddle_step)];
+            w_imag_fixed[j] = twiddle_factors[2 * (j * twiddle_step) + 1];
+        }
+
+        // Modify the outer loop to increment from 0 to N, increasing by step
+        for (uint16_t i = 0; i < N; i += step) {
+            // Calculate the starting index for this iteration
+            uint16_t idx = i;
+            for (uint16_t j = 0; j < halfstep; j++) {
+                // Butterfly operations - Access real and imag parts independently
+                int16_t a_real = xrev[2 * (idx + j)];
+                int16_t a_imag = xrev[2 * (idx + j) + 1];
+                int16_t b_real = xrev[2 * (idx + j + halfstep)];
+                int16_t b_imag = xrev[2 * (idx + j + halfstep) + 1];
+
+                // Complex multiplication (b * w) using 32-bit intermediate values
+                int32_t temp_real = ((int32_t)b_real * w_real_fixed[j] - (int32_t)b_imag * w_imag_fixed[j]) >> decimal_bits;
+                int32_t temp_imag = ((int32_t)b_real * w_imag_fixed[j] + (int32_t)b_imag * w_real_fixed[j]) >> decimal_bits;
+
+                // Store the results directly in the array, independently for real and imag parts
+                xrev[2 * (idx + j)] = a_real + temp_real;
+                xrev[2 * (idx + j) + 1] = a_imag + temp_imag;
+                xrev[2 * (idx + j + halfstep)] = a_real - temp_real;
+                xrev[2 * (idx + j + halfstep) + 1] = a_imag - temp_imag;
+            }
+        }
+    }
+
+    // Copy the result to output array X
+    for (uint16_t i = 0; i < 2 * N; i++) {
+        X[i] = xrev[i];
+    }
+}
+
+// Radix-4 FFT
+void __attribute__((noinline, aligned(4))) iterative_FFT_radix4(int16_t *x, int16_t *X, uint16_t N, int16_t *twiddle_factors, int16_t *w_real_fixed, int16_t * w_imag_fixed, int16_t *xrev, int8_t decimal_bits, int16_t * bit_reversed_seq) {
+
+    uint16_t stage_count = log_floor(N, 4);  // Radix-4 halves the number of stages
+    uint16_t twiddle_step = N;
+
+    for (uint16_t i = 0; i < N; i++) {
+        xrev[2 * i] = x[2 * bit_reversed_seq[i]];        // Real part
+        xrev[2 * i + 1] = x[2 * bit_reversed_seq[i] + 1]; // Imaginary part
+    }
+
+    // Unroll the first stage: radix-4 butterfly (4 points per butterfly)
+    uint16_t quarterstep = 1;
+    for (uint16_t i = 0; i < N; i += 4) {
+        uint16_t idx = i;
+        // Load the real and imaginary parts for the 4 input points
+        int16_t a_real = xrev[2 * idx];
+        int16_t a_imag = xrev[2 * idx + 1];
+        int16_t b_real = xrev[2 * (idx + quarterstep)];
+        int16_t b_imag = xrev[2 * (idx + quarterstep) + 1];
+        int16_t c_real = xrev[2 * (idx + 2 * quarterstep)];
+        int16_t c_imag = xrev[2 * (idx + 2 * quarterstep) + 1];
+        int16_t d_real = xrev[2 * (idx + 3 * quarterstep)];
+        int16_t d_imag = xrev[2 * (idx + 3 * quarterstep) + 1];
+
+        // Radix-4 butterfly calculations (without twiddle factors)
+        int16_t t0_real = a_real + c_real;
+        int16_t t0_imag = a_imag + c_imag;
+        int16_t t1_real = b_real + d_real;
+        int16_t t1_imag = b_imag + d_imag;
+
+        int16_t t2_real = a_real - c_real;
+        int16_t t2_imag = a_imag - c_imag;
+        int16_t t3_real = b_real - d_real;
+        int16_t t3_imag = b_imag - d_imag;
+
+        // Output without twiddle factors
+        xrev[2 * idx] = t0_real + t1_real;  // Result 1 real part
+        xrev[2 * idx + 1] = t0_imag + t1_imag;  // Result 1 imag part
+
+        xrev[2 * (idx + quarterstep)] = t2_real - t3_imag;  // Result 2 real part
+        xrev[2 * (idx + quarterstep) + 1] = t2_imag + t3_real;  // Result 2 imag part
+
+        xrev[2 * (idx + 2 * quarterstep)] = t0_real - t1_real;  // Result 3 real part
+        xrev[2 * (idx + 2 * quarterstep) + 1] = t0_imag - t1_imag;  // Result 3 imag part
+
+        xrev[2 * (idx + 3 * quarterstep)] = t2_real + t3_imag;  // Result 4 real part
+        xrev[2 * (idx + 3 * quarterstep) + 1] = t2_imag - t3_real;  // Result 4 imag part
+    }
+
+    // Perform the remaining stages
+    for (uint16_t stage = 1, step = 16; stage < stage_count; stage++, step *= 4) {
+        uint16_t quarterstep = step / 4;
+        twiddle_step /= 4;
+
+        // Precompute the twiddle factors for this stage
+        for (uint16_t j = 0; j < quarterstep; j++) {
+            w_real_fixed[j] = twiddle_factors[2 * (j * twiddle_step)];
+            w_imag_fixed[j] = twiddle_factors[2 * (j * twiddle_step) + 1];
+        }
+
+        // Loop over groups of 4 points per butterfly
+        for (uint16_t i = 0; i < N; i += step) {
+            uint16_t idx = i;
+
+            // Perform load, butterfly, and store operations in a single loop
+            for (uint16_t j = 0; j < quarterstep; j++) {
+                // Load the data for the 4 points
+                int16_t a_real = xrev[2 * (idx + j)];
+                int16_t a_imag = xrev[2 * (idx + j) + 1];
+                int16_t b_real = xrev[2 * (idx + j + quarterstep)];
+                int16_t b_imag = xrev[2 * (idx + j + quarterstep) + 1];
+                int16_t c_real = xrev[2 * (idx + j + 2 * quarterstep)];
+                int16_t c_imag = xrev[2 * (idx + j + 2 * quarterstep) + 1];
+                int16_t d_real = xrev[2 * (idx + j + 3 * quarterstep)];
+                int16_t d_imag = xrev[2 * (idx + j + 3 * quarterstep) + 1];
+
+                // Apply twiddle factors to b
+                int16_t tw_b_real = ((int32_t)b_real * w_real_fixed[j] - (int32_t)b_imag * w_imag_fixed[j]) >> decimal_bits;
+                int16_t tw_b_imag = ((int32_t)b_real * w_imag_fixed[j] + (int32_t)b_imag * w_real_fixed[j]) >> decimal_bits;
+
+                int16_t res1_real = a_real + tw_b_real;  // a + Tw(b)
+                int16_t res1_imag = a_imag + tw_b_imag;
+
+                int16_t res2_real = a_real - tw_b_real;  // a - Tw(b)
+                int16_t res2_imag = a_imag - tw_b_imag;
+
+                // Apply twiddle factors to c
+                int16_t tw_c_real = ((int32_t)c_real * w_real_fixed[2 * j] - (int32_t)c_imag * w_imag_fixed[2 * j]) >> decimal_bits;
+                int16_t tw_c_imag = ((int32_t)c_real * w_imag_fixed[2 * j] + (int32_t)c_imag * w_real_fixed[2 * j]) >> decimal_bits;
+
+                int16_t res3_real = a_real + tw_c_real;  // a + Tw(c)
+                int16_t res3_imag = a_imag + tw_c_imag;
+
+                int16_t res4_real = a_real - tw_c_real;  // a - Tw(c)
+                int16_t res4_imag = a_imag - tw_c_imag;
+
+                // Apply twiddle factors to d
+                int16_t tw_d_real = ((int32_t)d_real * w_real_fixed[3 * j] - (int32_t)d_imag * w_imag_fixed[3 * j]) >> decimal_bits;
+                int16_t tw_d_imag = ((int32_t)d_real * w_imag_fixed[3 * j] + (int32_t)d_imag * w_real_fixed[3 * j]) >> decimal_bits;
+
+                // Store the results
+                xrev[2 * (idx + j)] = res1_real;
+                xrev[2 * (idx + j) + 1] = res1_imag;
+                xrev[2 * (idx + j + quarterstep)] = res2_real;
+                xrev[2 * (idx + j + quarterstep) + 1] = res2_imag;
+                xrev[2 * (idx + j + 2 * quarterstep)] = res3_real;
+                xrev[2 * (idx + j + 2 * quarterstep) + 1] = res3_imag;
+                xrev[2 * (idx + j + 3 * quarterstep)] = res4_real;
+                xrev[2 * (idx + j + 3 * quarterstep) + 1] = res4_imag;
+            }
+        }
+    }
+
+    // Copy the result to output array X
+    for (uint16_t i = 0; i < 2 * N; i++) {
+        X[i] = xrev[i];
+    }
+}
+
+#define FIXED_POINT_SCALE (1 << DECIMAL_BITS)  
+
+// Helper function to print the FFT result
+void print_complex_array(int16_t *array, uint16_t N) {
+    for (uint16_t i = 0; i < N; i++) {
+        // Convert fixed-point to decimal by dividing by FIXED_POINT_SCALE
+        int16_t real_part = array[2 * i];
+        int16_t imag_part = array[2 * i + 1];
+
+        // Calculate integer and fractional parts
+        int16_t real_int = real_part / FIXED_POINT_SCALE;
+        int16_t imag_int = imag_part / FIXED_POINT_SCALE;
+
+        // Fractional part needs to be scaled and displayed with leading zeros if necessary
+        int16_t real_frac = (real_part % FIXED_POINT_SCALE) * 1000 / FIXED_POINT_SCALE;
+        int16_t imag_frac = (imag_part % FIXED_POINT_SCALE) * 1000 / FIXED_POINT_SCALE;
+
+        // Adjust the fractional part for negative values, and ensure fractional part is positive
+        if (real_part < 0 && real_frac > 0) {
+            real_frac = 1000 - real_frac;
+        }
+        if (imag_part < 0 && imag_frac > 0) {
+            imag_frac = 1000 - imag_frac;
+        }
+
+        // Print the complex number in the correct format
+        // Use separate handling for real and imaginary signs
+        printf("X[%d] = %c%d.%03d %c %d.%03dj\n", 
+               i, 
+               (real_part < 0) ? '-' : '+', abs(real_int), abs(real_frac),  // Real part
+               (imag_part < 0) ? '-' : '+', abs(imag_int), abs(imag_frac));  // Imaginary part
+    }
+}
+
+#endif // FFT_ITERATIVE_RADIX_2_H
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/main.c
new file mode 100644
index 00000000..2f5ebb2a
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_fft/main.c
@@ -0,0 +1,112 @@
+// Copyright 2024 EPFL 
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// File: main.c
+// Author: Francesco Poluzzi
+// Date: 04/09/2024
+// Description: FFT example for X-Heep
+// Functions for the FFT computation are in fft.h
+// Parameters as FFT_LEN and DECIMAL_BITS can be changed in data.h. To also automate the input and 
+// golden model generation with different parameters, the script datagen.py can be used. 
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <inttypes.h>
+
+#include "data.h"
+#include "x-heep.h"
+#include "timer_sdk.h"
+#include "fft.h"
+
+/* By default, PRINTs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   1
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+// Tolerance for the comparison of the results in fixed point (needs to be adjusted based on the number of decimal bits).
+// The error is due to shifts and roundings in the fixed-point computation.
+#define TOLERANCE 0x000000f 
+
+int16_t  __attribute__((aligned(4))) R_radix_2[2 * FFT_LEN] ;
+int16_t  __attribute__((aligned(4))) R_radix_4[2 * FFT_LEN] ; 
+int16_t  __attribute__((aligned(4))) twiddle_factors_radix2[FFT_LEN]; 
+int16_t  __attribute__((aligned(4))) twiddle_factors_radix4[FFT_LEN]; 
+int16_t  __attribute__((aligned(4))) w_real_fixed[FFT_LEN / 2];
+int16_t  __attribute__((aligned(4))) w_imag_fixed[FFT_LEN / 2];
+int32_t __attribute__((aligned(4))) xrev_32[ FFT_LEN];
+int16_t  __attribute__((aligned(4))) xrev[2* FFT_LEN];
+int16_t  __attribute__((aligned(4))) bit_reversed_seq_radix2[FFT_LEN];
+int16_t  __attribute__((aligned(4))) bit_reversed_seq_radix4[FFT_LEN];
+
+int main(void)
+{
+    uint32_t radix2_cycles, radix4_cycles;
+
+    if(!is_power_of(FFT_LEN, 2)){
+        PRINTF("FFT_LEN must be a power of 2, FFT radix 2 cannot be performed.\n");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("Starting radix 2 FFT\n");
+
+        // precompute twiddle factors for radix-2 FFT
+    compute_twiddle_factors_radix2(twiddle_factors_radix2, FFT_LEN, DECIMAL_BITS);
+
+    // precompute bit reversed sequence
+    get_bit_reversed_seq(bit_reversed_seq_radix2, FFT_LEN, log_floor(FFT_LEN, 2), 2);
+
+    timer_cycles_init();
+    timer_start();
+
+    iterative_FFT_radix2(A, R_radix_2, FFT_LEN, twiddle_factors_radix2, DECIMAL_BITS, w_real_fixed, w_imag_fixed, xrev, bit_reversed_seq_radix2);
+
+    radix2_cycles = timer_stop();
+
+    for(int i = 0; i < 2 * FFT_LEN; i++){
+        if(abs(R_radix_2[i] - R[i] > TOLERANCE)){
+            PRINTF("Error: R_gold[%d] = %x, R_radix_2[%d] = %x\n", i, R[i], i, R_radix_2[i]);
+            return 1;
+        }
+    }
+
+    PRINTF("Radix-2 FFT took %d cycles\n", radix2_cycles);
+
+    if(!is_power_of(FFT_LEN, 4)){
+        PRINTF("FFT_LEN must be a power of 4, FFT radix 4 cannot be performed.\n");
+        return EXIT_FAILURE;
+    }
+
+    PRINTF("Starting radix 4 FFT\n");
+
+    // precompute twiddle factors for radix-4 FFT
+    compute_twiddle_factors_radix4(twiddle_factors_radix4, FFT_LEN, DECIMAL_BITS);
+
+    // precompute bit reversed sequence
+    get_bit_reversed_seq(bit_reversed_seq_radix4, FFT_LEN, log_floor(FFT_LEN, 4), 4);
+
+    timer_cycles_init();
+    timer_start();
+
+    iterative_FFT_radix4(A, R_radix_4, FFT_LEN, twiddle_factors_radix4, w_real_fixed, w_imag_fixed, xrev, DECIMAL_BITS, bit_reversed_seq_radix4);
+    
+    radix4_cycles = timer_stop();
+
+    for(int i = 0; i < 2 * FFT_LEN; i++){
+        if(abs(R_radix_2[i] - R[i] > TOLERANCE)){
+            PRINTF("Error: R_gold[%d] = %x, R_radix_4[%d] = %x\n", i, R[i], i, R_radix_4[i]);
+            return 1;
+        }
+    }   
+
+    PRINTF("Radix-4 FFT took %d cycles\n", radix4_cycles);
+
+    return EXIT_SUCCESS;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c
index 2c7d9a16..cef21ff5 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_i2s/main.c
@@ -128,18 +128,18 @@ void setup()
      // -- DMA CONFIGURATION --
 
     tgt_src.ptr        = I2S_RX_DATA_ADDRESS;
-    tgt_src.inc_du     = 0;
+    tgt_src.inc_d1_du     = 0;
     tgt_src.trig       = DMA_TRIG_SLOT_I2S;
     tgt_src.type       = DMA_DATA_TYPE_WORD;
-    tgt_src.size_du    = AUDIO_DATA_NUM;
 
     tgt_dst.ptr        = audio_data_0;
-    tgt_dst.inc_du     = 1;
+    tgt_dst.inc_d1_du     = 1;
     tgt_dst.trig       = DMA_TRIG_MEMORY;
     tgt_dst.type       = DMA_DATA_TYPE_WORD;
 
     trans.src        = &tgt_src;
     trans.dst        = &tgt_dst;
+    trans.size_d1_du    = AUDIO_DATA_NUM;
     trans.end        = DMA_TRANS_END_INTR;
 
     dma_config_flags_t res;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
index 89cc242b..1afe2e6b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_iffifo/main.c
@@ -130,16 +130,16 @@ int main(int argc, char *argv[]) {
 
     dma_init(NULL);
     tgt_src.ptr        = to_fifo;
-    tgt_src.inc_du     = 1;
+    tgt_src.inc_d1_du     = 1;
     tgt_src.trig       = DMA_TRIG_MEMORY;
     tgt_src.type       = DMA_DATA_TYPE_WORD;
-    tgt_src.size_du    = 6;
 
     tgt_dst.ptr        = IFFIFO_START_ADDRESS + IFFIFO_FIFO_IN_REG_OFFSET;
-    tgt_dst.inc_du     = 0;
+    tgt_dst.inc_d1_du     = 0;
     tgt_dst.trig       = DMA_TRIG_SLOT_EXT_TX;
     tgt_dst.type       = DMA_DATA_TYPE_WORD;
     
+    trans.size_d1_du    = 6;
     trans.src        = &tgt_src;
     trans.dst        = &tgt_dst;
     trans.end        = DMA_TRANS_END_INTR;
@@ -171,16 +171,16 @@ int main(int argc, char *argv[]) {
     
     dma_init(NULL);
     tgt_src.ptr        = IFFIFO_START_ADDRESS + IFFIFO_FIFO_OUT_REG_OFFSET;
-    tgt_src.inc_du     = 0;
+    tgt_src.inc_d1_du     = 0;
     tgt_src.trig       = DMA_TRIG_SLOT_EXT_RX;
     tgt_src.type       = DMA_DATA_TYPE_WORD;
-    tgt_src.size_du    = 4;
 
     tgt_dst.ptr        = from_fifo;
-    tgt_dst.inc_du     = 1;
+    tgt_dst.inc_d1_du     = 1;
     tgt_dst.trig       = DMA_TRIG_MEMORY;
     tgt_dst.type       = DMA_DATA_TYPE_WORD;
 
+    trans.size_d1_du    = 4;
     trans.src        = &tgt_src;
     trans.dst        = &tgt_dst;
     trans.end        = DMA_TRANS_END_INTR;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c
deleted file mode 100644
index 7ffd56bb..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
-   Copyright EPFL contributors.
-  Licensed under the Apache License, Version 2.0, see LICENSE for details.
-  SPDX-License-Identifier: Apache-2.0
-
-  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
-
-  Info: Contains randomly generated input activations and the golden result of the im2col algorithm.
-*/
-
-#include "im2colGolden.h"
-
-const uint32_t input_image_nchw[48] = {
-    13932, 24003, 46802, 9895,
-    46807, 33972, 44507, 1507,
-    14638, 51479, 39560, 22725,
-    38212, 35631, 40479, 39503,
-    53705, 5796, 58640, 51585,
-    45069, 32035, 41983, 18828,
-    22247, 54792, 20499, 6640,
-    20565, 25501, 4154, 2925,
-    43660, 10618, 52141, 45092,
-    46500, 63085, 57079, 16974,
-    52033, 46977, 35992, 6933,
-    3158, 21127, 28588, 61815
-};
-
-const uint32_t golden_im2col_nchw[108] = {
-    0, 0, 0, 0, 33972, 1507, 0, 35631, 39503,
-    0, 0, 0, 46807, 44507, 0, 38212, 40479, 0,
-    0, 24003, 9895, 0, 51479, 22725, 0, 0, 0,
-    13932, 46802, 0, 14638, 39560, 0, 0, 0, 0,
-    0, 0, 0, 0, 32035, 18828, 0, 25501, 2925,
-    0, 0, 0, 45069, 41983, 0, 20565, 4154, 0,
-    0, 5796, 51585, 0, 54792, 6640, 0, 0, 0,
-    53705, 58640, 0, 22247, 20499, 0, 0, 0, 0,
-    0, 0, 0, 0, 63085, 16974, 0, 21127, 61815,
-    0, 0, 0, 46500, 57079, 0, 3158, 28588, 0,
-    0, 10618, 45092, 0, 46977, 6933, 0, 0, 0,
-    43660, 52141, 0, 52033, 35992, 0, 0, 0, 0
-};
-
-const uint32_t input_image_nhwc[48] = {
- 4047, 16986, 10416,
- 22393, 36967, 57252,
- 30217, 40720, 42651,
- 3810, 4754, 56157,
- 44724, 26083, 1010,
- 44426, 14005, 35222,
- 47712, 1887, 65,
- 37412, 50137, 2236,
- 7582, 53150, 12696,
- 24415, 40340, 26558,
- 22643, 14656, 7085,
- 804, 32415, 17930,
- 47706, 3314, 2947,
- 19673, 37744, 24015,
- 55137, 1975, 54009,
- 25888, 50886, 35445
-};
-
-const uint32_t golden_im2col_nhwc[108] = {
- 0, 0, 0, 4047, 0, 0, 0, 16986, 0, 0, 0, 10416,
- 0, 0, 22393, 30217, 0, 0, 36967, 40720, 0, 0, 57252, 42651,
- 0, 0, 3810, 0, 0, 0, 4754, 0, 0, 0, 56157, 0,
- 0, 44724, 0, 7582, 0, 26083, 0, 53150, 0, 1010, 0, 12696,
- 44426, 47712, 24415, 22643, 14005, 1887, 40340, 14656, 35222, 65, 26558, 7085,
- 37412, 0, 804, 0, 50137, 0, 32415, 0, 2236, 0, 17930, 0,
- 0, 47706, 0, 0, 0, 3314, 0, 0, 0, 2947, 0, 0,
- 19673, 55137, 0, 0, 37744, 1975, 0, 0, 24015, 54009, 0, 0,
- 25888, 0, 0, 0, 50886, 0, 0, 0, 35445, 0, 0, 0
-};
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h
deleted file mode 100644
index 27083aad..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2colGolden.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
-   Copyright EPFL contributors.
-  Licensed under the Apache License, Version 2.0, see LICENSE for details.
-  SPDX-License-Identifier: Apache-2.0
-
-  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
-
-  Info: Header file of im2colGolden, contains activations parameters and the prototypes of both input tensors and golden output.
-*/
-
-#ifndef IMAGE_AND_COL_H
-#define IMAGE_AND_COL_H
-
-#include <stdint.h>
-
-// Parameters
-#define IW 4
-#define IH 4
-#define CH 3
-#define FW 2
-#define FH 2
-#define STRIDES 2
-#define PAD 1
-#define BATCH 1
-
-extern const uint32_t input_image_nchw[48];
-extern const uint32_t golden_im2col_nchw[108];
-extern const uint32_t input_image_nhwc[48];
-extern const uint32_t golden_im2col_nhwc[108];
-
-#endif
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.c
new file mode 100644
index 00000000..c6716359
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.c
@@ -0,0 +1,20 @@
+/*
+	Copyright EPFL contributors.
+	Licensed under the Apache License, Version 2.0, see LICENSE for details.
+	SPDX-License-Identifier: Apache-2.0
+*/
+
+#include "im2col_golden.h"
+
+const uint32_t golden_im2col_nchw[225] = {
+ 0, 0, 0, 0, 0, 0, 45280, 44040, 39555, 48322, 0, 46986, 61580, 31407, 53015, 0, 48311, 52851, 12647, 34880, 0, 1708, 38684, 39145, 34646,
+ 0, 0, 0, 0, 0, 45280, 44040, 39555, 48322, 43761, 46986, 61580, 31407, 53015, 50099, 48311, 52851, 12647, 34880, 26310, 1708, 38684, 39145, 34646, 20833,
+ 0, 0, 0, 0, 0, 44040, 39555, 48322, 43761, 0, 61580, 31407, 53015, 50099, 0, 52851, 12647, 34880, 26310, 0, 38684, 39145, 34646, 20833, 0,
+ 0, 45280, 44040, 39555, 48322, 0, 46986, 61580, 31407, 53015, 0, 48311, 52851, 12647, 34880, 0, 1708, 38684, 39145, 34646, 0, 38991, 55892, 20081, 22175,
+ 45280, 44040, 39555, 48322, 43761, 46986, 61580, 31407, 53015, 50099, 48311, 52851, 12647, 34880, 26310, 1708, 38684, 39145, 34646, 20833, 38991, 55892, 20081, 22175, 48554,
+ 44040, 39555, 48322, 43761, 0, 61580, 31407, 53015, 50099, 0, 52851, 12647, 34880, 26310, 0, 38684, 39145, 34646, 20833, 0, 55892, 20081, 22175, 48554, 0,
+ 0, 46986, 61580, 31407, 53015, 0, 48311, 52851, 12647, 34880, 0, 1708, 38684, 39145, 34646, 0, 38991, 55892, 20081, 22175, 0, 0, 0, 0, 0,
+ 46986, 61580, 31407, 53015, 50099, 48311, 52851, 12647, 34880, 26310, 1708, 38684, 39145, 34646, 20833, 38991, 55892, 20081, 22175, 48554, 0, 0, 0, 0, 0,
+ 61580, 31407, 53015, 50099, 0, 52851, 12647, 34880, 26310, 0, 38684, 39145, 34646, 20833, 0, 55892, 20081, 22175, 48554, 0, 0, 0, 0, 0, 0
+};
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.h
new file mode 100644
index 00000000..8ef7092c
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_golden.h
@@ -0,0 +1,14 @@
+#ifndef GOLDEN_IM2COL_NCHW_H
+#define GOLDEN_IM2COL_NCHW_H
+
+/*
+	Copyright EPFL contributors.
+	Licensed under the Apache License, Version 2.0, see LICENSE for details.
+	SPDX-License-Identifier: Apache-2.0
+*/
+
+#include <stdint.h>
+
+extern const uint32_t golden_im2col_nchw[225];
+
+#endif // GOLDEN_IM2COL_NCHW_H
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.c
new file mode 100644
index 00000000..7def5007
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.c
@@ -0,0 +1,16 @@
+/*
+	Copyright EPFL contributors.
+	Licensed under the Apache License, Version 2.0, see LICENSE for details.
+	SPDX-License-Identifier: Apache-2.0
+*/
+
+#include "im2col_input.h"
+
+const uint32_t input_image_nchw[25] = {
+ 45280, 44040, 39555, 48322, 43761,
+ 46986, 61580, 31407, 53015, 50099,
+ 48311, 52851, 12647, 34880, 26310,
+ 1708, 38684, 39145, 34646, 20833,
+ 38991, 55892, 20081, 22175, 48554
+};
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.h
new file mode 100644
index 00000000..b1ec30ce
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_input.h
@@ -0,0 +1,27 @@
+#ifndef INPUT_IMAGE_NCHW_H
+#define INPUT_IMAGE_NCHW_H
+
+/*
+	Copyright EPFL contributors.
+	Licensed under the Apache License, Version 2.0, see LICENSE for details.
+	SPDX-License-Identifier: Apache-2.0
+*/
+
+#include <stdint.h>
+
+#define IH 5
+#define IW 5
+#define CH 1
+#define BATCH 1
+#define FH 3
+#define FW 3
+#define TOP_PAD 1
+#define BOTTOM_PAD 1
+#define LEFT_PAD 1
+#define RIGHT_PAD 1
+#define STRIDE_D1 1
+#define STRIDE_D2 1
+
+extern const uint32_t input_image_nchw[25];
+
+#endif // INPUT_IMAGE_NCHW_H
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c
index 75d38d74..6670cc0f 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.c
@@ -4,205 +4,483 @@
     SPDX-License-Identifier: Apache-2.0
 
     Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+                            <tommaso.terzano@gmail.com>
 
     Info: im2col_lib.c describes functions used to calculate im2col and verify it using 
     the golden result in im2colGolden.c.
 
-    Notes: im2col_nchw_int32() and im2col_nhwc_int32() algorithms are inspired from the library SHL, developed by T-HEAD Semi.
+    Notes: im2col_nchw_int32() algorithm is inspired from the library SHL, developed by T-HEAD Semi.
     For reference, check out the following link:
-    https://github.com/T-head-Semi/csi-nn2/blob/main/source/reference/im2col.c
+    https:/*github.com/T-head-Semi/csi-nn2/blob/main/source/reference/im2col.c
 */
 
 #include "im2col_lib.h"
 
-int output_data[OH_NCHW*OW_NCHW];
+#if INPUT_DATATYPE == 2
+    typedef uint8_t data_t;
+#elif INPUT_DATATYPE == 1
+    typedef uint16_t data_t;
+#elif INPUT_DATATYPE == 0
+    typedef uint32_t data_t;
+#endif
 
-int im2col_nchw_int32()
+data_t output_data[OH_NCHW*OW_NCHW];
+data_t* input_image_ptr = &input_image_nchw[0];
+data_t* output_data_ptr = &output_data[0];
+
+char im2col_done = 0;
+int ifr_status;
+
+void handler_irq_im2col_spc( void )
+{
+  im2col_done = 1;
+
+  /* Read the IFR to lower the interrupt flag */
+  ifr_status = * (volatile uint32_t * )(EXT_PERIPHERAL_START_ADDRESS + IM2COL_PER_OFFSET + IM2COL_SPC_SPC_IFR_REG_OFFSET);
+  return;
+}
+
+/* Used to wait for the SPC interrupt handler to end */
+__attribute__ ((optimize("O0"))) void waiting_for_spc_irq( void )
 {
-    PRINTF("OH: %d, OW: %d\n", OH_NCHW, OW_NCHW);
+  while (im2col_done == 0)
+  {
+    asm volatile ("wfi");
+  }
+}
 
+int im2col_nchw_int32(uint8_t test_id, unsigned int *cycles)
+{
     int size_transfer = 0;
+    int size_transfer_d2 = 0;
+    int counter = 0;
+    int n_zeros_left = 0;
+    int n_zeros_right = 0;
+    int n_zeros_top = 0;
+    int n_zeros_bottom = 0;
     int im_row = 0;
     int im_col = 0;
-    int w_offset = 0;  // the offset ALONG the IW
-    int h_offset = 0; // the offset ALONG the IH
-    int im_c = 0; // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
+    int im_c = 0; 
+    int w_offset = 0;  
+    int h_offset = 0;
     int col_index = 0;
-    
-    // Iterate over each row of the output matrix.
-    for (int c = 0; c < CH_COL; ++c) {
-        // Calculate offsets within the kernel window.
-        // These are used to move the filter around the input image
-
-        w_offset = c % FW;  
-        h_offset = (c / FW) % FH;
-        im_c = c / (FH * FW); // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
-
-        // Iterate over each BATCH.
-        for (int b = 0; b < BATCH; ++b) {
-            // Iterate over each patch on the IW of the input matrix.
-            for (int h = 0; h < N_PATCHES_H; ++h) {
-                // Iterate over each patch on the heigth in the output matrix.
-                for (int w = 0; w < N_PATCHES_W; ++w) {
-                    // Calculate the row and column indices in the original input image, applying the stride and offset.
-                    im_row = h_offset + h * STRIDES - PAD;
-                    im_col = w_offset + w * STRIDES - PAD;
-
-                    // Calculate the index in the flattened output array where this value should be stored.
-                    col_index = ((c * BATCH + b) * N_PATCHES_H + h) * N_PATCHES_W + w;
-                    
-                    // If the calculated indices are outside the bounds of the input image, set the output to 0 (padding effect).
-                    // Otherwise, fetch the value from the input image and store it in the output array.
-                    if (im_row < 0 || im_col < 0 || im_row >= IH || im_col >= IW) {
-                        output_data[col_index] = 0;
-                    } else {
-                        output_data[col_index] = input_image_nchw[get_index(CH, IH, IW, b, im_c, im_row, im_col)];                        
+    int minimum = 0;
+    int start_max = 0;
+    int start_min = 0;
+    int stray_elements = 0;
+    int last_position = 0;
+    int tmp_pad = 0;
+    int w_offset_pad = 0;
+    int h_offset_pad = 0;
+    int fw_minus_w_offset = 0;
+    int fh_minus_h_offset = 0;
+    unsigned int cycles_A = 0;
+    unsigned int cycles_B = 0;
+    unsigned int avg_first_zeros;
+    unsigned int avg_last_zeros;
+    unsigned int avg_patch = 0;
+    int src_inc_d2 = 0;
+    int w_offset_counter = 0;
+    int h_offset_counter = 0;
+    int h_offset_tmp_counter = 0;
+    int im_c_counter = 0;
+    int w_offset_vs_PAD = 0;
+    int h_offset_vs_PAD = 0;
+    int fw_minus_w_offset_vs_PAD = 0;
+    int fh_minus_h_offset_vs_PAD = 0;
+    int h_offset_tmp = 0;
+    int n_zeros_top_counter = 0;
+    int n_zeros_top_cond = 0;
+    int pad_min_w_offset = 0;
+
+    for (int i=0; i<OH_NCHW*OW_NCHW; i++)
+    {
+        output_data[i] = 0;
+    }
+
+    #if TIMING
+        timer_cycles_init();
+    #endif
+
+    /* Implementation of im2col algorithm using the CPU */
+    if (test_id == 0)
+    {
+        #if TIMING
+        timer_start();
+        #endif
+
+        for (int c = 0; c < CH_COL; ++c) {
+            /* Calculate offsets within the kernel window. */
+            /* These are used to move the filter around the input image */
+
+            w_offset = c % FW;  
+            h_offset = (c / FW) % FH;
+            
+            /* CH on which the im2col is being performed depending on the row of the output image (c) */
+            im_c = c / (FH * FW); 
+
+            /* Iterate over each BATCH. */
+            for (int b = 0; b < BATCH; ++b) {
+                /* Iterate over each patch on the IW of the input matrix.*/
+                for (int h = 0; h < N_PATCHES_H; ++h) {
+                    /* Iterate over each patch on the heigth in the output matrix.*/
+                    for (int w = 0; w < N_PATCHES_W; ++w) {
+                        /* Calculate the row and column indices in the original input image, applying the stride and offset. */
+                        im_row = h_offset + h * STRIDE_D2 - TOP_PAD;
+                        im_col = w_offset + w * STRIDE_D1 - LEFT_PAD;
+
+                        /* Calculate the index in the flattened output array where this value should be stored. */
+                        col_index = ((c * BATCH + b) * N_PATCHES_H + h) * N_PATCHES_W + w;
+                        PRINTF_DEB("\n\rim_row: %d, im_col: %d,", im_row, im_col);
+                        PRINTF_DEB("\n\rw_offset: %d, h_offset: %d\n\r", w_offset, h_offset);
+
+                        /* If the calculated indices are outside the bounds of the input image, perform padding. */
+                        /* Otherwise, fetch the value from the input image and store it in the output array. */
+                        if (im_row < 0 || im_col < 0 || im_row >= IH || im_col >= IW) {
+                            output_data[col_index] = 0;
+                            PRINTF_DEB("Padding with 0\n\r");
+                        } else {
+                            output_data[col_index] = input_image_nchw[get_index(CH, IH, IW, b, im_c, im_row, im_col)];                        
+                            PRINTF_DEB("Value: %d\n\r", input_image_nchw[get_index(CH, IH, IW, b, im_c, im_row, im_col)]);
+                        }
                     }
                 }
             }
         }
+
+        #if TIMING  
+        *cycles = timer_stop();
+        #endif
     }
 
-    // Finished!
+    /* Implementation of the nchw im2col algorithm using the DMA 2D feature */
+    else if (test_id == 1)
+    {
+      
+        data_t* input_image_ptr = &input_image_nchw[0];
+        data_t* output_data_ptr = &output_data[0];
+        /* Iterate over each row of the output matrix. */
 
-    PRINTF("Final output matrix:\n\n");
+        dma_config_flags_t res;
 
-    #if DEBUG
-    for (int i=0; i<OH; i++)
-    {
-        for (int j=0; j<OW; j++)
-        {
-            PRINTF("%d ", output_data[i*OW + j]);
-        }
-        PRINTF("\n");
-    }
-    #endif
+        static dma_target_t tgt_src = {
+                                    .ptr        = input_image_nchw,
+                                    .inc_d1_du  = STRIDE_D1,
+                                    .type       = INPUT_DATATYPE
+                            };
 
-    // Return a 0 to indicate a success
-    return 0;
-}
+        static dma_target_t tgt_dst = {
+                                    .inc_d1_du  = 1,
+                                    .inc_d2_du  = 1,
+                                    .type       = INPUT_DATATYPE
+                                    };
 
-int im2col_nhwc_int32()
-{
-    PRINTF("OH: %d, OW: %d\n", OH_NHWC, OW_NHWC);
+        static dma_trans_t trans = {
+                                    .src        = &tgt_src,
+                                    .dst        = &tgt_dst,
+                                    .mode       = DMA_TRANS_MODE_SINGLE,
+                                    .dim        = DMA_DIM_CONF_2D,
+                                    .end        = DMA_TRANS_END_INTR,
+                                    .channel    = 0
+                                    };
 
-    int size_transfer = 0;
-    int im_row = 0;
-    int im_col = 0;
-    int w_offset = 0;  // the offset ALONG the IW
-    int h_offset = 0; // the offset ALONG the IH
-    int im_c = 0; // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
-    int col_index = 0;
+        #if TIMING
+        timer_start();
+        #endif
+
+        /* The DMA is initialized (i.e. Any current transaction is cleaned.) */
+        dma_init(NULL); 
+
+        w_offset = 0;
+        h_offset = 0;
+        pad_min_w_offset = LEFT_PAD;
+
+        for (int c = 0; c < CH_COL; ++c) {
+
+            /* Iterate over each patch on the IW of the input matrix. */
+            fw_minus_w_offset = FW - 1 - w_offset;
+            fh_minus_h_offset = FH - 1 - h_offset;
+
+            /* Calculate offsets within the kernel window. */
+
+            /* Iterate over each BATCH. */
+            for (int32_t b = 0; b < BATCH; ++b) {
+
+                im_row = h_offset - TOP_PAD;
+                im_col = w_offset - LEFT_PAD;
+                
+                PRINTF_DEB("\n\rim_row: %d, im_col: %d", im_row, im_col);
+                PRINTF_DEB("\n\rw_offset: %d, h_offset: %d\n\r", w_offset, h_offset);
+
+                /* Computing the number of zeros on the left */
+
+                /* In the offset of the element in the filter is bigger than P, then no zeros are needed */
+                if ( w_offset >= LEFT_PAD)
+                {
+                    n_zeros_left = 0;
+                }
+                else if ( (LEFT_PAD - w_offset) % STRIDE_D1 == 0 )
+                {
+                    n_zeros_left = (LEFT_PAD - w_offset) / STRIDE_D1;
+                }
+                else
+                {
+                    n_zeros_left = (LEFT_PAD - w_offset) / STRIDE_D1 + 1;
+                }
+
+                /* Computing the number of zeros on the top */
+
+                /* In the offset of the element in the filter is bigger than P, then no zeros are needed */
+                if ( h_offset >= TOP_PAD)
+                {
+                    n_zeros_top = 0;
+                }
+                else if ( (TOP_PAD - h_offset) % STRIDE_D2 == 0 )
+                {
+                    n_zeros_top = (TOP_PAD - h_offset) / STRIDE_D2;
+                }
+                else
+                {
+                    n_zeros_top = (TOP_PAD - h_offset) / STRIDE_D2 + 1;
+                }
+
+                /* Computing the number of zeros on the right */
 
-    // Calculate the heigth of the output matrix
-
-    // Iterate over each row of the output matrix.
-    for (int b = 0; b < BATCH; ++b) {
-        // Iterate over each BATCH.
-        for (int h = 0; h < N_PATCHES_H; ++h) {
-            // Iterate over each patch on the IW of the input matrix.
-            for (int w = 0; w < N_PATCHES_W; ++w) {
-                // Iterate over each patch on the heigth in the output matrix.
-                for (int c = 0; c < CH_COL; ++c) {
-                    // Calculate offsets within the kernel window.
-                    // These are used to move the filter around the input image
-
-                    w_offset = c % FW;  
-                    h_offset = (c / FW) % FH;
-                    im_c = c / (FH * FW); // Gets the CH on which the im2col is being performed depending on the row of the output image (c)
-                    
-                    // Calculate the row and column indices in the original input image, applying the stride and offset.
-                    im_row = h_offset + h * STRIDES - PAD;
-                    im_col = w_offset + w * STRIDES - PAD;
-
-                    // Calculate the index in the flattened output array where this value should be stored.
-                    col_index = ((b * N_PATCHES_H + h) * N_PATCHES_W + w) * CH_COL + c; //  ((c * BATCH + b) * N_PATCHES_H + h) * N_PATCHES_W + w;
-                    
-                    // If the calculated indices are outside the bounds of the input image, set the output to 0 (padding effect).
-                    // Otherwise, fetch the value from the input image and store it in the output array.
-                    if (im_row < 0 || im_col < 0 || im_row >= IH || im_col >= IW) {
-                        output_data[col_index] = 0;
-                    } else {
-                        output_data[col_index] = input_image_nhwc[get_index(IH, IW, CH, b, im_row, im_col, im_c)];
-                    }                    
+                /* To adapt the final case to the formulas used to the first padded region, let's compute an "adapted" padded region,
+                /* by removing the elements of the row uncovered by the sliding filter */
+                
+                if (fw_minus_w_offset >= RIGHT_PAD || ADPT_PAD_RIGHT == 0)
+                {
+                    n_zeros_right = 0;
+                }
+                else if ( (ADPT_PAD_RIGHT - (fw_minus_w_offset)) % STRIDE_D1 == 0 )
+                {
+                    n_zeros_right = (ADPT_PAD_RIGHT - (fw_minus_w_offset)) / STRIDE_D1;
+                }
+                else
+                {
+                    n_zeros_right = (ADPT_PAD_RIGHT - (fw_minus_w_offset)) / STRIDE_D1 + 1;
+                }
+
+                /* Computing the number of zeros on the bottom */
+
+                /* To adapt the final case to the formulas used to the first padded region, let's compute an "adapted" padded region,
+                /* by removing the elements of the row uncovered by the sliding filter */
+
+                if (fh_minus_h_offset >= BOTTOM_PAD || ADPT_PAD_BOTTOM == 0)
+                {
+                    n_zeros_bottom = 0;
+                }
+                else if ( (ADPT_PAD_BOTTOM - (fh_minus_h_offset)) % STRIDE_D2 == 0)
+                {
+                    n_zeros_bottom = (ADPT_PAD_BOTTOM - (fh_minus_h_offset)) / STRIDE_D2;
+                }
+                else
+                {
+                    n_zeros_bottom = (ADPT_PAD_BOTTOM - (fh_minus_h_offset)) / STRIDE_D2 + 1;
+                }
+
+                /* Compute the number of elements to transfer */
+                size_transfer = N_PATCHES_W - n_zeros_left - n_zeros_right;
+                size_transfer_d2 = N_PATCHES_H - n_zeros_top - n_zeros_bottom;
+
+                PRINTF_DEB("\n\rn_zeros_left: %d, n_zeros_right: %d, n_zeros_top: %d, n_zeros_bottom: %d", n_zeros_left, n_zeros_right, n_zeros_top, n_zeros_bottom);
+                PRINTF_DEB("\n\rsize_transfer: %d, size_transfer_d2: %d\n\r", size_transfer, size_transfer_d2);
+    
+                /* DMA setup and transaction run */
+                int index = get_index(CH, IH, IW, b, im_c, im_row + n_zeros_top*STRIDE_D2, im_col + n_zeros_left*STRIDE_D1);
+                src_inc_d2 = (STRIDE_D2 * IW - (size_transfer - 1 + (STRIDE_D1 - 1) * (size_transfer - 1)));
+
+                PRINTF_DEB("\n\rindex: %d, src_inc_d2: %d", index, src_inc_d2);
+                
+                input_image_ptr = &input_image_nchw[0] + index;
+                PRINTF_DEB("\n\rsrc_ptr: %x dst_ptr: %x\n\r", input_image_ptr, output_data_ptr);
+
+                tgt_src.ptr = input_image_ptr;
+                tgt_src.inc_d2_du = src_inc_d2;
+
+                tgt_dst.ptr = output_data_ptr;
+
+                trans.src = &tgt_src;
+                trans.dst = &tgt_dst;
+                trans.size_d1_du = size_transfer;
+                trans.size_d2_du = size_transfer_d2;
+                trans.pad_top_du = n_zeros_top;
+                trans.pad_left_du = n_zeros_left;
+                trans.pad_right_du = n_zeros_right;
+                trans.pad_bottom_du = n_zeros_bottom;
+                
+                dma_run(&trans);
+
+                output_data_ptr += OW_NCHW;
+
+                PRINTF_DEB("\n\r");
+
+                #ifndef DEBUG
+                PRINTF_DEB("\n\rCurrent output matrix: \n\r");
+                for (int i=0; i<OH_NCHW; i++)
+                {
+                    for (int j=0; j<OW_NCHW; j++)
+                    {
+                        PRINTF_DEB("%d ", output_data[i*OW_NCHW + j]);
+                    }
+                    PRINTF_DEB("\n\r");
+                }
+                #endif
+            }
+                PRINTF_DEB("\n\r");
+            
+            /* Optimized w_offset computation: w_offset = c % FW */
+            if (w_offset == FW - 1)
+            {
+                w_offset = 0;
+            } 
+            else
+            {
+                w_offset++;
+            }
+
+            /* Optimized h_offset computation: h_offset = (h_offset_tmp) % FH with h_offset_tmp = c / FW */
+            if (h_offset_counter == FW - 1)
+            {
+                h_offset_counter = 0;
+                if (h_offset == FH - 1)
+                {
+                    h_offset = 0;
+                } 
+                else
+                {
+                    h_offset++;
                 }
+            } 
+            else
+            {
+                h_offset_counter++;
             }
+
+            /* Optimized im_c computation: im_c = c / FW*FH */
+            if (im_c_counter == FH*FW - 1)
+            {
+                im_c_counter = 0;
+                im_c++;
+            } 
+            else
+            {
+                im_c_counter++;
+            }     
         }
+
+        #if TIMING  
+        *cycles = timer_stop();
+        #endif
     }
 
-    PRINTF("Final output matrix:\n\n");
+    /* Implementation of im2col algorithm using the dedicated Smart Peripheral Controller */
+    else if (test_id == 2)
+    {
+        input_image_ptr = &input_image_nchw[0];
+        output_data_ptr = &output_data[0];
+
+        #if TIMING
+        timer_start();
+        #endif
+
+        im2col_spc_init(NULL);
+
+        static im2col_trans_t im2col_spc_trans = {
+          .ch_mask = SPC_CH_MASK,
+          .im_width = IW,
+          .im_height = IH,
+          .filter_width = FW,
+          .filter_height = FH,
+          .num_channels = CH,
+          .num_channels_col = CH_COL,
+          .stride_d1 = STRIDE_D1,
+          .stride_d2 = STRIDE_D2,
+          .batch = BATCH,
+          .n_patches_w = N_PATCHES_W,
+          .n_patches_h = N_PATCHES_H,
+          .left_pad = LEFT_PAD,
+          .right_pad = RIGHT_PAD,
+          .top_pad = TOP_PAD,
+          .bottom_pad = BOTTOM_PAD,
+          .adpt_pad_right = ADPT_PAD_RIGHT,
+          .adpt_pad_bottom = ADPT_PAD_BOTTOM,
+          .datatype = INPUT_DATATYPE
+        };
+
+        im2col_spc_trans.src = input_image_ptr;
+        im2col_spc_trans.dst = output_data_ptr;
+
+        im2col_spc_run(im2col_spc_trans);
+
+        waiting_for_spc_irq();
+
+        #if TIMING  
+        *cycles = timer_stop();
+        #endif
+    }
+    /* Finished! */
 
     #if DEBUG
-    for (int i=0; i<OH; i++)
+    PRINTF("Final output matrix:\n\r\n\r");
+    for (int i=0; i<OH_NCHW; i++)
     {
-        for (int j=0; j<OW; j++)
+        for (int j=0; j<OW_NCHW; j++)
         {
-            PRINTF("%d ", output_data[i*OW + j]);
+            PRINTF("%d ", output_data[i*OW_NCHW + j]);
         }
-        PRINTF("\n");
+        PRINTF("\n\r");
     }
     #endif
 
-    // Return a 0 to indicate a success
+    /* Return a 0 to indicate a success */
     return 0;
 }
 
-
 int get_index(int dim1, int dim2, int dim3, int index0, int index1, int index2,
                           int index3)
 {
     return ((index0 * dim1 + index1) * dim2 + index2) * dim3 + index3;
 }
 
-// Verifies the im2col using golden values generated by "verification_script.py"
-int verify(int format)
+/* Verifies the im2col using golden values generated by "verification_script.py" */
+int verify()
 {
-    int errors = 0;
+  int errors = 0;
 
-    if (format == 0)
-    {
-        for (int i=0; i<OH_NCHW; i++)
-        {
-            for (int j=0; j<OW_NCHW; j++)
-            {    
-                if (golden_im2col_nchw[i*OW_NCHW + j] != output_data[i*OW_NCHW + j])
-                {
-                    PRINTF("ERROR: Golden: %d, Output: %d, at %d %d\n", golden_im2col_nchw[i*OW_NCHW + j], output_data[i*OW_NCHW + j], i, j);
-                    errors ++;
-                }
-            }
-        }
-    }
-    else
-    {
-        for (int i=0; i<OH_NHWC; i++)
-        {
-            for (int j=0; j<OW_NHWC; j++)
-            {    
-                if (golden_im2col_nhwc[i*OW_NHWC + j] != output_data[i*OW_NHWC + j])
-                {
-                    PRINTF("ERROR: Golden: %d, Output: %d, at %d %d\n", golden_im2col_nhwc[i*OW_NHWC + j], output_data[i*OW_NHWC + j], i, j);
-                    errors ++;
-                }
-            }
-        }
-    }
+  for (int i=0; i<OH_NCHW; i++)
+      {
+          for (int j=0; j<OW_NCHW; j++)
+          {    
+              if (golden_im2col_nchw[i*OW_NCHW + j] != output_data[i*OW_NCHW + j])
+              {
+                  PRINTF("ERROR: Golden: %d, Output: %d, at %d %d %x\n\r", golden_im2col_nchw[i*OW_NCHW + j], output_data[i*OW_NCHW + j], i, j, &output_data[i*OW_NCHW + j]);
+                  errors ++;
+              }
+          }
+      }
+    
     return errors;
 }
 
 void dma_run(dma_trans_t * trans)
 {
     int res = dma_validate_transaction(trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
+    PRINTF_DEB("DMA validation result: %d\n\r", res);
     res = dma_load_transaction(trans);
+    PRINTF_DEB("DMA load result: %d\n\r", res);
     res = dma_launch(trans);
+    PRINTF_DEB("DMA launch result: %d\n\r", res);
 
     while( ! dma_is_ready(0)) {
-        // disable_interrupts
-        // this does not prevent waking up the core as this is controlled by the MIP register
+        /* Disable_interrupts */
+        /* This does not prevent waking up the core as this is controlled by the MIP register */
+        
         CSR_CLEAR_BITS(CSR_REG_MSTATUS, 0x8);
         if ( dma_is_ready(0) == 0 ) {
-            wait_for_interrupt();
-            //from here we wake up even if we did not jump to the ISR
+            asm volatile("wfi");
+            /* From here the core wakes up even if we did not jump to the ISR */
         }
         CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
     }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h
index 179f0e07..cc249ee5 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/im2col_lib.h
@@ -4,6 +4,7 @@
     SPDX-License-Identifier: Apache-2.0
 
     Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
     
     Info: Header file of im2col_lib.c, containing the function prototypes, parameters macros and the configuration of prints and performance analysis.
 */
@@ -14,25 +15,64 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdint.h>
-#include "im2colGolden.h"
+#include "im2col_golden.h"
+#include "im2col_input.h"
+#include "im2col.h"
 #include "dma.h"
+#include "im2col_spc_regs.h"
 #include "core_v_mini_mcu.h"
 #include "x-heep.h"
 #include "rv_plic.h"
 #include "csr.h"
+#include <math.h>
 
-// By default, printfs are activated for FPGA and for simulation.
+#include "mmio.h"
+#include "handler.h"
+#include "hart.h"
+#include "fast_intr_ctrl.h"
+#include "timer_sdk.h"
+
+/* 
+    Choose between several HW configurations:
+    - 0: Only CPU
+    - 1: Exploit standard DMA
+    - 2: Exploit 2D DMA
+    - 3: Exploit Smart Peripheral Controller (SPC)
+*/ 
+#define HW_CONFIG_CPU
+#define HW_CONFIG_DMA_2D
+#define HW_CONFIG_SPC
+
+/* Defines which DMA channels are available to the SPC, depending on HW specifications */
+#define SPC_CH_MASK 0b0001 
+
+/* Defines the datatype of the input */
+#define INPUT_DATATYPE 0
+
+/* Defines the offset of the im2col SPC in the system (0x4000 in testharness.sv) */
+#define IM2COL_PER_OFFSET 0x4000
+
+/* By default, printfs are activated for FPGA and for simulation. */
 #define PRINTF_IN_FPGA  1
 #define PRINTF_IN_SIM   0
-#define DEBUG 0 // Set to 1 to enable debug prints
-#define TIMING 0 // Set to 1 to enable timing measurements
 
-// Format is defined in im2colGolden.h
+/* Set to 1 to enable debug prints */
+#define DEBUG 0
+/* Set to 1 to enable timing measurements */
+#define TIMING 1
 
 #if TARGET_SIM && PRINTF_IN_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
-    #define PRINTF_DEB(...) 
-    #define PRINTF_TIM(...)   
+    #if DEBUG
+        #define PRINTF_DEB(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+    #else
+        #define PRINTF_DEB(...)
+    #endif
+    #if TIMING
+        #define PRINTF_TIM(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+    #else
+        #define PRINTF_TIM(...)
+    #endif  
 #elif PRINTF_IN_FPGA && !TARGET_SIM
     #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
     #if DEBUG
@@ -53,22 +93,30 @@
 
 // Define the dimensions of the input tensor and the kernel
 
-#define N_PATCHES_H ((IH + (PAD + PAD) - FH)/ STRIDES + 1)
-#define N_PATCHES_W ((IW + (PAD + PAD) - FW)/ STRIDES + 1)
+#define N_PATCHES_H ((IH + (TOP_PAD + BOTTOM_PAD) - FH)/ STRIDE_D2 + 1)
+#define N_PATCHES_W ((IW + (RIGHT_PAD + LEFT_PAD) - FW)/ STRIDE_D1 + 1)
+
+#define ADPT_PAD_BOTTOM (STRIDE_D2 * (N_PATCHES_H - 1) + FH - (TOP_PAD + IH))
+#define ADPT_PAD_RIGHT (STRIDE_D1 * (N_PATCHES_W - 1) + FW - (LEFT_PAD + IW))
 
 #define CH_COL (CH * FH * FW)
 
 #define OH_NCHW (CH * FH * FW * BATCH)
 #define OW_NCHW (N_PATCHES_H) * (N_PATCHES_W)
 
-#define OW_NHWC (FW * FH * CH * BATCH)
-#define OH_NHWC (N_PATCHES_W) * (N_PATCHES_H)
+#define START_ID 0
 
-int im2col_nchw_int32();
-int im2col_nhwc_int32();
+#define TEST_EN 0
+
+// Computations for 2D DMA
+#define SRC_INC_D2 (STRIDE_D2 * IW - (FW - 1 + (STRIDE_D1 - 1) * (FW - 1)))
+
+int im2col_nchw_int32(uint8_t test_id, unsigned int *cycles);
+
+__attribute__((weak, optimize("O0"))) void handler_irq_im2col_spc(void);
 
 int get_index(int dim1, int dim2, int dim3, int index0, int index1, int index2, int index3);
                 
-int verify(int format);
+int verify(void);
 
-#endif
\ No newline at end of file
+#endif
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c
index a22c8bf8..23c71e67 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_im2col/main.c
@@ -4,6 +4,7 @@
     SPDX-License-Identifier: Apache-2.0
 
     Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+                            <tommaso.terzano@gmail.com>
     
     Info: Example application of im2col algorithm with configurable format, verification and performance analysis.
 */
@@ -14,68 +15,45 @@
 #include "x-heep.h"
 #include "im2col_lib.h"
 
-#define NCHW_FORMAT 0
-#define NHWC_FORMAT 1
+/* Test variables */
+int errors;
+unsigned int cycles;
 
 int main()
 {
-    PRINTF("\nStarting test...\n\n");
-    
-    int errors;
-    unsigned int cycles;
-    
-    #if TIMING
-        CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-        CSR_WRITE(CSR_REG_MCYCLE, 0);
-    #endif 
-    
-    im2col_nchw_int32(); // Execute the im2col algorithm with NCHW format
-
-    #if TIMING
-        CSR_READ(CSR_REG_MCYCLE, &cycles);
-    #endif
-    
-    errors = verify(NCHW_FORMAT);
-
-    PRINTF("im2col NCHW test executed\n");
-    
-    PRINTF_TIM("Total number of cycles: [%d]\n\n", cycles);
-
-    if (errors != 0)
+    for (int i=START_ID; i<3; i++)
     {
-        PRINTF("TEST FAILED: %d errors\n", errors);
-        return 1;
-    } 
-    else
-    {
-        PRINTF("TEST PASSED!\n");
-    }
-
-    #if TIMING
-        CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
-        CSR_WRITE(CSR_REG_MCYCLE, 0);
-    #endif
-
-    im2col_nhwc_int32(); // Execute the im2col algorithm with NHWC format
-
-    #if TIMING
-        CSR_READ(CSR_REG_MCYCLE, &cycles);
-    #endif
-
-    errors = verify(NHWC_FORMAT);
-
-    PRINTF("im2col NHWC test executed\n");
-    PRINTF_TIM("Total number of cycles: [%d]\n\n", cycles);
-
-    if (errors != 0)
-    {
-        PRINTF("TEST FAILED: %d errors\n", errors);
-        return 1;
-    } 
-    else
-    {
-        PRINTF("TEST PASSED!\n");
+      im2col_nchw_int32(i, &cycles);
+
+      #if TEST_EN == 0
+      PRINTF("im2col NCHW test %d executed\n\r", i);
+      PRINTF_TIM("Total number of cycles: [%d]\n\r", cycles);
+      #endif
+
+      errors = verify();
+
+      if (errors != 0)
+      {
+          #if TEST_EN == 0
+          PRINTF("TEST %d FAILED: %d errors\n\r", i, errors);
+          return EXIT_FAILURE;
+          #else
+          PRINTF_TIM("%d:%d:1\n\r", i, cycles);
+          #endif
+          
+      } 
+      else
+      {
+          #if TEST_EN == 0
+          PRINTF("TEST PASSED!\n\r\n\r");
+          #else
+          PRINTF_TIM("%d:%d:0\n\r", i, cycles);                
+          #endif
+      } 
     }
+    
+    /* Print the end word for verification */
+    PRINTF("&\n\r");
 
-    return 0;
+    return EXIT_SUCCESS;
 }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c
index 4f025e1e..e1fe60e9 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_power_manager/main.c
@@ -49,7 +49,7 @@ static power_manager_t power_manager;
 
 #define TEST_WORD
 //this data has to be big to allow the CPU to power gate
-#define TEST_DATA_SIZE 500
+#define TEST_DATA_SIZE 450
 
 // Source and destination addresses have to be aligned on a 4 bytes address
 uint32_t test_data_4B[TEST_DATA_SIZE] __attribute__ ((aligned (4))) = { 0 };
@@ -179,37 +179,29 @@ int main(int argc, char *argv[])
     }
 
     dma_init(NULL);
-    dma_config_flags_t res;
-    dma_target_t tgt_src;
-    dma_target_t tgt_dst;
-    dma_target_t tgt_addr = {
-        .ptr = NULL,
-        .inc_du = 1,
-        .size_du = 0,
-        .trig = DMA_TRIG_MEMORY,
-    };
-    dma_trans_t trans;
+    static dma_config_flags_t res;
+    static dma_target_t tgt_src;
+    static dma_target_t tgt_dst;
+    static dma_trans_t trans;
 
     // Initialize the DMA for the next tests
     tgt_src.ptr = (uint8_t *)test_data_4B;
-    tgt_src.inc_du = 1;
-    tgt_src.size_du = TEST_DATA_SIZE;
+    tgt_src.inc_d1_du = 1;
     tgt_src.trig = DMA_TRIG_MEMORY;
     tgt_src.type = DMA_DATA_TYPE_WORD;
     tgt_src.env = NULL;
     tgt_src.inc_d2_du = 0;
 
     tgt_dst.ptr = (uint8_t *)copied_data_4B;
-    tgt_dst.inc_du = 1;
-    tgt_dst.size_du = TEST_DATA_SIZE;
+    tgt_dst.inc_d1_du = 1;
     tgt_dst.trig = DMA_TRIG_MEMORY;
     tgt_dst.type = DMA_DATA_TYPE_WORD;
     tgt_dst.env = NULL;
     tgt_dst.inc_d2_du = 0;
 
+    trans.size_d1_du = TEST_DATA_SIZE;
     trans.src = &tgt_src;
     trans.dst = &tgt_dst;
-    trans.src_addr = &tgt_addr;
     trans.src_type = DMA_DATA_TYPE_WORD;
     trans.dst_type = DMA_DATA_TYPE_WORD;
     trans.mode = DMA_TRANS_MODE_SINGLE;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/applications/example_tensor_format_conv/main.c b/hw/vendor/esl_epfl_x_heep/sw/applications/example_tensor_format_conv/main.c
new file mode 100644
index 00000000..575b8dee
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/applications/example_tensor_format_conv/main.c
@@ -0,0 +1,288 @@
+/*
+ *  Copyright EPFL contributors.
+ *  Licensed under the Apache License, Version 2.0, see LICENSE for details.
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+ *                         <tommaso.terzano@gmail.com>
+ *  
+ *  Info: This application converts a HWC tensor to a CHW tensor and viceversa, leveraging the DMA subsytem.
+ * 
+ *        This is a simple example of a HWC tensor with 3 channels, 2 rows and 2 columns:
+ *             (1, 2, 3) (4, 5, 6)
+ *             (7, 8, 9) (10, 11, 12)
+ *        (1, 2, 3) are the values of the first "pixel" of the tensor across different channels, 1 for CH0, 2 for CH1 and 3 for CH2.
+ *        
+ *        On the other hand, this is the same tensor represented with the CHW format:
+ * 
+ *             (1) (4)
+ *             (7) (10)
+ *             (2) (5)
+ *             (8) (11)
+ *             (3) (6)
+ *             (9) (12)
+ * 
+ *        (1) is the first pixel of CH0, which is composed of the values 1, 4, 7, 10, and so on.
+ * 
+ *        The conversion hwc -> chw is performed in this manner:
+ *        - Copy the first element (1)
+ *        - Skip #channels elements
+ *        - Copy the element (4) 
+ *        And so on.
+ * 
+ *        To speed the conversion up, the application makes use of the DMA.
+ *        Its transposition function is used in an unconventional way: the d1 increment is set to #channels, while the d2 increment
+ *        is set to 1. 
+ *        In this way, the DMA will copy H*W elements with a C stride, then start the next copy from the first element + 1, 
+ *        and repeat until completion.
+ *        This behaviour is similar to a 3D copy, because it performs a copy of a matrix (H*W) with a stride (C), even if 
+ *        using just 2 counters. 
+ * 
+ *        The conversion chw -> hwc is performed in a similar way, but it needs H loops, making it a lot slower than the other type
+ *        of conversion.  
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "dma.h"
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+#include "csr.h"
+#include "rv_plic.h"
+
+/* Uncomment to disable performance analysis */
+#define EN_PERF
+
+#define C 3
+#define H 4
+#define W 3
+
+/* By default, printfs are activated for FPGA and disabled for simulation. */
+#define PRINTF_IN_FPGA  1
+#define PRINTF_IN_SIM   0
+
+#if TARGET_SIM && PRINTF_IN_SIM
+        #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#elif PRINTF_IN_FPGA && !TARGET_SIM
+    #define PRINTF(fmt, ...)    printf(fmt, ## __VA_ARGS__)
+#else
+    #define PRINTF(...)
+#endif
+
+/* CHW example array */
+int chw_array[36] = {
+    // Channel 1
+    7,  8,  5,    // Row 1
+    9,  3,  6,    // Row 2
+    2,  4,  1,    // Row 3
+    8, 10, 12,    // Row 4
+
+    // Channel 2
+    15, 16, 13,   // Row 1
+    19, 11, 14,   // Row 2
+    10, 18, 17,   // Row 3
+    20, 22, 21,   // Row 4
+
+    // Channel 3
+    23, 25, 24,   // Row 1
+    28, 26, 27,   // Row 2
+    29, 31, 30,   // Row 3
+    32, 34, 33    // Row 4
+};
+
+/* HWC example array */
+int hwc_array[36] = {
+    // Row 1
+    7,  15, 23,   // W1C1, W1C2, W1C3
+    8,  16, 25,   // W2C1, W2C2, W2C3
+    5,  13, 24,   // W3C1, W3C2, W3C3
+
+    // Row 2
+    9,  19, 28,   // W1C1, W1C2, W1C3
+    3,  11, 26,   // W2C1, W2C2, W2C3
+    6,  14, 27,   // W3C1, W3C2, W3C3
+
+    // Row 3
+    2,  10, 29,   // W1C1, W1C2, W1C3
+    4,  18, 31,   // W2C1, W2C2, W2C3
+    1,  17, 30,   // W3C1, W3C2, W3C3
+
+    // Row 4
+    8,  20, 32,   // W1C1, W1C2, W1C3
+    10, 22, 34,   // W2C1, W2C2, W2C3
+    12, 21, 33    // W3C1, W3C2, W3C3
+};
+
+int convert_hwc_to_chw_int32(int *src, int *dst)
+{
+    #ifdef EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    static dma_target_t tgt_src;
+    static dma_target_t tgt_dst;
+    static dma_trans_t trans;
+    int res_valid, res_load, res_launch, cycles_dma;
+
+    /* Initialize the targets */
+    tgt_src.ptr = (uint8_t *) src;
+    tgt_src.inc_d1_du = 1;
+    tgt_src.inc_d2_du = C;
+    tgt_src.trig = DMA_TRIG_MEMORY;
+    tgt_src.type = DMA_DATA_TYPE_WORD;
+    
+    tgt_dst.ptr = (uint8_t *)  dst;
+    tgt_dst.inc_d1_du = 1;
+    tgt_dst.inc_d2_du = 1;
+    tgt_dst.trig = DMA_TRIG_MEMORY;
+    tgt_dst.type = DMA_DATA_TYPE_WORD;
+
+    trans.src = &tgt_src;
+    trans.dst = &tgt_dst;
+    trans.mode = DMA_TRANS_MODE_SINGLE;
+    trans.dim = DMA_DIM_CONF_2D;
+    trans.dim_inv        = 1; // Enable transposition function
+    trans.size_d1_du     = H * W;
+    trans.size_d2_du     = C;
+    trans.win_du         = 0,
+    trans.end            = DMA_TRANS_END_INTR_WAIT;
+
+    dma_init(NULL);
+
+    res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+    res_load = dma_load_transaction(&trans);
+    res_launch = dma_launch(&trans);
+    if (res_launch | res_load | res_valid) {
+        PRINTF("Error in the DMA transaction! %d - %d - %d\n", res_valid, res_load, res_launch);
+        exit(1);
+    }
+    
+    #ifdef EN_PERF
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+    return cycles_dma;
+    #endif
+
+    return 0;
+}
+
+int convert_chw_to_hwc_int32(int *src, int *dst)
+{
+    static dma_target_t tgt_src;
+    static dma_target_t tgt_dst;
+    static dma_trans_t trans;
+    int res_valid, res_load, res_launch, cycles_dma;
+    int * src_ptr = src;
+    int * dst_ptr = dst;
+
+    #ifdef EN_PERF
+
+    /* Reset the counter to evaluate the performance of the DMA */
+    CSR_CLEAR_BITS(CSR_REG_MCOUNTINHIBIT, 0x1);
+    CSR_WRITE(CSR_REG_MCYCLE, 0);
+    #endif
+
+    dma_init(NULL);
+
+    for (int i=0; i < H; i++) {
+
+      /* Initialize the targets */
+      tgt_src.ptr = (uint8_t *) src_ptr;
+      tgt_src.inc_d1_du = 1;
+      tgt_src.inc_d2_du = H * W;
+      tgt_src.trig = DMA_TRIG_MEMORY;
+      tgt_src.type = DMA_DATA_TYPE_WORD;
+
+      tgt_dst.ptr = (uint8_t *) dst_ptr;
+      tgt_dst.inc_d1_du = 1;
+      tgt_dst.inc_d2_du = 1;
+      tgt_dst.trig = DMA_TRIG_MEMORY;
+      tgt_dst.type = DMA_DATA_TYPE_WORD;
+
+      trans.src = &tgt_src;
+      trans.dst = &tgt_dst;
+      trans.mode = DMA_TRANS_MODE_SINGLE;
+      trans.dim = DMA_DIM_CONF_2D;
+      trans.dim_inv        = 1; // Enable transposition function
+      trans.size_d1_du     = C;
+      trans.size_d2_du     = W;
+      trans.win_du         = 0,
+      trans.end            = DMA_TRANS_END_INTR_WAIT;
+
+      res_valid = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY);
+      res_load = dma_load_transaction(&trans);
+      res_launch = dma_launch(&trans);
+      if (res_launch | res_load | res_valid) {
+        PRINTF("Error in the DMA transaction! %d - %d - %d\n", res_valid, res_load, res_launch);
+        exit(1);
+      }
+
+      src_ptr += W;
+      dst_ptr += W * C;
+    }
+
+    #ifdef EN_PERF
+
+    /* Read the cycles count after the DMA run */
+    CSR_READ(CSR_REG_MCYCLE, &cycles_dma);
+    return cycles_dma;
+    #endif
+
+    return 0;
+}
+
+int main()
+{ 
+    int cycles_dma;
+    int dst_array[36];
+    int passed_chw = 1;
+    int passed_hwc = 1;
+
+    /* Convert HWC to CHW */
+    cycles_dma = convert_hwc_to_chw_int32(hwc_array, dst_array);
+
+    #ifdef EN_PERF
+    PRINTF("DMA cycles HWC -> CHW: %d\n\n\r", cycles_dma);
+    #endif
+
+    /* Verify that the computed and the expected outputs are the same */
+    for (int i = 0; i < H * W * C; i++) {
+        if (chw_array[i] != dst_array[i]) {
+            passed_chw = 0;
+        }
+    }
+
+    /* Convert CHW to HWC */
+    cycles_dma = convert_chw_to_hwc_int32(chw_array, dst_array);
+
+    #ifdef EN_PERF
+    PRINTF("DMA cycles CHW -> HWC: %d\n\n\r", cycles_dma);
+    #endif
+
+    /* Verify that the computed and the expected outputs are the same */
+    for (int i = 0; i < H * W * C; i++) {
+        if (hwc_array[i] != dst_array[i]) {
+            passed_hwc = 0;
+        }
+    }
+
+    if (passed_hwc && passed_chw) {
+        PRINTF("Success\n\n\r");
+    } 
+    else 
+    {
+        if (!passed_hwc) {
+            PRINTF("Fail HWC -> CHW\n\r");
+        }
+        if (!passed_chw) {
+            PRINTF("Fail CHW -> HWC\n\r");
+        }
+        return EXIT_FAILURE;
+    }
+
+    return 0;
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
index 04908d8e..f6a3ac99 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q.c
@@ -441,7 +441,7 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data,
 }
 
 
-w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_dma, uint8_t no_sanity_checks) {
+w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_init_dma, uint8_t no_sanity_checks) {
 
     // Sanity checks
     if (!no_sanity_checks)  if (w25q128jw_sanity_checks(addr, data, length) != FLASH_OK) return FLASH_ERROR;
@@ -453,7 +453,7 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32
     uint32_t *fifo_ptr_rx = (uint32_t *)((uintptr_t)spi + SPI_HOST_RXDATA_REG_OFFSET);
 
     // Init DMA, the integrated DMA is used (peri == NULL)
-    if(!no_wait_dma)    dma_init(NULL);
+    if(!no_wait_init_dma)    dma_init(NULL);
 
     // The DMA will wait for the SPI HOST/FLASH RX FIFO valid signal
     #ifndef USE_SPI_FLASH
@@ -464,11 +464,9 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32
 
     // Set up DMA source target
     static dma_target_t tgt_src = {
-        .inc_du = 0, // Target is peripheral, no increment
+        .inc_d1_du = 0, // Target is peripheral, no increment
         .type = DMA_DATA_TYPE_WORD, // Data type is word
     };
-    // Size is in data units (words in this case)
-    tgt_src.size_du = length>>2;
     // Target is SPI RX FIFO
     tgt_src.ptr = (uint8_t*)fifo_ptr_rx;
     // Trigger to control the data flow
@@ -476,7 +474,7 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32
 
     // Set up DMA destination target
     static dma_target_t tgt_dst = {
-        .inc_du = 1, // Increment by 1 data unit (word)
+        .inc_d1_du = 1, // Increment by 1 data unit (word)
         .type = DMA_DATA_TYPE_WORD, // Data type is byte
         .trig = DMA_TRIG_MEMORY, // Read-write operation to memory
     };
@@ -488,6 +486,8 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32
         .dst = &tgt_dst,
         .end = DMA_TRANS_END_POLLING,
     };
+    // Size is in data units (words in this case)
+    trans.size_d1_du = length>>2;
 
     // Validate, load and launch DMA transaction
 
@@ -524,7 +524,7 @@ w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32
     spi_wait_for_ready(spi);
 
     // Wait for DMA to finish transaction
-    if(!no_wait_dma) while(!dma_is_ready(0));
+    if(!no_wait_init_dma) while(!dma_is_ready(0));
 
     // Take into account the extra bytes (if any)
     if (length % 4 != 0) {
@@ -569,11 +569,9 @@ w25q_error_codes_t w25q128jw_read_standard_dma_async(uint32_t addr, void *data,
 
     // Set up DMA source target
     static dma_target_t tgt_src = {
-        .inc_du = 0, // Target is peripheral, no increment
+        .inc_d1_du = 0, // Target is peripheral, no increment
         .type = DMA_DATA_TYPE_WORD, // Data type is word
     };
-    // Size is in data units (words in this case)
-    tgt_src.size_du = length>>2;
     // Target is SPI RX FIFO
     tgt_src.ptr = (uint8_t*)fifo_ptr_rx;
     // Trigger to control the data flow
@@ -581,7 +579,7 @@ w25q_error_codes_t w25q128jw_read_standard_dma_async(uint32_t addr, void *data,
 
     // Set up DMA destination target
     static dma_target_t tgt_dst = {
-        .inc_du = 1, // Increment by 1 data unit (word)
+        .inc_d1_du = 1, // Increment by 1 data unit (word)
         .type = DMA_DATA_TYPE_WORD, // Data type is byte
         .trig = DMA_TRIG_MEMORY, // Read-write operation to memory
     };
@@ -593,6 +591,8 @@ w25q_error_codes_t w25q128jw_read_standard_dma_async(uint32_t addr, void *data,
         .dst = &tgt_dst,
         .end = DMA_TRANS_END_INTR, //so that you can wait for interrupt
     };
+    // Size is in data units (words in this case)
+    trans.size_d1_du = length>>2;
     // Validate, load and launch DMA transaction
     dma_config_flags_t res;
     res = dma_validate_transaction(&trans, DMA_ENABLE_REALIGN, DMA_PERFORM_CHECKS_INTEGRITY );
@@ -903,11 +903,9 @@ w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t l
 
     // Set up DMA source target
     static dma_target_t tgt_src = {
-        .inc_du = 0, // Target is peripheral, no increment
+        .inc_d1_du = 0, // Target is peripheral, no increment
         .type = DMA_DATA_TYPE_WORD, // Data type is byte
     };
-    // Size is in data units (words in this case)
-    tgt_src.size_du = length>>2;
     // Target is SPI RX FIFO
     tgt_src.ptr = (uint8_t*)fifo_ptr_rx;
     // Trigger to control the data flow
@@ -915,7 +913,7 @@ w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t l
 
     // Set up DMA destination target
     static dma_target_t tgt_dst = {
-        .inc_du = 1, // Increment by 1 data unit (word)
+        .inc_d1_du = 1, // Increment by 1 data unit (word)
         .type = DMA_DATA_TYPE_WORD, // Data type is byte
         .trig = DMA_TRIG_MEMORY, // Read-write operation to memory
     };
@@ -927,6 +925,8 @@ w25q_error_codes_t w25q128jw_read_quad_dma(uint32_t addr, void *data, uint32_t l
         .dst = &tgt_dst,
         .end = DMA_TRANS_END_POLLING,
     };
+    // Size is in data units (words in this case)
+    trans.size_d1_du = length>>2;
 
     // Validate, load and launch DMA transaction
     dma_config_flags_t res;
@@ -1476,11 +1476,9 @@ static w25q_error_codes_t dma_send_toflash(uint8_t *data, uint32_t length) {
 
     // Set up DMA source target
     static dma_target_t tgt_src = {
-        .inc_du = 1, // Increment by 1 data unit (word)
+        .inc_d1_du = 1, // Increment by 1 data unit (word)
         .type = DMA_DATA_TYPE_WORD, // Data type is word
     };
-    // Size is in data units (words in this case)
-    tgt_src.size_du = length>>2;
     // Target is data buffer
     tgt_src.ptr = data;
     // Reads from memory
@@ -1488,7 +1486,7 @@ static w25q_error_codes_t dma_send_toflash(uint8_t *data, uint32_t length) {
 
     // Set up DMA destination target
     static dma_target_t tgt_dst = {
-        .inc_du = 0, // It's a peripheral, no increment
+        .inc_d1_du = 0, // It's a peripheral, no increment
         .type = DMA_DATA_TYPE_WORD, // Data type is word
     };
     tgt_dst.trig = slot;
@@ -1502,6 +1500,8 @@ static w25q_error_codes_t dma_send_toflash(uint8_t *data, uint32_t length) {
         .win_du = 0,
         .end = DMA_TRANS_END_POLLING,
     };
+    // Size is in data units (words in this case)
+    trans.size_d1_du = length>>2;
 
     // Validate, load and launch DMA transaction
     dma_config_flags_t res;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
index 1bc8b5e4..501f69c6 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/bsp/w25q/w25q128jw.h
@@ -267,7 +267,7 @@ w25q_error_codes_t w25q128jw_erase_and_write_standard(uint32_t addr, void* data,
  * @param length number of bytes to read.
  * @return FLASH_OK if the read is successful, @ref error_codes otherwise.
 */
-w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_dma, uint8_t no_sanity_checks);
+w25q_error_codes_t w25q128jw_read_standard_dma(uint32_t addr, void *data, uint32_t length, uint8_t no_wait_init_dma, uint8_t no_sanity_checks);
 
 /**
  * @brief Read from flash at standard speed using DMA but wait for DMA in the application
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/base.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/base.h
index e0582e74..0d56792b 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/base.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/base.h
@@ -106,7 +106,7 @@ typedef enum dif_toggle {
 // * @param val A potential dif_toggle_t value.
 // * @return Bool indicating validity of toggle value.
 // */
-// inline bool dif_is_valid_toggle(dif_toggle_t val) {
+// static inline bool dif_is_valid_toggle(dif_toggle_t val) {
 //  switch (val) {
 //    case kDifToggleEnabled:
 //      return true;
@@ -123,7 +123,7 @@ typedef enum dif_toggle {
 // * @param val A dif_toggle_t value.
 // * @return Corresponding bool value.
 // */
-// inline bool dif_toggle_to_bool(dif_toggle_t val) {
+// static inline bool dif_toggle_to_bool(dif_toggle_t val) {
 //  switch (val) {
 //    case kDifToggleEnabled:
 //      return true;
@@ -140,7 +140,7 @@ typedef enum dif_toggle {
 // * @param val A bool value.
 // * @return Corresponding dif_toggle_t value.
 // */
-// inline dif_toggle_t dif_bool_to_toggle(bool val) {
+// static inline dif_toggle_t dif_bool_to_toggle(bool val) {
 //  return val ? kDifToggleEnabled : kDifToggleDisabled;
 // }
 
@@ -150,7 +150,7 @@ typedef enum dif_toggle {
 // * @param val A multi-bit bool value.
 // * @return Corresponding dif_toggle_t value.
 // */
-// inline dif_toggle_t dif_multi_bit_bool_to_toggle(multi_bit_bool_t val) {
+// static inline dif_toggle_t dif_multi_bit_bool_to_toggle(multi_bit_bool_t val) {
 //  switch (val) {
 //    case kMultiBitBool4True:
 //    case kMultiBitBool8True:
@@ -169,7 +169,7 @@ typedef enum dif_toggle {
 // * @return Corresponding `multi_bit_bool_t` value. Invalid values resolve to
 // * "false".
 // */
-// inline multi_bit_bool_t dif_toggle_to_multi_bit_bool4(dif_toggle_t val) {
+// static inline multi_bit_bool_t dif_toggle_to_multi_bit_bool4(dif_toggle_t val) {
 //  if (val == kDifToggleEnabled) {
 //    return kMultiBitBool4True;
 //  } else {
@@ -184,7 +184,7 @@ typedef enum dif_toggle {
 // * @return Corresponding `multi_bit_bool_t` value. Invalid values resolve to
 // * "false".
 // */
-// inline multi_bit_bool_t dif_toggle_to_multi_bit_bool8(dif_toggle_t val) {
+// static inline multi_bit_bool_t dif_toggle_to_multi_bit_bool8(dif_toggle_t val) {
 //  if (val == kDifToggleEnabled) {
 //    return kMultiBitBool8True;
 //  } else {
@@ -199,7 +199,7 @@ typedef enum dif_toggle {
 // * @return Corresponding `multi_bit_bool_t` value. Invalid values resolve to
 // * "false".
 // */
-// inline multi_bit_bool_t dif_toggle_to_multi_bit_bool12(dif_toggle_t val) {
+// static inline multi_bit_bool_t dif_toggle_to_multi_bit_bool12(dif_toggle_t val) {
 //  if (val == kDifToggleEnabled) {
 //    return kMultiBitBool12True;
 //  } else {
@@ -214,7 +214,7 @@ typedef enum dif_toggle {
 // * @return Corresponding `multi_bit_bool_t` value. Invalid values resolve to
 // * "false".
 // */
-// inline multi_bit_bool_t dif_toggle_to_multi_bit_bool16(dif_toggle_t val) {
+// static inline multi_bit_bool_t dif_toggle_to_multi_bit_bool16(dif_toggle_t val) {
 //  if (val == kDifToggleEnabled) {
 //    return kMultiBitBool16True;
 //  } else {
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.c
deleted file mode 100644
index b2562c0d..00000000
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include "bitfield.h"
-
-// `extern` declarations to give the inline functions in the
-// corresponding header a link location.
-
-extern uint32_t bitfield_field32_read(uint32_t bitfield,
-                                      bitfield_field32_t field);
-extern uint32_t bitfield_field32_write(uint32_t bitfield,
-                                       bitfield_field32_t field,
-                                       uint32_t value);
-
-extern bitfield_field32_t bitfield_bit32_to_field32(
-    bitfield_bit32_index_t bit_index);
-
-extern bool bitfield_bit32_read(uint32_t bitfield,
-                                bitfield_bit32_index_t bit_index);
-extern uint32_t bitfield_bit32_write(uint32_t bitfield,
-                                     bitfield_bit32_index_t bit_index,
-                                     bool value);
-
-extern int32_t bitfield_find_first_set32(int32_t bitfield);
-extern int32_t bitfield_count_leading_zeroes32(uint32_t bitfield);
-extern int32_t bitfield_count_trailing_zeroes32(uint32_t bitfield);
-extern int32_t bitfield_popcount32(uint32_t bitfield);
-extern int32_t bitfield_parity32(uint32_t bitfield);
-extern uint32_t bitfield_byteswap32(uint32_t bitfield);
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.h
index e2b81b83..19377e35 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/bitfield.h
@@ -74,7 +74,7 @@ typedef struct bitfield_field32 {
  * @return Zero-extended `field` from `bitfield`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline uint32_t bitfield_field32_read(uint32_t bitfield,
+static inline uint32_t bitfield_field32_read(uint32_t bitfield,
                                       bitfield_field32_t field) {
   return (bitfield >> field.index) & field.mask;
 }
@@ -92,7 +92,7 @@ inline uint32_t bitfield_field32_read(uint32_t bitfield,
  * @return `bitfield` with `field` set to `value`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline uint32_t bitfield_field32_write(uint32_t bitfield,
+static inline uint32_t bitfield_field32_write(uint32_t bitfield,
                                        bitfield_field32_t field,
                                        uint32_t value) {
   bitfield &= ~(field.mask << field.index);
@@ -123,7 +123,7 @@ typedef uint32_t bitfield_bit32_index_t;
  * @return A 1-bit field that corresponds to `bit_index`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline bitfield_field32_t bitfield_bit32_to_field32(
+static inline bitfield_field32_t bitfield_bit32_to_field32(
     bitfield_bit32_index_t bit_index) {
   return (bitfield_field32_t){
       .mask = 0x1, .index = bit_index,
@@ -138,7 +138,7 @@ inline bitfield_field32_t bitfield_bit32_to_field32(
  * @return `true` if the bit was one, `false` otherwise.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline bool bitfield_bit32_read(uint32_t bitfield,
+static inline bool bitfield_bit32_read(uint32_t bitfield,
                                 bitfield_bit32_index_t bit_index) {
   return bitfield_field32_read(bitfield,
                                bitfield_bit32_to_field32(bit_index)) == 0x1u;
@@ -153,7 +153,7 @@ inline bool bitfield_bit32_read(uint32_t bitfield,
  * @return `bitfield` with the `bit_index`th bit set to `value`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline uint32_t bitfield_bit32_write(uint32_t bitfield,
+static inline uint32_t bitfield_bit32_write(uint32_t bitfield,
                                      bitfield_bit32_index_t bit_index,
                                      bool value) {
   return bitfield_field32_write(bitfield, bitfield_bit32_to_field32(bit_index),
@@ -174,7 +174,7 @@ inline uint32_t bitfield_bit32_write(uint32_t bitfield,
  * @return Zero-extended `field` from `bitfield`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline uint32_t bitfield_read(uint32_t bitfield, 
+static inline uint32_t bitfield_read(uint32_t bitfield, 
                               uint32_t mask, 
                               uint32_t index) 
 {
@@ -195,7 +195,7 @@ inline uint32_t bitfield_read(uint32_t bitfield,
  * @return `bitfield` with `field` set to `value`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline uint32_t bitfield_write(uint32_t bitfield,
+static inline uint32_t bitfield_write(uint32_t bitfield,
                                        uint32_t mask, 
                                        uint32_t index,
                                        uint32_t value) 
@@ -223,7 +223,7 @@ inline uint32_t bitfield_write(uint32_t bitfield,
  * @return One plus the index of the least-significant 1-bit of `bitfield`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline int32_t bitfield_find_first_set32(int32_t bitfield) {
+static inline int32_t bitfield_find_first_set32(int32_t bitfield) {
   return __builtin_ffs(bitfield);
 }
 
@@ -247,7 +247,7 @@ inline int32_t bitfield_find_first_set32(int32_t bitfield) {
  * @return The number of leading 0-bits in `bitfield`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline int32_t bitfield_count_leading_zeroes32(uint32_t bitfield) {
+static inline int32_t bitfield_count_leading_zeroes32(uint32_t bitfield) {
   return (bitfield != 0) ? __builtin_clz(bitfield) : 32;
 }
 
@@ -271,7 +271,7 @@ inline int32_t bitfield_count_leading_zeroes32(uint32_t bitfield) {
  * @return The number of trailing 0-bits in `bitfield`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline int32_t bitfield_count_trailing_zeroes32(uint32_t bitfield) {
+static inline int32_t bitfield_count_trailing_zeroes32(uint32_t bitfield) {
   return (bitfield != 0) ? __builtin_ctz(bitfield) : 32;
 }
 
@@ -293,7 +293,7 @@ inline int32_t bitfield_count_trailing_zeroes32(uint32_t bitfield) {
  * @return The number of 1-bits in `bitfield`.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline int32_t bitfield_popcount32(uint32_t bitfield) {
+static inline int32_t bitfield_popcount32(uint32_t bitfield) {
   return __builtin_popcount(bitfield);
 }
 
@@ -315,7 +315,7 @@ inline int32_t bitfield_popcount32(uint32_t bitfield) {
  * @return The number of 1-bits in `bitfield`, modulo 2.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline int32_t bitfield_parity32(uint32_t bitfield) {
+static inline int32_t bitfield_parity32(uint32_t bitfield) {
   return __builtin_parity(bitfield);
 }
 
@@ -338,7 +338,7 @@ inline int32_t bitfield_parity32(uint32_t bitfield) {
  * @return `bitfield` with the order of bytes reversed.
  */
 BITFIELD_WARN_UNUSED_RESULT
-inline uint32_t bitfield_byteswap32(uint32_t bitfield) {
+static inline uint32_t bitfield_byteswap32(uint32_t bitfield) {
   return __builtin_bswap32(bitfield);
 }
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c
index e0234bf1..a534074e 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.c
@@ -8,9 +8,6 @@ extern "C" {
 
 #include "memory.h"
 
-extern uint32_t read_32(const void *);
-extern void write_32(uint32_t, void *);
-
 // Some symbols below are only defined for device builds. For host builds, we
 // their implementations will be provided by the host's libc implementation.
 //
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h
index 3ff64ff7..7f91de70 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/memory.h
@@ -55,7 +55,7 @@ extern "C" {
  * @param ptr a word-aligned pointer pointed to at least four bytes of memory.
  * @return the word `ptr` points to.
  */
-inline uint32_t read_32(const void *ptr) {
+static inline uint32_t read_32(const void *ptr) {
   // Both GCC and Clang optimize the code below into a single word-load on most
   // platforms. It is necessary and sufficient to indicate to the compiler that
   // the pointer points to four bytes of four-byte-aligned memory.
@@ -86,7 +86,7 @@ inline uint32_t read_32(const void *ptr) {
  * @param value the value to store.
  * @param ptr a word-aligned pointer pointed to at least four bytes of memory.
  */
-inline void write_32(uint32_t value, void *ptr) {
+static inline void write_32(uint32_t value, void *ptr) {
   // Both GCC and Clang optimize the code below into a single word-store on most
   // platforms. See the comment in `read_32()` for more implementation-private
   // information.
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c
index dff7f78a..be75927d 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.c
@@ -125,45 +125,6 @@ void mmio_region_memcpy_to_mmio32(mmio_region_t base, uint32_t offset,
   mmio_region_memcpy32(base, offset, (void *)src, len, false);
 }
 
-// `extern` declarations to give the inline functions in the
-// corresponding header a link location.
-extern uint8_t mmio_region_read8(mmio_region_t base, ptrdiff_t offset);
-extern uint32_t mmio_region_read32(mmio_region_t base, ptrdiff_t offset);
-extern void mmio_region_write8(mmio_region_t base, ptrdiff_t offset,
-                               uint8_t value);
-extern void mmio_region_write32(mmio_region_t base, ptrdiff_t offset,
-                                uint32_t value);
-extern uint32_t mmio_region_read_mask32(mmio_region_t base, ptrdiff_t offset,
-                                        uint32_t mask, uint32_t mask_index);
-extern bool mmio_region_get_bit32(mmio_region_t base, ptrdiff_t offset,
-                                  uint32_t bit_index);
-extern void mmio_region_nonatomic_clear_mask32(mmio_region_t base,
-                                               ptrdiff_t offset, uint32_t mask,
-                                               uint32_t mask_index);
-extern void mmio_region_nonatomic_set_mask32(mmio_region_t base,
-                                             ptrdiff_t offset, uint32_t mask,
-                                             uint32_t mask_index);
-extern void mmio_region_write_only_set_mask32(mmio_region_t base,
-                                              ptrdiff_t offset, uint32_t mask,
-                                              uint32_t mask_index);
-extern void mmio_region_nonatomic_set_field32(mmio_region_t base,
-                                              ptrdiff_t offset,
-                                              bitfield_field32_t field,
-                                              uint32_t value);
-extern void mmio_region_write_only_set_field32(mmio_region_t base,
-                                               ptrdiff_t offset,
-                                               bitfield_field32_t field,
-                                               uint32_t value);
-extern void mmio_region_nonatomic_clear_bit32(mmio_region_t base,
-                                              ptrdiff_t offset,
-                                              uint32_t bit_index);
-extern void mmio_region_nonatomic_set_bit32(mmio_region_t base,
-                                            ptrdiff_t offset,
-                                            uint32_t bit_index);
-extern void mmio_region_write_only_set_bit32(mmio_region_t base,
-                                             ptrdiff_t offset,
-                                             uint32_t bit_index);
-
 
 #ifdef __cplusplus
 }
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.h
index d0b94a46..51173781 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/base/mmio.h
@@ -63,7 +63,7 @@ typedef struct mmio_region { volatile void *base; } mmio_region_t;
  * @return a `mmio_region_t` value representing that region.
  */
 MMIO_WARN_UNUSED_RESULT
-inline mmio_region_t mmio_region_from_addr(uintptr_t address) {
+static inline mmio_region_t mmio_region_from_addr(uintptr_t address) {
   return (mmio_region_t){
       .base = (volatile void *)address,
   };
@@ -81,7 +81,7 @@ inline mmio_region_t mmio_region_from_addr(uintptr_t address) {
  * @return the read value.
  */
 MMIO_WARN_UNUSED_RESULT
-inline uint8_t mmio_region_read8(mmio_region_t base, ptrdiff_t offset) {
+static inline uint8_t mmio_region_read8(mmio_region_t base, ptrdiff_t offset) {
   return ((volatile uint8_t *)base.base)[offset / sizeof(uint8_t)];
 }
 
@@ -97,7 +97,7 @@ inline uint8_t mmio_region_read8(mmio_region_t base, ptrdiff_t offset) {
  * @return the read value.
  */
 MMIO_WARN_UNUSED_RESULT
-inline uint32_t mmio_region_read32(mmio_region_t base, ptrdiff_t offset) {
+static inline uint32_t mmio_region_read32(mmio_region_t base, ptrdiff_t offset) {
   return ((volatile uint32_t *)base.base)[offset / sizeof(uint32_t)];
 }
 
@@ -112,7 +112,7 @@ inline uint32_t mmio_region_read32(mmio_region_t base, ptrdiff_t offset) {
  * @param offset the offset to write at, in bytes.
  * @param value the value to write.
  */
-inline void mmio_region_write8(mmio_region_t base, ptrdiff_t offset,
+static inline void mmio_region_write8(mmio_region_t base, ptrdiff_t offset,
                                uint8_t value) {
   ((volatile uint8_t *)base.base)[offset / sizeof(uint8_t)] = value;
 }
@@ -128,7 +128,7 @@ inline void mmio_region_write8(mmio_region_t base, ptrdiff_t offset,
  * @param offset the offset to write at, in bytes.
  * @param value the value to write.
  */
-inline void mmio_region_write32(mmio_region_t base, ptrdiff_t offset,
+static inline void mmio_region_write32(mmio_region_t base, ptrdiff_t offset,
                                 uint32_t value) {
   ((volatile uint32_t *)base.base)[offset / sizeof(uint32_t)] = value;
 }
@@ -171,7 +171,7 @@ void mmio_region_write32(mmio_region_t base, ptrdiff_t offset, uint32_t value);
  */
 MMIO_WARN_UNUSED_RESULT
 MMIO_DEPRECATED
-inline uint32_t mmio_region_read_mask32(mmio_region_t base, ptrdiff_t offset,
+static inline uint32_t mmio_region_read_mask32(mmio_region_t base, ptrdiff_t offset,
                                         uint32_t mask, uint32_t mask_index) {
   return bitfield_field32_read(
       mmio_region_read32(base, offset),
@@ -192,7 +192,7 @@ inline uint32_t mmio_region_read_mask32(mmio_region_t base, ptrdiff_t offset,
  */
 MMIO_WARN_UNUSED_RESULT
 MMIO_DEPRECATED
-inline bool mmio_region_get_bit32(mmio_region_t base, ptrdiff_t offset,
+static inline bool mmio_region_get_bit32(mmio_region_t base, ptrdiff_t offset,
                                   uint32_t bit_index) {
   return bitfield_bit32_read(mmio_region_read32(base, offset), bit_index);
 }
@@ -209,7 +209,7 @@ inline bool mmio_region_get_bit32(mmio_region_t base, ptrdiff_t offset,
  * @param mask_index mask position within the selected register.
  */
 MMIO_DEPRECATED
-inline void mmio_region_nonatomic_clear_mask32(mmio_region_t base,
+static inline void mmio_region_nonatomic_clear_mask32(mmio_region_t base,
                                                ptrdiff_t offset, uint32_t mask,
                                                uint32_t mask_index) {
   uint32_t register_value = mmio_region_read32(base, offset);
@@ -231,7 +231,7 @@ inline void mmio_region_nonatomic_clear_mask32(mmio_region_t base,
  * @param mask_index mask position within the selected register.
  */
 MMIO_DEPRECATED
-inline void mmio_region_nonatomic_set_mask32(mmio_region_t base,
+static inline void mmio_region_nonatomic_set_mask32(mmio_region_t base,
                                              ptrdiff_t offset, uint32_t mask,
                                              uint32_t mask_index) {
   uint32_t register_value = mmio_region_read32(base, offset);
@@ -253,7 +253,7 @@ inline void mmio_region_nonatomic_set_mask32(mmio_region_t base,
  * @param mask_index mask position within the selected register.
  */
 MMIO_DEPRECATED
-inline void mmio_region_write_only_set_mask32(mmio_region_t base,
+static inline void mmio_region_write_only_set_mask32(mmio_region_t base,
                                               ptrdiff_t offset, uint32_t mask,
                                               uint32_t mask_index) {
   uint32_t register_value = 0x0u;
@@ -278,7 +278,7 @@ inline void mmio_region_write_only_set_mask32(mmio_region_t base,
  * @param value value to set the field to.
  */
 MMIO_DEPRECATED
-inline void mmio_region_nonatomic_set_field32(mmio_region_t base,
+static inline void mmio_region_nonatomic_set_field32(mmio_region_t base,
                                               ptrdiff_t offset,
                                               bitfield_field32_t field,
                                               uint32_t value) {
@@ -299,7 +299,7 @@ inline void mmio_region_nonatomic_set_field32(mmio_region_t base,
  * @param value value to set field to.
  */
 MMIO_DEPRECATED
-inline void mmio_region_write_only_set_field32(mmio_region_t base,
+static inline void mmio_region_write_only_set_field32(mmio_region_t base,
                                                ptrdiff_t offset,
                                                bitfield_field32_t field,
                                                uint32_t value) {
@@ -319,7 +319,7 @@ inline void mmio_region_write_only_set_field32(mmio_region_t base,
  * @param bit_index the bit to clear.
  */
 MMIO_DEPRECATED
-inline void mmio_region_nonatomic_clear_bit32(mmio_region_t base,
+static inline void mmio_region_nonatomic_clear_bit32(mmio_region_t base,
                                               ptrdiff_t offset,
                                               uint32_t bit_index) {
   uint32_t register_value = mmio_region_read32(base, offset);
@@ -337,7 +337,7 @@ inline void mmio_region_nonatomic_clear_bit32(mmio_region_t base,
  * @param bit_index the bit to set.
  */
 MMIO_DEPRECATED
-inline void mmio_region_nonatomic_set_bit32(mmio_region_t base,
+static inline void mmio_region_nonatomic_set_bit32(mmio_region_t base,
                                             ptrdiff_t offset,
                                             uint32_t bit_index) {
   uint32_t register_value = mmio_region_read32(base, offset);
@@ -358,7 +358,7 @@ inline void mmio_region_nonatomic_set_bit32(mmio_region_t base,
  * @param bit_index the bit to set.
  */
 MMIO_DEPRECATED
-inline void mmio_region_write_only_set_bit32(mmio_region_t base,
+static inline void mmio_region_write_only_set_bit32(mmio_region_t base,
                                              ptrdiff_t offset,
                                              uint32_t bit_index) {
   uint32_t register_value = 0x0u;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S.tpl b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S.tpl
index 72d2b2e6..8b8ccfb7 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/crt/crt0.S.tpl
@@ -1,153 +1,153 @@
-/* Copyright (c) 2017  SiFive Inc. All rights reserved.
- * Copyright (c) 2019  ETH Zürich and University of Bologna
- * Copyright (c) 2022 EPFL
- * This copyrighted material is made available to anyone wishing to use,
- * modify, copy, or redistribute it subject to the terms and conditions
- * of the FreeBSD License.   This program is distributed in the hope that
- * it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
- * including the implied warranties of MERCHANTABILITY or FITNESS FOR
- * A PARTICULAR PURPOSE.  A copy of this license is available at
- * http://www.opensource.org/licenses.
- */
-
-#include "x-heep.h"
-#include "core_v_mini_mcu.h"
-#include "soc_ctrl_regs.h"
-
-#define RAMSIZE_COPIEDBY_BOOTROM 2048
-
-/* Entry point for bare metal programs */
-.section .text.start
-.global _start
-.type _start, @function
-
-_start:
-/* initialize global pointer */
-.option push
-.option norelax
-1: auipc gp, %pcrel_hi(__global_pointer$)
-   addi  gp, gp, %pcrel_lo(1b)
-.option pop
-
-/* initialize stack pointer */
-   la sp, _sp
-
-/* set the frequency */
-   li a0, SOC_CTRL_START_ADDRESS
-   li a2, REFERENCE_CLOCK_Hz
-   sw a2, SOC_CTRL_SYSTEM_FREQUENCY_HZ_REG_OFFSET(a0)
-
-#ifdef EXTERNAL_CRTO
-   #include "external_crt0.S"
-#endif
-
-#ifdef FLASH_LOAD
-
-    call w25q128jw_init_crt0
-
-    // This assumes ram base address is 0x00000000 and the section .text stars from ram0 (in the first RAMSIZE_COPIEDBY_BOOTROM Byte)
-    li     s1, RAMSIZE_COPIEDBY_BOOTROM
-    li     s2, FLASH_MEM_START_ADDRESS
-
-    // copy the remaining (if any) text and data sections //
-    // Setup the in/out pointers and copy size knowing 1KiB as already been copied
-    mv     a0, s2 // src ptr (flash)
-    add   a0, a0, s1
-
-    la     a1, _etext
-    // Skip if everything has already been copied, and copy the data section
-    blt    a1, s1, _load_data_section
-
-    // copy size in bytes, i.e. _etext - RAMSIZE_COPIEDBY_BOOTROM
-    sub   a2, a1, s1
-
-    // dst ptr (ram)
-    mv     a1, s1
-
-    // copy the remaining data --> w25q128jw_read_standard(a0 is src addr, a1 is dest ptr data, a2 is length)
-
-    // this sub is redundat as we could have simply set a0 to RAMSIZE_COPIEDBY_BOOTROM+0x0,
-    // but like this is more readable as we set the FLASH address as memory mapped to FLASH_MEM_START_ADDRESS, and then remove the offset
-    // as required bz the w25q128jw_read_standard function
-    sub    a0,a0,s2
-    call w25q128jw_read_standard
-
-% for i, section in enumerate(xheep.iter_linker_sections()):
-% if section.name != "code":
-_load_${section.name}_section:
-    // src ptr
-    la     a0, _lma_${section.name}_start
-    // dst ptr
-    la     a1, __${section.name}_start
-    // copy size in bytes
-    la     a2, _lma_${section.name}_end
-    sub    a2, a2, a0
-
-    bltz   a2, _load_${section.name}_section_end // dont do anything if you do not have something in ${section.name}
-
-    sub    a0,a0,s2
-    call w25q128jw_read_standard
-_load_${section.name}_section_end:
-
-% endif
-% endfor
-
-#endif
-
-/* clear the bss segment */
-_init_bss:
-    la     a0, __bss_start
-    la     a2, __bss_end
-    sub    a2, a2, a0
-    li     a1, 0
-    call   memset
-
-#ifdef FLASH_EXEC
-/* copy initialized data sections from flash to ram (to be verified, copied from picosoc)*/
-    la a0, _sidata
-    la a1, _sdata
-    la a2, _edata
-    bge a1, a2, end_init_data
-    loop_init_data:
-    lw a3, 0(a0)
-    sw a3, 0(a1)
-    addi a0, a0, 4
-    addi a1, a1, 4
-    blt a1, a2, loop_init_data
-    end_init_data:
-#endif
-
-/* set vector table address and vectored mode */
-    la a0, __vector_start
-    ori a0, a0, 0x1
-    csrw mtvec, a0
-
-/* new-style constructors and destructors */
-    la a0, __libc_fini_array
-    call atexit
-    call __libc_init_array
-
-/* call main */
-    lw a0, 0(sp)                    /* a0 = argc */
-    addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
-    li a2, 0                        /* a2 = envp = NULL */
-    call main
-    tail exit
-
-.size  _start, .-_start
-
-.global _init
-.type   _init, @function
-.global _fini
-.type   _fini, @function
-_init:
-    call init
-_fini:
- /* These don't have to do anything since we use init_array/fini_array. Prevent
-    missing symbol error */
-    ret
-.size  _init, .-_init
-.size _fini, .-_fini
-
-
-
+/* Copyright (c) 2017  SiFive Inc. All rights reserved.
+ * Copyright (c) 2019  ETH Zürich and University of Bologna
+ * Copyright (c) 2022 EPFL
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the FreeBSD License.   This program is distributed in the hope that
+ * it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
+ * including the implied warranties of MERCHANTABILITY or FITNESS FOR
+ * A PARTICULAR PURPOSE.  A copy of this license is available at
+ * http://www.opensource.org/licenses.
+ */
+
+#include "x-heep.h"
+#include "core_v_mini_mcu.h"
+#include "soc_ctrl_regs.h"
+
+#define RAMSIZE_COPIEDBY_BOOTROM 2048
+
+/* Entry point for bare metal programs */
+.section .text.start
+.global _start
+.type _start, @function
+
+_start:
+/* initialize global pointer */
+.option push
+.option norelax
+1: auipc gp, %pcrel_hi(__global_pointer$)
+   addi  gp, gp, %pcrel_lo(1b)
+.option pop
+
+/* initialize stack pointer */
+   la sp, _sp
+
+/* set the frequency */
+   li a0, SOC_CTRL_START_ADDRESS
+   li a2, REFERENCE_CLOCK_Hz
+   sw a2, SOC_CTRL_SYSTEM_FREQUENCY_HZ_REG_OFFSET(a0)
+
+#ifdef EXTERNAL_CRTO
+   #include "external_crt0.S"
+#endif
+
+#ifdef FLASH_LOAD
+
+    call w25q128jw_init_crt0
+
+    // This assumes ram base address is 0x00000000 and the section .text stars from ram0 (in the first RAMSIZE_COPIEDBY_BOOTROM Byte)
+    li     s1, RAMSIZE_COPIEDBY_BOOTROM
+    li     s2, FLASH_MEM_START_ADDRESS
+
+    // copy the remaining (if any) text and data sections //
+    // Setup the in/out pointers and copy size knowing 1KiB as already been copied
+    mv     a0, s2 // src ptr (flash)
+    add   a0, a0, s1
+
+    la     a1, _etext
+    // Skip if everything has already been copied, and copy the data section
+    blt    a1, s1, _load_data_section
+
+    // copy size in bytes, i.e. _etext - RAMSIZE_COPIEDBY_BOOTROM
+    sub   a2, a1, s1
+
+    // dst ptr (ram)
+    mv     a1, s1
+
+    // copy the remaining data --> w25q128jw_read_standard(a0 is src addr, a1 is dest ptr data, a2 is length)
+
+    // this sub is redundat as we could have simply set a0 to RAMSIZE_COPIEDBY_BOOTROM+0x0,
+    // but like this is more readable as we set the FLASH address as memory mapped to FLASH_MEM_START_ADDRESS, and then remove the offset
+    // as required bz the w25q128jw_read_standard function
+    sub    a0,a0,s2
+    call w25q128jw_read_standard
+
+% for i, section in enumerate(xheep.iter_linker_sections()):
+% if section.name != "code":
+_load_${section.name}_section:
+    // src ptr
+    la     a0, _lma_${section.name}_start
+    // dst ptr
+    la     a1, __${section.name}_start
+    // copy size in bytes
+    la     a2, _lma_${section.name}_end
+    sub    a2, a2, a0
+
+    bltz   a2, _load_${section.name}_section_end // dont do anything if you do not have something in ${section.name}
+
+    sub    a0,a0,s2
+    call w25q128jw_read_standard
+_load_${section.name}_section_end:
+
+% endif
+% endfor
+
+#endif
+
+/* clear the bss segment */
+_init_bss:
+    la     a0, __bss_start
+    la     a2, __bss_end
+    sub    a2, a2, a0
+    li     a1, 0
+    call   memset
+
+#ifdef FLASH_EXEC
+/* copy initialized data sections from flash to ram (to be verified, copied from picosoc)*/
+    la a0, _sidata
+    la a1, _sdata
+    la a2, _edata
+    bge a1, a2, end_init_data
+    loop_init_data:
+    lw a3, 0(a0)
+    sw a3, 0(a1)
+    addi a0, a0, 4
+    addi a1, a1, 4
+    blt a1, a2, loop_init_data
+    end_init_data:
+#endif
+
+/* set vector table address and vectored mode */
+    la a0, __vector_start
+    ori a0, a0, 0x1
+    csrw mtvec, a0
+
+/* new-style constructors and destructors */
+    la a0, __libc_fini_array
+    call atexit
+    call __libc_init_array
+
+/* call main */
+    lw a0, 0(sp)                    /* a0 = argc */
+    addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
+    li a2, 0                        /* a2 = envp = NULL */
+    call main
+    tail exit
+
+.size  _start, .-_start
+
+.global _init
+.type   _init, @function
+.global _fini
+.type   _fini, @function
+_init:
+    call init
+_fini:
+ /* These don't have to do anything since we use init_array/fini_array. Prevent
+    missing symbol error */
+    ret
+.size  _init, .-_init
+.size _fini, .-_fini
+
+
+
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
index 52097770..3d102314 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.c
@@ -125,7 +125,7 @@ typedef enum
  * @return A configuration flags mask. Each individual flag can be accessed with
  * a bitwise AND ( ret & DMA_CONFIG_* ).
  */
-dma_config_flags_t validate_target( dma_target_t *p_tgt );
+dma_config_flags_t validate_target( dma_target_t *p_tgt, dma_trans_t *p_trans );
 
 /**
  * @brief Creates an environment where targets can be added. An environment
@@ -159,17 +159,17 @@ static inline uint8_t get_misalignment_b(   uint8_t         *p_ptr,
  * @param p_start Pointer to the beginning of the region.
  * @param p_end Pointer to the last byte of the environment.
  * @param p_type The data type to be transferred.
- * @param p_size_du The number of data units to be transferred. Must be
+ * @param p_size_d1_du The number of data units to be transferred. Must be
  * non-zero.
- * @param p_inc_du The size in data units of each increment.
+ * @param p_inc_d1_du The size in data units of each increment.
  * @retval 1 There is an outbound.
  * @retval 0 There is NOT an outbound.
  */
 static inline uint8_t is_region_outbound_1D(   uint8_t  *p_start,
                                             uint8_t  *p_end,
                                             uint32_t p_type,
-                                            uint32_t p_size_du,
-                                            uint32_t p_inc_du );
+                                            uint32_t p_size_d1_du,
+                                            uint32_t p_inc_d1_du );
 
 /**
  * @brief Determines whether a given region will fit before the end of an
@@ -177,9 +177,9 @@ static inline uint8_t is_region_outbound_1D(   uint8_t  *p_start,
  * @param p_start Pointer to the beginning of the region.
  * @param p_end Pointer to the last byte of the environment.
  * @param p_type The data type to be transferred.
- * @param p_size_du The number of data units to be transferred. Must be
+ * @param p_size_d1_du The number of data units to be transferred. Must be
  * non-zero.
- * @param p_inc_du The size in data units of each increment.
+ * @param p_inc_d1_du The size in data units of each increment.
  * @retval 1 There is an outbound.
  * @retval 0 There is NOT an outbound.
  */
@@ -431,8 +431,8 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
      * A successful target validation has to be done before loading it to the
      * DMA.
      */
-    uint8_t errorSrc = validate_target( p_trans->src );
-    uint8_t errorDst = validate_target( p_trans->dst );
+    uint8_t errorSrc = validate_target( p_trans->src, p_trans);
+    uint8_t errorDst = validate_target( p_trans->dst, p_trans);
 
     /*
      * If there are any errors or warnings in the valdiation of the targets,
@@ -538,12 +538,6 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
     /* The flags are cleaned in case the structure was used before.*/
     p_trans->flags = DMA_CONFIG_OK;
 
-    /* The copy size of the source (in data units -of the source-) is
-    transformed to bytes, to be used as default size.*/
-    uint8_t dataSize_b = DMA_DATA_TYPE_2_SIZE(p_trans->src->type);
-    p_trans->size_b = p_trans->src->size_du * dataSize_b;
-    p_trans->size_d2_b = p_trans->src->size_d2_du * dataSize_b;
-
     p_trans->src_type = p_trans->src->type;
     p_trans->dst_type = p_trans->dst->type;
 
@@ -645,8 +639,8 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
              * No further operations are done to prevent corrupting
              * information that could be useful for debugging purposes.
              */
-            if(    ( p_trans->src->inc_du > 1 )
-                || ( p_trans->dst->inc_du > 1 ) )
+            if(    ( p_trans->src->inc_d1_du > 1 )
+                || ( p_trans->dst->inc_d1_du > 1 ) )
             {
                 p_trans->flags |= DMA_CONFIG_DISCONTINUOUS;
                 p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
@@ -682,7 +676,7 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
          * No further operations are done to prevent corrupting information
          * that could be useful for debugging purposes.
          */
-        if(p_trans->src->size_du == 0 || (p_trans->dim == DMA_DIM_CONF_2D && p_trans->src->size_d2_du == 0))
+        if(p_trans->size_d1_du == 0 || (p_trans->dim == DMA_DIM_CONF_2D && p_trans->size_d2_du == 0))
         {
             p_trans->flags |= DMA_CONFIG_SRC;
             p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
@@ -724,8 +718,8 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
                                         p_trans->dst->ptr,
                                         p_trans->dst->env->end,
                                         p_trans->dst_type,
-                                        p_trans->src->size_du,
-                                        p_trans->dst->inc_du );
+                                        p_trans->size_d1_du,
+                                        p_trans->dst->inc_d1_du );
             if( isOutb )
             {
                 p_trans->flags |= DMA_CONFIG_DST;
@@ -749,7 +743,7 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
          * this would not cause any error, the transaction is rejected because
          * it is likely a mistake.
          */
-        if( p_trans->win_du > p_trans->size_b )
+        if( p_trans->win_du > p_trans->size_d1_du )
         {
             p_trans->flags |= DMA_CONFIG_WINDOW_SIZE;
             p_trans->flags |= DMA_CONFIG_CRITICAL_ERROR;
@@ -767,7 +761,7 @@ dma_config_flags_t dma_validate_transaction(    dma_trans_t        *p_trans,
          * certainty that an real error will occur.
          */
         uint32_t threshold = dma_window_ratio_warning_threshold();
-        uint32_t ratio = p_trans->size_b / p_trans->win_du;
+        uint32_t ratio = p_trans->size_d1_du / p_trans->win_du;
         if(     p_trans->win_du
             &&  threshold
             &&  ( ratio > threshold) )
@@ -870,16 +864,17 @@ dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans)
     if (p_trans->dim == DMA_DIM_CONF_1D && (p_trans->pad_left_du != 0 || p_trans->pad_right_du != 0))
     {
         p_trans->dim = DMA_DIM_CONF_2D;
-        p_trans->size_d2_b = DMA_DATA_TYPE_2_SIZE( p_trans->dst_type );
+        /* Set the d2 size and increment to just the minimum */
+        p_trans->size_d2_du = 1;
         p_trans->src->inc_d2_du = DMA_DATA_TYPE_2_SIZE( p_trans->dst_type );
         
-        write_register( dma_subsys_per[channel].trans->pad_left_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+        write_register( dma_subsys_per[channel].trans->pad_left_du,
                         DMA_PAD_LEFT_REG_OFFSET,
                         DMA_PAD_LEFT_PAD_MASK,
                         DMA_PAD_LEFT_PAD_OFFSET,
                         dma_subsys_per[channel].peri);
 
-        write_register( dma_subsys_per[channel].trans->pad_right_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+        write_register( dma_subsys_per[channel].trans->pad_right_du,
                         DMA_PAD_RIGHT_REG_OFFSET,
                         DMA_PAD_RIGHT_PAD_MASK,
                         DMA_PAD_RIGHT_PAD_OFFSET,
@@ -887,31 +882,30 @@ dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans)
     }
     else if (p_trans->dim == DMA_DIM_CONF_2D)
     {
-        write_register( dma_subsys_per[channel].trans->pad_top_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+        write_register( dma_subsys_per[channel].trans->pad_top_du,
                         DMA_PAD_TOP_REG_OFFSET,
                         DMA_PAD_TOP_PAD_MASK,
                         DMA_PAD_TOP_PAD_OFFSET,
                         dma_subsys_per[channel].peri);
 
-        write_register( dma_subsys_per[channel].trans->pad_bottom_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+        write_register( dma_subsys_per[channel].trans->pad_bottom_du,
                         DMA_PAD_BOTTOM_REG_OFFSET,
                         DMA_PAD_BOTTOM_PAD_MASK,
                         DMA_PAD_BOTTOM_PAD_OFFSET,
                         dma_subsys_per[channel].peri);
 
-        write_register( dma_subsys_per[channel].trans->pad_left_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+        write_register( dma_subsys_per[channel].trans->pad_left_du,
                         DMA_PAD_LEFT_REG_OFFSET,
                         DMA_PAD_LEFT_PAD_MASK,
                         DMA_PAD_LEFT_PAD_OFFSET,
                         dma_subsys_per[channel].peri);
 
-        write_register( dma_subsys_per[channel].trans->pad_right_du * DMA_DATA_TYPE_2_SIZE( p_trans->src_type ),
+        write_register( dma_subsys_per[channel].trans->pad_right_du,
                         DMA_PAD_RIGHT_REG_OFFSET,
                         DMA_PAD_RIGHT_PAD_MASK,
                         DMA_PAD_RIGHT_PAD_OFFSET,
                         dma_subsys_per[channel].peri);
     }
-
     /*
      * SET THE POINTERS
      */
@@ -999,7 +993,7 @@ dma_config_flags_t dma_load_transaction( dma_trans_t *p_trans)
 
     dma_subsys_per[channel].peri->WINDOW_SIZE =   dma_subsys_per[channel].trans->win_du
                             ? dma_subsys_per[channel].trans->win_du
-                            : dma_subsys_per[channel].trans->size_b;
+                            : dma_subsys_per[channel].trans->size_d1_du;
 
     /* 
      * SET THE DIMENSIONALITY
@@ -1101,7 +1095,7 @@ dma_config_flags_t dma_launch( dma_trans_t *p_trans)
 
     if(dma_subsys_per[channel].trans->dim == DMA_DIM_CONF_2D)
     {
-        write_register( dma_subsys_per[channel].trans->size_d2_b,
+        write_register( dma_subsys_per[channel].trans->size_d2_du,
                         DMA_SIZE_D2_REG_OFFSET,
                         DMA_SIZE_D2_SIZE_MASK,
                         DMA_SIZE_D2_SIZE_OFFSET,
@@ -1109,7 +1103,7 @@ dma_config_flags_t dma_launch( dma_trans_t *p_trans)
                       );
     }
 
-    write_register( dma_subsys_per[channel].trans->size_b,
+    write_register( dma_subsys_per[channel].trans->size_d1_du,
                     DMA_SIZE_D1_REG_OFFSET,
                     DMA_SIZE_D1_SIZE_MASK,
                     DMA_SIZE_D1_SIZE_OFFSET,
@@ -1202,7 +1196,7 @@ __attribute__((weak, optimize("O0"))) uint8_t dma_window_ratio_warning_threshold
 /**                                                                        **/
 /****************************************************************************/
 
-dma_config_flags_t validate_target( dma_target_t *p_tgt )
+dma_config_flags_t validate_target( dma_target_t *p_tgt, dma_trans_t *p_trans )
 {
     /* Flags variable to pass encountered errors. */
     dma_config_flags_t flags = DMA_CONFIG_OK;
@@ -1211,14 +1205,14 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
      */
 
     /* Increment can be 0 when a trigger is used. */
-    DMA_STATIC_ASSERT( p_tgt->inc_du   >= 0  &&  p_tgt->inc_du < 64 , "Increment not valid");
+    DMA_STATIC_ASSERT( p_tgt->inc_d1_du   >= 0  &&  p_tgt->inc_d1_du < 64 , "Increment not valid");
     /* Increment on D2 has to be 0 for 1D operations */
     DMA_STATIC_ASSERT( p_tgt->inc_d2_du  >= 0  &&  p_tgt->inc_d2_du < 4194304 , "Increment d2 not valid");
     /* The size could be 0 if the target is only going to be used as a
     destination. */
-    DMA_STATIC_ASSERT( p_tgt->size_du  >= 0 && p_tgt->size_du  < 65536 , "Size not valid");
+    DMA_STATIC_ASSERT( p_tgt->size_d1_du  >= 0 && p_tgt->size_d1_du  < 65536 , "Size not valid");
     /* The size can be 0 or 1 if the target is involved in a 1D padded transaction */
-    DMA_STATIC_ASSERT( p_tgt->size_d2_du >= 0 && p_tgt->size_du  < 65536  , "Size d2 not valid");
+    DMA_STATIC_ASSERT( p_tgt->size_d2_du >= 0 && p_tgt->size_d1_du  < 65536  , "Size d2 not valid");
     /* The data type must be a valid type */
     DMA_STATIC_ASSERT( p_tgt->type     < DMA_DATA_TYPE__size , "Source type not valid");
     /* The trigger must be among the valid trigger values. */
@@ -1239,32 +1233,29 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
         /* Check if the environment was properly formed.*/
         flags |= validate_environment( p_tgt->env );
         /*
-         * Check if the target selected size goes beyond the boundaries of
+         * Check if the transaction size goes beyond the boundaries of
          * the environment.
-         * This is only analyzed if a size was defined.
          */
-        if( p_tgt->size_du != 0 )
+        
+        if( p_trans->size_d2_du != 0 )
         {
-            uint8_t isOutb = is_region_outbound_1D(  p_tgt->ptr,
+            uint8_t isOutb = is_region_outbound_2D(  p_tgt->ptr,
                                           p_tgt->env->end,
                                           p_tgt->type,
-                                          p_tgt->size_du,
-                                          p_tgt->inc_du );
+                                          p_trans->size_d1_du,
+                                          p_trans->size_d2_du,
+                                          p_tgt->inc_d1_du,
+                                          p_tgt->inc_d2_du);
             if( isOutb )
             {
                 flags |= DMA_CONFIG_OUTBOUNDS;
             }
-        }
-        /* Do the same but for 2D case */
-        if( p_tgt->size_d2_du != 0 )
-        {
-            uint8_t isOutb = is_region_outbound_2D(  p_tgt->ptr,
+        } else {
+            uint8_t isOutb = is_region_outbound_1D(  p_tgt->ptr,
                                           p_tgt->env->end,
                                           p_tgt->type,
-                                          p_tgt->size_du,
-                                          p_tgt->size_d2_du,
-                                          p_tgt->inc_du,
-                                          p_tgt->inc_d2_du);
+                                          p_trans->size_d1_du,
+                                          p_tgt->inc_d1_du );
             if( isOutb )
             {
                 flags |= DMA_CONFIG_OUTBOUNDS;
@@ -1290,7 +1281,7 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
 
     if( p_tgt->trig == DMA_TRIG_MEMORY ){ /* If it is a memory region. */
         /* It should have an increment. */
-        if( ( p_tgt->inc_du == 0 ) ){
+        if( ( p_tgt->inc_d1_du == 0 ) ){
             flags |= DMA_CONFIG_INCOMPATIBLE;
         }
     }
@@ -1298,7 +1289,7 @@ dma_config_flags_t validate_target( dma_target_t *p_tgt )
     {
         /* It should not have neither an environment nor an increment. */
         if( (     (p_tgt->env != NULL)
-              ||  ( p_tgt->inc_du != 0 ) ) )
+              ||  ( p_tgt->inc_d1_du != 0 ) ) )
         {
             flags |= DMA_CONFIG_INCOMPATIBLE;
         }
@@ -1403,8 +1394,8 @@ static inline uint8_t get_misalignment_b(   uint8_t         *p_ptr,
 static inline uint8_t is_region_outbound_1D(   uint8_t  *p_start,
                                             uint8_t  *p_end,
                                             uint32_t p_type,
-                                            uint32_t p_size_du,
-                                            uint32_t p_inc_du )
+                                            uint32_t p_size_d1_du,
+                                            uint32_t p_inc_d1_du )
 {
   /* 000 = A data unit to be copied
    * xxx = A data unit to be skipped
@@ -1420,7 +1411,7 @@ static inline uint8_t is_region_outbound_1D(   uint8_t  *p_start,
    * If the environment ends before the last affected byte, then there is
    * outbound writing and the function returns 1.
    */
-    uint32_t affectedUnits      = ( p_size_du - 1 ) * p_inc_du + 1;
+    uint32_t affectedUnits      = ( p_size_d1_du - 1 ) * p_inc_d1_du + 1;
     uint32_t rangeSize          = DMA_DATA_TYPE_2_SIZE(p_type) * affectedUnits;
     uint32_t lastByteInsideRange = (uint32_t)p_start + rangeSize -1;
     return ( p_end < lastByteInsideRange );
@@ -1467,8 +1458,8 @@ static inline uint32_t get_increment_b_1D( dma_target_t * p_tgt,
         */
         if( inc_b == 0 )
         {
-            uint8_t dataSize_b = DMA_DATA_TYPE_2_SIZE( p_tgt->type );
-            inc_b = ( p_tgt->inc_du * dataSize_b );
+            uint8_t dataSize_d1_du = DMA_DATA_TYPE_2_SIZE( p_tgt->type );
+            inc_b = ( p_tgt->inc_d1_du * dataSize_d1_du );
         }
     }
     return inc_b;
@@ -1493,8 +1484,8 @@ static inline uint32_t get_increment_b_2D( dma_target_t * p_tgt,
         */
         if( inc_b == 0 )
         {
-            uint8_t dataSize_b = DMA_DATA_TYPE_2_SIZE( p_tgt->type );
-            inc_b = ( p_tgt->inc_d2_du * dataSize_b );
+            uint8_t dataSize_d1_du = DMA_DATA_TYPE_2_SIZE( p_tgt->type );
+            inc_b = ( p_tgt->inc_d2_du * dataSize_d1_du );
         }
     }
     return inc_b;
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
index ad87434a..98a4f0f4 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma.h
@@ -324,15 +324,11 @@ typedef struct
     if the target is a peripheral. */
     uint8_t*                ptr;     /*!< Pointer to the start address from/to
     where data will be copied/pasted. */
-    uint8_t                inc_du;  /*!< How much the pointer will increase
+    uint8_t                inc_d1_du;  /*!< How much the pointer will increase
     every time a read/write operation is done. It is a multiple of the data units.
     Can be left blank if the target is a peripheral. */
     uint32_t                inc_d2_du; /*!< How much the D2 pointer will increase
     every time the DMA finishes to read a #D1 of data units. */
-    uint16_t                size_du; /*!< The size (in data units) of the data to
-    be copied. Can be left blank if the target will only be used as destination.*/
-    uint16_t                size_d2_du; /*!< The size (in data units) of the data
-    to be copied along D2.*/
     dma_data_type_t         type;    /*!< The type of data to be transferred.
     Can be left blank if the target will only be used as destination. */
     dma_trigger_slot_mask_t trig;    /*!< If the target is a peripheral, a
@@ -356,10 +352,8 @@ typedef struct
     copied. - only valid in address mode */
     uint16_t            inc_b;  /*!< A common increment in case both targets
     need to use one same increment. */
-    uint32_t            size_b; /*!< The size of the transfer along D1, in bytes (in
-    contrast, the size stored in the targets is in data units). */
-    uint32_t            size_d2_b; /*!< The size of the transfer along D2, in bytes (in
-    contrast, the size stored in the targets is in data units). */
+    uint32_t            size_d1_du; /*!< The size of the transfer along D1, in data units */
+    uint32_t            size_d2_du; /*!< The size of the transfer along D2, in data units */
     dma_dim_t           dim; /*!< Sets the dimensionality of the
     DMA, either 1D or 2D. */
     uint8_t             pad_top_du; /*!< Padding at the top of the 2D transfer. */
@@ -421,7 +415,7 @@ __attribute__((optimize("O0"))) void fic_irq_dma(void);
  */
 /* @ToDo: Consider changing the "mask" parameter for a bitfield definition
 (see dma_regs.h) */
-inline void write_register( uint32_t  p_val,
+static inline void write_register( uint32_t  p_val,
                                   uint32_t  p_offset,
                                   uint32_t  p_mask,
                                   uint8_t   p_sel,
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h
index 408b23ae..c0ef3797 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/dma/dma_regs.h
@@ -25,15 +25,16 @@ extern "C" {
 // Addess data pointer (word aligned)
 #define DMA_ADDR_PTR_REG_OFFSET 0x8
 
-// Number of bytes to copy from, defined with respect to the first dimension
-// - Once a value is written, the copy starts
+// Number of elements to copy from, defined with respect to the first
+// dimension - Once a value is written, the copy starts
 #define DMA_SIZE_D1_REG_OFFSET 0xc
 #define DMA_SIZE_D1_SIZE_MASK 0xffff
 #define DMA_SIZE_D1_SIZE_OFFSET 0
 #define DMA_SIZE_D1_SIZE_FIELD \
   ((bitfield_field32_t) { .mask = DMA_SIZE_D1_SIZE_MASK, .index = DMA_SIZE_D1_SIZE_OFFSET })
 
-// Number of bytes to copy from, defined with respect to the second dimension
+// Number of elements to copy from, defined with respect to the second
+// dimension
 #define DMA_SIZE_D2_REG_OFFSET 0x10
 #define DMA_SIZE_D2_SIZE_MASK 0xffff
 #define DMA_SIZE_D2_SIZE_OFFSET 0
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.c
new file mode 100644
index 00000000..af7e20f4
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.c
@@ -0,0 +1,234 @@
+/*
+    Copyright EPFL contributors.
+    Licensed under the Apache License, Version 2.0, see LICENSE for details.
+    SPDX-License-Identifier: Apache-2.0
+
+    Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+                            <tommaso.terzano@gmail.com>
+
+    Info: This simple HAL is used to load the im2col SPC and to run it.
+*/
+
+#include "im2col.h"
+
+uint32_t im2col_spc_base_addr;
+
+void handler_irq_im2col_spc( void )
+{
+  /* Read the IFR to lower the interrupt flag */
+  * (volatile uint32_t * )(im2col_spc_base_addr + IM2COL_SPC_SPC_IFR_REG_OFFSET);
+  return;
+}
+
+void im2col_spc_init(uint32_t im2col_spc_base_addr_i)
+{
+  if (im2col_spc_base_addr_i == NULL)
+  {
+    im2col_spc_base_addr = EXT_PERIPHERAL_START_ADDRESS + 0x4000;
+  } else {
+    im2col_spc_base_addr = im2col_spc_base_addr_i;
+  }
+}
+
+/* Simple function to extract the channel from the channel mask */
+int get_channel_number(uint32_t mask) {
+    int channel = 0;
+    
+    // Check the position of the first set bit
+    while (mask > 0) {
+        channel++;
+        if (mask & 1) {  // If the least significant bit is set
+            return channel - 1;
+        }
+        mask >>= 1;  // Right shift the mask to check the next bit
+    }
+    
+    // If no bit is set, return -1 indicating no valid channel
+    return -1;
+}
+
+int im2col_spc_run(im2col_trans_t trans){
+
+  /* Initializing PLIC */
+  if(plic_Init()) 
+  {
+      return EXIT_FAILURE;
+  };
+
+  if(plic_irq_set_priority(EXT_INTR_2, 1)) 
+  {
+      return EXIT_FAILURE;
+  };
+
+  if(plic_irq_set_enabled(EXT_INTR_2, kPlicToggleEnabled)) 
+  {
+      return EXIT_FAILURE;
+  };
+
+  plic_assign_external_irq_handler(EXT_INTR_2, &handler_irq_im2col_spc);
+
+  /* Enable global interrupt for machine-level interrupts */
+  CSR_SET_BITS(CSR_REG_MSTATUS, 0x8);
+
+  /* Set mie.MEIE bit to one to enable machine-level external interrupts */
+  const uint32_t mask = 1 << 11;
+  CSR_SET_BITS(CSR_REG_MIE, mask);
+
+  dma_init(NULL);
+
+  /* Write the DMA channel mask that the SPC has access to */
+  write_register( trans.ch_mask,
+                  IM2COL_SPC_SPC_CH_MASK_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  /* Write the offset of the DMA channel the SPC has access to */
+  write_register( get_channel_number(trans.ch_mask) * DMA_CH_SIZE + DMA_START_ADDRESS,
+                  IM2COL_SPC_SPC_CH_OFFSET_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  /* Write the source */
+  write_register( trans.src,
+                  IM2COL_SPC_SRC_PTR_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  /* Write the destination */
+  write_register( trans.dst,
+                  IM2COL_SPC_DST_PTR_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  /* Write the datatype */
+  write_register( trans.datatype,
+                  IM2COL_SPC_DATA_TYPE_REG_OFFSET,
+                  IM2COL_SPC_DATA_TYPE_DATA_TYPE_MASK,
+                  IM2COL_SPC_DATA_TYPE_DATA_TYPE_OFFSET,
+                  im2col_spc_base_addr );
+
+  /* Write the filter dimensions */
+  write_register( trans.filter_width,
+                  IM2COL_SPC_FW_REG_OFFSET,
+                  IM2COL_SPC_FW_SIZE_MASK,
+                  IM2COL_SPC_FW_SIZE_OFFSET,
+                  im2col_spc_base_addr );
+
+  write_register( trans.filter_height,
+                  IM2COL_SPC_FH_REG_OFFSET,
+                  IM2COL_SPC_FH_SIZE_MASK,
+                  IM2COL_SPC_FH_SIZE_OFFSET,
+                  im2col_spc_base_addr );
+
+  /* Write the image dimensions */
+  write_register( trans.im_width,
+                  IM2COL_SPC_IW_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  write_register( trans.im_height,
+                  IM2COL_SPC_IH_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  /* Write the CH_COL */
+  write_register( trans.num_channels_col,
+                  IM2COL_SPC_CH_COL_REG_OFFSET,
+                  IM2COL_SPC_CH_COL_NUM_MASK,
+                  IM2COL_SPC_CH_COL_NUM_OFFSET,
+                  im2col_spc_base_addr );
+
+  /* Write n_patches */
+  write_register( trans.n_patches_w,
+                  IM2COL_SPC_N_PATCHES_W_REG_OFFSET,
+                  IM2COL_SPC_N_PATCHES_W_NUM_MASK,
+                  IM2COL_SPC_N_PATCHES_W_NUM_OFFSET,
+                  im2col_spc_base_addr );
+
+  write_register( trans.n_patches_h,
+                  IM2COL_SPC_N_PATCHES_H_REG_OFFSET,
+                  IM2COL_SPC_N_PATCHES_H_NUM_MASK,
+                  IM2COL_SPC_N_PATCHES_H_NUM_OFFSET,
+                  im2col_spc_base_addr );
+
+  /* Write the padding */
+  write_register( trans.left_pad,
+                  IM2COL_SPC_PAD_LEFT_REG_OFFSET,
+                  IM2COL_SPC_PAD_LEFT_PAD_MASK,
+                  IM2COL_SPC_PAD_LEFT_PAD_OFFSET,
+                  im2col_spc_base_addr );
+
+  write_register( trans.right_pad,
+                  IM2COL_SPC_PAD_RIGHT_REG_OFFSET,
+                  IM2COL_SPC_PAD_RIGHT_PAD_MASK,
+                  IM2COL_SPC_PAD_RIGHT_PAD_OFFSET,
+                  im2col_spc_base_addr );
+
+  write_register( trans.top_pad,
+                  IM2COL_SPC_PAD_TOP_REG_OFFSET,
+                  IM2COL_SPC_PAD_TOP_PAD_MASK,
+                  IM2COL_SPC_PAD_TOP_PAD_OFFSET,
+                  im2col_spc_base_addr );
+
+  write_register( trans.bottom_pad,
+                  IM2COL_SPC_PAD_BOTTOM_REG_OFFSET,
+                  IM2COL_SPC_PAD_BOTTOM_PAD_MASK,
+                  IM2COL_SPC_PAD_BOTTOM_PAD_OFFSET,
+                  im2col_spc_base_addr );
+
+  /* 
+    * Write the strides. With respect to test_2 these are the application-point-of-view
+    * strides, so they are the same as STRIDE_D1 and STRIDE_D2.
+    */
+  write_register( (int) log2(trans.stride_d1),
+                  IM2COL_SPC_LOG_STRIDES_D1_REG_OFFSET,
+                  IM2COL_SPC_LOG_STRIDES_D1_SIZE_MASK,
+                  IM2COL_SPC_LOG_STRIDES_D1_SIZE_OFFSET,
+                  im2col_spc_base_addr );
+
+  write_register( (int) log2(trans.stride_d2),
+                  IM2COL_SPC_LOG_STRIDES_D2_REG_OFFSET,
+                  IM2COL_SPC_LOG_STRIDES_D2_SIZE_MASK,
+                  IM2COL_SPC_LOG_STRIDES_D2_SIZE_OFFSET,
+                  im2col_spc_base_addr );
+
+  /* Write the batch size */
+  write_register( trans.batch,
+                  IM2COL_SPC_BATCH_REG_OFFSET,
+                  IM2COL_SPC_BATCH_SIZE_MASK,
+                  IM2COL_SPC_BATCH_SIZE_OFFSET,
+                  im2col_spc_base_addr );
+
+  /* Write the adapted pad regions */
+  write_register( trans.adpt_pad_right,
+                  IM2COL_SPC_ADPT_PAD_RIGHT_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  write_register( trans.adpt_pad_bottom,
+                  IM2COL_SPC_ADPT_PAD_BOTTOM_REG_OFFSET,
+                  0xffffffff,
+                  0,
+                  im2col_spc_base_addr );
+
+  /* Enable the interrupt logic */
+  write_register( 0x1,
+                  IM2COL_SPC_INTERRUPT_EN_REG_OFFSET,
+                  0x1,
+                  IM2COL_SPC_INTERRUPT_EN_EN_BIT,
+                  im2col_spc_base_addr );
+
+  /* Write the number of channels to start the process */
+  write_register( trans.num_channels,
+                  IM2COL_SPC_NUM_CH_REG_OFFSET,
+                  IM2COL_SPC_NUM_CH_NUM_MASK,
+                  IM2COL_SPC_NUM_CH_NUM_OFFSET,
+                  im2col_spc_base_addr );
+}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.h
new file mode 100644
index 00000000..eaefc0af
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col.h
@@ -0,0 +1,60 @@
+/*
+    Copyright EPFL contributors.
+    Licensed under the Apache License, Version 2.0, see LICENSE for details.
+    SPDX-License-Identifier: Apache-2.0
+
+    Author: Tommaso Terzano <tommaso.terzano@epfl.ch>
+                            <tommaso.terzano@gmail.com>
+
+    Info: This simple HAL is used to load the im2col SPC and to run it. Remember, only one DMA channel
+          at a time can be used!
+*/
+
+#ifndef _IM2COL_SPC_
+#define _IM2COL_SPC_
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include "dma.h"
+#include "im2col_spc_regs.h"
+#include "core_v_mini_mcu.h"
+#include "x-heep.h"
+#include "rv_plic.h"
+#include "csr.h"
+#include <math.h>
+#include "mmio.h"
+#include "hart.h"
+#include "fast_intr_ctrl.h"
+
+/* Transaction structure */
+typedef struct
+{
+    uint32_t* src;                /*!< Target from where the data will be copied. */
+    uint32_t* dst;                /*!< Target to where the data will be copied. */
+    uint32_t ch_mask;             /*!< Mask of the channels to be used. */
+    uint32_t im_width;            /*!< Width of the input image. */
+    uint32_t im_height;           /*!< Height of the input image. */
+    uint32_t filter_width;        /*!< Width of the filter. */
+    uint32_t filter_height;       /*!< Height of the filter. */
+    uint32_t num_channels;        /*!< Number of channels. */
+    uint32_t num_channels_col;    /*!< Number of channels to be processed. */
+    uint32_t stride_d1;           /*!< Stride in the first dimension. */
+    uint32_t stride_d2;           /*!< Stride in the second dimension. */
+    uint32_t batch;               /*!< Number of batches. */
+    uint32_t n_patches_w;         /*!< Number of patches in the width. */
+    uint32_t n_patches_h;         /*!< Number of patches in the height. */
+    uint32_t left_pad;            /*!< Padding on the left. */
+    uint32_t right_pad;           /*!< Padding on the right. */
+    uint32_t top_pad;             /*!< Padding on the top. */
+    uint32_t bottom_pad;          /*!< Padding on the bottom. */
+    uint32_t adpt_pad_right;      /*!< Adaptive padding on the right. */
+    uint32_t adpt_pad_bottom;     /*!< Adaptive padding on the bottom. */
+    uint32_t datatype;            /*!< Data type of the input. */
+} im2col_trans_t;
+
+int im2col_spc_run(im2col_trans_t trans);
+void im2col_spc_init(uint32_t im2col_spc_base_addr_i);
+__attribute__((weak, optimize("00"))) void handler_irq_im2col_spc(void);
+
+#endif
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col_spc_regs.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col_spc_regs.h
new file mode 100644
index 00000000..ac34172a
--- /dev/null
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/drivers/im2col_spc/im2col_spc_regs.h
@@ -0,0 +1,188 @@
+// Generated register defines for im2col_spc
+
+// Copyright information found in source file:
+// Copyright EPFL contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _IM2COL_SPC_REG_DEFS_
+#define _IM2COL_SPC_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Register width
+#define IM2COL_SPC_PARAM_REG_WIDTH 32
+
+// Input data pointer (word aligned)
+#define IM2COL_SPC_SRC_PTR_REG_OFFSET 0x0
+
+// Output data pointer (word aligned)
+#define IM2COL_SPC_DST_PTR_REG_OFFSET 0x4
+
+// Image width
+#define IM2COL_SPC_IW_REG_OFFSET 0x8
+#define IM2COL_SPC_IW_SIZE_MASK 0xffff
+#define IM2COL_SPC_IW_SIZE_OFFSET 0
+#define IM2COL_SPC_IW_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_IW_SIZE_MASK, .index = IM2COL_SPC_IW_SIZE_OFFSET })
+
+// Image heigth
+#define IM2COL_SPC_IH_REG_OFFSET 0xc
+#define IM2COL_SPC_IH_SIZE_MASK 0xffff
+#define IM2COL_SPC_IH_SIZE_OFFSET 0
+#define IM2COL_SPC_IH_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_IH_SIZE_MASK, .index = IM2COL_SPC_IH_SIZE_OFFSET })
+
+// Filter width
+#define IM2COL_SPC_FW_REG_OFFSET 0x10
+#define IM2COL_SPC_FW_SIZE_MASK 0xff
+#define IM2COL_SPC_FW_SIZE_OFFSET 0
+#define IM2COL_SPC_FW_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_FW_SIZE_MASK, .index = IM2COL_SPC_FW_SIZE_OFFSET })
+
+// Filter heigth
+#define IM2COL_SPC_FH_REG_OFFSET 0x14
+#define IM2COL_SPC_FH_SIZE_MASK 0xff
+#define IM2COL_SPC_FH_SIZE_OFFSET 0
+#define IM2COL_SPC_FH_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_FH_SIZE_MASK, .index = IM2COL_SPC_FH_SIZE_OFFSET })
+
+// Batch number
+#define IM2COL_SPC_BATCH_REG_OFFSET 0x18
+#define IM2COL_SPC_BATCH_SIZE_MASK 0xff
+#define IM2COL_SPC_BATCH_SIZE_OFFSET 0
+#define IM2COL_SPC_BATCH_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_BATCH_SIZE_MASK, .index = IM2COL_SPC_BATCH_SIZE_OFFSET })
+
+// Number of channels. When written, the im2col will start executing
+#define IM2COL_SPC_NUM_CH_REG_OFFSET 0x1c
+#define IM2COL_SPC_NUM_CH_NUM_MASK 0xff
+#define IM2COL_SPC_NUM_CH_NUM_OFFSET 0
+#define IM2COL_SPC_NUM_CH_NUM_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_NUM_CH_NUM_MASK, .index = IM2COL_SPC_NUM_CH_NUM_OFFSET })
+
+// Number of iterations to perform
+#define IM2COL_SPC_CH_COL_REG_OFFSET 0x20
+#define IM2COL_SPC_CH_COL_NUM_MASK 0xffff
+#define IM2COL_SPC_CH_COL_NUM_OFFSET 0
+#define IM2COL_SPC_CH_COL_NUM_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_CH_COL_NUM_MASK, .index = IM2COL_SPC_CH_COL_NUM_OFFSET })
+
+// Number of patches along W
+#define IM2COL_SPC_N_PATCHES_W_REG_OFFSET 0x24
+#define IM2COL_SPC_N_PATCHES_W_NUM_MASK 0xffff
+#define IM2COL_SPC_N_PATCHES_W_NUM_OFFSET 0
+#define IM2COL_SPC_N_PATCHES_W_NUM_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_N_PATCHES_W_NUM_MASK, .index = IM2COL_SPC_N_PATCHES_W_NUM_OFFSET })
+
+// Number of patches along H
+#define IM2COL_SPC_N_PATCHES_H_REG_OFFSET 0x28
+#define IM2COL_SPC_N_PATCHES_H_NUM_MASK 0xffff
+#define IM2COL_SPC_N_PATCHES_H_NUM_OFFSET 0
+#define IM2COL_SPC_N_PATCHES_H_NUM_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_N_PATCHES_H_NUM_MASK, .index = IM2COL_SPC_N_PATCHES_H_NUM_OFFSET })
+
+// Adapted right padded region
+#define IM2COL_SPC_ADPT_PAD_RIGHT_REG_OFFSET 0x2c
+#define IM2COL_SPC_ADPT_PAD_RIGHT_SIZE_MASK 0xff
+#define IM2COL_SPC_ADPT_PAD_RIGHT_SIZE_OFFSET 0
+#define IM2COL_SPC_ADPT_PAD_RIGHT_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_ADPT_PAD_RIGHT_SIZE_MASK, .index = IM2COL_SPC_ADPT_PAD_RIGHT_SIZE_OFFSET })
+
+// Adapted bottom padded region
+#define IM2COL_SPC_ADPT_PAD_BOTTOM_REG_OFFSET 0x30
+#define IM2COL_SPC_ADPT_PAD_BOTTOM_SIZE_MASK 0xff
+#define IM2COL_SPC_ADPT_PAD_BOTTOM_SIZE_OFFSET 0
+#define IM2COL_SPC_ADPT_PAD_BOTTOM_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_ADPT_PAD_BOTTOM_SIZE_MASK, .index = IM2COL_SPC_ADPT_PAD_BOTTOM_SIZE_OFFSET })
+
+// Logarithmic number of strides along D1, set to 1 for no stride
+#define IM2COL_SPC_LOG_STRIDES_D1_REG_OFFSET 0x34
+#define IM2COL_SPC_LOG_STRIDES_D1_SIZE_MASK 0xf
+#define IM2COL_SPC_LOG_STRIDES_D1_SIZE_OFFSET 0
+#define IM2COL_SPC_LOG_STRIDES_D1_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_LOG_STRIDES_D1_SIZE_MASK, .index = IM2COL_SPC_LOG_STRIDES_D1_SIZE_OFFSET })
+
+// Logarithmic number of strides along D2, set to 1 for no stride
+#define IM2COL_SPC_LOG_STRIDES_D2_REG_OFFSET 0x38
+#define IM2COL_SPC_LOG_STRIDES_D2_SIZE_MASK 0xf
+#define IM2COL_SPC_LOG_STRIDES_D2_SIZE_OFFSET 0
+#define IM2COL_SPC_LOG_STRIDES_D2_SIZE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_LOG_STRIDES_D2_SIZE_MASK, .index = IM2COL_SPC_LOG_STRIDES_D2_SIZE_OFFSET })
+
+// Status bit is set to one when the im2col SPC is ready
+#define IM2COL_SPC_STATUS_REG_OFFSET 0x3c
+#define IM2COL_SPC_STATUS_READY_BIT 0
+
+// The DMA will wait for the signal
+#define IM2COL_SPC_SLOT_REG_OFFSET 0x40
+#define IM2COL_SPC_SLOT_RX_TRIGGER_SLOT_MASK 0xffff
+#define IM2COL_SPC_SLOT_RX_TRIGGER_SLOT_OFFSET 0
+#define IM2COL_SPC_SLOT_RX_TRIGGER_SLOT_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_SLOT_RX_TRIGGER_SLOT_MASK, .index = IM2COL_SPC_SLOT_RX_TRIGGER_SLOT_OFFSET })
+#define IM2COL_SPC_SLOT_TX_TRIGGER_SLOT_MASK 0xffff
+#define IM2COL_SPC_SLOT_TX_TRIGGER_SLOT_OFFSET 16
+#define IM2COL_SPC_SLOT_TX_TRIGGER_SLOT_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_SLOT_TX_TRIGGER_SLOT_MASK, .index = IM2COL_SPC_SLOT_TX_TRIGGER_SLOT_OFFSET })
+
+// Width/type of the data to transfer
+#define IM2COL_SPC_DATA_TYPE_REG_OFFSET 0x44
+#define IM2COL_SPC_DATA_TYPE_DATA_TYPE_MASK 0x3
+#define IM2COL_SPC_DATA_TYPE_DATA_TYPE_OFFSET 0
+#define IM2COL_SPC_DATA_TYPE_DATA_TYPE_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_DATA_TYPE_DATA_TYPE_MASK, .index = IM2COL_SPC_DATA_TYPE_DATA_TYPE_OFFSET })
+#define IM2COL_SPC_DATA_TYPE_DATA_TYPE_VALUE_DMA_32BIT_WORD 0x0
+#define IM2COL_SPC_DATA_TYPE_DATA_TYPE_VALUE_DMA_16BIT_WORD 0x1
+#define IM2COL_SPC_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD 0x2
+#define IM2COL_SPC_DATA_TYPE_DATA_TYPE_VALUE_DMA_8BIT_WORD_2 0x3
+
+// Set the top padding
+#define IM2COL_SPC_PAD_TOP_REG_OFFSET 0x48
+#define IM2COL_SPC_PAD_TOP_PAD_MASK 0x3f
+#define IM2COL_SPC_PAD_TOP_PAD_OFFSET 0
+#define IM2COL_SPC_PAD_TOP_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_PAD_TOP_PAD_MASK, .index = IM2COL_SPC_PAD_TOP_PAD_OFFSET })
+
+// Set the bottom padding
+#define IM2COL_SPC_PAD_BOTTOM_REG_OFFSET 0x4c
+#define IM2COL_SPC_PAD_BOTTOM_PAD_MASK 0x3f
+#define IM2COL_SPC_PAD_BOTTOM_PAD_OFFSET 0
+#define IM2COL_SPC_PAD_BOTTOM_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_PAD_BOTTOM_PAD_MASK, .index = IM2COL_SPC_PAD_BOTTOM_PAD_OFFSET })
+
+// Set the right padding
+#define IM2COL_SPC_PAD_RIGHT_REG_OFFSET 0x50
+#define IM2COL_SPC_PAD_RIGHT_PAD_MASK 0x3f
+#define IM2COL_SPC_PAD_RIGHT_PAD_OFFSET 0
+#define IM2COL_SPC_PAD_RIGHT_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_PAD_RIGHT_PAD_MASK, .index = IM2COL_SPC_PAD_RIGHT_PAD_OFFSET })
+
+// Set the left padding
+#define IM2COL_SPC_PAD_LEFT_REG_OFFSET 0x54
+#define IM2COL_SPC_PAD_LEFT_PAD_MASK 0x3f
+#define IM2COL_SPC_PAD_LEFT_PAD_OFFSET 0
+#define IM2COL_SPC_PAD_LEFT_PAD_FIELD \
+  ((bitfield_field32_t) { .mask = IM2COL_SPC_PAD_LEFT_PAD_MASK, .index = IM2COL_SPC_PAD_LEFT_PAD_OFFSET })
+
+// Interrupt Enable Register
+#define IM2COL_SPC_INTERRUPT_EN_REG_OFFSET 0x58
+#define IM2COL_SPC_INTERRUPT_EN_EN_BIT 0
+
+// Interrupt Flag Register for the SPC operation
+#define IM2COL_SPC_SPC_IFR_REG_OFFSET 0x5c
+#define IM2COL_SPC_SPC_IFR_FLAG_BIT 0
+
+// Mask that defines which DMA channel the SPC can access
+#define IM2COL_SPC_SPC_CH_MASK_REG_OFFSET 0x60
+
+// Offset of the DMA channel the SPC can access
+#define IM2COL_SPC_SPC_CH_OFFSET_REG_OFFSET 0x64
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // _IM2COL_SPC_REG_DEFS_
+// End generated register defines for im2col_spc
\ No newline at end of file
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
index 710cf02e..aa4d3b79 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/core_v_mini_mcu.h.tpl
@@ -41,6 +41,7 @@ extern "C" {
 
 #define DMA_CH_NUM ${dma_ch_count}
 #define DMA_CH_SIZE 0x${dma_ch_size}
+#define DMA_NUM_MASTER_PORTS ${num_dma_master_ports}
 
 //switch-on/off peripherals
 #define PERIPHERAL_START_ADDRESS 0x${peripheral_start_address}
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h
index 9759edfb..64e4d090 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/runtime/hart.h
@@ -27,7 +27,7 @@ extern "C" {
  *
  * This function may behave as if it is a no-op.
  */
-inline void wait_for_interrupt(void) { asm volatile("wfi"); }
+static inline void wait_for_interrupt(void) { asm volatile("wfi"); }
 
 
 #ifdef __cplusplus
diff --git a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c
index 67371531..8457086d 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c
+++ b/hw/vendor/esl_epfl_x_heep/sw/device/lib/sdk/dma/dma_sdk.c
@@ -38,7 +38,7 @@ extern "C"
 
     static __attribute__((always_inline)) void dma_start(dma *peri, uint32_t size, dma_data_type_t src_type)
     {
-        peri->SIZE_D1 = (uint32_t)((size * DMA_DATA_TYPE_2_SIZE(src_type)) & DMA_SIZE_D1_SIZE_MASK);
+        peri->SIZE_D1 = (uint32_t)((size) & DMA_SIZE_D1_SIZE_MASK);
     }
 
     // Initialize the DMA
diff --git a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
index 74755de3..2e43dd14 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
@@ -34,14 +34,14 @@ module ext_bus #(
     input  obi_pkg::obi_req_t  heep_debug_master_req_i,
     output obi_pkg::obi_resp_t heep_debug_master_resp_o,
 
-    input  obi_pkg::obi_req_t  heep_dma_read_ch0_req_i,
-    output obi_pkg::obi_resp_t heep_dma_read_ch0_resp_o,
+    input  obi_pkg::obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_read_req_i ,
+    output obi_pkg::obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_read_resp_o,
 
-    input  obi_pkg::obi_req_t  heep_dma_write_ch0_req_i,
-    output obi_pkg::obi_resp_t heep_dma_write_ch0_resp_o,
+    input  obi_pkg::obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_write_req_i,
+    output obi_pkg::obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_write_resp_o,
 
-    input  obi_pkg::obi_req_t  heep_dma_addr_ch0_req_i,
-    output obi_pkg::obi_resp_t heep_dma_addr_ch0_resp_o,
+    input  obi_pkg::obi_req_t  [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_addr_req_i ,
+    output obi_pkg::obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_addr_resp_o,
 
     // External master ports
     input  obi_pkg::obi_req_t  [EXT_XBAR_NMASTER_RND-1:0] ext_master_req_i,
@@ -67,7 +67,7 @@ module ext_bus #(
   obi_req_t [EXT_XBAR_NMASTER-1:0][1:0] demux_xbar_req;
   obi_resp_t [EXT_XBAR_NMASTER-1:0][1:0] demux_xbar_resp;
 
-  // Dummy external master portp (to prevent unused warning)
+  // Dummy external master port (to prevent unused warning)
   obi_req_t [EXT_XBAR_NMASTER_RND-1:0] ext_master_req_unused;
   obi_resp_t [EXT_XBAR_NMASTER_RND-1:0] heep_slave_resp_unused;
   obi_resp_t [EXT_XBAR_NSLAVE_RND-1:0] ext_slave_resp_unused;
@@ -80,9 +80,17 @@ module ext_bus #(
   assign master_req[CORE_INSTR_IDX] = heep_core_instr_req_i;
   assign master_req[CORE_DATA_IDX] = heep_core_data_req_i;
   assign master_req[DEBUG_MASTER_IDX] = heep_debug_master_req_i;
-  assign master_req[DMA_READ_CH0_IDX] = heep_dma_read_ch0_req_i;
-  assign master_req[DMA_WRITE_CH0_IDX] = heep_dma_write_ch0_req_i;
-  assign master_req[DMA_ADDR_CH0_IDX] = heep_dma_addr_ch0_req_i;
+
+  generate
+    for (
+        genvar i = 0; i < core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS; i++
+    ) begin : gen_dma_master_req_map
+      assign master_req[core_v_mini_mcu_pkg::DMA_READ_P0_IDX+i*3]  = heep_dma_read_req_i[i];
+      assign master_req[core_v_mini_mcu_pkg::DMA_WRITE_P0_IDX+i*3] = heep_dma_write_req_i[i];
+      assign master_req[core_v_mini_mcu_pkg::DMA_ADDR_P0_IDX+i*3]  = heep_dma_addr_req_i[i];
+    end
+  endgenerate
+
   generate
     for (genvar i = 0; i < EXT_XBAR_NMASTER; i++) begin : gen_ext_master_req_map
       assign master_req[SYSTEM_XBAR_NMASTER+i] = demux_xbar_req[i][DEMUX_XBAR_EXT_SLAVE_IDX];
@@ -93,9 +101,16 @@ module ext_bus #(
   assign heep_core_instr_resp_o = master_resp[CORE_INSTR_IDX];
   assign heep_core_data_resp_o = master_resp[CORE_DATA_IDX];
   assign heep_debug_master_resp_o = master_resp[DEBUG_MASTER_IDX];
-  assign heep_dma_read_ch0_resp_o = master_resp[DMA_READ_CH0_IDX];
-  assign heep_dma_write_ch0_resp_o = master_resp[DMA_WRITE_CH0_IDX];
-  assign heep_dma_addr_ch0_resp_o = master_resp[DMA_ADDR_CH0_IDX];
+
+  generate
+    for (
+        genvar i = 0; i < core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS; i++
+    ) begin : gen_dma_master_resp_map
+      assign heep_dma_read_resp_o[i]  = master_resp[core_v_mini_mcu_pkg::DMA_READ_P0_IDX+i];
+      assign heep_dma_write_resp_o[i] = master_resp[core_v_mini_mcu_pkg::DMA_WRITE_P0_IDX+i];
+      assign heep_dma_addr_resp_o[i]  = master_resp[core_v_mini_mcu_pkg::DMA_ADDR_P0_IDX+i];
+    end
+  endgenerate
 
   // X-HEEP slave requests
   generate
diff --git a/hw/vendor/esl_epfl_x_heep/tb/tb.vlt b/hw/vendor/esl_epfl_x_heep/tb/tb.vlt
index 31e1d7cd..6ccdab5b 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/tb.vlt
+++ b/hw/vendor/esl_epfl_x_heep/tb/tb.vlt
@@ -8,6 +8,8 @@ lint_off -rule UNUSED -file "*tb/testharness.sv" -match "*"
 lint_off -rule UNUSED -file "*tb/ext_xbar.sv" -match "Signal is not driven, nor used: '*"
 lint_off -rule UNOPTFLAT -file "*tb/ext_xbar.sv" -match "Signal unoptimizable: Feedback to clock or circular logic: 'testharness.ext_bus_i.__Vcellout__ext_xbar_i__slave_req_o'"
 lint_off -rule UNDRIVEN -file "*tb/testharness.sv" -match "Signal is not driven: 'jtag_tdo_o'*"
+lint_off -rule UNDRIVEN -file "*tb/testharness.sv" -match "Signal is not driven: 'ext_ao_peripheral_req'*"
+lint_off -rule UNDRIVEN -file "*tb/testharness.sv" -match "Signal is not driven: 'ext_ao_peripheral_resp'*"
 lint_off -rule SYNCASYNCNET -file "*tb/testharness.sv" -match "*"
 lint_off -rule WIDTH -file "*tb/testharness.sv" -match "*"
 lint_off -rule LITENDIAN -file "*tb/testharness.sv" -match "*"
diff --git a/hw/vendor/esl_epfl_x_heep/tb/testharness.sv b/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
index 9008beb4..e9a2cd3c 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/testharness.sv
@@ -48,7 +48,9 @@ module testharness #(
   import reg_pkg::*;
   import testharness_pkg::*;
   import addr_map_rule_pkg::*;
+  import core_v_mini_mcu_pkg::*;
 
+  localparam AO_SPC_NUM = 1;
   localparam SWITCH_ACK_LATENCY = 15;
   localparam EXT_XBAR_NMASTER_RND = USE_EXTERNAL_DEVICE_EXAMPLE ? testharness_pkg::EXT_XBAR_NMASTER : 1;
   localparam HEEP_EXT_XBAR_NMASTER = USE_EXTERNAL_DEVICE_EXAMPLE ? testharness_pkg::EXT_XBAR_NMASTER : 0;
@@ -88,6 +90,9 @@ module testharness #(
   logic iffifo_in_ready, iffifo_out_valid;
   logic iffifo_int_o;
 
+  // Im2col SPC interrupt signal
+  logic im2col_spc_done_int_o;
+
   // External DMA slots
   logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_tx;
   logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] ext_dma_slot_rx;
@@ -110,12 +115,12 @@ module testharness #(
   obi_resp_t heep_core_data_resp;
   obi_req_t heep_debug_master_req;
   obi_resp_t heep_debug_master_resp;
-  obi_req_t heep_dma_read_ch0_req;
-  obi_resp_t heep_dma_read_ch0_resp;
-  obi_req_t heep_dma_write_ch0_req;
-  obi_resp_t heep_dma_write_ch0_resp;
-  obi_req_t heep_dma_addr_ch0_req;
-  obi_resp_t heep_dma_addr_ch0_resp;
+  obi_req_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_read_req;
+  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_read_resp;
+  obi_req_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_write_req;
+  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_write_resp;
+  obi_req_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_addr_req;
+  obi_resp_t [core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0] heep_dma_addr_resp;
   obi_req_t [EXT_XBAR_NSLAVE-1:0] ext_slave_req;
   obi_resp_t [EXT_XBAR_NSLAVE-1:0] ext_slave_resp;
   reg_req_t periph_slave_req;
@@ -146,6 +151,12 @@ module testharness #(
       .X_MISA(fpu_ss_pkg::X_MISA)
   ) ext_if ();
 
+  // External SPC interface signals
+  reg_req_t [AO_SPC_NUM-1:0] ext_ao_peripheral_req;
+  reg_rsp_t [AO_SPC_NUM-1:0] ext_ao_peripheral_resp;
+
+  logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_busy;
+
   always_comb begin
     // All interrupt lines set to zero by default
     for (int i = 0; i < core_v_mini_mcu_pkg::NEXT_INT; i++) begin
@@ -154,6 +165,7 @@ module testharness #(
     // Re-assign the interrupt lines used here
     intr_vector_ext[0] = memcopy_intr;
     intr_vector_ext[1] = iffifo_int_o;
+    intr_vector_ext[2] = im2col_spc_done_int_o;
   end
 
   //log parameters
@@ -178,6 +190,7 @@ module testharness #(
   end
 `endif
 
+  // X-HEEP system
   x_heep_system #(
       .COREV_PULP(COREV_PULP),
       .FPU(FPU),
@@ -259,12 +272,14 @@ module testharness #(
       .ext_core_data_resp_i(heep_core_data_resp),
       .ext_debug_master_req_o(heep_debug_master_req),
       .ext_debug_master_resp_i(heep_debug_master_resp),
-      .ext_dma_read_ch0_req_o(heep_dma_read_ch0_req),
-      .ext_dma_read_ch0_resp_i(heep_dma_read_ch0_resp),
-      .ext_dma_write_ch0_req_o(heep_dma_write_ch0_req),
-      .ext_dma_write_ch0_resp_i(heep_dma_write_ch0_resp),
-      .ext_dma_addr_ch0_req_o(heep_dma_addr_ch0_req),
-      .ext_dma_addr_ch0_resp_i(heep_dma_addr_ch0_resp),
+      .ext_dma_read_req_o(heep_dma_read_req),
+      .ext_dma_read_resp_i(heep_dma_read_resp),
+      .ext_dma_write_req_o(heep_dma_write_req),
+      .ext_dma_write_resp_i(heep_dma_write_resp),
+      .ext_dma_addr_req_o(heep_dma_addr_req),
+      .ext_dma_addr_resp_i(heep_dma_addr_resp),
+      .ext_ao_peripheral_req_i(ext_ao_peripheral_req),
+      .ext_ao_peripheral_resp_o(ext_ao_peripheral_resp),
       .ext_peripheral_slave_req_o(periph_slave_req),
       .ext_peripheral_slave_resp_i(periph_slave_rsp),
       .external_subsystem_powergate_switch_no(external_subsystem_powergate_switch_n),
@@ -275,7 +290,8 @@ module testharness #(
       .external_subsystem_clkgate_en_no(external_subsystem_clkgate_en_n),
       .ext_dma_slot_tx_i(ext_dma_slot_tx),
       .ext_dma_slot_rx_i(ext_dma_slot_rx),
-      .ext_dma_stop_i('0)
+      .ext_dma_stop_i('0),
+      .dma_done_o(dma_busy)
   );
 
   // Testbench external bus
@@ -286,28 +302,28 @@ module testharness #(
       .EXT_XBAR_NMASTER(EXT_XBAR_NMASTER),
       .EXT_XBAR_NSLAVE (EXT_XBAR_NSLAVE)
   ) ext_bus_i (
-      .clk_i                    (clk_i),
-      .rst_ni                   (rst_ni),
-      .addr_map_i               (EXT_XBAR_ADDR_RULES),
-      .default_idx_i            (SLOW_MEMORY_IDX[LOG_EXT_XBAR_NSLAVE-1:0]),
-      .heep_core_instr_req_i    (heep_core_instr_req),
-      .heep_core_instr_resp_o   (heep_core_instr_resp),
-      .heep_core_data_req_i     (heep_core_data_req),
-      .heep_core_data_resp_o    (heep_core_data_resp),
-      .heep_debug_master_req_i  (heep_debug_master_req),
-      .heep_debug_master_resp_o (heep_debug_master_resp),
-      .heep_dma_read_ch0_req_i  (heep_dma_read_ch0_req),
-      .heep_dma_read_ch0_resp_o (heep_dma_read_ch0_resp),
-      .heep_dma_write_ch0_req_i (heep_dma_write_ch0_req),
-      .heep_dma_write_ch0_resp_o(heep_dma_write_ch0_resp),
-      .heep_dma_addr_ch0_req_i  (heep_dma_addr_ch0_req),
-      .heep_dma_addr_ch0_resp_o (heep_dma_addr_ch0_resp),
-      .ext_master_req_i         (ext_master_req),
-      .ext_master_resp_o        (ext_master_resp),
-      .heep_slave_req_o         (heep_slave_req),
-      .heep_slave_resp_i        (heep_slave_resp),
-      .ext_slave_req_o          (ext_slave_req),
-      .ext_slave_resp_i         (ext_slave_resp)
+      .clk_i                   (clk_i),
+      .rst_ni                  (rst_ni),
+      .addr_map_i              (EXT_XBAR_ADDR_RULES),
+      .default_idx_i           (SLOW_MEMORY_IDX[LOG_EXT_XBAR_NSLAVE-1:0]),
+      .heep_core_instr_req_i   (heep_core_instr_req),
+      .heep_core_instr_resp_o  (heep_core_instr_resp),
+      .heep_core_data_req_i    (heep_core_data_req),
+      .heep_core_data_resp_o   (heep_core_data_resp),
+      .heep_debug_master_req_i (heep_debug_master_req),
+      .heep_debug_master_resp_o(heep_debug_master_resp),
+      .heep_dma_read_req_i     (heep_dma_read_req),
+      .heep_dma_read_resp_o    (heep_dma_read_resp),
+      .heep_dma_write_req_i    (heep_dma_write_req),
+      .heep_dma_write_resp_o   (heep_dma_write_resp),
+      .heep_dma_addr_req_i     (heep_dma_addr_req),
+      .heep_dma_addr_resp_o    (heep_dma_addr_resp),
+      .ext_master_req_i        (ext_master_req),
+      .ext_master_resp_o       (ext_master_resp),
+      .heep_slave_req_o        (heep_slave_req),
+      .heep_slave_resp_i       (heep_slave_resp),
+      .ext_slave_req_o         (ext_slave_req),
+      .ext_slave_resp_i        (ext_slave_resp)
   );
 
   logic pdm;
@@ -469,18 +485,20 @@ module testharness #(
       ) dma_i (
           .clk_i,
           .rst_ni,
+          .clk_gate_en_ni('1),
           .ext_dma_stop_i('0),
           .reg_req_i(ext_periph_slv_req[testharness_pkg::MEMCOPY_CTRL_IDX]),
           .reg_rsp_o(ext_periph_slv_rsp[testharness_pkg::MEMCOPY_CTRL_IDX]),
-          .dma_read_ch0_req_o(ext_master_req[testharness_pkg::EXT_MASTER0_IDX]),
-          .dma_read_ch0_resp_i(ext_master_resp[testharness_pkg::EXT_MASTER0_IDX]),
-          .dma_write_ch0_req_o(ext_master_req[testharness_pkg::EXT_MASTER1_IDX]),
-          .dma_write_ch0_resp_i(ext_master_resp[testharness_pkg::EXT_MASTER1_IDX]),
-          .dma_addr_ch0_req_o(),
-          .dma_addr_ch0_resp_i('0),
+          .dma_read_req_o(ext_master_req[testharness_pkg::EXT_MASTER0_IDX]),
+          .dma_read_resp_i(ext_master_resp[testharness_pkg::EXT_MASTER0_IDX]),
+          .dma_write_req_o(ext_master_req[testharness_pkg::EXT_MASTER1_IDX]),
+          .dma_write_resp_i(ext_master_resp[testharness_pkg::EXT_MASTER1_IDX]),
+          .dma_addr_req_o(),
+          .dma_addr_resp_i('0),
           .trigger_slot_i('0),
           .dma_done_intr_o(memcopy_intr),
-          .dma_window_intr_o()
+          .dma_window_intr_o(),
+          .dma_done_o()
       );
 
       simple_accelerator #(
@@ -499,6 +517,20 @@ module testharness #(
           .acc_write_ch0_resp_i(ext_master_resp[testharness_pkg::EXT_MASTER3_IDX])
       );
 
+      im2col_spc im2col_spc_i (
+          .clk_i,
+          .rst_ni,
+
+          .aopb2im2col_resp_i(ext_ao_peripheral_resp[0]),
+          .im2col2aopb_req_o (ext_ao_peripheral_req[0]),
+
+          .reg_req_i(ext_periph_slv_req[testharness_pkg::IM2COL_SPC_IDX]),
+          .reg_rsp_o(ext_periph_slv_rsp[testharness_pkg::IM2COL_SPC_IDX]),
+
+          .dma_done_i(dma_busy),
+          .im2col_spc_done_int_o(im2col_spc_done_int_o)
+      );
+
       // AMS external peripheral
       ams #(
           .reg_req_t(reg_pkg::reg_req_t),
@@ -644,6 +676,7 @@ module testharness #(
       assign memcopy_intr = '0;
       assign iffifo_int_o = '0;
       assign periph_slave_rsp = '0;
+      assign im2col_spc_done_int_o = '0;
 
     end
   endgenerate
diff --git a/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv b/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv
index d74011f4..e26afd7a 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/testharness_pkg.sv
@@ -31,7 +31,7 @@ package testharness_pkg;
   };
 
   //slave encoder
-  localparam EXT_NPERIPHERALS = 4;
+  localparam EXT_NPERIPHERALS = 5;
 
   // Memcopy controller (external peripheral example)
   localparam logic [31:0] MEMCOPY_CTRL_START_ADDRESS = core_v_mini_mcu_pkg::EXT_PERIPHERAL_START_ADDRESS + 32'h0;
@@ -57,6 +57,12 @@ package testharness_pkg;
   localparam logic [31:0] SIMPLE_ACC_END_ADDRESS = SIMPLE_ACC_START_ADDRESS + SIMPLE_ACC_SIZE;
   localparam logic [31:0] SIMPLE_ACC_IDX = 32'd3;
 
+  // External im2col SPC Peripheral
+  localparam logic [31:0] IM2COL_SPC_START_ADDRESS = core_v_mini_mcu_pkg::EXT_PERIPHERAL_START_ADDRESS + 32'h04000;
+  localparam logic [31:0] IM2COL_SPC_SIZE = 32'h100;
+  localparam logic [31:0] IM2COL_SPC_END_ADDRESS = IM2COL_SPC_START_ADDRESS + IM2COL_SPC_SIZE;
+  localparam logic [31:0] IM2COL_SPC_IDX = 32'd4;
+
   localparam addr_map_rule_t [EXT_NPERIPHERALS-1:0] EXT_PERIPHERALS_ADDR_RULES = '{
       '{
           idx: MEMCOPY_CTRL_IDX,
@@ -69,6 +75,11 @@ package testharness_pkg;
           idx: SIMPLE_ACC_IDX,
           start_addr: SIMPLE_ACC_START_ADDRESS,
           end_addr: SIMPLE_ACC_END_ADDRESS
+      },
+      '{
+          idx: IM2COL_SPC_IDX,
+          start_addr: IM2COL_SPC_START_ADDRESS,
+          end_addr: IM2COL_SPC_END_ADDRESS
       }
   };
 
diff --git a/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py b/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
index 31826540..c187bf54 100755
--- a/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
+++ b/hw/vendor/esl_epfl_x_heep/util/mcu_gen.py
@@ -20,6 +20,7 @@
 from math import log2
 import x_heep_gen.load_config
 from x_heep_gen.system import BusType
+import math
 
 class Pad:
 
@@ -209,7 +210,7 @@ def create_pad_ring_bonding(self):
         self.pad_ring_bonding_bonding += '    .' + self.signal_name + 'oe_i(' + oe_internal_signals + '),'
         self.x_heep_system_interface += '    inout wire ' + self.signal_name + 'io,'
 
-  def __init__(self, name, cell_name, pad_type, pad_mapping, index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, has_attribute, attribute_bits):
+  def __init__(self, name, cell_name, pad_type, pad_mapping, index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, has_attribute, attribute_bits, pad_layout_index, pad_layout_orient, pad_layout_cell, pad_layout_offset, pad_layout_skip):
 
     self.name = name
     self.cell_name = cell_name
@@ -240,6 +241,12 @@ def __init__(self, name, cell_name, pad_type, pad_mapping, index, pad_active, pa
     self.is_driven_manually = pad_driven_manually
     self.do_skip_declaration = pad_skip_declaration
 
+    self.layout_index = pad_layout_index
+    self.layout_orient = pad_layout_orient
+    self.layout_cell = pad_layout_cell
+    self.layout_offset = pad_layout_offset
+    self.layout_skip = pad_layout_skip
+
     if(len(pad_mux_list) == 0):
         self.signal_name_drive.append(self.signal_name)
         self.pad_type_drive.append(pad_type)
@@ -505,11 +512,51 @@ def len_extracted_peripherals(peripherals):
     ao_peripherals = extract_peripherals(discard_path(obj['ao_peripherals']))
     ao_peripherals_count = len(ao_peripherals)
     dma_ch_count = ao_peripherals["dma"]["num_channels"]
+
     if int(dma_ch_count, 16) > int('256', 16) or int(dma_ch_count, 16) == 0:
         exit("Number of DMA channels has to be between 0 and 256, excluded")
 
     dma_ch_size = ao_peripherals["dma"]["ch_length"]
 
+    # Number of master ports for the dma subsystem
+    num_dma_master_ports = ao_peripherals["dma"]["num_master_ports"]
+    if int(num_dma_master_ports, 16) > int(dma_ch_count, 16) or int(num_dma_master_ports, 16) == 0:
+        exit("Number of DMA master ports has to be between 0 and " + str(dma_ch_count) + ", 0 excluded")
+
+    # Number of masters for each slave of the DMA NtoM xbar
+    num_dma_xbar_channels_per_master_port = ao_peripherals["dma"]["num_channels_per_master_port"]
+    if (int(num_dma_xbar_channels_per_master_port, 16) > int(dma_ch_count, 16) and int(dma_ch_count, 16) != 1) or int(num_dma_xbar_channels_per_master_port, 16) == 0:
+        exit("Number of DMA channels per system bus master ports has to be between 0 and " + str(dma_ch_count) + ", excluded")
+
+    if (int(num_dma_master_ports) > 1):
+        # Computation of full_masters_xbars
+        temp_full_masters_xbars = math.floor(int(dma_ch_count) / int(num_dma_xbar_channels_per_master_port))
+        if temp_full_masters_xbars < int(num_dma_master_ports) and temp_full_masters_xbars * int(num_dma_xbar_channels_per_master_port) == int(dma_ch_count):
+            full_masters_xbars = temp_full_masters_xbars - 1
+        else:
+            full_masters_xbars = temp_full_masters_xbars
+        last = int(num_dma_xbar_channels_per_master_port) * full_masters_xbars
+
+        # Array initialization
+        array_xbar_gen = [0] * int(num_dma_master_ports)
+
+        # Computation of the number of xbar channels for each master port
+        for i in range(int(num_dma_master_ports)):
+            if i < full_masters_xbars:
+                array_xbar_gen[i] = int(num_dma_xbar_channels_per_master_port)
+            else:
+                array_xbar_gen[i] = min(int(dma_ch_count) - last, int(dma_ch_count) - last - (int(num_dma_master_ports) - i - 1))
+                last = last + array_xbar_gen[i]
+
+        if (sum(array_xbar_gen) != int(dma_ch_count) or 0 in array_xbar_gen):
+            exit("Error in the DMA xbar generation: wrong parameters")
+        
+        dma_xbar_array = ", ".join(map(str, array_xbar_gen))
+    else:
+        if (int(num_dma_xbar_channels_per_master_port) != int(dma_ch_count)):
+            exit("With 1 master port, the number of DMA channels per master port has to be equal to the number of DMA channels")
+        dma_xbar_array = "default: 1"
+
     peripheral_start_address = string2int(obj['peripherals']['address'])
     if int(peripheral_start_address, 16) < int('10000', 16):
         exit("peripheral start address must be greater than 0x10000")
@@ -625,6 +672,31 @@ def len_extracted_peripherals(peripherals):
         except KeyError:
             pad_keep_internal = False
 
+        try:
+            pad_layout_orient = pads[key]['layout_attributes']['orient']
+        except KeyError:
+            pad_layout_orient = None
+        
+        try:
+            pad_layout_cell = pads[key]['layout_attributes']['cell']
+        except KeyError:
+            pad_layout_cell = None
+        
+        try:
+            pad_layout_offset = pads[key]['layout_attributes']['offset']
+        except KeyError:
+            pad_layout_offset = None
+
+        try:
+            pad_layout_skip = pads[key]['layout_attributes']['skip']
+        except KeyError:
+            pad_layout_skip = None
+
+        try:
+            pad_layout_index = pads[key]['layout_attributes']['index']
+        except KeyError:
+            pad_layout_index = None
+
         pad_mux_list = []
 
         for pad_mux in pad_mux_list_hjson:
@@ -650,13 +722,13 @@ def len_extracted_peripherals(peripherals):
             except KeyError:
                 pad_skip_declaration_mux = False
 
-            p = Pad(pad_mux, '', pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits)
+            p = Pad(pad_mux, '', pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits, pad_layout_index, pad_layout_orient, pad_layout_cell, pad_layout_offset, pad_layout_skip)
             pad_mux_list.append(p)
 
         if pad_num > 1:
             for p in range(pad_num):
                 pad_cell_name = "pad_" + key + "_" + str(p+pad_offset) + "_i"
-                pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+                pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits, pad_layout_index, pad_layout_orient, pad_layout_cell, pad_layout_offset, pad_layout_skip)
                 if not pad_keep_internal:
                     pad_obj.create_pad_ring()
                 pad_obj.create_core_v_mini_mcu_ctrl()
@@ -675,7 +747,7 @@ def len_extracted_peripherals(peripherals):
 
         else:
             pad_cell_name = "pad_" + key + "_i"
-            pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+            pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, pad_index_counter, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits, pad_layout_index, pad_layout_orient, pad_layout_cell, pad_layout_offset, pad_layout_skip)
             if not pad_keep_internal:
                 pad_obj.create_pad_ring()
             pad_obj.create_core_v_mini_mcu_ctrl()
@@ -736,6 +808,31 @@ def len_extracted_peripherals(peripherals):
             except KeyError:
                 pad_skip_declaration = False
 
+            try:
+                pad_layout_orient = external_pads[key]['layout_attributes']['orient']
+            except KeyError:
+                pad_layout_orient = None
+            
+            try:
+                pad_layout_cell = external_pads[key]['layout_attributes']['cell']
+            except KeyError:
+                pad_layout_cell = None
+            
+            try:
+                pad_layout_offset = external_pads[key]['layout_attributes']['offset']
+            except KeyError:
+                pad_layout_offset = None
+
+            try:
+                pad_layout_skip = external_pads[key]['layout_attributes']['skip']
+            except KeyError:
+                pad_layout_skip = None
+            
+            try:
+                pad_layout_index = external_pads[key]['layout_attributes']['index']
+            except KeyError:
+                pad_layout_index = None
+            
             pad_mux_list = []
 
             for pad_mux in pad_mux_list_hjson:
@@ -761,13 +858,13 @@ def len_extracted_peripherals(peripherals):
                 except KeyError:
                     pad_skip_declaration_mux = False
 
-                p = Pad(pad_mux, '', external_pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits)
+                p = Pad(pad_mux, '', external_pads[key]['mux'][pad_mux]['type'], pad_mapping, 0, pad_active_mux, pad_driven_manually_mux, pad_skip_declaration_mux, [], pads_attributes!=None, pads_attributes_bits, pad_layout_index, pad_layout_orient, pad_layout_cell, pad_layout_offset, pad_layout_skip)
                 pad_mux_list.append(p)
 
             if pad_num > 1:
                 for p in range(pad_num):
                     pad_cell_name = "pad_" + key + "_" + str(p+pad_offset) + "_i"
-                    pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+                    pad_obj = Pad(pad_name + "_" + str(p+pad_offset), pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits, pad_layout_index, pad_layout_orient, pad_layout_cell, pad_layout_offset, pad_layout_skip)
                     pad_obj.create_pad_ring()
                     pad_obj.create_pad_ring_bonding()
                     pad_obj.create_internal_signals()
@@ -783,7 +880,7 @@ def len_extracted_peripherals(peripherals):
 
             else:
                 pad_cell_name = "pad_" + key + "_i"
-                pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits)
+                pad_obj = Pad(pad_name, pad_cell_name, pad_type, pad_mapping, external_pad_index, pad_active, pad_driven_manually, pad_skip_declaration, pad_mux_list, pads_attributes!=None, pads_attributes_bits, pad_layout_index, pad_layout_orient, pad_layout_cell, pad_layout_offset, pad_layout_skip)
                 pad_obj.create_pad_ring()
                 pad_obj.create_pad_ring_bonding()
                 pad_obj.create_internal_signals()
@@ -828,6 +925,9 @@ def len_extracted_peripherals(peripherals):
         "ao_peripherals_count"             : ao_peripherals_count,
         "dma_ch_count"                     : dma_ch_count,
         "dma_ch_size"                      : dma_ch_size,
+        "num_dma_master_ports"             : num_dma_master_ports,
+        "num_dma_xbar_channels_per_master_port" : num_dma_xbar_channels_per_master_port,
+        "dma_xbar_masters_array"           : dma_xbar_array,
         "peripheral_start_address"         : peripheral_start_address,
         "peripheral_size_address"          : peripheral_size_address,
         "peripherals"                      : peripherals,
diff --git a/hw/vendor/esl_epfl_x_heep/util/test_all.sh b/hw/vendor/esl_epfl_x_heep/util/test_all.sh
index dd0d0374..99ad0084 100755
--- a/hw/vendor/esl_epfl_x_heep/util/test_all.sh
+++ b/hw/vendor/esl_epfl_x_heep/util/test_all.sh
@@ -174,7 +174,7 @@ SIMULATOR=''
 declare -a LINKERS=( )
 
 # Simulation timeout to prevent apps from running infinitely
-SIM_TIMEOUT_S=120 # This time, in seconds, was chosen empirically.
+SIM_TIMEOUT_S=240 # This time, in seconds, was chosen empirically.
 
 # Prevent the re-generation of the mcu and the simualtion model on every
 # execution by changing DEBUG to 1
diff --git a/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core b/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core
index 98252573..0caaea00 100644
--- a/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core
+++ b/hw/vendor/esl_epfl_x_heep/x-heep-tb-utils.core
@@ -17,6 +17,7 @@ filesets:
     - example:ip:iffifo
     - example:ip:i2s_microphone
     - example:ip:simple_accelerator
+    - example:ip:im2col_spc
     files:
     file_type: systemVerilogSource
 
@@ -26,6 +27,7 @@ filesets:
     - hw/ip_examples/ams/ams.vlt
     - hw/ip_examples/iffifo/iffifo.vlt
     - hw/ip_examples/simple_accelerator/simple_accelerator.vlt
+    - hw/ip_examples/im2col_spc/im2col_spc.vlt
     - tb/tb.vlt
     file_type: vlt
 
diff --git a/hw/vendor/eslepfl_x_heep.lock.hjson b/hw/vendor/eslepfl_x_heep.lock.hjson
index ee180557..c62e55c8 100644
--- a/hw/vendor/eslepfl_x_heep.lock.hjson
+++ b/hw/vendor/eslepfl_x_heep.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/Luigi2898/x-heep.git
-    rev: 798fd6ffc9193b613f5a85f54a496bfcc149a07d
+    rev: 83f1563fd4894787167b27099006c8b1b042d3d1
   }
 }

From 7fd73a7cafbea3d1324b61160ba63351d396cdd7 Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Tue, 8 Oct 2024 12:17:43 +0200
Subject: [PATCH 23/27] Updating HEEPsilon to the final version, plus fixing
 CGRA memory generation conflicts (generate_sram_...tcl(s))

---
 Makefile                                      |   4 +-
 heepsilon.core                                | 115 ++++++++------
 hw/fpga_cgra/cgra_sram_wrapper.sv             |  96 +++++++++--
 hw/fpga_cgra/scripts/generate_sram_emem.tcl   |  26 +++
 .../scripts/generate_sram_general.tcl         | 150 ++++++++++++++++++
 hw/rtl/heepsilon_top.sv                       |  24 +--
 .../esl_epfl_x_heep/configs/general.hjson     |   2 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv     |  36 +++++
 hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv       |   5 +-
 9 files changed, 379 insertions(+), 79 deletions(-)
 create mode 100644 hw/fpga_cgra/scripts/generate_sram_emem.tcl
 create mode 100644 hw/fpga_cgra/scripts/generate_sram_general.tcl

diff --git a/Makefile b/Makefile
index 5be58865..ad59c028 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ PORT		?= /dev/ttyUSB2
 EXTERNAL_DOMAINS = 1
 PROJECT ?= hello_world
 
-MEMORY_BANKS ?= 2 # Multiple of 2
-MEMORY_BANKS_IL ?= 4 # Power of 2
+#MEMORY_BANKS ?= 2 # Multiple of 2
+#MEMORY_BANKS_IL ?= 4 # Power of 2
   
 export HEEP_DIR = hw/vendor/esl_epfl_x_heep/
 include $(HEEP_DIR)Makefile.venv
diff --git a/heepsilon.core b/heepsilon.core
index b19142a3..b54290ac 100644
--- a/heepsilon.core
+++ b/heepsilon.core
@@ -100,31 +100,23 @@ filesets:
     depend:
     - openhwgroup.org:systems:core-v-mini-mcu-fpga
     files:
-    - hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv
-    - hw/fpga/sram_wrapper.sv
-    - hw/fpga_cgra/cgra_sram_wrapper.sv
-    - hw/fpga_cgra/cgra_clock_gate.sv
-    - hw/fpga_cgra/xilinx_heepsilon_wrapper.sv
-    file_type: systemVerilogSource
-
-  ip-fpga:
-    files:
-    - hw/fpga/scripts/generate_sram.tcl:  { file_type: tclSource }
-    - hw/fpga/prim_xilinx_clk.sv:  { file_type: systemVerilogSource } # Here there are the following modules
-    - hw/fpga/cve2_xilinx_clock_gate.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_output_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_inout_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_input_xilinx.sv:  { file_type: systemVerilogSource }
-    - hw/fpga/pad_cell_bypass_output_xilinx.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/scripts/generate_sram_general.tcl: { file_type: tclSource }
+    - hw/fpga_cgra/scripts/generate_sram_emem.tcl: { file_type: tclSource }
+    - hw/vendor/esl_epfl_x_heep/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/cgra_sram_wrapper.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/cgra_clock_gate.sv:  { file_type: systemVerilogSource }
+    - hw/fpga_cgra/xilinx_heepsilon_wrapper.sv:  { file_type: systemVerilogSource }
 
-  ip-fpga-pynq-z2:
+  xdc-fpga-pynq-z2:
     files:
-    - hw/fpga/scripts/pynq-z2/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+    - hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
+    - hw/fpga/constraints/pynq-z2/constraints.xdc
+    file_type: xdc
 
-  ip-fpga-zcu104:
+  xdc-fpga-zcu104:
     files:
-    - hw/fpga/scripts/zcu104/xilinx_generate_clk_wizard.tcl:  { file_type: tclSource }
+    - hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
+    file_type: xdc
 
   fpga-arm-emulation:
     depend:
@@ -136,39 +128,67 @@ filesets:
     - linux_femu/constraints/pin_assign.xdc: {file_type: xdc}
     - linux_femu/constraints/constraints.xdc: {file_type: xdc}
 
-  xdc-fpga-pynq-z2:
-    files:
-    - hw/fpga_cgra/constraints/pynq-z2/pin_assign.xdc
-    - hw/fpga/constraints/pynq-z2/constraints.xdc
-    file_type: xdc
-
-  xdc-fpga-zcu104:
-    files:
-    - hw/fpga_cgra/constraints/zcu104/pin_assign.xdc
-    file_type: xdc
-
-  netlist-fpga:
-    files:
-    - build/openhwgroup.org_systems_core-v-mini-mcu_0/nexys-a7-100t-vivado/core_v_mini_mcu_xiling_postsynth.v
-    file_type: verilogSource
-
 parameters:
   COREV_PULP:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables COREV_PULP custom RISC-V extension on the CV32E40P core. Admitted values: 1|0.
+    default: 0
+  FPU:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables RV32F RISC-V extension on the CV32E40P core. Admitted values: 1|0.
     default: 0
   JTAG_DPI:
     datatype: int
     paramtype: vlogparam
+    description: |
+      Enables testbench JTAG DIPs. Admitted values: 1|0.
+    default: 0
+  X_EXT:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables CORE-V-XIF interface for the CV32E40X and CV32E40PX cores. Admitted values: 1|0.
     default: 0
+  USE_EXTERNAL_DEVICE_EXAMPLE:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables testbench modules compilation. Admitted values: 1|0.
+    default: 1
   USE_UPF:
     datatype: bool
     paramtype: vlogdefine
-    default: false
+    description: |
+      Enables simulation with UPF with Modelsim/VCS
+  REMOVE_OBI_FIFO:
+    datatype: bool
+    paramtype: vlogdefine
+    description: |
+      Remove the FIFO between the BUS and the peripherals subsystems
   SYNTHESIS:
     datatype: bool
     paramtype: vlogdefine
     default: false
+  VERILATOR: #used by SV2V
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  SIM_SYSTEMC:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
+  FPGA_NEXYS:
+    datatype: bool
+    paramtype: vlogdefine
+    default: false
   FPGA_ZCU104:
     datatype: bool
     paramtype: vlogdefine
@@ -285,18 +305,21 @@ targets:
     description: TUL Pynq-Z2 Board
     filesets_append:
     - x_heep_system
-    - files_rtl_generic # Already added by default?
     - rtl-fpga
-    - ip-fpga-pynq-z2
-    - ip-fpga
     - xdc-fpga-pynq-z2
     - ext_bus
     parameters:
-    - COREV_PULP=0
+    - COREV_PULP
+    - FPU
+    - X_EXT
     - SYNTHESIS=true
+    - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
     tools:
       vivado:
         part: xc7z020clg400-1
+        board_part: tul.com.tw:pynq-z2:part0:1.0
+        board_repo_paths: [../../../hw/fpga/board_files/vendor/esl_epfl_pynq_z2_board_files]
     toplevel: [xilinx_heepsilon_wrapper]
 
   zcu104:
@@ -306,13 +329,15 @@ targets:
     filesets_append:
     - x_heep_system
     - rtl-fpga
-    - ip-fpga-zcu104
-    - ip-fpga
     - xdc-fpga-zcu104
     - ext_bus
     parameters:
-    - COREV_PULP=0
+    - COREV_PULP
+    - FPU
+    - X_EXT
     - SYNTHESIS=true
+    - REMOVE_OBI_FIFO
+    - FPGA_SYNTHESIS=true
     - FPGA_ZCU104=true
     tools:
       vivado:
diff --git a/hw/fpga_cgra/cgra_sram_wrapper.sv b/hw/fpga_cgra/cgra_sram_wrapper.sv
index 1d924b29..b9b65778 100644
--- a/hw/fpga_cgra/cgra_sram_wrapper.sv
+++ b/hw/fpga_cgra/cgra_sram_wrapper.sv
@@ -16,25 +16,87 @@ module cgra_sram_wrapper #(
     input  logic [AddrWidth-1:0] addr_i,   // request address
     input  logic [         31:0] wdata_i,  // write data
     input  logic [          3:0] be_i,     // write byte enable
-    input  logic                 set_retentive_i,
+    input  logic                 set_retentive_ni,
     // output ports
     output logic [         31:0] rdata_o   // read data
 );
-  sram_wrapper#(
-    .NumWords (NumWords),
-    .DataWidth(DataWidth),
-    .AddrWidth(AddrWidth)
-  ) sram_wrapper_i(
-    .clk_i          (clk_i),
-    .rst_ni         (rst_ni),
-    .req_i          (req_i),
-    .we_i           (we_i),
-    .addr_i         (addr_i),
-    .wdata_i        (wdata_i),
-    .be_i           (be_i),
-    .set_retentive_ni(set_retentive_i),
-    // output ports
-    .rdata_o        (rdata_o)
-  );
+
+  localparam int unsigned NUM_WORDS = NumWords;
+  
+  generate
+    if (NUM_WORDS == 128) begin
+      xilinx_emem_gen xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 512) begin
+      xilinx_mem_gen_2k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 1024) begin
+      xilinx_mem_gen_4k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 2048) begin
+      xilinx_mem_gen_8k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 4096) begin
+      xilinx_mem_gen_16k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 8192) begin
+      xilinx_mem_gen_32k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else if (NUM_WORDS == 16384) begin
+      xilinx_mem_gen_64k xilinx_sram_i (
+        .clka (clk_i),
+        .ena  (req_i),
+        .wea  ({4{req_i & we_i}} & be_i),
+        .addra(addr_i),
+        .dina (wdata_i),
+        // output ports
+        .douta(rdata_o)
+      );
+    end else begin
+      $error("Bank size not generated for NumWords = %0d.", NumWords);
+    end
+  endgenerate
 
 endmodule
\ No newline at end of file
diff --git a/hw/fpga_cgra/scripts/generate_sram_emem.tcl b/hw/fpga_cgra/scripts/generate_sram_emem.tcl
new file mode 100644
index 00000000..2907ec83
--- /dev/null
+++ b/hw/fpga_cgra/scripts/generate_sram_emem.tcl
@@ -0,0 +1,26 @@
+
+set ipName xilinx_emem_gen
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name $ipName
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \
+                        CONFIG.Use_Byte_Write_Enable {true}  \
+                        CONFIG.Byte_Size {8}  \
+                        CONFIG.Algorithm {Minimum_Area}  \
+                        CONFIG.Write_Width_A {32}  \
+                        CONFIG.Write_Depth_A {128}  \
+                        CONFIG.Read_Width_A {32}  \
+                        CONFIG.Enable_A {Use_ENA_Pin}  \
+                        CONFIG.Write_Width_B {32}  \
+                        CONFIG.Read_Width_B {32}  \
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
+                        CONFIG.Use_RSTA_Pin {false}  \
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips $ipName]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips $ipName]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1
diff --git a/hw/fpga_cgra/scripts/generate_sram_general.tcl b/hw/fpga_cgra/scripts/generate_sram_general.tcl
new file mode 100644
index 00000000..d134f9ed
--- /dev/null
+++ b/hw/fpga_cgra/scripts/generate_sram_general.tcl
@@ -0,0 +1,150 @@
+set ipName xilinx_mem_gen_2k
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name xilinx_mem_gen_2k
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \
+                        CONFIG.Use_Byte_Write_Enable {true}  \
+                        CONFIG.Byte_Size {8}  \
+                        CONFIG.Write_Width_A {32}  \
+                        CONFIG.Write_Depth_A {512}  \
+                        CONFIG.Read_Width_A {32}  \
+                        CONFIG.Enable_A {Use_ENA_Pin}  \
+                        CONFIG.Write_Width_B {32}  \
+                        CONFIG.Read_Width_B {32}  \
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
+                        CONFIG.Use_RSTA_Pin {false}  \
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips xilinx_mem_gen_2k]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips xilinx_mem_gen_2k]
+launch_run -jobs 8 xilinx_mem_gen_2k_synth_1
+
+set ipName xilinx_mem_gen_4k
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name xilinx_mem_gen_4k
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \
+                        CONFIG.Use_Byte_Write_Enable {true}  \
+                        CONFIG.Byte_Size {8}  \
+                        CONFIG.Write_Width_A {32}  \
+                        CONFIG.Write_Depth_A {1024}  \
+                        CONFIG.Read_Width_A {32}  \
+                        CONFIG.Enable_A {Use_ENA_Pin}  \
+                        CONFIG.Write_Width_B {32}  \
+                        CONFIG.Read_Width_B {32}  \
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
+                        CONFIG.Use_RSTA_Pin {false}  \
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips xilinx_mem_gen_4k]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips xilinx_mem_gen_4k]
+launch_run -jobs 8 xilinx_mem_gen_4k_synth_1
+
+set ipName xilinx_mem_gen_8k
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name xilinx_mem_gen_8k
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \
+                        CONFIG.Use_Byte_Write_Enable {true}  \
+                        CONFIG.Byte_Size {8}  \
+                        CONFIG.Write_Width_A {32}  \
+                        CONFIG.Write_Depth_A {2048}  \
+                        CONFIG.Read_Width_A {32}  \
+                        CONFIG.Enable_A {Use_ENA_Pin}  \
+                        CONFIG.Write_Width_B {32}  \
+                        CONFIG.Read_Width_B {32}  \
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
+                        CONFIG.Use_RSTA_Pin {false}  \
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips xilinx_mem_gen_8k]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips xilinx_mem_gen_8k]
+launch_run -jobs 8 xilinx_mem_gen_8k_synth_1
+
+set ipName xilinx_mem_gen_16k
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name xilinx_mem_gen_16k
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \
+                        CONFIG.Use_Byte_Write_Enable {true}  \
+                        CONFIG.Byte_Size {8}  \
+                        CONFIG.Write_Width_A {32}  \
+                        CONFIG.Write_Depth_A {4096}  \
+                        CONFIG.Read_Width_A {32}  \
+                        CONFIG.Enable_A {Use_ENA_Pin}  \
+                        CONFIG.Write_Width_B {32}  \
+                        CONFIG.Read_Width_B {32}  \
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
+                        CONFIG.Use_RSTA_Pin {false}  \
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips xilinx_mem_gen_16k]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips xilinx_mem_gen_16k]
+launch_run -jobs 8 xilinx_mem_gen_16k_synth_1
+
+set ipName xilinx_mem_gen_32k
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name xilinx_mem_gen_32k
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \
+                        CONFIG.Use_Byte_Write_Enable {true}  \
+                        CONFIG.Byte_Size {8}  \
+                        CONFIG.Write_Width_A {32}  \
+                        CONFIG.Write_Depth_A {8192}  \
+                        CONFIG.Read_Width_A {32}  \
+                        CONFIG.Enable_A {Use_ENA_Pin}  \
+                        CONFIG.Write_Width_B {32}  \
+                        CONFIG.Read_Width_B {32}  \
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
+                        CONFIG.Use_RSTA_Pin {false}  \
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips xilinx_mem_gen_32k]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips xilinx_mem_gen_32k]
+launch_run -jobs 8 xilinx_mem_gen_32k_synth_1
+
+set ipName xilinx_mem_gen_64k
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name xilinx_mem_gen_64k
+
+set_property -dict [list CONFIG.Enable_32bit_Address {false} \
+                        CONFIG.Use_Byte_Write_Enable {true}  \
+                        CONFIG.Byte_Size {8}  \
+                        CONFIG.Write_Width_A {32}  \
+                        CONFIG.Write_Depth_A {16384}  \
+                        CONFIG.Read_Width_A {32}  \
+                        CONFIG.Enable_A {Use_ENA_Pin}  \
+                        CONFIG.Write_Width_B {32}  \
+                        CONFIG.Read_Width_B {32}  \
+                        CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \
+                        CONFIG.Use_RSTA_Pin {false}  \
+                        CONFIG.EN_SAFETY_CKT {false}] [get_ips xilinx_mem_gen_64k]
+
+#generate_target {instantiation_template} [get_ips $ipName]
+
+#export_ip_user_files -of_objects [get_ips $ipName] -no_script -sync -force -quiet
+
+create_ip_run [get_ips xilinx_mem_gen_64k]
+launch_run -jobs 8 xilinx_mem_gen_64k_synth_1
+
+wait_on_run xilinx_mem_gen_2k_synth_1
+wait_on_run xilinx_mem_gen_4k_synth_1
+wait_on_run xilinx_mem_gen_8k_synth_1
+wait_on_run xilinx_mem_gen_16k_synth_1
+wait_on_run xilinx_mem_gen_32k_synth_1
+wait_on_run xilinx_mem_gen_64k_synth_1
diff --git a/hw/rtl/heepsilon_top.sv b/hw/rtl/heepsilon_top.sv
index 6ed60463..70366e66 100644
--- a/hw/rtl/heepsilon_top.sv
+++ b/hw/rtl/heepsilon_top.sv
@@ -126,12 +126,12 @@ module heepsilon_top #(
       .heep_core_data_resp_o    (heep_core_data_resp),
       .heep_debug_master_req_i  (heep_debug_master_req),
       .heep_debug_master_resp_o (heep_debug_master_resp),
-      .heep_dma_read_ch0_req_i  (heep_dma_read_ch0_req),
-      .heep_dma_read_ch0_resp_o (heep_dma_read_ch0_resp),
-      .heep_dma_write_ch0_req_i (heep_dma_write_ch0_req),
-      .heep_dma_write_ch0_resp_o(heep_dma_write_ch0_resp),
-      .heep_dma_addr_ch0_req_i  (heep_dma_addr_ch0_req),
-      .heep_dma_addr_ch0_resp_o (heep_dma_addr_ch0_resp),
+      .heep_dma_read_req_i  (heep_dma_read_ch0_req),
+      .heep_dma_read_resp_o (heep_dma_read_ch0_resp),
+      .heep_dma_write_req_i (heep_dma_write_ch0_req),
+      .heep_dma_write_resp_o(heep_dma_write_ch0_resp),
+      .heep_dma_addr_req_i  (heep_dma_addr_ch0_req),
+      .heep_dma_addr_resp_o (heep_dma_addr_ch0_resp),
 
       .ext_master_req_i (ext_master_req),
       .ext_master_resp_o(ext_master_resp),
@@ -245,12 +245,12 @@ module heepsilon_top #(
       .ext_core_data_resp_i(heep_core_data_resp),
       .ext_debug_master_req_o(heep_debug_master_req),
       .ext_debug_master_resp_i(heep_debug_master_resp),
-      .ext_dma_read_ch0_req_o(heep_dma_read_ch0_req),
-      .ext_dma_read_ch0_resp_i(heep_dma_read_ch0_resp),
-      .ext_dma_write_ch0_req_o(heep_dma_write_ch0_req),
-      .ext_dma_write_ch0_resp_i(heep_dma_write_ch0_resp),
-      .ext_dma_addr_ch0_req_o(heep_dma_addr_ch0_req),
-      .ext_dma_addr_ch0_resp_i(heep_dma_addr_ch0_resp),
+      .ext_dma_read_req_o(heep_dma_read_ch0_req),
+      .ext_dma_read_resp_i(heep_dma_read_ch0_resp),
+      .ext_dma_write_req_o(heep_dma_write_ch0_req),
+      .ext_dma_write_resp_i(heep_dma_write_ch0_resp),
+      .ext_dma_addr_req_o(heep_dma_addr_ch0_req),
+      .ext_dma_addr_resp_i(heep_dma_addr_ch0_resp),
       .external_subsystem_clkgate_en_no(external_subsystem_clkgate_en_n),
       .ext_peripheral_slave_req_o(ext_periph_slave_req),
       .ext_peripheral_slave_resp_i(ext_periph_slave_resp),
diff --git a/hw/vendor/esl_epfl_x_heep/configs/general.hjson b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
index 0afb35ef..ec460f78 100644
--- a/hw/vendor/esl_epfl_x_heep/configs/general.hjson
+++ b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
@@ -3,7 +3,7 @@
     bus_type: "onetoM",
     ram_banks: {
         code_and_data: {
-            num: 2
+            num: 8
             sizes: [32]
         }
     }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
index 3ebc1e77..db16c9a3 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
@@ -459,6 +459,42 @@ module core_v_mini_mcu
   assign memory_subsystem_banks_powergate_iso_n[1] = memory_subsystem_pwr_ctrl_out[1].isogate_en_n;
   assign memory_subsystem_banks_set_retentive_n[1] = memory_subsystem_pwr_ctrl_out[1].retentive_en_n;
   assign memory_subsystem_clkgate_en_n[1] = memory_subsystem_pwr_ctrl_out[1].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[2] = memory_subsystem_pwr_ctrl_out[2].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[2].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[2];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[2] = memory_subsystem_pwr_ctrl_out[2].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[2] = memory_subsystem_pwr_ctrl_out[2].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[2] = memory_subsystem_pwr_ctrl_out[2].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[3] = memory_subsystem_pwr_ctrl_out[3].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[3].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[3];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[3] = memory_subsystem_pwr_ctrl_out[3].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[3] = memory_subsystem_pwr_ctrl_out[3].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[3] = memory_subsystem_pwr_ctrl_out[3].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[4] = memory_subsystem_pwr_ctrl_out[4].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[4].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[4];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[4] = memory_subsystem_pwr_ctrl_out[4].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[4] = memory_subsystem_pwr_ctrl_out[4].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[4] = memory_subsystem_pwr_ctrl_out[4].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[5] = memory_subsystem_pwr_ctrl_out[5].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[5].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[5];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[5] = memory_subsystem_pwr_ctrl_out[5].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[5] = memory_subsystem_pwr_ctrl_out[5].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[5] = memory_subsystem_pwr_ctrl_out[5].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[6] = memory_subsystem_pwr_ctrl_out[6].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[6].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[6];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[6] = memory_subsystem_pwr_ctrl_out[6].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[6] = memory_subsystem_pwr_ctrl_out[6].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[6] = memory_subsystem_pwr_ctrl_out[6].clkgate_en_n;
+  assign memory_subsystem_banks_powergate_switch_n[7] = memory_subsystem_pwr_ctrl_out[7].pwrgate_en_n;
+  assign memory_subsystem_pwr_ctrl_in[7].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[7];
+  //isogate exposed outside for UPF sim flow and switch cells
+  assign memory_subsystem_banks_powergate_iso_n[7] = memory_subsystem_pwr_ctrl_out[7].isogate_en_n;
+  assign memory_subsystem_banks_set_retentive_n[7] = memory_subsystem_pwr_ctrl_out[7].retentive_en_n;
+  assign memory_subsystem_clkgate_en_n[7] = memory_subsystem_pwr_ctrl_out[7].clkgate_en_n;
 
   for (genvar i = 0; i < EXT_DOMAINS_RND; i = i + 1) begin
     assign external_subsystem_powergate_switch_no[i]        = external_subsystem_pwr_ctrl_out[i].pwrgate_en_n;
diff --git a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
index 2e43dd14..beed1bcf 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
@@ -137,8 +137,9 @@ module ext_bus #(
   // show writes if requested
   always_ff @(posedge clk_i, negedge rst_ni) begin : verbose_writes
     if ($test$plusargs("verbose") != 0 && heep_core_data_req_i.req && heep_core_data_req_i.we)
-      $display("write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr,
-               heep_core_data_req_i.wdata);
+      $display(
+          "write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr, heep_core_data_req_i.wdata
+      );
   end
 `endif
 

From e97c3081ca42e0db5b579be4241bca81a4c9d96b Mon Sep 17 00:00:00 2001
From: JoseCalero <mirandacalero.joseangel@gmail.com>
Date: Tue, 8 Oct 2024 12:18:25 +0200
Subject: [PATCH 24/27] deleting fpga xheep link

---
 hw/fpga | 1 -
 1 file changed, 1 deletion(-)
 delete mode 120000 hw/fpga

diff --git a/hw/fpga b/hw/fpga
deleted file mode 120000
index b31c1596..00000000
--- a/hw/fpga
+++ /dev/null
@@ -1 +0,0 @@
-./vendor/esl_epfl_x_heep/hw/fpga
\ No newline at end of file

From 9da9e3a3a831fb3e7d7599b9bdf5a67e2628a580 Mon Sep 17 00:00:00 2001
From: jmiranda <mirandacalero.joseangel@gmail.com>
Date: Tue, 8 Oct 2024 14:39:38 +0200
Subject: [PATCH 25/27] revendorizing x-heep to fix ci issues

---
 .../esl_epfl_x_heep/configs/general.hjson     |  2 +-
 .../hw/core-v-mini-mcu/core_v_mini_mcu.sv     | 36 -------------------
 hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv       |  5 ++-
 hw/vendor/eslepfl_x_heep.lock.hjson           |  2 +-
 hw/vendor/eslepfl_x_heep.vendor.hjson         |  2 +-
 5 files changed, 5 insertions(+), 42 deletions(-)

diff --git a/hw/vendor/esl_epfl_x_heep/configs/general.hjson b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
index ec460f78..0afb35ef 100644
--- a/hw/vendor/esl_epfl_x_heep/configs/general.hjson
+++ b/hw/vendor/esl_epfl_x_heep/configs/general.hjson
@@ -3,7 +3,7 @@
     bus_type: "onetoM",
     ram_banks: {
         code_and_data: {
-            num: 8
+            num: 2
             sizes: [32]
         }
     }
diff --git a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
index db16c9a3..3ebc1e77 100644
--- a/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
+++ b/hw/vendor/esl_epfl_x_heep/hw/core-v-mini-mcu/core_v_mini_mcu.sv
@@ -459,42 +459,6 @@ module core_v_mini_mcu
   assign memory_subsystem_banks_powergate_iso_n[1] = memory_subsystem_pwr_ctrl_out[1].isogate_en_n;
   assign memory_subsystem_banks_set_retentive_n[1] = memory_subsystem_pwr_ctrl_out[1].retentive_en_n;
   assign memory_subsystem_clkgate_en_n[1] = memory_subsystem_pwr_ctrl_out[1].clkgate_en_n;
-  assign memory_subsystem_banks_powergate_switch_n[2] = memory_subsystem_pwr_ctrl_out[2].pwrgate_en_n;
-  assign memory_subsystem_pwr_ctrl_in[2].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[2];
-  //isogate exposed outside for UPF sim flow and switch cells
-  assign memory_subsystem_banks_powergate_iso_n[2] = memory_subsystem_pwr_ctrl_out[2].isogate_en_n;
-  assign memory_subsystem_banks_set_retentive_n[2] = memory_subsystem_pwr_ctrl_out[2].retentive_en_n;
-  assign memory_subsystem_clkgate_en_n[2] = memory_subsystem_pwr_ctrl_out[2].clkgate_en_n;
-  assign memory_subsystem_banks_powergate_switch_n[3] = memory_subsystem_pwr_ctrl_out[3].pwrgate_en_n;
-  assign memory_subsystem_pwr_ctrl_in[3].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[3];
-  //isogate exposed outside for UPF sim flow and switch cells
-  assign memory_subsystem_banks_powergate_iso_n[3] = memory_subsystem_pwr_ctrl_out[3].isogate_en_n;
-  assign memory_subsystem_banks_set_retentive_n[3] = memory_subsystem_pwr_ctrl_out[3].retentive_en_n;
-  assign memory_subsystem_clkgate_en_n[3] = memory_subsystem_pwr_ctrl_out[3].clkgate_en_n;
-  assign memory_subsystem_banks_powergate_switch_n[4] = memory_subsystem_pwr_ctrl_out[4].pwrgate_en_n;
-  assign memory_subsystem_pwr_ctrl_in[4].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[4];
-  //isogate exposed outside for UPF sim flow and switch cells
-  assign memory_subsystem_banks_powergate_iso_n[4] = memory_subsystem_pwr_ctrl_out[4].isogate_en_n;
-  assign memory_subsystem_banks_set_retentive_n[4] = memory_subsystem_pwr_ctrl_out[4].retentive_en_n;
-  assign memory_subsystem_clkgate_en_n[4] = memory_subsystem_pwr_ctrl_out[4].clkgate_en_n;
-  assign memory_subsystem_banks_powergate_switch_n[5] = memory_subsystem_pwr_ctrl_out[5].pwrgate_en_n;
-  assign memory_subsystem_pwr_ctrl_in[5].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[5];
-  //isogate exposed outside for UPF sim flow and switch cells
-  assign memory_subsystem_banks_powergate_iso_n[5] = memory_subsystem_pwr_ctrl_out[5].isogate_en_n;
-  assign memory_subsystem_banks_set_retentive_n[5] = memory_subsystem_pwr_ctrl_out[5].retentive_en_n;
-  assign memory_subsystem_clkgate_en_n[5] = memory_subsystem_pwr_ctrl_out[5].clkgate_en_n;
-  assign memory_subsystem_banks_powergate_switch_n[6] = memory_subsystem_pwr_ctrl_out[6].pwrgate_en_n;
-  assign memory_subsystem_pwr_ctrl_in[6].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[6];
-  //isogate exposed outside for UPF sim flow and switch cells
-  assign memory_subsystem_banks_powergate_iso_n[6] = memory_subsystem_pwr_ctrl_out[6].isogate_en_n;
-  assign memory_subsystem_banks_set_retentive_n[6] = memory_subsystem_pwr_ctrl_out[6].retentive_en_n;
-  assign memory_subsystem_clkgate_en_n[6] = memory_subsystem_pwr_ctrl_out[6].clkgate_en_n;
-  assign memory_subsystem_banks_powergate_switch_n[7] = memory_subsystem_pwr_ctrl_out[7].pwrgate_en_n;
-  assign memory_subsystem_pwr_ctrl_in[7].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[7];
-  //isogate exposed outside for UPF sim flow and switch cells
-  assign memory_subsystem_banks_powergate_iso_n[7] = memory_subsystem_pwr_ctrl_out[7].isogate_en_n;
-  assign memory_subsystem_banks_set_retentive_n[7] = memory_subsystem_pwr_ctrl_out[7].retentive_en_n;
-  assign memory_subsystem_clkgate_en_n[7] = memory_subsystem_pwr_ctrl_out[7].clkgate_en_n;
 
   for (genvar i = 0; i < EXT_DOMAINS_RND; i = i + 1) begin
     assign external_subsystem_powergate_switch_no[i]        = external_subsystem_pwr_ctrl_out[i].pwrgate_en_n;
diff --git a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
index beed1bcf..2e43dd14 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
@@ -137,9 +137,8 @@ module ext_bus #(
   // show writes if requested
   always_ff @(posedge clk_i, negedge rst_ni) begin : verbose_writes
     if ($test$plusargs("verbose") != 0 && heep_core_data_req_i.req && heep_core_data_req_i.we)
-      $display(
-          "write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr, heep_core_data_req_i.wdata
-      );
+      $display("write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr,
+               heep_core_data_req_i.wdata);
   end
 `endif
 
diff --git a/hw/vendor/eslepfl_x_heep.lock.hjson b/hw/vendor/eslepfl_x_heep.lock.hjson
index c62e55c8..213b5fa1 100644
--- a/hw/vendor/eslepfl_x_heep.lock.hjson
+++ b/hw/vendor/eslepfl_x_heep.lock.hjson
@@ -8,7 +8,7 @@
 {
   upstream:
   {
-    url: https://github.com/Luigi2898/x-heep.git
+    url: https://github.com/esl-epfl/x-heep.git
     rev: 83f1563fd4894787167b27099006c8b1b042d3d1
   }
 }
diff --git a/hw/vendor/eslepfl_x_heep.vendor.hjson b/hw/vendor/eslepfl_x_heep.vendor.hjson
index 655e0a58..0dcb0caa 100644
--- a/hw/vendor/eslepfl_x_heep.vendor.hjson
+++ b/hw/vendor/eslepfl_x_heep.vendor.hjson
@@ -7,7 +7,7 @@
   target_dir: "esl_epfl_x_heep",
 
   upstream: {
-    url: "https://github.com/Luigi2898/x-heep.git",
+    url: "https://github.com/esl-epfl/x-heep.git",
     rev: "83f1563fd4894787167b27099006c8b1b042d3d1",
   },
 

From 8a0170b7ba7deb81aa9eef4d660bcb58283184b5 Mon Sep 17 00:00:00 2001
From: jmiranda <mirandacalero.joseangel@gmail.com>
Date: Tue, 8 Oct 2024 14:58:50 +0200
Subject: [PATCH 26/27] revendorizing x-heep and cgra to fix ci issues

---
 .../util/INSTRUCTIONS_FFT_SPLITOPS.py         | 186 ------------------
 .../util/instructions_max_peak.py             |  87 --------
 .../util/instructions_min_max_circular.py     |  83 --------
 hw/vendor/esl_epfl_x_heep/Makefile            |  12 +-
 hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt   |  58 ++++--
 hw/vendor/esl_epfl_x_heep/sw/Makefile         |  14 +-
 .../esl_epfl_x_heep/sw/cmake/targets.mak      |  10 +-
 hw/vendor/eslepfl_cgra.lock.hjson             |   2 +-
 hw/vendor/eslepfl_cgra.vendor.hjson           |   2 +-
 hw/vendor/eslepfl_x_heep.lock.hjson           |   2 +-
 hw/vendor/eslepfl_x_heep.vendor.hjson         |   2 +-
 11 files changed, 66 insertions(+), 392 deletions(-)
 delete mode 100644 hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py
 delete mode 100644 hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py
 delete mode 100644 hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py

diff --git a/hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py b/hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py
deleted file mode 100644
index 75586fca..00000000
--- a/hw/vendor/esl_epfl_cgra/util/INSTRUCTIONS_FFT_SPLITOPS.py
+++ /dev/null
@@ -1,186 +0,0 @@
-# FFT OUTPUT SPLIT OPS instructions DEPREDECATED
-
-instructions.append(["NEXT RC"])
-
-# RC1_0
-# PROLOGUE
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["RF2", "CONST", "SADD", "RF2", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-
-# RC1_1
-# PROLOGUE
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF2", "CONST", "SSUB", "RF2", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-#################################################################################################
-#################################################################################################
-#################################################################################################
-
-instructions.append(["NEXT RC"])
-
-# RC2_0
-# PROLOGUE
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["DATA", "OUT_D", "IN1", "RF3", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF3", "RCT", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCB", "OUT_D", "IN1", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCT", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "EXIT", "RF1", "OFF", "OUT_F", "0"])
-
-
-# RC2_1
-# PROLOGUE
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["DATA", "OUT_D", "IN1", "RF3", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF3", "RCT", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCL", "OUT_D", "FXP_ADD", "RF2", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCL", "RCB", "FXP_SUB", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF2", "OUT_D", "FXP_ADD", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-#################################################################################################
-#################################################################################################
-#################################################################################################
-
-instructions.append(["NEXT RC"])
-
-# RC3_0
-# PROLOGUE
-instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-instructions.append(["RF1", "CONST", "SSUB", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF2", "CONST", "SSUB", "RF2", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCB", "RF1", "SWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-
-# RC3_1
-# PROLOGUE
-instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-instructions.append(["RF1", "CONST", "SSUB", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "IN1", "RF3", "ON", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "IN1", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF3", "OUT_D", "FXP_MUL", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCT", "RF1", "SWI", "RF1", "OFF", "OUT_F", "0"])
-
-#################################################################################################
-#################################################################################################
-#################################################################################################
-
-instructions.append(["NEXT RC"])
-
-# RC4_0
-# PROLOGUE
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCR", "OUT_D", "FXP_MUL", "RF2", "ON", "OUT_F", "0"])
-instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["RF2", "RCB", "FXP_SUB", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCT", "OUT_D", "FXP_ADD", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RCB", "OUT_D", "FXP_ADD", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-
-
-# RC4_1
-# PROLOGUE
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF1", "ON", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF2", "ON", "OUT_F", "0"])
-instructions.append(["DATA", "OUT_D", "LWD", "RF3", "ON", "OUT_F", "0"])
-
-# ITERATION LOOP
-instructions.append(["DATA", "RF1", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF1", "CONST", "SADD", "RF1", "ON", "OUT_F", "4"])
-instructions.append(["DATA", "RF2", "LWI", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF2", "CONST", "SADD", "RF2", "ON", "OUT_F", "4"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF4", "CONST", "SADD", "RF4", "ON", "OUT_F", "1"])
-instructions.append(["ZEROS", "OUT_D", "NOP", "RF1", "OFF", "OUT_F", "0"])
-instructions.append(["RF4", "RF3", "BLT", "RF1", "OFF", "OUT_F", "6"])
-
-
-#################################################################################################
-#################################################################################################
-#################################################################################################
-
-kernel_col_needed = "0011"
-row_st_add = 58
-n_instructions = 14
diff --git a/hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py b/hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py
deleted file mode 100644
index 5c236c82..00000000
--- a/hw/vendor/esl_epfl_cgra/util/instructions_max_peak.py
+++ /dev/null
@@ -1,87 +0,0 @@
-#
-# MAX_PEAK search instructions DEPREDECATED
-#
-
-ker_col_needed = 1
-ker_num_instr  = 11
-
-ker_conf_words[ker_next_id] = get_bin(int(pow(2,ker_col_needed))-1,CGRA_N_COL) +\
-                                get_bin(ker_start_add, CGRA_IMEM_NL_LOG2) +\
-                                get_bin(ker_num_instr-1, RCS_NUM_CREG_LOG2)
-
-# Save current start address
-start_add     = ker_start_add
-# Update start address and ID for next kernel
-ker_start_add = ker_start_add + ker_num_instr*ker_col_needed
-ker_next_id   = ker_next_id+1
-
-# Used for multi-column kernels
-k = ker_num_instr
-
-#################################################################################################
-############################################## RC0 ##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[0][start_add+ 0] = rcs_nop_instr
-rcs_instructions[0][start_add+ 1] = rcs_nop_instr
-rcs_instructions[0][start_add+ 2] = ["SRAM",    "-",  "LWD", "R1",      "-", "-"]
-rcs_instructions[0][start_add+ 3] = ["SRAM",    "-",  "LWD", "R0",      "-", "-"]
-rcs_instructions[0][start_add+ 4] = rcs_nop_instr
-rcs_instructions[0][start_add+ 5] = [  "R2",   "R1", "SSUB",  "-",      "-", "-"]
-rcs_instructions[0][start_add+ 6] = [  "R1",   "R2", "BSFA",  "-",   "PREV", "-"]
-rcs_instructions[0][start_add+ 7] = [  "R2", "PREV", "BSFA", "R2",    "RCB", "-"]
-rcs_instructions[0][start_add+ 8] = [  "R0",    "-",  "INA", "R1",      "-", "-"]
-rcs_instructions[0][start_add+ 9] = rcs_nop_instr
-rcs_instructions[0][start_add+10] = [  "R2",    "-",  "SWD",  "-",      "-", "-"]
-
-#################################################################################################
-############################################## RC1 ##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[1][start_add+ 0] = rcs_nop_instr
-rcs_instructions[1][start_add+ 1] = ["SRAM",    "-",  "LWD", "R0",      "-", "-"]
-rcs_instructions[1][start_add+ 2] = [   "-",  "IMM",  "INB", "R1",      "-", "-1"]
-rcs_instructions[1][start_add+ 3] = [ "RCT",    "-",  "INA", "R3",      "-", "-"]
-rcs_instructions[1][start_add+ 4] = [  "R3",   "R0", "SSUB",  "-",      "-", "-"]
-rcs_instructions[1][start_add+ 5] = [  "R1",   "R2", "BSFA",  "-",   "PREV", "-"]
-rcs_instructions[1][start_add+ 6] = [ "RCB", "PREV", "SADD",  "-",      "-", "-"]
-rcs_instructions[1][start_add+ 7] = rcs_nop_instr
-rcs_instructions[1][start_add+ 8] = [  "R3",    "-",  "INA", "R0",      "-", "-"]
-rcs_instructions[1][start_add+ 9] = rcs_nop_instr
-rcs_instructions[1][start_add+10] = rcs_nop_instr
-
-#################################################################################################
-############################################## RC2 ##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[2][start_add+ 0] = rcs_nop_instr
-rcs_instructions[2][start_add+ 1] = rcs_nop_instr
-rcs_instructions[2][start_add+ 2] = [   "-",  "IMM",  "INB", "R1",      "-", "-1"]
-rcs_instructions[2][start_add+ 3] = ["SRAM",    "-",  "INA",  "-",      "-", "-"]
-rcs_instructions[2][start_add+ 4] = [ "RCB", "PREV", "SSUB",  "-",      "-", "-"]
-rcs_instructions[2][start_add+ 5] = [  "R1",   "R2", "BSFA",  "-",   "PREV", "-"]
-rcs_instructions[2][start_add+ 6] = [ "RCT", "PREV", "SADD",  "-",      "-", "-"]
-rcs_instructions[2][start_add+ 7] = rcs_nop_instr
-rcs_instructions[2][start_add+ 8] = rcs_nop_instr
-rcs_instructions[2][start_add+ 9] = rcs_nop_instr
-rcs_instructions[2][start_add+10] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
-
-#################################################################################################
-############################################## RC3 ##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[3][start_add+ 0] = ["SRAM",    "-",  "LWD", "R3",      "-", "-"]
-rcs_instructions[3][start_add+ 1] = rcs_nop_instr
-rcs_instructions[3][start_add+ 2] = ["SRAM",    "-",  "INA", "R1",      "-", "-"]
-rcs_instructions[3][start_add+ 3] = [  "R1",    "-",  "INA",  "-",      "-", "-"]
-rcs_instructions[3][start_add+ 4] = [ "RCB",    "-",  "INA", "R1",      "-", "-"]
-rcs_instructions[3][start_add+ 5] = [  "R0",  "IMM", "SADD", "R0",      "-", "1"]
-rcs_instructions[3][start_add+ 6] = [  "R0",   "R2", "BSFA",  "-",    "RCB", "-"]
-rcs_instructions[3][start_add+ 7] = [  "R2", "PREV", "BSFA", "R2",    "RCT", "-"]
-rcs_instructions[3][start_add+ 8] = [  "R0",   "R3",  "BLT",  "-",      "-", "3"]
-rcs_instructions[3][start_add+ 9] = [  "R2",    "-",  "SWD",  "-",      "-", "-"]
-rcs_instructions[3][start_add+10] = rcs_nop_instr
diff --git a/hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py b/hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py
deleted file mode 100644
index 2669aa8d..00000000
--- a/hw/vendor/esl_epfl_cgra/util/instructions_min_max_circular.py
+++ /dev/null
@@ -1,83 +0,0 @@
-#
-# MIN_MAX_CIRCULAR search instructions (manual mapping) DEPREDECATED
-#
-
-ker_col_needed = 1
-ker_num_instr  = 10
-
-ker_conf_words[ker_next_id] = get_bin(int(pow(2,ker_col_needed))-1,CGRA_N_COL) +\
-                                get_bin(ker_start_add, CGRA_IMEM_NL_LOG2) +\
-                                get_bin(ker_num_instr-1, RCS_NUM_CREG_LOG2)
-
-# Save current start address
-start_add     = ker_start_add
-# Update start address and ID for next kernel
-ker_start_add = ker_start_add + ker_num_instr*ker_col_needed
-ker_next_id   = ker_next_id+1
-
-# Used for multi-column kernels
-k = ker_num_instr
-
-#################################################################################################
-############################################## RC0 ##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[0][start_add+ 0] = rcs_nop_instr
-rcs_instructions[0][start_add+ 1] = [ "RCB",  "IMM",  "SLT", "R3",      "-", "2"]
-rcs_instructions[0][start_add+ 2] = [ "RCB",  "IMM",  "SLT", "R1",      "-", "2"]
-rcs_instructions[0][start_add+ 3] = ["SRAM",    "-",  "LWD", "R0",      "-", "-"]
-rcs_instructions[0][start_add+ 4] = [  "R0",   "R1", "SADD",  "-",      "-", "-"]
-rcs_instructions[0][start_add+ 5] = [  "R1",  "IMM", "SADD",  "-",      "-", "4"]
-rcs_instructions[0][start_add+ 6] = [  "R3", "PREV", "LAND", "R1",      "-", "-"]
-rcs_instructions[0][start_add+ 7] = [  "R0",   "R1", "SADD",  "-",      "-", "-"]
-rcs_instructions[0][start_add+ 8] = rcs_nop_instr
-rcs_instructions[0][start_add+ 9] = rcs_nop_instr
-
-#################################################################################################
-############################################## RC1 ##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[1][start_add+ 0] = ["SRAM",    "-",  "LWD",  "-",      "-", "-"]
-rcs_instructions[1][start_add+ 1] = ["SRAM",    "-",  "LWD",  "-",      "-", "-"]
-rcs_instructions[1][start_add+ 2] = ["SRAM",    "-",  "LWD", "R3",      "-", "-"]
-rcs_instructions[1][start_add+ 3] = rcs_nop_instr
-rcs_instructions[1][start_add+ 4] = rcs_nop_instr
-rcs_instructions[1][start_add+ 5] = ["SRAM",  "RCT",  "LWI",  "-",      "-", "-"]
-rcs_instructions[1][start_add+ 6] = [  "R0",  "IMM", "SADD", "R0",      "-", "1"]
-rcs_instructions[1][start_add+ 7] = [  "R0",   "R3",  "BLT",  "-",      "-", "5"]
-rcs_instructions[1][start_add+ 8] = rcs_nop_instr
-rcs_instructions[1][start_add+ 9] = rcs_nop_instr
-
-#################################################################################################
-############################################## RC2 ##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[2][start_add+ 0] = rcs_nop_instr
-rcs_instructions[2][start_add+ 1] = rcs_nop_instr
-rcs_instructions[2][start_add+ 2] = rcs_nop_instr
-rcs_instructions[2][start_add+ 3] = rcs_nop_instr
-rcs_instructions[2][start_add+ 4] = rcs_nop_instr
-rcs_instructions[2][start_add+ 5] = ["SRAM",    "-",  "INA", "R1",      "-", "-"]
-rcs_instructions[2][start_add+ 6] = [  "R0",   "R1", "SSUB",  "-",      "-", "-"]
-rcs_instructions[2][start_add+ 7] = [  "R1",   "R0", "BSFA", "R0",   "PREV", "-"]
-rcs_instructions[2][start_add+ 8] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
-rcs_instructions[2][start_add+ 9] = [   "-",    "-", "EXIT",  "-",      "-", "-"]
-
-#################################################################################################
-############################################## RC03##############################################
-#################################################################################################
-
-# COLUMN-0
-rcs_instructions[3][start_add+ 0] = rcs_nop_instr
-rcs_instructions[3][start_add+ 1] = rcs_nop_instr
-rcs_instructions[3][start_add+ 2] = rcs_nop_instr
-rcs_instructions[3][start_add+ 3] = rcs_nop_instr
-rcs_instructions[3][start_add+ 4] = rcs_nop_instr
-rcs_instructions[3][start_add+ 5] = ["SRAM",    "-",  "INA", "R1",      "-", "-"]
-rcs_instructions[3][start_add+ 6] = [  "R0",   "R1", "SSUB",  "-",      "-", "-"]
-rcs_instructions[3][start_add+ 7] = [  "R0",   "R1", "BSFA", "R0",   "PREV", "-"]
-rcs_instructions[3][start_add+ 8] = rcs_nop_instr
-rcs_instructions[3][start_add+ 9] = [  "R0",    "-",  "SWD",  "-",      "-", "-"]
diff --git a/hw/vendor/esl_epfl_x_heep/Makefile b/hw/vendor/esl_epfl_x_heep/Makefile
index f65c4640..e1c6deac 100644
--- a/hw/vendor/esl_epfl_x_heep/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/Makefile
@@ -150,13 +150,13 @@ verible:
 ## @param COMPILER_PREFIX=riscv32-unknown-(default)
 ## @param ARCH=rv32imc(default), <any RISC-V ISA string supported by the CPU>
 app: clean-app
-	$(MAKE) -C sw PROJECT=$(PROJECT) TARGET=$(TARGET) LINKER=$(LINKER) LINK_FOLDER=$(LINK_FOLDER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH) SOURCE=$(SOURCE) \
+	@$(MAKE) -C sw PROJECT=$(PROJECT) TARGET=$(TARGET) LINKER=$(LINKER) LINK_FOLDER=$(LINK_FOLDER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH) SOURCE=$(SOURCE) \
 	|| { \
-	echo "\033[0;31mHmmm... seems like the compilation failed...\033[0m"; \
-	echo "\033[0;31mIf you do not understand why, it is likely that you either:\033[0m"; \
-	echo "\033[0;31m  a) offended the Leprechaun of Electronics\033[0m"; \
-	echo "\033[0;31m  b) forgot to run make mcu-gen\033[0m"; \
-	echo "\033[0;31mI would start by checking b) if I were you!\033[0m"; \
+	@echo "\033[0;31mHmmm... seems like the compilation failed...\033[0m"; \
+	@echo "\033[0;31mIf you do not understand why, it is likely that you either:\033[0m"; \
+	@echo "\033[0;31m  a) offended the Leprechaun of Electronics\033[0m"; \
+	@echo "\033[0;31m  b) forgot to run make mcu-gen\033[0m"; \
+	@echo "\033[0;31mI would start by checking b) if I were you!\033[0m"; \
 	exit 1; \
 	}
 
diff --git a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
index cdb2a8f7..adc4546e 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
+++ b/hw/vendor/esl_epfl_x_heep/sw/CMakeLists.txt
@@ -13,7 +13,7 @@
 # OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 # PERFORMANCE OF THIS SOFTWARE.
 
-# Author: Juan Sapriza (juan.sapriza@epfl.ch)
+# Author: Jose Miranda, Juan Sapriza (jose.mirandacalero / juan.sapriza @epfl.ch)
 
 cmake_minimum_required(VERSION 3.15)
 
@@ -154,7 +154,9 @@ ENDFOREACH()
 
 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
 # If the app was not found, look into the root project
+# Before re-setting SOURCE_PATH, save it so we can look later for external defined files
 
+SET(ORIGIN_SRCPATH ${SOURCE_PATH})
 if( app_found EQUAL 0 )
   SET(SOURCE_PATH ${ROOT_PROJECT})
 
@@ -185,9 +187,9 @@ if( app_found EQUAL 0 )
       string(REPLACE ";" "" c_dir_list ${c_dir_list})
     endif()
 
-    ENDFOREACH()
-  endif()
-  
+  ENDFOREACH()
+endif()
+
 LIST(REMOVE_DUPLICATES c_dir_list)
 
 
@@ -204,6 +206,11 @@ else()
   message( "${Magenta}External application${ColourReset}")
 endif()
 
+#######################################################################
+#      ADD CUSTOM DEFINITIONS
+#######################################################################
+add_compile_definitions($ENV{CDEFS})
+
 #######################################################################
 #      FIND CRT FILES TO BE INCLUDED
 #######################################################################
@@ -219,15 +226,27 @@ SET(LIB_VCTR_P  "${ROOT_PROJECT}device/lib/crt/vectors.S")
 
 SET(CRTO "INTERNAL_CRTO")
 SET( LIB_CRT_EXT_P  "" )
-if( internal_app EQUAL 0 )
- FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS "${SOURCE_PATH}/external/lib/crt/*.S")
+FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS "${SOURCE_PATH}/external/lib/crt/*.S")
+FOREACH(file_path IN LISTS new_list)
+  if(${file_path} MATCHES "external_crt0.S")
+    SET( CRTO "EXTERNAL_CRTO" )
+    SET( LIB_CRT_EXT_P  "${file_path}" )
+    GET_FILENAME_COMPONENT(dir_path ${file_path} PATH)
+    SET(INCLUDE_FOLDERS "${INCLUDE_FOLDERS} -I ${dir_path}")
+    SET(h_dir_list_ ${h_dir_list_} "${dir_path}")
+  endif()
+ENDFOREACH()
+
+#In case the application is internal, but there is still an external CRT
+if(NOT ${ORIGIN_SRCPATH} MATCHES ${SOURCE_PATH})
+ FILE(GLOB_RECURSE new_list FOLLOW_SYMLINKS "${ORIGIN_SRCPATH}external/lib/crt/*.S")
  FOREACH(file_path IN LISTS new_list)
    if(${file_path} MATCHES "external_crt0.S")
-      SET( CRTO "EXTERNAL_CRTO" )
-      SET( LIB_CRT_EXT_P  "${file_path}" )
-      GET_FILENAME_COMPONENT(dir_path ${file_path} PATH)
-      SET(INCLUDE_FOLDERS "${INCLUDE_FOLDERS} -I ${dir_path}")
-      SET(h_dir_list_ ${h_dir_list_} "${dir_path}")
+     SET( CRTO "EXTERNAL_CRTO" )
+     SET( LIB_CRT_EXT_P  "${file_path}" )
+     GET_FILENAME_COMPONENT(dir_path ${file_path} PATH)
+     SET(INCLUDE_FOLDERS "${INCLUDE_FOLDERS} -I ${dir_path}")
+     SET(h_dir_list_ ${h_dir_list_} "${dir_path}")
    endif()
  ENDFOREACH()
 endif()
@@ -262,6 +281,7 @@ else()
   message( FATAL_ERROR "Linker specification is not correct" )
 endif()
 
+if (${VERBOSE} MATCHES "true")
 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
 # Debug messages to check the paths
 
@@ -271,10 +291,10 @@ message( "${Magenta}Root project: ${ROOT_PROJECT}${ColourReset}")
 message( "${Magenta}Source path: ${SOURCE_PATH}${ColourReset}")
 message( "${Magenta}LIB_CRT PATH for Cmake: ${LIB_CRT_P}${ColourReset}")
 message( "${Magenta}LINKER File for Cmake: ${LINK_FILE}${ColourReset}")
-message( "${Magenta}LIB_DRIVERS PATH for Cmake: ${LIB_DRIVERS}${ColourReset}")
-message( "${Magenta}Targetting folder: ${INC_FOLDERS}${ColourReset}")
 message( "${Magenta}Target: ${TARGET}${ColourReset}")
 
+endif()
+
 
 #######################################################################
 #      SET LINKER PROPERTIES
@@ -289,7 +309,9 @@ SET(LINKED_FILES    "${LIB_CRT_P} \
                      ${LIB_CRT_EXT_P} \
                      ${c_dir_list}") 
 
-message( "${Magenta}Linked files: ${LINKED_FILES}${ColourReset}")
+if (${VERBOSE} MATCHES "true")
+ message( "${Magenta}Linked files: ${LINKED_FILES}${ColourReset}")
+endif()
 
 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
 # Free-RTOS configurations
@@ -413,7 +435,11 @@ SET(CMAKE_EXE_LINKER_FLAGS  "-T ${LINKER_SCRIPT}  \
                             -ffunction-sections -fdata-sections -specs=nano.specs")
 message( "${Magenta}Lib Folder RISCV-GCC: ${RISCV}/${COMPILER_PREFIX}elf/lib${ColourReset}")
 
-SET(CMAKE_VERBOSE_MAKEFILE on)
+if (${VERBOSE} MATCHES "true")
+ SET(CMAKE_VERBOSE_MAKEFILE ON)
+else()
+ SET(CMAKE_VERBOSE_MAKEFILE OFF)
+endif()
 
 # To make sure that .obj files are created and fetched from the same path.
 # When setting an inner path to add_executable, .obj files are stored in ${MAINFILE}.elf.dir/<relative path>
@@ -434,7 +460,7 @@ if (${COMPILER} MATCHES "clang")
 								_deps/freertos_kernel-build/libfreertos_kernel.a \ _deps/freertos_kernel-build/portable/libfreertos_kernel_port.a \ _deps/freertos_kernel-build/libfreertos_kernel.a \ _deps/freertos_kernel-build/portable/libfreertos_kernel_port.a \
 								")
 	else()
-  set( CMAKE_C_LINK_EXECUTABLE "${CMAKE_LINKER} ${COMPILER_LINKER_FLAGS} ${CMAKE_EXE_LINKER_FLAGS} \
+    set( CMAKE_C_LINK_EXECUTABLE "${CMAKE_LINKER} ${COMPILER_LINKER_FLAGS} ${CMAKE_EXE_LINKER_FLAGS} \
                                 ${SOURCE_PATH}build/CMakeFiles/${MAINFILE}.elf.dir/${OBJ_PATH}applications/${PROJECT}/${MAINFILE}.c.obj \
                                 -o ${MAINFILE}.elf")
     endif()
diff --git a/hw/vendor/esl_epfl_x_heep/sw/Makefile b/hw/vendor/esl_epfl_x_heep/sw/Makefile
index e327138b..e0fa1ff1 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/Makefile
+++ b/hw/vendor/esl_epfl_x_heep/sw/Makefile
@@ -15,7 +15,7 @@
 # OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 # PERFORMANCE OF THIS SOFTWARE.
 
-# Author: Juan Sapriza (juan.sapriza@epfl.ch)
+# Author: Jose Miranda, Juan Sapriza (jose.mirandacalero / juan.sapriza @epfl.ch)
 
 MAKE                       = make
 
@@ -40,6 +40,8 @@ ARCH     ?= rv32imc
 # Path relative from the location of sw/Makefile from which to fetch source files. The directory of that file is the default value.
 SOURCE 	 ?= $(".")
 
+VERBOSE ?= false
+
 # riscv toolchain install path
 RISCV                      ?= ~/.riscv
 RISCV_EXE_PREFIX           = $(RISCV)/bin/${COMPILER_PREFIX}elf-
@@ -48,13 +50,14 @@ RISCV_GDB_PATH             = $(RISCV_EXE_PREFIX)gdb
 # Get the absolute path
 mkfile_path := $(shell dirname "$(realpath $(firstword $(MAKEFILE_LIST)))")
 
-# Check the absolute path
-$(info $$You are executing from: $(mkfile_path))
-
 # Get the absolute path of where to fetch sources
 source_path := $(realpath $(mkfile_path)/$(SOURCE))
-$(info $$You are fetching sources from $(source_path) )
 
+ifeq ($(ARG), value1)
+  $(info $$You are executing from: $(mkfile_path))
+else ifeq ($(ARG), value2)
+  $(info $$You are fetching sources from $(source_path) )
+endif
 
 SOURCE_PATH   		       = $(source_path)/
 ROOT_PROJECT               = $(mkfile_path)/
@@ -64,6 +67,7 @@ LINK_FOLDER                ?= $(mkfile_path)/linker
 # CMake keyword
 CMAKE_DIR=cmake
 
+# to distinguish between cmake distros
 ifeq (, $(shell which cmake3)) # cmake3 is not defined
 CMAKE=cmake
 else
diff --git a/hw/vendor/esl_epfl_x_heep/sw/cmake/targets.mak b/hw/vendor/esl_epfl_x_heep/sw/cmake/targets.mak
index 33ab1777..d7679da5 100644
--- a/hw/vendor/esl_epfl_x_heep/sw/cmake/targets.mak
+++ b/hw/vendor/esl_epfl_x_heep/sw/cmake/targets.mak
@@ -13,17 +13,17 @@
 # OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 # PERFORMANCE OF THIS SOFTWARE.
 
-# Author: Juan Sapriza (juan.sapriza@epfl.ch)
+# Author: Jose Miranda, Juan Sapriza (jose.mirandacalero / juan.sapriza @epfl.ch)
 
 build : build/Makefile
 	@echo Build 
-	${MAKE} -C build
+	${MAKE} -s -C build
 
 setup : build/Makefile
 
 build/Makefile : CMakeLists.txt ${CMAKE_DIR}/riscv.cmake
-	if [ ! -d build ] ; then mkdir build ; fi
-	cd build;  \
+	@if [ ! -d build ] ; then mkdir build ; fi
+	@cd build;  \
 		${CMAKE} \
 		    -G "Unix Makefiles" \
 			-DCMAKE_TOOLCHAIN_FILE=../${CMAKE_DIR}/riscv.cmake \
@@ -32,11 +32,11 @@ build/Makefile : CMakeLists.txt ${CMAKE_DIR}/riscv.cmake
 			-DTARGET=${TARGET} \
 			-DPROJECT:STRING=${PROJECT} \
 			-DRISCV:STRING=${RISCV} \
-			-DINC_FOLDERS:STRING=${INC_FOLDERS} \
 			-DLINK_FOLDER:STRING=${LINK_FOLDER} \
 			-DLINKER:STRING=${LINKER} \
 			-DCOMPILER:STRING=${COMPILER} \
 			-DCOMPILER_PREFIX:STRING=${COMPILER_PREFIX} \
+			-DVERBOSE:STRING=${VERBOSE} \
 		    ../ 
 
 clean:
diff --git a/hw/vendor/eslepfl_cgra.lock.hjson b/hw/vendor/eslepfl_cgra.lock.hjson
index 3e767f56..b4a34e3f 100644
--- a/hw/vendor/eslepfl_cgra.lock.hjson
+++ b/hw/vendor/eslepfl_cgra.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/OpenEdgeCGRA.git
-    rev: 92cc0b97dd9f11b17b16a2d1cc19adc902bec3d1
+    rev: 618b45d2c5deb0ae3741b8dfdd472354ed073126
   }
 }
diff --git a/hw/vendor/eslepfl_cgra.vendor.hjson b/hw/vendor/eslepfl_cgra.vendor.hjson
index 1e05fb8b..7848d7e9 100644
--- a/hw/vendor/eslepfl_cgra.vendor.hjson
+++ b/hw/vendor/eslepfl_cgra.vendor.hjson
@@ -8,7 +8,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/OpenEdgeCGRA.git",
-    rev: "92cc0b97dd9f11b17b16a2d1cc19adc902bec3d1",
+    rev: "618b45d2c5deb0ae3741b8dfdd472354ed073126",
   },
 
   patch_dir: "patches/esl_epfl_cgra",
diff --git a/hw/vendor/eslepfl_x_heep.lock.hjson b/hw/vendor/eslepfl_x_heep.lock.hjson
index 213b5fa1..c432c29c 100644
--- a/hw/vendor/eslepfl_x_heep.lock.hjson
+++ b/hw/vendor/eslepfl_x_heep.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/x-heep.git
-    rev: 83f1563fd4894787167b27099006c8b1b042d3d1
+    rev: 2c6d7d8f581020d4961bd08dbd3956c90b676085
   }
 }
diff --git a/hw/vendor/eslepfl_x_heep.vendor.hjson b/hw/vendor/eslepfl_x_heep.vendor.hjson
index 0dcb0caa..32af0bc2 100644
--- a/hw/vendor/eslepfl_x_heep.vendor.hjson
+++ b/hw/vendor/eslepfl_x_heep.vendor.hjson
@@ -8,7 +8,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/x-heep.git",
-    rev: "83f1563fd4894787167b27099006c8b1b042d3d1",
+    rev: "2c6d7d8f581020d4961bd08dbd3956c90b676085",
   },
 
   patch_dir: "patches/esl_epfl_x_heep",

From 984e55bf1c26d6cd45c01bfc29c1fd5a589a4a90 Mon Sep 17 00:00:00 2001
From: jmiranda <mirandacalero.joseangel@gmail.com>
Date: Tue, 8 Oct 2024 15:02:28 +0200
Subject: [PATCH 27/27] revendorizing x-heep and cgra to fix ci issues

---
 hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
index beed1bcf..2e43dd14 100644
--- a/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
+++ b/hw/vendor/esl_epfl_x_heep/tb/ext_bus.sv
@@ -137,9 +137,8 @@ module ext_bus #(
   // show writes if requested
   always_ff @(posedge clk_i, negedge rst_ni) begin : verbose_writes
     if ($test$plusargs("verbose") != 0 && heep_core_data_req_i.req && heep_core_data_req_i.we)
-      $display(
-          "write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr, heep_core_data_req_i.wdata
-      );
+      $display("write addr=0x%08x: data=0x%08x", heep_core_data_req_i.addr,
+               heep_core_data_req_i.wdata);
   end
 `endif