Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

When instantiating, the signal can be listed in the form of wire #220

Open
haidoph opened this issue Jan 19, 2024 · 1 comment
Open

When instantiating, the signal can be listed in the form of wire #220

haidoph opened this issue Jan 19, 2024 · 1 comment

Comments

@haidoph
Copy link

haidoph commented Jan 19, 2024

hi ,
1, When instantiating, the signal can be listed in the form of wire
2, Add this feature to support instantiating multiple modules at the same time, similar to Verilog_mode

tks
@joecrop
Copy link
Collaborator

joecrop commented Jan 23, 2024

I don't think there's enough information to work with here. Can you be specific about what you are asking here? Maybe code examples?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@joecrop @haidoph