PowerFPGA.kicad_sch

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	(paper "A4")
	(title_block
		(title "PCIeDMA")
		(date "2024-01-01")
		(rev "1")
		(company "github.com/eggsampler")
	)
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	(text "Notes:\n------------\nInput voltages\nPCIe: 12V, 3.3V, 3.3V_aux\nUSB: 5V\n\nOutput voltages\nVCCO: 3.3V\nVCCINT: 1.0V\nVCCBRAM: Use VCCINT\nVCCAUX: 1.8V\nMGTAVCC: 1.0V\nMGTAVTT: 1.2V\n5V: Leds\n3.3V: FT601, CH347\n\nV_OUT=0.6 * R1/R2 + 0.6\n1.0=0.6*(100/150)+0.6\n1.2=0.6*(100/100)+0.6\n1.8=0.6*(200/100)+0.6\n\nGeneral concept is to power everything from the pcie 12v -> 5v buck if possible, \nphysical switch on that 5v line to turn fpga off"
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	(text "Notes:\n------------\nThis circuit powers VCCO after VCCAUX is up\n10kOhm * 10uF = a few 10s of ms until the npn conducts\nFerrite bead for filtering\nTODO: Consider filter specifically for pcie 3v3 ripple"
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	(text "Notes:\n------------\nDS181 Page 8 Power‐On/Off Power Supply Sequencing\nThe recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO\nto achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.\n\nThe recommended power-on sequence to achieve minimum current draw for the GTP transceivers\nis VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT.\nBoth VMGTAVCC and VCCINT can be ramped simultaneously.\n\nVCCINT (& VCCBRAM) & VMGTAVCC -> VMGTAVTT & VCCAUX -> VCCO"
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	(text "Notes:\n------------\nMin ramp time for all supplies on FPGA is 0.2ms (DS181 Table 7)\n\nEA3059 datasheet gives values 100k and 10n to 100n for power sequencing on EN pins\nand a minimum voltage for Enable Pin Input High Voltage of 2V\n\nAt 100kR at 22nF,\n2=5(1-e^(-t/((100*10^3)*(22*10^-9))))\ngives a time of approx 0.0011238, or 1.1238ms\n\nAt 100kR and 47nF\n2=5(1-e^(-t/((100*10^3)*(47*10^-9))))\ngives a time of approx 0.0024009, or 2.4009ms\n"
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