diff --git a/Makefile b/Makefile index 4cdbe930..4990d16b 100644 --- a/Makefile +++ b/Makefile @@ -80,6 +80,7 @@ CARAVEL_ROOT ?= $(shell pwd) # User project root UPRJ_ROOT ?= $(shell pwd) +PRECHECK_RESULT_ROOT ?= $(shell pwd)/mpw_precheck # MANAGEMENT AREA ROOT MGMT_AREA_ROOT ?= $(shell pwd)/mgmt_core_wrapper @@ -102,6 +103,8 @@ OPEN_PDKS_COMMIT ?= 12df12e2e74145e31c5a13de02f9a1e176b56e67 # = 1.0.303 PDK_MAGIC_COMMIT ?= 085131b090cb511d785baf52a10cf6df8a657d44 # = 8.3.294 +LVS_ROOT = $(CARAVEL_ROOT)/scripts/be_checks +export LVS_ROOT .DEFAULT_GOAL := ship # We need portable GDS_FILE pointers... @@ -151,6 +154,36 @@ __ship: @cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/$(PDK) MAGTYPE=mag magic -noc -dnull -rcfile ./.magicrc $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_ship.out ### @rm $(UPRJ_ROOT)/mag/mag2gds_caravel.tcl +# Check LVS setup +.PHONY: check-lvs-setup +check-lvs-setup: + @if [ -z "$(LVS_ROOT)" ]; then echo "Please set LVS_ROOT"; exit 1; fi + @if [ -z "$(PDK_ROOT)" ]; then echo "Please set PDK_ROOT"; exit 1; fi + @if [ -z "$(CARAVEL_ROOT)" ]; then echo "Please set CARAVEL_ROOT"; exit 1; fi + @if [ -z "$(MCW_ROOT)" ]; then echo "Please set MCW_ROOT"; exit 1; fi + @if [ -z "$(UPRJ_ROOT)" ]; then echo "Please set UPRJ_ROOT"; exit 1; fi + @if [ -z "$(TAPEOUT_ROOT)" ]; then echo "Please set TAPEOUT_ROOT"; exit 1; fi + @if [ -z "$(PRECHECK_RESULT_ROOT)" ]; then echo "Please set PRECHECK_RESULT_ROOT"; exit 1; fi + @echo -e "\n\ +LVS setup\n\ +LVS_ROOT: $(LVS_ROOT)\n\ +PDK_ROOT: $(PDK_ROOT)\n\ +CARAVEL_ROOT: $(CARAVEL_ROOT)\n\ +MCW_ROOT: $(MCW_ROOT)\n\ +UPRJ_ROOT: $(UPRJ_ROOT)\n\ +TAPEOUT_ROOT: $(TAPEOUT_ROOT)\n\ +PRECHECK_RESULT_ROOT: $(PRECHECK_RESULT_ROOT)\n\ +WORK_ROOT: $(WORK_ROOT)\n\ +" + +# Requires LVS_ROOT, PDK_ROOT, CARAVEL_ROOT, MCW_ROOT, UPRJ_ROOT, TAPEOUT_ROOT, PRECHECK_RESULT_ROOT +.PHONY: ship-lvs +ship-lvs: check-lvs-setup + mkdir -p $(UPRJ_ROOT)/signoff/build + $(eval LAYOUT := $(shell /foss/tools/sak/klayout/gdsAllcells.rb $(UPRJ_ROOT)/gds/caravel.gds | grep caravel_core)) + $(LVS_ROOT)/run_be_checks $(LVS_ROOT)/tech/$(PDK)/lvs_config.caravel_core-upw.json caravel_core $(LAYOUT) $(UPRJ_ROOT)/gds/caravel.gds > $(UPRJ_ROOT)/signoff/build/extra_be_check.log 2>&1 + $(LVS_ROOT)/check_gpio_and_id > $(UPRJ_ROOT)/signoff/build/gpio_check.log 2>&1 + truck: check-env uncompress uncompress-caravel ifeq ($(FOREGROUND),1) @echo "Running make truck in the foreground..." @@ -200,6 +233,14 @@ __truck: @cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/$(PDK) MAGTYPE=mag magic -noc -dnull -rcfile ./.magicrc $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_truck.out ### @rm $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl +# Requires LVS_ROOT, PDK_ROOT, CARAVEL_ROOT, MCW_ROOT, UPRJ_ROOT, TAPEOUT_ROOT, PRECHECK_RESULT_ROOT +.PHONY: truck-lvs +truck-lvs: check-lvs-setup + mkdir -p $(UPRJ_ROOT)/signoff/build + $(eval LAYOUT := $(shell /foss/tools/sak/klayout/gdsAllcells.rb $(UPRJ_ROOT)/gds/caravan.gds | grep caravan_core)) + $(LVS_ROOT)/run_be_checks $(LVS_ROOT)/tech/$(PDK)/lvs_config.caravan_core-upw.json caravan_core $(LAYOUT) $(UPRJ_ROOT)/gds/caravan.gds > $(UPRJ_ROOT)/signoff/build/extra_be_check.log 2>&1 + $(LVS_ROOT)/check_gpio_and_id > $(UPRJ_ROOT)/signoff/build/gpio_check.log 2>&1 + .PHONY: openframe openframe: check-env uncompress uncompress-caravel ifeq ($(FOREGROUND),1) diff --git a/scripts/be_checks/LICENSE b/scripts/be_checks/LICENSE new file mode 100644 index 00000000..261eeb9e --- /dev/null +++ b/scripts/be_checks/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/scripts/be_checks/README.md b/scripts/be_checks/README.md new file mode 100644 index 00000000..5db53272 --- /dev/null +++ b/scripts/be_checks/README.md @@ -0,0 +1,206 @@ +# extra_be_checks +Scripts to run additional back-end checks on gds files. + +INSTALLATION: +Requires: +- magic 3.8.413 https://github.com/RTimothyEdwards/magic.git +- netgen 1.5.255 https://github.com/RTimothyEdwards/netgen.git +- cvc 1.1.4 https://github.com/d-m-bailey/cvc.git + +git clone -b precheck https://github.com/d-m-bailey/extra_be_checks.git +export LVS_ROOT=$PWD/extra_be_checks + +In your `caravel_user_project` or `caravel_user_project_analog` directory, +create an LVS configuration file based on `extra_be_checks/tech/$PDK/lvs_config..json`. +`mpw_precheck` expects this file to be in `lvs//lvs_config.json`. + +Environment variables. +These checks will use the following environment variables' +`LVS_ROOT`: path to the extra_be_checks directory. No default. Must be set. +`WORK_ROOT`: path to temporary work directory. Defaults to $PWD/work/$top_source +`LOG_ROOT`: path to runtime logs. Defaults to $PWD/logs/$top_source +`SIGNOFF_ROOT`: path to results. Defaults to $PWD/signoff/$top_source + + +``` +$LVS_ROOT/run_be_checks [--noextract] [--nooeb] lvs//lvs_config.json +``` +This command will run the following checks. +``` +run_hier_check: Checks layout hierarchy against verilog hierarchy +run_scheck: Soft connection check +run_full_lvs: Device level LVS +run_cvc: ERC checks +run_oeb_check: Check oeb connections +``` + +1. Check design hierarchies. A fast check for digital designs to ensure that design hierarchies match. + + Usage: `run_hier_check top_source verilog_files top_layout layout_file [primitive_prefix [layout_prefix]]` + + Requires: + - klayout: + + Arguments: + - `top_source`: Top cell name from verilog + - `verilog_files`: Verilog files (only cells in the listed verilog files will be checked) + - `top_layout`: Top cell name in the layout + - `layout_file`: gds/oasis/text file (gzip compression allowed). + - `primitive_prefix`: If given, prefix is removed from both source and layout before comparison. + - `layout_prefix`: If given, prefix is removed from layout cell names before comparison. + + Input: + - `verilog_files`: List of referenced verilog files. Should have child modules listed before parents. + + Output: + - `$WORK_ROOT/verilog.hier`: The netlist hierarchy. + - `$WORK_ROOT/layout.txt.gz`: If input is gds/oas, the layout hierarchy converted to text. + - `$WORK_ROOT/layout.hier`: The layout hierarchy. + - `$SIGNOFF_ROOT/hier.csv`: Comparison results. + + Algorithm: + - Convert gds/oasis to gds text file. + - Extract netlist hierarchy. + - Extract layout hierarchy. + - Compare. + +2. Soft connection check: find high resistance connections (i.e. soft connections) through n/pwell. + + Usage: + `run_softcheck [--noextract] [ [ []]]` + + Requires: + - magic 3.8.413 + - netgen 1.5.255 + + Arguments: + - `--noextract`: Use previous extraction results. + - `config_file`: Configuration file. For details, see sample in repo. + - `top_layout`: Top layout name. Overrides config_file setting. + - `gds_file`: gds file (gzip compression allowed). Overrides config_file setting. + + References: (created from config_file) + - `$WORK_ROOT/flatglob`: cells to be flattened before extraction. + - `$WORK_ROOT/abstract.glob`: cells to be abstracted during extraction. + + Output: + - `$WORK_ROOT/ext/*`: Extraction results with well connectivity. + - `$LOG_ROOT/ext.log`: Well connectivity extraction log. + - `$WORK_ROOT/nowell.ext/*`: Extraction results without well connectivity. + - `$LOG_ROOT/nowell.ext.log`: No well connectivity extraction log. + - `$LOG_ROOT/soft.log`: Soft connection check LVS log. + - `$SIGNOFF_ROOT/soft.report`: Comparison results. + + Algorithm: + - Create 2 versions of the extracted netlist. + - Version 1 extracts well connectivity. + - Remove well connections and disconnected signals. + - Version 2 does not extract well connectivity. + - Remove disconnected signals. + - Compare with LVS. + + Analysis: + - Any discrepancies should be the result of well/substrate taps not connected to the correct power net. + - Use the `$SIGNOFF_ROOT/soft.report` file to find problem nets. + - Use the problem nets to find a connected device in the `$WORK_ROOT/nowell.ext/.gds.nowell.spice` file. + - Use the corresponding `$WORK_ROOT/nowell.ext/*.ext` file to find the coordinates of error devices. (divide by 200 to get coordinates in um). + +3. Full device level LVS + + Usage: `run_full_lvs [--noextract] [ [ [ [layout_file]]]] + + Requires: + - magic 3.8.413 + - netgen 1.5.255 + + Arguments: + - `--noextract`: Use previous extraction results. + - `config_file`: Configuration file. For details, see sample in repo. + - `top_source`: Top source name. Overrides config_file setting. + - `top_layout`: Top layout name. Overrides config_file setting. + - `layout_file`: Top layout file name. Overrides config_file setting. + + References: (created from config_file) + - `$WORK_ROOT/flatglob`: cells to be flattened before extraction. + - `$WORK_ROOT/abstract.glob`: cells to be abstracted during extraction. + - `$WORK_ROOT/flatten.glob`: cells to be flattened during LVS. + - `$WORK_ROOT/noflatten.glob`: cells not to be flattened during LVS. + - `$WORK_ROOT/ignore.glob`: cells to be ignored during extraction. + - `$WORK_ROOT/spice_files`: list of spice files in hierachical order (lowest level first). + - `$WORK_ROOT/verilog_files`: list of verilog files in hierachical order (lowest level first). + + Output: + - `$WORK_ROOT/ext/*`: Extraction results with well connectivity. + - `$LOG_ROOT/ext.log`: Well connectivity extraction log. + - `$LOG_ROOT/lvs.log`: LVS comparison log. + - `$SIGNOFF_ROOT/lvs.report`: Comparison results. + + Hints: + - Rerunning with --noextract is faster because previous extraction result will be used. + - Add cells to the `EXTRACT_FLATGLOB` to flatten before extraction. + - Cells in `EXTRACT_ABSTRACT` will be extracted (top level?), but netlisted as black-boxes. + - `LVS_FLATTEN` is a list of cell names to be flattened during LVS. + Flattening cells with unmatched ports may resolve proxy port errors. + - netgen normally flattens unmatched cells which can lead to confusing results at higher levels. + To avoid this, add cells to `LVS_NOFLATTEN`. + - Add cells to `LVS_IGNORE` to skip LVS checks. + +4. CVC-RV. Circuit Validity Check - Reliability Verification - voltage aware ERC. + Voltage aware ERC tool to detect current leaks and electrical overstress errors. + + Usage: `run_cvc [--noextract] [lvs_config_file [top_layout [layout_file]]]]" + + Requires: + - cvc_rv 1.1.4 + + Arguments: + - `--noextract`: Use previous extraction results. + - `lvs_config_file`: Configuration file. For details, see sample in repo. + - `top_layout`: Top layout name. Overrides config_file setting. + - `layout_file`: gds file (gzip compression allowed). Overrides config_file setting. + + Input: + - `$WORK_ROOT/ext/.gds.spice`: Extracted spice file. + - `$WORK_ROOT/cvc.power.`: Power settings. + - `cvc.$PDK.models`: Model settings. + + Output: + - `$WORK_ROOT/ext/.cdl.gz`: CDL file converted from extracted spice file. + - `$WORK_ROOT/cvc.error.gz`: Detailed errors results. + - `$LOG_ROOT/cvc.log`: Log file with error summary. + + Analysis; + - Works well with digital designs. Analog results can be obscure. + - If the log file shows errors, look for details in the error file. + - Error device locations can be found in the respective `$WORK_ROOT/ext/*.ext` files. (coordinates should be divided by 200). + +5. OEB check. Check for user oeb signal output to gpio cells. + The following conditions are errors. + - gpio with both digital (io_in/io_out) and analog (analog_io/gpio_analog) connections + - gpio with analog (analog_io/gpio_analog) and oeb not high + - gpio with only input (io_in) but oeb not high + - gpio with output (io_out) but oeb never low + The following condition is a warning. + - gpio with both input (io_in) and output (io_out) and oeb always low + + Usage: `run_oeb_check [--noextract] [lvs_config_file [top_layout [layout_file]]]]" + + Requires: + - cvc_rv 1.1.4 + + Arguments: + - `--noextract`: Use previous extraction results. + - `lvs_config_file`: Configuration file. For details, see sample in repo. + - `top_layout`: Top layout name. Overrides config_file setting. + - `layout_file`: gds file (gzip compression allowed). Overrides config_file setting. + + Input: + - `$WORK_ROOT/ext/.gds.spice`: Extracted spice file. + - `$WORK_ROOT/cvc.power.`: Power settings. + - `cvc.$PDK.models`: Model settings. + + Output: + - `$WORK_ROOT/ext/.cdl.gz`: CDL file converted from extracted spice file. + - `$WORK_ROOT/cvc.oeb.error.gz`: Detailed errors results. + - `$LOG_ROOT/cvc.oeb.log`: Log file with error summary. + - `$SIGNOFF_ROOT/cvc.oeb.report`: List of each gpio, connection counts, and errors diff --git a/scripts/be_checks/check_gpio_and_id b/scripts/be_checks/check_gpio_and_id new file mode 100755 index 00000000..830a6369 --- /dev/null +++ b/scripts/be_checks/check_gpio_and_id @@ -0,0 +1,198 @@ +#! /usr/bin/env bash + +# check that default gpio configurations and id match expected values + +# After LVS at the caravel_core/caravan_core level, run verilog on the gate level netlist +# to get the actual defaults for each gpio pad and the user id. +# Compare these results to the original user specification. +# Returns a non-zero return code is there is a mismatch or error. + +# Copyright 2024 D. Mitch Bailey efabless dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Return codes +# 1: Missing environment variables: *_ROOT or PDK +# 2: Missing files +# 3: Mismatch between expected and actual + +# Use cases +# Print only mismatches: check_gpio_and_id +# Print matches and mismatches: check_gpio_and_id --verbose + +usage="usage: check_gpio_and_id [--verbose]" +if [[ $# -gt 1 ]]; then + echo $usage + exit 1 +fi +if [[ $# -eq 1 && $1 != "--verbose" ]]; then + echo $usage + exit 1 +fi + +# Check for *_ROOT directories +if [[ -z "$LVS_ROOT" || -z "$PDK_ROOT" || -z "$CARAVEL_ROOT" || -z "$MCW_ROOT" || -z "$PRECHECK_RESULT_ROOT" || -z "$TAPEOUT_ROOT" ]]; then + echo "Missing at least one of LVS_ROOT, PDK_ROOT, CARAVEL_ROOT, MCW_ROOT, PRECHECK_RESULT_ROOT, TAPEOUT_ROOT." + exit 1 +fi + +# Check for PDK +if [[ -z "$PDK" ]]; then + echo "PDK not set." + exit 1 +fi + +# 1. convert caravel_core/caravan_core verilog +if [[ -f $TAPEOUT_ROOT/outputs/verilog/gl/caravel_core.v ]]; then + if [[ ! -f $LVS_ROOT/tech/$PDK/caravel_gpio_test.v ]]; then + echo "Could not find caravel_gpio_test.v in \$LVS_ROOT/tech/\$PDK($LVS_ROOT/tech/$PDK)" + exit 2 + fi + if [[ ! -f $LVS_ROOT/tech/$PDK/caravel_core.v.sed ]]; then + echo "Could not find caravel_core.v.sed in \$LVS_ROOT/tech/\$PDK($LVS_ROOT/tech/$PDK)" + exit 2 + fi + echo "WORK_ROOT : ${WORK_ROOT:=$(pwd)/work/caravel_core}" + mkdir -p $WORK_ROOT + sed -f $LVS_ROOT/tech/$PDK/caravel_core.v.sed $TAPEOUT_ROOT/outputs/verilog/gl/caravel_core.v > $WORK_ROOT/caravel_core.v + cat > $WORK_ROOT/verilog.includes <<-EOF + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/verilog/primitives.v + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v + $CARAVEL_ROOT/verilog/rtl/defines.v + $CARAVEL_ROOT/verilog/gl/caravel_clocking.v + $CARAVEL_ROOT/verilog/gl/caravel_logo.v + $CARAVEL_ROOT/verilog/gl/caravel_motto.v + $CARAVEL_ROOT/verilog/gl/constant_block.v + $CARAVEL_ROOT/verilog/gl/copyright_block.v + $CARAVEL_ROOT/verilog/gl/empty_macro.v + $CARAVEL_ROOT/verilog/gl/gpio_defaults_block.v + $CARAVEL_ROOT/verilog/gl/gpio_logic_high.v + $CARAVEL_ROOT/verilog/gl/housekeeping.v + $CARAVEL_ROOT/verilog/gl/manual_power_connections.v + $CARAVEL_ROOT/verilog/gl/mgmt_protect.v + $CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v + $CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v + $CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v + $CARAVEL_ROOT/verilog/gl/mprj_logic_high.v + $CARAVEL_ROOT/verilog/gl/open_source.v + $CARAVEL_ROOT/verilog/gl/spare_logic_block.v + $CARAVEL_ROOT/verilog/gl/user_id_textblock.v + $CARAVEL_ROOT/verilog/gl/xres_buf.v + $CARAVEL_ROOT/verilog/rtl/simple_por.v + $MCW_ROOT/verilog/gl/RAM128.v + $LVS_ROOT/tech/$PDK/user_project_wrapper_dummy.v + $LVS_ROOT/tech/$PDK/caravel_gpio_test.v + $WORK_ROOT/caravel_core.v +EOF + +elif [[ -f $TAPEOUT_ROOT/outputs/verilog/gl/caravan_core.v ]]; then + if [[ ! -f $LVS_ROOT/tech/$PDK/caravan_gpio_test.v ]]; then + echo "Could not find caravan_gpio_test.v in \$LVS_ROOT/tech/\$PDK($LVS_ROOT/tech/$PDK)" + exit 2 + fi + if [[ ! -f $LVS_ROOT/tech/$PDK/caravan_core.v.sed ]]; then + echo "Could not find caravan_core.v.sed in \$LVS_ROOT/tech/\$PDK($LVS_ROOT/tech/$PDK)" + exit 2 + fi + echo "WORK_ROOT : ${WORK_ROOT:=$(pwd)/work/caravan_core}" + mkdir -p $WORK_ROOT + sed -f $LVS_ROOT/tech/$PDK/caravan_core.v.sed $TAPEOUT_ROOT/outputs/verilog/gl/caravan_core.v > $WORK_ROOT/caravan_core.v + cat > $WORK_ROOT/verilog.includes <<-EOF + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/verilog/primitives.v + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v + $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v + $CARAVEL_ROOT/verilog/rtl/defines.v + $CARAVEL_ROOT/verilog/gl/caravan_signal_routing.v + $CARAVEL_ROOT/verilog/gl/caravel_clocking.v + $CARAVEL_ROOT/verilog/gl/caravel_logo.v + $CARAVEL_ROOT/verilog/gl/caravel_motto.v + $CARAVEL_ROOT/verilog/gl/constant_block.v + $CARAVEL_ROOT/verilog/gl/copyright_block.v + $CARAVEL_ROOT/verilog/gl/empty_macro.v + $CARAVEL_ROOT/verilog/gl/empty_macro_1.v + $CARAVEL_ROOT/verilog/gl/gpio_defaults_block.v + $CARAVEL_ROOT/verilog/gl/gpio_logic_high.v + $CARAVEL_ROOT/verilog/gl/housekeeping_alt.v + $CARAVEL_ROOT/verilog/gl/manual_power_connections.v + $CARAVEL_ROOT/verilog/gl/mgmt_protect.v + $CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v + $CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v + $CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v + $CARAVEL_ROOT/verilog/gl/mprj_logic_high.v + $CARAVEL_ROOT/verilog/gl/open_source.v + $CARAVEL_ROOT/verilog/gl/spare_logic_block.v + $CARAVEL_ROOT/verilog/gl/user_id_textblock.v + $CARAVEL_ROOT/verilog/gl/xres_buf.v + $CARAVEL_ROOT/verilog/rtl/simple_por.v + $MCW_ROOT/verilog/gl/RAM128.v + $LVS_ROOT/tech/$PDK/user_analog_project_wrapper_dummy.v + $LVS_ROOT/tech/$PDK/caravan_gpio_test.v + $WORK_ROOT/caravan_core.v +EOF + +else + echo "Could not find caravel_core.v or caravan_core.v in $TAPEOUT_ROOT/outputs/verilog" + exit 2 +fi + +echo "LOG_ROOT : ${LOG_ROOT:=$WORK_ROOT}" +echo "SIGNOFF_ROOT: ${SIGNOFF_ROOT:=$WORK_ROOT}" + +echo "Compiling verilog..." +iverilog \ + -o $WORK_ROOT/gpio_test \ + -s gpio_test \ + -gno-specify \ + -c $WORK_ROOT/verilog.includes \ + -DUSE_POWER_PINS \ + $TAPEOUT_ROOT/outputs/verilog/gl/gpio_defaults_block*.v \ + $TAPEOUT_ROOT/outputs/verilog/gl/user_id_programming.v 2>&1 | + grep -v ': warning:' + +# 2. Create expected result +if [[ ! -f $LVS_ROOT/tech/$PDK/expected_gpio ]]; then + echo "Could not find expected_gpio in \$LVS_ROOT/tech/\$PDK($LVS_ROOT/tech/$PDK)" + exit 2 +fi +cp $LVS_ROOT/tech/$PDK/expected_gpio $WORK_ROOT/expected +if [[ ! -f $PRECHECK_RESULT_ROOT/outputs/reports/gpio_defines.report ]]; then + echo "Could not find precheck defaults file $PRECHECK_RESULT_ROOT/outputs/reports/gpio_defines.report" + exit 2 +fi +sed "s/[0-9]*'h//" $PRECHECK_RESULT_ROOT/outputs/reports/gpio_defines.report >> $WORK_ROOT/expected +if [[ ! -f $TAPEOUT_ROOT/logs/set_user_id.log ]]; then + echo "Could not find set user id log $TAPEOUT_ROOT/logs/set_user_id.log" + exit 2 +fi +grep 'Setting Project Chip ID' $TAPEOUT_ROOT/logs/set_user_id.log >> $WORK_ROOT/expected + +# 3. Run verilog +echo "Running verilog..." +vvp -n -l$WORK_ROOT/actual $WORK_ROOT/gpio_test > /dev/null + +# 4. Compare +diff -w -y --suppress-common-lines $WORK_ROOT/expected $WORK_ROOT/actual > $WORK_ROOT/gpio_check.log +if [[ $1 == "--verbose" ]]; then + diff -w -y $WORK_ROOT/expected $WORK_ROOT/actual +fi + +if [[ $( cat $WORK_ROOT/gpio_check.log | wc -l ) -ne 1 ]]; then + echo " " + cat $WORK_ROOT/gpio_check.log + exit 3 +else + exit 0 +fi diff --git a/scripts/be_checks/generate_subcut.py b/scripts/be_checks/generate_subcut.py new file mode 100755 index 00000000..f158aaa5 --- /dev/null +++ b/scripts/be_checks/generate_subcut.py @@ -0,0 +1,174 @@ +#!/usr/bin/env python3 +# SPDX-FileCopyrightText: 2024 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# +# generate_subcut.py --- +# +# Run the subcut generation on a layout top level. +# + +import sys +import os +import re +import glob +import subprocess +import multiprocessing + +def Usage(): + print("Usage:") + print("generate_subcut.py [-keep] [-test]") + print("") + print("where:") + print(" is the target cell name.") + print(" is the input gds filename.") + print(" is the output gds filename.") + print("") + print(" If '-keep' is specified, then keep the generation script.") + print(" If '-test' is specified, then create but do not run the generation script.") + + return 0 + + +def Create_Subcut_Script(script_filename, # this file will be created + gds_filename, # input gds file + cellname, # + subcut_cellname, # cellname of new subcut only cell + subcut_filename): # filename of gds with new subcut cell + + subcut_script_template = """ +#!/bin/env wish +drc off +tech unlock * +snap internal +cif istyle subcutin +set starttime [orig_clock format [orig_clock seconds] -format "%D %T"] +puts stdout "Started: $starttime" + +# Read the cellname from GDS +gds rescale false +gds read {gds_filename} +load {cellname} +select top cell +# Save the boundary +set cellboundary [property FIXED_BBOX] +expand + +# Flatten into a cell with a new name +puts stdout "Flattening layout ..." +flush stdout +update idletasks +flatten -dobox -nolabels {subcut_cellname} +load {subcut_cellname} +# Reset the boundary after flattening +property FIXED_BBOX $cellboundary +# Remove any GDS_FILE reference (there should not be any?) +property GDS_FILE "" +select top cell +flush stdout +update idletasks +cif ostyle subcutout + +gds write {subcut_filename} +set endtime [orig_clock format [orig_clock seconds] -format "%D %T"] +puts stdout "Ended: $endtime" +quit -noprompt +""" + with open(script_filename, 'w') as script_file: + print(subcut_script_template.format(gds_filename=gds_filename, + cellname=cellname, + subcut_cellname=subcut_cellname, + subcut_filename=subcut_filename), + file=script_file) + + +if __name__ == '__main__': + + optionlist = [] + arguments = [] + + debugmode = False + keepmode = False + testmode = False + + for option in sys.argv[1:]: + if option.find('-', 0) == 0: + optionlist.append(option) + else: + arguments.append(option) + + if len(arguments) < 3: + print("Wrong number of arguments given to generate_subcut.py.") + Usage() + sys.exit(1) + + cellname = arguments[0] + gds_filename = arguments[1] + subcut_filename = arguments[2] + + if '-debug' in optionlist: + debugmode = True + if '-keep' in optionlist: + keepmode = True + if '-test' in optionlist: + testmode = True + + lvs_root = os.getenv("LVS_ROOT") + pdk = os.getenv("PDK") + rcfilename = lvs_root + '/tech/' + pdk + '/subcut.magicrc' + + if not os.path.isfile(rcfilename): + print("Cannot find subcut.magicrc. Should be in $LVS_ROOT/tech/$PDK") + sys.exit(2) + + if not os.path.isfile(gds_filename): + print("Could not locate GDS file " + gds_filename) + sys.exit(2) + + script_filename = 'generate_' + cellname + '_subcut.tcl' + Create_Subcut_Script(script_filename=script_filename, + gds_filename=gds_filename, + cellname=cellname, + subcut_cellname=cellname+'_subcut', + subcut_filename=subcut_filename) + + myenv = os.environ.copy() + myenv['MAGTYPE'] = 'mag' + + if not testmode: + # Diagnostic + print('This script will generate ' + subcut_filename) + mproc = subprocess.run(['magic', '-dnull', '-noconsole', '-rcfile', rcfilename, script_filename], + stdin = subprocess.DEVNULL, + stdout = subprocess.PIPE, + stderr = subprocess.PIPE, + env = myenv, + universal_newlines = True) + if mproc.stdout: + for line in mproc.stdout.splitlines(): + print(line) + if mproc.stderr: + print('Error message output from magic:') + for line in mproc.stderr.splitlines(): + print(line) + if mproc.returncode != 0: + print('ERROR: Magic exited with status ' + str(mproc.returncode)) + + if not keepmode: + # Remove fill generation script + os.remove(script_filename) + + print('Done!') + exit(0) diff --git a/scripts/be_checks/lvs_config.md b/scripts/be_checks/lvs_config.md new file mode 100644 index 00000000..b664e659 --- /dev/null +++ b/scripts/be_checks/lvs_config.md @@ -0,0 +1,42 @@ +# lvs_config.json + +The `lvs_config.json` files are a possibly hierarchical set of files to set parameteters for device level LVS + +Required variables: +- **TOP_SOURCE** : Top source cell name. +- **TOP_LAYOUT** : Top layout cell name. +- **LAYOUT_FILE** : Layout gds data file. +- **LVS_SPICE_FILES_TO_FIX** : A list of spice files that work with mag extraction but need to be modified for gds extraction. +- **LVS_SPICE_FILES** : A list of spice files. +- **LVS_VERILOG_FILES** : A list of verilog files. Note: files with child modules should be listed before parent modules. Not needed for purely analog designs. + +Files must be defined as a absolute path beginning with a shell variable such as `$PDK_ROOT` or `$UPRJ_ROOT`. +File globbing is permitted. + +Optional variable lists: +Hierarchical config files: +- **INCLUDE_CONFIGS** : List of configuration files to read recursively. + +Extraction related. `*` may be used as a wild card character. +- **EXTRACT_FLATGLOB** : List of cell names to flatten before extraction. + Cells without text tend to work better if flattened. + Note: it is necessary to flatten all sub cells of any cells listed. +- **EXTRACT_ABSTRACT** : List of cells to extract as abstract devices. + Normally, cells that do not contain any devices will be flattened during netlisting. + Using this variable can prevent unwanted flattening of empty cells. + This has no effect of cells that are flattened because of a small number of layers. + Internal connectivity is maintained (at least at the top level). + +LVS related. `*` may be used as a wild card character. +- **LVS_FLATTEN** : List of cells to flatten before comparing, + Sometimes matching topologies with mismatched pins cause errors at a higher level. + Flattening these cells can yield a match. +- **LVS_NOFLATTEN** : List of cells not to be flattened in case of a mismatch. + Lower level errors can propagate to the top of the chip resulting in long run times. + Specify cells here to prevent flattening. May still cause higher level problems if there are pin mismatches. +- **LVS_IGNORE** : List of cells to ignore during LVS. + Cells ignored result in LVS ending with a warning. + Generally, should only be used when debugging and not on the final netlist. + Ignoring cells results in a non-zero return code. + +Simple shell variable substitution will be attempted on all values. Missing files and undefined variables result in fatal errors. diff --git a/scripts/be_checks/run_be_checks b/scripts/be_checks/run_be_checks new file mode 100755 index 00000000..2f8bb400 --- /dev/null +++ b/scripts/be_checks/run_be_checks @@ -0,0 +1,194 @@ +#! /bin/bash +# run_be_checks: Runs scheck, full_lvs and for digital designs cvc-rv. + +# Copyright 2022 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Overview: +# 1. Run hierarchy check +# 2. Run soft connection check +# 3. Run full lvs +# 4. Run cvc for digital designs +# +# All variable specified in LVS configuration file + +# Usage +# run_be_checks [--nooeb] LVS_config_file [top_netlist [top_layout [layout_file]]] : extract, then check +# run_be_checks --noextract [--nooeb] LVS_config_file [top_netlist [top_layout [layout_file]]] : use previous extraction results to compare + +export EXTRACT_LAYOUT=yes +SKIP_OEB=no +while [[ "$1" == "--"* ]]; do + if [[ "$1" == "--noextract" ]]; then + export EXTRACT_LAYOUT=no + shift + elif [[ "$1" == "--nooeb" ]]; then + SKIP_OEB=yes + shift + else + echo "ERROR: unrecognized option $1" + exit 2 + fi +done + +if [[ $# -gt 4 ]]; then + echo $0 $* + echo "usage: run_be_checks [--noextract] [lvs_config_file [netlist_top [layout_top [layout_file]]]]" + exit 1 +fi + +# Check for LVS_ROOT +if [[ -z "$LVS_ROOT" ]]; then + echo "LVS_ROOT not set." + exit 1 +fi + +CONFIG_FILE=$1 +DESIGN_NAME=${2:+"-d $2"} + +if [[ $# -ne 0 ]]; then # if config file not specified, skip and use current environment + source <($LVS_ROOT/set_lvs_env.py -c $CONFIG_FILE $DESIGN_NAME) +fi +if [[ ! -v EXTRACT_FLATGLOB ]]; then + echo "ERROR: LVS environment problem." + exit 1 +fi + +# Command line values override config file values +export TOP_SOURCE=${2:-$TOP_SOURCE} +export TOP_LAYOUT=${3:-$TOP_LAYOUT} +export LAYOUT_FILE=${4:-$LAYOUT_FILE} + +echo " +TOP SOURCE: $TOP_SOURCE" +echo "SOURCE FILE(S): $(echo $LVS_SPICE_FILES_TO_FIX $LVS_SPICE_FILES $LVS_VERILOG_FILES | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "TOP LAYOUT: $TOP_LAYOUT" +echo "LAYOUT FILE: $LAYOUT_FILE" +echo "EXTRACT_FLATGLOB: $(echo $EXTRACT_FLATGLOB | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "EXTRACT_ABSTRACT: $(echo $EXTRACT_ABSTRACT | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "LVS_FLATTEN: $(echo $LVS_FLATTEN | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "LVS_NOFLATTEN: $(echo $LVS_NOFLATTEN | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "LVS_IGNORE: $(echo $LVS_IGNORE | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" + +if [[ ! -f $LAYOUT_FILE ]]; then + echo " +ERROR: missing layout file $LAYOUT_FILE" + exit 2 +fi + +: "${WORK_ROOT:=$(pwd)/$TOP_SOURCE}" +: "${LOG_ROOT:=$WORK_ROOT}" +: "${SIGNOFF_ROOT:=$WORK_ROOT}" +export LOG_ROOT SIGNOFF_ROOT WORK_ROOT + +mkdir -p $LOG_ROOT $SIGNOFF_ROOT $WORK_ROOT +rm -f $LOG_ROOT/{soft,lvs,cvc}.log $SIGNOFF_ROOT/{soft,lvs,cvc}.report $SIGNOFF_ROOT/hier.csv +if [[ $SKIP_OEB == no ]]; then + rm -f $LOG_ROOT/cvc.oeb.log $SIGNOFF_ROOT/cvc.oeb.report +fi +if [[ $EXTRACT_LAYOUT == yes ]]; then + rm -f $LOG_ROOT/{ext,nowell.ext}.log +fi + +start_time=$SECONDS + +$LVS_ROOT/run_hier_check $TOP_SOURCE "$(echo $LVS_VERILOG_FILES | sed 's/#[^ ]*//g')" $TOP_LAYOUT $LAYOUT_FILE "${PDK%?}_([^/_]*_)*_" +hier_status=$? + +if [[ $EXTRACT_LAYOUT == yes ]]; then + $LVS_ROOT/run_scheck + scheck_status=$? +else + $LVS_ROOT/run_scheck --noextract + scheck_status=$? +fi + +$LVS_ROOT/run_full_lvs --noextract +lvs_status=$? + +if [[ -f $LVS_ROOT/tech/$PDK/cvc.power.$TOP_SOURCE || -f ${CONFIG_FILE%/*}/cvc.power.$TOP_SOURCE ]]; then + if [[ -f ${CONFIG_FILE%/*}/cvc.power.$TOP_SOURCE ]]; then + cp ${CONFIG_FILE%/*}/cvc.power.$TOP_SOURCE $WORK_ROOT/cvc.power.$TOP_LAYOUT + fi + $LVS_ROOT/run_cvc --noextract + cvc_status=$? +fi + +if [[ $TOP_SOURCE == *user_*project_wrapper && $SKIP_OEB == no ]]; then + $LVS_ROOT/run_oeb_check --noextract + oeb_status=$? +fi + +echo " +Soft check result:" +tail -n 20 $LOG_ROOT/soft.log | awk '/Final result/,/Logging/' | grep -v ^Logging +if [[ $scheck_status -ne 0 ]]; then + echo "Soft check problem: check the following files +$LOG_ROOT/ext.log +$LOG_ROOT/nowell.ext.log +$LOG_ROOT/soft.log +$SIGNOFF_ROOT/soft.report" +fi + +echo " +LVS result:" +tail -n 20 $LOG_ROOT/lvs.log | awk '/Final result/,/^END/' | grep -v ^Logging | grep -v "^END" +if [[ $lvs_status -ne 0 ]]; then + echo "LVS problem: check the following files +$LOG_ROOT/ext.log +$LOG_ROOT/lvs.log +$SIGNOFF_ROOT/lvs.report" +fi + +if [[ -f $LOG_ROOT/cvc.log ]]; then + echo " +CVC result:" + grep 'CVC: Total:' $LOG_ROOT/cvc.log +fi + +if [[ $TOP_SOURCE == *user_*project_wrapper && $SKIP_OEB == no ]]; then + oeb_errors=$(grep -c ERROR $SIGNOFF_ROOT/cvc.oeb.report) + oeb_warnings=$(grep -c Warning $SIGNOFF_ROOT/cvc.oeb.report) + echo " +OEB check result: ERRORS: $oeb_errors Warnings: $oeb_warnings" +fi + +runtime=$((SECONDS - start_time)) +hours=$((runtime / 3600)) +minutes=$(((runtime % 3600) / 60)) +seconds=$(((runtime % 3600) % 60)) +printf "\nRuntime: %d:%02d:%02d (hh:mm:ss)\n" $hours $minutes $seconds + +# If any of the checks had an error, set return code. +# NOTE: ignores hierarchy check errors +# NOTE: cvc_status and oeb_status ignored if not run +if [[ $scheck_status -eq 0 && $lvs_status -eq 0 && ${cvc_status:=0} -eq 0 && ${oeb_status:=0} -eq 0 ]]; then + echo " +No errors detected" + exit 0 + +elif [[ $scheck_status -eq 0 && $lvs_status -eq 0 && ${cvc_status:=0} -eq 4 && ${oeb_status:=0} -eq 0 ]]; then + echo " +WARNING: possible errors CVC $cvc_status" + exit 4 + +elif [[ $SKIP_OEB == no ]]; then + echo " +WARNING: possible errors SOFT $scheck_status LVS $lvs_status CVC $cvc_status OEB $oeb_status" + exit 1 +else + echo " +WARNING: possible errors SOFT $scheck_status LVS $lvs_status CVC $cvc_status" + exit 1 +fi diff --git a/scripts/be_checks/run_cvc b/scripts/be_checks/run_cvc new file mode 100755 index 00000000..3f23720f --- /dev/null +++ b/scripts/be_checks/run_cvc @@ -0,0 +1,146 @@ +#! /usr/bin/env bash + +# Script to run a simplifed setup for CVC + +# Uses lvs_config to optionally extract a spice netlist +# Requires a netlist $WORK_ROOT/ext/$DESIGN_NAME.gds.spice +# Converts this netlist to $WORK_ROOT/ext/$DESIGN_NAME.cdl.gz + +# Copyright 2023 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Set LVS parameters in lvs_config file or use environment + +# Use cases +# run_cvc [--noextract] [lvs_config_file [top_layout [layout_file]]] + +if [[ $1 == "--noextract" ]]; then + export EXTRACT_LAYOUT=no + shift +else + export EXTRACT_LAYOUT=yes +fi + +usage="usage: run_cvc [--noextract] [lvs_config_file [top_layout [layout_file]]]]" +if [[ $# -gt 3 ]]; then + echo $usage + exit 1 +fi + +# Check for LVS_ROOT +if [[ -z "$LVS_ROOT" ]]; then + echo "LVS_ROOT not set." + exit 1 +fi + +CONFIG_FILE=$1 +DESIGN_NAME=${2:+"-d $2"} + +if [[ $# -ne 0 ]]; then # if config file not specified, skip and use current environment + source <($LVS_ROOT/set_lvs_env.py -c $CONFIG_FILE $DESIGN_NAME) +fi +if [[ ! -v EXTRACT_FLATGLOB ]]; then + echo "ERROR: LVS environment problem." + exit 1 +fi +export TOP_LAYOUT=${2:-$TOP_LAYOUT} +export LAYOUT_FILE=${3:-$LAYOUT_FILE} + +export DESIGN_NAME=$TOP_LAYOUT + +echo "DESIGN NAME: $DESIGN_NAME" + +echo "WORK_ROOT : ${WORK_ROOT:=$(pwd)/$DESIGN_NAME}" +echo "LOG_ROOT : ${LOG_ROOT:=$(pwd)/$DESIGN_NAME}" +echo "SIGNOFF_ROOT: ${SIGNOFF_ROOT:=$(pwd)/$DESIGN_NAME}" +export LOG_ROOT SIGNOFF_ROOT WORK_ROOT + +mkdir -p $LOG_ROOT $SIGNOFF_ROOT $WORK_ROOT + +rm -f $LOG_ROOT/cvc.log $SIGNOFF_ROOT/cvc.error.gz +rm -f $WORK_ROOT/cvc.log $WORK_ROOT/cvc.error.gz + +export RESULTS_DIR=$WORK_ROOT/ext +if [[ $EXTRACT_LAYOUT == yes ]]; then + env RUN_DIR=$RESULTS_DIR CIFIN_STYLE= EXTRACT_STYLE= LOG_FILE=ext.log $LVS_ROOT/run_extract + ext_status=$? +fi + +echo " " +echo "Running CVC..." + +# Create cdl file from extracted spice file if it doesn't exist +if [[ ! -f $RESULTS_DIR/$DESIGN_NAME.cdl.gz || $RESULTS_DIR/$DESIGN_NAME.gds.spice -nt $RESULTS_DIR/$DESIGN_NAME.cdl.gz ]]; then + if [[ ! -f $RESULTS_DIR/$DESIGN_NAME.gds.spice ]]; then + echo "Could not create cdl file from $RESULTS_DIR/$DESIGN_NAME.gds.spice" + exit 2 + else + echo "Creating $RESULTS_DIR/$DESIGN_NAME.cdl" + $LVS_ROOT/tech/$PDK/spi2cdl $RESULTS_DIR/$DESIGN_NAME.gds.spice | + gzip -c >$RESULTS_DIR/$DESIGN_NAME.cdl.gz + fi +fi + +# Copy default power file to work area if it doesn't exist +shopt -u nocasematch +BASE_NAME=${DESIGN_NAME//[A-Z0-9][A-Z0-9]_} # remove leading 2 byte prefices +if [[ ! -f $WORK_ROOT/cvc.power.$DESIGN_NAME ]]; then + if [[ -f $LVS_ROOT/tech/$PDK/cvc.power.$BASE_NAME ]]; then + cp $LVS_ROOT/tech/$PDK/cvc.power.$BASE_NAME $WORK_ROOT/cvc.power.$DESIGN_NAME + else + echo " +ERROR: Could not find $WORK_ROOT/cvc.power.$DESIGN_NAME" + exit 2 + fi +fi + +# Copy default configuration file +if [[ ! -f $WORK_ROOT/cvcrc ]]; then + if [[ -f $LVS_ROOT/tech/$PDK/cvcrc ]]; then + cp $LVS_ROOT/tech/$PDK/cvcrc $WORK_ROOT/. + else + echo " +ERROR: Could not file $WORK_ROOT/cvcrc" + exit 2 + fi +fi + +start_time=$SECONDS +cvc_rv $WORK_ROOT/cvcrc +cvc_status=$? + +runtime=$((SECONDS - start_time)) +hours=$((runtime / 3600)) +minutes=$(((runtime % 3600) / 60)) +seconds=$(((runtime % 3600) % 60)) +printf "Runtime: %d:%02d:%02d (hh:mm:ss)\n" $hours $minutes $seconds >>$WORK_ROOT/cvc.log + +if [[ $WORK_ROOT != $LOG_ROOT ]]; then + cp $WORK_ROOT/cvc.log $LOG_ROOT/. +fi +if [[ $WORK_ROOT != $SIGNOFF_ROOT ]]; then + cp $WORK_ROOT/cvc.error.gz $SIGNOFF_ROOT/. +fi + +if [[ $cvc_status -eq 0 && $(grep -c '^CVC: End:' $WORK_ROOT/cvc.log) -ne 1 ]]; then + # CVC finished abnormally + exit 3 + +elif [[ $cvc_status -eq 0 && $(awk '/^CVC: Total:/ {print $NF}' $WORK_ROOT/cvc.log) -gt 0 ]]; then + # CVC finished normally, but detected errors + exit 4 + +else + exit $cvc_status +fi diff --git a/scripts/be_checks/run_extract b/scripts/be_checks/run_extract new file mode 100755 index 00000000..0391c548 --- /dev/null +++ b/scripts/be_checks/run_extract @@ -0,0 +1,452 @@ +#! /bin/bash +# run_extract: extract with magic + +# Copyright 2023 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Set LVS parameters in lvs_config file + +# Use cases +# run_extract [lvs_config_file [top_layout [layout_file]]] + +usage="usage: run_extract [lvs_config_file [top_layout [layout_file]]]" +if [[ $# -gt 3 ]]; then + echo $usage + exit 1 +fi + +CONFIG_FILE=$1 +DESIGN_NAME=${2:+"-d $2"} + +if [[ $# -ne 0 ]]; then # if config file not specified, skip and use current environment + source <($LVS_ROOT/set_lvs_env.py -c $CONFIG_FILE $DESIGN_NAME) +fi +if [[ ! -v EXTRACT_FLATGLOB ]]; then + echo "Error: LVS environment problem." + exit 1 +fi +export TOP_LAYOUT=${2:-$TOP_LAYOUT} +export LAYOUT_FILE=${3:-$LAYOUT_FILE} + +echo " " +echo "Running extract..." + +echo "TOP LAYOUT: $TOP_LAYOUT" +echo "LAYOUT FILE: $LAYOUT_FILE" +echo "EXTRACT_FLATGLOB: $(echo $EXTRACT_FLATGLOB | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "EXTRACT_ABSTRACT: $(echo $EXTRACT_ABSTRACT | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" + +echo "WORK_ROOT : ${WORK_ROOT:=$(pwd)/$TOP_SOURCE}" +echo "LOG_ROOT : ${LOG_ROOT:=$WORK_ROOT}" +echo "SIGNOFF_ROOT: ${SIGNOFF_ROOT:=$WORK_ROOT}" +export LOG_ROOT SIGNOFF_ROOT WORK_ROOT + +mkdir -p $LOG_ROOT +mkdir -p $SIGNOFF_ROOT +mkdir -p $WORK_ROOT + +# Check for PDK_ROOT and PDK +if [[ -z "$PDK_ROOT" || -z "$PDK" ]]; then + echo "PDK_ROOT and/or PDK not set." + exit 1 +fi + +echo "LOG FILE: $LOG_ROOT/${LOG_FILE:=ext.log}" +rm -f $LOG_ROOT/$LOG_FILE $WORK_ROOT/$LOG_FILE + +if cmp -s $PDK_ROOT/$PDK/libs.tech/magic/$PDK.tech $LVS_ROOT/tech/$PDK/$PDK.tech; then + awk 'NF > 1 && /version/' $LVS_ROOT/tech/$PDK/$PDK.tech +else + echo "Tech files do not match:" + grep version $PDK_ROOT/$PDK/libs.tech/magic/$PDK.tech $LVS_ROOT/tech/$PDK/$PDK.tech | + awk 'NF > 2 && ! /^ *#/' + echo "Results may be incorrect. Contact efabless to update the soft connection rules." + #exit 1 +fi + +if [[ ! -f $WORK_ROOT/layout.cells ]]; then + $LVS_ROOT/run_hier_check "" "" $TOP_LAYOUT $LAYOUT_FILE "${PDK%?}_([^/_]*_)*_" +fi + +# Create extraction result directories. No error if they already exist. +echo "Extracting to ${EXT_DIR:=$WORK_ROOT/ext}" +rm -rf $EXT_DIR +mkdir -p $EXT_DIR + +# create work abstract file based on actual cells used (psuedo globbing) +# Will work with wildcards directly, but use psuedo globbing to check later. +echo $EXTRACT_FLATGLOB | + sed 's/ */\n/g' >$EXT_DIR/flatglob +if [[ -f $WORK_ROOT/layout.cells ]]; then + sed -e 's/\*/.*/g' -e 's/^/^/' -e 's/$/$/' $EXT_DIR/flatglob | + grep -f - $WORK_ROOT/layout.cells >$EXT_DIR/flatglob.glob +else + cp $EXT_DIR/flatglob $EXT_DIR/flatglob.glob +fi + +# create work abstract file based on actual cells used (psuedo globbing) +echo $EXTRACT_ABSTRACT | + sed 's/ */\n/g' >$EXT_DIR/abstract +if [[ -f $WORK_ROOT/layout.cells ]]; then + sed -e 's/\*/.*/g' -e 's/^/^/' -e 's/$/$/' $EXT_DIR/abstract | + grep -f - $WORK_ROOT/layout.cells >$EXT_DIR/abstract.glob +else + cp $EXT_DIR/abstract $EXT_DIR/abstract.glob +fi + +# create work subcut file based on actual cells used (psuedo globbing) +echo $EXTRACT_CREATE_SUBCUT | + sed 's/ */\n/g' >$EXT_DIR/subcut +if [[ -f $WORK_ROOT/layout.cells ]]; then + sed -e 's/\*/.*/g' -e 's/^/^/' -e 's/$/$/' $EXT_DIR/subcut | + grep -f - $WORK_ROOT/layout.cells >$EXT_DIR/subcut.glob +else + cp $EXT_DIR/abstract $EXT_DIR/subcut.glob +fi + +# Add any cells that should be flattened before extraction to 'flatten'. +export FLATGLOB_CELLS="$(cat $EXT_DIR/flatglob.glob 2>/dev/null | grep -v '^#')" +# Add any empty cells that should be extracted as black-boxes to 'abstract'. +export ABSTRACT_CELLS="$(cat $EXT_DIR/abstract.glob 2>/dev/null | grep -v '^#')" +# Add any cells that should be have a subcut layer added. +export SUBCUT_CELLS="$(cat $EXT_DIR/subcut.glob 2>/dev/null | grep -v '^#')" + +# Verify that magic is executable. +if ! which magic >&/dev/null; then + echo "Error: Could not execute magic." + exit 1 +fi + +if [[ ! -f $LAYOUT_FILE ]]; then + echo "Error: File not found: $LAYOUT_FILE" + exit 2 +fi + +# 1. Extract gds_file +date "+BEGIN: %c" >$WORK_ROOT/$LOG_FILE +start_time=$SECONDS + +echo " " +if [[ -z "$EXTRACT_TYPE" && $TOP_LAYOUT == *analog* ]]; then + EXTRACT_TYPE=analog +fi +if [[ $EXTRACT_TYPE == analog ]]; then + echo "Extracting as analog. Top ports connected by name." >>$WORK_ROOT/$LOG_FILE + export EXT_TYPE=analog + EXT_MESSAGE="connected by name (analog)" + EXT_TEXT="unique notopports" +else + echo "Extracting as digital. Top ports unique." >>$WORK_ROOT/$LOG_FILE + export EXT_TYPE=digital + EXT_MESSAGE="unique (digital)" + EXT_TEXT="unique" +fi + +# create gds abstraction script +cat > $EXT_DIR/abstract.tcl <= 0} { + cif istyle sky130($CIFIN_STYLE) + +} elseif {[string first gf180mcu $PDK] >= 0} { + cif istyle import($CIFIN_STYLE) + +} else { + puts "ERROR: Unknown PDK - $PDK" + exit 1 +} + +set last_time [orig_clock seconds] +puts "Abstracting $LAYOUT_FILE" +gds read $LAYOUT_FILE +cd $EXT_DIR +set current_time [orig_clock seconds] +puts "\nTIME: read GDS: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time + +# Create subcut gds +foreach cell { $SUBCUT_CELLS } { + # Adds an isosub/subcut layer to the cell. + # 1. For each cell, create a new cell with an isosub/subcut layer = boundary - ( dnwell | isosub ). + load \$cell + select top cell + set cellboundary [view bbox] ;# Save the boundary. + expand + puts stdout "Creating subcut for \$cell ..." + set subcut_cell_name \${cell}_subcut + flatten -nolabels \$subcut_cell_name ;# Flatten into a cell with a new name. + load \$subcut_cell_name + property FIXED_BBOX \$cellboundary ;# Reset the boundary after flattening. + cif ostyle subcutout + gds write \$subcut_cell_name ;# Write just the subcut layer. +} +set current_time [orig_clock seconds] +puts "\nTIME: create subcut: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time + +# Create abstract cells +foreach cell { $ABSTRACT_CELLS } { ;# Set abstract cells and delete all their subcell instances. + load \$cell + property LEFview true + puts "Abstracting \$cell" + set instance_list [cellname list childinst \$cell] + set instance_count [llength \$instance_list] + select top cell + select visible + set port_list [lindex [what -list] 1] + puts "instance count:\$instance_count port count:[llength \$port_list]" + if { \$instance_count > 0 || [llength \$port_list] > 10 } { + # When an abstract cell has child, all the children are extracted. + # To avoid this, delete the child instances. + # If there are many instances this can take hours. + # Split the layout up into a grid and delete by grid. + select top cell + set cell_bbox [box values] + puts "Full size \$cell_bbox" + set cell_left [lindex \$cell_bbox 0] + set cell_bottom [lindex \$cell_bbox 1] + set cell_right [lindex \$cell_bbox 2] + set cell_top [lindex \$cell_bbox 3] + set cell_height [box height] + set cell_width [box width] + see no * + set window_size 100 + set current_time [orig_clock seconds] + set start_time \$current_time + # Coordinates returned from box are in internal units. + # Without qualifiers, arguments to box are in lambda units. Force internal units with i suffix. + # Search for a region where the subcells can be deleted in under 12 seconds. Region is increased 4x each loop. + while { [expr \$current_time - \$start_time] < 3 && \$window_size < \$cell_height && \$window_size < \$cell_width } { + set start_time \$current_time + incr window_size \$window_size + box size \${window_size}i \${window_size}i + select visible + select less area * ;# unselect text + delete + set current_time [orig_clock seconds] + } + set step_estimate [expr \$cell_height / \$window_size * \$cell_width / \$window_size] + puts "Setting deletion window size to \$window_size. Estimate \$step_estimate steps." + set step_count 0 + for {set box_left \$cell_left} {\$box_left < \$cell_right} {incr box_left \$window_size} { + for {set box_bottom \$cell_bottom} {\$box_bottom < \$cell_top} {incr box_bottom \$window_size} { + incr step_count + box position \${box_left}i \${box_bottom}i + select visible + select less area * ;# unselect text + puts "Step \$step_count/\$step_estimate: deleting [llength [lindex [what -list] 2]] objects at [box values]" + delete + } + } + # Delete instances that may have been missed. + select top cell + select visible + select less area * + puts "Deleting [llength [lindex [what -list] 2]] final objects" + delete + + # Delete non-port layers. Shorted ports can cause problems in parent hierarchy. + # Deleting non-port layers should eliminate the shorts. + see * + select visible + set select_list [what -list] + see no * + foreach layer [lindex \$select_list 0] { + select area \$layer ;# select ports + if { [llength [lindex [what -list] 1]] == 0 } { + see \$layer + select visible \$layer + puts "Deleting \$layer" + delete + } + } + lef nocheck vssd1 vssd2 vccd1 vccd2 vssa1 vssa2 vdda1 vdda2 + lef write \$cell -hide -pinonly + } +} +set current_time [orig_clock seconds] +puts "\nTIME: create abstract: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time +EOF + +# Create abstract and subcut cells +magic -dnull -noc -rcfile $LVS_ROOT/tech/magicrc $EXT_DIR/abstract.tcl &1 | + tee -a $WORK_ROOT/$LOG_FILE +abstract_status=${PIPESTATUS[0]} + +# create gds extraction script +cat > $EXT_DIR/extract.tcl <= 0} { + cif istyle sky130($CIFIN_STYLE) + +} elseif {[string first gf180mcu $PDK] >= 0} { + cif istyle import($CIFIN_STYLE) + +} else { + puts "ERROR: Unknown PDK - $PDK" + exit 1 +} + +set last_time [orig_clock seconds] +foreach cell { $ABSTRACT_CELLS } { ;# Load abstract cells + if { [file exists $EXT_DIR/\$cell.lef] } { + puts "Using abstracted \$cell" + lef read $EXT_DIR/\$cell.lef + } +} + +foreach cell { $FLATGLOB_CELLS } { + gds flatglob \$cell +} +# list cells to be flattened +puts "Flattening [string map {" " "\n"} [gds flatglob]]" +gds flatten yes ;# Flattens cells with few layers +gds noduplicates yes ;# keep abstract views +puts "\nExtracting $LAYOUT_FILE" +gds read $LAYOUT_FILE +cd $EXT_DIR +set current_time [orig_clock seconds] +puts "\nTIME: read GDS: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time + +set flatglob_error 0 +foreach cell { $FLATGLOB_CELLS } { ;# Check for unflattened flatglob cells. + if { [llength [cellname list children \$cell]] > 0 } { + set flatglob_error 1 + puts "Could not flatten \$cell because it contains these subcells:" + foreach subcell [cellname list children \$cell] { + puts " \$subcell" + } + } +} +if { \$flatglob_error } { ;# Quit if there are unflattened flatglob cells. + exit 1 +} + +gds flatten no ;# subcut cells will have few shapes, so don't flatten them when reading their gds later. + +foreach cell { $SUBCUT_CELLS } { + # Adds an isosub/subcut layer to the cell. + # 2. Add this new cell to the original cell. + # 3. Flatten the new cell instance in the original cell. + set subcut_cell_name \${cell}_subcut + gds read \$subcut_cell_name ;# Read the subcut only cell. + load \$cell + select top cell + getcell \$subcut_cell_name child 0 0 parent 0 0 ;# Place the subcut cell at the origin. + puts "Flattening [instance list self] in \$cell" + flatten -doinplace [instance list self] ;# flatten subcut cell to place subcut layer. +} +set current_time [orig_clock seconds] +puts "\nTIME: add subcut: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time + +foreach cell { $ABSTRACT_CELLS } { ;# Set abstract cells + load \$cell + property LEFview true + puts "Abstracting \$cell" +} +set current_time [orig_clock seconds] +puts "\nTIME: set abstract: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time + +load $TOP_LAYOUT +select top cell +expand +extract no all ;# clear all flags +extract do aliases +extract do local +extract $EXT_TEXT +extract style ngspice($EXTRACT_STYLE) +extract +set current_time [orig_clock seconds] +puts "\nTIME: extract: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time + +ext2spice lvs +ext2spice merge conservative ;# reduce parallel devices +ext2spice short resistor ;# keep both ports but connect them with a 0 ohm resistor +ext2spice -o $TOP_LAYOUT.gds.spice $TOP_LAYOUT.ext +set current_time [orig_clock seconds] +puts "\nTIME: netlist: [orig_clock format [expr {\$current_time - \$last_time}] -gmt true -format %H:%M:%S] \n" +set last_time \$current_time + +feedback save $TOP_LAYOUT-ext2gds.spice.feedback.txt +EOF + +magic -dnull -noc -rcfile $LVS_ROOT/tech/magicrc $EXT_DIR/extract.tcl &1 | + tee -a $WORK_ROOT/$LOG_FILE +ext_status=${PIPESTATUS[0]} + +date "+END: %c" >>$WORK_ROOT/$LOG_FILE +runtime=$((SECONDS - start_time)) +hours=$((runtime / 3600)) +minutes=$(((runtime % 3600) / 60)) +seconds=$(((runtime % 3600) % 60)) +printf "Runtime: %d:%02d:%02d (hh:mm:ss)\n" $hours $minutes $seconds >>$WORK_ROOT/$LOG_FILE +if [[ $WORK_ROOT != $LOG_ROOT ]]; then + cp $WORK_ROOT/$LOG_FILE $LOG_ROOT/$LOG_FILE +fi + +# Create extracted hierarchy +echo "Creating layout hierarchy in $EXT_DIR/$TOP_LAYOUT.hier..." +awk -f $LVS_ROOT/scripts/ext.hier.awk -v TOP=$TOP_LAYOUT $EXT_DIR/*.ext >$EXT_DIR/$TOP_LAYOUT.hier + +# Compress large ext files +find $EXT_DIR -name '*.ext' -size +1M -exec gzip {} \; + +if [[ $(grep -c 'direction reversal in path' $LOG_ROOT/$LOG_FILE) -ne 0 ]]; then + echo " +Error: invalid path reversal. See $LOG_ROOT/$LOG_FILE" + magic_status=1 +fi + +grep 'layer=' $LOG_ROOT/$LOG_FILE | + awk '/, layer=/ {print gensub(/.*, layer=/, "layer=", 1)}' | + sort -u | + comm -23 - $LVS_ROOT/tech/$PDK/known.undefined.layer >$EXT_DIR/unknown.layers +if [[ $(cat $EXT_DIR/unknown.layers | wc -w) -ne 0 ]]; then + echo " +Error: invalid layers. See $LOG_ROOT/$LOG_FILE" + cat $EXT_DIR/unknown.layers + magic_status=1 +fi + +# Check that extraction completed successfully +if [[ $abstract_status -ne 0 || \ + $ext_status -ne 0 || \ + ${magic_status:=0} -ne 0 || \ + $(grep -c 'exttospice finished.' $LOG_ROOT/$LOG_FILE) -ne 1 ]]; then + echo " +Error: extraction did not complete successfully" + exit 4 +fi + diff --git a/scripts/be_checks/run_full_lvs b/scripts/be_checks/run_full_lvs new file mode 100755 index 00000000..1a2b862d --- /dev/null +++ b/scripts/be_checks/run_full_lvs @@ -0,0 +1,328 @@ +#! /bin/bash +# run_full_lvs: extract (if necessary) and run lvs with netgen + +# Copyright 2022 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Set LVS parameters in lvs_config file + +# Use cases +# run_full_lvs [--noextract] lvs_config_file [top_source [top_layout]] + +if [[ $1 == "--noextract" ]]; then + export EXTRACT_LAYOUT=no + shift +else + export EXTRACT_LAYOUT=yes +fi + +usage="usage: run_full_lvs [--noextract] [lvs_config_file [top_source [top_layout [layout_file]]]]" +if [[ $# -gt 4 ]]; then + echo $usage + exit 1 +fi + +CONFIG_FILE=$1 +DESIGN_NAME=${2:+"-d $2"} + +if [[ $# -ne 0 ]]; then # if config file not specified, skip and use current environment + source <($LVS_ROOT/set_lvs_env.py -c $CONFIG_FILE $DESIGN_NAME) +fi +if [[ ! -v EXTRACT_FLATGLOB ]]; then + echo "ERROR: LVS environment problem." + exit 1 +fi +export TOP_SOURCE=${2:-$TOP_SOURCE} +export TOP_LAYOUT=${3:-$TOP_LAYOUT} +export LAYOUT_FILE=${4:-$LAYOUT_FILE} + +#if [[ $EXTRACT_LAYOUT == no ]]; then +# export LAYOUT_FILE= +#fi + +echo " " +echo "Running LVS..." + +echo "TOP SOURCE: $TOP_SOURCE" +echo "SOURCE FILE(S): $(echo $LVS_SPICE_FILES_TO_FIX $LVS_SPICE_FILES $LVS_VERILOG_FILES | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "TOP LAYOUT: $TOP_LAYOUT" +echo "LAYOUT FILE: $LAYOUT_FILE" +echo "EXTRACT_FLATGLOB: $(echo $EXTRACT_FLATGLOB | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "EXTRACT_ABSTRACT: $(echo $EXTRACT_ABSTRACT | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "LVS_FLATTEN: $(echo $LVS_FLATTEN | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "LVS_NOFLATTEN: $(echo $LVS_NOFLATTEN | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "LVS_IGNORE: $(echo $LVS_IGNORE | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" + +echo "WORK_ROOT : ${WORK_ROOT:=$(pwd)/$TOP_SOURCE}" +echo "LOG_ROOT : ${LOG_ROOT:=$WORK_ROOT}" +echo "SIGNOFF_ROOT: ${SIGNOFF_ROOT:=$WORK_ROOT}" +export LOG_ROOT SIGNOFF_ROOT WORK_ROOT + +mkdir -p $LOG_ROOT +mkdir -p $SIGNOFF_ROOT +mkdir -p $WORK_ROOT + +# Check for PDK_ROOT and PDK +if [[ -z "$PDK_ROOT" || -z "$PDK" ]]; then + echo "PDK_ROOT and/or PDK not set." + exit 1 +fi + +if [[ ! -f $WORK_ROOT/layout.cells || ! -f $WORK_ROOT/verilog.cells ]]; then + $LVS_ROOT/run_hier_check $TOP_SOURCE "$(echo $LVS_VERILOG_FILES | sed 's/#[^ ]*//g')" $TOP_LAYOUT $LAYOUT_FILE "${PDK%?}_([^/_]*_)*_" +fi + +# Extraction is now a separate program. +rm -f $LOG_ROOT/lvs.log $SIGNOFF_ROOT/lvs.report +export EXT_DIR=$WORK_ROOT/ext +if [[ $EXTRACT_LAYOUT == yes ]]; then + env CIFIN_STYLE= EXTRACT_STYLE= $LVS_ROOT/run_extract + extract_status=$? +else + if [[ ! -f $EXT_DIR/$TOP_LAYOUT.gds.spice ]]; then + echo "Error: missing $EXT_DIR/$TOP_LAYOUT.gds.spice" + echo "Specify gds_file to create" + echo $usage + exit 2 + fi + echo "Reusing $EXT_DIR/$TOP_LAYOUT.gds.spice." +fi + +# Check that extraction completed successfully +if [[ ${extract_status:=0} -ne 0 || $(grep -c 'exttospice finished.' $LOG_ROOT/ext.log) -ne 1 ]]; then + echo " +Error: extraction did not complete successfully" + exit 4 +fi + +# create work flatten file based on actual cells used (pseudo globbing) +echo $LVS_FLATTEN | + sed 's/ */\n/g' >$WORK_ROOT/flatten +if [[ -f $WORK_ROOT/layout.cells && -f $WORK_ROOT/verilog.cells ]]; then + # Do pseudo globbing against layout and verilog. "*" expansion only. + sed -e 's/\*/.*/g' $WORK_ROOT/flatten | + grep -hx -f - $WORK_ROOT/layout.cells $WORK_ROOT/verilog.cells | + cat - $WORK_ROOT/flatten | + sed 's/^\*//' | + awk 'NF > 0' | + sort -u >$WORK_ROOT/flatten.glob +else + cp $WORK_ROOT/flatten $WORK_ROOT/flatten.glob +fi + +# create work noflatten file based on actual cells used (pseudo globbing) +echo $LVS_NOFLATTEN | + sed 's/ */\n/g' >$WORK_ROOT/noflatten +if [[ -f $WORK_ROOT/layout.cells && -f $WORK_ROOT/verilog.cells ]]; then + # Do pseudo globbing against layout and verilog. "*" expansion only. + sed -e 's/\*/.*/g' $WORK_ROOT/noflatten | + grep -hx -f - $WORK_ROOT/layout.cells $WORK_ROOT/verilog.cells | + cat - $WORK_ROOT/noflatten | + sed 's/^\*//' | + awk 'NF > 0' | + sort -u >$WORK_ROOT/noflatten.glob +else + cp $WORK_ROOT/noflatten $WORK_ROOT/noflatten.glob +fi + +# create work ignore file based on actual cells used (pseudo globbing) +echo $LVS_IGNORE | + sed 's/ */\n/g' >$WORK_ROOT/ignore +if [[ -f $WORK_ROOT/layout.cells && -f $WORK_ROOT/verilog.cells ]]; then + # Do pseudo globbing against layout and verilog. "*" expansion only. + sed -e 's/\*/.*/g' $WORK_ROOT/ignore | + grep -hx -f - $WORK_ROOT/layout.cells $WORK_ROOT/verilog.cells | + cat - $WORK_ROOT/ignore | + sed 's/^\*//' | + awk 'NF > 0' | + sort -u >$WORK_ROOT/ignore.glob +else + cp $WORK_ROOT/ignore $WORK_ROOT/ignore.glob +fi + +# Verify that netgen is executable. +if ! which netgen >&/dev/null; then + echo "Error: Could not execute netgen." + exit 1 +fi + +# 5. Compare +# Create lists of source files. Allow globbing. +# Files in LVS_SPICE_FILES_TO_FIX are modified with a pdk specific program to local versions. + +rm -rf $WORK_ROOT/spice_fix +mkdir -p $WORK_ROOT/spice_fix +cat /dev/null > $WORK_ROOT/spice_files +SPICE_FIX_LIST=$(echo $LVS_SPICE_FILES_TO_FIX | sed 's/ */\n/g' | awk 'NF > 0 && ! /^#/') +if [[ $SPICE_FIX_LIST ]]; then + cp $SPICE_FIX_LIST $WORK_ROOT/spice_fix/. + $LVS_ROOT/tech/$PDK/fix_spice $WORK_ROOT/spice_fix/*.spice + ls --sort=none $WORK_ROOT/spice_fix/* | + grep -v '.org$' >$WORK_ROOT/spice_files +fi + +SPICE_LIST=$(echo $LVS_SPICE_FILES | sed 's/ */\n/g' | awk 'NF > 0 && ! /^#/') +if [[ $SPICE_LIST ]]; then + ls --sort=none $SPICE_LIST >>$WORK_ROOT/spice_files +fi + +cat /dev/null > $WORK_ROOT/verilog_files +VERILOG_LIST=$(echo $LVS_VERILOG_FILES | sed 's/ */\n/g' | awk 'NF > 0 && ! /^#/') +if [[ $VERILOG_LIST ]]; then + ls --sort=none $VERILOG_LIST >>$WORK_ROOT/verilog_files +fi + +cp $LVS_ROOT/tech/$PDK/${PDK}_setup.tcl $WORK_ROOT/${PDK}_setup.tcl + +while read cell; do + cat >>$WORK_ROOT/${PDK}_setup.tcl <<-flatten + if { [lsearch \$cells1 {$cell}] >= 0 } { + #puts stdout "Flattening $cell in layout" + flatten class {-circuit1 $cell} + } + if { [lsearch \$cells2 {$cell}] >= 0 } { + #puts stdout "Flattening $cell in source" + flatten class {-circuit2 $cell} + } + flatten +done <$WORK_ROOT/flatten.glob + +while read cell; do + cat >>$WORK_ROOT/${PDK}_setup.tcl <<-ignore + if { [lsearch \$cells1 {$cell}] >= 0 } { + puts stdout {Ignoring $cell in layout} + ignore class {-circuit1 $cell} + } + if { [lsearch \$cells2 {$cell}] >= 0 } { + puts stdout {Ignoring $cell in source} + ignore class {-circuit2 $cell} + } + ignore +done <$WORK_ROOT/ignore.glob + +cat >$WORK_ROOT/lvs.script <<-script + puts "Reading layout $WORK_ROOT/ext/$TOP_LAYOUT.gds.spice..." + set layout [readnet spice $WORK_ROOT/ext/$TOP_LAYOUT.gds.spice] + set source [readnet spice /dev/null] +script + +while read spice_file; do + cat >>$WORK_ROOT/lvs.script <<-spice + puts "Reading source $spice_file..." + readnet spice $spice_file \$source + spice +done <$WORK_ROOT/spice_files +while read verilog_file; do + cat >>$WORK_ROOT/lvs.script <<-verilog + puts "Reading source $verilog_file..." + readnet verilog $verilog_file \$source + verilog +done <$WORK_ROOT/verilog_files + +cat >>$WORK_ROOT/lvs.script <<-lvs + lvs "\$layout $TOP_LAYOUT" "\$source $TOP_SOURCE" $WORK_ROOT/${PDK}_setup.tcl $WORK_ROOT/lvs.report -blackbox -json -noflatten=$WORK_ROOT/noflatten.glob +lvs + +date "+BEGIN: %c" >$WORK_ROOT/lvs.log +start_time=$SECONDS + +echo " " +: "${NETGEN_COLUMNS:=80}" +export NETGEN_COLUMNS +netgen -batch source $WORK_ROOT/lvs.script 2>&1 | + tee -a $WORK_ROOT/lvs.log +netgen_status=${PIPESTATUS[0]} + +# Check for circuits that were compared as black boxes. +awk ' +/Circuit 1 .* will not flatten/ {print $4, "is a black box in the layout"} +/Circuit 2 .* will not flatten/ {print $4, "is a black box in the source"} +' $WORK_ROOT/lvs.report >$WORK_ROOT/lvs.unflattened +awk -f $LVS_ROOT/tech/$PDK/known_abstract_filter.awk $WORK_ROOT/lvs.log | + grep -w -v $WORK_DIR/abstract.glob | + awk ' +/Matching pins/ {print $4, "is a black box in the layout and source"} +/contains no devices/ {print $2, "contains no devices"} +' - >>$WORK_ROOT/lvs.unflattened +if [[ -s $WORK_ROOT/lvs.unflattened ]]; then + if grep -q -w -v -f $WORK_ROOT/abstract.glob $WORK_ROOT/lvs.unflattened; then + echo "Warning: device level LVS may be incomplete due to these unflattened cell(s): " | + tee -a $WORK_ROOT/lvs.report | + tee -a $WORK_ROOT/lvs.log + # Only set an error for unabstracted mismatches + lvs_warning=1 + else + echo "Notice: LVS completed with these abstracted cells: " | + tee -a $WORK_ROOT/lvs.report | + tee -a $WORK_ROOT/lvs.log + fi + cat $WORK_ROOT/lvs.unflattened | + tee -a $WORK_ROOT/lvs.report | + tee -a $WORK_ROOT/lvs.log +fi + +if [[ -s $WORK_ROOT/ignore.glob ]]; then + echo "Warning: device level LVS may be incomplete because $(cat $WORK_ROOT/ignore.glob | wc -l) cell(s) was/were ignored: see $WORK_ROOT/ignore.glob" | + tee -a $WORK_ROOT/lvs.report | + tee -a $WORK_ROOT/lvs.log + lvs_warning=1 +fi + +date "+END: %c" >>$WORK_ROOT/lvs.log +runtime=$((SECONDS - start_time)) +hours=$((runtime / 3600)) +minutes=$(((runtime % 3600) / 60)) +seconds=$(((runtime % 3600) % 60)) +printf "Runtime: %d:%02d:%02d (hh:mm:ss)\n" $hours $minutes $seconds >>$WORK_ROOT/lvs.log +if [[ $WORK_ROOT != $LOG_ROOT ]]; then + cp $WORK_ROOT/lvs.log $LOG_ROOT/. +fi +if [[ $WORK_ROOT != $SIGNOFF_ROOT ]]; then + cp $WORK_ROOT/lvs.report $WORK_ROOT/lvs.unflattened $SIGNOFF_ROOT/. +fi + +# Set exit code +if [[ $netgen_status -ne 0 ]]; then + echo " +Error: netgen ended abnormally." + +# Missing 'Final result' line. +elif [[ $(grep -c 'Final result:' $SIGNOFF_ROOT/lvs.report) -ne 1 ]]; then + netgen_status=4 + echo " +Error: netgen did not complete." + +# Did not uniquely match. +elif [[ $(grep -c 'Final result: Circuits match uniquely\.' $SIGNOFF_ROOT/lvs.report) -ne 1 ]]; then + netgen_status=4 + echo " +Error: LVS mismatch." + +# Property errors +elif [[ $(grep -c 'The following cells had property errors:' $SIGNOFF_ROOT/lvs.report) -gt 0 ]]; then + netgen_status=6 + echo " +Error: Property mismatch." + +# Uniquely matched, but cells were black-boxed or ignored. +elif [[ ${lvs_warning:=0} -ne 0 ]]; then + netgen_status=5 + echo " +Warning: possible lvs discrepancy" + +else + netgen_status=0 +fi + +exit $netgen_status diff --git a/scripts/be_checks/run_hier_check b/scripts/be_checks/run_hier_check new file mode 100755 index 00000000..e0e9dbab --- /dev/null +++ b/scripts/be_checks/run_hier_check @@ -0,0 +1,269 @@ +#! /bin/bash +# run_hier_check: Checks layout hierarchy against verilog + +# Copyright 2022 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Overview: +# 1. Extract verilog hierarchy, limit to TOP_CIRCUIT and child subcircuits. +# 2. Extract gds/oas hierachy, if necessary. +# 3. Compare +# + +# Use case +# run_hier_check top_source verilog_files top_layout layout_file [primitive_prefix [gds_prefix]] +if [[ $# -lt 4 || $# -gt 6 ]]; then + echo "usage: run_hier_check top_source verilog_files top_layout gds_file [primitive_prefix [gds_prefix]]" + exit 1 +fi + +export TOP_SOURCE=$1 +export SOURCE_FILES=$2 +export TOP_LAYOUT=$3 +export LAYOUT_FILE=$4 +PRIMITIVE_PREFIX_FILTER='-e s/\$WORK_ROOT/hier.log +start_time=$SECONDS + +if [[ $(echo $SOURCE_FILES | wc -w) -gt 0 ]]; then + echo "Creating $verilog_cell_file from the following files..." | + tee -a $WORK_ROOT/hier.log + echo $SOURCE_FILES | + sed -e 's/ */\n/g' | + sed -e 's/^/ /' | + tee -a $WORK_ROOT/hier.log + + sed '/^[ ]*module[ ].*[^ ](/s/(/ (/' $(echo $SOURCE_FILES) | + awk -v top=$TOP_SOURCE ' + $1 ~ /^\/\*/ { # skip block comments + while ( ! /\*\// ) { + getline; + } + } + $1 == "module" { + if ( $2 in modules ) { + print "Duplicate module definition", $2 > "'$WORK_ROOT/hier.log'"; + } + modules[$2] = 1; + if ( ! ( $2 in cells ) ) { + cells[$2] = 1; + } + module = $2; + next; + } + $1 ~ /^[ ]*\/\// { # skip single line comments + next; + } + / \(/ && $1 !~ /^\./ { + key = module "/" $1; + if ( ! ( $1 in cells ) ) { + cells[$1] = 1; + } + if ( key in hier ) { + hier[key] += 1; + } else { + subcells[module] = subcells[module] " " $1; + hier[key] = 1; + } + } + END { + print_subckt[top] = 1; + AddPrintSubckts(subcells[top]); + for ( key in hier ) { + split(key, path, "/"); + if ( path[1] in print_subckt ) { + print key, hier[key]; + } + } + for ( cell in cells ) { + print cell > "'$verilog_cell_file'"; + } + } + function AddPrintSubckts(subckt_list, subckts, subckt_it) { + subcell_count = split(subckt_list, subckts); + for ( subckt_it in subckts ) { + print_subckt[subckts[subckt_it]] = 1; + AddPrintSubckts(subcells[subckts[subckt_it]]); + } + }' - | + grep -v // | + sed -E $PRIMITIVE_PREFIX_FILTER | + sort >$WORK_ROOT/verilog.hier +else + echo "No verilog files..." + rm -f $WORK_ROOT/verilog.hier $verilog_cell_file + touch $WORK_ROOT/verilog.hier + cat >$verilog_cell_file <<-EOF + $TOP_SOURCE + EOF +fi + +if [[ $LAYOUT_FILE ]]; then + if [[ $LAYOUT_FILE == *.gz ]]; then + CAT=zcat + BASE_LAYOUT=${LAYOUT_FILE%.gz} + else + CAT=cat + BASE_LAYOUT=$LAYOUT_FILE + fi + EXT=${BASE_LAYOUT##*.} + if [[ "$EXT" == "txt" ]]; then + TEXT_FILE=$BASE_LAYOUT + elif [[ "$EXT" == "gds" || "$EXT" == "oas" ]]; then + TEXT_FILE=$WORK_ROOT/layout.txt + cat >$WORK_ROOT/gds2txt.py <<-EOF + import pya + + app = pya.Application.instance() + opt = pya.SaveLayoutOptions() + layout_view = pya.Layout() + + input_layout = "$LAYOUT_FILE" + output = "$TEXT_FILE" + # Setting the name of the output file and setting the substitution character + print("[INFO] Changing from " + input_layout + "\n to " + output) + opt.set_format_from_filename(output) + opt.oasis_substitution_char='' + + # Reading the input file and writing it to the output file name + layout_view.read(input_layout) + for cell_it in layout_view.each_cell(): + if cell_it.name.endswith("$TOP_LAYOUT"): + myIndex = layout_view.cell(cell_it.name).cell_index() + break + opt.select_cell(myIndex) + opt.add_layer(0, pya.LayerInfo()) + layout_view.write(output, opt) + + app.exit(0) + EOF + klayout -b -rm $WORK_ROOT/gds2txt.py | + tee -a $WORK_ROOT/hier.log + gzip -f $TEXT_FILE + CAT=zcat + fi + + $CAT $TEXT_FILE | + awk ' + /^STRNAME/ { + module = $2; + } + /^SNAME/ { + key = module "/" $2; + if ( key in hier ) { + hier[key] += 1; + } else { + hier[key] = 1; + } + } + END { + for ( key in hier ) { + print key, hier[key]; + } + }' - | + sed -E $GDS_PREFIX_FILTER $PRIMITIVE_PREFIX_FILTER | + sort -u >$WORK_ROOT/layout.hier + $CAT $TEXT_FILE | + grep STRNAME | + awk '{print $2}' | + sort >$WORK_ROOT/layout.cells + +elif [[ -f $WORK_ROOT/layout.hier ]]; then + echo "Reusing $WORK_ROOT/layout.hier" +else + echo "Could not locate $WORK_ROOT/layout.hier" + exit 1 +fi + +comm -23 $WORK_ROOT/verilog.hier $WORK_ROOT/layout.hier | + awk '{print $1}' | + fgrep -f - $WORK_ROOT/verilog.hier $WORK_ROOT/layout.hier | + sed 's/:/ /' | + awk ' BEGIN { + print "verilog,,layout"; + } + /verilog.hier/ { + verilog_count += 1; + verilog[verilog_count] = $2; + instances[$2] = $3; + } + /layout.hier/ { + if ( match_count == verilog_count || verilog[match_count+1] > $2 ) { + print ",," $2 "," $3; + } else { + while ( match_count < verilog_count && verilog[match_count+1] <= $2 ) { + match_count += 1; + if ( verilog[match_count] < $2 ) { + print verilog[match_count] "," instances[verilog[match_count]]; + } else { # equal + print verilog[match_count] "," instances[verilog[match_count]] "," $2 "," $3; + } + } + if ( match_count == verilog_count && verilog[match_count] != $2 ) { + print verilog[match_count] "," instances[verilog[match_count]]; + } + } + } + END { + while ( match_count < verilog_count ) { + match_count += 1; + print verilog[match_count] "," instances[verilog[match_count]]; + } + }' - >$WORK_ROOT/hier.csv + +if [[ $(cat $WORK_ROOT/hier.csv | wc -l) -eq 1 ]]; then + echo "Hierarchy check for $TOP_SOURCE passed." | + tee -a $WORK_ROOT/hier.log +else + echo "Hierarchy check for $TOP_SOURCE failed. See $WORK_ROOT/hier.csv" | + tee -a $WORK_ROOT/hier.log +fi + +date "+END: %c" >>$WORK_ROOT/hier.log +runtime=$((SECONDS - start_time)) +hours=$((runtime / 3600)) +minutes=$(((runtime % 3600) / 60)) +seconds=$(((runtime % 3600) % 60)) +printf "Runtime: %d:%02d:%02d (hh:mm:ss)\n" $hours $minutes $seconds >>$WORK_ROOT/hier.log +if [[ $WORK_ROOT != $LOG_ROOT ]]; then + cp $WORK_ROOT/hier.log $LOG_ROOT/. +fi +if [[ $WORK_ROOT != $SIGNOFF_ROOT ]]; then + cp $WORK_ROOT/hier.csv $SIGNOFF_ROOT/. +fi diff --git a/scripts/be_checks/run_oeb_check b/scripts/be_checks/run_oeb_check new file mode 100755 index 00000000..a5a357ce --- /dev/null +++ b/scripts/be_checks/run_oeb_check @@ -0,0 +1,617 @@ +#! /usr/bin/env bash + +# check that the oeb pin is low/high based on io_in and io_out connections + +# Uses lvs_config to optionally extract a spice netlist +# Requires a netlist $WORK_ROOT/ext/$DESIGN_NAME.gds.spice +# Converts this netlist to $WORK_ROOT/ext/$DESIGN_NAME.cdl.gz + +# Copyright 2023 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Parameters are read from $WORK_ROOT/cvcrc.oeb which is copied from the default in $LVS_ROOT if non-existent. + +# Return codes +# 1: LVS_ROOT not set +# 2: Missing file +# 3: Unrecognized block name +# 4: CVC execution error +# 5: OEB related error +# 6: OEB related warning + +# Use cases +# run_oeb_check [--noextract] [lvs_config_file [top_layout [layout_file]]] + +if [[ $1 == "--noextract" ]]; then + export EXTRACT_LAYOUT=no + shift +else + export EXTRACT_LAYOUT=yes +fi + +usage="usage: run_oeb_check [--noextract] [lvs_config_file [top_layout [layout_file]]]]" +if [[ $# -gt 3 ]]; then + echo $usage + exit 1 +fi + +# Check for LVS_ROOT +if [[ -z "$LVS_ROOT" ]]; then + echo "LVS_ROOT not set." + exit 1 +fi + +CONFIG_FILE=$1 +DESIGN_NAME=${2:+"-d $2"} + +if [[ $# -ne 0 ]]; then # if config file not specified, skip and use current environment + source <($LVS_ROOT/set_lvs_env.py -c $CONFIG_FILE $DESIGN_NAME) +fi +if [[ ! -v EXTRACT_FLATGLOB ]]; then + echo "ERROR: LVS environment problem." + exit 1 +fi +export TOP_LAYOUT=${2:-$TOP_LAYOUT} +export LAYOUT_FILE=${3:-$LAYOUT_FILE} + +export DESIGN_NAME=$TOP_LAYOUT + +echo "DESIGN NAME: $DESIGN_NAME" + +echo "WORK_ROOT : ${WORK_ROOT:=$(pwd)/$DESIGN_NAME}" +echo "LOG_ROOT : ${LOG_ROOT:=$(pwd)/$DESIGN_NAME}" +echo "SIGNOFF_ROOT: ${SIGNOFF_ROOT:=$(pwd)/$DESIGN_NAME}" +export LOG_ROOT SIGNOFF_ROOT WORK_ROOT + +mkdir -p $LOG_ROOT $SIGNOFF_ROOT $WORK_ROOT +export RESULTS_DIR=$WORK_ROOT/ext + +rm -f $WORK_ROOT/cvc.oeb* $LOG_ROOT/cvc.oeb* $SIGNOFF_ROOT/cvc.oeb* + +export RESULTS_DIR=$WORK_ROOT/ext +if [[ $EXTRACT_LAYOUT == yes ]]; then + env RUN_DIR=$RESULTS_DIR CIFIN_STYLE= EXTRACT_STYLE= LOG_FILE=ext.log $LVS_ROOT/run_extract + ext_status=$? +fi + +echo " " +echo "Running CVC for oeb check..." + +# Create cdl file from extracted spice file if it doesn't exist +if [[ ! -f $RESULTS_DIR/$DESIGN_NAME.cdl.gz || $RESULTS_DIR/$DESIGN_NAME.gds.spice -nt $RESULTS_DIR/$DESIGN_NAME.cdl.gz ]]; then + if [[ ! -f $RESULTS_DIR/$DESIGN_NAME.gds.spice ]]; then + echo "Could not create cdl file from $RESULTS_DIR/$DESIGN_NAME.gds.spice" + exit 2 + else + echo "Creating $RESULTS_DIR/$DESIGN_NAME.cdl" + $LVS_ROOT/tech/$PDK/spi2cdl $RESULTS_DIR/$DESIGN_NAME.gds.spice | + gzip -c >$RESULTS_DIR/$DESIGN_NAME.cdl.gz + fi +fi + +# Copy default power file to work area if it doesn't exist +shopt -u nocasematch +BASE_NAME=${DESIGN_NAME//[A-Z0-9][A-Z0-9]_} # remove leading 2 byte prefices +if [[ ! -f $WORK_ROOT/cvc.power.$DESIGN_NAME ]]; then + if [[ -f $LVS_ROOT/tech/$PDK/cvc.power.$BASE_NAME ]]; then + cp $LVS_ROOT/tech/$PDK/cvc.power.$BASE_NAME $WORK_ROOT/cvc.power.$DESIGN_NAME + else + echo " +ERROR: Could not find $WORK_ROOT/cvc.power.$DESIGN_NAME" + exit 2 + fi +fi + +if [[ ! -f $WORK_ROOT/cvcrc.oeb ]]; then + if [[ ! -f $WORK_ROOT/cvcrc ]]; then + if [[ -f $LVS_ROOT/tech/$PDK/cvcrc ]]; then + cp $LVS_ROOT/tech/$PDK/cvcrc $WORK_ROOT/cvcrc + else + echo " +ERROR: Could not create $WORK_ROOT/cvcrc.oeb" + exit 2 + fi + fi + sed 's/cvc.log/cvc.oeb.log/' $WORK_ROOT/cvcrc >$WORK_ROOT/cvcrc.oeb +fi + +if [[ $DESIGN_NAME == *user_analog_project_wrapper ]]; then + cat >$WORK_ROOT/cvc.oeb.script <<-cvcin + c 6 + gn io_in[0] + gn io_in[1] + gn io_in[2] + gn io_in[3] + gn io_in[4] + gn io_in[5] + gn io_in[6] + gn io_in[7] + gn io_in[8] + gn io_in[9] + gn io_in[10] + gn io_in[11] + gn io_in[12] + gn io_in[13] + gn io_in[14] + gn io_in[15] + gn io_in[16] + gn io_in[17] + gn io_in[18] + gn io_in[19] + gn io_in[20] + gn io_in[21] + gn io_in[22] + gn io_in[23] + gn io_in[24] + gn io_in[25] + gn io_in[26] + gn io_in_3v3[0] + gn io_in_3v3[1] + gn io_in_3v3[2] + gn io_in_3v3[3] + gn io_in_3v3[4] + gn io_in_3v3[5] + gn io_in_3v3[6] + gn io_in_3v3[7] + gn io_in_3v3[8] + gn io_in_3v3[9] + gn io_in_3v3[10] + gn io_in_3v3[11] + gn io_in_3v3[12] + gn io_in_3v3[13] + gn io_in_3v3[14] + gn io_in_3v3[15] + gn io_in_3v3[16] + gn io_in_3v3[17] + gn io_in_3v3[18] + gn io_in_3v3[19] + gn io_in_3v3[20] + gn io_in_3v3[21] + gn io_in_3v3[22] + gn io_in_3v3[23] + gn io_in_3v3[24] + gn io_in_3v3[25] + gn io_in_3v3[26] + gn io_out[0] + gn io_out[1] + gn io_out[2] + gn io_out[3] + gn io_out[4] + gn io_out[5] + gn io_out[6] + gn io_out[7] + gn io_out[8] + gn io_out[9] + gn io_out[10] + gn io_out[11] + gn io_out[12] + gn io_out[13] + gn io_out[14] + gn io_out[15] + gn io_out[16] + gn io_out[17] + gn io_out[18] + gn io_out[19] + gn io_out[20] + gn io_out[21] + gn io_out[22] + gn io_out[23] + gn io_out[24] + gn io_out[25] + gn io_out[26] + gn io_oeb[0] + gn io_oeb[1] + gn io_oeb[2] + gn io_oeb[3] + gn io_oeb[4] + gn io_oeb[5] + gn io_oeb[6] + gn io_oeb[7] + gn io_oeb[8] + gn io_oeb[9] + gn io_oeb[10] + gn io_oeb[11] + gn io_oeb[12] + gn io_oeb[13] + gn io_oeb[14] + gn io_oeb[15] + gn io_oeb[16] + gn io_oeb[17] + gn io_oeb[18] + gn io_oeb[19] + gn io_oeb[20] + gn io_oeb[21] + gn io_oeb[22] + gn io_oeb[23] + gn io_oeb[24] + gn io_oeb[25] + gn io_oeb[26] + gn gpio_analog[0] + gn gpio_analog[1] + gn gpio_analog[2] + gn gpio_analog[3] + gn gpio_analog[4] + gn gpio_analog[5] + gn gpio_analog[6] + gn gpio_analog[7] + gn gpio_analog[8] + gn gpio_analog[9] + gn gpio_analog[10] + gn gpio_analog[11] + gn gpio_analog[12] + gn gpio_analog[13] + gn gpio_analog[14] + gn gpio_analog[15] + gn gpio_analog[16] + gn gpio_analog[17] + gn gpio_noesd[0] + gn gpio_noesd[1] + gn gpio_noesd[2] + gn gpio_noesd[3] + gn gpio_noesd[4] + gn gpio_noesd[5] + gn gpio_noesd[6] + gn gpio_noesd[7] + gn gpio_noesd[8] + gn gpio_noesd[9] + gn gpio_noesd[10] + gn gpio_noesd[11] + gn gpio_noesd[12] + gn gpio_noesd[13] + gn gpio_noesd[14] + gn gpio_noesd[15] + gn gpio_noesd[16] + gn gpio_noesd[17] + q + cvcin +elif [[ $DESIGN_NAME == *user_project_wrapper ]]; then + cat >$WORK_ROOT/cvc.oeb.script <<-cvcin + c 6 + gn io_in[0] + gn io_in[1] + gn io_in[2] + gn io_in[3] + gn io_in[4] + gn io_in[5] + gn io_in[6] + gn io_in[7] + gn io_in[8] + gn io_in[9] + gn io_in[10] + gn io_in[11] + gn io_in[12] + gn io_in[13] + gn io_in[14] + gn io_in[15] + gn io_in[16] + gn io_in[17] + gn io_in[18] + gn io_in[19] + gn io_in[20] + gn io_in[21] + gn io_in[22] + gn io_in[23] + gn io_in[24] + gn io_in[25] + gn io_in[26] + gn io_in[27] + gn io_in[28] + gn io_in[29] + gn io_in[30] + gn io_in[31] + gn io_in[32] + gn io_in[33] + gn io_in[34] + gn io_in[35] + gn io_in[36] + gn io_in[37] + gn io_out[0] + gn io_out[1] + gn io_out[2] + gn io_out[3] + gn io_out[4] + gn io_out[5] + gn io_out[6] + gn io_out[7] + gn io_out[8] + gn io_out[9] + gn io_out[10] + gn io_out[11] + gn io_out[12] + gn io_out[13] + gn io_out[14] + gn io_out[15] + gn io_out[16] + gn io_out[17] + gn io_out[18] + gn io_out[19] + gn io_out[20] + gn io_out[21] + gn io_out[22] + gn io_out[23] + gn io_out[24] + gn io_out[25] + gn io_out[26] + gn io_out[27] + gn io_out[28] + gn io_out[29] + gn io_out[30] + gn io_out[31] + gn io_out[32] + gn io_out[33] + gn io_out[34] + gn io_out[35] + gn io_out[36] + gn io_out[37] + gn io_oeb[0] + gn io_oeb[1] + gn io_oeb[2] + gn io_oeb[3] + gn io_oeb[4] + gn io_oeb[5] + gn io_oeb[6] + gn io_oeb[7] + gn io_oeb[8] + gn io_oeb[9] + gn io_oeb[10] + gn io_oeb[11] + gn io_oeb[12] + gn io_oeb[13] + gn io_oeb[14] + gn io_oeb[15] + gn io_oeb[16] + gn io_oeb[17] + gn io_oeb[18] + gn io_oeb[19] + gn io_oeb[20] + gn io_oeb[21] + gn io_oeb[22] + gn io_oeb[23] + gn io_oeb[24] + gn io_oeb[25] + gn io_oeb[26] + gn io_oeb[27] + gn io_oeb[28] + gn io_oeb[29] + gn io_oeb[30] + gn io_oeb[31] + gn io_oeb[32] + gn io_oeb[33] + gn io_oeb[34] + gn io_oeb[35] + gn io_oeb[36] + gn io_oeb[37] + gn io_in[0] + gn io_in[1] + gn io_in[2] + gn io_in[3] + gn io_in[4] + gn io_in[5] + gn io_in[6] + gn io_in[7] + gn io_in[8] + gn io_in[9] + gn io_in[10] + gn io_in[11] + gn io_in[12] + gn io_in[13] + gn io_in[14] + gn io_in[15] + gn io_in[16] + gn io_in[17] + gn io_in[18] + gn io_in[19] + gn io_in[20] + gn io_in[21] + gn io_in[22] + gn io_in[23] + gn io_in[24] + gn io_in[25] + gn io_in[26] + gn io_in[27] + gn io_in[28] + gn io_in[29] + gn io_in[30] + gn io_in[31] + gn io_in[32] + gn io_in[33] + gn io_in[34] + gn io_in[35] + gn io_in[36] + gn io_in[37] + gn analog_io[0] + gn analog_io[1] + gn analog_io[2] + gn analog_io[3] + gn analog_io[4] + gn analog_io[5] + gn analog_io[6] + gn analog_io[7] + gn analog_io[8] + gn analog_io[9] + gn analog_io[10] + gn analog_io[11] + gn analog_io[12] + gn analog_io[13] + gn analog_io[14] + gn analog_io[15] + gn analog_io[16] + gn analog_io[17] + gn analog_io[18] + gn analog_io[19] + gn analog_io[20] + gn analog_io[21] + gn analog_io[22] + gn analog_io[23] + gn analog_io[24] + gn analog_io[25] + gn analog_io[26] + gn analog_io[27] + gn analog_io[28] + q + cvcin +else + echo "ERROR: unrecognized top block $DESIGN_NAME" + exit 3 +fi + +start_time=$SECONDS +cvc_rv -i $WORK_ROOT/cvcrc.oeb <$WORK_ROOT/cvc.oeb.script + +cvc_status=$? + +runtime=$((SECONDS - start_time)) +hours=$((runtime / 3600)) +minutes=$(((runtime % 3600) / 60)) +seconds=$(((runtime % 3600) % 60)) +printf "Runtime: %d:%02d:%02d (hh:mm:ss)\n" $hours $minutes $seconds >>$WORK_ROOT/cvc.oeb.log + +if [[ $WORK_ROOT != $LOG_ROOT ]]; then + cp $WORK_ROOT/cvc.oeb.log $LOG_ROOT/. +fi + +awk ' + /^> gn io_in/ { + net = gensub(/.*\[([0-9]*)\]/, "\\1", 1); + getline; + getline; + in_connections[net] += $3 + $5 + $7; + } + /^> gn analog_io/ { + net = gensub(/.*\[([0-9]*)\]/, "\\1", 1); + getline; + getline; + analog_connections[net+7] += $3 + $5 + $7; + } + /^> gn gpio_analog/ || /^> gn gpio_noesd/ { + net = gensub(/.*\[([0-9]*)\]/, "\\1", 1); + getline; + getline; + analog_connections[net+7] += $3 + $5 + $7; + } + /^> gn io_out/ { + net = gensub(/.*\[([0-9]*)\]/, "\\1", 1); + getline; + getline; + out_connections[net] = $3 + $5 + $7; + # 2 blank lines mark the end of a segment + while ( NF > 0 ) { + if ( /^Min path/ ) { + while ( NF > 0 ) { + out_min[net] = $1; + getline; + } + } else if ( /^Sim path/ ) { + while ( NF > 0 ) { + out_sim[net] = $1; + getline; + } + } else if ( /^Max path/ ) { + while ( NF > 0 ) { + out_max[net] = $1; + getline; + } + } else { + while ( NF > 0 ) { + getline; + } + } + getline; + } + if ( out_min[net] == out_sim[net] && out_sim[net] == out_max[net] ) { + fixed[net] = out_sim[net]; + } + } + /^> gn io_oeb/ { + net = gensub(/.*\[([0-9]*)\]/, "\\1", 1); + getline; + getline; + oeb_connections[net] = $3 + $5 + $7; + # 2 blank lines mark the end of a segment + while ( NF > 0 ) { + if ( /^Min path/ ) { + while ( NF > 0 ) { + oeb_min[net] = $1; + getline; + } + } else if ( /^Sim path/ ) { + while ( NF > 0 ) { + oeb_sim[net] = $1; + getline; + } + } else if ( /^Max path/ ) { + while ( NF > 0 ) { + oeb_max[net] = $1; + getline; + } + } else { + while ( NF > 0 ) { + getline; + } + } + getline; + } + } + END { + #print "oeb connections:", length(oeb_connections); + print " gpio | in | out | analog | oeb min/sim/max | Message"; + #" xx | xxxxxx | xxxxxx | xxxxxx | vxxx*/vxxx*/vxxx* | + for ( i in oeb_connections ) { + printf " %2d | %6s | %6s | %6s | %5s/%5s/%5s | ", \ + i, (in_connections[i] == 0) ? "" : sprintf("%6d", in_connections[i]), \ + (out_connections[i] == 0) ? "" : + (i in fixed) ? fixed[i] : sprintf("%6d", out_connections[i]), \ + (analog_connections[i] == 0) ? "" : sprintf("%6d", analog_connections[i]), \ + oeb_min[i], oeb_sim[i], oeb_max[i]; + if ( analog_connections[i] > 0 ) { + if ( in_connections[i] > 0 || (out_connections[i] > 0 && ! (i in fixed)) ) { # both digital and analog + printf "Warning: both analog and digital connections"; + } else if ( ! ( oeb_sim[i] ~ /vccd/ || oeb_sim[i] ~ /vdd/ ) ) { # analog signals should disable output + printf "Warning: oeb expected high for analog"; + } + } else if ( in_connections[i] > 0 && out_connections[i] == 0 ) { + if ( ! ( oeb_sim[i] ~ /vccd/ || oeb_sim[i] ~ /vdd/ ) ) { # input only signals should never enable output + printf "Warning: oeb expected high for input only"; + } + } else if ( out_connections[i] > 0 && ! (i in fixed) ) { + if ( oeb_min[i] !~ /vss/ ) { # output signals must be enable-able + printf "ERROR: oeb must have possible low for output"; + } else if ( in_connections[i] > 0 && oeb_sim[i] ~ /vss/ ) { # input is always driven by user output in user mode + printf "Warning: output always drives input. sky130: OK for pull up/down."; + } + } + printf "\n"; + } + }' $LOG_ROOT/cvc.oeb.log | + tee $WORK_ROOT/cvc.oeb.report + +if [[ $WORK_ROOT != $SIGNOFF_ROOT ]]; then + cp $WORK_ROOT/cvc.oeb.report $SIGNOFF_ROOT/cvc.oeb.report +fi + +if [[ $cvc_status -eq 0 && $(grep -c '^CVC: End:' $LOG_ROOT/cvc.oeb.log) -ne 1 ]]; then + # CVC finished abnormally + exit 4 + +elif [[ $cvc_status -eq 0 && $(grep -c ERROR $SIGNOFF_ROOT/cvc.oeb.report) -gt 0 ]]; then + # CVC finished normally, but detected errors + exit 5 + +elif [[ $cvc_status -eq 0 && $(grep -c Warning $SIGNOFF_ROOT/cvc.oeb.report) -gt 0 ]]; then + # CVC finished normally, but detected warings + exit 6 + +else + exit $cvc_status +fi diff --git a/scripts/be_checks/run_scheck b/scripts/be_checks/run_scheck new file mode 100755 index 00000000..1bd11af1 --- /dev/null +++ b/scripts/be_checks/run_scheck @@ -0,0 +1,206 @@ +#! /bin/bash +# run_scheck: Detect well only connections in GDS file. + +# Copyright 2022 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Overview: +# 1. Extract gds_file with well connectivity. +# 2. Remove well connections and disconnected nets. +# 3. Extract gds_file without well connectivity. +# 4. Remove disconnected nets. +# 5. Compare +# + + +# Use cases +# run_scheck [--noextract] [lvs_config_file [top_block [gds_file]]] + +if [[ $1 == "--noextract" ]]; then + export EXTRACT_LAYOUT=no + shift +else + export EXTRACT_LAYOUT=yes +fi + +if [[ $# -gt 3 ]]; then + echo "usage: run_scheck [--noextract] [lvs_config_file [top_block [gds_file]]]" + exit 1 +fi + +echo " " +echo "Running soft connection check on layout..." + +# Check for PDK_ROOT and PDK +if [[ -z "$PDK_ROOT" || -z "$PDK" ]]; then + echo "PDK_ROOT and/or PDK not set." + exit 1 +fi + +# Check for LVS_ROOT +if [[ -z "$LVS_ROOT" ]]; then + echo "LVS_ROOT not set." + exit 1 +fi + +if cmp -s $PDK_ROOT/$PDK/libs.tech/magic/$PDK.tech $LVS_ROOT/tech/$PDK/$PDK.tech; then + awk 'NF > 1 && /version/' $LVS_ROOT/tech/$PDK/$PDK.tech +else + echo "WARNING: Tech files do not match:" + grep version $PDK_ROOT/$PDK/libs.tech/magic/$PDK.tech $LVS_ROOT/tech/$PDK/$PDK.tech | + awk 'NF > 2 && ! /^ *#/' + echo "Results may be incorrect. Contact efabless to update the soft connection rules." + #exit 1 +fi + +CONFIG_FILE=$1 +DESIGN_NAME=${2:+"-d $2"} + +if [[ $# -ne 0 ]]; then # if config file not specified, skip and use current environment + source <($LVS_ROOT/set_lvs_env.py -c $CONFIG_FILE $DESIGN_NAME) +fi +if [[ ! -v EXTRACT_FLATGLOB ]]; then + echo "ERROR: LVS environment problem." + exit 1 +fi + +export TOP=${2:-$TOP_LAYOUT} +export LAYOUT_FILE=${3:-$LAYOUT_FILE} +if [[ $EXTRACT_LAYOUT == no ]]; then + export LAYOUT_FILE= +fi + +echo "WORK_ROOT : ${WORK_ROOT:=$(pwd)/$TOP}" +echo "LOG_ROOT : ${LOG_ROOT:=$WORK_ROOT}" +echo "SIGNOFF_ROOT: ${SIGNOFF_ROOT:=$WORK_ROOT}" +export LOG_ROOT SIGNOFF_ROOT WORK_ROOT + +echo "TOP: $TOP" +echo "LAYOUT: $LAYOUT_FILE" +echo "EXTRACT_FLATGLOB: $(echo $EXTRACT_FLATGLOB | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" +echo "EXTRACT_ABSTRACT: $(echo $EXTRACT_ABSTRACT | sed -e 's/#[^ ]*//g' -e 's/ /\n /g')" + +mkdir -p $LOG_ROOT +mkdir -p $WORK_ROOT +mkdir -p $SIGNOFF_ROOT + +rm -f $LOG_ROOT/soft.log $SIGNOFF_ROOT/soft.report +echo $EXTRACT_FLATGLOB | + sed 's/ */\n/g' >$WORK_ROOT/flatglob +echo $EXTRACT_ABSTRACT | + sed 's/ */\n/g' >$WORK_ROOT/abstract +if [[ -f $WORK_ROOT/layout.cells ]]; then + sed -e 's/\*/.*/g' -e 's/^/^/' -e 's/$/$/' $WORK_ROOT/abstract | + grep -f - $WORK_ROOT/layout.cells >$WORK_ROOT/abstract.glob +else + cp $WORK_ROOT/abstract $WORK_ROOT/abstract.glob +fi + +# Add any cells that should be flattened before extraction to 'flatten'. globbing allowed. +export FLATGLOB_CELLS="$(cat $WORK_ROOT/flatglob 2>/dev/null | grep -v '^#')" +# Add any empty cells that should be extracted as black-boxes to 'abstract'. +export ABSTRACT_CELLS="$(cat $WORK_ROOT/abstract.glob 2>/dev/null | grep -v '^#')" + +# Verify that netgen is executable. +if ! which netgen >&/dev/null; then + echo "Error: Could not execute netgen." + exit 1 +fi + +if [[ $EXTRACT_LAYOUT == yes ]]; then + rm -f $LOG_ROOT/ext.log + # Extract gds_file. + + export EXT_DIR=$WORK_ROOT/ext + echo "Extracting layout with well in background process. See $WORK_ROOT/ext.log." + ( + # 1. Extract gds_file with well connectivity + env CIFIN_STYLE="" EXTRACT_STYLE="" LOG_FILE=ext.log $LVS_ROOT/run_extract >$WORK_ROOT/ext.out 2>&1 + # 2. Remove well connections and disconnected nets. + sed -f $LVS_ROOT/tech/$PDK/remove_well.sed $EXT_DIR/$TOP.gds.spice | + awk -f $LVS_ROOT/scripts/remove_disconnect.awk - >$EXT_DIR/$TOP.gds.nowell.spice + ) & + + export EXT_DIR=$WORK_ROOT/nowell.ext + echo "Extracting layout without well in background process. See $WORK_ROOT/nowell.ext.log." + ( + # 3. Extract gds_file without well connectivity + env CIFIN_STYLE="nowell" EXTRACT_STYLE="nowell" LOG_FILE=nowell.ext.log $LVS_ROOT/run_extract >$WORK_ROOT/nowell.ext.out 2>&1 + # 4. Remove disconnected nets. + awk -f $LVS_ROOT/scripts/remove_disconnect.awk $EXT_DIR/$TOP.gds.spice >$EXT_DIR/$TOP.gds.nowell.spice + ) & + + wait + + if [[ $(cat $LOG_ROOT/ext.log $LOG_ROOT/nowell.ext.log | grep -c 'exttospice finished' ) -ne 2 ]]; then + echo "Extraction error: see $LOG_ROOT/ext.log +and/or $LOG_ROOT/nowell.ext.log" + exit 2 + fi +else + # No gds_file so LVS only. Check for existing valid extraction results. + if [[ ! -f $WORK_ROOT/ext/$TOP.gds.nowell.spice ]]; then + echo "Error: missing $WORK_ROOT/ext/$TOP.gds.nowell.spice" + echo "Specify gds_file to create" + echo "usage: run_scheck top_block [gds_file]" + exit 2 + fi + if [[ ! -f $WORK_ROOT/nowell.ext/$TOP.gds.nowell.spice ]]; then + echo "Error: missing $WORK_ROOT/nowell.ext/$TOP.gds.nowell.spice" + echo "Specify gds_file to create" + echo "usage: run_scheck top_block [gds_file]" + exit 2 + fi + if [[ $(grep -c 'exttospice finished.' $LOG_ROOT/ext.log) -ne 1 ]]; then + echo " +Error: extraction did not complete successfully. See +$LOG_ROOT/ext.log" + exit 4 + fi + if [[ $(grep -c 'exttospice finished.' $LOG_ROOT/nowell.ext.log) -ne 1 ]]; then + echo " +Error: extraction did not complete successfully. See +$LOG_ROOT/nowell.ext.log" + exit 4 + fi +fi + +# 5. Compare +rm -f $LOG_ROOT/soft.log +date "+BEGIN: %c" >$WORK_ROOT/soft.log +start_time=$SECONDS +: "${NETGEN_COLUMNS:=80}" +export NETGEN_COLUMNS +netgen -batch source $LVS_ROOT/tech/soft.lvs.script | + tee -a $WORK_ROOT/soft.log 2>&1 +scheck_status=${PIPESTATUS[0]} +if [[ $scheck_status -ne 0 || $(tail $WORK_ROOT/soft.report | grep -c 'Circuits match uniquely\.') -ne 1 ]]; then + echo "scheck status $scheck_status" + scheck_status=3 +fi + +date "+END: %c" >>$WORK_ROOT/soft.log +runtime=$((SECONDS - start_time)) +hours=$((runtime / 3600)) +minutes=$(((runtime % 3600) / 60)) +seconds=$(((runtime % 3600) % 60)) +printf "Runtime: %d:%02d:%02d (hh:mm:ss)\n" $hours $minutes $seconds >>$WORK_ROOT/soft.log +if [[ $WORK_ROOT != $LOG_ROOT ]]; then + cp $WORK_ROOT/soft.log $LOG_ROOT/. +fi +if [[ $WORK_ROOT != $SIGNOFF_ROOT ]]; then + cp $WORK_ROOT/soft.report $SIGNOFF_ROOT/. +fi + +exit $scheck_status diff --git a/scripts/be_checks/scripts/ext.hier.awk b/scripts/be_checks/scripts/ext.hier.awk new file mode 100644 index 00000000..f3988cdf --- /dev/null +++ b/scripts/be_checks/scripts/ext.hier.awk @@ -0,0 +1,25 @@ +BEGIN { + top = TOP; +} +FILENAME != last_file { + split(FILENAME, path, "/"); + sub(/.ext$/, "", path[length(path)]); + subckt = path[length(path)]; + last_file = FILENAME; +} +/^use / { + subcells[subckt, $2] += 1; +} +END { + print top; + PrintHierarchy(top, ""); +} +function PrintHierarchy(subckt, prefix) { + for ( instance in subcells ) { + split(instance, tokens, SUBSEP); + if ( tokens[1] == subckt ) { + print prefix, tokens[2], subcells[instance]; + PrintHierarchy(tokens[2], prefix " "); + } + } +} diff --git a/scripts/be_checks/scripts/remove_disconnect.awk b/scripts/be_checks/scripts/remove_disconnect.awk new file mode 100644 index 00000000..0a754544 --- /dev/null +++ b/scripts/be_checks/scripts/remove_disconnect.awk @@ -0,0 +1,202 @@ +# remove_disconnect.awk: Recursively removes disconnected ports from a spice file + +# Copyright 2022 D. Mitch Bailey cvc at shuharisystem dot com + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# port_lines: all the port lines for the current subckt +# instance_lines: all the lines for the current instance +# device_lines: all the lines for all instances in the current subckt + +# Dictionaries +# port_order: maps 'port' to port_order for current subckt +# connections: maps 'subckt "&" port_order' to number of connections + +BEGIN { + # initialize autoincrement arrays + delete port_lines[0] + delete device_lines[0] + delete instance_lines[0] +} + +/^\+/ { + # continuation line: either a port or an instance + if ( continuation_type == "port" ) { + ReadPorts(subckt, 2); + } else { + instance_lines[length(instance_lines)+1] = $0; + # the parent is always the last field of the instance, + # update for each continuation line. + parent = $NF; + } + next; +} + +/^.subckt/ || /^.SUBCKT/ { + # subckt definition; start reading ports + continuation_type = "port"; + subckt = $2; + port_count = 0; + ReadPorts(subckt, 3); + next; +} + +/^[CcDdMmRrXx]/ { + # instance definition; start reading instance + if ( length(instance_lines) > 0 ) { + # copy previous instance lines to device lines + # after removing disconnected ports + SaveInstance(subckt, parent); + } + continuation_type = "device"; + instance_lines[length(instance_lines)+1] = $0; + # the parent is always the last field of the instance + parent = $NF; + next; +} + +/^.ends/ || /^.ENDS/ { + # end of subckt; print out used ports and updated instances + if ( length(instance_lines) > 0 ) { + # copy previous instance lines to device lines + # after removing disconnected ports + SaveInstance(subckt, parent); + } + # save the current line + current = $0; + # print the port lines after removing disconnected ports + port_count = 0; + for (port_line_it = 1; port_line_it <= length(port_lines); port_line_it++ ) { + # automatic parsing with $0 = ... + $0 = port_lines[port_line_it]; + if ( port_line_it == 1 ) { + RemoveDisconnectedPorts(subckt, 3); + } else { + RemoveDisconnectedPorts(subckt, 2); + } + # only print lines that have ports remaining + if ( ! /^\+ *$/ ) { + print $0; + } + } + # print device lines + for (device_line_it = 1; device_line_it <= length(device_lines); device_line_it++ ) { + print device_lines[device_line_it]; + } + print current; + delete port_order; + delete port_lines; + delete port_lines[0]; # reinitialize array + delete device_lines; + delete device_lines[0]; # reinitialize array + next; +} + + { + # print any other lines: comments and spaces. + # does not preserve order of lines within a subckt. + print $0; +} + + +function SaveInstance(subckt, parent) { + # SaveInstance: copy instance_lines to device_lines after removing nets + # when the corresponding parent port is disconnected + # Inputs: + # subckt: the current subckt name + # parent: the parent subckt name for this instance + # Modifies: + # connections: adds the number of connections to each of the current subckt ports + # device_lines: appends the modified instance_lines + # instance_lines: resets after processing + net_number = 0; + used_count = 0; + # save the current line + current = $0; + verified_count = length(device_lines); + for (instance_line_it = 1; instance_line_it <= length(instance_lines); instance_line_it++ ) { + # automatic parsing with $0 = ... + $0 = instance_lines[instance_line_it]; + # first field is either instance name or '+' so skip it + for (net_it = 2; net_it <= NF; net_it++) { + net_number += 1; + connection_key = parent "&" net_number; + if ( connection_key in connections && connections[connection_key] == 0 ) { + # if the parent port is unused, removed it + $net_it = ""; + } else if ( $net_it != parent ) { + used_count += 1; + if ( $net_it in port_order ) { + # if this net is a port, count it + connections[subckt "&" port_order[$net_it]] += 1; + } + } + } + ## ignore one line instances that have all ports removed + #if ( length(instance_lines) == 1 && used_count == 0 ) { + #continue; + #} + # only keep lines that have nets remaining + if ( ! /^\+ *$/ ) { + device_lines[length(device_lines)+1] = $0; + } + } + if ( used_count == 0 ) { + # Remove instances that have all ports removed + while ( length(device_lines) > verified_count ) { + delete device_lines[length(device_lines)]; + } + } + delete instance_lines; + delete instance_lines[0]; # reinitialize array + # restore the current line + $0 = current; +} + + +function ReadPorts(subckt, start) { + # ReadPorts: sets port_order for each port and initializes connection count + # Inputs: + # start: index of first port field on current line + # subckt: the current subckt name + # Modifies: + # port_lines: saves current line + # port_count: increments for each port + # port_order: sets port order for each port + # connections: initializes connection count for each port in subckt + port_lines[length(port_lines)+1] = $0; + for (port_it = start; port_it <= NF; port_it++ ) { + port_count += 1; + port_order[$port_it] = port_count; + connections[subckt "&" port_count] = 0; + } +} + + +function RemoveDisconnectedPorts(subckt, start) { + # RemoveDisconnectedPorts: removes disconnected ports from current line + # Inputs: + # start: index of first port field on current line + # subckt: the current subckt name + # Modifies: + # port_count: increments for each port + # current line: removes unused ports + for ( port_it = start; port_it <= NF; port_it++ ) { + port_count += 1; + connection_key = subckt "&" port_count; + if ( connection_key in connections && connections[connection_key] == 0 ) { + # if the port is unused, removed it + $port_it = ""; + } + } +} diff --git a/scripts/be_checks/set_lvs_env.py b/scripts/be_checks/set_lvs_env.py new file mode 100755 index 00000000..15ba30e3 --- /dev/null +++ b/scripts/be_checks/set_lvs_env.py @@ -0,0 +1,138 @@ +#! /usr/bin/env python3 + +""" +Create environment variables from a hierarchy of configuration files. + +Return codes: +0: no error +2: file not found +3: invalid json +4. could not substitute environment variable +""" + +import argparse +import logging +import subprocess +import os +import pprint +import sys +from pathlib import Path +from datetime import datetime +import json +import re + +lvs_vars = [ + 'TOP_SOURCE', + 'TOP_LAYOUT', + 'LAYOUT_FILE', + 'EXTRACT_FLATGLOB', + 'EXTRACT_ABSTRACT', + 'EXTRACT_CREATE_SUBCUT', + 'EXTRACT_TYPE', + 'LVS_FLATTEN', + 'LVS_NOFLATTEN', + 'LVS_IGNORE', + 'LVS_SPICE_FILES_TO_FIX', + 'LVS_SPICE_FILES', + 'LVS_VERILOG_FILES' +] + + +def substitute_env_variables(input_string, env): + """ Return the string after replacing all environment variables ($varname) with the corresponding values from the environment. + + Only handles simple variables $[A-Za-z0-9_]*. Does not handle ${varname}, $$, etc. + Missing variables are fatal errors. + """ + string = input_string + if "$" in string: + words = re.findall(r'\$\w+', string) # returns a list of all environment variables used. + for w in words: + env_var = w[1:] # remove leading '$' + if env_var in env: + string = string.replace(w, env.get(env_var), 1) # only replace first occurence. Others will be replaced later. + else: + print(f"ERROR: couldn't find environment variable {w} used in {input_string}", file=sys.stderr) + sys.exit(4) + + return string + + +def parse_config_file(json_file, lvs_env): + """ Parses a json file which may reference other json files and uses the values to set environment variables. + + List values are accumulated while scalar values are overwritten when processing sub files. + Duplicate list values are silently ignored. + json syntax errors are fatal errors. + """ + if not os.path.exists(f"{json_file}"): + print(f"ERROR: Could not find configuration file {json_file}", file=sys.stderr) + sys.exit(2) + + print(f"Loading LVS environment from {json_file}", file=sys.stderr) + try: + with open(json_file, "r") as f: + data = json.load(f) + for key, value in data.items(): + if type(value) == list: + exports = lvs_env[key].split() if key in lvs_env else [] # current environment list values + for val in value: + val = substitute_env_variables(val, lvs_env) + if val not in exports: # only add if not already in list + exports.append(val) + if key == 'INCLUDE_CONFIGS': # load child configs + lvs_env['INCLUDE_CONFIGS'] += " " + val # prevents loading same config twice + parse_config_file(val, lvs_env) + if key != 'INCLUDE_CONFIGS': # the value of the INCLUDE_CONFIGS key is already updated before the recursive call. + lvs_env[key] = ' '.join(exports) + else: # value is not a list. new value overrides any previous value. + value = substitute_env_variables(value, lvs_env) + lvs_env[key] = value + except Exception as err: + print(type(err), file=sys.stderr) + print(err.args, file=sys.stderr) + print(f"ERROR: with file {json_file}", file=sys.stderr) + sys.exit(3) + + +def clear_env(env, keys): + """ Clear any previous setting for keys in the environment. + """ + for key in keys: + if key in env: + del env[key] + print(f"unset {key}") + + +def print_env(env, keys): + """ Print assignment statements for keys in env. + """ + for key in keys: + if key in env: + print(f"export {key}='{env[key]}'") + #pprint.pprint({key: env[key]}, stream=sys.stderr) + else: + print(f"export {key}=") + #pprint.pprint({key: ''}, stream=sys.stderr) + + +def set_lvs_env(config_file, design_name): + """ Print a list of shell export commands to set LVS variables. + + Any errors are fatal. + """ + lvs_env = os.environ.copy() + clear_env(lvs_env, lvs_vars) + lvs_env['INCLUDE_CONFIGS'] = f"{config_file}" + lvs_env['DESIGN_NAME'] = design_name + parse_config_file(config_file, lvs_env) + print_env(lvs_env, lvs_vars) + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='Creates the LVS environment') + parser.add_argument('--config_file', '-c', required=True, help='LVS config file') + parser.add_argument('--design_name', '-d', required=False, help='Top source override') + args = parser.parse_args() + config_file = Path(args.config_file) + set_lvs_env(config_file, args.design_name) diff --git a/scripts/be_checks/tech/magicrc b/scripts/be_checks/tech/magicrc new file mode 100644 index 00000000..a3201318 --- /dev/null +++ b/scripts/be_checks/tech/magicrc @@ -0,0 +1,69 @@ +puts stdout "Sourcing design magicrc.well for technology $::env(PDK) ..." + +# Put internal grid on 0.005 pitch. This is important to match vendor file +# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um). + +set scalefac [tech lambda] + +if {[string first sky130 $::env(PDK)] >= 0} { + if {[lindex $scalefac 1] < 2} { + scalegrid 1 2 + } + # set sky130 standard power, ground, and substrate names + set VDD VPWR + set GND VGND + set SUB VSUBS + +} elseif {[string first gf180mcu $::env(PDK)] >= 0} { + if {[lindex $scalefac 1] < 10} { + scalegrid 1 10 + } + # set gf180mcu standard power, ground, and substrate names + set VDD VDD + set GND VSS + set SUB VSUBS + +} else { + puts "ERROR: Unknown PDK - $::env(PDK)" +} + +drc off +drc euclidean on +see no * +# Change this to a fixed number for repeatable behavior with GDS writes +# e.g., "random seed 12345" +catch {random seed} + +tech load $::env(LVS_ROOT)/tech/$::env(PDK)/$::env(PDK).tech + +# set units to lambda grid +snap lambda + +# BE-EDIT: BE checks work on gds. do not want to load from libraries. + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +#if {[catch {set MAGTYPE $env(MAGTYPE)}]} { +# set MAGTYPE mag +#} +# +## add path to reference cells +#if {[file isdir ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}]} { +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_fd_pr +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0 +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0 +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_fd_io +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram +#} else { +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_pr/${MAGTYPE} +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE} +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE} +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_io/${MAGTYPE} +# addpath ${PDK_ROOT}/gf180mcuC/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE} +#} +# +## add path to IP from catalog. This procedure defined in the PDK script. +#catch {magic::query_mylib_ip} +## add path to local IP from user design space. Defined in the PDK script. +#catch {magic::query_my_projects} diff --git a/scripts/be_checks/tech/sky130A/caravan_core.v.sed b/scripts/be_checks/tech/sky130A/caravan_core.v.sed new file mode 100644 index 00000000..da53f7f7 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/caravan_core.v.sed @@ -0,0 +1,42 @@ +s/.gpio_control_bidir_1.0..gpio_defaults/gpio_defaults[0]/g +s/.gpio_control_bidir_1.1..gpio_defaults/gpio_defaults[1]/g +s/.gpio_control_in_1.2..gpio_defaults/gpio_defaults[10]/g +s/.gpio_control_in_1.3..gpio_defaults/gpio_defaults[11]/g +s/.gpio_control_in_1.4..gpio_defaults/gpio_defaults[12]/g +s/.gpio_control_in_1.5..gpio_defaults/gpio_defaults[13]/g +s/.gpio_control_in_1a.0..gpio_defaults/gpio_defaults[2]/g +s/.gpio_control_in_2.0..gpio_defaults/gpio_defaults[25]/g +s/.gpio_control_in_2.1..gpio_defaults/gpio_defaults[26]/g +s/.gpio_control_in_2.2..gpio_defaults/gpio_defaults[27]/g +s/.gpio_control_in_2.3..gpio_defaults/gpio_defaults[28]/g +s/.gpio_control_in_2.4..gpio_defaults/gpio_defaults[29]/g +s/.gpio_control_in_1a.1..gpio_defaults/gpio_defaults[3]/g +s/.gpio_control_in_2.5..gpio_defaults/gpio_defaults[30]/g +s/.gpio_control_in_2.6..gpio_defaults/gpio_defaults[31]/g +s/.gpio_control_in_2.7..gpio_defaults/gpio_defaults[32]/g +s/.gpio_control_in_2.8..gpio_defaults/gpio_defaults[33]/g +s/.gpio_control_in_2.9..gpio_defaults/gpio_defaults[34]/g +s/.gpio_control_bidir_2.0..gpio_defaults/gpio_defaults[35]/g +s/.gpio_control_bidir_2.1..gpio_defaults/gpio_defaults[36]/g +s/.gpio_control_bidir_2.2..gpio_defaults/gpio_defaults[37]/g +s/.gpio_control_in_1a.2..gpio_defaults/gpio_defaults[4]/g +s/.gpio_control_in_1a.3..gpio_defaults/gpio_defaults[5]/g +s/.gpio_control_in_1a.4..gpio_defaults/gpio_defaults[6]/g +s/.gpio_control_in_1a.5..gpio_defaults/gpio_defaults[7]/g +s/.gpio_control_in_1.0..gpio_defaults/gpio_defaults[8]/g +s/.gpio_control_in_1.1..gpio_defaults/gpio_defaults[9]/g +s/\\mask_rev/mask_rev/g +/wire mask_rev/d +/wire gpio_defaults/d +s/^ user_gpio_noesd);/ user_gpio_noesd,\ + gpio_defaults_out,\ + mask_rev);/ +s/^ inout .17:0. user_gpio_noesd;/ inout [17:0] user_gpio_noesd;\ + output [38*13-1:0] gpio_defaults_out;\ + output [31:0] mask_rev;\ +\ + wire [12:0] gpio_defaults [37:0];\ + genvar i;\ + generate for (i = 0; i < 38; i = i+1) begin:instgpio\ + assign gpio_defaults_out[13*i +: 13] = gpio_defaults[i];\ + end endgenerate/ diff --git a/scripts/be_checks/tech/sky130A/caravan_gpio_test.v b/scripts/be_checks/tech/sky130A/caravan_gpio_test.v new file mode 100644 index 00000000..6379a15d --- /dev/null +++ b/scripts/be_checks/tech/sky130A/caravan_gpio_test.v @@ -0,0 +1,173 @@ +module gpio_test; + + wire clock_core; + wire flash_clk_frame; + wire flash_clk_oeb; + wire flash_csb_frame; + wire flash_csb_oeb; + wire flash_io0_di; + wire flash_io0_do; + wire flash_io0_ieb; + wire flash_io0_oeb; + wire flash_io1_di; + wire flash_io1_do; + wire flash_io1_ieb; + wire flash_io1_oeb; + wire gpio_in_core; + wire gpio_inenb_core; + wire gpio_mode0_core; + wire gpio_mode1_core; + wire gpio_out_core; + wire gpio_outenb_core; + wire por_l; + wire porb_h; + wire rstb_h; + wire vccd; + wire vssd; + wire vccd1; + wire vssd1; + wire vssd2; + wire vccd2; + wire vssa1; + wire vdda2; + wire vssa2; + wire vdda1; + wire vddio; + wire vssio; + wire [26:0] mprj_io_analog_en; + wire [26:0] mprj_io_analog_pol; + wire [26:0] mprj_io_analog_sel; + wire [80:0] mprj_io_dm; + wire [26:0] mprj_io_holdover; + wire [26:0] mprj_io_ib_mode_sel; + wire [26:0] mprj_io_in; + wire [26:0] mprj_io_in_3v3; + wire [26:0] mprj_io_inp_dis; + wire [26:0] mprj_io_oeb; + wire [26:0] mprj_io_one; + wire [26:0] mprj_io_out; + wire [26:0] mprj_io_slow_sel; + wire [26:0] mprj_io_vtrip_sel; + wire [10:0] user_analog; + wire [2:0] user_clamp_high; + wire [2:0] user_clamp_low; + wire [17:0] user_gpio_analog; + wire [17:0] user_gpio_noesd; + + wire [38*13-1:0] all_gpio_defaults; + + wire [12:0] gpio_defaults [37:0]; + wire [31:0] mask_rev; + + assign vccd = 1; + assign vssd = 0; + + genvar i; + generate for (i = 0; i < 38; i = i+1) begin:instgpio + assign gpio_defaults[i] = all_gpio_defaults[13*i +: 13]; + end endgenerate + + caravan_core chip_core ( + .clock_core(clock_core), + .flash_clk_frame(flash_clk_frame), + .flash_clk_oeb(flash_clk_oeb), + .flash_csb_frame(flash_csb_frame), + .flash_csb_oeb(flash_csb_oeb), + .flash_io0_di(flash_io0_di), + .flash_io0_do(flash_io0_do), + .flash_io0_ieb(flash_io0_ieb), + .flash_io0_oeb(flash_io0_oeb), + .flash_io1_di(flash_io1_di), + .flash_io1_do(flash_io1_do), + .flash_io1_ieb(flash_io1_ieb), + .flash_io1_oeb(flash_io1_oeb), + .gpio_in_core(gpio_in_core), + .gpio_inenb_core(gpio_inenb_core), + .gpio_mode0_core(gpio_mode0_core), + .gpio_mode1_core(gpio_mode1_core), + .gpio_out_core(gpio_out_core), + .gpio_outenb_core(gpio_outenb_core), + .mprj_io_analog_en(mprj_io_analog_en), + .mprj_io_analog_pol(mprj_io_analog_pol), + .mprj_io_analog_sel(mprj_io_analog_sel), + .mprj_io_dm(mprj_io_dm), + .mprj_io_holdover(mprj_io_holdover), + .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel), + .mprj_io_in(mprj_io_in), + .mprj_io_in_3v3(mprj_io_in_3v3), + .mprj_io_inp_dis(mprj_io_inp_dis), + .mprj_io_oeb(mprj_io_oeb ), + .mprj_io_one(mprj_io_one ), + .mprj_io_out(mprj_io_out ), + .mprj_io_slow_sel(mprj_io_slow_sel ), + .mprj_io_vtrip_sel(mprj_io_vtrip_sel ), + .por_l(por_l), + .porb_h(porb_h), + .rstb_h(rstb_h), + .user_analog(user_analog ), + .user_clamp_high(user_clamp_high ), + .user_clamp_low(user_clamp_low ), + .user_gpio_analog(user_gpio_analog ), + .user_gpio_noesd(user_gpio_noesd ), + .vccd(vccd), + .vccd1(vccd1), + .vccd2(vccd2), + .vdda1(vdda1), + .vdda2(vdda2), + .vddio(vddio), + .vssa1(vssa1), + .vssa2(vssa2), + .vssd(vssd), + .vssd1(vssd1), + .vssd2(vssd2), + .vssio(vssio), + .gpio_defaults_out(all_gpio_defaults), + .mask_rev(mask_rev) + ); + +initial begin + #10 $monitor("Actual"); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 0, gpio_defaults[0]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 1, gpio_defaults[1]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 2, gpio_defaults[2]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 3, gpio_defaults[3]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 4, gpio_defaults[4]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 5, gpio_defaults[5]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 6, gpio_defaults[6]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 7, gpio_defaults[7]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 8, gpio_defaults[8]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 9, gpio_defaults[9]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 10, gpio_defaults[10]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 11, gpio_defaults[11]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 12, gpio_defaults[12]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 13, gpio_defaults[13]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 14, gpio_defaults[14]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 15, gpio_defaults[15]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 16, gpio_defaults[16]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 17, gpio_defaults[17]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 18, gpio_defaults[18]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 19, gpio_defaults[19]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 20, gpio_defaults[20]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 21, gpio_defaults[21]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 22, gpio_defaults[22]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 23, gpio_defaults[23]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 24, gpio_defaults[24]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 25, gpio_defaults[25]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 26, gpio_defaults[26]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 27, gpio_defaults[27]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 28, gpio_defaults[28]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 29, gpio_defaults[29]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 30, gpio_defaults[30]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 31, gpio_defaults[31]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 32, gpio_defaults[32]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 33, gpio_defaults[33]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 34, gpio_defaults[34]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 35, gpio_defaults[35]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 36, gpio_defaults[36]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 37, gpio_defaults[37]); + #10 $monitor("Setting Project Chip ID to: %h", mask_rev); + #100 $stop; +end + +endmodule // gpio_test + diff --git a/scripts/be_checks/tech/sky130A/caravel_core.v.sed b/scripts/be_checks/tech/sky130A/caravel_core.v.sed new file mode 100644 index 00000000..050312b5 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/caravel_core.v.sed @@ -0,0 +1,53 @@ +s/.gpio_control_bidir_1.0..gpio_defaults/gpio_defaults[0]/g +s/.gpio_control_bidir_1.1..gpio_defaults/gpio_defaults[1]/g +s/.gpio_control_in_1.2..gpio_defaults/gpio_defaults[10]/g +s/.gpio_control_in_1.3..gpio_defaults/gpio_defaults[11]/g +s/.gpio_control_in_1.4..gpio_defaults/gpio_defaults[12]/g +s/.gpio_control_in_1.5..gpio_defaults/gpio_defaults[13]/g +s/.gpio_control_in_1.6..gpio_defaults/gpio_defaults[14]/g +s/.gpio_control_in_1.7..gpio_defaults/gpio_defaults[15]/g +s/.gpio_control_in_1.8..gpio_defaults/gpio_defaults[16]/g +s/.gpio_control_in_1.9..gpio_defaults/gpio_defaults[17]/g +s/.gpio_control_in_1.10..gpio_defaults/gpio_defaults[18]/g +s/.gpio_control_in_2.0..gpio_defaults/gpio_defaults[19]/g +s/.gpio_control_in_1a.0..gpio_defaults/gpio_defaults[2]/g +s/.gpio_control_in_2.1..gpio_defaults/gpio_defaults[20]/g +s/.gpio_control_in_2.2..gpio_defaults/gpio_defaults[21]/g +s/.gpio_control_in_2.3..gpio_defaults/gpio_defaults[22]/g +s/.gpio_control_in_2.4..gpio_defaults/gpio_defaults[23]/g +s/.gpio_control_in_2.5..gpio_defaults/gpio_defaults[24]/g +s/.gpio_control_in_2.6..gpio_defaults/gpio_defaults[25]/g +s/.gpio_control_in_2.7..gpio_defaults/gpio_defaults[26]/g +s/.gpio_control_in_2.8..gpio_defaults/gpio_defaults[27]/g +s/.gpio_control_in_2.9..gpio_defaults/gpio_defaults[28]/g +s/.gpio_control_in_2.10..gpio_defaults/gpio_defaults[29]/g +s/.gpio_control_in_1a.1..gpio_defaults/gpio_defaults[3]/g +s/.gpio_control_in_2.11..gpio_defaults/gpio_defaults[30]/g +s/.gpio_control_in_2.12..gpio_defaults/gpio_defaults[31]/g +s/.gpio_control_in_2.13..gpio_defaults/gpio_defaults[32]/g +s/.gpio_control_in_2.14..gpio_defaults/gpio_defaults[33]/g +s/.gpio_control_in_2.15..gpio_defaults/gpio_defaults[34]/g +s/.gpio_control_bidir_2.0..gpio_defaults/gpio_defaults[35]/g +s/.gpio_control_bidir_2.1..gpio_defaults/gpio_defaults[36]/g +s/.gpio_control_bidir_2.2..gpio_defaults/gpio_defaults[37]/g +s/.gpio_control_in_1a.2..gpio_defaults/gpio_defaults[4]/g +s/.gpio_control_in_1a.3..gpio_defaults/gpio_defaults[5]/g +s/.gpio_control_in_1a.4..gpio_defaults/gpio_defaults[6]/g +s/.gpio_control_in_1a.5..gpio_defaults/gpio_defaults[7]/g +s/.gpio_control_in_1.0..gpio_defaults/gpio_defaults[8]/g +s/.gpio_control_in_1.1..gpio_defaults/gpio_defaults[9]/g +s/\\mask_rev/mask_rev/g +/wire mask_rev/d +/wire gpio_defaults/d +s/^ mprj_io_vtrip_sel);/ mprj_io_vtrip_sel,\ + gpio_defaults_out,\ + mask_rev);/ +s/^ output .37:0. mprj_io_vtrip_sel;/ output [37:0] mprj_io_vtrip_sel;\ + output [38*13-1:0] gpio_defaults_out;\ + output [31:0] mask_rev;\ +\ + wire [12:0] gpio_defaults [37:0];\ + genvar i;\ + generate for (i = 0; i < 38; i = i+1) begin:instgpio\ + assign gpio_defaults_out[13*i +: 13] = gpio_defaults[i];\ + end endgenerate/ diff --git a/scripts/be_checks/tech/sky130A/caravel_gpio_test.v b/scripts/be_checks/tech/sky130A/caravel_gpio_test.v new file mode 100644 index 00000000..09c297c7 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/caravel_gpio_test.v @@ -0,0 +1,163 @@ +module gpio_test; + + wire clock_core; + wire [7:0] value; + wire flash_clk_frame; + wire flash_clk_oeb; + wire flash_csb_frame; + wire flash_csb_oeb; + wire flash_io0_di; + wire flash_io0_do; + wire flash_io0_ieb; + wire flash_io0_oeb; + wire flash_io1_di; + wire flash_io1_do; + wire flash_io1_ieb; + wire flash_io1_oeb; + wire gpio_in_core; + wire gpio_inenb_core; + wire gpio_mode0_core; + wire gpio_mode1_core; + wire gpio_out_core; + wire gpio_outenb_core; + wire por_l; + wire porb_h; + wire rstb_h; + wire vccd; + wire vssd; + wire vccd1; + wire vssd1; + wire vssa2; + wire vdda2; + wire vssa1; + wire vdda1; + wire vssd2; + wire vccd2; + wire vddio; + wire vssio; + wire [28:0] mprj_analog_io; + wire [37:0] mprj_io_analog_en; + wire [37:0] mprj_io_analog_pol; + wire [37:0] mprj_io_analog_sel; + wire [113:0] mprj_io_dm; + wire [37:0] mprj_io_holdover; + wire [37:0] mprj_io_ib_mode_sel; + wire [37:0] mprj_io_in; + wire [37:0] mprj_io_inp_dis; + wire [37:0] mprj_io_oeb; + wire [37:0] mprj_io_one; + wire [37:0] mprj_io_out; + wire [37:0] mprj_io_slow_sel; + wire [37:0] mprj_io_vtrip_sel; + wire [38*13-1:0] all_gpio_defaults; + + wire [12:0] gpio_defaults [37:0]; + wire [31:0] mask_rev; + + assign vccd = 1; + assign vssd = 0; + + genvar i; + generate for (i = 0; i < 38; i = i+1) begin:instgpio + assign gpio_defaults[i] = all_gpio_defaults[13*i +: 13]; + end endgenerate + + caravel_core caravel_core_0 ( + .clock_core(clock_core), + .flash_clk_frame(flash_clk_frame), + .flash_clk_oeb(flash_clk_oeb), + .flash_csb_frame(flash_csb_frame), + .flash_csb_oeb(flash_csb_oeb), + .flash_io0_di(flash_io0_di), + .flash_io0_do(flash_io0_do), + .flash_io0_ieb(flash_io0_ieb), + .flash_io0_oeb(flash_io0_oeb), + .flash_io1_di(flash_io1_di), + .flash_io1_do(flash_io1_do), + .flash_io1_ieb(flash_io1_ieb), + .flash_io1_oeb(flash_io1_oeb), + .gpio_in_core(gpio_in_core), + .gpio_inenb_core(gpio_inenb_core), + .gpio_mode0_core(gpio_mode0_core), + .gpio_mode1_core(gpio_mode1_core), + .gpio_out_core(gpio_out_core), + .gpio_outenb_core(gpio_outenb_core), + .por_l(por_l), + .porb_h(porb_h), + .rstb_h(rstb_h), + .vccd(vccd), + .vssd(vssd), + .vccd1(vccd1), + .vssd1(vssd1), + .vssa2(vssa2), + .vdda2(vdda2), + .vssa1(vssa1), + .vdda1(vdda1), + .vssd2(vssd2), + .vccd2(vccd2), + .vddio(vddio), + .vssio(vssio), + .mprj_analog_io(mprj_analog_io), + .mprj_io_analog_en(mprj_io_analog_en), + .mprj_io_analog_pol(mprj_io_analog_pol), + .mprj_io_analog_sel(mprj_io_analog_sel), + .mprj_io_dm(mprj_io_dm), + .mprj_io_holdover(mprj_io_holdover), + .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel), + .mprj_io_in(mprj_io_in), + .mprj_io_inp_dis(mprj_io_inp_dis), + .mprj_io_oeb(mprj_io_oeb), + .mprj_io_one(mprj_io_one), + .mprj_io_out(mprj_io_out), + .mprj_io_slow_sel(mprj_io_slow_sel), + .mprj_io_vtrip_sel(mprj_io_vtrip_sel), + .gpio_defaults_out(all_gpio_defaults), + .mask_rev(mask_rev) + ); + +initial begin + #10 $monitor("Actual"); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 0, gpio_defaults[0]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 1, gpio_defaults[1]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 2, gpio_defaults[2]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 3, gpio_defaults[3]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 4, gpio_defaults[4]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 5, gpio_defaults[5]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 6, gpio_defaults[6]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 7, gpio_defaults[7]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 8, gpio_defaults[8]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 9, gpio_defaults[9]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 10, gpio_defaults[10]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 11, gpio_defaults[11]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 12, gpio_defaults[12]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 13, gpio_defaults[13]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 14, gpio_defaults[14]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 15, gpio_defaults[15]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 16, gpio_defaults[16]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 17, gpio_defaults[17]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 18, gpio_defaults[18]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 19, gpio_defaults[19]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 20, gpio_defaults[20]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 21, gpio_defaults[21]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 22, gpio_defaults[22]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 23, gpio_defaults[23]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 24, gpio_defaults[24]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 25, gpio_defaults[25]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 26, gpio_defaults[26]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 27, gpio_defaults[27]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 28, gpio_defaults[28]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 29, gpio_defaults[29]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 30, gpio_defaults[30]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 31, gpio_defaults[31]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 32, gpio_defaults[32]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 33, gpio_defaults[33]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 34, gpio_defaults[34]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 35, gpio_defaults[35]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 36, gpio_defaults[36]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 37, gpio_defaults[37]); + #10 $monitor("Setting Project Chip ID to: %h", mask_rev); + #100 $stop; +end + +endmodule // gpio_test + diff --git a/scripts/be_checks/tech/sky130A/cvc.models b/scripts/be_checks/tech/sky130A/cvc.models new file mode 100644 index 00000000..a61a8ab2 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/cvc.models @@ -0,0 +1,79 @@ +MN nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8 +MP pfet_01v8_hvt Vth=-0.2 Vgs=1.8 Vds=1.8 + +R short model=switch_on + +D sky130_fd_pr__diode_pw2nd_05v5 +D sky130_fd_pr__diode_pw2nd_11v0 +D sky130_fd_pr__diode_pw2nd_05v5_lvt +D sky130_fd_pr__diode_pw2nd_05v5_nvt +D sky130_fd_pr__diode_pd2nw_05v5 +D sky130_fd_pr__diode_pd2nw_05v5_lvt +D sky130_fd_pr__diode_pd2nw_11v0 +D sky130_fd_pr__model__parasitic__diode_ps2dn +D sky130_fd_pr__model__parasitic__diode_ps2nw +D sky130_fd_pr__model__parasitic__diode_pw2dn +D condiode + + +#R sky130_fd_pr__res_generic_m1 R=l/w*0.125 +#R sky130_fd_pr__res_generic_m2 R=l/w*0.125 +#R sky130_fd_pr__res_generic_m3 R=l/w*0.047 +#R sky130_fd_pr__res_generic_m4 R=l/w*0.047 +#R sky130_fd_pr__res_generic_nd R=l/w*0.029 +R sky130_fd_pr__res_generic_l1 model=switch_on +R sky130_fd_pr__res_generic_m1 model=switch_on +R sky130_fd_pr__res_generic_m2 model=switch_on +R sky130_fd_pr__res_generic_m3 model=switch_on +R sky130_fd_pr__res_generic_m4 model=switch_on +R sky130_fd_pr__res_generic_m5 model=switch_on +R sky130_fd_pr__res_generic_nd R=l/w*120 +R sky130_fd_pr__res_generic_pd R=l/w*197 +R sky130_fd_pr__res_generic_nd__hv R=l/w*114 +R sky130_fd_pr__res_generic_pd__hv R=l/w*191 +R sky130_fd_pr__res_generic_po R=l/w*48 +R sky130_fd_pr__res_xhigh_po R=l/w*2000 +R sky130_fd_pr__res_xhigh_po_0p35 R=l/0.35*2000 +R sky130_fd_pr__res_xhigh_po_0p69 R=l/0.69*2000 +R sky130_fd_pr__res_xhigh_po_1p41 R=l/1.41*2000 +R sky130_fd_pr__res_xhigh_po_2p85 R=l/2.85*2000 +R sky130_fd_pr__res_xhigh_po_5p73 R=l/5.73*2000 +R sky130_fd_pr__res_high_po R=l/w*300 +R sky130_fd_pr__res_high_po_0p35 R=l/0.35*300 +R sky130_fd_pr__res_high_po_0p69 R=l/0.69*300 +R sky130_fd_pr__res_high_po_1p41 R=l/1.41*300 +R sky130_fd_pr__res_high_po_2p85 R=l/2.85*300 +R sky130_fd_pr__res_high_po_5p73 R=l/5.73*300 +R sky130_fd_pr__res_iso_pw R=l/w*4400 + +MN sky130_fd_pr__nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__special_nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__nfet_01v8_lvt Vth=0.1 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__special_nfet_latch Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__special_nfet_pass Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__nfet_03v3_nvt Vth=0.2 Vgs=3.3 Vds=3.3 +MN sky130_fd_pr__esd_nfet_g5v0d10v5 Vth=0.2 +MN sky130_fd_pr__nfet_05v0_nvt Vth=0.2 +MN sky130_fd_pr__nfet_g5v0d10v5 Vth=0.2 +MN sky130_fd_bs_flash__special_sonosfet_star Vth=0.2 + +MP sky130_fd_pr__pfet_01v8 Vth=-0.2 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__pfet_01v8_lvt Vth=-0.1 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__pfet_01v8_hvt Vth=-0.3 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__special_pfet_01v8_hvt Vth=-0.3 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__special_pfet_pass Vth=-0.2 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__special_pfet_latch Vth=-0.2 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__pfet_g5v0d10v5 Vth=-0.2 + +C sky130_fd_pr__cap_mim_m3_1 +C sky130_fd_pr__cap_mim_m3_2 +C sky130_fd_pr__cap_var +C sky130_fd_pr__cap_var_lvt + +Q sky130_fd_pr__pnp_05v5 +Q sky130_fd_pr__pnp_05v5_W0p68L0p68 +Q sky130_fd_pr__pnp_05v5_W3p40L3p40 +Q sky130_fd_pr__npn_11v0 +Q sky130_fd_pr__npn_11v0_W1p00L1p00 + + diff --git a/scripts/be_checks/tech/sky130A/cvc.power.caravan b/scripts/be_checks/tech/sky130A/cvc.power.caravan new file mode 100644 index 00000000..2f854a41 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/cvc.power.caravan @@ -0,0 +1,19 @@ +vccd power 1.8 +vccd1 power 1.8 +vccd2 power 1.8 +vdda power 3.3 +vdda1 power 3.3 +vdda1_2 power 3.3 +vdda2 power 3.3 +vddio power 3.3 +vddio_2 power 3.3 +vssa power 0.0 +vssa1 power 0.0 +vssa1_2 power 0.0 +vssa2 power 0.0 +vssd power 0.0 +vssd1 power 0.0 +vssd2 power 0.0 +vssio power 0.0 +vssio_2 power 0.0 +mprj_io[18] power 3.3 diff --git a/scripts/be_checks/tech/sky130A/cvc.power.caravel b/scripts/be_checks/tech/sky130A/cvc.power.caravel new file mode 100644 index 00000000..f80e6dc5 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/cvc.power.caravel @@ -0,0 +1,18 @@ +vccd power 1.8 +vccd1 power 1.8 +vccd2 power 1.8 +vdda power 3.3 +vdda1 power 3.3 +vdda1_2 power 3.3 +vdda2 power 3.3 +vddio power 3.3 +vddio_2 power 3.3 +vssa power 0.0 +vssa1 power 0.0 +vssa1_2 power 0.0 +vssa2 power 0.0 +vssd power 0.0 +vssd1 power 0.0 +vssd2 power 0.0 +vssio power 0.0 +vssio_2 power 0.0 diff --git a/scripts/be_checks/tech/sky130A/cvc.power.user_analog_project_wrapper b/scripts/be_checks/tech/sky130A/cvc.power.user_analog_project_wrapper new file mode 100644 index 00000000..e72e2e24 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/cvc.power.user_analog_project_wrapper @@ -0,0 +1,18 @@ +vccd* power 1.8 +vdda* power 3.3 +vssa* power 0.0 +vssd* power 0.0 +io_analog[*] input min@0.0 max@1.8 +wb_clk_i input min@0.0 max@1.8 +wb_rst_i input min@0.0 max@1.8 +wbs_stb_i input min@0.0 max@1.8 +wbs_cyc_i input min@0.0 max@1.8 +wbs_we_i input min@0.0 max@1.8 +wbs_sel_i[*] input min@0.0 max@1.8 +wbs_dat_i[*] input min@0.0 max@1.8 +wbs_adr_i[*] input min@0.0 max@1.8 +la_data_in[*] input min@0.0 max@1.8 +la_oenb[*] input min@0.0 max@1.8 +io_in[*] input min@0.0 max@1.8 +io_in_3v3[*] input min@0.0 max@3.3 +user_clock2 input min@0.0 max@1.8 diff --git a/scripts/be_checks/tech/sky130A/cvc.power.user_project_wrapper b/scripts/be_checks/tech/sky130A/cvc.power.user_project_wrapper new file mode 100644 index 00000000..8c3b6aac --- /dev/null +++ b/scripts/be_checks/tech/sky130A/cvc.power.user_project_wrapper @@ -0,0 +1,17 @@ +vccd* power 1.8 +vdda* power 3.3 +vssa* power 0.0 +vssd* power 0.0 +user_clock2 input min@0.0 max@1.8 +wb_clk_i input min@0.0 max@1.8 +wb_rst_i input min@0.0 max@1.8 +wbs_cyc_i input min@0.0 max@1.8 +wbs_stb_i input min@0.0 max@1.8 +wbs_we_i input min@0.0 max@1.8 +io_in[*] input min@0.0 max@1.8 +la_data_in[*] input min@0.0 max@1.8 +la_oenb[*] input min@0.0 max@1.8 +wbs_adr_i[*] input min@0.0 max@1.8 +wbs_dat_i[*] input min@0.0 max@1.8 +wbs_sel_i[*] input min@0.0 max@1.8 + diff --git a/scripts/be_checks/tech/sky130A/cvcrc b/scripts/be_checks/tech/sky130A/cvcrc new file mode 100644 index 00000000..ead440be --- /dev/null +++ b/scripts/be_checks/tech/sky130A/cvcrc @@ -0,0 +1,35 @@ +CVC_TOP = $DESIGN_NAME +CVC_NETLIST = $RESULTS_DIR/$CVC_TOP.cdl.gz +CVC_MODE = $CVC_TOP +CVC_MODEL_FILE = $LVS_ROOT/tech/$PDK/cvc.models +CVC_POWER_FILE = $WORK_ROOT/cvc.power.$CVC_TOP +CVC_FUSE_FILE = '' +CVC_REPORT_FILE = $WORK_ROOT/cvc.log +CVC_REPORT_TITLE = "CVC $CVC_TOP" +CVC_CIRCUIT_ERROR_LIMIT = '100' +CVC_SEARCH_LIMIT = '100' +CVC_LEAK_LIMIT = '0.0002' +CVC_SOI = 'false' +CVC_SCRC = 'false' +CVC_VTH_GATES = 'false' +CVC_MIN_VTH_GATES = 'false' +CVC_IGNORE_VTH_FLOATING = 'false' +CVC_IGNORE_NO_LEAK_FLOATING = 'false' +CVC_LEAK_OVERVOLTAGE = 'true' +CVC_LOGIC_DIODES = 'false' +CVC_ANALOG_GATES = 'true' +CVC_BACKUP_RESULTS = 'false' +CVC_MOS_DIODE_ERROR_THRESHOLD = '0' +CVC_SHORT_ERROR_THRESHOLD = '0' +CVC_BIAS_ERROR_THRESHOLD = '0' +CVC_FORWARD_ERROR_THRESHOLD = '0' +CVC_FLOATING_ERROR_THRESHOLD = '0' +CVC_GATE_ERROR_THRESHOLD = '0' +CVC_LEAK?_ERROR_THRESHOLD = '0' +CVC_EXPECTED_ERROR_THRESHOLD = '0' +CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0' +CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0' +CVC_CELL_ERROR_LIMIT_FILE = '' +CVC_CELL_CHECKSUM_FILE = '' +CVC_LARGE_CIRCUIT_SIZE = '10000000' +CVC_NET_CHECK_FILE = '' diff --git a/scripts/be_checks/tech/sky130A/expected_gpio b/scripts/be_checks/tech/sky130A/expected_gpio new file mode 100644 index 00000000..9a2e4706 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/expected_gpio @@ -0,0 +1,6 @@ +Expected +USER_CONFIG_GPIO_0_INIT 1803 +USER_CONFIG_GPIO_1_INIT 1803 +USER_CONFIG_GPIO_2_INIT 0403 +USER_CONFIG_GPIO_3_INIT 0801 +USER_CONFIG_GPIO_4_INIT 0403 diff --git a/scripts/be_checks/tech/sky130A/known.undefined.layer b/scripts/be_checks/tech/sky130A/known.undefined.layer new file mode 100644 index 00000000..f5602dd9 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/known.undefined.layer @@ -0,0 +1,4 @@ +layer=22 type=21 +layer=22 type=22 +layer=33 type=42 +layer=33 type=43 diff --git a/scripts/be_checks/tech/sky130A/known.undefined.layer.def b/scripts/be_checks/tech/sky130A/known.undefined.layer.def new file mode 100644 index 00000000..3c719a13 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/known.undefined.layer.def @@ -0,0 +1,5 @@ +layer=22 type=21 # cfom/mask add +layer=22 type=22 # cfom/mask drop +layer=235 type=0 +layer=33 type=42 # cp1m/mask drop +layer=33 type=43 # cp1m/mask add diff --git a/scripts/be_checks/tech/sky130A/known_abstract_filter.awk b/scripts/be_checks/tech/sky130A/known_abstract_filter.awk new file mode 100644 index 00000000..f832f602 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/known_abstract_filter.awk @@ -0,0 +1,5 @@ +/__fill_/ {next} # ignore abstract devices +/__tapvpwrvgnd_/ {next} +/__fakediode_/ {next} +/sky130_fd_pr__/ {next} # ignore primitive devices +{ print } diff --git a/scripts/be_checks/tech/sky130A/lvs_config.base.json b/scripts/be_checks/tech/sky130A/lvs_config.base.json new file mode 100644 index 00000000..08982d72 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.base.json @@ -0,0 +1,25 @@ +{ + "EXTRACT_FLATGLOB": [ + "*sky130_fd_pr__*[A-Z]*" + ], + "EXTRACT_ABSTRACT": [ + "*__fill_*", + "*__fakediode_*", + "*__tapvpwrvgnd_*" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$PDK_ROOT/$PDK/libs.ref/$STD_CELL_LIBRARY/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "" + ] +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.caravan_core-upw.json b/scripts/be_checks/tech/sky130A/lvs_config.caravan_core-upw.json new file mode 100644 index 00000000..1e1a2a57 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.caravan_core-upw.json @@ -0,0 +1,47 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "caravan_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "*user_analog_project_wrapper", + "*sky130_fd_sc_hd__macro_sparecell" + ], + "LVS_FLATTEN": [ + "caravan_signal_routing", + "empty_macro_1" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping_alt.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/$TOP_SOURCE.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.caravan_core.json b/scripts/be_checks/tech/sky130A/lvs_config.caravan_core.json new file mode 100644 index 00000000..5f4261c1 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.caravan_core.json @@ -0,0 +1,47 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json", + "$UPRJ_ROOT/lvs/user_analog_project_wrapper/lvs_config.json" + ], + "TOP_SOURCE": "caravan_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "caravan_signal_routing", + "empty_macro_1" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping_alt.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/verilog/gl/$TOP_SOURCE.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.caravel.json b/scripts/be_checks/tech/sky130A/lvs_config.caravel.json new file mode 100644 index 00000000..f03d816d --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.caravel.json @@ -0,0 +1,38 @@ +{ + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.chip_io.json", + "$LVS_ROOT/tech/$PDK/lvs_config.caravel_core.json" + ], + "TOP_SOURCE": "caravel", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "EXTRACT_CREATE_SUBCUT": [ + "*user_project_wrapper" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "" + ], + "LVS_VERILOG_FILES": [ + "$CARAVEL_ROOT/verilog/gl/caravel_logo.v", + "$CARAVEL_ROOT/verilog/gl/caravel_motto.v", + "$CARAVEL_ROOT/verilog/gl/copyright_block.v", + "$CARAVEL_ROOT/verilog/gl/open_source.v", + "$CARAVEL_ROOT/verilog/gl/user_id_textblock.v", + "$CARAVEL_ROOT/verilog/gl/caravel.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.caravel_core-upw.json b/scripts/be_checks/tech/sky130A/lvs_config.caravel_core-upw.json new file mode 100644 index 00000000..a039a430 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.caravel_core-upw.json @@ -0,0 +1,46 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "caravel_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "*user_project_wrapper", + "*sky130_fd_sc_hd__macro_sparecell" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/$TOP_SOURCE.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.caravel_core.json b/scripts/be_checks/tech/sky130A/lvs_config.caravel_core.json new file mode 100644 index 00000000..f079e873 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.caravel_core.json @@ -0,0 +1,46 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json", + "$UPRJ_ROOT/lvs/user_project_wrapper/lvs_config.json" + ], + "TOP_SOURCE": "caravel_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/verilog/gl/caravel_core.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.chip_io.json b/scripts/be_checks/tech/sky130A/lvs_config.chip_io.json new file mode 100644 index 00000000..6d37b9d5 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.chip_io.json @@ -0,0 +1,64 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "chip_io", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "*sky130_fd_pr__*example*", + "*sky130_ef_io__com*", + "*sky130_ef_io__connect*", + "*sky130_ef_io__corner*", + "*sky130_ef_io__*_overlay", + "*sky130_fd_io__amux*", + "*sky130_fd_io__amx_inv1", + "*sky130_fd_io__com*", + "*sky130_fd_io__corner*", + "*sky130_fd_io__esd*", + "*sky130_fd_io__feas*", + "*sky130_fd_io__gpio*", + "*sky130_fd_io__gnd2gnd*", + "*sky130_fd_io__hvc*", + "*sky130_fd_io__hvsbt*", + "*sky130_fd_io__inv*", + "*sky130_fd_io__nand*", + "*sky130_fd_io__nfet_con*", + "*sky130_fd_io__nor*", + "*sky130_fd_io__overlay*", + "*sky130_fd_io__pad_esd", + "*sky130_fd_io__pfet_con*", + "*sky130_fd_io__res250*", + "*sky130_fd_io__res75*", + "*sky130_fd_io__signal*", + "*sky130_fd_io__sio*", + "*sky130_fd_io__simple_pad_*", + "*sky130_fd_io__tap*", + "*sky130_fd_io__tk_tie*", + "*sky130_fd_io__top_gpio*", + "*sky130_fd_io__top_ground*", + "*sky130_fd_io__top_power*", + "*sky130_fd_io__xor*", + "*sky130_fd_io__xres*" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$LVS_ROOT/spice/sky130_*_io.1_0_410+.spice" + ], + "LVS_VERILOG_FILES": [ + "$CARAVEL_ROOT/verilog/gl/constant_block.v", + "$CARAVEL_ROOT/verilog/gl/chip_io.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.chip_io_alt.json b/scripts/be_checks/tech/sky130A/lvs_config.chip_io_alt.json new file mode 100644 index 00000000..60f589c5 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.chip_io_alt.json @@ -0,0 +1,65 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "chip_io", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "*sky130_fd_pr__*example*", + "*sky130_ef_io__com*", + "*sky130_ef_io__connect*", + "*sky130_ef_io__corner*", + "*sky130_ef_io__gpiov2_pad", + "*sky130_ef_io__*_overlay", + "*sky130_fd_io__amux*", + "*sky130_fd_io__amx_inv1", + "*sky130_fd_io__com*", + "*sky130_fd_io__corner*", + "*sky130_fd_io__esd*", + "*sky130_fd_io__feas*", + "*sky130_fd_io__gpio*", + "*sky130_fd_io__gnd2gnd*", + "*sky130_fd_io__hvc*", + "*sky130_fd_io__hvsbt*", + "*sky130_fd_io__inv*", + "*sky130_fd_io__nand*", + "*sky130_fd_io__nfet_con*", + "*sky130_fd_io__nor*", + "*sky130_fd_io__overlay*", + "*sky130_fd_io__pad_esd", + "*sky130_fd_io__pfet_con*", + "*sky130_fd_io__res250*", + "*sky130_fd_io__res75*", + "*sky130_fd_io__signal*", + "*sky130_fd_io__sio*", + "*sky130_fd_io__simple_pad_*", + "*sky130_fd_io__tap*", + "*sky130_fd_io__tk_tie*", + "*sky130_fd_io__top_gpio*", + "*sky130_fd_io__top_ground*", + "*sky130_fd_io__top_power*", + "*sky130_fd_io__xor*", + "*sky130_fd_io__xres*" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$CARAVEL_ROOT/verilog/gl/constant_block.v", + "$CARAVEL_ROOT/verilog/gl/chip_io.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.sram.json b/scripts/be_checks/tech/sky130A/lvs_config.sram.json new file mode 100644 index 00000000..20e9a586 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.sram.json @@ -0,0 +1,24 @@ +{ + "EXTRACT_FLATGLOB": [ + "*_nmos_m*", + "*_pmos_m*" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$LVS_ROOT/spice/$SRAM_MACRO.470.spice" + ], + "LVS_VERILOG_FILES": [ + "" + ] +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.user_analog_project_wrapper.json b/scripts/be_checks/tech/sky130A/lvs_config.user_analog_project_wrapper.json new file mode 100644 index 00000000..2d79501c --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.user_analog_project_wrapper.json @@ -0,0 +1,30 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "user_analog_project_wrapper", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$UPRJ_ROOT/xschem/user_analog_project_wrapper.spice" + ], + "LVS_VERILOG_FILES": [ + "" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/user_analog_project_wrapper.gds" +} diff --git a/scripts/be_checks/tech/sky130A/lvs_config.user_project_wrapper.json b/scripts/be_checks/tech/sky130A/lvs_config.user_project_wrapper.json new file mode 100644 index 00000000..f1d2e7fa --- /dev/null +++ b/scripts/be_checks/tech/sky130A/lvs_config.user_project_wrapper.json @@ -0,0 +1,31 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "user_project_wrapper", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "" + ], + "LVS_VERILOG_FILES": [ + "$UPRJ_ROOT/verilog/gl/user_proj_example.v", + "$UPRJ_ROOT/verilog/gl/user_project_wrapper.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/user_project_wrapper.gds" +} diff --git a/scripts/be_checks/tech/sky130A/remove_well.sed b/scripts/be_checks/tech/sky130A/remove_well.sed new file mode 100644 index 00000000..924bfa3f --- /dev/null +++ b/scripts/be_checks/tech/sky130A/remove_well.sed @@ -0,0 +1,21 @@ +s/[^ ]* \(sky130_fd_pr__.fet\)/\1/ +s/[^ ]* \(sky130_fd_pr__special_.fet\)/\1/ +s/[^ ]* \(sky130_fd_pr__esd_.fet\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_high_po\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_xhigh_po\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_generic_nd\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_generic_pd\)/\1/ +s/[^ ]* \(sky130_fd_pr__cap_var\)/\1/ +s/[^ ]* \(sky130_fd_bs_flash__special_sonosfet_star\)/\1/ +s/[^ ]* \(ppolyf_u_1k_6p0\)/\1/ +s/[^ ]* \(ppolyf_u\)/\1/ +s/[^ ]* \(.fet_06v0\)/\1/ +/^D.* sky130_fd_pr__diode_pd2nw_/d +/^D.* sky130_fd_pr__diode_pw2nd_/d +/^D.* sky130_fd_pr__model__parasitic__diode_ps2dn/d +/^D.* diode_pd2nw_06v0/d +/^D.* diode_nd2ps_06v0/d +/^D.* np_6p0/d +/^D.* pn_6p0/d +/^R.* sky130_fd_pr__res_iso_pw/d +/^X.* sky130_fd_pr__pnp_05v5/d diff --git a/scripts/be_checks/tech/sky130A/sky130A.tech b/scripts/be_checks/tech/sky130A/sky130A.tech new file mode 100644 index 00000000..1e1c2b15 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/sky130A.tech @@ -0,0 +1,6288 @@ +#------------------------------------------------------------------------ +# Copyright (c) 2020 R. Timothy Edwards +# Revisions: See below +# +# This file is an Open Source foundry process describing +# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication +# process. The file may be distributed under the terms +# of the Apache 2.0 license agreement. +# +#------------------------------------------------------------------------ +tech + format 35 + sky130A +end + +version + version 1.0.470-0-g6d4d117 + description "SkyWater SKY130: Open Source rules and DRC" + requires magic-8.3.411 +end + +#------------------------------------------------------------------------ +# Status 7/10/20: Rev 1 (alpha): +# First public release +# Status 8/14/20: Rev 2 (alpha): +# Started updating with new device/model naming convention +# Status 1/3/21: Taking out of beta and declaring an official release. +# Status 3/17/22: Added fringeshieldhalo to improve parasitic capacitance +# calculations. +# Status 5/21/22: Added sidewall edge (spacing) enlargement. +#------------------------------------------------------------------------ + +#------------------------------------------------------------------------ +# Supported device types +#------------------------------------------------------------------------ +# device name magic ID layer description +#------------------------------------------------------------------------ +# sky130_fd_pr__nfet_01v8 nfet standard nFET +# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell** +# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell +# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell +# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET +# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET +# sky130_fd_pr__pfet_01v8 pfet standard pFET +# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell** +# sky130_fd_pr__special_pfet_latch ppu special pFET in SRAM cell +# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET +# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET +# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET +# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET +# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET +# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET +# sky130_fd_pr__nfet_05v0_nvt mvnnfet thickox native nFET +# sky130_fd_pr__nfet_g5v0d16v0 mvnfet extended-drain nFET*** +# sky130_fd_pr__pfet_g5v0d16v0 mvpfet extended-drain pFET*** +# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode +# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode +# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff +# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode +# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode +# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell +# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN +# sky130_fd_pr__pnp_05v5 nbase PNP +# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate +# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate +# sky130_fd_pr__res_generic_nd rdn n+ diff resistor +# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor +# sky130_fd_pr__res_generic_pd rdp p+ diff resistor +# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor +# sky130_fd_pr__res_generic_l1 rli local interconnect resistor +# sky130_fd_pr__res_generic_po npres n+ poly resistor +# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq) +# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq) +# sky130_fd_pr__cap_var_lvt varactor low Vt varactor +# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor +# sky130_fd_pr__cap_var mvvaractor thickox varactor +# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell) +# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET +# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET +# sky130_fd_pr__photodiode photo Photodiode +# +# (*) Note that ppres may extract into some generic type called +# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are +# allowed, and these are created from fixed layouts like the types below. +# +# (**) nFET and pFET in standard cells are the same as devices +# outside of the standard cell except for the DRC rule for +# FET to diffusion contact spacing (which is 0.05um, not 0.055um) +# +# (***) The extended-drain devices have the same identifying +# FET type as the thick oxide devices, but the drain side of the +# device is represented by layer extdrain extending to nsd or psd. +# +#------------------------------------------------------------- +# The following devices are not extracted but are represented +# only by script-generated subcells in the PDK. +#------------------------------------------------------------- +# sky130_fd_pr__esd_nfet_01v8 ESD nFET +# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET +# sky130_fd_pr__special_nfet_pass_flash flash nFET device +# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode +# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode +# sky130_fd_pr__cap_vpp_* Vpp cap +# sky130_fd_pr__ind_* inductor +# sky130_fd_pr__fuse_m4 metal fuse device +#-------------------------------------------------------------- + +#----------------------------------------------------- +# Tile planes +#----------------------------------------------------- + +planes + dwell,dw + well,w + active,a + locali,li1,li + metal1,m1 + metal2,m2 + metal3,m3 + cap1,c1 + metal4,m4 + cap2,c2 + metal5,m5 + metali,mi + block,b + comment,c +end + +#----------------------------------------------------- +# Tile types +#----------------------------------------------------- + +types +# Deep nwell + dwell dnwell,dnw + dwell isosubstrate,isosub + dwell photodiode,photo + +# Wells + well nwell,nw + well pwell,pw + well rpw,rpwell + -well obswell + well pbase,npn + well nbase,pnp + +# Transistors + active nmos,ntransistor,nfet + -active scnmos,scntransistor,scnfet + -active npd,npdfet,sramnfet + -active npass,npassfet,srampassfet + active pmos,ptransistor,pfet + -active scpmos,scptransistor,scpfet + -active scpmoshvt,scpfethvt + -active ppu,ppufet,srampfet + active nnmos,nntransistor,nnfet + active mvnmos,mvntransistor,mvnfet + active mvpmos,mvptransistor,mvpfet + active mvnnmos,mvnntransistor,mvnnfet + -active mvnmosesd,mvntransistoresd,mvnfetesd + -active mvpmosesd,mvptransistoresd,mvpfetesd + active varactor,varact,var + active mvvaractor,mvvaract,mvvar + + active pmoslvt,pfetlvt + active pmosmvt,pfetmvt + active pmoshvt,pfethvt + active nmoslvt,nfetlvt + active varactorhvt,varacthvt,varhvt + -active nsonos,sonos + -active sramnvar,corenvar,corenvaractor + -active srampvar,corepvar,corepvaractor + +# Diffusions + -active fomfill + active ndiff,ndiffusion,ndif + active pdiff,pdiffusion,pdif + active mvndiff,mvndiffusion,mvndif + active mvpdiff,mvpdiffusion,mvpdif + active ndiffc,ndcontact,ndc + active pdiffc,pdcontact,pdc + active mvndiffc,mvndcontact,mvndc + active mvpdiffc,mvpdcontact,mvpdc + active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap + active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap + active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap + active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap + active psubdiffcont,psubstratepcontact,psc,ptapc + active nsubdiffcont,nsubstratencontact,nsc,ntapc + active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc + active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc + active extdrain,ed + -active obsactive + -active mvobsactive + +# Poly + active poly,p,polysilicon + active polycont,pc,pcontact,polycut,polyc + active xpolycontact,xpolyc,xpc + -active polyfill + +# Resistors + active npolyres,npres,mrp1 + active ppolyres,ppres,xhrpoly + active xpolyres,xpres,xres,uhrpoly + active ndiffres,rnd,rdn,rndiff + active pdiffres,rpd,rdp,rpdiff + active mvndiffres,mvrnd,mvrdn,mvrndiff + active mvpdiffres,mvrpd,mvrdp,mvrpdiff + active rmp + +# Diodes + active pdiode,pdi + active ndiode,ndi + active nndiode,nndi + active pdiodec,pdic + active ndiodec,ndic + active nndiodec,nndic + active mvpdiode,mvpdi + active mvndiode,mvndi + active mvpdiodec,mvpdic + active mvndiodec,mvndic + active pdiodelvt,pdilvt + active pdiodehvt,pdihvt + active ndiodelvt,ndilvt + active pdiodelvtc,pdilvtc + active pdiodehvtc,pdihvtc + active ndiodelvtc,ndilvtc + +# Local Interconnect + locali locali,li1,li + -locali corelocali,coreli1,coreli + locali rlocali,rli1,rli + locali viali,vial,mcon,m1c,v0 + -locali obsli1,obsli + -locali obsli1c,obsmcon + -locali lifill + +# Metal 1 + metal1 metal1,m1,met1 + metal1 rmetal1,rm1,rmet1 + metal1 via1,m2contact,m2cut,m2c,via,v,v1 + -metal1 obsm1 + -metal1 m1fill + + +# Metal 2 + metal2 metal2,m2,met2 + metal2 rmetal2,rm2,rmet2 + metal2 via2,m3contact,m3cut,m3c,v2 + -metal2 obsm2 + -metal2 m2fill + +# Metal 3 + metal3 metal3,m3,met3 + metal3 rmetal3,rm3,rmet3 + -metal3 obsm3 + metal3 via3,v3 + -metal3 m3fill + + cap1 mimcap,mim,capm + cap1 mimcapcontact,mimcapc,mimcc,capmc + +# Metal 4 + metal4 metal4,m4,met4 + metal4 rmetal4,rm4,rmet4 + -metal4 obsm4 + metal4 via4,v4 + -metal4 m4fill + + cap2 mimcap2,mim2,capm2 + cap2 mimcap2contact,mimcap2c,mim2cc,capm2c + +# Metal 5 + metal5 metal5,m5,met5 + metal5 rm5,rmetal5,rmet5 + -metal5 obsm5 + -metal5 m5fill + + metal5 mrdlcontact,mrdlc,pi1 + metali metalrdl,mrdl,metrdl,rdl + -metali obsmrdl + metali pi2 + block ubm + +# Miscellaneous + -block glass + -block fillblock,fillblock4 + comment comment + -comment obscomment + +end + +#----------------------------------------------------- +# Magic contact types +#----------------------------------------------------- + +contact + pc poly locali + ndc ndiff locali + pdc pdiff locali + nsc nsd locali + psc psd locali + ndic ndiode locali + ndilvtc ndiodelvt locali + nndic nndiode locali + pdic pdiode locali + pdilvtc pdiodelvt locali + pdihvtc pdiodehvt locali + xpc xpc locali + + mvndc mvndiff locali + mvpdc mvpdiff locali + mvnsc mvnsd locali + mvpsc mvpsd locali + mvndic mvndiode locali + mvpdic mvpdiode locali + + mcon locali metal1 + obsmcon obsli metal1 + + via1 metal1 metal2 + via2 metal2 metal3 + via3 metal3 metal4 + via4 metal4 metal5 + stackable + + # MiM cap contacts are not stackable! + mimcc mimcap metal4 + mim2cc mimcap2 metal5 + + mrdlc metal5 mrdl + pi2 mrdl ubm +end + +#----------------------------------------------------- +# Layer aliases +#----------------------------------------------------- + +aliases + + allwellplane nwell + allnwell nwell,obswell,pnp + + allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos + allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt + allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar + allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt + allfetsspecial scnfet,scpfet,scpfethvt + allfetscore npass,npd,nsonos,ppu,corenvar,corepvar + allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar + + allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt + allnactive allnactivenonfet,allnfets + allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets + allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar + + allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt + allpactive allpactivenonfet,allpfets + allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets + allpactivetap *psd,*mvpsd,corepvar + + allactivenonfet allnactivenonfet,allpactivenonfet + allactive allactivenonfet,allfets + + allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres + + allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos + allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt + alldifflv allndifflv,allpdifflv + allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt + allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt + alldifflvnonfet allndifflvnonfet,allpdifflvnonfet + + allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet + allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd + alldiffmv allndiffmv,allpdiffmv + allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet + allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd + alldiffmvnontap allndiffmvnontap,allpdiffmvnontap + allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres + allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres + alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet + + alldiffnonfet alldifflvnonfet,alldiffmvnonfet + alldiff alldifflv,alldiffmv,fomfill + + allpolyres mrp1,xhrpoly,uhrpoly,rmp + allpolynonfet *poly,allpolyres,xpc + allpolynonres *poly,allfets,xpc + + allpoly allpolynonfet,allfets + allpolynoncap *poly,xpc,allfets,allpolyres + + allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc + allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc + allndiffcontmv mvndc,mvnsc,mvndic + allpdiffcontmv mvpdc,mvpsc,mvpdic + allndiffcont allndiffcontlv,allndiffcontmv + allpdiffcont allpdiffcontlv,allpdiffcontmv + alldiffcontlv allndiffcontlv,allpdiffcontlv + alldiffcontmv allndiffcontmv,allpdiffcontmv + alldiffcont alldiffcontlv,alldiffcontmv + + allcont alldiffcont,pc + + allres allpolyres,allactiveres + + allli *locali,coreli,rli + allm1 *m1,rm1 + allm2 *m2,rm2 + allm3 *m3,rm3 + allm4 *m4,rm4 + allm5 *m5,rm5 + + psub pwell + + obstypes obswell,mvobsactive,obsactive,obsli,obsmcon,obsm1,obsm2,obsm3,obsm4,obsm5,obsmrdl,obscomment + blocktypes fillblock,fillblock4 + +end + +#----------------------------------------------------- +# Layer drawing styles +#----------------------------------------------------- + +styles + styletype mos + dnwell cwell + isosub subcircuit + nwell nwell + pwell pwell + rpwell pwell ptransistor_stripes + photo nwell nwell_field_implant + ndiff ndiffusion + fomfill ndiffusion + pdiff pdiffusion + nsd ndiff_in_nwell + psd pdiff_in_pwell + nfet ntransistor ntransistor_stripes + scnfet ntransistor ntransistor_stripes + npass ntransistor ntransistor_stripes + npd ntransistor ntransistor_stripes + pfet ptransistor ptransistor_stripes + scpfet ptransistor ptransistor_stripes + scpfethvt ptransistor ptransistor_stripes implant2 + ppu ptransistor ptransistor_stripes + var polysilicon ndiff_in_nwell + ndc ndiffusion metal1 contact_X'es + pdc pdiffusion metal1 contact_X'es + nsc ndiff_in_nwell metal1 contact_X'es + psc pdiff_in_pwell metal1 contact_X'es + corenvar polysilicon ndiff_in_nwell + corepvar polysilicon pdiff_in_pwell + + pnp nwell ntransistor_stripes + npn pwell ptransistor_stripes + + pfetlvt ptransistor ptransistor_stripes implant1 + pfetmvt ptransistor ptransistor_stripes implant3 + pfethvt ptransistor ptransistor_stripes implant2 + nfetlvt ntransistor ntransistor_stripes implant1 + nsonos ntransistor implant3 + varhvt polysilicon ndiff_in_nwell implant2 + nnfet ntransistor ndiff_in_nwell + + mvndiff ndiffusion hvndiff_mask + mvpdiff pdiffusion hvpdiff_mask + mvnsd ndiff_in_nwell hvndiff_mask + mvpsd pdiff_in_pwell hvpdiff_mask + mvnfet ntransistor ntransistor_stripes hvndiff_mask + mvnfetesd ntransistor ntransistor_stripes hvndiff_mask + mvnnfet ntransistor ndiff_in_nwell hvndiff_mask + mvpfet ptransistor ptransistor_stripes + mvpfetesd ptransistor ptransistor_stripes + mvvar polysilicon ndiff_in_nwell hvndiff_mask + mvndc ndiffusion metal1 contact_X'es hvndiff_mask + mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask + mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask + mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask + + extdrain nselect pselect + + poly polysilicon + polyfill polysilicon + pc polysilicon metal1 contact_X'es + npolyres polysilicon silicide_block nselect2 + ppolyres polysilicon silicide_block pselect2 + xpc polysilicon pselect2 metal1 contact_X'es + rmp polysilicon poly_resist_stripes + + pdiode pdiffusion pselect2 + ndiode ndiffusion nselect2 + pdiodec pdiffusion pselect2 metal1 contact_X'es + ndiodec ndiffusion nselect2 metal1 contact_X'es + + nndiode ndiffusion nselect2 implant3 + ndiodelvt ndiffusion nselect2 implant1 + pdiodelvt pdiffusion pselect2 implant1 + pdiodehvt pdiffusion pselect2 implant2 + pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es + pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es + ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es + + mvpdiode pdiffusion pselect2 hvpdiff_mask + mvndiode ndiffusion nselect2 hvndiff_mask + mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask + mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask + nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask + + locali metal1 + lifill metal1 + coreli metal1 + rli metal1 poly_resist_stripes + mcon metal1 metal2 via1arrow + obsli metal1 + obsmcon metal1 metal2 via1arrow + + metal1 metal2 + m1fill metal2 + rm1 metal2 poly_resist_stripes + obsm1 metal2 + m2c metal2 metal3 via2arrow + + + metal2 metal3 + m2fill metal3 + rm2 metal3 poly_resist_stripes + obsm2 metal3 + m3c metal3 metal4 via3alt + metal3 metal4 + m3fill metal4 + rm3 metal4 poly_resist_stripes + obsm3 metal4 + mimcap metal3 mems + mimcc metal3 contact_X'es mems + mimcap2 metal4 mems + mim2cc metal4 contact_X'es mems + via3 metal4 metal5 via4 + metal4 metal5 + m4fill metal5 + rm4 metal5 poly_resist_stripes + obsm4 metal5 + via4 metal5 metal6 via5 + metal5 metal6 + m5fill metal6 + rm5 metal6 poly_resist_stripes + obsm5 metal6 + mrdlc metal6 metal7 via6 + metalrdl metal7 + obsmrdl metal7 + ubm metal8 + pi2 metal7 metal8 via7 + + glass overglass + mrp1 poly_resist poly_resist_stripes + xhrpoly poly_resist silicide_block + uhrpoly poly_resist + ndiffres ndiffusion ndop_stripes + pdiffres pdiffusion pdop_stripes + mvndiffres ndiffusion hvndiff_mask ndop_stripes + mvpdiffres pdiffusion hvpdiff_mask pdop_stripes + comment comment + error_p error_waffle + error_s error_waffle + error_ps error_waffle + fillblock cwell + fillblock4 cwell + + obswell cwell + obsactive implant4 + + magnet substrate_field_implant + rotate via3alt + fence via5 +end + +#----------------------------------------------------- +# Special paint/erase rules +#----------------------------------------------------- + +compose + compose nfet poly ndiff + compose pfet poly pdiff + compose var poly nsd + + decompose npass poly ndiff + decompose npd poly ndiff + decompose scnfet poly ndiff + decompose nfetlvt poly ndiff + decompose nsonos poly ndiff + + decompose ppu poly pdiff + decompose scpfet poly pdiff + decompose scpfethvt poly pdiff + decompose pfethvt poly pdiff + decompose pfetlvt poly pdiff + decompose pfetmvt poly pdiff + decompose corenvar poly nsd + decompose corepvar poly psd + decompose varhvt poly nsd + + compose mvnfet poly mvndiff + compose mvpfet poly mvpdiff + compose mvvar poly mvnsd + + decompose nnfet poly mvndiff + decompose mvnfetesd poly mvndiff + decompose mvnnfet poly mvndiff + decompose mvpfetesd poly mvpdiff + + paint obsmcon locali via1 + paint obsmcon obsm1 obsli,obsm1 + + paint ndc nwell pdc + paint nfet nwell pfet + paint scnfet nwell scpfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint npd nwell ppu + + paint pdc pwell ndc + paint pfet pwell nfet + paint scpfet pwell scnfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint ppu pwell npd + + paint pdc coreli pdc + paint ndc coreli ndc + paint pc coreli pc + paint nsc coreli nsc + paint psc coreli psc + paint viali coreli viali + paint mvpdc coreli mvpdc + paint mvndc coreli mvndc + paint mvnsc coreli mvnsc + paint mvpsc coreli mvpsc + + paint coreli pdc pdc + paint coreli ndc ndc + paint coreli pc pc + paint coreli nsc nsc + paint coreli psc psc + paint coreli viali viali + paint coreli mvpdc mvpdc + paint coreli mvndc mvndc + paint coreli mvnsc mvnsc + paint coreli mvpsc mvpsc + + + paint m4 obsm4 m4 + paint m5 obsm5 m5 +end + +#----------------------------------------------------- +# Electrical connectivity +#----------------------------------------------------- + +connect + *nwell,*nsd,*mvnsd,dnwell,pnp,photo *nwell,*nsd,*mvnsd,dnwell,pnp,photo + pwell,*psd,*mvpsd,npn,isosub pwell,*psd,*mvpsd,npn,isosub + *mvnsd ed + *mvpsd ed + *li,coreli,lifill *li,coreli,lifill + *m1,m1fill,obsmcon *m1,m1fill,obsmcon + *m2,m2fill *m2,m2fill + *m3,m3fill *m3,m3fill + *m4,m4fill *m4,m4fill + *m5,m5fill *m5,m5fill + *mimcap *mimcap + *mimcap2 *mimcap2 + allnactivenonfet allnactivenonfet + allpactivenonfet allpactivenonfet + *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill + # RDL connects to m5 through glass cut + *mrdl *mrdl + glass metrdl +end + +#----------------------------------------------------- +# CIF/GDS output layer definitions +#----------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size + +cifoutput + +#---------------------------------------------------------------- +style gdsii +# NOTE: This section is used for actual GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + +#---------------------------------------------------------------- +# Create a temp layer from the cell bounding box for use in +# generating ID layers. Note that "boundary", unlike "bbox", +# requires the FIXED_BBOX property (abutment box) in the cell. +#---------------------------------------------------------------- + templayer CELLBOUND + boundary + +#---------------------------------------------------------------- +# BOUND +#---------------------------------------------------------------- + layer BOUND CELLBOUND + calma 235 4 + +#---------------------------------------------------------------- +# DNWELL +#---------------------------------------------------------------- + + layer DNWELL dnwell,npn,photo + calma 64 18 + + layer PWRES rpw + and dnwell + calma 64 13 + +#---------------------------------------------------------------- +# SUBCUT +#---------------------------------------------------------------- + + layer SUBCUT isosub + calma 81 53 + +#---------------------------------------------------------------- +# NWELL +#---------------------------------------------------------------- + + # Identify LDMOS drain areas + templayer ndrainarea + bloat-all ed *mvnsd + and-not ed + + templayer pdrainarea + bloat-all ed *mvpsd + and-not ed + + # Generate n-well under extended-drain nFET + templayer extnwell + bloat-or *mvnsd * 0 extdrain 1150 + and-not *mvnsd + or ndrainarea + grow 660 + + # Erase n-well under extended-drain pFET + templayer extpwell + bloat-or *mvpsd * 0 extdrain 590 + and-not *mvpsd + or pdrainarea + grow 860 + + layer NWELL allnwell + bloat-all rpw dnwell + and-not rpw,pwell + or extnwell + and-not extpwell + calma 64 20 + + layer WELLTXT + labels allnwell + calma 64 5 + + layer WELLPIN + labels allnwell port + calma 64 16 + +#---------------------------------------------------------------- +# SUB (text/port only) +#---------------------------------------------------------------- + + layer SUBTXT + labels pwell + calma 64 59 + + layer SUBPIN + labels pwell port + calma 122 16 + +#---------------------------------------------------------------- +# DIFF +#---------------------------------------------------------------- + + # Extended-drain FETs cut the diffusion under the gate + templayer ldbreak + bloat-or *mvnsd * 0 extdrain 1585 + bloat-or *mvpsd * 0 extdrain 1190 + + layer DIFF allnactivenontap,allpactivenontap,allactiveres + and-not ldbreak + calma 65 20 + + layer DIFFTXT + labels allnactivenontap,allpactivenontap + calma 65 6 + + layer DIFFPIN + labels allnactivenontap,allpactivenontap port + calma 65 16 + +#---------------------------------------------------------------- +# TAP +#---------------------------------------------------------------- + + layer TAP allnactivetap,allpactivetap + labels allnactivetap,allpactivetap port + calma 65 44 + + layer TAPTXT + labels allnactivetap,allpactivetap + calma 65 5 + +#---------------------------------------------------------------- +# FOM +#---------------------------------------------------------------- + + layer FOMFILL fomfill + labels fomfill + calma 23 28 + +#---------------------------------------------------------------- +# PSDM, NSDM (PPLUS, NPLUS implants) +#---------------------------------------------------------------- + + templayer basePSDM pdiffres,mvpdiffres + grow 15 + or xhrpoly,uhrpoly,xpc + grow 110 + bloat-or allpactivetap * 125 allnactivenontap 0 + bloat-or allpactivenontap * 125 allnactivetap 0 + + templayer baseNSDM ndiffres,mvndiffres + grow 125 + bloat-or allnactivetap * 125 allpactivenontap 0 + bloat-or allnactivenontap * 125 allpactivetap 0 + + templayer extendPSDM basePSDM + bridge 380 380 + and-not baseNSDM + + layer PSDM basePSDM,extendPSDM + grow 185 + shrink 185 + close 265000 + mask-hints PSDM + calma 94 20 + + templayer extendNSDM baseNSDM + bridge 380 380 + and-not basePSDM + + layer NSDM baseNSDM,extendNSDM + grow 185 + shrink 185 + close 265000 + mask-hints NSDM + calma 93 44 + +#---------------------------------------------------------------- +# EDID (Extended drain identifier) +#---------------------------------------------------------------- + + layer EDID + bloat-all extdrain *mvnsd,*mvpsd,mvnfet,mvpfet,*mvndiff,*mvpdiff + labels extdrain + calma 81 57 + +#---------------------------------------------------------------- +# LVID +#---------------------------------------------------------------- + + layer LVID nnfet + grow 100 + calma 81 60 + +#---------------------------------------------------------------- +# LVTN +#---------------------------------------------------------------- + + layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + mask-hints LVTN + calma 125 44 + +#---------------------------------------------------------------- +# HVTR +#---------------------------------------------------------------- + + layer HVTR pfetmvt + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + calma 18 20 + +#---------------------------------------------------------------- +# HVTP +#---------------------------------------------------------------- + + layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + mask-hints HVTP + calma 78 44 + +#---------------------------------------------------------------- +# SONOS +#---------------------------------------------------------------- + + layer SONOS nsonos + grow 100 + grow-min 410 + bridge 500 410 + grow 250 + shrink 250 + calma 80 20 + +#---------------------------------------------------------------- +# The coreli layer indicates a cell needing COREID. Also, +# devices npd, npass, and ppu indicate a COREID cell. NOTE: +# SONOS does not use COREID, counter to SkyWater rules. +#---------------------------------------------------------------- + + layer COREID + bloat-all coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND + mask-hints COREID + calma 81 2 + +#---------------------------------------------------------------- +# STDCELL applies to all cells containing scnfet or scpfet. +#---------------------------------------------------------------- + + layer STDCELL scnfet + bloat-all scpfet,scpfethvt,scnfet CELLBOUND + mask-hints STDCELL + calma 81 4 + +#---------------------------------------------------------------- +# ESDID is a marker layer for ESD devices in the padframe I/O. +#---------------------------------------------------------------- + + layer ESDID + bloat-all mvnfetesd *mvndiff,*poly + bloat-all mvpfetesd *mvpdiff,*poly + grow 100 + mask-hints ESDID + calma 81 19 + +#---------------------------------------------------------------- +# NPNID and PNPID apply to bipolar transistors +#---------------------------------------------------------------- + + layer NPNID + bloat-all npn dnwell + mask-hints NPNID + calma 82 20 + + templayer pnparea pnp + grow 400 + + layer PNPID + bloat-all pnparea *psd + or pnparea + mask-hints PNPID + calma 82 44 + + layer PHOTO photo + calma 81 81 + +#---------------------------------------------------------------- +# RPM +#---------------------------------------------------------------- + + layer RPM + bloat-all xhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 86 20 + +#---------------------------------------------------------------- +# URPM (2kOhms/sq. poly implant) +#---------------------------------------------------------------- + + layer URPM + bloat-all uhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 79 20 + +#---------------------------------------------------------------- +# LDNTM (Tip implant for SONOS FETs) +#---------------------------------------------------------------- + + layer LDNTM + bloat-all nsonos *ndiff + grow 185 + grow 345 + shrink 345 + calma 11 44 + +#---------------------------------------------------------------- +# HVNTM (Tip implant for MV ndiff devices) +#---------------------------------------------------------------- + + templayer hvntm_block *mvpsd + grow 185 + + layer HVNTM + bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff + bloat-all mvvaractor *mvnsd + and-not hvntm_block + grow 185 + grow 345 + shrink 345 + and-not hvntm_block + mask-hints HVNTM + calma 125 20 + +#---------------------------------------------------------------- +# POLY +#---------------------------------------------------------------- + + layer POLY allpoly + calma 66 20 + + layer POLYTXT + labels allpoly + calma 66 5 + + layer POLYPIN + labels allpoly port + calma 66 16 + + layer POLYFILL polyfill + labels polyfill + calma 28 28 + +#---------------------------------------------------------------- +# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26) +#---------------------------------------------------------------- + + templayer thkox_area ed + grow 475 + or alldiffmv,mvvar + grow 185 + bloat-all alldiffmv nwell + grow 345 + shrink 345 + + templayer large_ptap_mv thkox_area + shrink 420 + grow 420 + + templayer small_ptap_mv thkox_area + and-not large_ptap_mv + # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um) + grow-min 840 + + layer HVI thkox_area,small_ptap_mv + bridge 700 600 + grow 345 + shrink 345 + mask-hints HVI + calma 75 20 + +#---------------------------------------------------------------- +# CONT (LICON) +#---------------------------------------------------------------- + + layer CONT allcont + squares-grid 0 170 170 + calma 66 44 + + # Contact for pres is different than other LICON contacts + # See rules LICON 1b, 1c (width/length) and 2b (spacing) + templayer xpc_horiz xpc + shrink 1007 + grow 1007 + + layer CONT xpc + and-not xpc_horiz + # Force long edge vertical for contacts narrower than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 190 520 80 2000 350 + calma 66 44 + + layer CONT xpc + and xpc_horiz + # Force long edge vertical for contacts wider than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 2000 350 80 190 520 + calma 66 44 + +#---------------------------------------------------------------- +# NPC (Nitride poly cut) +# surrounds CONT (LICON) on poly only (i.e., pc) +#---------------------------------------------------------------- + + # Avoids a common case of NPC bridges too close to other LICON shapes. + templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc + grow 90 + + layer NPC pc + squares-grid 0 170 170 + grow 100 + bridge 270 270 + and-not diffcutarea + bridge 270 270 + grow 130 + shrink 130 + mask-hints NPC + calma 95 20 + + # NPC is also generated on xhrpoly and uhrpoly resistors + + layer NPC xpc,xhrpoly,uhrpoly + # xpc surrounds precision_resistor by 0.095um + grow 95 + grow 130 + shrink 130 + calma 95 20 + +#---------------------------------------------------------------- +# Device markers +#---------------------------------------------------------------- + + layer DIFFRES rdn,mvrdn,rdp,mvrdp + calma 65 13 + + layer POLYRES mrp1 + calma 66 13 + + # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers + layer POLYSHORT rmp + calma 66 15 + + # POLYRES extends to edge of contact cut + layer POLYRES xhrpoly,uhrpoly + grow 80 + and xpc + or xhrpoly,uhrpoly + calma 66 13 + + layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt + # To be done: Expand to include anode, cathode, and guard ring + calma 81 23 + +#---------------------------------------------------------------- +# LI +#---------------------------------------------------------------- + layer LI allli + calma 67 20 + + layer LITXT + labels *locali,coreli + calma 67 5 + + layer LIPIN + labels *locali,coreli port + calma 67 16 + + layer LIRES rli + labels rli + calma 67 13 + + layer LIFILL lifill + labels lifill + calma 56 28 + +#---------------------------------------------------------------- +# MCON +#---------------------------------------------------------------- + layer MCON mcon + squares-grid 0 170 190 + calma 67 44 + +#---------------------------------------------------------------- +# MET1 +#---------------------------------------------------------------- + layer MET1 allm1 + calma 68 20 + + layer MET1TXT + labels allm1 + calma 68 5 + + layer MET1PIN + labels allm1 port + calma 68 16 + + layer MET1RES rm1 + labels rm1 + calma 68 13 + + layer MET1FILL m1fill + labels m1fill + calma 36 28 + +#---------------------------------------------------------------- +# VIA1 +#---------------------------------------------------------------- + layer VIA1 via1 + squares-grid 55 150 170 + calma 68 44 + + +#---------------------------------------------------------------- +# MET2 +#---------------------------------------------------------------- + layer MET2 allm2 + calma 69 20 + + layer MET2TXT + labels allm2 + calma 69 5 + + layer MET2PIN + labels allm2 port + calma 69 16 + + layer MET2RES rm2 + labels rm2 + calma 69 13 + + layer MET2FILL m2fill + labels m2fill + calma 41 28 + +#---------------------------------------------------------------- +# VIA2 +#---------------------------------------------------------------- + layer VIA2 via2 + squares-grid 40 200 200 + calma 69 44 + +#---------------------------------------------------------------- +# MET3 +#---------------------------------------------------------------- + layer MET3 allm3 + calma 70 20 + + layer MET3TXT + labels allm3 + calma 70 5 + + layer MET3PIN + labels allm3 port + calma 70 16 + + layer MET3RES rm3 + labels rm3 + calma 70 13 + + layer MET3FILL m3fill + labels m3fill + calma 34 28 + +#---------------------------------------------------------------- +# VIA3 +#---------------------------------------------------------------- + layer VIA3 via3 + or mimcc + squares-grid 60 200 200 + calma 70 44 + +#---------------------------------------------------------------- +# MET4 +#---------------------------------------------------------------- + layer MET4 allm4 + calma 71 20 + + layer MET4TXT + labels allm4 + calma 71 5 + + layer MET4PIN + labels allm4 port + calma 71 16 + + layer MET4RES rm4 + labels rm4 + calma 71 13 + + layer MET4FILL m4fill + labels m4fill + calma 51 28 + +#---------------------------------------------------------------- +# VIA4 +#---------------------------------------------------------------- + layer VIA4 via4 + or mim2cc + squares-grid 190 800 800 + calma 71 44 + +#---------------------------------------------------------------- +# MET5 +#---------------------------------------------------------------- + layer MET5 allm5,m5fill + calma 72 20 + + layer MET5TXT + labels allm5 + calma 72 5 + + layer MET5PIN + labels allm5 port + calma 72 16 + + layer MET5RES rm5 + labels rm5 + calma 72 13 + + layer MET5FILL m5fill + labels m5fill + calma 59 28 + + +#---------------------------------------------------------------- +# RDL +#---------------------------------------------------------------- + layer RDL *metrdl + calma 74 20 + + layer RDLTXT + labels *metrdl + calma 74 5 + + layer RDLPIN + labels *metrdl port + calma 74 16 + + layer PI1 *metrdl + and m5,glass + # Test only---needs GDS layer number + + layer UBM *metrdl + shrink 50000 + grow 40000 + # Test only---needs GDS layer number + + layer PI2 *metrdl + shrink 50000 + grow 25000 + # Test only---needs GDS layer number + + +#---------------------------------------------------------------- +# GLASS +#---------------------------------------------------------------- + layer GLASS glass + calma 76 20 + +#---------------------------------------------------------------- +# CAPM +#---------------------------------------------------------------- + layer CAPM *mimcap + labels mimcap + calma 89 44 + + layer CAPM2 *mimcap2 + labels mimcap2 + calma 97 44 + +#---------------------------------------------------------------- +# Chip top level marker for DRC latchup rules to check 15um +# distance to taps (otherwise 6um is used) +#---------------------------------------------------------------- + + layer LOWTAPDENSITY + bbox top + # Clear 200um for pads + 50um for required high tap density + # in critical area. + shrink 250000 + calma 81 14 + +#---------------------------------------------------------------- +# FILLBLOCK +#---------------------------------------------------------------- + layer FILLOBSFOM obsactive + calma 22 24 + + layer FILLOBSM1 fillblock,fillblock4 + calma 62 24 + + layer FILLOBSM2 fillblock,fillblock4 + calma 105 52 + + layer FILLOBSM3 fillblock,fillblock4 + calma 107 24 + + layer FILLOBSM4 fillblock,fillblock4 + calma 112 4 + + layer FILLOBSM5 fillblock,fillblock4 + calma 117 4 + + render DNWELL cwell -0.1 0.1 + render NWELL nwell 0.0 0.2062 + render DIFF ndiffusion 0.2062 0.12 + render TAP pdiffusion 0.2062 0.12 + render POLY polysilicon 0.3262 0.18 + render CONT via 0.5062 0.43 + render LI metal1 0.9361 0.10 + render MCON via 1.0361 0.34 + render MET1 metal2 1.3761 0.36 + render VIA1 via 1.7361 0.27 + render MET2 metal3 2.0061 0.36 + render VIA2 via 2.3661 0.42 + render MET3 metal4 2.7861 0.845 + render VIA3 via 3.6311 0.39 + render MET4 metal5 4.0211 0.845 + render VIA4 via 4.8661 0.505 + render MET5 metal6 5.3711 1.26 + render CAPM metal8 2.4661 0.2 + render CAPM2 metal9 3.7311 0.2 + render RDL metal7 11.8834 4.0 + +#---------------------------------------------------------------- +style drc +#---------------------------------------------------------------- +# NOTE: This style is used for DRC only, not for GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + + # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside + templayer dnwell_shrink dnwell + shrink 1030 + + templayer nwell_missing dnwell + grow 400 + and-not dnwell_shrink + and-not nwell + + templayer pwell_in_dnwell dnwell + and-not nwell + + # SONOS nFET devices must be in deep nwell + templayer dnwell_missing nsonos + and-not dnwell + + # SONOS nFET devices must be in cell with abutment box + templayer abutment_box + boundary + + templayer bbox_missing nsonos + and-not abutment_box + + # Make sure nwell covers varactor poly + templayer var_poly_no_nwell + bloat-all varactor,mvvaractor *poly + grow 150 + and-not nwell + + # Define MiM cap bottom plate for spacing rule + templayer mim_bottom + bloat-all *mimcap *metal3 + + # Define MiM2 cap bottom plate for spacing rule + templayer mim2_bottom + bloat-all *mimcap2 *metal4 + + # Define areas where mim2cc is inside the boundary of mimcc + # by more than the contact surround + templayer mim2_contact_overlap + bloat-all *mimcap2 mimcc + shrink 60 + and-not *mimcap2 + + # Note that metal fill is performed by the foundry and so is not + # an option for a cifoutput style. + + # Check latchup rule (15um minimum from tap LICON center to any + # non-tap diffusion. Note that to count as a tap, the diffusion + # must be contacted to LI + + templayer ptap_reach psc,mvpsc + and-not dnwell + # grow total is 15um. grow in 0.84um increments to ensure that + # no nwell ring is crossed + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 635 + and-not nwell,dnwell + + templayer ptap_missing *ndiff,*mvndiff + and-not dnwell + and-not ptap_reach + + templayer ntap_reach nsc,mvnsc + # grow total is 15um. grow in 1.27um increments to ensure that + # no nwell ring is crossed. There is no difference between + # ntaps in and out of deep nwell. + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 945 + and nwell,pnp + + templayer ntap_missing *pdiff,*mvpdiff + and-not pwell_in_dnwell + and-not ntap_reach + + templayer dptap_reach psc,mvpsc + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 635 + and-not nwell + and dnwell + + templayer dptap_missing *ndiff,*mvndiff + and dnwell + and-not dptap_reach + + templayer pdiff_crosses_dnwell dnwell + grow 20 + and-not dnwell + and allpdifflv,allpdiffmv + + # MV nwell must be 2um from any other nwell + templayer mvnwell + bloat-all alldiffmv nwell + grow-min 840 + bridge 700 600 + + # Simple spacing checks to lvnwell must use CIF-DRC rule + # Note that HVI may *abut* lvnwell; this can only be handled + # with mask-hints layers. + + templayer drawn_hvi + mask-hints HVI + + templayer allmvdiffnowell *mvndiff,*mvpsd + and-not drawn_hvi + + templayer nwell_or_hvi nwell,drawn_hvi + + templayer lvnwell nwell + and-not mvnwell + + # Check for low-voltage diffusion in high-voltage well + templayer lvdiff_in_mvnwell *pdiff,*pdiode,pdiffres,*nsd + or pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt + and mvnwell + + templayer nwell_with_tap + bloat-all nsc,mvnsc nwell,pnp + + templayer nwell_missing_tap nwell,pnp + and-not nwell_with_tap + + templayer tap_with_licon + bloat-all allpactivetap psd,mvpsd + bloat-all allnactivetap nsd,mvnsd + + templayer tap_missing_licon allnactivetap,allpactivetap + and-not tap_with_licon + + # Make sure varactor nwell contains no P diffusion + templayer pdiff_in_varactor_well + bloat-all varactor,mvvaractor nwell + and allpactive + + # HVNTM spacing requires recreating HVNTM + templayer hvntm_block *mvpsd + grow 185 + + templayer hvntm_generate + bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff + bloat-all mvvaractor *mvnsd + and-not hvntm_block + grow 185 + grow 345 + shrink 345 + and-not hvntm_block + + # RPM spacing checks require recreating RPM + templayer rpm_generate + bloat-all xhrpoly,uhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + + # Check distance RPM to NSDM + templayer rpm_nsd_check rpm_generate + grow 325 + and allndifflv,allndiffmv + + # Check distance RPM to (unrelated) POLY + templayer rpm_poly_check rpm_generate + grow 200 + and-not xhrpoly,uhrpoly,xpc + and allpoly + + # Check distance RPM to HVNTM + templayer rpm_hvntm_check rpm_generate + grow 385 + and allndiffmvnontap + + templayer m1_small_hole allm1,obsm1,obsmcon + close 140000 + + templayer m1_hole_empty m1_small_hole + and-not allm1,obsm1,obsmcon + + templayer m2_small_hole allm2,obsm2 + close 140000 + + templayer m2_hole_empty m2_small_hole + and-not allm2,obsm2 + + templayer m1_huge allm1 + shrink 1500 + grow 1500 + + templayer m1_large_halo m1_huge + grow 280 + and-not m1_huge + and allm1 + + templayer m2_huge allm2 + shrink 1500 + grow 1500 + + templayer m2_large_halo m2_huge + grow 280 + and-not m2_huge + and allm2 + + templayer m3_huge allm3 + shrink 1500 + grow 1500 + + templayer m3_large_halo m3_huge + grow 400 + and-not m3_huge + and allm3 + + templayer m4_huge allm4 + shrink 1500 + grow 1500 + + templayer m4_large_halo m4_huge + grow 400 + and-not m4_huge + and allm4 + + +#---------------------------------------------------------------- +style density +#---------------------------------------------------------------- +# Style used by scripts to check for fill density +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + + templayer fom_all alldiff,fomfill + + templayer poly_all allpoly,polyfill + + templayer li_all allli,lifill + + templayer m1_all allm1,m1fill + + templayer m2_all allm2,m2fill + + templayer m3_all allm3,m3fill + + templayer m4_all allm4,m4fill + + templayer m5_all allm5,m5fill + +#---------------------------------------------------------------- +style wafflefill variants (),(tiled) +#---------------------------------------------------------------- +# Style used by scripts for automatically generating fill layers +# NOTE: Be sure to generate output on flattened layout. +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + +#---------------------------------------------------------------- +# Generate and retain a layer representing the bounding box. +# +# For variant (): +# The bounding box is the full extent of geometry on the top level +# cell. +# +# For variant (tiled): +# Use with a script that breaks layout into flattened tiles and runs +# fill individually on each. The tiles should be larger than the +# step size, and each should draw a layer "comment" the size of the +# step box. +#---------------------------------------------------------------- + + variants () + templayer topbox + bbox top + + variants (tiled) + templayer topbox comment + # Each tile imposes the full keepout distance rule of + # 3um on all sides. + shrink 1500 + + variants * + +#---------------------------------------------------------------- +# Generate guard-band around nwells to keep FOM from crossing +# Spacing from LV nwell = Diff/Tap 9 = 0.34um +# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25) +# Enclosure by nwell = Diff/Tap 8 = 0.18um +#---------------------------------------------------------------- + + templayer mvnwell + bloat-all alldiffmv nwell + + templayer lvnwell allnwell + and-not mvnwell + + templayer well_shrink mvnwell + shrink 250 + or lvnwell + shrink 180 + templayer well_guardband allnwell + grow 340 + and-not well_shrink + +#--------------------------------------------------- +# Diffusion and poly keep-out areas +#--------------------------------------------------- + templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive + or rpw,pnp,npn + grow 500 + or well_guardband + + templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive + or rpw,pnp,npn + grow 1000 + +#--------------------------------------------------- +# FOM and POLY fill +#--------------------------------------------------- + templayer fomfill_pass1 topbox + # slots 0 4080 1320 0 4080 1320 1360 0 + slots 0 4080 1600 0 4080 1600 1360 0 + and-not obstruct_fom + and topbox + shrink 2035 + grow 2035 + +#--------------------------------------------------- + + templayer obstruct_poly_pass1 fomfill_pass1 + grow 300 + or obstruct_poly + templayer polyfill_pass1 topbox + slots 0 720 360 0 720 360 240 0 + and-not obstruct_poly_pass1 + and topbox + shrink 355 + grow 355 + +#--------------------------------------------------- + + templayer obstruct_fom_pass2 fomfill_pass1 + grow 1290 + or polyfill_pass1 + grow 300 + or obstruct_fom + templayer fomfill_pass2 topbox + slots 0 2500 1320 0 2500 1320 1360 0 + and-not obstruct_fom_pass2 + and topbox + shrink 1245 + grow 1245 + +#--------------------------------------------------- + + templayer obstruct_poly_coarse polyfill_pass1 + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_coarse topbox + slots 0 720 360 0 720 360 240 120 + and-not obstruct_poly_coarse + and topbox + shrink 355 + grow 355 + +#--------------------------------------------------- + templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_medium topbox + slots 0 540 360 0 540 360 240 100 + and-not obstruct_poly_medium + and topbox + shrink 265 + grow 265 + +#--------------------------------------------------- + templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_fine topbox + slots 0 480 360 0 480 360 240 200 + and-not obstruct_poly_fine + and topbox + shrink 235 + grow 235 + +#--------------------------------------------------- + + templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2 + grow 1290 + or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine + grow 300 + or obstruct_fom + templayer fomfill_coarse topbox + slots 0 1500 1320 0 1500 1320 1360 0 + and-not obstruct_fom_coarse + and topbox + shrink 745 + grow 745 + +#--------------------------------------------------- + + templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse + grow 1290 + or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine + grow 300 + or obstruct_fom + templayer fomfill_fine topbox + slots 0 500 400 0 500 400 160 0 + and-not obstruct_fom_fine + and topbox + shrink 245 + grow 245 + +#--------------------------------------------------- + layer FOMFILL fomfill_pass1 + or fomfill_pass2 + or fomfill_coarse + or fomfill_fine + calma 23 28 + + layer POLYFILL polyfill_pass1 + or polyfill_coarse + or polyfill_medium + or polyfill_fine + calma 28 28 + +#--------------------------------------------------------- +# LI fill +# Note requirement that LI fill may not overlap (non-fill) +# diff or poly. +#--------------------------------------------------------- + + templayer obstruct_li_coarse allli,obsli,lifill,fillblock,fillblock4 + grow 2800 + or alldiff,allpoly + grow 200 + templayer lifill_coarse topbox + # slots 0 3000 650 0 3000 650 700 0 + slots 0 3000 900 0 3000 900 700 0 + and-not obstruct_li_coarse + and topbox + shrink 1495 + grow 1495 + + templayer obstruct_li_medium allli,obsli,lifill,fillblock,fillblock4 + grow 2500 + or lifill_coarse + grow 300 + or alldiff,allpoly + grow 200 + templayer lifill_medium topbox + slots 0 1500 500 0 1500 500 700 0 + and-not obstruct_li_medium + and topbox + shrink 745 + grow 745 + + templayer obstruct_li_fine allli,obsli,lifill,fillblock,fillblock4 + or lifill_coarse,lifill_medium + grow 300 + or alldiff,allpoly + grow 200 + templayer lifill_fine topbox + slots 0 580 500 0 580 500 700 0 + and-not obstruct_li_fine + and topbox + shrink 285 + grow 285 + + layer LIFILL lifill_coarse + or lifill_medium + or lifill_fine + calma 56 28 + +#--------------------------------------------------- +# MET1 fill +#--------------------------------------------------- + + templayer obstruct_m1_coarse allm1,obsm1,m1fill,fillblock,fillblock4 + grow 3000 + templayer met1fill_coarse topbox + # slots 0 2000 200 0 2000 200 700 0 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m1_coarse + and topbox + shrink 995 + grow 995 + + templayer obstruct_m1_medium allm1,obsm1,m1fill,fillblock,fillblock4 + grow 2800 + or met1fill_coarse + grow 200 + templayer met1fill_medium topbox + slots 0 1000 200 0 1000 200 700 0 + and-not obstruct_m1_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m1_fine allm1,obsm1,m1fill,fillblock,fillblock4 + grow 300 + or met1fill_coarse,met1fill_medium + grow 200 + templayer met1fill_fine topbox + slots 0 580 200 0 580 200 700 0 + and-not obstruct_m1_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m1_veryfine allm1,obsm1,m1fill,fillblock,fillblock4 + grow 100 + or met1fill_coarse,met1fill_medium,met1fill_fine + grow 200 + templayer met1fill_veryfine topbox + slots 0 300 200 0 300 200 100 50 + and-not obstruct_m1_veryfine + and topbox + shrink 145 + grow 145 + + layer MET1FILL met1fill_coarse + or met1fill_medium + or met1fill_fine + or met1fill_veryfine + calma 36 28 + +#--------------------------------------------------- +# MET2 fill +#--------------------------------------------------- + templayer obstruct_m2 allm2,obsm2,m2fill,fillblock,fillblock4 + grow 3000 + templayer met2fill_coarse topbox + # slots 0 2000 200 0 2000 200 700 350 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m2 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m2_medium allm2,obsm2,m2fill,fillblock,fillblock4 + grow 2800 + or met2fill_coarse + grow 200 + templayer met2fill_medium topbox + slots 0 1000 200 0 1000 200 700 350 + and-not obstruct_m2_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m2_fine allm2,obsm2,m2fill,fillblock,fillblock4 + grow 300 + or met2fill_coarse,met2fill_medium + grow 200 + templayer met2fill_fine topbox + slots 0 580 200 0 580 200 700 350 + and-not obstruct_m2_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m2_veryfine allm2,obsm2,m2fill,fillblock,fillblock4 + grow 100 + or met2fill_coarse,met2fill_medium,met2fill_fine + grow 200 + templayer met2fill_veryfine topbox + slots 0 300 200 0 300 200 100 100 + and-not obstruct_m2_veryfine + and topbox + shrink 145 + grow 145 + + layer MET2FILL met2fill_coarse + or met2fill_medium + or met2fill_fine + or met2fill_veryfine + calma 41 28 + +#--------------------------------------------------- +# MET3 fill +#--------------------------------------------------- + templayer obstruct_m3 allm3,glass,obsm3,m3fill,fillblock,fillblock4 + grow 3000 + templayer met3fill_coarse topbox + # slots 0 2000 300 0 2000 300 700 700 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m3 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m3_medium allm3,glass,obsm3,m3fill,fillblock,fillblock4 + grow 2700 + or met3fill_coarse + grow 300 + templayer met3fill_medium topbox + slots 0 1000 300 0 1000 300 700 700 + and-not obstruct_m3_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m3_fine allm3,glass,obsm3,m3fill,fillblock,fillblock4 + grow 200 + or met3fill_coarse,met3fill_medium + grow 300 + templayer met3fill_fine topbox + slots 0 580 300 0 580 300 700 700 + and-not obstruct_m3_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m3_veryfine allm3,glass,obsm3,m3fill,fillblock,fillblock4 + # Note: Adding 0.1 to waffle rule to clear wide spacing rule + grow 100 + or met3fill_coarse,met3fill_medium,met3fill_fine + grow 300 + templayer met3fill_veryfine topbox + slots 0 400 300 0 400 300 150 200 + and-not obstruct_m3_veryfine + and topbox + shrink 195 + grow 195 + + layer MET3FILL met3fill_coarse + or met3fill_medium + or met3fill_fine + or met3fill_veryfine + calma 34 28 + +#--------------------------------------------------- +# MET4 fill +#--------------------------------------------------- + templayer obstruct_m4 glass + grow 2500 + or allm4,obsm4,m4fill,fillblock,fillblock4 + grow 3000 + templayer met4fill_coarse topbox + # slots 0 2000 300 0 2000 300 700 1050 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m4 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m4_medium glass + grow 2500 + or allm4,obsm4,m4fill,fillblock,fillblock4 + grow 2700 + or met4fill_coarse + grow 300 + templayer met4fill_medium topbox + slots 0 1000 300 0 1000 300 700 1050 + and-not obstruct_m4_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m4_fine glass + grow 5000 + or allm4,obsm4,m4fill,fillblock,fillblock4 + grow 200 + or met4fill_coarse,met4fill_medium + grow 300 + templayer met4fill_fine topbox + slots 0 580 300 0 580 300 700 1050 + and-not obstruct_m4_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m4_veryfine glass + grow 5100 + or allm4,obsm4,m4fill,fillblock,fillblock4 + # Note: Adding 0.1 to waffle rule to clear wide spacing rule + grow 100 + or met4fill_coarse,met4fill_medium,met4fill_fine + grow 300 + templayer met4fill_veryfine topbox + slots 0 400 300 0 400 300 150 300 + and-not obstruct_m4_veryfine + and topbox + shrink 195 + grow 195 + + layer MET4FILL met4fill_coarse + or met4fill_medium + or met4fill_fine + or met4fill_veryfine + calma 51 28 + +#--------------------------------------------------- +# MET5 fill +#--------------------------------------------------- + templayer obstruct_m5 allm5,glass,obsm5,m5fill,fillblock + grow 3000 + templayer met5fill_coarse topbox + slots 0 5000 1600 0 5000 1600 1000 100 + and-not obstruct_m5 + and topbox + shrink 2495 + grow 2495 + + templayer obstruct_m5_medium allm5,glass,obsm5,m5fill,fillblock + grow 1400 + or met5fill_coarse + grow 1600 + templayer met5fill_medium topbox + slots 0 3000 1600 0 3000 1600 1000 100 + and-not obstruct_m5_medium + and topbox + shrink 1495 + grow 1495 + + layer MET5FILL met5fill_coarse + or met5fill_medium + calma 59 28 + +style subcutout + # generates a new subcut layer from the cell boundary, with windows for existing subcut and dnwell + # should be used on a flattened layout + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + + templayer CELLBOUND + boundary + + templayer large_dnwell dnwell + grow 10 + + templayer large_isosub isosub + grow 10 + + layer SUBCUT CELLBOUND + grow 10 + and-not large_dnwell + and-not large_isosub + calma 81 53 +end + +#----------------------------------------------------------------------- +cifinput +#----------------------------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size +#----------------------------------------------------------------------- + +style sky130 variants (),(vendor),(nowell) + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels + + ignore NPC + ignore SEALID + ignore CAPID + ignore LDNTM + ignore HVNTM + ignore POLYMOD + ignore LOWTAPDENSITY + ignore FILLOBSPOLY + ignore FILLOBSFOM + ignore MET5BLOCK + ignore OUTLINE + ignore POLYCUT + ignore POLYGATE + ignore DIFFCUT + ignore HVNWELLID + ignore PADDIFFID + ignore PADMETALID + ignore PADCENTERID +variants (nowell) + ignore DNWELL + ignore SUBCUT + ignore NWELL + ignore PWRES + ignore NPNID + ignore PNPID + ignore PHOTO + ignore SUBTXT + ignore WELLTXT + ignore SUBPIN + ignore WELLPIN + +variants (),(vendor) + layer pnp NWELL,WELLTXT,WELLPIN + and PNPID + labels NWELL + labels WELLPIN port + labels WELLTXT text + + layer nwell NWELL,WELLTXT,WELLPIN + and-not PNPID + labels NWELL + labels WELLPIN port + labels WELLTXT text + + templayer nwellarea NWELL + copyup nwelcheck + + # Copy nwell areas up for diffusion checks + templayer xnwelcheck nwelcheck + copyup nwelcheck + + # Always draw pwell under p-tap and n-diff. This is not always + # necessary but works better with deep nwell for correct extraction. + layer pwell TAP,DIFF + and-not NWELL,nwelcheck + grow 130 + or SUBTXT,SUBPIN + grow 420 + shrink 420 + labels SUBPIN port + labels SUBTXT text + + layer dnwell DNWELL + labels DNWELL + + layer isosub SUBCUT + labels SUBCUT + + layer npn DNWELL + and-not NWELL,nwelcheck + and NPNID + + layer photo DNWELL + and PHOTO + + layer rpw PWRES + and DNWELL + labels PWRES + +variants * + templayer hvarea HVI + copyup hvcheck + + # Copy high-voltage (HVI) areas up for diffusion checks + templayer xhvcheck hvcheck + copyup hvcheck + + templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and-not NWELL,nwelcheck + and-not PSDM + and-not DIODE + and-not DIFFRES + and-not HVI,hvcheck + and NSDM + and-not CORELI + copyup ndifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + variants * + + layer ndiff ndiffarea + + # Copy ndiff areas up for contact checks + templayer xndifcheck ndifcheck + copyup ndifcheck + + templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and-not NWELL,nwelcheck + and-not PSDM + and-not DIODE + and-not DIFFRES + and HVI,hvcheck + and NSDM + copyup ndifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer mvndiff mvndiffarea + + # Copy ndiff areas up for contact checks + templayer mvxndifcheck mvndifcheck + copyup mvndifcheck + + layer ndiode DIFF,barediff + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and-not LVTN + labels DIFF + + layer ndiodelvt DIFF,barediff + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and LVTN + labels DIFF + + templayer ndiodearea DIODE + and NSDM + and-not HVI,hvcheck + and-not NWELL,nwelcheck + copyup DIODE,NSDM + + layer ndiffres DIFFRES + and NSDM + and-not HVI,hvcheck + labels DIFF + + templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and NWELL,nwelcheck + and-not NSDM + and-not DIODE + and-not HVI,hvcheck + and PSDM + copyup pdifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer pdiff pdiffarea + + layer mvndiode DIFF,barediff + and NSDM + and DIODE + and HVI,hvcheck + and-not POLY + and-not PSDM + and-not LVTN + labels DIFF + + layer nndiode DIFF,barediff + and NSDM + and DIODE + and HVI,hvcheck + and-not POLY + and-not PSDM + and LVTN + labels DIFF + + templayer mvndiodearea DIODE + and NSDM + and HVI,hvcheck + and-not NWELL,nwelcheck + copyup DIODE,NSDM + + layer mvndiffres DIFFRES + and NSDM + and HVI,hvcheck + labels DIFF + + templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and NWELL,nwelcheck + and-not NSDM + and HVI,hvcheck + and-not DIODE + and-not DIFFRES + and PSDM + copyup mvpdifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer mvpdiff mvpdiffarea + + # Copy pdiff areas up for contact checks + templayer xpdifcheck pdifcheck + copyup pdifcheck + + layer pdiode DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodelvt DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodehvt DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and HVTP + and DIODE + labels DIFF + + templayer pdiodearea DIODE + and PSDM + and-not HVI,hvcheck + copyup DIODE,PSDM + + # Define pfet areas as known pdiff, regardless of the presence of a well. + + templayer pfetarea DIFF,barediff + and POLY + or baretrans + and-not NSDM + and-not HVI,hvcheck + + layer pfet pfetarea + and-not LVTN + and-not HVTP + and-not STDCELL + and-not COREID + labels DIFF + + layer scpfet pfetarea + and-not LVTN + and-not HVTP + and STDCELL + and-not COREID + labels DIFF + + layer scpfethvt pfetarea + and-not LVTN + and HVTP + and STDCELL + labels DIFF + + layer ppu pfetarea + and-not LVTN + and HVTP + and COREID + # Shrink-grow operation eliminates the smaller parasitie device + # shrink 70 + # grow 70 + labels DIFF + + layer pfetlvt pfetarea + and LVTN + labels DIFF + + layer pfetmvt pfetarea + and HVTR + labels DIFF + + layer pfethvt pfetarea + and HVTP + and-not STDCELL + and-not COREID + labels DIFF + + # Always force nwell under pfet (nwell encloses pdiff by 0.18) + layer nwell pfetarea + and-not COREID + grow 180 + + # Copy mvpdiff areas up for contact checks + templayer mvxpdifcheck mvpdifcheck + copyup mvpdifcheck + + layer mvpdiode DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and HVI,hvcheck + and DIODE + labels DIFF + + templayer mvpdiodearea DIODE + and PSDM + and HVI,hvcheck + copyup DIODE,PSDM + + # Define pfet areas as known pdiff, + # regardless of the presence of a + # well. + + templayer mvpfetarea DIFF,barediff + and POLY + or baretrans + and-not NSDM + and HVI,hvcheck + + layer mvpfet mvpfetarea + and-not ESDID + labels DIFF + + layer mvpfetesd mvpfetarea + and ESDID + labels DIFF + + layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff + and-not NSDM + and-not POLY + and-not HVI,hvcheck + and-not DIODE + and-not DIFFRES + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer pdiffres DIFFRES + and PSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + labels DIFF + + layer nfet DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not HVI,hvcheck + and-not LVTN + and-not SONOS + and-not STDCELL + and-not COREID + labels DIFF + + layer scnfet DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and-not HVI,hvcheck + and-not LVTN + and-not SONOS + and STDCELL + labels DIFF + + layer npass DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and COREID + labels DIFF + + layer npd DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and COREID + # Shrink-grow operation eliminates the smaller npass device + shrink 70 + grow 70 + labels DIFF + + # Devices abutting tap under gate are officially npd, not npass + layer npd TAP + grow 100 + and DIFF + and POLY + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and COREID + labels DIFF + + layer nfetlvt DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not HVI,hvcheck + and LVTN + and-not SONOS + labels DIFF + + layer nsonos DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not HVI,hvcheck + and LVTN + and SONOS + labels DIFF + + templayer nsdarea TAP,DIFF + and NSDM + and NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and-not CORELI + copyup nsubcheck + + layer nsd nsdarea + labels TAP + + layer nsd TAP,TAPTXT + and NSDM + and-not POLY + and-not HVI,hvcheck + labels TAP + labels TAPTXT text + + layer corenvar TAP + and NSDM + and POLY + and COREID + labels TAP + + templayer nsdexpand nsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer xnsubcheck nsubcheck + copyup nsubcheck + + templayer psdarea TAP,DIFF + and PSDM + and-not NWELL,nwelcheck + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not pfetexpand + copyup psubcheck + + layer psd psdarea + labels TAP + + layer psd TAP + and PSDM + and-not POLY + and-not HVI,hvcheck + labels TAP + labels TAPTXT text + + layer corepvar TAP + and PSDM + and POLY + and COREID + labels TAP + + templayer psdexpand psdarea + grow 500 + + layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff + and-not NSDM + and-not POLY + and HVI,hvcheck + and mvpfetexpand + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer mvpdiffres DIFFRES + and PSDM + and NWELL,nwelcheck + and HVI,hvcheck + and-not mvrdpioedge + labels DIFF + + templayer mvnfetarea DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not LVTN + and HVI,hvcheck + grow 350 + + templayer mvnnfetarea DIFF,TAP,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and LVTN + and HVI,hvcheck + and-not mvnfetarea + + layer mvnfetesd DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and HVI,hvcheck + and ESDID + and-not mvnnfetarea + labels DIFF + + layer mvnfet DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and HVI,hvcheck + and-not ESDID + and-not mvnnfetarea + labels DIFF + + layer nnfet mvnnfetarea + and LVID + labels DIFF + + layer mvnnfet mvnnfetarea + and-not LVID + labels DIFF + + templayer mvnsdarea TAP,DIFF + and NSDM + and NWELL,nwelcheck + and-not POLY + and-not PSDM + and HVI,hvcheck + copyup mvnsubcheck + + layer mvnsd mvnsdarea + labels TAP + + layer mvnsd TAP,TAPTXT + and NSDM + and HVI,hvcheck + labels TAP + labels TAPTXT text + + # Fill in FET under extended drain + layer mvpfet EDID + and POLY + and-not DIFF + and-not TAP + and-not NWELL + + layer mvnfet EDID + and POLY + and-not DIFF + and-not TAP + and NWELL + + # Restrict where nwell is merged + templayer ldmos_nwell EDID + grow 1200 + and NWELL + + # Remove or add well under extended FET gate + layer nwell EDID + and POLY + and DIFF + and PSDM + grow 685 + or ldmos_nwell + grow 420 + shrink 420 + + layer pwell EDID + and POLY + and DIFF + and NSDM + grow 660 + grow 420 + shrink 420 + + layer ed EDID + and-not POLY + and-not DIFF + and-not TAP + + templayer mvnsdexpand mvnsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer mvxnsubcheck mvnsubcheck + copyup mvnsubcheck + + templayer mvpsdarea TAP,DIFF,barediff + and PSDM + and-not NWELL,nwelcheck + and-not POLY + and-not NSDM + and HVI,hvcheck + and-not mvpfetexpand + copyup mvpsubcheck + + layer mvpsd mvpsdarea + labels DIFF + + layer mvpsd TAP,TAPTXT + and PSDM + and HVI,hvcheck + labels TAP + labels TAPTXT text + + templayer mvpsdexpand mvpsdarea + grow 500 + + # Copy psub areas up for contact checks + templayer xpsubcheck psubcheck + copyup psubcheck + + templayer mvxpsubcheck mvpsubcheck + copyup mvpsubcheck + + layer psd TAP + and-not PSDM + and-not NSDM + and-not POLY + and-not HVI,hvcheck + and-not pfetexpand + and psdexpand + + layer nsd TAP + and-not PSDM + and-not NSDM + and-not POLY + and-not HVI,hvcheck + and nsdexpand + + layer mvpsd TAP + and-not PSDM + and-not NSDM + and-not POLY + and HVI,hvcheck + and-not mvpfetexpand + and mvpsdexpand + + layer mvnsd TAP + and-not PSDM + and-not NSDM + and-not POLY + and HVI,hvcheck + and mvnsdexpand + +# The following recipes deal with DIFFRES layers expanded over large areas +# outside the resistor. Find areas which may have been accidentally +# captured as a resistor which were supposed to be transistors. + + templayer diffresarea DIFFRES + and-not HVI,hvcheck + grow 3000 + + layer pfet DIFF + and diffresarea + and POLY + and-not NSDM + and-not STDCELL + and-not HVI + + layer mvpfet DIFF + and diffresarea + and POLY + and-not NSDM + and-not STDCELL + and HVI + + layer scpfet STDCELL + and POLY + and diffresarea + and DIFF + and-not NSDM + and-not HVTP + + layer scpfethvt STDCELL + and POLY + and diffresarea + and DIFF + and-not NSDM + and HVTP + +# End of resistor area hack + + templayer xpolyterm RPM,URPM + and POLY + and-not POLYRES + # add back the 0.08um contact surround in the direction of the resistor + grow 80 + and POLY + + layer xpc xpolyterm + + templayer polyarea POLY,POLYTXT,POLYPIN + and-not POLYRES + and-not POLYSHORT + and-not DIFF + and-not TAP + and-not RPM + and-not URPM + + templayer polycontarea polyarea + # Remove areas too small for a contact + shrink 130 + grow 130 + copyup polycheck + + layer poly polyarea + labels POLY + labels POLYPIN port + labels POLYTXT text + + # Copy (non-resistor) poly areas up for contact checks + templayer xpolycheck polycheck + copyup polycheck + + layer mrp1 POLYRES + and POLY + and-not RPM + and-not URPM + labels POLY + + layer rmp POLYSHORT + and POLY + labels POLY + + layer xhrpoly RPM + and POLYRES + and POLY + and-not URPM + and PSDM + and NPC + and-not xpolyterm + labels POLY + + layer uhrpoly URPM + and POLYRES + and POLY + and-not RPM + and NPC + and-not xpolyterm + labels POLY + + templayer ndcbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and-not NWELL,nwelcheck + and-not HVI,hvcheck + + layer ndc ndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndcbase + labels CONT + + templayer nscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and NSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + + layer nsc nscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nscbase + labels CONT + + templayer pdcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + + layer pdc pdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcbase + labels CONT + + templayer pdcnowell CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and pfetexpand + and-not HVI,hvcheck + + layer pdc pdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcnowell + labels CONT + + templayer pscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and PSDM + and-not NWELL,nwelcheck + and-not pfetexpand + and-not HVI,hvcheck + + layer psc pscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pscbase + labels CONT + + templayer pcbase CONT + or barecont + and LI + or barelicont + and POLY + and-not DIFF + and-not RPM,URPM + + layer pc pcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pcbase + labels CONT + + templayer ndicbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and-not LVTN + + layer ndic ndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndicbase + labels CONT + + templayer ndilvtcbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and LVTN + + layer ndilvtc ndilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndilvtcbase + labels CONT + + templayer pdicbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and-not HVTP + + layer pdic pdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdicbase + labels CONT + + templayer pdilvtcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and LVTN + and-not HVTP + + layer pdilvtc pdilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdilvtcbase + labels CONT + + templayer pdihvtcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and HVTP + + layer pdihvtc pdihvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdihvtcbase + labels CONT + + templayer mvndcbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and-not NWELL,nwelcheck + and HVI,hvcheck + + layer mvndc mvndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndcbase + labels CONT + + templayer mvnscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and NSDM + and NWELL,nwelcheck + and HVI,hvcheck + + layer mvnsc mvnscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnscbase + labels CONT + + templayer mvpdcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and NWELL,nwelcheck + and HVI,hvcheck + + layer mvpdc mvpdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcbase + labels CONT + + templayer mvpdcnowell CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and mvpfetexpand + and MET1 + and HVI,hvcheck + + layer mvpdc mvpdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcnowell + labels CONT + + templayer mvpscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and PSDM + and-not NWELL,nwelcheck + and-not mvpfetexpand + and HVI,hvcheck + + layer mvpsc mvpscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpscbase + labels CONT + + templayer mvndicbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not POLY + and-not PSDM + and-not LVTN + and HVI,hvcheck + + layer mvndic mvndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndicbase + labels CONT + + templayer nndicbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not POLY + and-not PSDM + and LVTN + and HVI,hvcheck + + layer nndic nndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nndicbase + labels CONT + + templayer mvpdicbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and HVI,hvcheck + + layer mvpdic mvpdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdicbase + labels CONT + + layer fomfill FOMFILL + labels FOMFILL + + layer polyfill POLYFILL + labels POLYFILL + + layer coreli LI,LITXT,LIPIN + and-not LIRES,LISHORT + and COREID + labels LI + labels LIPIN port + labels LITXT text + + layer locali LI,LITXT,LIPIN + and-not LIRES,LISHORT + and-not COREID + labels LI + labels LIPIN port + labels LITXT text + + layer rli LI + and LIRES,LISHORT + labels LIRES,LISHORT + + layer lifill LIFILL + labels LIFILL + + layer mcon MCON + grow 95 + shrink 95 + shrink 85 + grow 85 + or MCON + labels MCON + + layer m1 MET1,MET1TXT,MET1PIN + and-not MET1RES,MET1SHORT + labels MET1 + labels MET1PIN port + labels MET1TXT text + + layer rm1 MET1 + and MET1RES,MET1SHORT + labels MET1RES,MET1SHORT + + layer m1fill MET1FILL + labels MET1FILL + + layer mimcap MET3 + and CAPM + labels CAPM + + layer mimcc VIA3 + and CAPM + grow 60 + grow 40 + shrink 40 + labels CAPM + + layer mimcap2 MET4 + and CAPM2 + labels CAPM2 + + layer mim2cc VIA4 + and CAPM2 + grow 190 + grow 210 + shrink 210 + labels CAPM2 + + + + templayer m2cbase VIA1 + and-not COREID + grow 5 + or VIA1 + grow 50 + + layer m2c m2cbase + grow 30 + shrink 30 + shrink 130 + grow 130 + or m2cbase + + layer m2 MET2,MET2TXT,MET2PIN + and-not MET2RES,MET2SHORT + labels MET2 + labels MET2PIN port + labels MET2TXT text + + layer rm2 MET2 + and MET2RES,MET2SHORT + labels MET2RES,MET2SHORT + + layer m2fill MET2FILL + labels MET2FILL + + templayer m3cbase VIA2 + grow 40 + + layer m3c m3cbase + grow 60 + shrink 60 + shrink 140 + grow 140 + or m3cbase + + layer m3 MET3,MET3TXT,MET3PIN + and-not MET3RES,MET3SHORT + labels MET3 + labels MET3PIN port + labels MET3TXT text + + layer rm3 MET3 + and MET3RES,MET3SHORT + labels MET3RES,MET3SHORT + + layer m3fill MET3FILL + labels MET3FILL + + + templayer via3base VIA3 + and-not CAPM + grow 60 + + layer via3 via3base + grow 40 + shrink 40 + shrink 160 + grow 160 + or via3base + + layer m4 MET4,MET4TXT,MET4PIN + and-not MET4RES,MET4SHORT + labels MET4 + labels MET4PIN port + labels MET4TXT text + + layer rm4 MET4 + and MET4RES,MET4SHORT + labels MET4RES,MET4SHORT + + layer m4fill MET4FILL + labels MET4FILL + + layer m5 MET5,MET5TXT,MET5PIN + and-not MET5RES,MET5SHORT + labels MET5 + labels MET5PIN port + labels MET5TXT text + + layer rm5 MET5 + and MET5RES,MET5SHORT + labels MET5RES,MET5SHORT + + layer m5fill MET5FILL + labels MET5FILL + + templayer via4base VIA4 + and-not CAPM2 + grow 190 + + layer via4 via4base + grow 210 + shrink 210 + shrink 590 + grow 590 + or via4base + + layer metrdl RDL,RDLTXT,RDLPIN + labels RDL + labels RDLPIN port + labels RDLTXT text + + # Find diffusion not covered in + # NSDM or PSDM and pull it into + # the next layer up + + templayer gentrans DIFF + and-not PSDM + and-not NSDM + and POLY + copyup baretrans + + templayer gendiff DIFF,TAP + and-not PSDM + and-not NSDM + and-not POLY + and-not COREID + copyup barediff + + # Handle contacts found by copyup + + templayer ndiccopy CONT + and LI + and DIODE + and DIFF + and-not NWELL,nwelcheck + and NSDM + and-not LVTN + and-not HVI,hvcheck + + layer ndic ndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndiccopy + labels CONT + + templayer mvndiccopy CONT + and LI + and DIODE + and DIFF + and-not NWELL,nwelcheck + and NSDM + and-not LVTN + and HVI,hvcheck + + layer mvndic mvndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndiccopy + labels CONT + + templayer pdiccopy CONT + and LI + and DIODE + and DIFF + and PSDM + and-not HVI,hvcheck + + layer pdic pdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdiccopy + labels CONT + + templayer mvpdiccopy CONT + and LI + and DIODE + and PSDM + and HVI,hvcheck + + layer mvpdic mvpdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdiccopy + labels CONT + + templayer ndccopy CONT + and ndifcheck + + layer ndc ndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndccopy + labels CONT + + templayer mvndccopy CONT + and mvndifcheck + + layer mvndc mvndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndccopy + labels CONT + + templayer pdccopy CONT + and pdifcheck + + layer pdc pdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdccopy + labels CONT + + templayer mvpdccopy CONT + and mvpdifcheck + + layer mvpdc mvpdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdccopy + labels CONT + + templayer pccopy CONT + and polycheck + + layer pc pccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pccopy + labels CONT + + templayer nsccopy CONT + and nsubcheck + + layer nsc nsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or nsccopy + labels CONT + + templayer mvnsccopy CONT + and mvnsubcheck + + layer mvnsc mvnsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnsccopy + labels CONT + + templayer psccopy CONT + and psubcheck + + layer psc psccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or psccopy + labels CONT + + templayer mvpsccopy CONT + and mvpsubcheck + + layer mvpsc mvpsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpsccopy + labels CONT + + # Find contacts not covered in + # metal and pull them into the + # next layer up + + templayer barelicont CONT + and LI + and-not DIFF,TAP + and-not POLY + and-not DIODE + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + and-not CORELI + copyup barelicont + + templayer barecont CONT + and-not LI + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + and-not CORELI + copyup barecont + + layer glass GLASS,PADTXT,PADPIN + labels GLASS + labels PADPIN port + labels PADTXT text + + templayer boundary BOUND,STDCELL,PADCELL + boundary + + layer comment LVSTEXT + labels LVSTEXT text + + layer comment TTEXT + labels TTEXT text + + layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4,FILLOBSM5 + labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4,FILLOBSM5 + + layer fillblock4 FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + and-not FILLOBSM5 + labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + +# MOS Varactor + + layer var POLY + and TAP + and NSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + and-not HVTP + # NOTE: Else forms a varactor that is not in the vendor netlist. + and-not COREID + labels POLY + + layer varhvt POLY + and TAP + and NSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + and HVTP + labels POLY + + layer mvvar POLY + and TAP + and NSDM + and NWELL,nwelcheck + and HVI,hvcheck + labels POLY + + calma NWELL 64 20 + calma DIFF 65 20 + calma TAP 65 44 + calma DNWELL 64 18 + calma SUBCUT 81 53 + calma PWRES 64 13 + # LVTN + calma LVTN 125 44 + # HVTR + calma HVTR 18 20 + # HVTP + calma HVTP 78 44 + # SONOS (TUNM) + calma SONOS 80 20 + # NSDM (NPLUS) + calma NSDM 93 44 + # PSDM (PPLUS) + calma PSDM 94 20 + # HVI (THKOX) + calma HVI 75 20 + # EDID + calma EDID 81 57 + # NPC + calma NPC 95 20 + # P+ POLY MASK + calma RPM 86 20 + calma URPM 79 20 + calma LDNTM 11 44 + calma HVNTM 125 20 + # Poly resistor ID mark + calma POLYRES 66 13 + # Diffusion resistor ID mark + calma DIFFRES 65 13 + calma POLY 66 20 + calma POLYMOD 66 83 + # 3.3V native FET ID mark + calma LVID 81 60 + # Diode ID mark + calma DIODE 81 23 + # Bipolar NPN mark + calma NPNID 82 20 + # Bipolar PNP mark + calma PNPID 82 44 + # Capacitor ID + calma CAPID 82 64 + # Core area ID mark + calma COREID 81 2 + # Photodiode ID mark + calma PHOTO 81 81 + # Standard cell ID mark + calma STDCELL 81 4 + # Padframe cell ID mark + calma PADCELL 81 3 + # Seal ring ID mark + calma SEALID 81 1 + # Low tap density ID mark + calma LOWTAPDENSITY 81 14 + # ESD area ID + calma ESDID 81 19 + # Various unused layers + calma OUTLINE 236 0 + calma POLYCUT 66 14 + calma POLYGATE 66 9 + calma DIFFCUT 65 14 + calma HVNWELLID 81 63 + calma MET5BLOCK 72 10 + calma PADDIFFID 81 6 + calma PADMETALID 81 8 + calma PADCENTERID 81 20 + + # LICON + calma CONT 66 44 + calma LI 67 20 + calma MCON 67 44 + + calma MET1 68 20 + calma VIA1 68 44 + calma MET2 69 20 + calma VIA2 69 44 + calma MET3 70 20 + calma VIA3 70 44 + calma MET4 71 20 + calma VIA4 71 44 + calma MET5 72 20 + calma RDL 74 20 + calma GLASS 76 20 + + calma SUBTXT 64 59 + calma PADTXT 76 5 + calma DIFFTXT 65 6 + calma TAPTXT 65 5 + calma WELLTXT 64 5 + calma LITXT 67 5 + calma POLYTXT 66 5 + calma MET1TXT 68 5 + calma MET2TXT 69 5 + calma MET3TXT 70 5 + calma MET4TXT 71 5 + calma MET5TXT 72 5 + calma RDLTXT 74 5 + + calma LIRES 67 13 + calma MET1RES 68 13 + calma MET2RES 69 13 + calma MET3RES 70 13 + calma MET4RES 71 13 + calma MET5RES 72 13 + + calma LIFILL 56 28 + calma MET1FILL 36 28 + calma MET2FILL 41 28 + calma MET3FILL 34 28 + calma MET4FILL 51 28 + calma MET5FILL 59 28 + + calma POLYSHORT 66 15 + calma LISHORT 67 15 + calma MET1SHORT 68 15 + calma MET2SHORT 69 15 + calma MET3SHORT 70 15 + calma MET4SHORT 71 15 + calma MET5SHORT 72 15 + + calma SUBPIN 122 16 + calma PADPIN 76 16 + calma DIFFPIN 65 16 + calma POLYPIN 66 16 + calma WELLPIN 64 16 + calma LIPIN 67 16 + calma MET1PIN 68 16 + calma MET2PIN 69 16 + calma MET3PIN 70 16 + calma MET4PIN 71 16 + calma MET5PIN 72 16 + calma RDLPIN 74 16 + + calma BOUND 235 4 + + calma LVSTEXT 83 44 + + calma CAPM 89 44 + calma CAPM2 97 44 + + calma FILLOBSM1 62 24 + calma FILLOBSM2 105 52 + calma FILLOBSM3 107 24 + calma FILLOBSM4 112 4 + calma FILLOBSM5 117 4 + calma FILLOBSFOM 22 24 + calma FILLOBSPOLY 33 24 + + calma FOMFILL 23 28 + calma POLYFILL 28 28 + calma LIFILL 56 28 + calma MET1FILL 36 28 + calma MET2FILL 41 28 + calma MET3FILL 34 28 + calma MET4FILL 51 28 + calma MET5FILL 59 28 + +#----------------------------------------------------------------------- + +style rdlimport + # This style is for reading shapes generated with the RDL layers + + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels no-reconnect-labels + + layer mrdl RDL + layer mrdlc RDLC + + calma RDL 10 0 + calma RDLC 20 0 + +end + +#----------------------------------------------------- +# Digital flow maze router cost parameters +#----------------------------------------------------- + +mzrouter +end + +#----------------------------------------------------- +# Vendor DRC rules +#----------------------------------------------------- + +drc + + style drc variants (fast),(full),(routing) + scalefactor 10 + cifstyle drc + + variants (fast),(full) + +#----------------------------- +# DNWELL +#----------------------------- + + width dnwell 3000 "Deep N-well width < %d (dnwell.2)" + spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)" + spacing allnwell dnwell 4500 surround_ok \ + "Deep N-well spacing to N-well < %d (nwell.7)" + + variants (full) + cifmaxwidth nwell_missing 0 bend_illegal \ + "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)" + cifmaxwidth dnwell_missing 0 bend_illegal \ + "SONOS nFET must be in Deep N-well (tunm.6a)" + + cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \ + "P+ diff cannot straddle Deep N-well (dnwell.5)" + variants (fast),(full) + + width photo 3000 "Photodiode width < %d (photo.2)" + spacing photo photo 5000 touching_ok "Photodiode spacing < %d (photo.3)" + spacing photo dnwell 5300 touching_illegal \ + "Photodiode spacing to deep nwell < %d (photo.4)" + +#----------------------------- +# NWELL +#----------------------------- + + width allnwell 840 "N-well width < %d (nwell.1)" + spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)" + + variants (full) + cifmaxwidth nwell_missing_tap 0 bend_illegal \ + "All nwells must contain metal-connected N+ taps (nwell.4)" + + cifspacing mvnwell lvnwell 2000 touching_illegal \ + "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)" + cifspacing mvnwell mvnwell 2000 touching_ok \ + "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)" + + cifmaxwidth lvdiff_in_mvnwell 0 bend_illegal \ + "All HV nwell can contain only HV diffusion (diff/tap.21)" + + variants (fast),(full) + +#----------------------------- +# DIFF +#----------------------------- + + width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \ + 150 "Diffusion width < %d (diff/tap.1)" + width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \ + "MV Diffusion width < %d (diff/tap.14)" + + width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)" + extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)" + extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)" + extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)" + extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)" + width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)" + spacing alldifflv,var,varhvt,corenvar,corepvar,fomfill \ + alldifflv,var,varhvt,corenvar,corepvar,fomfill 270 touching_ok \ + "Diffusion spacing < %d (diff/tap.3)" + spacing alldifflv,var,varhvt alldiffmv,mvvar 270 touching_illegal \ + "LV to MV Diffusion spacing < %d (diff/tap.3)" + spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \ + "MV Diffusion spacing < %d (diff/tap.15a)" + spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \ + "MV Diffusion to MV tap spacing < %d (diff/tap.3)" + spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \ + touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)" + spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \ + "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)" + spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \ + "N-Diffusion spacing to N-well < %d (diff/tap.9)" + spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \ + "N-Diffusion spacing to N-well < %d (diff/tap.9)" + spacing *psd allnwell 130 touching_illegal \ + "P-tap spacing to N-well < %d (diff/tap.11)" + spacing *mvpsd allnwell 130 touching_illegal \ + "P-tap spacing to N-well < %d (diff/tap.11)" + surround *nsd allnwell 180 absence_illegal \ + "N-well overlap of N-tap < %d (diff/tap.10)" + surround *mvnsd allnwell 330 absence_illegal \ + "N-well overlap of MV N-tap < %d (diff/tap.19)" + surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \ + "N-well overlap of P-Diffusion < %d (diff/tap.8)" + surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \ + "N-well overlap of P-Diffusion < %d (diff/tap.17)" + surround mvvar allnwell 560 absence_illegal \ + "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)" + spacing *mvndiode *mvndiode 1070 touching_ok \ + "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)" + +variants (full) + cifspacing allmvdiffnowell lvnwell 825 touching_illegal \ + "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)" + cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \ + "HVI to HVI or LV nwell spacing < %d (hvi.5)" +variants (fast),(full) + + spacing allnfets allpactivenonfet 270 touching_illegal \ + "nFET cannot abut P-diffusion (diff/tap.3)" + spacing allpfets allnactivenonfet 270 touching_illegal \ + "pFET cannot abut N-diffusion (diff/tap.3)" + + # Butting junction rules + edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)" + edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)" + edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)" + edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)" + + edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)" + edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)" + edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)" + edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)" + + # Sandwiched butting junction restrictions + edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)" + edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)" + + # Extended drain rules + edge4way space/a ed/a 5000 ~(space)/a 0 0 "LDNFET/LDPFET width < %d (denmos/depmos.2)" + edge4way (*mvndiff)/a mvnfet 1055 ~(ed)/a 0 0 "LDNFET length < %d (denmos.1)" + edge4way (*mvnsd)/a ed/a 2510 ~(*mvndiff)/a 0 0 \ + "LDNFET drain to source < %d (denmos.6 + denmos.3)" + edge4way (*mvpdiff)/a mvpfet 1050 ~(ed)/a 0 0 "LDPFET length < %d (depmos.1)" + edge4way (*mvpsd)/a ed/a 2110 ~(*mvpdiff)/a 0 0 \ + "LDPFET drain to source < %d (depmos.6 + depmos.3)" + + area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)" + area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)" + + angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)" + + variants (full) + cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)" + + # Latchup rules + cifmaxwidth ptap_missing 0 bend_illegal \ + "N-diff distance to P-tap must be < 15.0um (LU.2)" + cifmaxwidth dptap_missing 0 bend_illegal \ + "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)" + cifmaxwidth ntap_missing 0 bend_illegal \ + "P-diff distance to N-tap must be < 15.0um (LU.3)" + + variants (fast),(full) + +#----------------------------- +# POLY +#----------------------------- + + width allpoly,polyfill 150 "poly width < %d (poly.1a)" + spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)" + + spacing allpolynonfet,polyfill \ + *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \ + 75 corner_ok allfets \ + "poly spacing to Diffusion < %d (poly.4)" + spacing npres *nsd 480 touching_illegal \ + "poly resistor spacing to N-tap < %d (poly.9)" + overhang *ndiff,rndiff nfet,scnfet,npd,npass,nsonos 250 "N-Diffusion overhang of nFET < %d (poly.7)" + overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \ + "N-Diffusion overhang of nFET < %d (poly.7)" + overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)" + overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)" + overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)" + overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)" + rect_only allfets "No bends in transistors (poly.11)" + extend xpc/a xhrpoly,uhrpoly 2160 \ + "poly contact extends poly resistor by < %d (licon.1c + li.5)" + spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 210 touching_illegal \ + "Distance between precision resistors < %d (poly.2)" + spacing xhrpoly,uhrpoly,xpc *poly,allfets,mrp1,rmp 400 touching_illegal \ + "Distance from precision resistor to poly < %d (rpm.7 + rpm.3)" + + variants (fast) + + spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \ + "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)" + spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \ + "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)" + spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \ + "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)" + + # Minimum width requirement means actual spacing from res to ndiff has to be + # constructed from mask rules. These supercede the simpler checks. + + variants (full) + + cifmaxwidth rpm_nsd_check 0 bend_illegal \ + "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)" + cifmaxwidth rpm_poly_check 0 bend_illegal \ + "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)" + cifmaxwidth rpm_hvntm_check 0 bend_illegal \ + "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)" + + variants (fast),(full) + + angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)" + +#-------------------------------------------------------------------- +# HVTP +#-------------------------------------------------------------------- + + spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \ + 360 touching_illegal \ + "Min. spacing between pFET and HVTP < %d (hvtp.4)" + + spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \ + "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)" + +#-------------------------------------------------------------------- +# LVTN +#-------------------------------------------------------------------- + + spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \ + allfetsnolvt 360 touching_illegal \ + "Min. spacing between FET and LVTN < %d (lvtn.3a)" + + spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \ + 740 touching_illegal \ + "Min. spacing between LVTN and HVTP < %d (lvtn.9)" + + # Spacing across S/D direction requires edge rule + edge4way allfetsnolvt allactivenonfet 415 \ + ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \ + "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)" + +#-------------------------------------------------------------------- +# HVNTM +#-------------------------------------------------------------------- + +variants (full) + # This requires extra spacing of hvndiff if a ptap is in between + cifwidth hvntm_generate 700 "Width of HVNTM < %d (hvntm.1)" + cifspacing hvntm_generate hvntm_generate 700 touching_ok \ + "HVNTM spacing < %d (hvntm.2)" +variants * + +#-------------------------------------------------------------------- +# NPC (Nitride poly Cut) +#-------------------------------------------------------------------- + +# Layer NPC is defined automatically around poly contacts (grow 0.1um) + +#-------------------------------------------------------------------- +# CONT (LICON, contact between poly/diff and LI) +#-------------------------------------------------------------------- + + width ndc/li 170 "N-diffusion contact width < %d (licon.1)" + width nsc/li 170 "N-tap contact width < %d (licon.1)" + width pdc/li 170 "P-diffusion contact width < %d (licon.1)" + width psc/li 170 "P-tap contact width < %d (licon.1)" + width ndic/li 170 "N-diode contact width < %d (licon.1)" + width pdic/li 170 "P-diode contact width < %d (licon.1)" + width pc/li 170 "poly contact width < %d (licon.1)" + + width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)" + area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)" + area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)" + + width mvndc/li 170 "N-diffusion contact width < %d (licon.1)" + width mvnsc/li 170 "N-tap contact width < %d (licon.1)" + width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)" + width mvpsc/li 170 "P-tap contact width < %d (licon.1)" + width mvndic/li 170 "N-diode contact width < %d (licon.1)" + width mvpdic/li 170 "P-diode contact width < %d (licon.1)" + + spacing allpdiffcont allndiffcont 170 touching_illegal \ + "Diffusion contact spacing < %d (licon.2)" + spacing allndiffcont allndiffcont 170 touching_ok \ + "Diffusion contact spacing < %d (licon.2)" + spacing allpdiffcont allpdiffcont 170 touching_ok \ + "Diffusion contact spacing < %d (licon.2)" + spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)" + + spacing pc alldiff 190 touching_illegal \ + "poly contact spacing to diffusion < %d (licon.14)" + spacing pc allpdifflv,allpdiffmv 235 touching_illegal \ + "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)" + + spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \ + "Diffusion contact to gate < %d (licon.11)" + spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \ + "Diffusion contact to standard cell gate < %d (licon.11)" + spacing ndc,pdc npd,npass,ppu 40 touching_illegal \ + "Diffusion contact to SRAM gate < %d (licon.11)" + spacing ndc,pdc nsonos 75 touching_illegal \ + "Diffusion contact to SONOS gate < %d (licon.11)" + spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \ + "Diffusion contact to gate < %d (licon.11)" + spacing nsc varactor,varhvt 250 touching_illegal \ + "Diffusion contact to varactor gate < %d (licon.10)" + spacing mvnsc mvvar 250 touching_illegal \ + "Diffusion contact to varactor gate < %d (licon.10)" + + surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \ + "N-diffusion overlap of N-diffusion contact < %d (licon.5a)" + surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \ + 40 absence_illegal \ + "P-diffusion overlap of P-diffusion contact < %d (licon.5a)" + surround ndic/a *ndi 40 absence_illegal \ + "N-diode overlap of N-diode contact < %d (licon.5a)" + surround pdic/a *pdi 40 absence_illegal \ + "P-diode overlap of N-diode contact < %d (licon.5a)" + + spacing psc/a allnactivenontap 60 touching_illegal \ + "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)" + spacing nsc/a allpactivenontap 60 touching_illegal \ + "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)" + + surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \ + "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)" + surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \ + 60 directional \ + "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)" + surround ndic/a *ndi 60 directional \ + "N-diode overlap of N-diode contact < %d in one direction (licon.5c)" + surround pdic/a *pdi 60 directional \ + "P-diode overlap of N-diode contact < %d in one direction (licon.5c)" + + surround nsc/a *nsd,pdiff,corenvar 120 directional \ + "N-tap overlap of N-tap contact < %d in one direction (licon.7)" + surround psc/a *psd,ndiff,corepvar 120 directional \ + "P-tap overlap of P-tap contact < %d in one direction (licon.7)" + + surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \ + "N-diffusion overlap of N-diffusion contact < %d (licon.5a)" + surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \ + "P-diffusion overlap of P-diffusion contact < %d (licon.5a)" + surround mvndic/a *mvndi 40 absence_illegal \ + "N-diode overlap of N-diode contact < %d (licon.5a)" + surround mvpdic/a *mvpdi 40 absence_illegal \ + "P-diode overlap of N-diode contact < %d (licon.5a)" + + spacing mvpsc/a allndiffmvnontap 60 touching_illegal \ + "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)" + spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \ + "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)" + + surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \ + "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)" + surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \ + "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)" + surround mvndic/a *mvndi 60 directional \ + "N-diode overlap of N-diode contact < %d in one direction (licon.5c)" + surround mvpdic/a *mvpdi 60 directional \ + "P-diode overlap of N-diode contact < %d in one direction (licon.5c)" + + surround mvnsc/a *mvnsd 120 directional \ + "N-tap overlap of N-tap contact < %d in one direction (licon.7)" + surround mvpsc/a *mvpsd 120 directional \ + "P-tap overlap of P-tap contact < %d in one direction (licon.7)" + + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \ + "poly overlap of poly contact < %d (licon.8)" + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \ + "poly overlap of poly contact < %d in one direction (licon.8a)" + + exact_overlap (allcont)/a + +#------------------------------------------------------------- +# LI - Local interconnect layer +#------------------------------------------------------------- + +variants * + + width *li 170 "Local interconnect width < %d (li.1)" + width rli 290 "Local interconnect width < %d (li.7)" + + spacing *locali,rli *locali,rli,*obsli 170 touching_ok \ + "Local interconnect spacing < %d (li.3)" + + # Local interconnect in core (SRAM) cells has more relaxed rules. There are + # no special layers for the contacts in core cells, so they must be included + # in the rule. + width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \ + "Core local interconnect width < %d (li.c1)" + + spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \ + "Core local interconnect spacing < %d (li.c2)" + + surround pc/li *li,coreli 80 directional \ + "Local interconnect overlap of poly contact < %d in one direction (li.5)" + + surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \ + *li,rli,coreli 80 directional \ + "Local interconnect overlap of diffusion contact < %d in one direction (li.5)" + + area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)" + + angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)" + angles coreli 45 \ + "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)" + +#------------------------------------------------------------- +# MCON - Contact between local interconnect and metal1 +#------------------------------------------------------------- + + width mcon/m1 170 "mcon.width < %d (mcon.1)" + spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)" + + exact_overlap mcon/li + +#------------------------------------------------------------- +# METAL1 - +#------------------------------------------------------------- + + width *m1,rm1 140 "Metal1 width < %d (met1.1)" + spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)" + area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)" + + surround mcon/m1 *met1 30 absence_illegal \ + "Metal1 overlap of local interconnect contact < %d (met1.4)" + surround mcon/m1 *met1 60 directional \ + "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)" + + angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)" + +variants (fast),(full) + widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)" + widespacing *obsm1 3005 allm1 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)" + +variants (full) + cifmaxwidth m1_hole_empty 0 bend_illegal \ + "Min area of metal1 holes > 0.14um^2 (met1.7)" + + cifspacing m1_large_halo m1_large_halo 280 touching_ok \ + "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)" +variants * + +#-------------------------------------------------- +# VIA1 +#-------------------------------------------------- + + width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)" + spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)" + surround v1/m1 *m1,rm1 30 directional \ + "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)" + surround v1/m2 *m2,rm2 30 directional \ + "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)" + + exact_overlap v1/m1 + + +#-------------------------------------------------- +# METAL2 - +#-------------------------------------------------- + + width allm2,m2fill 140 "Metal2 width < %d (met2.1)" + spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)" + area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)" + + angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)" + +variants (fast),(full) + widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)" + widespacing obsm2 3005 allm2 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)" + +variants (full) + cifmaxwidth m2_hole_empty 0 bend_illegal \ + "Min area of metal2 holes > 0.14um^2 (met2.7)" + + cifspacing m2_large_halo m2_large_halo 280 touching_ok \ + "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)" +variants * + +#-------------------------------------------------- +# VIA2 +#-------------------------------------------------- + + width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)" + + spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)" + + surround v2/m2 *m2,rm2 45 directional \ + "Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)" + surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)" + + exact_overlap v2/m2 + +#-------------------------------------------------- +# METAL3 - +#-------------------------------------------------- + + width allm3,m3fill 300 "Metal3 width < %d (met3.1)" + spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)" + area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)" + + angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)" + +variants (fast),(full) + widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)" + widespacing obsm3 3005 allm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)" +variants (full) + cifspacing m3_large_halo m3_large_halo 400 touching_ok \ + "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)" +variants * + + +#-------------------------------------------------- +# VIA3 - Requires METAL5 Module +#-------------------------------------------------- + + width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)" + spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)" + surround v3/m3 *m3,rm3 30 directional \ + "Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)" + surround v3/m4 *m4,rm4 5 absence_illegal \ + "Metal4 overlap of via3 < %d (met4.3 - via3.4)" + + exact_overlap v3/m3 + +#----------------------------- +# METAL4 - METAL4 Module +#----------------------------- + +variants * + + width allm4,m4fill 300 "Metal4 width < %d (met4.1)" + spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)" + area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)" + + angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)" + +variants (fast),(full) + widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)" + widespacing obsm4 3005 allm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)" +variants (full) + cifspacing m4_large_halo m4_large_halo 400 touching_ok \ + "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)" +variants * + +#-------------------------------------------------- +# VIA4 - Requires METAL5 Module +#-------------------------------------------------- + + width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)" + spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)" + surround v4/m5 *m5,rm5 120 absence_illegal \ + "Metal5 overlap of via4 < %d (met5.3 - via4.4)" + + exact_overlap v4/m4 + +#----------------------------- +# METAL5 - METAL5 Module +#----------------------------- + + width allm5,m5fill 1600 "Metal5 width < %d (met5.1)" + spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)" + area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)" + + angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)" + + + +variants (full) + + width metrdl 10000 "RDL width < %d (rdl.1)" + spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)" + surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)" + spacing glass metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)" + +variants (fast),(full) + + +#-------------------------------------------------- +# NMOS, PMOS +#-------------------------------------------------- + + edge4way *poly allfetsstd 420 allfets 0 0 \ + "Transistor width < %d (diff/tap.2)" + edge4way *poly allfetsspecial 360 allfets 0 0 \ + "Transistor in standard cell width < %d (diff/tap.2)" + edge4way *poly npass,npd,nsonos 210 allfets 0 0 \ + "N-Transistor in SRAM core width < %d (diff/tap.2)" + edge4way *poly ppu 140 allfets 0 0 \ + "P-Transistor in SRAM core width < %d (diff/tap.2)" + + # Except: Note that standard cells allow transistor width minimum 0.36um + width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)" + + spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \ + "poly spacing to diffusion tap < %d (poly.5)" + spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \ + "poly spacing to diffusion tap < %d (poly.5)" + spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \ + "poly spacing to diffusion tap < %d (poly.5)" + spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \ + "poly spacing to diffusion tap < %d (poly.5)" + + edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \ + "Butting P-tap spacing to NMOS gate < %d (poly.6)" + edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \ + "Butting N-tap spacing to PMOS gate < %d (poly.6)" + edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \ + "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)" + edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \ + "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)" + + # No LV FETs in HV diff + spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \ + "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)" + + spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \ + "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)" + + # No HV FETs in LV diff + spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \ + "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)" + + spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \ + "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)" + + # Minimum length of MV FETs. Note that this is larger than the minimum + # width (0.29um), so an edge rule is required + + edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \ + "MV NMOS minimum length < %d (poly.13)" + + edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \ + "MV Varactor minimum length < %d (poly.13)" + + edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \ + "MV PMOS minimum length < %d (poly.13)" + +#-------------------------------------------------- +# mrp1 (N+ poly resistor) +#-------------------------------------------------- + + width mrp1 330 "mrp1 resistor width < %d (poly.3)" + +#-------------------------------------------------- +# xhrpoly (P+ poly resistor) +# uhrpoly (P+ poly resistor, 2kOhm/sq) +#-------------------------------------------------- + + # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27. + width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)" + width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)" + + spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \ + "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)" + + spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing mrp1 *poly 480 touching_ok \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \ + "Poly resistor spacing to diffusion < %d (poly.9)" + +#------------------------------------ +# nsonos +#------------------------------------ + +variants (full) + cifmaxwidth bbox_missing 0 bend_illegal \ + "SONOS transistor must be in cell with abutment box (tunm.8)" +variants (fast),(full) + +#------------------------------------ +# MOS Varactor device rules +#------------------------------------ + + overhang *nsd var,varhvt 250 \ + "N-Tap overhang of Varactor < %d (var.4)" + + overhang *mvnsd mvvar 250 \ + "N-Tap overhang of Varactor < %d (var.4)" + + width var,varhvt,mvvar 180 "Varactor length < %d (var.1)" + extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)" + +variants (full) + cifmaxwidth var_poly_no_nwell 0 bend_illegal \ + "N-well overlap of varactor poly < 0.15um (varac.5)" + + cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \ + "Varactor N-well must not contain P+ diffusion (varac.7)" +variants (fast),(full) + +#----------------------------------------------------------- +# MiM CAP (CAPM) - +#----------------------------------------------------------- + + width *mimcap 1000 "MiM cap width < %d (capm.1)" + spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)" + spacing *mimcap via3/m3 80 touching_illegal \ + "MiM cap spacing to via3 < %d (capm.5 - via3.4)" + surround *mimcc *mimcap 80 absence_illegal \ + "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)" + rect_only *mimcap "MiM cap must be rectangular (capm.7) + + surround *mimcap *metal3/m3 140 absence_illegal \ + "Metal3 must surround MiM cap by %d (capm.3)" + spacing via2 *mimcap 100 touching_illegal \ + "MiM cap spacing to via2 < %d (capm.8 - via2.4)" + spacing *mimcap *metal3/m3 500 surround_ok \ + "MiM cap spacing to unrelated metal3 < %d (capm.11)" + +variants (full) + cifspacing mim_bottom mim_bottom 1200 touching_ok \ + "MiM cap bottom plate spacing < %d (capm.2b)" +variants (fast),(full) + + # MiM cap contact rules (VIA3) + + width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)" + spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)" + surround mimcc/m4 *m4 5 directional \ + "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)" + exact_overlap mimcc/c1 + + width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)" + spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)" + spacing *mimcap2 via4/m4 10 touching_illegal \ + "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)" + surround *mim2cc *mimcap2 10 absence_illegal \ + "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)" + rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7) + + surround *mimcap2 *metal4/m4 140 absence_illegal \ + "Metal4 must surround MiM2 cap by %d (cap2m.3)" + spacing via3 *mimcap2 80 touching_illegal \ + "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)" + spacing *mimcap2 *metal4/m4 500 surround_ok \ + "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)" + +variants (full) + cifmaxwidth mim2_contact_overlap 0 bend_illegal \ + "MiM2 cap contact must not cross MiM cap contact (cap2m.8)" + + cifspacing mim2_bottom mim2_bottom 1200 touching_ok \ + "MiM2 cap bottom plate spacing < %d (cap2m.2b)" +variants (fast),(full) + + # MiM cap contact rules (VIA4) + + width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)" + spacing mim2cc mim2cc 420 touching_ok \ + "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)" + surround mim2cc/m5 *m5 120 absence_illegal \ + "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)" + exact_overlap mim2cc/c2 + + +#---------------------------- +# HVNTM +#---------------------------- +variants (full) + cifspacing hvntm_generate hvntm_generate 700 touching_ok \ + "HVNTM spacing < %d (hvntm.2)" +variants (fast),(full) + +#---------------------------- +# End DRC style +#---------------------------- + +end + +#---------------------------- +# LEF format definitions +#---------------------------- + +lef + + masterslice pwell pwell PWELL substrate + masterslice nwell nwell NWELL + + routing li li1 LI1 LI li + + routing m1 met1 MET1 m1 + routing m2 met2 MET2 m2 + routing m3 met3 MET3 m3 + routing m4 met4 MET4 m4 + routing m5 met5 MET5 m5 + routing mrdl met6 MET6 m6 MRDL METRDL + + cut mcon mcon MCON Mcon + cut m2c via via1 VIA VIA1 cont2 via12 + cut m3c via2 VIA2 cont3 via23 + cut via3 via3 VIA3 cont4 via34 + cut via4 via4 VIA4 cont5 via45 + + obs obsli li1 + obs obsm1 met1 + obs obsm2 met2 + obs obsm3 met3 + + obs obsm4 met4 + obs obsm5 met5 + obs obsmrdl met6 + + # NOTE: obsmcon only used with li1, not obsli. + obs obsmcon mcon + + # Vias on obstruction layers should be ignored, so cast to obstruction metal. + obs obsm1 via + obs obsm2 via2 + obs obsm3 via3 + obs obsm4 via4 + +end + +#----------------------------------------------------- +# Device and Parasitic extraction +#----------------------------------------------------- + +extract + style ngspice variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc),(nowell) + cscale 1 + # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all + # dimensions must be in units of microns in the extract file. + # Use extract style "ngspice(si)" to override this and produce + # a file with SI units for length/area. + + variants (),(orig),(hrhc),(lrhc),(hrlc),(lrlc),(nowell) + lambda 1E6 + variants (si) + lambda 1.0 + variants * + + units microns + step 7 + sidehalo 8 + fringeshieldhalo 8 + + # NOTE: MiM cap layers have been purposely put out of order, + # may want to reconsider. + + planeorder dwell 0 + planeorder well 1 + planeorder active 2 + planeorder locali 3 + planeorder metal1 4 + planeorder metal2 5 + planeorder metal3 6 + planeorder metal4 7 + planeorder metal5 8 + planeorder metali 9 + planeorder block 10 + planeorder comment 11 + planeorder cap1 12 + planeorder cap2 13 + + height dnwell -0.1 0.1 + height nwell,pwell 0.0 0.2062 + height alldiff 0.2062 0.12 + height fomfill 0.2062 0.12 + height allpoly 0.3262 0.18 + height polyfill 0.3262 0.18 + height alldiffcont 0.3262 0.61 + height pc 0.5062 0.43 + height allli 0.9361 0.10 + height mcon 1.0361 0.34 + height allm1 1.3761 0.36 + height m1fill 1.3761 0.36 + height v1 1.7361 0.27 + height allm2 2.0061 0.36 + height m2fill 2.0061 0.36 + height v2 2.3661 0.42 + height allm3 2.7861 0.845 + height m3fill 2.7861 0.845 + height mimcap 2.4661 0.2 + height mimcap2 3.7311 0.2 + height mimcc 2.6661 0.12 + height mim2cc 3.9311 0.09 + height v3 3.6311 0.39 + height allm4 4.0211 0.845 + height m4fill 4.0211 0.845 + height v4 4.8661 0.505 + height allm5 5.3711 1.26 + height m5fill 5.3711 1.26 + height mrdlc 6.6311 0.63 + height mrdl 7.2611 3.0 + + # Antenna check parameters + # Note that checks w/diode diffusion are not modeled + model partial + antenna poly sidewall 50 none + antenna allcont surface 3 none + antenna li sidewall 75 0 450 + antenna mcon surface 3 0 18 + antenna m1,m2,m3 sidewall 400 2200 400 + antenna v1 surface 3 0 18 + antenna v2 surface 6 0 36 + antenna m4,m5 sidewall 400 2200 400 + antenna v3,v4 surface 6 0 36 + + tiedown alldiffnonfet + +variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc) + # for all variants except (nowell) + + substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub + +variants * + +# Resistances are in milliohms per square +# Optional 3rd argument is the corner adjustment fraction +# Device values come from trtc.cor (typical corner) + +variants (),(orig),(si),(nowell) + + resist (pwell,isosub)/well 4400000 + resist (dnwell)/dwell 2200000 + resist (nwell)/well 950000 + resist (rpw)/well 3050000 0.5 + resist (*ndiff,nsd)/active 120000 + resist (*pdiff,*psd)/active 197000 + resist (*mvndiff,mvnsd)/active 114000 + resist (*mvpdiff,*mvpsd)/active 191000 + + resist ndiffres/active 120000 0.5 + resist pdiffres/active 197000 0.5 + resist mvndiffres/active 114000 0.5 + resist mvpdiffres/active 191000 0.5 + resist mrp1/active 48200 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 48200 + resist rmp/active 48200 + + resist (allli)/locali 12800 + resist (allm1)/metal1 125 + resist (allm2)/metal2 125 + resist (allm3)/metal3 47 + resist (allm4)/metal4 47 + resist (allm5)/metal5 29 + resist mrdl/metali 5 + + contact ndc,nsc 185000 + contact ndic,ndilvtc,nndic 185000 + contact pdc,psc 585000 + contact pdic,pdilvtc,pdihvtc 585000 + contact mvndc,mvnsc,mvndic 185000 + contact mvpdc,mvpsc,mvpdic 585000 + contact pc,xpc 152000 + contact mcon 9300 + contact m2c 4500 + contact m3c 3410 + contact mimcc 4500 + contact mim2cc 3410 + contact via3 3410 + contact via4 380 + contact mrdlc 6 + +variants (hrhc),(hrlc) + + # High-end corner resistances + # No corner values available for: substrate, xhrpoly, uhrpoly, RDL + resist (pwell,isosub)/well 4400000 + resist (dnwell)/dwell 2575000 + resist (nwell)/well 1350000 + resist (rpw)/well 3535000 0.5 + resist (*ndiff,nsd)/active 132000 + resist (*pdiff,*psd)/active 228000 + resist (*mvndiff,mvnsd)/active 126000 + resist (*mvpdiff,*mvpsd)/active 228000 + + resist ndiffres/active 132000 0.5 + resist pdiffres/active 228000 0.5 + resist mvndiffres/active 126000 0.5 + resist mvpdiffres/active 228000 0.5 + resist mrp1/active 55800 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 55800 + resist rmp/active 55800 + + resist (allli)/locali 17000 + resist (allm1)/metal1 145 + resist (allm2)/metal2 145 + resist (allm3)/metal3 56 + resist (allm4)/metal4 56 + resist (allm5)/metal5 36 + resist mrdl/metali 5 + + contact ndc,nsc 280000 + contact ndic,ndilvtc,nndic 280000 + contact pdc,psc 840000 + contact pdic,pdilvtc,pdihvtc 840000 + contact mvndc,mvnsc,mvndic 280000 + contact mvpdc,mvpsc,mvpdic 840000 + contact pc,xpc 252000 + contact mcon 23000 + contact m2c 15000 + contact m3c 8000 + contact mimcc 15000 + contact mim2cc 8000 + contact via3 8000 + contact via4 891 + contact mrdlc 6 + +variants (lrhc),(lrlc) + + # Low-end corner resistances + # No corner values available for: substrate, xhrpoly, uhrpoly, RDL + resist (pwell,isosub)/well 4400000 + resist (dnwell)/dwell 1825000 + resist (nwell)/well 550000 + resist (rpw)/well 2565000 0.5 + resist (*ndiff,nsd)/active 108000 + resist (*pdiff,*psd)/active 166000 + resist (*mvndiff,mvnsd)/active 102000 + resist (*mvpdiff,*mvpsd)/active 160000 + + resist ndiffres/active 108000 0.5 + resist pdiffres/active 166000 0.5 + resist mvndiffres/active 102000 0.5 + resist mvpdiffres/active 160000 0.5 + resist mrp1/active 42200 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 42200 + resist rmp/active 42200 + + resist (allli)/locali 10500 + resist (allm1)/metal1 105 + resist (allm2)/metal2 105 + resist (allm3)/metal3 38 + resist (allm4)/metal4 38 + resist (allm5)/metal5 21 + resist mrdl/metali 5 + + contact ndc,nsc 95000 + contact ndic,ndilvtc,nndic 95000 + contact pdc,psc 345000 + contact pdic,pdilvtc,pdihvtc 345000 + contact mvndc,mvnsc,mvndic 95000 + contact mvpdc,mvpsc,mvpdic 345000 + contact pc,xpc 52000 + contact mcon 1600 + contact m2c 2000 + contact m3c 500 + contact mimcc 2000 + contact mim2cc 500 + contact via3 500 + contact via4 12 + contact mrdlc 6 + +variants * + + # These types should not be considered as electrical nodes + resist blocktypes None + resist obstypes None + resist comment None + +#------------------------------------------------------------------------- +# Parasitic capacitance values: Use document (...) +#------------------------------------------------------------------------- +# This uses the new "default" definitions that determine the intervening +# planes from the planeorder stack, take care of the reflexive sideoverlap +# definitions, and generally clean up the section and make it more readable. +# +# Also uses "units microns" statement. All values are taken from the +# document PEX/xRC/cap_models. Fringe capacitance values are approximated. +# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps. +#------------------------------------------------------------------------- +# Remember that device capacitances to substrate are taken care of by the +# models. Thus, active and poly definitions ignore all "fet" types. +# fet types are excluded when computing parasitic capacitance to +# active from layers above them because poly is a shield; fet types are +# included for parasitics from layers above to poly. Resistor types +# should be removed from all parasitic capacitance calculations, or else +# they just create floating caps. Technically, the capacitance probably +# should be split between the two terminals. Unsure of the correct model. +#------------------------------------------------------------------------- + +variants (),(orig),(si) +# Nominal capacitances + +#deep n-well +defaultareacap dnwell dwell 120 + +#p-well +defaultoverlap pwell well dnwell dwell 120 + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well dnwell dwell 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 17 +# defaultareacap allpolynonfet active 106 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 16.0 + defaultareacap *poly active 106.13 + defaultperimeter *poly active 55.27 + defaultoverlap *poly active nwell,pwell well 106.13 + defaultsideoverlap *poly active nwell,pwell well 55.27 + +#locali + defaultsidewall allli locali 25.5 0.14 + defaultareacap allli locali 36.99 + defaultperimeter allli locali 40.70 + defaultoverlap allli locali nwell,pwell well 36.99 + defaultsideoverlap allli locali nwell,pwell well 40.70 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 55.3 + defaultsideoverlap allli locali allactivenonfet active 44.27 + +#locali->poly + defaultoverlap allli locali allpolynonres active 94.16 + defaultsideoverlap allli locali allpolynonres active 51.85 + defaultsideoverlap *poly active allli locali 25.14 + +#metal1 + defaultsidewall allm1 metal1 44 0.25 + defaultareacap allm1 metal1 25.78 + defaultperimeter allm1 metal1 40.57 + defaultoverlap allm1 metal1 nwell,pwell well 25.78 + defaultsideoverlap allm1 metal1 nwell,pwell well 40.57 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 33.6 + defaultsideoverlap allm1 metal1 allactivenonfet active 43.10 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 44.81 + defaultsideoverlap allm1 metal1 allpolynonres active 46.72 + defaultsideoverlap *poly active allm1 metal1 16.69 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 114.20 + defaultsideoverlap allm1 metal1 allli locali 59.50 + defaultsideoverlap allli locali allm1 metal1 34.70 + +#metal2 + defaultsidewall allm2 metal2 50 0.3 + + defaultareacap allm2 metal2 17.5 + defaultperimeter allm2 metal2 37.76 + defaultoverlap allm2 metal2 nwell,pwell well 17.5 + defaultsideoverlap allm2 metal2 nwell,pwell well 37.76 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 20.8 + defaultsideoverlap allm2 metal2 allactivenonfet active 39.54 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 24.50 + defaultsideoverlap allm2 metal2 allpolynonres active 41.22 + defaultsideoverlap *poly active allm2 metal2 11.17 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 37.56 + defaultsideoverlap allm2 metal2 allli locali 46.28 + defaultsideoverlap allli locali allm2 metal2 21.74 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 133.86 + defaultsideoverlap allm2 metal2 allm1 metal1 67.05 + defaultsideoverlap allm1 metal1 allm2 metal2 48.19 + + +#metal3 + defaultsidewall allm3 metal3 74.0 0.40 + + defaultareacap allm3 metal3 12.37 + defaultperimeter allm3 metal3 40.99 + defaultoverlap allm3 metal3 nwell,pwell well 12.37 + defaultsideoverlap allm3 metal3 nwell,pwell well 40.99 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 14.2 + defaultsideoverlap allm3 metal3 allactive active 42.25 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 16.06 + defaultsideoverlap allm3 metal3 allpolynonres active 43.53 + defaultsideoverlap *poly active allm3 metal3 9.18 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 20.79 + defaultsideoverlap allm3 metal3 allli locali 46.71 + defaultsideoverlap allli locali allm3 metal3 15.08 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 34.54 + defaultsideoverlap allm3 metal3 allm1 metal1 54.81 + defaultsideoverlap allm1 metal1 allm3 metal3 26.68 + + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 86.19 + defaultsideoverlap allm3 metal3 allm2 metal2 69.85 + defaultsideoverlap allm2 metal2 allm3 metal3 44.43 + +#metal4 + defaultsidewall allm4 metal4 94.0 0.57 + defaultareacap allm4 metal4 8.42 + defaultperimeter allm4 metal4 36.68 + defaultoverlap allm4 metal4 nwell,pwell well 8.42 + defaultsideoverlap allm4 metal4 nwell,pwell well 36.68 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 9.41 + defaultsideoverlap allm4 metal4 allactivenonfet active 37.57 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 10.01 + defaultsideoverlap allm4 metal4 allpolynonres active 38.11 + defaultsideoverlap *poly active allm4 metal4 6.35 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 11.67 + defaultsideoverlap allm4 metal4 allli locali 39.71 + defaultsideoverlap allli locali allm4 metal4 10.14 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 15.03 + defaultsideoverlap allm4 metal4 allm1 metal1 42.56 + defaultsideoverlap allm1 metal1 allm4 metal4 16.42 + + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 20.33 + defaultsideoverlap allm4 metal4 allm2 metal2 46.38 + defaultsideoverlap allm2 metal2 allm4 metal4 22.33 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 84.03 + defaultsideoverlap allm4 metal4 allm3 metal3 70.52 + defaultsideoverlap allm3 metal3 allm4 metal4 42.64 + +#metal5 + defaultsidewall allm5 metal5 155 0.5 + defaultareacap allm5 metal5 6.32 + defaultperimeter allm5 metal5 38.85 + defaultoverlap allm5 metal5 nwell,pwell well 6.32 + defaultsideoverlap allm5 metal5 nwell,pwell well 38.85 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 6.88 + defaultsideoverlap allm5 metal5 allactivenonfet active 39.52 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 7.21 + defaultsideoverlap allm5 metal5 allpolynonres active 39.91 + defaultsideoverlap *poly active allm5 metal5 6.49 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 8.03 + defaultsideoverlap allm5 metal5 allli locali 41.15 + defaultsideoverlap allli locali allm5 metal5 7.64 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 9.48 + defaultsideoverlap allm5 metal5 allm1 metal1 43.19 + defaultsideoverlap allm1 metal1 allm5 metal5 12.02 + + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 11.34 + defaultsideoverlap allm5 metal5 allm2 metal2 45.59 + defaultsideoverlap allm2 metal2 allm5 metal5 15.69 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 19.63 + defaultsideoverlap allm5 metal5 allm3 metal3 54.15 + defaultsideoverlap allm3 metal3 allm5 metal5 27.84 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 68.33 + defaultsideoverlap allm5 metal5 allm4 metal4 82.82 + defaultsideoverlap allm4 metal4 allm5 metal5 46.98 + +#------------------------------------------------------------------------- +# Parasitic capacitance values for minimum corner +#------------------------------------------------------------------------- + +variants (hrlc),(lrlc) +# Minimum corner capacitances + +#deep n-well +defaultareacap dnwell dwell 120 + +#p-well +defaultoverlap pwell well dnwell dwell 120 + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well dnwell dwell 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 80.4 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 17.0 0.21 + defaultareacap *poly active 80.4 + defaultperimeter *poly active 48.83 + defaultoverlap *poly active nwell,pwell well 80.4 + defaultsideoverlap *poly active nwell,pwell well 48.83 + +#locali + defaultsidewall allli locali 26.7 0.17 + defaultareacap allli locali 29.3 + defaultperimeter allli locali 35.69 + defaultoverlap allli locali nwell,pwell well 29.3 + defaultsideoverlap allli locali nwell,pwell well 35.69 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 45.3 + defaultsideoverlap allli locali allactivenonfet active 39.59 + +#locali->poly + defaultoverlap allli locali allpolynonres active 64.5 + defaultsideoverlap allli locali allpolynonres active 43.75 + defaultsideoverlap *poly active allli locali 21.21 + +#metal1 + defaultsidewall allm1 metal1 35.6 0.14 + defaultareacap allm1 metal1 20.2 + defaultperimeter allm1 metal1 34.41 + defaultoverlap allm1 metal1 nwell,pwell well 20.2 + defaultsideoverlap allm1 metal1 nwell,pwell well 34.41 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 26.7 + defaultsideoverlap allm1 metal1 allactivenonfet active 37.22 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 32.3 + defaultsideoverlap allm1 metal1 allpolynonres active 40.34 + defaultsideoverlap *poly active allm1 metal1 14.41 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 77.2 + defaultsideoverlap allm1 metal1 allli locali 49.46 + defaultsideoverlap allli locali allm1 metal1 28.84 + +#metal2 + defaultsidewall allm2 metal2 37.61 0.14 + + defaultareacap allm2 metal2 14.0 + defaultperimeter allm2 metal2 32.60 + defaultoverlap allm2 metal2 nwell,pwell well 14.0 + defaultsideoverlap allm2 metal2 nwell,pwell well 32.60 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 16.8 + defaultsideoverlap allm2 metal2 allactivenonfet active 34.16 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 18.9 + defaultsideoverlap allm2 metal2 allpolynonres active 34.46 + defaultsideoverlap *poly active allm2 metal2 9.34 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 28.6 + defaultsideoverlap allm2 metal2 allli locali 39.67 + defaultsideoverlap allli locali allm2 metal2 18.63 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 80.4 + defaultsideoverlap allm2 metal2 allm1 metal1 53.85 + defaultsideoverlap allm1 metal1 allm2 metal2 38.70 + + +#metal3 + defaultsidewall allm3 metal3 52.0 0.30 + + defaultareacap allm3 metal3 10.2 + defaultperimeter allm3 metal3 36.05 + defaultoverlap allm3 metal3 nwell,pwell well 10.2 + defaultsideoverlap allm3 metal3 nwell,pwell well 36.05 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 11.7 + defaultsideoverlap allm3 metal3 allactive active 37.59 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 12.6 + defaultsideoverlap allm3 metal3 allpolynonres active 38.28 + defaultsideoverlap *poly active allm3 metal3 8.07 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 16.3 + defaultsideoverlap allm3 metal3 allli locali 41.75 + defaultsideoverlap allli locali allm3 metal3 13.48 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 25.8 + defaultsideoverlap allm3 metal3 allm1 metal1 48.82 + defaultsideoverlap allm1 metal1 allm3 metal3 23.76 + + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 59.5 + defaultsideoverlap allm3 metal3 allm2 metal2 61.18 + defaultsideoverlap allm2 metal2 allm3 metal3 38.92 + +#metal4 + defaultsidewall allm4 metal4 53.7 0.30 + defaultareacap allm4 metal4 7.28 + defaultperimeter allm4 metal4 32.39 + defaultoverlap allm4 metal4 nwell,pwell well 7.28 + defaultsideoverlap allm4 metal4 nwell,pwell well 32.39 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 7.98 + defaultsideoverlap allm4 metal4 allactivenonfet active 33.54 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 8.42 + defaultsideoverlap allm4 metal4 allpolynonres active 33.59 + defaultsideoverlap *poly active allm4 metal4 5.60 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 9.92 + defaultsideoverlap allm4 metal4 allli locali 35.49 + defaultsideoverlap allli locali allm4 metal4 9.06 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 12.8 + defaultsideoverlap allm4 metal4 allm1 metal1 38.29 + defaultsideoverlap allm1 metal1 allm4 metal4 14.77 + + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 17.8 + defaultsideoverlap allm4 metal4 allm2 metal2 42.08 + defaultsideoverlap allm2 metal2 allm4 metal4 20.26 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 57.6 + defaultsideoverlap allm4 metal4 allm3 metal3 59.42 + defaultsideoverlap allm3 metal3 allm4 metal4 35.93 + +#metal5 + defaultsidewall allm5 metal5 81.5 1.6 + defaultareacap allm5 metal5 5.56 + defaultperimeter allm5 metal5 34.65 + defaultoverlap allm5 metal5 nwell,pwell well 5.56 + defaultsideoverlap allm5 metal5 nwell,pwell well 34.65 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 5.96 + defaultsideoverlap allm5 metal5 allactivenonfet active 35.55 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 6.2 + defaultsideoverlap allm5 metal5 allpolynonres active 35.59 + defaultsideoverlap *poly active allm5 metal5 5.79 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 6.97 + defaultsideoverlap allm5 metal5 allli locali 37.24 + defaultsideoverlap allli locali allm5 metal5 6.91 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 8.26 + defaultsideoverlap allm5 metal5 allm1 metal1 39.30 + defaultsideoverlap allm1 metal1 allm5 metal5 10.94 + + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 10.1 + defaultsideoverlap allm5 metal5 allm2 metal2 41.75 + defaultsideoverlap allm2 metal2 allm5 metal5 14.37 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 16.7 + defaultsideoverlap allm5 metal5 allm3 metal3 48.75 + defaultsideoverlap allm3 metal3 allm5 metal5 25.06 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 48.7 + defaultsideoverlap allm5 metal5 allm4 metal4 70.26 + defaultsideoverlap allm4 metal4 allm5 metal5 39.86 + +#------------------------------------------------------------------------- +# Parasitic capacitance values for maximum corner +#------------------------------------------------------------------------- + +variants (hrhc),(lrhc) +# Maximum corner capacitances + +#deep n-well +defaultareacap dnwell dwell 120 + +#p-well +defaultoverlap pwell well dnwell dwell 120 + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well dnwell dwell 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 106 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 17.0 0.21 + defaultareacap *poly active 155.0 + defaultperimeter *poly active 64.82 + defaultoverlap *poly active nwell,pwell well 155.0 + defaultsideoverlap *poly active nwell,pwell well 64.82 + +#locali + defaultsidewall allli locali 28.7 0.17 + defaultareacap allli locali 49.7 + defaultperimeter allli locali 47.02 + defaultoverlap allli locali nwell,pwell well 49.7 + defaultsideoverlap allli locali nwell,pwell well 47.02 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 70.9 + defaultsideoverlap allli locali allactivenonfet active 49.94 + +#locali->poly + defaultoverlap allli locali allpolynonres active 174.0 + defaultsideoverlap allli locali allpolynonres active 66.60 + defaultsideoverlap *poly active allli locali 32.29 + +#metal1 + defaultsidewall allm1 metal1 37.6 0.14 + defaultareacap allm1 metal1 35.7 + defaultperimeter allm1 metal1 49.59 + defaultoverlap allm1 metal1 nwell,pwell well 35.7 + defaultsideoverlap allm1 metal1 nwell,pwell well 49.59 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 45.4 + defaultsideoverlap allm1 metal1 allactivenonfet active 51.17 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 73.2 + defaultsideoverlap allm1 metal1 allpolynonres active 59.78 + defaultsideoverlap *poly active allm1 metal1 21.36 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 215.0 + defaultsideoverlap allm1 metal1 allli locali 80.12 + defaultsideoverlap allli locali allm1 metal1 46.73 + +#metal2 + defaultsidewall allm2 metal2 40.2 0.14 + + defaultareacap allm2 metal2 23.5 + defaultperimeter allm2 metal2 46.03 + defaultoverlap allm2 metal2 nwell,pwell well 23.5 + defaultsideoverlap allm2 metal2 nwell,pwell well 46.03 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 27.4 + defaultsideoverlap allm2 metal2 allactivenonfet active 47.45 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 35.5 + defaultsideoverlap allm2 metal2 allpolynonres active 51.29 + defaultsideoverlap *poly active allm2 metal2 13.90 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 52.3 + defaultsideoverlap allm2 metal2 allli locali 55.56 + defaultsideoverlap allli locali allm2 metal2 26.10 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 313.0 + defaultsideoverlap allm2 metal2 allm1 metal1 102.37 + defaultsideoverlap allm1 metal1 allm2 metal2 73.576 + + +#metal3 + defaultsidewall allm3 metal3 60.6 0.30 + + defaultareacap allm3 metal3 16.3 + defaultperimeter allm3 metal3 47.38 + defaultoverlap allm3 metal3 nwell,pwell well 16.3 + defaultsideoverlap allm3 metal3 nwell,pwell well 47.38 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 18.1 + defaultsideoverlap allm3 metal3 allactive active 48.19 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 21.3 + defaultsideoverlap allm3 metal3 allpolynonres active 50.44 + defaultsideoverlap *poly active allm3 metal3 10.64 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 26.3 + defaultsideoverlap allm3 metal3 allli locali 53.29 + defaultsideoverlap allli locali allm3 metal3 17.20 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 45.2 + defaultsideoverlap allm3 metal3 allm1 metal1 62.88 + defaultsideoverlap allm1 metal1 allm3 metal3 30.61 + + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 131.0 + defaultsideoverlap allm3 metal3 allm2 metal2 82.67 + defaultsideoverlap allm2 metal2 allm3 metal3 52.59 + +#metal4 + defaultsidewall allm4 metal4 65.4 0.30 + defaultareacap allm4 metal4 10.7 + defaultperimeter allm4 metal4 42.40 + defaultoverlap allm4 metal4 nwell,pwell well 10.7 + defaultsideoverlap allm4 metal4 nwell,pwell well 42.40 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 11.4 + defaultsideoverlap allm4 metal4 allactivenonfet active 43.0 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 12.6 + defaultsideoverlap allm4 metal4 allpolynonres active 43.99 + defaultsideoverlap *poly active allm4 metal4 7.33 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 14.3 + defaultsideoverlap allm4 metal4 allli locali 45.09 + defaultsideoverlap allli locali allm4 metal4 11.51 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 18.5 + defaultsideoverlap allm4 metal4 allm1 metal1 48.07 + defaultsideoverlap allm1 metal1 allm4 metal4 18.55 + + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 25.2 + defaultsideoverlap allm4 metal4 allm2 metal2 51.98 + defaultsideoverlap allm2 metal2 allm4 metal4 25.03 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 191.0 + defaultsideoverlap allm4 metal4 allm3 metal3 92.12 + defaultsideoverlap allm3 metal3 allm4 metal4 55.70 + +#metal5 + defaultsidewall allm5 metal5 118.7 1.6 + defaultareacap allm5 metal5 7.76 + defaultperimeter allm5 metal5 44.91 + defaultoverlap allm5 metal5 nwell,pwell well 7.76 + defaultsideoverlap allm5 metal5 nwell,pwell well 44.91 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 8.14 + defaultsideoverlap allm5 metal5 allactivenonfet active 45.47 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 8.74 + defaultsideoverlap allm5 metal5 allpolynonres active 46.31 + defaultsideoverlap *poly active allm5 metal5 7.53 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 9.48 + defaultsideoverlap allm5 metal5 allli locali 47.09 + defaultsideoverlap allli locali allm5 metal5 8.74 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 11.2 + defaultsideoverlap allm5 metal5 allm1 metal1 49.44 + defaultsideoverlap allm1 metal1 allm5 metal5 13.76 + + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 13.3 + defaultsideoverlap allm5 metal5 allm2 metal2 51.69 + defaultsideoverlap allm2 metal2 allm5 metal5 17.79 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 24.6 + defaultsideoverlap allm5 metal5 allm3 metal3 63.24 + defaultsideoverlap allm3 metal3 allm5 metal5 32.51 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 115.0 + defaultsideoverlap allm5 metal5 allm4 metal4 109.69 + defaultsideoverlap allm4 metal4 allm5 metal5 62.22 + +#--------------------------------------------------------- + +variants * + + +# Devices: Base models (not subcircuit wrappers) + +variants (),(si),(hrhc),(lrhc),(hrlc),(lrlc) + + device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_latch ppu \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error w>=0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_01v8_hvt scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error w<0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + + device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error \ + w>=0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_01v8 scnfet \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error \ + w<0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_pass npass \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device subcircuit sky130_fd_pr__cap_var_lvt varactor \ + *nndiff pwell,space/w error l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt \ + *nndiff pwell,space/w error l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor \ + *mvnndiff pwell,space/w error l=l w=w + + # Bipolars + device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a1=area + device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \ + error a1>0.99 a1<1.01 + device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \ + error a1>1.99 a1<2.01 + device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a1=area + device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \ + pwell,space/w a1>0.45 a1<0.47 + device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \ + pwell,space/w a1>11.55 a1<11.57 + device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a1=area + device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \ + dnwell space/w error a1>0.99 a1<1.01 + + # Ignore the extended-drain FET geometry that forms part of the high-voltage + # bipolar devices. + device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp + device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp + + # Extended drain devices (must appear before the regular devices) + device msubcircuit sky130_fd_pr__nfet_g5v0d16v0 mvnfet *mvndiff \ + extdrain,*mvnsd pwell,space/w error l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_g5v0d16v0 mvpfet *mvpdiff \ + extdrain,*mvpsd nwell error l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd + device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd + device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ + pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd + + device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 + device ndiode sky130_fd_pr__model__parasitic__diode_ps2dn \ + photo pwell,space/w error a=area + + device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \ + xpc nwell,pwell,space/w error l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \ + xpc nwell,pwell,space/w error w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \ + xpc nwell,pwell,space/w error w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \ + xpc nwell,pwell,space/w error w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \ + xpc nwell,pwell,space/w error w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \ + xpc nwell,pwell,space/w error w>5.72 w<5.74 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \ + xpc nwell,pwell,space/w error l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \ + xpc nwell,pwell,space/w error w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \ + xpc nwell,pwell,space/w error w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \ + xpc nwell,pwell,space/w error w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \ + xpc nwell,pwell,space/w error w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \ + xpc nwell,pwell,space/w error w>5.72 w<5.74 l=l+0.16 + + device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \ + *ndiff pwell,space/w error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \ + *pdiff nwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_iso_pw rpw \ + pwell dnwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \ + *mvndiff pwell,space/w error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \ + *mvpdiff nwell error l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + + # NOTE: SkyWater diode models have bizarre units requiring bizarre scaling + device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area*1E12 p=pj*1E6 + + device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area*1E12 p=pj*1E6 + + + device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l + device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l + +variants (nowell) + + device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_latch ppu \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres w>=0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_01v8_hvt scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres w<0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + + device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \ + *ndiff,ndiffres *ndiff,ndiffres \ + w>=0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_01v8 scnfet \ + *ndiff,ndiffres *ndiff,ndiffres \ + w<0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *srampvar l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_pass npass \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device subcircuit sky130_fd_pr__cap_var_lvt varactor \ + *nndiff l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt \ + *nndiff l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor \ + *mvnndiff l=l w=w + + # Bipolars +# device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a1=area +# device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \ +# error a1>0.99 a1<1.01 +# device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \ +# error a1>1.99 a1<2.01 +# device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a1=area +# device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \ +# pwell,space/w a1>0.45 a1<0.47 +# device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \ +# pwell,space/w a1>11.55 a1<11.57 +# device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a1=area +# device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \ +# dnwell space/w error a1>0.99 a1<1.01 +# + # Ignore the extended-drain FET geometry that forms part of the high-voltage + # bipolar devices. +# device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp +# device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp + + # Extended drain devices (must appear before the regular devices) +# device msubcircuit sky130_fd_pr__nfet_g5v0d16v0 mvnfet *mvndiff \ +# extdrain,*mvnsd pwell,space/w error l=l w=w a1=as p1=ps a2=ad p2=pd +# device msubcircuit sky130_fd_pr__pfet_g5v0d16v0 mvpfet *mvpdiff \ +# extdrain,*mvpsd nwell error l=l w=w a1=as p1=ps a2=ad p2=pd +# device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ +# dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd +# device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ +# dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd +# device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ +# pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd + + device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 +# device ndiode sky130_fd_pr__model__parasitic__diode_ps2dn \ +# photo pwell,space/w error a=area + + device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \ + xpc l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \ + xpc w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \ + xpc w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \ + xpc w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \ + xpc w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \ + xpc w>5.72 w<5.74 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \ + xpc l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \ + xpc w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \ + xpc w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \ + xpc w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \ + xpc w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \ + xpc w>5.72 w<5.74 l=l+0.16 + + device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \ + *ndiff l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \ + *pdiff l=l w=w +# device rsubcircuit sky130_fd_pr__res_iso_pw rpw \ +# pwell dnwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \ + *mvndiff l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \ + *mvpdiff l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + + # NOTE: SkyWater diode models have bizarre units requiring bizarre scaling +# device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area*1E12 p=pj*1E6 +# device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area*1E12 p=pj*1E6 +# device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area*1E12 p=pj*1E6 +# device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area*1E12 p=pj*1E6 + +# device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area*1E12 p=pj*1E6 +# device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area*1E12 p=pj*1E6 +# device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area*1E12 p=pj*1E6 +# device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area*1E12 p=pj*1E6 + + + device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l + device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l + + variants (orig) + + device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__special_pfet_latch ppu pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \ + pwell,space/w + + # Note that corenvar, corepvar are not considered devices, and extract as + # parasitic capacitance instead (but cap values need to be added). + + # Extended drain devices (must appear before the regular devices) + device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error + device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error + device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ + pwell,space/w nwell error + + device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell + device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell + device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w + device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w + device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w + device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w + + # These devices always extract as subcircuits + device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 + + device resistor sky130_fd_pr__res_high_po xhrpoly xpc + device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff + device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff + device resistor mrdn_hv mvndiffres *mvndiff + device resistor mrdp_hv mvpdiffres *mvpdiff + device resistor sky130_fd_pr__res_iso_pw rpw pwell + + # NOTE: SkyWater diode models have bizarre units requiring bizarre scaling + device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area*1E12 p=pj*1E6 + + device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area*1E12 p=pj*1E6 + + device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a1=area + device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error \ + a1>0.99 a1<1.01 + device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error \ + a1>1.99 a1<2.01 + device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a1=area + device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w \ + a1>0.45 a1<0.48 + device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w \ + a1>11.55 a1<11.57 + device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a1=area + device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error \ + a1>0.99 a1<1.01 + + device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1 + device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1 + +end + +#----------------------------------------------------- +# Wiring tool definitions +#----------------------------------------------------- + +wiring + # All wiring values are in nanometers + scalefactor 10 + + contact mcon 170 li 0 0 m1 30 60 + contact v1 260 m1 0 30 m2 0 30 + contact v2 280 m2 0 45 m3 25 0 + contact v3 320 m3 0 30 m4 5 5 + contact v4 1180 m4 0 m5 120 + + contact pc 170 poly 50 80 li 0 80 + contact pdc 170 pdiff 40 60 li 0 80 + contact ndc 170 ndiff 40 60 li 0 80 + contact psc 170 psd 40 60 li 0 80 + contact nsc 170 nsd 40 60 li 0 80 + +end + +#----------------------------------------------------- +# Plain old router. . . +#----------------------------------------------------- + +router +end + +#------------------------------------------------------------ +# Plowing (restored in magic 8.2, need to fill this section) +#------------------------------------------------------------ + +plowing +end + +#----------------------------------------------------------------- +# No special plot layers defined (use default PNM color choices) +#----------------------------------------------------------------- + +plot + style pnm + default + draw fillblock no_color_at_all + draw fillblock4 no_color_at_all + draw fomfill no_color_at_all + draw polyfill no_color_at_all + draw m1fill no_color_at_all + draw m2fill no_color_at_all + draw m3fill no_color_at_all + draw m4fill no_color_at_all + draw m5fill no_color_at_all + draw nwell cwell +end + diff --git a/scripts/be_checks/tech/sky130A/sky130A_setup.tcl b/scripts/be_checks/tech/sky130A/sky130A_setup.tcl new file mode 100644 index 00000000..75a6329b --- /dev/null +++ b/scripts/be_checks/tech/sky130A/sky130A_setup.tcl @@ -0,0 +1,540 @@ +#--------------------------------------------------------------- +# Setup file for netgen LVS +# SkyWater sky130A +#--------------------------------------------------------------- +permute default +property default +property parallel none + +# Allow override of default #columns in the output format. +catch {format $env(NETGEN_COLUMNS)} + +#--------------------------------------------------------------- +# For the following, get the cell lists from +# circuit1 and circuit2. +#--------------------------------------------------------------- + +set cells1 [cells list -all -circuit1] +set cells2 [cells list -all -circuit2] + +#------------------------------------------- +# Resistors (except metal) +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__res_iso_pw +lappend devices sky130_fd_pr__res_high_po_0p35 +lappend devices sky130_fd_pr__res_high_po_0p69 +lappend devices sky130_fd_pr__res_high_po_1p41 +lappend devices sky130_fd_pr__res_high_po_2p85 +lappend devices sky130_fd_pr__res_high_po_5p73 +lappend devices sky130_fd_pr__res_high_po +lappend devices sky130_fd_pr__res_xhigh_po_0p35 +lappend devices sky130_fd_pr__res_xhigh_po_0p69 +lappend devices sky130_fd_pr__res_xhigh_po_1p41 +lappend devices sky130_fd_pr__res_xhigh_po_2p85 +lappend devices sky130_fd_pr__res_xhigh_po_5p73 +lappend devices sky130_fd_pr__res_xhigh_po +lappend devices sky130_fd_pr__res_generic_nd +lappend devices sky130_fd_pr__res_generic_pd +lappend devices sky130_fd_pr__res_generic_nd__hv +lappend devices sky130_fd_pr__res_generic_pd__hv +lappend devices mrdn_hv mrdp_hv + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" 1 2 + property "-circuit1 $dev" series enable + property "-circuit1 $dev" series {w critical} + property "-circuit1 $dev" series {l add} + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" parallel {value par} + property "-circuit1 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" 1 2 + property "-circuit2 $dev" series enable + property "-circuit2 $dev" series {w critical} + property "-circuit2 $dev" series {l add} + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" parallel {value par} + property "-circuit2 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#------------------------------------------- +# poly resistor +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__res_generic_po + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" end_a end_b + property "-circuit1 $dev" series enable + property "-circuit1 $dev" series {w critical} + property "-circuit1 $dev" series {l add} + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" parallel {value par} + property "-circuit1 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" end_a end_b + property "-circuit2 $dev" series enable + property "-circuit2 $dev" series {w critical} + property "-circuit2 $dev" series {l add} + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" parallel {value par} + property "-circuit2 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#------------------------------------------- +# MRM (metal) resistors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__res_generic_l1 +lappend devices sky130_fd_pr__res_generic_m1 +lappend devices sky130_fd_pr__res_generic_m2 +lappend devices sky130_fd_pr__res_generic_m3 +lappend devices sky130_fd_pr__res_generic_m4 +lappend devices sky130_fd_pr__res_generic_m5 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" end_a end_b + property "-circuit1 $dev" series enable + property "-circuit1 $dev" series {w critical} + property "-circuit1 $dev" series {l add} + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" parallel {value par} + property "-circuit1 $dev" tolerance {l 10.0} {w 10.0} + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" end_a end_b + property "-circuit2 $dev" series enable + property "-circuit2 $dev" series {w critical} + property "-circuit2 $dev" series {l add} + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" parallel {value par} + property "-circuit2 $dev" tolerance {l 10.0} {w 10.0} + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#------------------------------------------- +# (MOS) transistors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__nfet_01v8 +lappend devices sky130_fd_pr__nfet_01v8_lvt +lappend devices sky130_fd_bs_flash__special_sonosfet_star +lappend devices sky130_fd_pr__nfet_g5v0d10v5 +lappend devices sky130_fd_pr__nfet_03v3_nvt +lappend devices sky130_fd_pr__nfet_05v0_nvt +lappend devices sky130_fd_pr__pfet_01v8 +lappend devices sky130_fd_pr__pfet_01v8_lvt +lappend devices sky130_fd_pr__pfet_01v8_mvt +lappend devices sky130_fd_pr__pfet_01v8_hvt +lappend devices sky130_fd_pr__pfet_g5v0d10v5 +lappend devices sky130_fd_pr__special_nfet_latch +lappend devices sky130_fd_pr__special_nfet_pass +lappend devices sky130_fd_pr__special_pfet_latch +lappend devices sky130_fd_pr__special_nfet_01v8 +lappend devices sky130_fd_pr__special_pfet_01v8_hvt +lappend devices sky130_fd_pr__cap_var_lvt +lappend devices sky130_fd_pr__cap_var_hvt +lappend devices sky130_fd_pr__cap_var + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" 1 3 + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" 1 3 + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } +} + +#--------------------------------------------------------------------- +# Extended drain MOSFET devices. These have asymmetric source and +# drain, and so the source and drain are not permutable. +#--------------------------------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__nfet_20v0_zvt +lappend devices sky130_fd_pr__nfet_20v0_nvt +lappend devices sky130_fd_pr__nfet_20v0_iso +lappend devices sky130_fd_pr__nfet_20v0 +lappend devices sky130_fd_pr__pfet_20v0 +lappend devices sky130_fd_pr__nfet_g5v0d16v0 +lappend devices sky130_fd_pr__pfet_g5v0d16v0 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } +} + +#--------------------------------------------------------------------- +# (MOS) ESD transistors. Note that the ESD transistors have a flanged +# gate. Magic disagrees slightly on how to interpret the width of the +# devices, so the tolerance is increased to 7% to cover the difference +#--------------------------------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__esd_nfet_g5v0d10v5 +lappend devices sky130_fd_pr__esd_pfet_g5v0d10v5 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" 1 3 + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" tolerance {w 0.07} {l 0.01} + # Ignore these properties + property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" 1 3 + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" tolerance {w 0.07} {l 0.01} + # Ignore these properties + property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } +} + +#------------------------------------------- +# diodes +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__diode_pw2nd_05v5 +lappend devices sky130_fd_pr__diode_pw2nd_05v5_lvt +lappend devices sky130_fd_pr__diode_pw2nd_05v5_nvt +lappend devices sky130_fd_pr__diode_pd2nw_05v5 +lappend devices sky130_fd_pr__diode_pd2nw_05v5_lvt +lappend devices sky130_fd_pr__diode_pd2nw_05v5_hvt +lappend devices sky130_fd_pr__diode_pw2nd_11v0 +lappend devices sky130_fd_pr__diode_pd2nw_11v0 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {area add} + property "-circuit1 $dev" parallel {pj add} + property "-circuit1 $dev" parallel {value add} + property "-circuit1 $dev" tolerance {area 0.02} {pj 0.02} + # Ignore these properties + property "-circuit1 $dev" delete mult perim + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {area add} + property "-circuit2 $dev" parallel {pj add} + property "-circuit2 $dev" parallel {value add} + property "-circuit2 $dev" tolerance {area 0.02} {pj 0.02} + # Ignore these properties + property "-circuit2 $dev" delete mult perim + } +} + +#------------------------------------------- +# capacitors +# MiM capacitors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__cap_mim_m3_1 +lappend devices sky130_fd_pr__cap_mim_m3_2 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {area add} + property "-circuit1 $dev" parallel {value add} + property "-circuit1 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit1 $dev" delete mult perim mf + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {area add} + property "-circuit2 $dev" parallel {value add} + property "-circuit2 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit2 $dev" delete mult perim mf + } +} + +#------------------------------------------- +# Fixed-layout devices +# bipolar transistors, +# VPP capacitors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__npn_05v5_W1p00L1p00 +lappend devices sky130_fd_pr__npn_05v5_W1p00L2p00 +lappend devices sky130_fd_pr__pnp_05v5_W0p68L0p68 +lappend devices sky130_fd_pr__pnp_05v5_W3p40L3p40 +lappend devices sky130_fd_pr__rf_npn_05v5_W1p00L1p00 +lappend devices sky130_fd_pr__rf_npn_05v5_W1p00L2p00 +lappend devices sky130_fd_pr__rf_pnp_05v5_W0p68L0p68 +lappend devices sky130_fd_pr__rf_pnp_05v5_W3p40L3p40 +lappend devices sky130_fd_pr__npn_05v5 +lappend devices sky130_fd_pr__pnp_05v5 +lappend devices sky130_fd_pr__npn_11v0 + +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m4_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_pom4_shield +lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_lim4_shield +lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_polym4_shield +lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_li_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_shield +lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_li_shield +lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_m3_shield +lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_li_shield +lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_shield +lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_li_shield +lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_shield +lappend devices sky130_fd_pr__ind_04_01 +lappend devices sky130_fd_pr__ind_04_02 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#--------------------------------------------------------------- +# Schematic cells which are not extractable +#--------------------------------------------------------------- + +set devices {sky130_fd_io__condiode sky130_fd_io__tap_1} + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + ignore class "-circuit1 $dev" + } + if {[lsearch $cells2 $dev] >= 0} { + ignore class "-circuit2 $dev" + } +} + +#--------------------------------------------------------------- +# Digital cells (ignore decap, fill, and tap cells) +# Make a separate list for each supported library +#--------------------------------------------------------------- +# e.g., ignore class "-circuit2 sky130_fc_sc_hd__decap_3" +#--------------------------------------------------------------- + +#--------------------------------------------------------------- +# Allow the fill, decap, etc., cells to be parallelized +#--------------------------------------------------------------- + +foreach cell $cells1 { + if {[regexp {.*sky130_.._sc_[^_]+__decap_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__fill_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__diode_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } +} +foreach cell $cells2 { + if {[regexp {sky130_ef_sc_[^_]+__decap_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } +} + +#--------------------------------------------------------------- +# Handle cells captured from Electric +# +# Find cells of the form "__" in the netlist +# from Electric where the extracted layout netlist has only +# "". Cross-check by ensuring that the full name +# "__" does not exist in both cells, and that +# the truncated name "" does not exist in both cells. +#--------------------------------------------------------------- +# e.g., hydra_spi_controller__hydra_spi_controller +#--------------------------------------------------------------- + +foreach cell $cells1 { + if {[regexp "(.+)__(.+)" $cell match library cellname]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0) && \ + ([lsearch $cells1 $cellname] < 0)} { + equate classes "-circuit1 $cell" "-circuit2 $cellname" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + #puts stdout "Matching pins of $cell in circuit 1 and $cellname in circuit 2" + #equate pins "-circuit1 $cell" "-circuit2 $cellname" + } + } +} + +foreach cell $cells2 { + if {[regexp "(.+)__(.+)" $cell match library cellname]} { + if {([lsearch $cells1 $cell] < 0) && \ + ([lsearch $cells1 $cellname] >= 0) && \ + ([lsearch $cells2 $cellname] < 0)} { + equate classes "-circuit1 $cellname" "-circuit2 $cell" + puts stdout "Equating $cellname in circuit 1 and $cell in circuit 2" + #puts stdout "Matching pins of $cellname in circuit 1 and $cell in circuit 2" + #equate pins "-circuit1 $cellname" "-circuit2 $cell" + } + } +} + +# Match pins on black-box cells if LVS is called with "-blackbox" +if {[model blackbox]} { + foreach cell $cells1 { + if {[model "-circuit1 $cell"] == "blackbox"} { + if {[lsearch $cells2 $cell] >= 0} { + puts stdout "Matching pins of $cell in circuits 1 and 2" + equate pins "-circuit1 $cell" "-circuit2 $cell" + } + } + } +} + +#--------------------------------------------------------------- +# Equate sram layout cells with corresponding source +foreach cell $cells1 { + if {[regexp {([A-Z][A-Z0-9]_)*sky130_sram_([^_]+)_([^_]+)_([^_]+)_([^_]+)_(.+)} $cell match prefix memory_size memory_type matrix io cellname]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0) && \ + ([lsearch $cells1 $cellname] < 0)} { + # netlist with the N names should always be the second netlist + equate classes "-circuit2 $cellname" "-circuit1 $cell" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + #equate pins "-circuit1 $cell" "-circuit2 $cellname" + } + } +} + +# Equate prefixed layout cells with corresponding source +foreach cell $cells1 { + set layout $cell + while {[regexp {([A-Z][A-Z0-9]_)(.*)} $layout match prefix cellname]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0)} { + # netlist with the N names should always be the second netlist + equate classes "-circuit2 $cellname" "-circuit1 $cell" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + #if { [lsearch $cells1 $cellname] > 0 } { + #equate classes "-circuit2 $cellname" "-circuit1 $cellname" + #puts stdout "Equating $cellname in circuit 1 and $cellname in circuit 2" + #} + #equate pins "-circuit1 $cell" "-circuit2 $cellname" + } + set layout $cellname + } +} + +# Equate suffixed layout cells with corresponding source +foreach cell $cells1 { + if {[regexp {(.*)(\$[0-9])} $cell match cellname suffix]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0)} { + # netlist with the N names should always be the second netlist + equate classes "-circuit2 $cellname" "-circuit1 $cell" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + } + } +} + +#Added programatically. diff --git a/scripts/be_checks/tech/sky130A/spi2cdl b/scripts/be_checks/tech/sky130A/spi2cdl new file mode 100755 index 00000000..3f4de4e8 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/spi2cdl @@ -0,0 +1,42 @@ +#! /bin/bash + +awk ' +/^X.*pr__diode.*=/ { + print "D" $0; + next; +} +/^X.*__special_[^ _]*fet.*=/ || /^X.*pr__.fet.*=/ || /^X.*pr__esd_.fet.*=/ || /^X.*[np]fet_[0-9]*v[0-9].*=/ { + print "M" $0; + next; +} +/^X.*pr__pnp_.*=/ || /^X.*pr__pnp_[^ ]* *$/ { + print "Q" $0; + next; +} +/^X.*pr__cap_mim_.*=/ || /^X.*mim_2p0fF.*=/ || /^X.*cap_mim_2f0_m4m5/ { + print "C" $0; + next; +} +/^X.*pr__cap_var.*=/ { + bulk = $4; + $4 = ""; + print "C" $0, "$SUB=" bulk; + next; +} +/^X.*pr__res_.*=/ || /^X.*ppolyf_u_1k_6p0/ { + bulk = $4; + $4 = ""; + print "R" $0, "$SUB=" bulk; + next; +} +/^X.*sky130_fd_pr__reram_reram_cell.*=/ { + print "R" $0; + next; +} +/^R/ && NF == 4 && $4 == "0.000000" { + $4 = "short " $4; +} + { + print $0; +}' $1 + diff --git a/scripts/be_checks/tech/sky130A/user_analog_project_wrapper_dummy.v b/scripts/be_checks/tech/sky130A/user_analog_project_wrapper_dummy.v new file mode 100644 index 00000000..ef2ad663 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/user_analog_project_wrapper_dummy.v @@ -0,0 +1,123 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_analog_project_wrapper + * + * This wrapper enumerates all of the pins available to the + * user for the user analog project. + * + *------------------------------------------------------------- + */ + +/// sta-blackbox +module user_analog_project_wrapper ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + /* GPIOs. There are 27 GPIOs, on either side of the analog. + * These have the following mapping to the GPIO padframe pins + * and memory-mapped registers, since the numbering remains the + * same as caravel but skips over the analog I/O: + * + * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25] + * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0] + * + * When the GPIOs are configured by the Management SoC for + * user use, they have three basic bidirectional controls: + * in, out, and oeb (output enable, sense inverted). For + * analog projects, a 3.3V copy of the signal input is + * available. out and oeb must be 1.8V signals. + */ + + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in, + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb, + + /* Analog (direct connection to GPIO pad---not for high voltage or + * high frequency use). The management SoC must turn off both + * input and output buffers on these GPIOs to allow analog access. + * These signals may drive a voltage up to the value of VDDIO + * (3.3V typical, 5.5V maximum). + * + * Note that analog I/O is not available on the 7 lowest-numbered + * GPIO pads, and so the analog_io indexing is offset from the + * GPIO indexing by 7, as follows: + * + * gpio_analog/noesd [17:7] <---> mprj_io[35:25] + * gpio_analog/noesd [6:0] <---> mprj_io[13:7] + * + */ + + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog, + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd, + + /* Analog signals, direct through to pad. These have no ESD at all, + * so ESD protection is the responsibility of the designer. + * + * user_analog[10:0] <---> mprj_io[24:14] + * + */ + inout [`ANALOG_PADS-1:0] io_analog, + + /* Additional power supply ESD clamps, one per analog pad. The + * high side should be connected to a 3.3-5.5V power supply. + * The low side should be connected to ground. + * + * clamp_high[2:0] <---> mprj_io[20:18] + * clamp_low[2:0] <---> mprj_io[20:18] + * + */ + inout [2:0] io_clamp_high, + inout [2:0] io_clamp_low, + + // Independent clock (on independent integer divider) + input user_clock2, + + // User maskable interrupt signals + output [2:0] user_irq +); + + +endmodule // user_analog_project_wrapper diff --git a/scripts/be_checks/tech/sky130A/user_project_wrapper_dummy.v b/scripts/be_checks/tech/sky130A/user_project_wrapper_dummy.v new file mode 100644 index 00000000..bf76cf09 --- /dev/null +++ b/scripts/be_checks/tech/sky130A/user_project_wrapper_dummy.v @@ -0,0 +1,87 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_project_wrapper + * + * This wrapper enumerates all of the pins available to the + * user for the user project. + * + * An example user project is provided in this wrapper. The + * example should be removed and replaced with the actual + * user project. + * + *------------------------------------------------------------- + */ + +module user_project_wrapper #( + parameter BITS = 32 +) ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb, + + // Analog (direct connection to GPIO pad---use with caution) + // Note that analog I/O is not available on the 7 lowest-numbered + // GPIO pads, and so the analog_io indexing is offset from the + // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io). + inout [`MPRJ_IO_PADS-10:0] analog_io, + + // Independent clock (on independent integer divider) + input user_clock2, + + // User maskable interrupt signals + output [2:0] user_irq +); + +/*--------------------------------------*/ +/* User project is instantiated here */ +/*--------------------------------------*/ + +endmodule // user_project_wrapper + +`default_nettype wire diff --git a/scripts/be_checks/tech/sky130B/caravan_core.v.sed b/scripts/be_checks/tech/sky130B/caravan_core.v.sed new file mode 100644 index 00000000..da53f7f7 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/caravan_core.v.sed @@ -0,0 +1,42 @@ +s/.gpio_control_bidir_1.0..gpio_defaults/gpio_defaults[0]/g +s/.gpio_control_bidir_1.1..gpio_defaults/gpio_defaults[1]/g +s/.gpio_control_in_1.2..gpio_defaults/gpio_defaults[10]/g +s/.gpio_control_in_1.3..gpio_defaults/gpio_defaults[11]/g +s/.gpio_control_in_1.4..gpio_defaults/gpio_defaults[12]/g +s/.gpio_control_in_1.5..gpio_defaults/gpio_defaults[13]/g +s/.gpio_control_in_1a.0..gpio_defaults/gpio_defaults[2]/g +s/.gpio_control_in_2.0..gpio_defaults/gpio_defaults[25]/g +s/.gpio_control_in_2.1..gpio_defaults/gpio_defaults[26]/g +s/.gpio_control_in_2.2..gpio_defaults/gpio_defaults[27]/g +s/.gpio_control_in_2.3..gpio_defaults/gpio_defaults[28]/g +s/.gpio_control_in_2.4..gpio_defaults/gpio_defaults[29]/g +s/.gpio_control_in_1a.1..gpio_defaults/gpio_defaults[3]/g +s/.gpio_control_in_2.5..gpio_defaults/gpio_defaults[30]/g +s/.gpio_control_in_2.6..gpio_defaults/gpio_defaults[31]/g +s/.gpio_control_in_2.7..gpio_defaults/gpio_defaults[32]/g +s/.gpio_control_in_2.8..gpio_defaults/gpio_defaults[33]/g +s/.gpio_control_in_2.9..gpio_defaults/gpio_defaults[34]/g +s/.gpio_control_bidir_2.0..gpio_defaults/gpio_defaults[35]/g +s/.gpio_control_bidir_2.1..gpio_defaults/gpio_defaults[36]/g +s/.gpio_control_bidir_2.2..gpio_defaults/gpio_defaults[37]/g +s/.gpio_control_in_1a.2..gpio_defaults/gpio_defaults[4]/g +s/.gpio_control_in_1a.3..gpio_defaults/gpio_defaults[5]/g +s/.gpio_control_in_1a.4..gpio_defaults/gpio_defaults[6]/g +s/.gpio_control_in_1a.5..gpio_defaults/gpio_defaults[7]/g +s/.gpio_control_in_1.0..gpio_defaults/gpio_defaults[8]/g +s/.gpio_control_in_1.1..gpio_defaults/gpio_defaults[9]/g +s/\\mask_rev/mask_rev/g +/wire mask_rev/d +/wire gpio_defaults/d +s/^ user_gpio_noesd);/ user_gpio_noesd,\ + gpio_defaults_out,\ + mask_rev);/ +s/^ inout .17:0. user_gpio_noesd;/ inout [17:0] user_gpio_noesd;\ + output [38*13-1:0] gpio_defaults_out;\ + output [31:0] mask_rev;\ +\ + wire [12:0] gpio_defaults [37:0];\ + genvar i;\ + generate for (i = 0; i < 38; i = i+1) begin:instgpio\ + assign gpio_defaults_out[13*i +: 13] = gpio_defaults[i];\ + end endgenerate/ diff --git a/scripts/be_checks/tech/sky130B/caravan_gpio_test.v b/scripts/be_checks/tech/sky130B/caravan_gpio_test.v new file mode 100644 index 00000000..6379a15d --- /dev/null +++ b/scripts/be_checks/tech/sky130B/caravan_gpio_test.v @@ -0,0 +1,173 @@ +module gpio_test; + + wire clock_core; + wire flash_clk_frame; + wire flash_clk_oeb; + wire flash_csb_frame; + wire flash_csb_oeb; + wire flash_io0_di; + wire flash_io0_do; + wire flash_io0_ieb; + wire flash_io0_oeb; + wire flash_io1_di; + wire flash_io1_do; + wire flash_io1_ieb; + wire flash_io1_oeb; + wire gpio_in_core; + wire gpio_inenb_core; + wire gpio_mode0_core; + wire gpio_mode1_core; + wire gpio_out_core; + wire gpio_outenb_core; + wire por_l; + wire porb_h; + wire rstb_h; + wire vccd; + wire vssd; + wire vccd1; + wire vssd1; + wire vssd2; + wire vccd2; + wire vssa1; + wire vdda2; + wire vssa2; + wire vdda1; + wire vddio; + wire vssio; + wire [26:0] mprj_io_analog_en; + wire [26:0] mprj_io_analog_pol; + wire [26:0] mprj_io_analog_sel; + wire [80:0] mprj_io_dm; + wire [26:0] mprj_io_holdover; + wire [26:0] mprj_io_ib_mode_sel; + wire [26:0] mprj_io_in; + wire [26:0] mprj_io_in_3v3; + wire [26:0] mprj_io_inp_dis; + wire [26:0] mprj_io_oeb; + wire [26:0] mprj_io_one; + wire [26:0] mprj_io_out; + wire [26:0] mprj_io_slow_sel; + wire [26:0] mprj_io_vtrip_sel; + wire [10:0] user_analog; + wire [2:0] user_clamp_high; + wire [2:0] user_clamp_low; + wire [17:0] user_gpio_analog; + wire [17:0] user_gpio_noesd; + + wire [38*13-1:0] all_gpio_defaults; + + wire [12:0] gpio_defaults [37:0]; + wire [31:0] mask_rev; + + assign vccd = 1; + assign vssd = 0; + + genvar i; + generate for (i = 0; i < 38; i = i+1) begin:instgpio + assign gpio_defaults[i] = all_gpio_defaults[13*i +: 13]; + end endgenerate + + caravan_core chip_core ( + .clock_core(clock_core), + .flash_clk_frame(flash_clk_frame), + .flash_clk_oeb(flash_clk_oeb), + .flash_csb_frame(flash_csb_frame), + .flash_csb_oeb(flash_csb_oeb), + .flash_io0_di(flash_io0_di), + .flash_io0_do(flash_io0_do), + .flash_io0_ieb(flash_io0_ieb), + .flash_io0_oeb(flash_io0_oeb), + .flash_io1_di(flash_io1_di), + .flash_io1_do(flash_io1_do), + .flash_io1_ieb(flash_io1_ieb), + .flash_io1_oeb(flash_io1_oeb), + .gpio_in_core(gpio_in_core), + .gpio_inenb_core(gpio_inenb_core), + .gpio_mode0_core(gpio_mode0_core), + .gpio_mode1_core(gpio_mode1_core), + .gpio_out_core(gpio_out_core), + .gpio_outenb_core(gpio_outenb_core), + .mprj_io_analog_en(mprj_io_analog_en), + .mprj_io_analog_pol(mprj_io_analog_pol), + .mprj_io_analog_sel(mprj_io_analog_sel), + .mprj_io_dm(mprj_io_dm), + .mprj_io_holdover(mprj_io_holdover), + .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel), + .mprj_io_in(mprj_io_in), + .mprj_io_in_3v3(mprj_io_in_3v3), + .mprj_io_inp_dis(mprj_io_inp_dis), + .mprj_io_oeb(mprj_io_oeb ), + .mprj_io_one(mprj_io_one ), + .mprj_io_out(mprj_io_out ), + .mprj_io_slow_sel(mprj_io_slow_sel ), + .mprj_io_vtrip_sel(mprj_io_vtrip_sel ), + .por_l(por_l), + .porb_h(porb_h), + .rstb_h(rstb_h), + .user_analog(user_analog ), + .user_clamp_high(user_clamp_high ), + .user_clamp_low(user_clamp_low ), + .user_gpio_analog(user_gpio_analog ), + .user_gpio_noesd(user_gpio_noesd ), + .vccd(vccd), + .vccd1(vccd1), + .vccd2(vccd2), + .vdda1(vdda1), + .vdda2(vdda2), + .vddio(vddio), + .vssa1(vssa1), + .vssa2(vssa2), + .vssd(vssd), + .vssd1(vssd1), + .vssd2(vssd2), + .vssio(vssio), + .gpio_defaults_out(all_gpio_defaults), + .mask_rev(mask_rev) + ); + +initial begin + #10 $monitor("Actual"); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 0, gpio_defaults[0]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 1, gpio_defaults[1]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 2, gpio_defaults[2]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 3, gpio_defaults[3]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 4, gpio_defaults[4]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 5, gpio_defaults[5]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 6, gpio_defaults[6]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 7, gpio_defaults[7]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 8, gpio_defaults[8]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 9, gpio_defaults[9]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 10, gpio_defaults[10]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 11, gpio_defaults[11]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 12, gpio_defaults[12]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 13, gpio_defaults[13]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 14, gpio_defaults[14]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 15, gpio_defaults[15]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 16, gpio_defaults[16]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 17, gpio_defaults[17]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 18, gpio_defaults[18]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 19, gpio_defaults[19]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 20, gpio_defaults[20]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 21, gpio_defaults[21]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 22, gpio_defaults[22]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 23, gpio_defaults[23]); + //#10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 24, gpio_defaults[24]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 25, gpio_defaults[25]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 26, gpio_defaults[26]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 27, gpio_defaults[27]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 28, gpio_defaults[28]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 29, gpio_defaults[29]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 30, gpio_defaults[30]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 31, gpio_defaults[31]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 32, gpio_defaults[32]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 33, gpio_defaults[33]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 34, gpio_defaults[34]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 35, gpio_defaults[35]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 36, gpio_defaults[36]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 37, gpio_defaults[37]); + #10 $monitor("Setting Project Chip ID to: %h", mask_rev); + #100 $stop; +end + +endmodule // gpio_test + diff --git a/scripts/be_checks/tech/sky130B/caravel_core.v.sed b/scripts/be_checks/tech/sky130B/caravel_core.v.sed new file mode 100644 index 00000000..050312b5 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/caravel_core.v.sed @@ -0,0 +1,53 @@ +s/.gpio_control_bidir_1.0..gpio_defaults/gpio_defaults[0]/g +s/.gpio_control_bidir_1.1..gpio_defaults/gpio_defaults[1]/g +s/.gpio_control_in_1.2..gpio_defaults/gpio_defaults[10]/g +s/.gpio_control_in_1.3..gpio_defaults/gpio_defaults[11]/g +s/.gpio_control_in_1.4..gpio_defaults/gpio_defaults[12]/g +s/.gpio_control_in_1.5..gpio_defaults/gpio_defaults[13]/g +s/.gpio_control_in_1.6..gpio_defaults/gpio_defaults[14]/g +s/.gpio_control_in_1.7..gpio_defaults/gpio_defaults[15]/g +s/.gpio_control_in_1.8..gpio_defaults/gpio_defaults[16]/g +s/.gpio_control_in_1.9..gpio_defaults/gpio_defaults[17]/g +s/.gpio_control_in_1.10..gpio_defaults/gpio_defaults[18]/g +s/.gpio_control_in_2.0..gpio_defaults/gpio_defaults[19]/g +s/.gpio_control_in_1a.0..gpio_defaults/gpio_defaults[2]/g +s/.gpio_control_in_2.1..gpio_defaults/gpio_defaults[20]/g +s/.gpio_control_in_2.2..gpio_defaults/gpio_defaults[21]/g +s/.gpio_control_in_2.3..gpio_defaults/gpio_defaults[22]/g +s/.gpio_control_in_2.4..gpio_defaults/gpio_defaults[23]/g +s/.gpio_control_in_2.5..gpio_defaults/gpio_defaults[24]/g +s/.gpio_control_in_2.6..gpio_defaults/gpio_defaults[25]/g +s/.gpio_control_in_2.7..gpio_defaults/gpio_defaults[26]/g +s/.gpio_control_in_2.8..gpio_defaults/gpio_defaults[27]/g +s/.gpio_control_in_2.9..gpio_defaults/gpio_defaults[28]/g +s/.gpio_control_in_2.10..gpio_defaults/gpio_defaults[29]/g +s/.gpio_control_in_1a.1..gpio_defaults/gpio_defaults[3]/g +s/.gpio_control_in_2.11..gpio_defaults/gpio_defaults[30]/g +s/.gpio_control_in_2.12..gpio_defaults/gpio_defaults[31]/g +s/.gpio_control_in_2.13..gpio_defaults/gpio_defaults[32]/g +s/.gpio_control_in_2.14..gpio_defaults/gpio_defaults[33]/g +s/.gpio_control_in_2.15..gpio_defaults/gpio_defaults[34]/g +s/.gpio_control_bidir_2.0..gpio_defaults/gpio_defaults[35]/g +s/.gpio_control_bidir_2.1..gpio_defaults/gpio_defaults[36]/g +s/.gpio_control_bidir_2.2..gpio_defaults/gpio_defaults[37]/g +s/.gpio_control_in_1a.2..gpio_defaults/gpio_defaults[4]/g +s/.gpio_control_in_1a.3..gpio_defaults/gpio_defaults[5]/g +s/.gpio_control_in_1a.4..gpio_defaults/gpio_defaults[6]/g +s/.gpio_control_in_1a.5..gpio_defaults/gpio_defaults[7]/g +s/.gpio_control_in_1.0..gpio_defaults/gpio_defaults[8]/g +s/.gpio_control_in_1.1..gpio_defaults/gpio_defaults[9]/g +s/\\mask_rev/mask_rev/g +/wire mask_rev/d +/wire gpio_defaults/d +s/^ mprj_io_vtrip_sel);/ mprj_io_vtrip_sel,\ + gpio_defaults_out,\ + mask_rev);/ +s/^ output .37:0. mprj_io_vtrip_sel;/ output [37:0] mprj_io_vtrip_sel;\ + output [38*13-1:0] gpio_defaults_out;\ + output [31:0] mask_rev;\ +\ + wire [12:0] gpio_defaults [37:0];\ + genvar i;\ + generate for (i = 0; i < 38; i = i+1) begin:instgpio\ + assign gpio_defaults_out[13*i +: 13] = gpio_defaults[i];\ + end endgenerate/ diff --git a/scripts/be_checks/tech/sky130B/caravel_gpio_test.v b/scripts/be_checks/tech/sky130B/caravel_gpio_test.v new file mode 100644 index 00000000..09c297c7 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/caravel_gpio_test.v @@ -0,0 +1,163 @@ +module gpio_test; + + wire clock_core; + wire [7:0] value; + wire flash_clk_frame; + wire flash_clk_oeb; + wire flash_csb_frame; + wire flash_csb_oeb; + wire flash_io0_di; + wire flash_io0_do; + wire flash_io0_ieb; + wire flash_io0_oeb; + wire flash_io1_di; + wire flash_io1_do; + wire flash_io1_ieb; + wire flash_io1_oeb; + wire gpio_in_core; + wire gpio_inenb_core; + wire gpio_mode0_core; + wire gpio_mode1_core; + wire gpio_out_core; + wire gpio_outenb_core; + wire por_l; + wire porb_h; + wire rstb_h; + wire vccd; + wire vssd; + wire vccd1; + wire vssd1; + wire vssa2; + wire vdda2; + wire vssa1; + wire vdda1; + wire vssd2; + wire vccd2; + wire vddio; + wire vssio; + wire [28:0] mprj_analog_io; + wire [37:0] mprj_io_analog_en; + wire [37:0] mprj_io_analog_pol; + wire [37:0] mprj_io_analog_sel; + wire [113:0] mprj_io_dm; + wire [37:0] mprj_io_holdover; + wire [37:0] mprj_io_ib_mode_sel; + wire [37:0] mprj_io_in; + wire [37:0] mprj_io_inp_dis; + wire [37:0] mprj_io_oeb; + wire [37:0] mprj_io_one; + wire [37:0] mprj_io_out; + wire [37:0] mprj_io_slow_sel; + wire [37:0] mprj_io_vtrip_sel; + wire [38*13-1:0] all_gpio_defaults; + + wire [12:0] gpio_defaults [37:0]; + wire [31:0] mask_rev; + + assign vccd = 1; + assign vssd = 0; + + genvar i; + generate for (i = 0; i < 38; i = i+1) begin:instgpio + assign gpio_defaults[i] = all_gpio_defaults[13*i +: 13]; + end endgenerate + + caravel_core caravel_core_0 ( + .clock_core(clock_core), + .flash_clk_frame(flash_clk_frame), + .flash_clk_oeb(flash_clk_oeb), + .flash_csb_frame(flash_csb_frame), + .flash_csb_oeb(flash_csb_oeb), + .flash_io0_di(flash_io0_di), + .flash_io0_do(flash_io0_do), + .flash_io0_ieb(flash_io0_ieb), + .flash_io0_oeb(flash_io0_oeb), + .flash_io1_di(flash_io1_di), + .flash_io1_do(flash_io1_do), + .flash_io1_ieb(flash_io1_ieb), + .flash_io1_oeb(flash_io1_oeb), + .gpio_in_core(gpio_in_core), + .gpio_inenb_core(gpio_inenb_core), + .gpio_mode0_core(gpio_mode0_core), + .gpio_mode1_core(gpio_mode1_core), + .gpio_out_core(gpio_out_core), + .gpio_outenb_core(gpio_outenb_core), + .por_l(por_l), + .porb_h(porb_h), + .rstb_h(rstb_h), + .vccd(vccd), + .vssd(vssd), + .vccd1(vccd1), + .vssd1(vssd1), + .vssa2(vssa2), + .vdda2(vdda2), + .vssa1(vssa1), + .vdda1(vdda1), + .vssd2(vssd2), + .vccd2(vccd2), + .vddio(vddio), + .vssio(vssio), + .mprj_analog_io(mprj_analog_io), + .mprj_io_analog_en(mprj_io_analog_en), + .mprj_io_analog_pol(mprj_io_analog_pol), + .mprj_io_analog_sel(mprj_io_analog_sel), + .mprj_io_dm(mprj_io_dm), + .mprj_io_holdover(mprj_io_holdover), + .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel), + .mprj_io_in(mprj_io_in), + .mprj_io_inp_dis(mprj_io_inp_dis), + .mprj_io_oeb(mprj_io_oeb), + .mprj_io_one(mprj_io_one), + .mprj_io_out(mprj_io_out), + .mprj_io_slow_sel(mprj_io_slow_sel), + .mprj_io_vtrip_sel(mprj_io_vtrip_sel), + .gpio_defaults_out(all_gpio_defaults), + .mask_rev(mask_rev) + ); + +initial begin + #10 $monitor("Actual"); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 0, gpio_defaults[0]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 1, gpio_defaults[1]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 2, gpio_defaults[2]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 3, gpio_defaults[3]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 4, gpio_defaults[4]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 5, gpio_defaults[5]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 6, gpio_defaults[6]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 7, gpio_defaults[7]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 8, gpio_defaults[8]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 9, gpio_defaults[9]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 10, gpio_defaults[10]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 11, gpio_defaults[11]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 12, gpio_defaults[12]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 13, gpio_defaults[13]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 14, gpio_defaults[14]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 15, gpio_defaults[15]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 16, gpio_defaults[16]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 17, gpio_defaults[17]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 18, gpio_defaults[18]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 19, gpio_defaults[19]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 20, gpio_defaults[20]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 21, gpio_defaults[21]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 22, gpio_defaults[22]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 23, gpio_defaults[23]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 24, gpio_defaults[24]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 25, gpio_defaults[25]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 26, gpio_defaults[26]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 27, gpio_defaults[27]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 28, gpio_defaults[28]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 29, gpio_defaults[29]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 30, gpio_defaults[30]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 31, gpio_defaults[31]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 32, gpio_defaults[32]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 33, gpio_defaults[33]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 34, gpio_defaults[34]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 35, gpio_defaults[35]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 36, gpio_defaults[36]); + #10 $monitor("USER_CONFIG_GPIO_%1d_INIT %h", 37, gpio_defaults[37]); + #10 $monitor("Setting Project Chip ID to: %h", mask_rev); + #100 $stop; +end + +endmodule // gpio_test + diff --git a/scripts/be_checks/tech/sky130B/cvc.models b/scripts/be_checks/tech/sky130B/cvc.models new file mode 100644 index 00000000..fd208319 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/cvc.models @@ -0,0 +1,81 @@ +MN nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8 +MP pfet_01v8_hvt Vth=-0.2 Vgs=1.8 Vds=1.8 + +R short model=switch_on + +D sky130_fd_pr__diode_pw2nd_05v5 +D sky130_fd_pr__diode_pw2nd_11v0 +D sky130_fd_pr__diode_pw2nd_05v5_lvt +D sky130_fd_pr__diode_pw2nd_05v5_nvt +D sky130_fd_pr__diode_pd2nw_05v5 +D sky130_fd_pr__diode_pd2nw_05v5_lvt +D sky130_fd_pr__diode_pd2nw_11v0 +D sky130_fd_pr__model__parasitic__diode_ps2dn +D sky130_fd_pr__model__parasitic__diode_ps2nw +D sky130_fd_pr__model__parasitic__diode_pw2dn +D condiode + + +#R sky130_fd_pr__res_generic_m1 R=l/w*0.125 +#R sky130_fd_pr__res_generic_m2 R=l/w*0.125 +#R sky130_fd_pr__res_generic_m3 R=l/w*0.047 +#R sky130_fd_pr__res_generic_m4 R=l/w*0.047 +#R sky130_fd_pr__res_generic_nd R=l/w*0.029 +R sky130_fd_pr__res_generic_l1 model=switch_on +R sky130_fd_pr__res_generic_m1 model=switch_on +R sky130_fd_pr__res_generic_m2 model=switch_on +R sky130_fd_pr__res_generic_m3 model=switch_on +R sky130_fd_pr__res_generic_m4 model=switch_on +R sky130_fd_pr__res_generic_m5 model=switch_on +R sky130_fd_pr__res_generic_nd R=l/w*120 +R sky130_fd_pr__res_generic_pd R=l/w*197 +R sky130_fd_pr__res_generic_nd__hv R=l/w*114 +R sky130_fd_pr__res_generic_pd__hv R=l/w*191 +R sky130_fd_pr__res_generic_po R=l/w*48 +R sky130_fd_pr__res_xhigh_po R=l/w*2000 +R sky130_fd_pr__res_xhigh_po_0p35 R=l/0.35*2000 +R sky130_fd_pr__res_xhigh_po_0p69 R=l/0.69*2000 +R sky130_fd_pr__res_xhigh_po_1p41 R=l/1.41*2000 +R sky130_fd_pr__res_xhigh_po_2p85 R=l/2.85*2000 +R sky130_fd_pr__res_xhigh_po_5p73 R=l/5.73*2000 +R sky130_fd_pr__res_high_po R=l/w*300 +R sky130_fd_pr__res_high_po_0p35 R=l/0.35*300 +R sky130_fd_pr__res_high_po_0p69 R=l/0.69*300 +R sky130_fd_pr__res_high_po_1p41 R=l/1.41*300 +R sky130_fd_pr__res_high_po_2p85 R=l/2.85*300 +R sky130_fd_pr__res_high_po_5p73 R=l/5.73*300 +R sky130_fd_pr__res_iso_pw R=l/w*4400 +R sky130_fd_pr_reram__reram_cell R=10 +R sky130_fd_pr__reram_reram_cell R=10 + +MN sky130_fd_pr__nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__special_nfet_01v8 Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__nfet_01v8_lvt Vth=0.1 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__special_nfet_latch Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__special_nfet_pass Vth=0.2 Vgs=1.8 Vds=1.8 +MN sky130_fd_pr__nfet_03v3_nvt Vth=0.2 Vgs=3.3 Vds=3.3 +MN sky130_fd_pr__esd_nfet_g5v0d10v5 Vth=0.2 +MN sky130_fd_pr__nfet_05v0_nvt Vth=0.2 +MN sky130_fd_pr__nfet_g5v0d10v5 Vth=0.2 +MN sky130_fd_bs_flash__special_sonosfet_star Vth=0.2 + +MP sky130_fd_pr__pfet_01v8 Vth=-0.2 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__pfet_01v8_lvt Vth=-0.1 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__pfet_01v8_hvt Vth=-0.3 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__special_pfet_01v8_hvt Vth=-0.3 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__special_pfet_pass Vth=-0.2 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__special_pfet_latch Vth=-0.2 Vgs=1.8 Vds=1.8 +MP sky130_fd_pr__pfet_g5v0d10v5 Vth=-0.2 + +C sky130_fd_pr__cap_mim_m3_1 +C sky130_fd_pr__cap_mim_m3_2 +C sky130_fd_pr__cap_var +C sky130_fd_pr__cap_var_lvt + +Q sky130_fd_pr__pnp_05v5 +Q sky130_fd_pr__pnp_05v5_W0p68L0p68 +Q sky130_fd_pr__pnp_05v5_W3p40L3p40 +Q sky130_fd_pr__npn_11v0 +Q sky130_fd_pr__npn_11v0_W1p00L1p00 + + diff --git a/scripts/be_checks/tech/sky130B/cvc.power.caravan b/scripts/be_checks/tech/sky130B/cvc.power.caravan new file mode 100644 index 00000000..2f854a41 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/cvc.power.caravan @@ -0,0 +1,19 @@ +vccd power 1.8 +vccd1 power 1.8 +vccd2 power 1.8 +vdda power 3.3 +vdda1 power 3.3 +vdda1_2 power 3.3 +vdda2 power 3.3 +vddio power 3.3 +vddio_2 power 3.3 +vssa power 0.0 +vssa1 power 0.0 +vssa1_2 power 0.0 +vssa2 power 0.0 +vssd power 0.0 +vssd1 power 0.0 +vssd2 power 0.0 +vssio power 0.0 +vssio_2 power 0.0 +mprj_io[18] power 3.3 diff --git a/scripts/be_checks/tech/sky130B/cvc.power.caravel b/scripts/be_checks/tech/sky130B/cvc.power.caravel new file mode 100644 index 00000000..f80e6dc5 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/cvc.power.caravel @@ -0,0 +1,18 @@ +vccd power 1.8 +vccd1 power 1.8 +vccd2 power 1.8 +vdda power 3.3 +vdda1 power 3.3 +vdda1_2 power 3.3 +vdda2 power 3.3 +vddio power 3.3 +vddio_2 power 3.3 +vssa power 0.0 +vssa1 power 0.0 +vssa1_2 power 0.0 +vssa2 power 0.0 +vssd power 0.0 +vssd1 power 0.0 +vssd2 power 0.0 +vssio power 0.0 +vssio_2 power 0.0 diff --git a/scripts/be_checks/tech/sky130B/cvc.power.user_analog_project_wrapper b/scripts/be_checks/tech/sky130B/cvc.power.user_analog_project_wrapper new file mode 100644 index 00000000..e72e2e24 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/cvc.power.user_analog_project_wrapper @@ -0,0 +1,18 @@ +vccd* power 1.8 +vdda* power 3.3 +vssa* power 0.0 +vssd* power 0.0 +io_analog[*] input min@0.0 max@1.8 +wb_clk_i input min@0.0 max@1.8 +wb_rst_i input min@0.0 max@1.8 +wbs_stb_i input min@0.0 max@1.8 +wbs_cyc_i input min@0.0 max@1.8 +wbs_we_i input min@0.0 max@1.8 +wbs_sel_i[*] input min@0.0 max@1.8 +wbs_dat_i[*] input min@0.0 max@1.8 +wbs_adr_i[*] input min@0.0 max@1.8 +la_data_in[*] input min@0.0 max@1.8 +la_oenb[*] input min@0.0 max@1.8 +io_in[*] input min@0.0 max@1.8 +io_in_3v3[*] input min@0.0 max@3.3 +user_clock2 input min@0.0 max@1.8 diff --git a/scripts/be_checks/tech/sky130B/cvc.power.user_project_wrapper b/scripts/be_checks/tech/sky130B/cvc.power.user_project_wrapper new file mode 100644 index 00000000..8c3b6aac --- /dev/null +++ b/scripts/be_checks/tech/sky130B/cvc.power.user_project_wrapper @@ -0,0 +1,17 @@ +vccd* power 1.8 +vdda* power 3.3 +vssa* power 0.0 +vssd* power 0.0 +user_clock2 input min@0.0 max@1.8 +wb_clk_i input min@0.0 max@1.8 +wb_rst_i input min@0.0 max@1.8 +wbs_cyc_i input min@0.0 max@1.8 +wbs_stb_i input min@0.0 max@1.8 +wbs_we_i input min@0.0 max@1.8 +io_in[*] input min@0.0 max@1.8 +la_data_in[*] input min@0.0 max@1.8 +la_oenb[*] input min@0.0 max@1.8 +wbs_adr_i[*] input min@0.0 max@1.8 +wbs_dat_i[*] input min@0.0 max@1.8 +wbs_sel_i[*] input min@0.0 max@1.8 + diff --git a/scripts/be_checks/tech/sky130B/cvcrc b/scripts/be_checks/tech/sky130B/cvcrc new file mode 100644 index 00000000..ead440be --- /dev/null +++ b/scripts/be_checks/tech/sky130B/cvcrc @@ -0,0 +1,35 @@ +CVC_TOP = $DESIGN_NAME +CVC_NETLIST = $RESULTS_DIR/$CVC_TOP.cdl.gz +CVC_MODE = $CVC_TOP +CVC_MODEL_FILE = $LVS_ROOT/tech/$PDK/cvc.models +CVC_POWER_FILE = $WORK_ROOT/cvc.power.$CVC_TOP +CVC_FUSE_FILE = '' +CVC_REPORT_FILE = $WORK_ROOT/cvc.log +CVC_REPORT_TITLE = "CVC $CVC_TOP" +CVC_CIRCUIT_ERROR_LIMIT = '100' +CVC_SEARCH_LIMIT = '100' +CVC_LEAK_LIMIT = '0.0002' +CVC_SOI = 'false' +CVC_SCRC = 'false' +CVC_VTH_GATES = 'false' +CVC_MIN_VTH_GATES = 'false' +CVC_IGNORE_VTH_FLOATING = 'false' +CVC_IGNORE_NO_LEAK_FLOATING = 'false' +CVC_LEAK_OVERVOLTAGE = 'true' +CVC_LOGIC_DIODES = 'false' +CVC_ANALOG_GATES = 'true' +CVC_BACKUP_RESULTS = 'false' +CVC_MOS_DIODE_ERROR_THRESHOLD = '0' +CVC_SHORT_ERROR_THRESHOLD = '0' +CVC_BIAS_ERROR_THRESHOLD = '0' +CVC_FORWARD_ERROR_THRESHOLD = '0' +CVC_FLOATING_ERROR_THRESHOLD = '0' +CVC_GATE_ERROR_THRESHOLD = '0' +CVC_LEAK?_ERROR_THRESHOLD = '0' +CVC_EXPECTED_ERROR_THRESHOLD = '0' +CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0' +CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0' +CVC_CELL_ERROR_LIMIT_FILE = '' +CVC_CELL_CHECKSUM_FILE = '' +CVC_LARGE_CIRCUIT_SIZE = '10000000' +CVC_NET_CHECK_FILE = '' diff --git a/scripts/be_checks/tech/sky130B/expected_gpio b/scripts/be_checks/tech/sky130B/expected_gpio new file mode 100644 index 00000000..9a2e4706 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/expected_gpio @@ -0,0 +1,6 @@ +Expected +USER_CONFIG_GPIO_0_INIT 1803 +USER_CONFIG_GPIO_1_INIT 1803 +USER_CONFIG_GPIO_2_INIT 0403 +USER_CONFIG_GPIO_3_INIT 0801 +USER_CONFIG_GPIO_4_INIT 0403 diff --git a/scripts/be_checks/tech/sky130B/known.undefined.layer b/scripts/be_checks/tech/sky130B/known.undefined.layer new file mode 100644 index 00000000..e69de29b diff --git a/scripts/be_checks/tech/sky130B/known_abstract_filter.awk b/scripts/be_checks/tech/sky130B/known_abstract_filter.awk new file mode 100644 index 00000000..3652cba3 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/known_abstract_filter.awk @@ -0,0 +1,6 @@ +/__fill_/ {next} # ignore abstract devices +/__tapvpwrvgnd_/ {next} +/__fakediode_/ {next} +/sky130_fd_pr__/ {next} # ignore primitive devices +/sky130_fd_pr_reram__/ {next} # ignore primitive reram devices +{ print } diff --git a/scripts/be_checks/tech/sky130B/lvs_config.base.json b/scripts/be_checks/tech/sky130B/lvs_config.base.json new file mode 100644 index 00000000..08982d72 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.base.json @@ -0,0 +1,25 @@ +{ + "EXTRACT_FLATGLOB": [ + "*sky130_fd_pr__*[A-Z]*" + ], + "EXTRACT_ABSTRACT": [ + "*__fill_*", + "*__fakediode_*", + "*__tapvpwrvgnd_*" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$PDK_ROOT/$PDK/libs.ref/$STD_CELL_LIBRARY/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "" + ] +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.caravan_core-upw.json b/scripts/be_checks/tech/sky130B/lvs_config.caravan_core-upw.json new file mode 100644 index 00000000..1e1a2a57 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.caravan_core-upw.json @@ -0,0 +1,47 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "caravan_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "*user_analog_project_wrapper", + "*sky130_fd_sc_hd__macro_sparecell" + ], + "LVS_FLATTEN": [ + "caravan_signal_routing", + "empty_macro_1" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping_alt.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/$TOP_SOURCE.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.caravan_core.json b/scripts/be_checks/tech/sky130B/lvs_config.caravan_core.json new file mode 100644 index 00000000..5f4261c1 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.caravan_core.json @@ -0,0 +1,47 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json", + "$UPRJ_ROOT/lvs/user_analog_project_wrapper/lvs_config.json" + ], + "TOP_SOURCE": "caravan_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "caravan_signal_routing", + "empty_macro_1" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping_alt.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/verilog/gl/$TOP_SOURCE.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.caravel-upw.json b/scripts/be_checks/tech/sky130B/lvs_config.caravel-upw.json new file mode 100644 index 00000000..3508401b --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.caravel-upw.json @@ -0,0 +1,38 @@ +{ + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.chip_io.json", + "$LVS_ROOT/tech/$PDK/lvs_config.caravel_core.json" + ], + "TOP_SOURCE": "caravel", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "*user_project_wrapper" + ], + "EXTRACT_CREATE_SUBCUT": [ + "*user_project_wrapper" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "*caravel_core" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "" + ], + "LVS_VERILOG_FILES": [ + "$CARAVEL_ROOT/verilog/gl/caravel_logo.v", + "$CARAVEL_ROOT/verilog/gl/caravel_motto.v", + "$CARAVEL_ROOT/verilog/gl/copyright_block.v", + "$CARAVEL_ROOT/verilog/gl/open_source.v", + "$CARAVEL_ROOT/verilog/gl/user_id_textblock.v", + "$CARAVEL_ROOT/verilog/gl/caravel.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.caravel.json b/scripts/be_checks/tech/sky130B/lvs_config.caravel.json new file mode 100644 index 00000000..f03d816d --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.caravel.json @@ -0,0 +1,38 @@ +{ + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.chip_io.json", + "$LVS_ROOT/tech/$PDK/lvs_config.caravel_core.json" + ], + "TOP_SOURCE": "caravel", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "EXTRACT_CREATE_SUBCUT": [ + "*user_project_wrapper" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "" + ], + "LVS_VERILOG_FILES": [ + "$CARAVEL_ROOT/verilog/gl/caravel_logo.v", + "$CARAVEL_ROOT/verilog/gl/caravel_motto.v", + "$CARAVEL_ROOT/verilog/gl/copyright_block.v", + "$CARAVEL_ROOT/verilog/gl/open_source.v", + "$CARAVEL_ROOT/verilog/gl/user_id_textblock.v", + "$CARAVEL_ROOT/verilog/gl/caravel.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.caravel_core-upw.json b/scripts/be_checks/tech/sky130B/lvs_config.caravel_core-upw.json new file mode 100644 index 00000000..a039a430 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.caravel_core-upw.json @@ -0,0 +1,46 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "caravel_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "*user_project_wrapper", + "*sky130_fd_sc_hd__macro_sparecell" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/outputs/verilog/gl/$TOP_SOURCE.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.caravel_core.json b/scripts/be_checks/tech/sky130B/lvs_config.caravel_core.json new file mode 100644 index 00000000..f079e873 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.caravel_core.json @@ -0,0 +1,46 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json", + "$UPRJ_ROOT/lvs/user_project_wrapper/lvs_config.json" + ], + "TOP_SOURCE": "caravel_core", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$CARAVEL_ROOT/xschem/simple_por.spice", + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$MCW_ROOT/verilog/gl/RAM128.v", + "$CARAVEL_ROOT/verilog/gl/caravel_clocking.v", + "$CARAVEL_ROOT/verilog/gl/empty_macro.v", + "$CARAVEL_ROOT/verilog/gl/gpio_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/housekeeping.v", + "$CARAVEL_ROOT/verilog/gl/manual_power_connections.v", + "$CARAVEL_ROOT/verilog/gl/mgmt_protect_hv.v", + "$CARAVEL_ROOT/verilog/gl/mprj2_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/mprj_io_buffer.v", + "$CARAVEL_ROOT/verilog/gl/mprj_logic_high.v", + "$CARAVEL_ROOT/verilog/gl/spare_logic_block.v", + "$CARAVEL_ROOT/verilog/gl/xres_buf.v", + "$TAPEOUT_ROOT/verilog/gl/gpio_defaults_block_*.v", + "$TAPEOUT_ROOT/verilog/gl/user_id_programming.v", + "$TAPEOUT_ROOT/verilog/gl/caravel_core.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.chip_io.json b/scripts/be_checks/tech/sky130B/lvs_config.chip_io.json new file mode 100644 index 00000000..6d37b9d5 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.chip_io.json @@ -0,0 +1,64 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "chip_io", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "*sky130_fd_pr__*example*", + "*sky130_ef_io__com*", + "*sky130_ef_io__connect*", + "*sky130_ef_io__corner*", + "*sky130_ef_io__*_overlay", + "*sky130_fd_io__amux*", + "*sky130_fd_io__amx_inv1", + "*sky130_fd_io__com*", + "*sky130_fd_io__corner*", + "*sky130_fd_io__esd*", + "*sky130_fd_io__feas*", + "*sky130_fd_io__gpio*", + "*sky130_fd_io__gnd2gnd*", + "*sky130_fd_io__hvc*", + "*sky130_fd_io__hvsbt*", + "*sky130_fd_io__inv*", + "*sky130_fd_io__nand*", + "*sky130_fd_io__nfet_con*", + "*sky130_fd_io__nor*", + "*sky130_fd_io__overlay*", + "*sky130_fd_io__pad_esd", + "*sky130_fd_io__pfet_con*", + "*sky130_fd_io__res250*", + "*sky130_fd_io__res75*", + "*sky130_fd_io__signal*", + "*sky130_fd_io__sio*", + "*sky130_fd_io__simple_pad_*", + "*sky130_fd_io__tap*", + "*sky130_fd_io__tk_tie*", + "*sky130_fd_io__top_gpio*", + "*sky130_fd_io__top_ground*", + "*sky130_fd_io__top_power*", + "*sky130_fd_io__xor*", + "*sky130_fd_io__xres*" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$LVS_ROOT/spice/sky130_*_io.1_0_410+.spice" + ], + "LVS_VERILOG_FILES": [ + "$CARAVEL_ROOT/verilog/gl/constant_block.v", + "$CARAVEL_ROOT/verilog/gl/chip_io.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.chip_io_alt.json b/scripts/be_checks/tech/sky130B/lvs_config.chip_io_alt.json new file mode 100644 index 00000000..60f589c5 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.chip_io_alt.json @@ -0,0 +1,65 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "chip_io", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "*sky130_fd_pr__*example*", + "*sky130_ef_io__com*", + "*sky130_ef_io__connect*", + "*sky130_ef_io__corner*", + "*sky130_ef_io__gpiov2_pad", + "*sky130_ef_io__*_overlay", + "*sky130_fd_io__amux*", + "*sky130_fd_io__amx_inv1", + "*sky130_fd_io__com*", + "*sky130_fd_io__corner*", + "*sky130_fd_io__esd*", + "*sky130_fd_io__feas*", + "*sky130_fd_io__gpio*", + "*sky130_fd_io__gnd2gnd*", + "*sky130_fd_io__hvc*", + "*sky130_fd_io__hvsbt*", + "*sky130_fd_io__inv*", + "*sky130_fd_io__nand*", + "*sky130_fd_io__nfet_con*", + "*sky130_fd_io__nor*", + "*sky130_fd_io__overlay*", + "*sky130_fd_io__pad_esd", + "*sky130_fd_io__pfet_con*", + "*sky130_fd_io__res250*", + "*sky130_fd_io__res75*", + "*sky130_fd_io__signal*", + "*sky130_fd_io__sio*", + "*sky130_fd_io__simple_pad_*", + "*sky130_fd_io__tap*", + "*sky130_fd_io__tk_tie*", + "*sky130_fd_io__top_gpio*", + "*sky130_fd_io__top_ground*", + "*sky130_fd_io__top_power*", + "*sky130_fd_io__xor*", + "*sky130_fd_io__xres*" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/*.spice" + ], + "LVS_VERILOG_FILES": [ + "$CARAVEL_ROOT/verilog/gl/constant_block.v", + "$CARAVEL_ROOT/verilog/gl/chip_io.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/caravel.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.sram.json b/scripts/be_checks/tech/sky130B/lvs_config.sram.json new file mode 100644 index 00000000..20e9a586 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.sram.json @@ -0,0 +1,24 @@ +{ + "EXTRACT_FLATGLOB": [ + "*_nmos_m*", + "*_pmos_m*" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$LVS_ROOT/spice/$SRAM_MACRO.470.spice" + ], + "LVS_VERILOG_FILES": [ + "" + ] +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.user_analog_project_wrapper.json b/scripts/be_checks/tech/sky130B/lvs_config.user_analog_project_wrapper.json new file mode 100644 index 00000000..2d79501c --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.user_analog_project_wrapper.json @@ -0,0 +1,30 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "user_analog_project_wrapper", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "$UPRJ_ROOT/xschem/user_analog_project_wrapper.spice" + ], + "LVS_VERILOG_FILES": [ + "" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/user_analog_project_wrapper.gds" +} diff --git a/scripts/be_checks/tech/sky130B/lvs_config.user_project_wrapper.json b/scripts/be_checks/tech/sky130B/lvs_config.user_project_wrapper.json new file mode 100644 index 00000000..f1d2e7fa --- /dev/null +++ b/scripts/be_checks/tech/sky130B/lvs_config.user_project_wrapper.json @@ -0,0 +1,31 @@ +{ + "STD_CELL_LIBRARY": "sky130_fd_sc_hd", + "INCLUDE_CONFIGS": [ + "$LVS_ROOT/tech/$PDK/lvs_config.base.json" + ], + "TOP_SOURCE": "user_project_wrapper", + "TOP_LAYOUT": "$TOP_SOURCE", + "EXTRACT_FLATGLOB": [ + "" + ], + "EXTRACT_ABSTRACT": [ + "" + ], + "LVS_FLATTEN": [ + "" + ], + "LVS_NOFLATTEN": [ + "" + ], + "LVS_IGNORE": [ + "" + ], + "LVS_SPICE_FILES": [ + "" + ], + "LVS_VERILOG_FILES": [ + "$UPRJ_ROOT/verilog/gl/user_proj_example.v", + "$UPRJ_ROOT/verilog/gl/user_project_wrapper.v" + ], + "LAYOUT_FILE": "$UPRJ_ROOT/gds/user_project_wrapper.gds" +} diff --git a/scripts/be_checks/tech/sky130B/remove_well.sed b/scripts/be_checks/tech/sky130B/remove_well.sed new file mode 100644 index 00000000..924bfa3f --- /dev/null +++ b/scripts/be_checks/tech/sky130B/remove_well.sed @@ -0,0 +1,21 @@ +s/[^ ]* \(sky130_fd_pr__.fet\)/\1/ +s/[^ ]* \(sky130_fd_pr__special_.fet\)/\1/ +s/[^ ]* \(sky130_fd_pr__esd_.fet\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_high_po\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_xhigh_po\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_generic_nd\)/\1/ +s/[^ ]* \(sky130_fd_pr__res_generic_pd\)/\1/ +s/[^ ]* \(sky130_fd_pr__cap_var\)/\1/ +s/[^ ]* \(sky130_fd_bs_flash__special_sonosfet_star\)/\1/ +s/[^ ]* \(ppolyf_u_1k_6p0\)/\1/ +s/[^ ]* \(ppolyf_u\)/\1/ +s/[^ ]* \(.fet_06v0\)/\1/ +/^D.* sky130_fd_pr__diode_pd2nw_/d +/^D.* sky130_fd_pr__diode_pw2nd_/d +/^D.* sky130_fd_pr__model__parasitic__diode_ps2dn/d +/^D.* diode_pd2nw_06v0/d +/^D.* diode_nd2ps_06v0/d +/^D.* np_6p0/d +/^D.* pn_6p0/d +/^R.* sky130_fd_pr__res_iso_pw/d +/^X.* sky130_fd_pr__pnp_05v5/d diff --git a/scripts/be_checks/tech/sky130B/sky130B.tech b/scripts/be_checks/tech/sky130B/sky130B.tech new file mode 100644 index 00000000..367c733c --- /dev/null +++ b/scripts/be_checks/tech/sky130B/sky130B.tech @@ -0,0 +1,6326 @@ +#------------------------------------------------------------------------ +# Copyright (c) 2020 R. Timothy Edwards +# Revisions: See below +# +# This file is an Open Source foundry process describing +# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication +# process. The file may be distributed under the terms +# of the Apache 2.0 license agreement. +# +#------------------------------------------------------------------------ +tech + format 35 + sky130B +end + +version + version 1.0.470-0-g6d4d117 + description "SkyWater SKY130: Open Source rules and DRC" + requires magic-8.3.411 +end + +#------------------------------------------------------------------------ +# Status 7/10/20: Rev 1 (alpha): +# First public release +# Status 8/14/20: Rev 2 (alpha): +# Started updating with new device/model naming convention +# Status 1/3/21: Taking out of beta and declaring an official release. +# Status 3/17/22: Added fringeshieldhalo to improve parasitic capacitance +# calculations. +# Status 5/21/22: Added sidewall edge (spacing) enlargement. +#------------------------------------------------------------------------ + +#------------------------------------------------------------------------ +# Supported device types +#------------------------------------------------------------------------ +# device name magic ID layer description +#------------------------------------------------------------------------ +# sky130_fd_pr__nfet_01v8 nfet standard nFET +# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell** +# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell +# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell +# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET +# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET +# sky130_fd_pr__pfet_01v8 pfet standard pFET +# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell** +# sky130_fd_pr__special_pfet_latch ppu special pFET in SRAM cell +# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET +# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET +# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET +# sky130_fd_pr__nfet_03v3_nvt nnfet native nFET +# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET +# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET +# sky130_fd_pr__nfet_05v0_nvt mvnnfet thickox native nFET +# sky130_fd_pr__nfet_g5v0d16v0 mvnfet extended-drain nFET*** +# sky130_fd_pr__pfet_g5v0d16v0 mvpfet extended-drain pFET*** +# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode +# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode +# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff +# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode +# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode +# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode +# sky130_fd_pr__npn_05v5 pbase NPN in deep nwell +# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN +# sky130_fd_pr__pnp_05v5 nbase PNP +# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate +# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate +# sky130_fd_pr__res_generic_nd rdn n+ diff resistor +# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor +# sky130_fd_pr__res_generic_pd rdp p+ diff resistor +# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor +# sky130_fd_pr__res_generic_l1 rli local interconnect resistor +# sky130_fd_pr__res_generic_po npres n+ poly resistor +# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq) +# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq) +# sky130_fd_pr__cap_var_lvt varactor low Vt varactor +# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor +# sky130_fd_pr__cap_var mvvaractor thickox varactor +# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell) +# sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd ESD thickox nFET +# sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd ESD thickox pFET +# sky130_fd_pr__photodiode photo Photodiode +# +# (*) Note that ppres may extract into some generic type called +# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are +# allowed, and these are created from fixed layouts like the types below. +# +# (**) nFET and pFET in standard cells are the same as devices +# outside of the standard cell except for the DRC rule for +# FET to diffusion contact spacing (which is 0.05um, not 0.055um) +# +# (***) The extended-drain devices have the same identifying +# FET type as the thick oxide devices, but the drain side of the +# device is represented by layer extdrain extending to nsd or psd. +# +#------------------------------------------------------------- +# The following devices are not extracted but are represented +# only by script-generated subcells in the PDK. +#------------------------------------------------------------- +# sky130_fd_pr__esd_nfet_01v8 ESD nFET +# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET +# sky130_fd_pr__special_nfet_pass_flash flash nFET device +# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode +# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode +# sky130_fd_pr__cap_vpp_* Vpp cap +# sky130_fd_pr__ind_* inductor +# sky130_fd_pr__fuse_m4 metal fuse device +#-------------------------------------------------------------- + +#----------------------------------------------------- +# Tile planes +#----------------------------------------------------- + +planes + dwell,dw + well,w + active,a + locali,li1,li + metal1,m1 + metal2,m2 + metal3,m3 + cap1,c1 + metal4,m4 + cap2,c2 + metal5,m5 + metali,mi + block,b + comment,c +end + +#----------------------------------------------------- +# Tile types +#----------------------------------------------------- + +types +# Deep nwell + dwell dnwell,dnw + dwell isosubstrate,isosub + dwell photodiode,photo + +# Wells + well nwell,nw + well pwell,pw + well rpw,rpwell + -well obswell + well pbase,npn + well nbase,pnp + +# Transistors + active nmos,ntransistor,nfet + -active scnmos,scntransistor,scnfet + -active npd,npdfet,sramnfet + -active npass,npassfet,srampassfet + active pmos,ptransistor,pfet + -active scpmos,scptransistor,scpfet + -active scpmoshvt,scpfethvt + -active ppu,ppufet,srampfet + active nnmos,nntransistor,nnfet + active mvnmos,mvntransistor,mvnfet + active mvpmos,mvptransistor,mvpfet + active mvnnmos,mvnntransistor,mvnnfet + -active mvnmosesd,mvntransistoresd,mvnfetesd + -active mvpmosesd,mvptransistoresd,mvpfetesd + active varactor,varact,var + active mvvaractor,mvvaract,mvvar + + active pmoslvt,pfetlvt + active pmosmvt,pfetmvt + active pmoshvt,pfethvt + active nmoslvt,nfetlvt + active varactorhvt,varacthvt,varhvt + -active nsonos,sonos + -active sramnvar,corenvar,corenvaractor + -active srampvar,corepvar,corepvaractor + +# Diffusions + -active fomfill + active ndiff,ndiffusion,ndif + active pdiff,pdiffusion,pdif + active mvndiff,mvndiffusion,mvndif + active mvpdiff,mvpdiffusion,mvpdif + active ndiffc,ndcontact,ndc + active pdiffc,pdcontact,pdc + active mvndiffc,mvndcontact,mvndc + active mvpdiffc,mvpdcontact,mvpdc + active psubdiff,psubstratepdiff,ppdiff,ppd,psd,ptap + active nsubdiff,nsubstratendiff,nndiff,nnd,nsd,ntap + active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd,mvptap + active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd,mvntap + active psubdiffcont,psubstratepcontact,psc,ptapc + active nsubdiffcont,nsubstratencontact,nsc,ntapc + active mvpsubdiffcont,mvpsubstratepcontact,mvpsc,mvptapc + active mvnsubdiffcont,mvnsubstratencontact,mvnsc,mvntapc + active extdrain,ed + -active obsactive + -active mvobsactive + +# Poly + active poly,p,polysilicon + active polycont,pc,pcontact,polycut,polyc + active xpolycontact,xpolyc,xpc + -active polyfill + +# Resistors + active npolyres,npres,mrp1 + active ppolyres,ppres,xhrpoly + active xpolyres,xpres,xres,uhrpoly + active ndiffres,rnd,rdn,rndiff + active pdiffres,rpd,rdp,rpdiff + active mvndiffres,mvrnd,mvrdn,mvrndiff + active mvpdiffres,mvrpd,mvrdp,mvrpdiff + active rmp + +# Diodes + active pdiode,pdi + active ndiode,ndi + active nndiode,nndi + active pdiodec,pdic + active ndiodec,ndic + active nndiodec,nndic + active mvpdiode,mvpdi + active mvndiode,mvndi + active mvpdiodec,mvpdic + active mvndiodec,mvndic + active pdiodelvt,pdilvt + active pdiodehvt,pdihvt + active ndiodelvt,ndilvt + active pdiodelvtc,pdilvtc + active pdiodehvtc,pdihvtc + active ndiodelvtc,ndilvtc + +# Local Interconnect + locali locali,li1,li + -locali corelocali,coreli1,coreli + locali rlocali,rli1,rli + locali viali,vial,mcon,m1c,v0 + -locali obsli1,obsli + -locali obsli1c,obsmcon + -locali lifill + +# Metal 1 + metal1 metal1,m1,met1 + metal1 rmetal1,rm1,rmet1 + metal1 via1,m2contact,m2cut,m2c,via,v,v1 + -metal1 obsm1 + -metal1 m1fill + + metal2 reram,rr + +# Metal 2 + metal2 metal2,m2,met2 + metal2 rmetal2,rm2,rmet2 + metal2 via2,m3contact,m3cut,m3c,v2 + -metal2 obsm2 + -metal2 m2fill + +# Metal 3 + metal3 metal3,m3,met3 + metal3 rmetal3,rm3,rmet3 + -metal3 obsm3 + metal3 via3,v3 + -metal3 m3fill + + cap1 mimcap,mim,capm + cap1 mimcapcontact,mimcapc,mimcc,capmc + +# Metal 4 + metal4 metal4,m4,met4 + metal4 rmetal4,rm4,rmet4 + -metal4 obsm4 + metal4 via4,v4 + -metal4 m4fill + + cap2 mimcap2,mim2,capm2 + cap2 mimcap2contact,mimcap2c,mim2cc,capm2c + +# Metal 5 + metal5 metal5,m5,met5 + metal5 rm5,rmetal5,rmet5 + -metal5 obsm5 + -metal5 m5fill + + metal5 mrdlcontact,mrdlc,pi1 + metali metalrdl,mrdl,metrdl,rdl + -metali obsmrdl + metali pi2 + block ubm + +# Miscellaneous + -block glass + -block fillblock,fillblock4 + comment comment + -comment obscomment + +end + +#----------------------------------------------------- +# Magic contact types +#----------------------------------------------------- + +contact + pc poly locali + ndc ndiff locali + pdc pdiff locali + nsc nsd locali + psc psd locali + ndic ndiode locali + ndilvtc ndiodelvt locali + nndic nndiode locali + pdic pdiode locali + pdilvtc pdiodelvt locali + pdihvtc pdiodehvt locali + xpc xpc locali + + mvndc mvndiff locali + mvpdc mvpdiff locali + mvnsc mvnsd locali + mvpsc mvpsd locali + mvndic mvndiode locali + mvpdic mvpdiode locali + + mcon locali metal1 + obsmcon obsli metal1 + + via1 metal1 metal2 + via2 metal2 metal3 + via3 metal3 metal4 + via4 metal4 metal5 + stackable + + # MiM cap contacts are not stackable! + mimcc mimcap metal4 + mim2cc mimcap2 metal5 + + mrdlc metal5 mrdl + pi2 mrdl ubm +end + +#----------------------------------------------------- +# Layer aliases +#----------------------------------------------------- + +aliases + + allwellplane nwell + allnwell nwell,obswell,pnp + + allnfets nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,nsonos + allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt + allfets allnfets,allpfets,varactor,mvvaractor,varhvt,corenvar,corepvar + allfetsstd nfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nfetlvt,pfet,mvpfet,mvpfetesd,pfethvt,pfetlvt,pfetmvt + allfetsspecial scnfet,scpfet,scpfethvt + allfetscore npass,npd,nsonos,ppu,corenvar,corepvar + allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnfetesd,mvnnfet,nnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,mvpfetesd,pfethvt,pfetmvt,varactor,mvvaractor,varhvt,corenvar + + allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt + allnactive allnactivenonfet,allnfets + allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets + allnactivetap *nsd,*mvnsd,var,varhvt,mvvar,corenvar + + allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt + allpactive allpactivenonfet,allpfets + allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets + allpactivetap *psd,*mvpsd,corepvar + + allactivenonfet allnactivenonfet,allpactivenonfet + allactive allactivenonfet,allfets + + allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres + + allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos + allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt + alldifflv allndifflv,allpdifflv + allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt + allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt + alldifflvnonfet allndifflvnonfet,allpdifflvnonfet + + allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet + allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd + alldiffmv allndiffmv,allpdiffmv + allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnfetesd,mvnnfet,nnfet + allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet,mvpfetesd + alldiffmvnontap allndiffmvnontap,allpdiffmvnontap + allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres + allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres + alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet + + alldiffnonfet alldifflvnonfet,alldiffmvnonfet + alldiff alldifflv,alldiffmv,fomfill + + allpolyres mrp1,xhrpoly,uhrpoly,rmp + allpolynonfet *poly,allpolyres,xpc + allpolynonres *poly,allfets,xpc + + allpoly allpolynonfet,allfets + allpolynoncap *poly,xpc,allfets,allpolyres + + allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc + allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc + allndiffcontmv mvndc,mvnsc,mvndic + allpdiffcontmv mvpdc,mvpsc,mvpdic + allndiffcont allndiffcontlv,allndiffcontmv + allpdiffcont allpdiffcontlv,allpdiffcontmv + alldiffcontlv allndiffcontlv,allpdiffcontlv + alldiffcontmv allndiffcontmv,allpdiffcontmv + alldiffcont alldiffcontlv,alldiffcontmv + + allcont alldiffcont,pc + + allres allpolyres,allactiveres + + allli *locali,coreli,rli + allm1 *m1,rm1 + allm2 *m2,rm2,reram + allm3 *m3,rm3 + allm4 *m4,rm4 + allm5 *m5,rm5 + + psub pwell + + obstypes obswell,mvobsactive,obsactive,obsli,obsmcon,obsm1,obsm2,obsm3,obsm4,obsm5,obsmrdl,obscomment + blocktypes fillblock,fillblock4 + +end + +#----------------------------------------------------- +# Layer drawing styles +#----------------------------------------------------- + +styles + styletype mos + dnwell cwell + isosub subcircuit + nwell nwell + pwell pwell + rpwell pwell ptransistor_stripes + photo nwell nwell_field_implant + ndiff ndiffusion + fomfill ndiffusion + pdiff pdiffusion + nsd ndiff_in_nwell + psd pdiff_in_pwell + nfet ntransistor ntransistor_stripes + scnfet ntransistor ntransistor_stripes + npass ntransistor ntransistor_stripes + npd ntransistor ntransistor_stripes + pfet ptransistor ptransistor_stripes + scpfet ptransistor ptransistor_stripes + scpfethvt ptransistor ptransistor_stripes implant2 + ppu ptransistor ptransistor_stripes + var polysilicon ndiff_in_nwell + ndc ndiffusion metal1 contact_X'es + pdc pdiffusion metal1 contact_X'es + nsc ndiff_in_nwell metal1 contact_X'es + psc pdiff_in_pwell metal1 contact_X'es + corenvar polysilicon ndiff_in_nwell + corepvar polysilicon pdiff_in_pwell + + pnp nwell ntransistor_stripes + npn pwell ptransistor_stripes + + pfetlvt ptransistor ptransistor_stripes implant1 + pfetmvt ptransistor ptransistor_stripes implant3 + pfethvt ptransistor ptransistor_stripes implant2 + nfetlvt ntransistor ntransistor_stripes implant1 + nsonos ntransistor implant3 + varhvt polysilicon ndiff_in_nwell implant2 + nnfet ntransistor ndiff_in_nwell + + mvndiff ndiffusion hvndiff_mask + mvpdiff pdiffusion hvpdiff_mask + mvnsd ndiff_in_nwell hvndiff_mask + mvpsd pdiff_in_pwell hvpdiff_mask + mvnfet ntransistor ntransistor_stripes hvndiff_mask + mvnfetesd ntransistor ntransistor_stripes hvndiff_mask + mvnnfet ntransistor ndiff_in_nwell hvndiff_mask + mvpfet ptransistor ptransistor_stripes + mvpfetesd ptransistor ptransistor_stripes + mvvar polysilicon ndiff_in_nwell hvndiff_mask + mvndc ndiffusion metal1 contact_X'es hvndiff_mask + mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask + mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask + mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask + + extdrain nselect pselect + + poly polysilicon + polyfill polysilicon + pc polysilicon metal1 contact_X'es + npolyres polysilicon silicide_block nselect2 + ppolyres polysilicon silicide_block pselect2 + xpc polysilicon pselect2 metal1 contact_X'es + rmp polysilicon poly_resist_stripes + + pdiode pdiffusion pselect2 + ndiode ndiffusion nselect2 + pdiodec pdiffusion pselect2 metal1 contact_X'es + ndiodec ndiffusion nselect2 metal1 contact_X'es + + nndiode ndiffusion nselect2 implant3 + ndiodelvt ndiffusion nselect2 implant1 + pdiodelvt pdiffusion pselect2 implant1 + pdiodehvt pdiffusion pselect2 implant2 + pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es + pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es + ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es + + mvpdiode pdiffusion pselect2 hvpdiff_mask + mvndiode ndiffusion nselect2 hvndiff_mask + mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask + mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask + nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask + + locali metal1 + lifill metal1 + coreli metal1 + rli metal1 poly_resist_stripes + mcon metal1 metal2 via1arrow + obsli metal1 + obsmcon metal1 metal2 via1arrow + + metal1 metal2 + m1fill metal2 + rm1 metal2 poly_resist_stripes + obsm1 metal2 + m2c metal2 metal3 via2arrow + + reram metal2 metal3 via2 contact_X'es + + metal2 metal3 + m2fill metal3 + rm2 metal3 poly_resist_stripes + obsm2 metal3 + m3c metal3 metal4 via3alt + metal3 metal4 + m3fill metal4 + rm3 metal4 poly_resist_stripes + obsm3 metal4 + mimcap metal3 mems + mimcc metal3 contact_X'es mems + mimcap2 metal4 mems + mim2cc metal4 contact_X'es mems + via3 metal4 metal5 via4 + metal4 metal5 + m4fill metal5 + rm4 metal5 poly_resist_stripes + obsm4 metal5 + via4 metal5 metal6 via5 + metal5 metal6 + m5fill metal6 + rm5 metal6 poly_resist_stripes + obsm5 metal6 + mrdlc metal6 metal7 via6 + metalrdl metal7 + obsmrdl metal7 + ubm metal8 + pi2 metal7 metal8 via7 + + glass overglass + mrp1 poly_resist poly_resist_stripes + xhrpoly poly_resist silicide_block + uhrpoly poly_resist + ndiffres ndiffusion ndop_stripes + pdiffres pdiffusion pdop_stripes + mvndiffres ndiffusion hvndiff_mask ndop_stripes + mvpdiffres pdiffusion hvpdiff_mask pdop_stripes + comment comment + error_p error_waffle + error_s error_waffle + error_ps error_waffle + fillblock cwell + fillblock4 cwell + + obswell cwell + obsactive implant4 + + magnet substrate_field_implant + rotate via3alt + fence via5 +end + +#----------------------------------------------------- +# Special paint/erase rules +#----------------------------------------------------- + +compose + compose nfet poly ndiff + compose pfet poly pdiff + compose var poly nsd + + decompose npass poly ndiff + decompose npd poly ndiff + decompose scnfet poly ndiff + decompose nfetlvt poly ndiff + decompose nsonos poly ndiff + + decompose ppu poly pdiff + decompose scpfet poly pdiff + decompose scpfethvt poly pdiff + decompose pfethvt poly pdiff + decompose pfetlvt poly pdiff + decompose pfetmvt poly pdiff + decompose corenvar poly nsd + decompose corepvar poly psd + decompose varhvt poly nsd + + compose mvnfet poly mvndiff + compose mvpfet poly mvpdiff + compose mvvar poly mvnsd + + decompose nnfet poly mvndiff + decompose mvnfetesd poly mvndiff + decompose mvnnfet poly mvndiff + decompose mvpfetesd poly mvpdiff + + paint obsmcon locali via1 + paint obsmcon obsm1 obsli,obsm1 + + paint ndc nwell pdc + paint nfet nwell pfet + paint scnfet nwell scpfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint npd nwell ppu + + paint pdc pwell ndc + paint pfet pwell nfet + paint scpfet pwell scnfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint ppu pwell npd + + paint pdc coreli pdc + paint ndc coreli ndc + paint pc coreli pc + paint nsc coreli nsc + paint psc coreli psc + paint viali coreli viali + paint mvpdc coreli mvpdc + paint mvndc coreli mvndc + paint mvnsc coreli mvnsc + paint mvpsc coreli mvpsc + + paint coreli pdc pdc + paint coreli ndc ndc + paint coreli pc pc + paint coreli nsc nsc + paint coreli psc psc + paint coreli viali viali + paint coreli mvpdc mvpdc + paint coreli mvndc mvndc + paint coreli mvnsc mvnsc + paint coreli mvpsc mvpsc + + paint reram metal2 reram + + paint m4 obsm4 m4 + paint m5 obsm5 m5 +end + +#----------------------------------------------------- +# Electrical connectivity +#----------------------------------------------------- + +connect + *nwell,*nsd,*mvnsd,dnwell,pnp,photo *nwell,*nsd,*mvnsd,dnwell,pnp,photo + pwell,*psd,*mvpsd,npn,isosub pwell,*psd,*mvpsd,npn,isosub + *mvnsd ed + *mvpsd ed + *li,coreli,lifill *li,coreli,lifill + *m1,m1fill,obsmcon *m1,m1fill,obsmcon + *m2,m2fill,reram *m2,m2fill,reram + *m3,m3fill *m3,m3fill + *m4,m4fill *m4,m4fill + *m5,m5fill *m5,m5fill + *mimcap *mimcap + *mimcap2 *mimcap2 + allnactivenonfet allnactivenonfet + allpactivenonfet allpactivenonfet + *poly,xpc,allfets,polyfill *poly,xpc,allfets,polyfill + # RDL connects to m5 through glass cut + *mrdl *mrdl + glass metrdl +end + +#----------------------------------------------------- +# CIF/GDS output layer definitions +#----------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size + +cifoutput + +#---------------------------------------------------------------- +style gdsii +# NOTE: This section is used for actual GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + +#---------------------------------------------------------------- +# Create a temp layer from the cell bounding box for use in +# generating ID layers. Note that "boundary", unlike "bbox", +# requires the FIXED_BBOX property (abutment box) in the cell. +#---------------------------------------------------------------- + templayer CELLBOUND + boundary + +#---------------------------------------------------------------- +# BOUND +#---------------------------------------------------------------- + layer BOUND CELLBOUND + calma 235 4 + +#---------------------------------------------------------------- +# DNWELL +#---------------------------------------------------------------- + + layer DNWELL dnwell,npn,photo + calma 64 18 + + layer PWRES rpw + and dnwell + calma 64 13 + +#---------------------------------------------------------------- +# SUBCUT +#---------------------------------------------------------------- + + layer SUBCUT isosub + calma 81 53 + +#---------------------------------------------------------------- +# NWELL +#---------------------------------------------------------------- + + # Identify LDMOS drain areas + templayer ndrainarea + bloat-all ed *mvnsd + and-not ed + + templayer pdrainarea + bloat-all ed *mvpsd + and-not ed + + # Generate n-well under extended-drain nFET + templayer extnwell + bloat-or *mvnsd * 0 extdrain 1150 + and-not *mvnsd + or ndrainarea + grow 660 + + # Erase n-well under extended-drain pFET + templayer extpwell + bloat-or *mvpsd * 0 extdrain 590 + and-not *mvpsd + or pdrainarea + grow 860 + + layer NWELL allnwell + bloat-all rpw dnwell + and-not rpw,pwell + or extnwell + and-not extpwell + calma 64 20 + + layer WELLTXT + labels allnwell + calma 64 5 + + layer WELLPIN + labels allnwell port + calma 64 16 + +#---------------------------------------------------------------- +# SUB (text/port only) +#---------------------------------------------------------------- + + layer SUBTXT + labels pwell + calma 64 59 + + layer SUBPIN + labels pwell port + calma 122 16 + +#---------------------------------------------------------------- +# DIFF +#---------------------------------------------------------------- + + # Extended-drain FETs cut the diffusion under the gate + templayer ldbreak + bloat-or *mvnsd * 0 extdrain 1585 + bloat-or *mvpsd * 0 extdrain 1190 + + layer DIFF allnactivenontap,allpactivenontap,allactiveres + and-not ldbreak + calma 65 20 + + layer DIFFTXT + labels allnactivenontap,allpactivenontap + calma 65 6 + + layer DIFFPIN + labels allnactivenontap,allpactivenontap port + calma 65 16 + +#---------------------------------------------------------------- +# TAP +#---------------------------------------------------------------- + + layer TAP allnactivetap,allpactivetap + labels allnactivetap,allpactivetap port + calma 65 44 + + layer TAPTXT + labels allnactivetap,allpactivetap + calma 65 5 + +#---------------------------------------------------------------- +# FOM +#---------------------------------------------------------------- + + layer FOMFILL fomfill + labels fomfill + calma 23 28 + +#---------------------------------------------------------------- +# PSDM, NSDM (PPLUS, NPLUS implants) +#---------------------------------------------------------------- + + templayer basePSDM pdiffres,mvpdiffres + grow 15 + or xhrpoly,uhrpoly,xpc + grow 110 + bloat-or allpactivetap * 125 allnactivenontap 0 + bloat-or allpactivenontap * 125 allnactivetap 0 + + templayer baseNSDM ndiffres,mvndiffres + grow 125 + bloat-or allnactivetap * 125 allpactivenontap 0 + bloat-or allnactivenontap * 125 allpactivetap 0 + + templayer extendPSDM basePSDM + bridge 380 380 + and-not baseNSDM + + layer PSDM basePSDM,extendPSDM + grow 185 + shrink 185 + close 265000 + mask-hints PSDM + calma 94 20 + + templayer extendNSDM baseNSDM + bridge 380 380 + and-not basePSDM + + layer NSDM baseNSDM,extendNSDM + grow 185 + shrink 185 + close 265000 + mask-hints NSDM + calma 93 44 + +#---------------------------------------------------------------- +# EDID (Extended drain identifier) +#---------------------------------------------------------------- + + layer EDID + bloat-all extdrain *mvnsd,*mvpsd,mvnfet,mvpfet,*mvndiff,*mvpdiff + labels extdrain + calma 81 57 + +#---------------------------------------------------------------- +# LVID +#---------------------------------------------------------------- + + layer LVID nnfet + grow 100 + calma 81 60 + +#---------------------------------------------------------------- +# LVTN +#---------------------------------------------------------------- + + layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + mask-hints LVTN + calma 125 44 + +#---------------------------------------------------------------- +# HVTR +#---------------------------------------------------------------- + + layer HVTR pfetmvt + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + calma 18 20 + +#---------------------------------------------------------------- +# HVTP +#---------------------------------------------------------------- + + layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + mask-hints HVTP + calma 78 44 + +#---------------------------------------------------------------- +# SONOS +#---------------------------------------------------------------- + + layer SONOS nsonos + grow 100 + grow-min 410 + bridge 500 410 + grow 250 + shrink 250 + calma 80 20 + +#---------------------------------------------------------------- +# The coreli layer indicates a cell needing COREID. Also, +# devices npd, npass, and ppu indicate a COREID cell. NOTE: +# SONOS does not use COREID, counter to SkyWater rules. +#---------------------------------------------------------------- + + layer COREID + bloat-all coreli,ppu,npd,npass,corepvar,corenvar CELLBOUND + mask-hints COREID + calma 81 2 + +#---------------------------------------------------------------- +# STDCELL applies to all cells containing scnfet or scpfet. +#---------------------------------------------------------------- + + layer STDCELL scnfet + bloat-all scpfet,scpfethvt,scnfet CELLBOUND + mask-hints STDCELL + calma 81 4 + +#---------------------------------------------------------------- +# ESDID is a marker layer for ESD devices in the padframe I/O. +#---------------------------------------------------------------- + + layer ESDID + bloat-all mvnfetesd *mvndiff,*poly + bloat-all mvpfetesd *mvpdiff,*poly + grow 100 + mask-hints ESDID + calma 81 19 + +#---------------------------------------------------------------- +# NPNID and PNPID apply to bipolar transistors +#---------------------------------------------------------------- + + layer NPNID + bloat-all npn dnwell + mask-hints NPNID + calma 82 20 + + templayer pnparea pnp + grow 400 + + layer PNPID + bloat-all pnparea *psd + or pnparea + mask-hints PNPID + calma 82 44 + + layer PHOTO photo + calma 81 81 + +#---------------------------------------------------------------- +# RPM +#---------------------------------------------------------------- + + layer RPM + bloat-all xhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 86 20 + +#---------------------------------------------------------------- +# URPM (2kOhms/sq. poly implant) +#---------------------------------------------------------------- + + layer URPM + bloat-all uhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 79 20 + +#---------------------------------------------------------------- +# LDNTM (Tip implant for SONOS FETs) +#---------------------------------------------------------------- + + layer LDNTM + bloat-all nsonos *ndiff + grow 185 + grow 345 + shrink 345 + calma 11 44 + +#---------------------------------------------------------------- +# HVNTM (Tip implant for MV ndiff devices) +#---------------------------------------------------------------- + + templayer hvntm_block *mvpsd + grow 185 + + layer HVNTM + bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff + bloat-all mvvaractor *mvnsd + and-not hvntm_block + grow 185 + grow 345 + shrink 345 + and-not hvntm_block + mask-hints HVNTM + calma 125 20 + +#---------------------------------------------------------------- +# POLY +#---------------------------------------------------------------- + + layer POLY allpoly + calma 66 20 + + layer POLYTXT + labels allpoly + calma 66 5 + + layer POLYPIN + labels allpoly port + calma 66 16 + + layer POLYFILL polyfill + labels polyfill + calma 28 28 + +#---------------------------------------------------------------- +# HVI (includes rules NWELL 8-11 and DIFFTAP 14-26) +#---------------------------------------------------------------- + + templayer thkox_area ed + grow 475 + or alldiffmv,mvvar + grow 185 + bloat-all alldiffmv nwell + grow 345 + shrink 345 + + templayer large_ptap_mv thkox_area + shrink 420 + grow 420 + + templayer small_ptap_mv thkox_area + and-not large_ptap_mv + # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um) + grow-min 840 + + layer HVI thkox_area,small_ptap_mv + bridge 700 600 + grow 345 + shrink 345 + mask-hints HVI + calma 75 20 + +#---------------------------------------------------------------- +# CONT (LICON) +#---------------------------------------------------------------- + + layer CONT allcont + squares-grid 0 170 170 + calma 66 44 + + # Contact for pres is different than other LICON contacts + # See rules LICON 1b, 1c (width/length) and 2b (spacing) + templayer xpc_horiz xpc + shrink 1007 + grow 1007 + + layer CONT xpc + and-not xpc_horiz + # Force long edge vertical for contacts narrower than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 190 520 80 2000 350 + calma 66 44 + + layer CONT xpc + and xpc_horiz + # Force long edge vertical for contacts wider than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 2000 350 80 190 520 + calma 66 44 + +#---------------------------------------------------------------- +# NPC (Nitride poly cut) +# surrounds CONT (LICON) on poly only (i.e., pc) +#---------------------------------------------------------------- + + # Avoids a common case of NPC bridges too close to other LICON shapes. + templayer diffcutarea pdc,ndc,psc,nsc,mvpdc,mvndc,mvpsc,mvnsc + grow 90 + + layer NPC pc + squares-grid 0 170 170 + grow 100 + bridge 270 270 + and-not diffcutarea + bridge 270 270 + grow 130 + shrink 130 + mask-hints NPC + calma 95 20 + + # NPC is also generated on xhrpoly and uhrpoly resistors + + layer NPC xpc,xhrpoly,uhrpoly + # xpc surrounds precision_resistor by 0.095um + grow 95 + grow 130 + shrink 130 + calma 95 20 + +#---------------------------------------------------------------- +# Device markers +#---------------------------------------------------------------- + + layer DIFFRES rdn,mvrdn,rdp,mvrdp + calma 65 13 + + layer POLYRES mrp1 + calma 66 13 + + # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers + layer POLYSHORT rmp + calma 66 15 + + # POLYRES extends to edge of contact cut + layer POLYRES xhrpoly,uhrpoly + grow 80 + and xpc + or xhrpoly,uhrpoly + calma 66 13 + + layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt + # To be done: Expand to include anode, cathode, and guard ring + calma 81 23 + +#---------------------------------------------------------------- +# LI +#---------------------------------------------------------------- + layer LI allli + calma 67 20 + + layer LITXT + labels *locali,coreli + calma 67 5 + + layer LIPIN + labels *locali,coreli port + calma 67 16 + + layer LIRES rli + labels rli + calma 67 13 + + layer LIFILL lifill + labels lifill + calma 56 28 + +#---------------------------------------------------------------- +# MCON +#---------------------------------------------------------------- + layer MCON mcon + squares-grid 0 170 190 + calma 67 44 + +#---------------------------------------------------------------- +# MET1 +#---------------------------------------------------------------- + layer MET1 allm1 + calma 68 20 + + layer MET1TXT + labels allm1 + calma 68 5 + + layer MET1PIN + labels allm1 port + calma 68 16 + + layer MET1RES rm1 + labels rm1 + calma 68 13 + + layer MET1FILL m1fill + labels m1fill + calma 36 28 + +#---------------------------------------------------------------- +# VIA1 +#---------------------------------------------------------------- + layer VIA1 via1 + squares-grid 55 150 170 + calma 68 44 + + layer VIA1 reram + squares-grid 55 150 170 + calma 68 44 + + layer RERAM reram + calma 201 20 + +#---------------------------------------------------------------- +# MET2 +#---------------------------------------------------------------- + layer MET2 allm2 + calma 69 20 + + layer MET2TXT + labels allm2 + calma 69 5 + + layer MET2PIN + labels allm2 port + calma 69 16 + + layer MET2RES rm2 + labels rm2 + calma 69 13 + + layer MET2FILL m2fill + labels m2fill + calma 41 28 + +#---------------------------------------------------------------- +# VIA2 +#---------------------------------------------------------------- + layer VIA2 via2 + squares-grid 40 200 200 + calma 69 44 + +#---------------------------------------------------------------- +# MET3 +#---------------------------------------------------------------- + layer MET3 allm3 + calma 70 20 + + layer MET3TXT + labels allm3 + calma 70 5 + + layer MET3PIN + labels allm3 port + calma 70 16 + + layer MET3RES rm3 + labels rm3 + calma 70 13 + + layer MET3FILL m3fill + labels m3fill + calma 34 28 + +#---------------------------------------------------------------- +# VIA3 +#---------------------------------------------------------------- + layer VIA3 via3 + or mimcc + squares-grid 60 200 200 + calma 70 44 + +#---------------------------------------------------------------- +# MET4 +#---------------------------------------------------------------- + layer MET4 allm4 + calma 71 20 + + layer MET4TXT + labels allm4 + calma 71 5 + + layer MET4PIN + labels allm4 port + calma 71 16 + + layer MET4RES rm4 + labels rm4 + calma 71 13 + + layer MET4FILL m4fill + labels m4fill + calma 51 28 + +#---------------------------------------------------------------- +# VIA4 +#---------------------------------------------------------------- + layer VIA4 via4 + or mim2cc + squares-grid 190 800 800 + calma 71 44 + +#---------------------------------------------------------------- +# MET5 +#---------------------------------------------------------------- + layer MET5 allm5,m5fill + calma 72 20 + + layer MET5TXT + labels allm5 + calma 72 5 + + layer MET5PIN + labels allm5 port + calma 72 16 + + layer MET5RES rm5 + labels rm5 + calma 72 13 + + layer MET5FILL m5fill + labels m5fill + calma 59 28 + + +#---------------------------------------------------------------- +# RDL +#---------------------------------------------------------------- + layer RDL *metrdl + calma 74 20 + + layer RDLTXT + labels *metrdl + calma 74 5 + + layer RDLPIN + labels *metrdl port + calma 74 16 + + layer PI1 *metrdl + and m5,glass + # Test only---needs GDS layer number + + layer UBM *metrdl + shrink 50000 + grow 40000 + # Test only---needs GDS layer number + + layer PI2 *metrdl + shrink 50000 + grow 25000 + # Test only---needs GDS layer number + + +#---------------------------------------------------------------- +# GLASS +#---------------------------------------------------------------- + layer GLASS glass + calma 76 20 + +#---------------------------------------------------------------- +# CAPM +#---------------------------------------------------------------- + layer CAPM *mimcap + labels mimcap + calma 89 44 + + layer CAPM2 *mimcap2 + labels mimcap2 + calma 97 44 + +#---------------------------------------------------------------- +# Chip top level marker for DRC latchup rules to check 15um +# distance to taps (otherwise 6um is used) +#---------------------------------------------------------------- + + layer LOWTAPDENSITY + bbox top + # Clear 200um for pads + 50um for required high tap density + # in critical area. + shrink 250000 + calma 81 14 + +#---------------------------------------------------------------- +# FILLBLOCK +#---------------------------------------------------------------- + layer FILLOBSFOM obsactive + calma 22 24 + + layer FILLOBSM1 fillblock,fillblock4 + calma 62 24 + + layer FILLOBSM2 fillblock,fillblock4 + calma 105 52 + + layer FILLOBSM3 fillblock,fillblock4 + calma 107 24 + + layer FILLOBSM4 fillblock,fillblock4 + calma 112 4 + + layer FILLOBSM5 fillblock,fillblock4 + calma 117 4 + + render DNWELL cwell -0.1 0.1 + render NWELL nwell 0.0 0.2062 + render DIFF ndiffusion 0.2062 0.12 + render TAP pdiffusion 0.2062 0.12 + render POLY polysilicon 0.3262 0.18 + render CONT via 0.5062 0.43 + render LI metal1 0.9361 0.10 + render MCON via 1.0361 0.34 + render MET1 metal2 1.3761 0.36 + render VIA1 via 1.7361 0.27 + render MET2 metal3 2.0061 0.36 + render VIA2 via 2.3661 0.42 + render MET3 metal4 2.7861 0.845 + render VIA3 via 3.6311 0.39 + render MET4 metal5 4.0211 0.845 + render VIA4 via 4.8661 0.505 + render MET5 metal6 5.3711 1.26 + render CAPM metal8 2.4661 0.2 + render CAPM2 metal9 3.7311 0.2 + render RDL metal7 11.8834 4.0 + +#---------------------------------------------------------------- +style drc +#---------------------------------------------------------------- +# NOTE: This style is used for DRC only, not for GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + + # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside + templayer dnwell_shrink dnwell + shrink 1030 + + templayer nwell_missing dnwell + grow 400 + and-not dnwell_shrink + and-not nwell + + templayer pwell_in_dnwell dnwell + and-not nwell + + # SONOS nFET devices must be in deep nwell + templayer dnwell_missing nsonos + and-not dnwell + + # SONOS nFET devices must be in cell with abutment box + templayer abutment_box + boundary + + templayer bbox_missing nsonos + and-not abutment_box + + # Make sure nwell covers varactor poly + templayer var_poly_no_nwell + bloat-all varactor,mvvaractor *poly + grow 150 + and-not nwell + + # Define MiM cap bottom plate for spacing rule + templayer mim_bottom + bloat-all *mimcap *metal3 + + # Define MiM2 cap bottom plate for spacing rule + templayer mim2_bottom + bloat-all *mimcap2 *metal4 + + # Define areas where mim2cc is inside the boundary of mimcc + # by more than the contact surround + templayer mim2_contact_overlap + bloat-all *mimcap2 mimcc + shrink 60 + and-not *mimcap2 + + # Note that metal fill is performed by the foundry and so is not + # an option for a cifoutput style. + + # Check latchup rule (15um minimum from tap LICON center to any + # non-tap diffusion. Note that to count as a tap, the diffusion + # must be contacted to LI + + templayer ptap_reach psc,mvpsc + and-not dnwell + # grow total is 15um. grow in 0.84um increments to ensure that + # no nwell ring is crossed + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 635 + and-not nwell,dnwell + + templayer ptap_missing *ndiff,*mvndiff + and-not dnwell + and-not ptap_reach + + templayer ntap_reach nsc,mvnsc + # grow total is 15um. grow in 1.27um increments to ensure that + # no nwell ring is crossed. There is no difference between + # ntaps in and out of deep nwell. + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 1270 + and nwell,pnp + grow 945 + and nwell,pnp + + templayer ntap_missing *pdiff,*mvpdiff + and-not pwell_in_dnwell + and-not ntap_reach + + templayer dptap_reach psc,mvpsc + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 635 + and-not nwell + and dnwell + + templayer dptap_missing *ndiff,*mvndiff + and dnwell + and-not dptap_reach + + templayer pdiff_crosses_dnwell dnwell + grow 20 + and-not dnwell + and allpdifflv,allpdiffmv + + # MV nwell must be 2um from any other nwell + templayer mvnwell + bloat-all alldiffmv nwell + grow-min 840 + bridge 700 600 + + # Simple spacing checks to lvnwell must use CIF-DRC rule + # Note that HVI may *abut* lvnwell; this can only be handled + # with mask-hints layers. + + templayer drawn_hvi + mask-hints HVI + + templayer allmvdiffnowell *mvndiff,*mvpsd + and-not drawn_hvi + + templayer nwell_or_hvi nwell,drawn_hvi + + templayer lvnwell nwell + and-not mvnwell + + # Check for low-voltage diffusion in high-voltage well + templayer lvdiff_in_mvnwell *pdiff,*pdiode,pdiffres,*nsd + or pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt + and mvnwell + + templayer nwell_with_tap + bloat-all nsc,mvnsc nwell,pnp + + templayer nwell_missing_tap nwell,pnp + and-not nwell_with_tap + + templayer tap_with_licon + bloat-all allpactivetap psd,mvpsd + bloat-all allnactivetap nsd,mvnsd + + templayer tap_missing_licon allnactivetap,allpactivetap + and-not tap_with_licon + + # Make sure varactor nwell contains no P diffusion + templayer pdiff_in_varactor_well + bloat-all varactor,mvvaractor nwell + and allpactive + + # HVNTM spacing requires recreating HVNTM + templayer hvntm_block *mvpsd + grow 185 + + templayer hvntm_generate + bloat-all mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,mvrdn,*nndiode *mvndiff + bloat-all mvvaractor *mvnsd + and-not hvntm_block + grow 185 + grow 345 + shrink 345 + and-not hvntm_block + + # RPM spacing checks require recreating RPM + templayer rpm_generate + bloat-all xhrpoly,uhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + + # Check distance RPM to NSDM + templayer rpm_nsd_check rpm_generate + grow 325 + and allndifflv,allndiffmv + + # Check distance RPM to (unrelated) POLY + templayer rpm_poly_check rpm_generate + grow 200 + and-not xhrpoly,uhrpoly,xpc + and allpoly + + # Check distance RPM to HVNTM + templayer rpm_hvntm_check rpm_generate + grow 385 + and allndiffmvnontap + + templayer m1_small_hole allm1,obsm1,obsmcon + close 140000 + + templayer m1_hole_empty m1_small_hole + and-not allm1,obsm1,obsmcon + + templayer m2_small_hole allm2,obsm2 + close 140000 + + templayer m2_hole_empty m2_small_hole + and-not allm2,obsm2 + + templayer m1_huge allm1 + shrink 1500 + grow 1500 + + templayer m1_large_halo m1_huge + grow 280 + and-not m1_huge + and allm1 + + templayer m2_huge allm2 + shrink 1500 + grow 1500 + + templayer m2_large_halo m2_huge + grow 280 + and-not m2_huge + and allm2 + + templayer m3_huge allm3 + shrink 1500 + grow 1500 + + templayer m3_large_halo m3_huge + grow 400 + and-not m3_huge + and allm3 + + templayer m4_huge allm4 + shrink 1500 + grow 1500 + + templayer m4_large_halo m4_huge + grow 400 + and-not m4_huge + and allm4 + + +#---------------------------------------------------------------- +style density +#---------------------------------------------------------------- +# Style used by scripts to check for fill density +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + + templayer fom_all alldiff,fomfill + + templayer poly_all allpoly,polyfill + + templayer li_all allli,lifill + + templayer m1_all allm1,m1fill + + templayer m2_all allm2,m2fill + + templayer m3_all allm3,m3fill + + templayer m4_all allm4,m4fill + + templayer m5_all allm5,m5fill + +#---------------------------------------------------------------- +style wafflefill variants (),(tiled) +#---------------------------------------------------------------- +# Style used by scripts for automatically generating fill layers +# NOTE: Be sure to generate output on flattened layout. +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + +#---------------------------------------------------------------- +# Generate and retain a layer representing the bounding box. +# +# For variant (): +# The bounding box is the full extent of geometry on the top level +# cell. +# +# For variant (tiled): +# Use with a script that breaks layout into flattened tiles and runs +# fill individually on each. The tiles should be larger than the +# step size, and each should draw a layer "comment" the size of the +# step box. +#---------------------------------------------------------------- + + variants () + templayer topbox + bbox top + + variants (tiled) + templayer topbox comment + # Each tile imposes the full keepout distance rule of + # 3um on all sides. + shrink 1500 + + variants * + +#---------------------------------------------------------------- +# Generate guard-band around nwells to keep FOM from crossing +# Spacing from LV nwell = Diff/Tap 9 = 0.34um +# Spacing from HV nwell = Diff/Tap 18 = 0.43um (= 0.18 + 0.25) +# Enclosure by nwell = Diff/Tap 8 = 0.18um +#---------------------------------------------------------------- + + templayer mvnwell + bloat-all alldiffmv nwell + + templayer lvnwell allnwell + and-not mvnwell + + templayer well_shrink mvnwell + shrink 250 + or lvnwell + shrink 180 + templayer well_guardband allnwell + grow 340 + and-not well_shrink + +#--------------------------------------------------- +# Diffusion and poly keep-out areas +#--------------------------------------------------- + templayer obstruct_fom alldiff,allpoly,fomfill,polyfill,obsactive + or rpw,pnp,npn + grow 500 + or well_guardband + + templayer obstruct_poly alldiff,allpoly,fomfill,polyfill,obsactive + or rpw,pnp,npn + grow 1000 + +#--------------------------------------------------- +# FOM and POLY fill +#--------------------------------------------------- + templayer fomfill_pass1 topbox + # slots 0 4080 1320 0 4080 1320 1360 0 + slots 0 4080 1600 0 4080 1600 1360 0 + and-not obstruct_fom + and topbox + shrink 2035 + grow 2035 + +#--------------------------------------------------- + + templayer obstruct_poly_pass1 fomfill_pass1 + grow 300 + or obstruct_poly + templayer polyfill_pass1 topbox + slots 0 720 360 0 720 360 240 0 + and-not obstruct_poly_pass1 + and topbox + shrink 355 + grow 355 + +#--------------------------------------------------- + + templayer obstruct_fom_pass2 fomfill_pass1 + grow 1290 + or polyfill_pass1 + grow 300 + or obstruct_fom + templayer fomfill_pass2 topbox + slots 0 2500 1320 0 2500 1320 1360 0 + and-not obstruct_fom_pass2 + and topbox + shrink 1245 + grow 1245 + +#--------------------------------------------------- + + templayer obstruct_poly_coarse polyfill_pass1 + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_coarse topbox + slots 0 720 360 0 720 360 240 120 + and-not obstruct_poly_coarse + and topbox + shrink 355 + grow 355 + +#--------------------------------------------------- + templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_medium topbox + slots 0 540 360 0 540 360 240 100 + and-not obstruct_poly_medium + and topbox + shrink 265 + grow 265 + +#--------------------------------------------------- + templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium + grow 60 + or fomfill_pass1,fomfill_pass2 + grow 300 + or obstruct_poly + templayer polyfill_fine topbox + slots 0 480 360 0 480 360 240 200 + and-not obstruct_poly_fine + and topbox + shrink 235 + grow 235 + +#--------------------------------------------------- + + templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2 + grow 1290 + or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine + grow 300 + or obstruct_fom + templayer fomfill_coarse topbox + slots 0 1500 1320 0 1500 1320 1360 0 + and-not obstruct_fom_coarse + and topbox + shrink 745 + grow 745 + +#--------------------------------------------------- + + templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse + grow 1290 + or polyfill_pass1,polyfill_coarse,polyfill_medium,polyfill_fine + grow 300 + or obstruct_fom + templayer fomfill_fine topbox + slots 0 500 400 0 500 400 160 0 + and-not obstruct_fom_fine + and topbox + shrink 245 + grow 245 + +#--------------------------------------------------- + layer FOMFILL fomfill_pass1 + or fomfill_pass2 + or fomfill_coarse + or fomfill_fine + calma 23 28 + + layer POLYFILL polyfill_pass1 + or polyfill_coarse + or polyfill_medium + or polyfill_fine + calma 28 28 + +#--------------------------------------------------------- +# LI fill +# Note requirement that LI fill may not overlap (non-fill) +# diff or poly. +#--------------------------------------------------------- + + templayer obstruct_li_coarse allli,obsli,lifill,fillblock,fillblock4 + grow 2800 + or alldiff,allpoly + grow 200 + templayer lifill_coarse topbox + # slots 0 3000 650 0 3000 650 700 0 + slots 0 3000 900 0 3000 900 700 0 + and-not obstruct_li_coarse + and topbox + shrink 1495 + grow 1495 + + templayer obstruct_li_medium allli,obsli,lifill,fillblock,fillblock4 + grow 2500 + or lifill_coarse + grow 300 + or alldiff,allpoly + grow 200 + templayer lifill_medium topbox + slots 0 1500 500 0 1500 500 700 0 + and-not obstruct_li_medium + and topbox + shrink 745 + grow 745 + + templayer obstruct_li_fine allli,obsli,lifill,fillblock,fillblock4 + or lifill_coarse,lifill_medium + grow 300 + or alldiff,allpoly + grow 200 + templayer lifill_fine topbox + slots 0 580 500 0 580 500 700 0 + and-not obstruct_li_fine + and topbox + shrink 285 + grow 285 + + layer LIFILL lifill_coarse + or lifill_medium + or lifill_fine + calma 56 28 + +#--------------------------------------------------- +# MET1 fill +#--------------------------------------------------- + + templayer obstruct_m1_coarse allm1,obsm1,m1fill,fillblock,fillblock4 + grow 3000 + templayer met1fill_coarse topbox + # slots 0 2000 200 0 2000 200 700 0 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m1_coarse + and topbox + shrink 995 + grow 995 + + templayer obstruct_m1_medium allm1,obsm1,m1fill,fillblock,fillblock4 + grow 2800 + or met1fill_coarse + grow 200 + templayer met1fill_medium topbox + slots 0 1000 200 0 1000 200 700 0 + and-not obstruct_m1_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m1_fine allm1,obsm1,m1fill,fillblock,fillblock4 + grow 300 + or met1fill_coarse,met1fill_medium + grow 200 + templayer met1fill_fine topbox + slots 0 580 200 0 580 200 700 0 + and-not obstruct_m1_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m1_veryfine allm1,obsm1,m1fill,fillblock,fillblock4 + grow 100 + or met1fill_coarse,met1fill_medium,met1fill_fine + grow 200 + templayer met1fill_veryfine topbox + slots 0 300 200 0 300 200 100 50 + and-not obstruct_m1_veryfine + and topbox + shrink 145 + grow 145 + + layer MET1FILL met1fill_coarse + or met1fill_medium + or met1fill_fine + or met1fill_veryfine + calma 36 28 + +#--------------------------------------------------- +# MET2 fill +#--------------------------------------------------- + templayer obstruct_m2 allm2,obsm2,m2fill,fillblock,fillblock4 + grow 3000 + templayer met2fill_coarse topbox + # slots 0 2000 200 0 2000 200 700 350 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m2 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m2_medium allm2,obsm2,m2fill,fillblock,fillblock4 + grow 2800 + or met2fill_coarse + grow 200 + templayer met2fill_medium topbox + slots 0 1000 200 0 1000 200 700 350 + and-not obstruct_m2_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m2_fine allm2,obsm2,m2fill,fillblock,fillblock4 + grow 300 + or met2fill_coarse,met2fill_medium + grow 200 + templayer met2fill_fine topbox + slots 0 580 200 0 580 200 700 350 + and-not obstruct_m2_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m2_veryfine allm2,obsm2,m2fill,fillblock,fillblock4 + grow 100 + or met2fill_coarse,met2fill_medium,met2fill_fine + grow 200 + templayer met2fill_veryfine topbox + slots 0 300 200 0 300 200 100 100 + and-not obstruct_m2_veryfine + and topbox + shrink 145 + grow 145 + + layer MET2FILL met2fill_coarse + or met2fill_medium + or met2fill_fine + or met2fill_veryfine + calma 41 28 + +#--------------------------------------------------- +# MET3 fill +#--------------------------------------------------- + templayer obstruct_m3 allm3,glass,obsm3,m3fill,fillblock,fillblock4 + grow 3000 + templayer met3fill_coarse topbox + # slots 0 2000 300 0 2000 300 700 700 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m3 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m3_medium allm3,glass,obsm3,m3fill,fillblock,fillblock4 + grow 2700 + or met3fill_coarse + grow 300 + templayer met3fill_medium topbox + slots 0 1000 300 0 1000 300 700 700 + and-not obstruct_m3_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m3_fine allm3,glass,obsm3,m3fill,fillblock,fillblock4 + grow 200 + or met3fill_coarse,met3fill_medium + grow 300 + templayer met3fill_fine topbox + slots 0 580 300 0 580 300 700 700 + and-not obstruct_m3_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m3_veryfine allm3,glass,obsm3,m3fill,fillblock,fillblock4 + # Note: Adding 0.1 to waffle rule to clear wide spacing rule + grow 100 + or met3fill_coarse,met3fill_medium,met3fill_fine + grow 300 + templayer met3fill_veryfine topbox + slots 0 400 300 0 400 300 150 200 + and-not obstruct_m3_veryfine + and topbox + shrink 195 + grow 195 + + layer MET3FILL met3fill_coarse + or met3fill_medium + or met3fill_fine + or met3fill_veryfine + calma 34 28 + +#--------------------------------------------------- +# MET4 fill +#--------------------------------------------------- + templayer obstruct_m4 glass + grow 2500 + or allm4,obsm4,m4fill,fillblock,fillblock4 + grow 3000 + templayer met4fill_coarse topbox + # slots 0 2000 300 0 2000 300 700 1050 + slots 0 2000 800 0 2000 800 700 350 + and-not obstruct_m4 + and topbox + shrink 995 + grow 995 + + templayer obstruct_m4_medium glass + grow 2500 + or allm4,obsm4,m4fill,fillblock,fillblock4 + grow 2700 + or met4fill_coarse + grow 300 + templayer met4fill_medium topbox + slots 0 1000 300 0 1000 300 700 1050 + and-not obstruct_m4_medium + and topbox + shrink 495 + grow 495 + + templayer obstruct_m4_fine glass + grow 5000 + or allm4,obsm4,m4fill,fillblock,fillblock4 + grow 200 + or met4fill_coarse,met4fill_medium + grow 300 + templayer met4fill_fine topbox + slots 0 580 300 0 580 300 700 1050 + and-not obstruct_m4_fine + and topbox + shrink 285 + grow 285 + + templayer obstruct_m4_veryfine glass + grow 5100 + or allm4,obsm4,m4fill,fillblock,fillblock4 + # Note: Adding 0.1 to waffle rule to clear wide spacing rule + grow 100 + or met4fill_coarse,met4fill_medium,met4fill_fine + grow 300 + templayer met4fill_veryfine topbox + slots 0 400 300 0 400 300 150 300 + and-not obstruct_m4_veryfine + and topbox + shrink 195 + grow 195 + + layer MET4FILL met4fill_coarse + or met4fill_medium + or met4fill_fine + or met4fill_veryfine + calma 51 28 + +#--------------------------------------------------- +# MET5 fill +#--------------------------------------------------- + templayer obstruct_m5 allm5,glass,obsm5,m5fill,fillblock + grow 3000 + templayer met5fill_coarse topbox + slots 0 5000 1600 0 5000 1600 1000 100 + and-not obstruct_m5 + and topbox + shrink 2495 + grow 2495 + + templayer obstruct_m5_medium allm5,glass,obsm5,m5fill,fillblock + grow 1400 + or met5fill_coarse + grow 1600 + templayer met5fill_medium topbox + slots 0 3000 1600 0 3000 1600 1000 100 + and-not obstruct_m5_medium + and topbox + shrink 1495 + grow 1495 + + layer MET5FILL met5fill_coarse + or met5fill_medium + calma 59 28 + +style subcutout + # generates a new subcut layer from the cell boundary, with windows for existing subcut and dnwell + # should be used on a flattened layout + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + + templayer CELLBOUND + boundary + + templayer large_dnwell dnwell + grow 10 + + templayer large_isosub isosub + grow 10 + + layer SUBCUT CELLBOUND + grow 10 + and-not large_dnwell + and-not large_isosub + calma 81 53 +end + +#----------------------------------------------------------------------- +cifinput +#----------------------------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size +#----------------------------------------------------------------------- + +style sky130 variants (),(vendor),(nowell) + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels + + ignore NPC + ignore SEALID + ignore CAPID + ignore LDNTM + ignore HVNTM + ignore POLYMOD + ignore LOWTAPDENSITY + ignore FILLOBSPOLY + ignore FILLOBSFOM + ignore MET5BLOCK + ignore OUTLINE + ignore POLYCUT + ignore POLYGATE + ignore DIFFCUT + ignore HVNWELLID + ignore PADDIFFID + ignore PADMETALID + ignore PADCENTERID +variants (nowell) + ignore DNWELL + ignore SUBCUT + ignore NWELL + ignore PWRES + ignore NPNID + ignore PNPID + ignore PHOTO + ignore SUBTXT + ignore WELLTXT + ignore SUBPIN + ignore WELLPIN + +variants (),(vendor) + layer pnp NWELL,WELLTXT,WELLPIN + and PNPID + labels NWELL + labels WELLPIN port + labels WELLTXT text + + layer nwell NWELL,WELLTXT,WELLPIN + and-not PNPID + labels NWELL + labels WELLPIN port + labels WELLTXT text + + templayer nwellarea NWELL + copyup nwelcheck + + # Copy nwell areas up for diffusion checks + templayer xnwelcheck nwelcheck + copyup nwelcheck + + # Always draw pwell under p-tap and n-diff. This is not always + # necessary but works better with deep nwell for correct extraction. + layer pwell TAP,DIFF + and-not NWELL,nwelcheck + grow 130 + or SUBTXT,SUBPIN + grow 420 + shrink 420 + labels SUBPIN port + labels SUBTXT text + + layer dnwell DNWELL + labels DNWELL + + layer isosub SUBCUT + labels SUBCUT + + layer npn DNWELL + and-not NWELL,nwelcheck + and NPNID + + layer photo DNWELL + and PHOTO + + layer rpw PWRES + and DNWELL + labels PWRES + +variants * + templayer hvarea HVI + copyup hvcheck + + # Copy high-voltage (HVI) areas up for diffusion checks + templayer xhvcheck hvcheck + copyup hvcheck + + templayer ndiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and-not NWELL,nwelcheck + and-not PSDM + and-not DIODE + and-not DIFFRES + and-not HVI,hvcheck + and NSDM + and-not CORELI + copyup ndifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + variants * + + layer ndiff ndiffarea + + # Copy ndiff areas up for contact checks + templayer xndifcheck ndifcheck + copyup ndifcheck + + templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and-not NWELL,nwelcheck + and-not PSDM + and-not DIODE + and-not DIFFRES + and HVI,hvcheck + and NSDM + copyup ndifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer mvndiff mvndiffarea + + # Copy ndiff areas up for contact checks + templayer mvxndifcheck mvndifcheck + copyup mvndifcheck + + layer ndiode DIFF,barediff + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and-not LVTN + labels DIFF + + layer ndiodelvt DIFF,barediff + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and LVTN + labels DIFF + + templayer ndiodearea DIODE + and NSDM + and-not HVI,hvcheck + and-not NWELL,nwelcheck + copyup DIODE,NSDM + + layer ndiffres DIFFRES + and NSDM + and-not HVI,hvcheck + labels DIFF + + templayer pdiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and NWELL,nwelcheck + and-not NSDM + and-not DIODE + and-not HVI,hvcheck + and PSDM + copyup pdifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer pdiff pdiffarea + + layer mvndiode DIFF,barediff + and NSDM + and DIODE + and HVI,hvcheck + and-not POLY + and-not PSDM + and-not LVTN + labels DIFF + + layer nndiode DIFF,barediff + and NSDM + and DIODE + and HVI,hvcheck + and-not POLY + and-not PSDM + and LVTN + labels DIFF + + templayer mvndiodearea DIODE + and NSDM + and HVI,hvcheck + and-not NWELL,nwelcheck + copyup DIODE,NSDM + + layer mvndiffres DIFFRES + and NSDM + and HVI,hvcheck + labels DIFF + + templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN,barediff + and-not POLY + and NWELL,nwelcheck + and-not NSDM + and HVI,hvcheck + and-not DIODE + and-not DIFFRES + and PSDM + copyup mvpdifcheck + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer mvpdiff mvpdiffarea + + # Copy pdiff areas up for contact checks + templayer xpdifcheck pdifcheck + copyup pdifcheck + + layer pdiode DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodelvt DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodehvt DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and HVTP + and DIODE + labels DIFF + + templayer pdiodearea DIODE + and PSDM + and-not HVI,hvcheck + copyup DIODE,PSDM + + # Define pfet areas as known pdiff, regardless of the presence of a well. + + templayer pfetarea DIFF,barediff + and POLY + or baretrans + and-not NSDM + and-not HVI,hvcheck + + layer pfet pfetarea + and-not LVTN + and-not HVTP + and-not STDCELL + and-not COREID + labels DIFF + + layer scpfet pfetarea + and-not LVTN + and-not HVTP + and STDCELL + and-not COREID + labels DIFF + + layer scpfethvt pfetarea + and-not LVTN + and HVTP + and STDCELL + labels DIFF + + layer ppu pfetarea + and-not LVTN + and HVTP + and COREID + # Shrink-grow operation eliminates the smaller parasitie device + # shrink 70 + # grow 70 + labels DIFF + + layer pfetlvt pfetarea + and LVTN + labels DIFF + + layer pfetmvt pfetarea + and HVTR + labels DIFF + + layer pfethvt pfetarea + and HVTP + and-not STDCELL + and-not COREID + labels DIFF + + # Always force nwell under pfet (nwell encloses pdiff by 0.18) + layer nwell pfetarea + and-not COREID + grow 180 + + # Copy mvpdiff areas up for contact checks + templayer mvxpdifcheck mvpdifcheck + copyup mvpdifcheck + + layer mvpdiode DIFF,barediff + and PSDM + and-not POLY + and-not NSDM + and HVI,hvcheck + and DIODE + labels DIFF + + templayer mvpdiodearea DIODE + and PSDM + and HVI,hvcheck + copyup DIODE,PSDM + + # Define pfet areas as known pdiff, + # regardless of the presence of a + # well. + + templayer mvpfetarea DIFF,barediff + and POLY + or baretrans + and-not NSDM + and HVI,hvcheck + + layer mvpfet mvpfetarea + and-not ESDID + labels DIFF + + layer mvpfetesd mvpfetarea + and ESDID + labels DIFF + + layer pdiff DIFF,DIFFTXT,DIFFPIN,barediff + and-not NSDM + and-not POLY + and-not HVI,hvcheck + and-not DIODE + and-not DIFFRES + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer pdiffres DIFFRES + and PSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + labels DIFF + + layer nfet DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not HVI,hvcheck + and-not LVTN + and-not SONOS + and-not STDCELL + and-not COREID + labels DIFF + + layer scnfet DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and-not HVI,hvcheck + and-not LVTN + and-not SONOS + and STDCELL + labels DIFF + + layer npass DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and COREID + labels DIFF + + layer npd DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and COREID + # Shrink-grow operation eliminates the smaller npass device + shrink 70 + grow 70 + labels DIFF + + # Devices abutting tap under gate are officially npd, not npass + layer npd TAP + grow 100 + and DIFF + and POLY + and-not PSDM + and NSDM + and-not NWELL,nwelcheck + and COREID + labels DIFF + + layer nfetlvt DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not HVI,hvcheck + and LVTN + and-not SONOS + labels DIFF + + layer nsonos DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not HVI,hvcheck + and LVTN + and SONOS + labels DIFF + + templayer nsdarea TAP,DIFF + and NSDM + and NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and-not CORELI + copyup nsubcheck + + layer nsd nsdarea + labels TAP + + layer nsd TAP,TAPTXT + and NSDM + and-not POLY + and-not HVI,hvcheck + labels TAP + labels TAPTXT text + + layer corenvar TAP + and NSDM + and POLY + and COREID + labels TAP + + templayer nsdexpand nsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer xnsubcheck nsubcheck + copyup nsubcheck + + templayer psdarea TAP,DIFF + and PSDM + and-not NWELL,nwelcheck + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not pfetexpand + copyup psubcheck + + layer psd psdarea + labels TAP + + layer psd TAP + and PSDM + and-not POLY + and-not HVI,hvcheck + labels TAP + labels TAPTXT text + + layer corepvar TAP + and PSDM + and POLY + and COREID + labels TAP + + templayer psdexpand psdarea + grow 500 + + layer mvpdiff DIFF,DIFFTXT,DIFFPIN,barediff + and-not NSDM + and-not POLY + and HVI,hvcheck + and mvpfetexpand + labels DIFF + labels DIFFPIN port + labels DIFFTXT text + + layer mvpdiffres DIFFRES + and PSDM + and NWELL,nwelcheck + and HVI,hvcheck + and-not mvrdpioedge + labels DIFF + + templayer mvnfetarea DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and-not LVTN + and HVI,hvcheck + grow 350 + + templayer mvnnfetarea DIFF,TAP,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and LVTN + and HVI,hvcheck + and-not mvnfetarea + + layer mvnfetesd DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and HVI,hvcheck + and ESDID + and-not mvnnfetarea + labels DIFF + + layer mvnfet DIFF,barediff + and POLY + or baretrans + and-not PSDM + and NSDM + and HVI,hvcheck + and-not ESDID + and-not mvnnfetarea + labels DIFF + + layer nnfet mvnnfetarea + and LVID + labels DIFF + + layer mvnnfet mvnnfetarea + and-not LVID + labels DIFF + + templayer mvnsdarea TAP,DIFF + and NSDM + and NWELL,nwelcheck + and-not POLY + and-not PSDM + and HVI,hvcheck + copyup mvnsubcheck + + layer mvnsd mvnsdarea + labels TAP + + layer mvnsd TAP,TAPTXT + and NSDM + and HVI,hvcheck + labels TAP + labels TAPTXT text + + # Fill in FET under extended drain + layer mvpfet EDID + and POLY + and-not DIFF + and-not TAP + and-not NWELL + + layer mvnfet EDID + and POLY + and-not DIFF + and-not TAP + and NWELL + + # Restrict where nwell is merged + templayer ldmos_nwell EDID + grow 1200 + and NWELL + + # Remove or add well under extended FET gate + layer nwell EDID + and POLY + and DIFF + and PSDM + grow 685 + or ldmos_nwell + grow 420 + shrink 420 + + layer pwell EDID + and POLY + and DIFF + and NSDM + grow 660 + grow 420 + shrink 420 + + layer ed EDID + and-not POLY + and-not DIFF + and-not TAP + + templayer mvnsdexpand mvnsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer mvxnsubcheck mvnsubcheck + copyup mvnsubcheck + + templayer mvpsdarea TAP,DIFF,barediff + and PSDM + and-not NWELL,nwelcheck + and-not POLY + and-not NSDM + and HVI,hvcheck + and-not mvpfetexpand + copyup mvpsubcheck + + layer mvpsd mvpsdarea + labels DIFF + + layer mvpsd TAP,TAPTXT + and PSDM + and HVI,hvcheck + labels TAP + labels TAPTXT text + + templayer mvpsdexpand mvpsdarea + grow 500 + + # Copy psub areas up for contact checks + templayer xpsubcheck psubcheck + copyup psubcheck + + templayer mvxpsubcheck mvpsubcheck + copyup mvpsubcheck + + layer psd TAP + and-not PSDM + and-not NSDM + and-not POLY + and-not HVI,hvcheck + and-not pfetexpand + and psdexpand + + layer nsd TAP + and-not PSDM + and-not NSDM + and-not POLY + and-not HVI,hvcheck + and nsdexpand + + layer mvpsd TAP + and-not PSDM + and-not NSDM + and-not POLY + and HVI,hvcheck + and-not mvpfetexpand + and mvpsdexpand + + layer mvnsd TAP + and-not PSDM + and-not NSDM + and-not POLY + and HVI,hvcheck + and mvnsdexpand + +# The following recipes deal with DIFFRES layers expanded over large areas +# outside the resistor. Find areas which may have been accidentally +# captured as a resistor which were supposed to be transistors. + + templayer diffresarea DIFFRES + and-not HVI,hvcheck + grow 3000 + + layer pfet DIFF + and diffresarea + and POLY + and-not NSDM + and-not STDCELL + and-not HVI + + layer mvpfet DIFF + and diffresarea + and POLY + and-not NSDM + and-not STDCELL + and HVI + + layer scpfet STDCELL + and POLY + and diffresarea + and DIFF + and-not NSDM + and-not HVTP + + layer scpfethvt STDCELL + and POLY + and diffresarea + and DIFF + and-not NSDM + and HVTP + +# End of resistor area hack + + templayer xpolyterm RPM,URPM + and POLY + and-not POLYRES + # add back the 0.08um contact surround in the direction of the resistor + grow 80 + and POLY + + layer xpc xpolyterm + + templayer polyarea POLY,POLYTXT,POLYPIN + and-not POLYRES + and-not POLYSHORT + and-not DIFF + and-not TAP + and-not RPM + and-not URPM + + templayer polycontarea polyarea + # Remove areas too small for a contact + shrink 130 + grow 130 + copyup polycheck + + layer poly polyarea + labels POLY + labels POLYPIN port + labels POLYTXT text + + # Copy (non-resistor) poly areas up for contact checks + templayer xpolycheck polycheck + copyup polycheck + + layer mrp1 POLYRES + and POLY + and-not RPM + and-not URPM + labels POLY + + layer rmp POLYSHORT + and POLY + labels POLY + + layer xhrpoly RPM + and POLYRES + and POLY + and-not URPM + and PSDM + and NPC + and-not xpolyterm + labels POLY + + layer uhrpoly URPM + and POLYRES + and POLY + and-not RPM + and NPC + and-not xpolyterm + labels POLY + + templayer ndcbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and-not NWELL,nwelcheck + and-not HVI,hvcheck + + layer ndc ndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndcbase + labels CONT + + templayer nscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and NSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + + layer nsc nscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nscbase + labels CONT + + templayer pdcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + + layer pdc pdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcbase + labels CONT + + templayer pdcnowell CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and pfetexpand + and-not HVI,hvcheck + + layer pdc pdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcnowell + labels CONT + + templayer pscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and PSDM + and-not NWELL,nwelcheck + and-not pfetexpand + and-not HVI,hvcheck + + layer psc pscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pscbase + labels CONT + + templayer pcbase CONT + or barecont + and LI + or barelicont + and POLY + and-not DIFF + and-not RPM,URPM + + layer pc pcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pcbase + labels CONT + + templayer ndicbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and-not LVTN + + layer ndic ndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndicbase + labels CONT + + templayer ndilvtcbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not NWELL,nwelcheck + and-not POLY + and-not PSDM + and-not HVI,hvcheck + and LVTN + + layer ndilvtc ndilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndilvtcbase + labels CONT + + templayer pdicbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and-not HVTP + + layer pdic pdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdicbase + labels CONT + + templayer pdilvtcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and LVTN + and-not HVTP + + layer pdilvtc pdilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdilvtcbase + labels CONT + + templayer pdihvtcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and-not HVI,hvcheck + and-not LVTN + and HVTP + + layer pdihvtc pdihvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdihvtcbase + labels CONT + + templayer mvndcbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and-not NWELL,nwelcheck + and HVI,hvcheck + + layer mvndc mvndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndcbase + labels CONT + + templayer mvnscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and NSDM + and NWELL,nwelcheck + and HVI,hvcheck + + layer mvnsc mvnscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnscbase + labels CONT + + templayer mvpdcbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and NWELL,nwelcheck + and HVI,hvcheck + + layer mvpdc mvpdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcbase + labels CONT + + templayer mvpdcnowell CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and mvpfetexpand + and MET1 + and HVI,hvcheck + + layer mvpdc mvpdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcnowell + labels CONT + + templayer mvpscbase CONT + or barecont + and LI + or barelicont + and DIFF,TAP + and PSDM + and-not NWELL,nwelcheck + and-not mvpfetexpand + and HVI,hvcheck + + layer mvpsc mvpscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpscbase + labels CONT + + templayer mvndicbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not POLY + and-not PSDM + and-not LVTN + and HVI,hvcheck + + layer mvndic mvndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndicbase + labels CONT + + templayer nndicbase CONT + or barecont + and LI + or barelicont + and DIFF + and NSDM + and DIODE + and-not POLY + and-not PSDM + and LVTN + and HVI,hvcheck + + layer nndic nndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nndicbase + labels CONT + + templayer mvpdicbase CONT + or barecont + and LI + or barelicont + and DIFF + and PSDM + and DIODE + and-not POLY + and-not NSDM + and HVI,hvcheck + + layer mvpdic mvpdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdicbase + labels CONT + + layer fomfill FOMFILL + labels FOMFILL + + layer polyfill POLYFILL + labels POLYFILL + + layer coreli LI,LITXT,LIPIN + and-not LIRES,LISHORT + and COREID + labels LI + labels LIPIN port + labels LITXT text + + layer locali LI,LITXT,LIPIN + and-not LIRES,LISHORT + and-not COREID + labels LI + labels LIPIN port + labels LITXT text + + layer rli LI + and LIRES,LISHORT + labels LIRES,LISHORT + + layer lifill LIFILL + labels LIFILL + + layer mcon MCON + grow 95 + shrink 95 + shrink 85 + grow 85 + or MCON + labels MCON + + layer m1 MET1,MET1TXT,MET1PIN + and-not MET1RES,MET1SHORT + labels MET1 + labels MET1PIN port + labels MET1TXT text + + layer rm1 MET1 + and MET1RES,MET1SHORT + labels MET1RES,MET1SHORT + + layer m1fill MET1FILL + labels MET1FILL + + layer mimcap MET3 + and CAPM + labels CAPM + + layer mimcc VIA3 + and CAPM + grow 60 + grow 40 + shrink 40 + labels CAPM + + layer mimcap2 MET4 + and CAPM2 + labels CAPM2 + + layer mim2cc VIA4 + and CAPM2 + grow 190 + grow 210 + shrink 210 + labels CAPM2 + + + # RERAM is drawn as-is + layer reram RERAM + + templayer m2cbase VIA1 + and-not RERAM + and-not COREID + grow 5 + or VIA1 + and-not RERAM + grow 50 + + layer m2c m2cbase + grow 30 + shrink 30 + shrink 130 + grow 130 + or m2cbase + + layer m2 MET2,MET2TXT,MET2PIN + and-not MET2RES,MET2SHORT + labels MET2 + labels MET2PIN port + labels MET2TXT text + + layer rm2 MET2 + and MET2RES,MET2SHORT + labels MET2RES,MET2SHORT + + layer m2fill MET2FILL + labels MET2FILL + + templayer m3cbase VIA2 + grow 40 + + layer m3c m3cbase + grow 60 + shrink 60 + shrink 140 + grow 140 + or m3cbase + + layer m3 MET3,MET3TXT,MET3PIN + and-not MET3RES,MET3SHORT + labels MET3 + labels MET3PIN port + labels MET3TXT text + + layer rm3 MET3 + and MET3RES,MET3SHORT + labels MET3RES,MET3SHORT + + layer m3fill MET3FILL + labels MET3FILL + + + templayer via3base VIA3 + and-not CAPM + grow 60 + + layer via3 via3base + grow 40 + shrink 40 + shrink 160 + grow 160 + or via3base + + layer m4 MET4,MET4TXT,MET4PIN + and-not MET4RES,MET4SHORT + labels MET4 + labels MET4PIN port + labels MET4TXT text + + layer rm4 MET4 + and MET4RES,MET4SHORT + labels MET4RES,MET4SHORT + + layer m4fill MET4FILL + labels MET4FILL + + layer m5 MET5,MET5TXT,MET5PIN + and-not MET5RES,MET5SHORT + labels MET5 + labels MET5PIN port + labels MET5TXT text + + layer rm5 MET5 + and MET5RES,MET5SHORT + labels MET5RES,MET5SHORT + + layer m5fill MET5FILL + labels MET5FILL + + templayer via4base VIA4 + and-not CAPM2 + grow 190 + + layer via4 via4base + grow 210 + shrink 210 + shrink 590 + grow 590 + or via4base + + layer metrdl RDL,RDLTXT,RDLPIN + labels RDL + labels RDLPIN port + labels RDLTXT text + + # Find diffusion not covered in + # NSDM or PSDM and pull it into + # the next layer up + + templayer gentrans DIFF + and-not PSDM + and-not NSDM + and POLY + copyup baretrans + + templayer gendiff DIFF,TAP + and-not PSDM + and-not NSDM + and-not POLY + and-not COREID + copyup barediff + + # Handle contacts found by copyup + + templayer ndiccopy CONT + and LI + and DIODE + and DIFF + and-not NWELL,nwelcheck + and NSDM + and-not LVTN + and-not HVI,hvcheck + + layer ndic ndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndiccopy + labels CONT + + templayer mvndiccopy CONT + and LI + and DIODE + and DIFF + and-not NWELL,nwelcheck + and NSDM + and-not LVTN + and HVI,hvcheck + + layer mvndic mvndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndiccopy + labels CONT + + templayer pdiccopy CONT + and LI + and DIODE + and DIFF + and PSDM + and-not HVI,hvcheck + + layer pdic pdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdiccopy + labels CONT + + templayer mvpdiccopy CONT + and LI + and DIODE + and PSDM + and HVI,hvcheck + + layer mvpdic mvpdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdiccopy + labels CONT + + templayer ndccopy CONT + and ndifcheck + + layer ndc ndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndccopy + labels CONT + + templayer mvndccopy CONT + and mvndifcheck + + layer mvndc mvndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndccopy + labels CONT + + templayer pdccopy CONT + and pdifcheck + + layer pdc pdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdccopy + labels CONT + + templayer mvpdccopy CONT + and mvpdifcheck + + layer mvpdc mvpdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdccopy + labels CONT + + templayer pccopy CONT + and polycheck + + layer pc pccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pccopy + labels CONT + + templayer nsccopy CONT + and nsubcheck + + layer nsc nsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or nsccopy + labels CONT + + templayer mvnsccopy CONT + and mvnsubcheck + + layer mvnsc mvnsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnsccopy + labels CONT + + templayer psccopy CONT + and psubcheck + + layer psc psccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or psccopy + labels CONT + + templayer mvpsccopy CONT + and mvpsubcheck + + layer mvpsc mvpsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpsccopy + labels CONT + + # Find contacts not covered in + # metal and pull them into the + # next layer up + + templayer barelicont CONT + and LI + and-not DIFF,TAP + and-not POLY + and-not DIODE + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + and-not CORELI + copyup barelicont + + templayer barecont CONT + and-not LI + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + and-not CORELI + copyup barecont + + layer glass GLASS,PADTXT,PADPIN + labels GLASS + labels PADPIN port + labels PADTXT text + + templayer boundary BOUND,STDCELL,PADCELL + boundary + + layer comment LVSTEXT + labels LVSTEXT text + + layer comment TTEXT + labels TTEXT text + + layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4,FILLOBSM5 + labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4,FILLOBSM5 + + layer fillblock4 FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + and-not FILLOBSM5 + labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + +# MOS Varactor + + layer var POLY + and TAP + and NSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + and-not HVTP + # NOTE: Else forms a varactor that is not in the vendor netlist. + and-not COREID + labels POLY + + layer varhvt POLY + and TAP + and NSDM + and NWELL,nwelcheck + and-not HVI,hvcheck + and HVTP + labels POLY + + layer mvvar POLY + and TAP + and NSDM + and NWELL,nwelcheck + and HVI,hvcheck + labels POLY + + calma NWELL 64 20 + calma DIFF 65 20 + calma TAP 65 44 + calma DNWELL 64 18 + calma SUBCUT 81 53 + calma PWRES 64 13 + # LVTN + calma LVTN 125 44 + # HVTR + calma HVTR 18 20 + # HVTP + calma HVTP 78 44 + # SONOS (TUNM) + calma SONOS 80 20 + # NSDM (NPLUS) + calma NSDM 93 44 + # PSDM (PPLUS) + calma PSDM 94 20 + # HVI (THKOX) + calma HVI 75 20 + # EDID + calma EDID 81 57 + # NPC + calma NPC 95 20 + # P+ POLY MASK + calma RPM 86 20 + calma URPM 79 20 + calma LDNTM 11 44 + calma HVNTM 125 20 + # Poly resistor ID mark + calma POLYRES 66 13 + # Diffusion resistor ID mark + calma DIFFRES 65 13 + calma POLY 66 20 + calma POLYMOD 66 83 + # 3.3V native FET ID mark + calma LVID 81 60 + # Diode ID mark + calma DIODE 81 23 + # Bipolar NPN mark + calma NPNID 82 20 + # Bipolar PNP mark + calma PNPID 82 44 + # Capacitor ID + calma CAPID 82 64 + # Core area ID mark + calma COREID 81 2 + # Photodiode ID mark + calma PHOTO 81 81 + # Standard cell ID mark + calma STDCELL 81 4 + # Padframe cell ID mark + calma PADCELL 81 3 + # Seal ring ID mark + calma SEALID 81 1 + # Low tap density ID mark + calma LOWTAPDENSITY 81 14 + # ESD area ID + calma ESDID 81 19 + # Various unused layers + calma OUTLINE 236 0 + calma POLYCUT 66 14 + calma POLYGATE 66 9 + calma DIFFCUT 65 14 + calma HVNWELLID 81 63 + calma MET5BLOCK 72 10 + calma PADDIFFID 81 6 + calma PADMETALID 81 8 + calma PADCENTERID 81 20 + + # LICON + calma CONT 66 44 + calma LI 67 20 + calma MCON 67 44 + + calma MET1 68 20 + calma VIA1 68 44 + calma RERAM 201 20 + calma MET2 69 20 + calma VIA2 69 44 + calma MET3 70 20 + calma VIA3 70 44 + calma MET4 71 20 + calma VIA4 71 44 + calma MET5 72 20 + calma RDL 74 20 + calma GLASS 76 20 + + calma SUBTXT 64 59 + calma PADTXT 76 5 + calma DIFFTXT 65 6 + calma TAPTXT 65 5 + calma WELLTXT 64 5 + calma LITXT 67 5 + calma POLYTXT 66 5 + calma MET1TXT 68 5 + calma MET2TXT 69 5 + calma MET3TXT 70 5 + calma MET4TXT 71 5 + calma MET5TXT 72 5 + calma RDLTXT 74 5 + + calma LIRES 67 13 + calma MET1RES 68 13 + calma MET2RES 69 13 + calma MET3RES 70 13 + calma MET4RES 71 13 + calma MET5RES 72 13 + + calma LIFILL 56 28 + calma MET1FILL 36 28 + calma MET2FILL 41 28 + calma MET3FILL 34 28 + calma MET4FILL 51 28 + calma MET5FILL 59 28 + + calma POLYSHORT 66 15 + calma LISHORT 67 15 + calma MET1SHORT 68 15 + calma MET2SHORT 69 15 + calma MET3SHORT 70 15 + calma MET4SHORT 71 15 + calma MET5SHORT 72 15 + + calma SUBPIN 122 16 + calma PADPIN 76 16 + calma DIFFPIN 65 16 + calma POLYPIN 66 16 + calma WELLPIN 64 16 + calma LIPIN 67 16 + calma MET1PIN 68 16 + calma MET2PIN 69 16 + calma MET3PIN 70 16 + calma MET4PIN 71 16 + calma MET5PIN 72 16 + calma RDLPIN 74 16 + + calma BOUND 235 4 + + calma LVSTEXT 83 44 + + calma CAPM 89 44 + calma CAPM2 97 44 + + calma FILLOBSM1 62 24 + calma FILLOBSM2 105 52 + calma FILLOBSM3 107 24 + calma FILLOBSM4 112 4 + calma FILLOBSM5 117 4 + calma FILLOBSFOM 22 24 + calma FILLOBSPOLY 33 24 + + calma FOMFILL 23 28 + calma POLYFILL 28 28 + calma LIFILL 56 28 + calma MET1FILL 36 28 + calma MET2FILL 41 28 + calma MET3FILL 34 28 + calma MET4FILL 51 28 + calma MET5FILL 59 28 + +#----------------------------------------------------------------------- + +style rdlimport + # This style is for reading shapes generated with the RDL layers + + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels no-reconnect-labels + + layer mrdl RDL + layer mrdlc RDLC + + calma RDL 10 0 + calma RDLC 20 0 + +end + +#----------------------------------------------------- +# Digital flow maze router cost parameters +#----------------------------------------------------- + +mzrouter +end + +#----------------------------------------------------- +# Vendor DRC rules +#----------------------------------------------------- + +drc + + style drc variants (fast),(full),(routing) + scalefactor 10 + cifstyle drc + + variants (fast),(full) + +#----------------------------- +# DNWELL +#----------------------------- + + width dnwell 3000 "Deep N-well width < %d (dnwell.2)" + spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)" + spacing allnwell dnwell 4500 surround_ok \ + "Deep N-well spacing to N-well < %d (nwell.7)" + + variants (full) + cifmaxwidth nwell_missing 0 bend_illegal \ + "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)" + cifmaxwidth dnwell_missing 0 bend_illegal \ + "SONOS nFET must be in Deep N-well (tunm.6a)" + + cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \ + "P+ diff cannot straddle Deep N-well (dnwell.5)" + variants (fast),(full) + + width photo 3000 "Photodiode width < %d (photo.2)" + spacing photo photo 5000 touching_ok "Photodiode spacing < %d (photo.3)" + spacing photo dnwell 5300 touching_illegal \ + "Photodiode spacing to deep nwell < %d (photo.4)" + +#----------------------------- +# NWELL +#----------------------------- + + width allnwell 840 "N-well width < %d (nwell.1)" + spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)" + + variants (full) + cifmaxwidth nwell_missing_tap 0 bend_illegal \ + "All nwells must contain metal-connected N+ taps (nwell.4)" + + cifspacing mvnwell lvnwell 2000 touching_illegal \ + "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)" + cifspacing mvnwell mvnwell 2000 touching_ok \ + "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)" + + cifmaxwidth lvdiff_in_mvnwell 0 bend_illegal \ + "All HV nwell can contain only HV diffusion (diff/tap.21)" + + variants (fast),(full) + +#----------------------------- +# DIFF +#----------------------------- + + width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres,fomfill \ + 150 "Diffusion width < %d (diff/tap.1)" + width *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,mvpfetesd,*mvpdiode,mvpdiffres 290 \ + "MV Diffusion width < %d (diff/tap.14)" + + width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)" + extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)" + extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)" + extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)" + extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)" + width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)" + spacing alldifflv,var,varhvt,corenvar,corepvar,fomfill \ + alldifflv,var,varhvt,corenvar,corepvar,fomfill 270 touching_ok \ + "Diffusion spacing < %d (diff/tap.3)" + spacing alldifflv,var,varhvt alldiffmv,mvvar 270 touching_illegal \ + "LV to MV Diffusion spacing < %d (diff/tap.3)" + spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \ + "MV Diffusion spacing < %d (diff/tap.15a)" + spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \ + "MV Diffusion to MV tap spacing < %d (diff/tap.3)" + spacing *mvndiff,mvnfet,mvnfetesd,mvnnfet,nnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \ + touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)" + spacing *mvnsd,*mvpdiff,mvpfet,mvpfetesd,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \ + "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)" + spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \ + "N-Diffusion spacing to N-well < %d (diff/tap.9)" + spacing *mvndiff,*mvndiode,mvnfet,mvnnfet,nnfet allnwell 340 touching_illegal \ + "N-Diffusion spacing to N-well < %d (diff/tap.9)" + spacing *psd allnwell 130 touching_illegal \ + "P-tap spacing to N-well < %d (diff/tap.11)" + spacing *mvpsd allnwell 130 touching_illegal \ + "P-tap spacing to N-well < %d (diff/tap.11)" + surround *nsd allnwell 180 absence_illegal \ + "N-well overlap of N-tap < %d (diff/tap.10)" + surround *mvnsd allnwell 330 absence_illegal \ + "N-well overlap of MV N-tap < %d (diff/tap.19)" + surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \ + "N-well overlap of P-Diffusion < %d (diff/tap.8)" + surround *mvpdiff,*mvpdiode,mvpfet,mvpfetesd allnwell 330 absence_illegal \ + "N-well overlap of P-Diffusion < %d (diff/tap.17)" + surround mvvar allnwell 560 absence_illegal \ + "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)" + spacing *mvndiode *mvndiode 1070 touching_ok \ + "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)" + +variants (full) + cifspacing allmvdiffnowell lvnwell 825 touching_illegal \ + "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)" + cifspacing nwell_or_hvi nwell_or_hvi 700 touching_ok \ + "HVI to HVI or LV nwell spacing < %d (hvi.5)" +variants (fast),(full) + + spacing allnfets allpactivenonfet 270 touching_illegal \ + "nFET cannot abut P-diffusion (diff/tap.3)" + spacing allpfets allnactivenonfet 270 touching_illegal \ + "pFET cannot abut N-diffusion (diff/tap.3)" + + # Butting junction rules + edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)" + edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)" + edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)" + edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)" + + edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)" + edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)" + edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)" + edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)" + + # Sandwiched butting junction restrictions + edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)" + edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)" + + # Extended drain rules + edge4way space/a ed/a 5000 ~(space)/a 0 0 "LDNFET/LDPFET width < %d (denmos/depmos.2)" + edge4way (*mvndiff)/a mvnfet 1055 ~(ed)/a 0 0 "LDNFET length < %d (denmos.1)" + edge4way (*mvnsd)/a ed/a 2510 ~(*mvndiff)/a 0 0 \ + "LDNFET drain to source < %d (denmos.6 + denmos.3)" + edge4way (*mvpdiff)/a mvpfet 1050 ~(ed)/a 0 0 "LDPFET length < %d (depmos.1)" + edge4way (*mvpsd)/a ed/a 2110 ~(*mvpdiff)/a 0 0 \ + "LDPFET drain to source < %d (depmos.6 + depmos.3)" + + area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)" + area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)" + + angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)" + + variants (full) + cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)" + + # Latchup rules + cifmaxwidth ptap_missing 0 bend_illegal \ + "N-diff distance to P-tap must be < 15.0um (LU.2)" + cifmaxwidth dptap_missing 0 bend_illegal \ + "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)" + cifmaxwidth ntap_missing 0 bend_illegal \ + "P-diff distance to N-tap must be < 15.0um (LU.3)" + + variants (fast),(full) + +#----------------------------- +# POLY +#----------------------------- + + width allpoly,polyfill 150 "poly width < %d (poly.1a)" + spacing allpoly,polyfill allpoly,polyfill 210 touching_ok "poly spacing < %d (poly.2)" + + spacing allpolynonfet,polyfill \ + *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \ + 75 corner_ok allfets \ + "poly spacing to Diffusion < %d (poly.4)" + spacing npres *nsd 480 touching_illegal \ + "poly resistor spacing to N-tap < %d (poly.9)" + overhang *ndiff,rndiff nfet,scnfet,npd,npass,nsonos 250 "N-Diffusion overhang of nFET < %d (poly.7)" + overhang *mvndiff,mvrndiff mvnfet,mvnnfet,nnfet 250 \ + "N-Diffusion overhang of nFET < %d (poly.7)" + overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)" + overhang *mvpdiff,mvrpdiff mvpfet,mvpfetesd 250 "P-Diffusion overhang of pmos < %d (poly.7)" + overhang *poly allfetsstd,allfetsspecial 130 "poly overhang of transistor < %d (poly.8)" + overhang *poly allfetscore 110 "poly overhang of SRAM core transistor < %d (poly.8)" + rect_only allfets "No bends in transistors (poly.11)" + extend xpc/a xhrpoly,uhrpoly 2160 \ + "poly contact extends poly resistor by < %d (licon.1c + li.5)" + spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 210 touching_illegal \ + "Distance between precision resistors < %d (poly.2)" + spacing xhrpoly,uhrpoly,xpc *poly,allfets,mrp1,rmp 400 touching_illegal \ + "Distance from precision resistor to poly < %d (rpm.7 + rpm.3)" + + variants (fast) + + spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 525 touching_illegal \ + "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)" + spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \ + "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)" + spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 585 touching_illegal \ + "Distance from precision resistor to MV N+ device < %d (rpm.3 + rpm.9 + hvntm.3)" + + # Minimum width requirement means actual spacing from res to ndiff has to be + # constructed from mask rules. These supercede the simpler checks. + + variants (full) + + cifmaxwidth rpm_nsd_check 0 bend_illegal \ + "Distance from precision resistor to N+ diffusion < 0.525um (rpm.3 + rpm.6 + nsd.5a)" + cifmaxwidth rpm_poly_check 0 bend_illegal \ + "Distance from precision resistor to unrelated poly < 0.4um (rpm.3 + rpm.7)" + cifmaxwidth rpm_hvntm_check 0 bend_illegal \ + "Distance from precision resistor to MV N+ device < 0.585um (rpm.3 + rpm.9 + hvntm.3)" + + variants (fast),(full) + + angles allpoly,polyfill 90 "Only 90 degree angles permitted on poly (x.2)" + +#-------------------------------------------------------------------- +# HVTP +#-------------------------------------------------------------------- + + spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,mvpfetesd,pfetlvt,pfetmvt \ + 360 touching_illegal \ + "Min. spacing between pFET and HVTP < %d (hvtp.4)" + + spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \ + "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)" + +#-------------------------------------------------------------------- +# LVTN +#-------------------------------------------------------------------- + + spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \ + allfetsnolvt 360 touching_illegal \ + "Min. spacing between FET and LVTN < %d (lvtn.3a)" + + spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \ + 740 touching_illegal \ + "Min. spacing between LVTN and HVTP < %d (lvtn.9)" + + # Spacing across S/D direction requires edge rule + edge4way allfetsnolvt allactivenonfet 415 \ + ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \ + "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)" + +#-------------------------------------------------------------------- +# HVNTM +#-------------------------------------------------------------------- + +variants (full) + # This requires extra spacing of hvndiff if a ptap is in between + cifwidth hvntm_generate 700 "Width of HVNTM < %d (hvntm.1)" + cifspacing hvntm_generate hvntm_generate 700 touching_ok \ + "HVNTM spacing < %d (hvntm.2)" +variants * + +#-------------------------------------------------------------------- +# NPC (Nitride poly Cut) +#-------------------------------------------------------------------- + +# Layer NPC is defined automatically around poly contacts (grow 0.1um) + +#-------------------------------------------------------------------- +# CONT (LICON, contact between poly/diff and LI) +#-------------------------------------------------------------------- + + width ndc/li 170 "N-diffusion contact width < %d (licon.1)" + width nsc/li 170 "N-tap contact width < %d (licon.1)" + width pdc/li 170 "P-diffusion contact width < %d (licon.1)" + width psc/li 170 "P-tap contact width < %d (licon.1)" + width ndic/li 170 "N-diode contact width < %d (licon.1)" + width pdic/li 170 "P-diode contact width < %d (licon.1)" + width pc/li 170 "poly contact width < %d (licon.1)" + + width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)" + area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)" + area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)" + + width mvndc/li 170 "N-diffusion contact width < %d (licon.1)" + width mvnsc/li 170 "N-tap contact width < %d (licon.1)" + width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)" + width mvpsc/li 170 "P-tap contact width < %d (licon.1)" + width mvndic/li 170 "N-diode contact width < %d (licon.1)" + width mvpdic/li 170 "P-diode contact width < %d (licon.1)" + + spacing allpdiffcont allndiffcont 170 touching_illegal \ + "Diffusion contact spacing < %d (licon.2)" + spacing allndiffcont allndiffcont 170 touching_ok \ + "Diffusion contact spacing < %d (licon.2)" + spacing allpdiffcont allpdiffcont 170 touching_ok \ + "Diffusion contact spacing < %d (licon.2)" + spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)" + + spacing pc alldiff 190 touching_illegal \ + "poly contact spacing to diffusion < %d (licon.14)" + spacing pc allpdifflv,allpdiffmv 235 touching_illegal \ + "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)" + + spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \ + "Diffusion contact to gate < %d (licon.11)" + spacing ndc,pdc scnfet,scpfet,scpfethvt 50 touching_illegal \ + "Diffusion contact to standard cell gate < %d (licon.11)" + spacing ndc,pdc npd,npass,ppu 40 touching_illegal \ + "Diffusion contact to SRAM gate < %d (licon.11)" + spacing ndc,pdc nsonos 75 touching_illegal \ + "Diffusion contact to SONOS gate < %d (licon.11)" + spacing mvndc,mvpdc mvnfet,mvnfetesd,mvnnfet,nnfet,mvpfet,mvpfetesd 55 touching_illegal \ + "Diffusion contact to gate < %d (licon.11)" + spacing nsc varactor,varhvt 250 touching_illegal \ + "Diffusion contact to varactor gate < %d (licon.10)" + spacing mvnsc mvvar 250 touching_illegal \ + "Diffusion contact to varactor gate < %d (licon.10)" + + surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 40 absence_illegal \ + "N-diffusion overlap of N-diffusion contact < %d (licon.5a)" + surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \ + 40 absence_illegal \ + "P-diffusion overlap of P-diffusion contact < %d (licon.5a)" + surround ndic/a *ndi 40 absence_illegal \ + "N-diode overlap of N-diode contact < %d (licon.5a)" + surround pdic/a *pdi 40 absence_illegal \ + "P-diode overlap of N-diode contact < %d (licon.5a)" + + spacing psc/a allnactivenontap 60 touching_illegal \ + "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)" + spacing nsc/a allpactivenontap 60 touching_illegal \ + "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)" + + surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt,rnd 60 directional \ + "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)" + surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt,rpd \ + 60 directional \ + "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)" + surround ndic/a *ndi 60 directional \ + "N-diode overlap of N-diode contact < %d in one direction (licon.5c)" + surround pdic/a *pdi 60 directional \ + "P-diode overlap of N-diode contact < %d in one direction (licon.5c)" + + surround nsc/a *nsd,pdiff,corenvar 120 directional \ + "N-tap overlap of N-tap contact < %d in one direction (licon.7)" + surround psc/a *psd,ndiff,corepvar 120 directional \ + "P-tap overlap of P-tap contact < %d in one direction (licon.7)" + + surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 40 absence_illegal \ + "N-diffusion overlap of N-diffusion contact < %d (licon.5a)" + surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 40 absence_illegal \ + "P-diffusion overlap of P-diffusion contact < %d (licon.5a)" + surround mvndic/a *mvndi 40 absence_illegal \ + "N-diode overlap of N-diode contact < %d (licon.5a)" + surround mvpdic/a *mvpdi 40 absence_illegal \ + "P-diode overlap of N-diode contact < %d (licon.5a)" + + spacing mvpsc/a allndiffmvnontap 60 touching_illegal \ + "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)" + spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \ + "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)" + + surround mvndc/a *mvndiff,mvnfet,mvnfetesd,mvrnd 60 directional \ + "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)" + surround mvpdc/a *mvpdiff,mvpfet,mvpfetesd,mvrpd 60 directional \ + "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)" + surround mvndic/a *mvndi 60 directional \ + "N-diode overlap of N-diode contact < %d in one direction (licon.5c)" + surround mvpdic/a *mvpdi 60 directional \ + "P-diode overlap of N-diode contact < %d in one direction (licon.5c)" + + surround mvnsc/a *mvnsd 120 directional \ + "N-tap overlap of N-tap contact < %d in one direction (licon.7)" + surround mvpsc/a *mvpsd 120 directional \ + "P-tap overlap of P-tap contact < %d in one direction (licon.7)" + + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \ + "poly overlap of poly contact < %d (licon.8)" + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \ + "poly overlap of poly contact < %d in one direction (licon.8a)" + + exact_overlap (allcont)/a + +#------------------------------------------------------------- +# LI - Local interconnect layer +#------------------------------------------------------------- + +variants * + + width *li 170 "Local interconnect width < %d (li.1)" + width rli 290 "Local interconnect width < %d (li.7)" + + spacing *locali,rli *locali,rli,*obsli 170 touching_ok \ + "Local interconnect spacing < %d (li.3)" + + # Local interconnect in core (SRAM) cells has more relaxed rules. There are + # no special layers for the contacts in core cells, so they must be included + # in the rule. + width coreli,pc,ndc,nsc,pdc,psc,allli,*obsli 140 \ + "Core local interconnect width < %d (li.c1)" + + spacing coreli,pc,ndc,nsc,pdc,psc,mcon allli,*obsli 140 touching_ok \ + "Core local interconnect spacing < %d (li.c2)" + + surround pc/li *li,coreli 80 directional \ + "Local interconnect overlap of poly contact < %d in one direction (li.5)" + + surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \ + *li,rli,coreli 80 directional \ + "Local interconnect overlap of diffusion contact < %d in one direction (li.5)" + + area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)" + + angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)" + angles coreli 45 \ + "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)" + +#------------------------------------------------------------- +# MCON - Contact between local interconnect and metal1 +#------------------------------------------------------------- + + width mcon/m1 170 "mcon.width < %d (mcon.1)" + spacing mcon/m1 mcon/m1,obsmcon/m1 190 touching_ok "mcon.spacing < %d (mcon.2)" + + exact_overlap mcon/li + +#------------------------------------------------------------- +# METAL1 - +#------------------------------------------------------------- + + width *m1,rm1 140 "Metal1 width < %d (met1.1)" + spacing allm1,m1fill allm1,*obsm1,m1fill 140 touching_ok "Metal1 spacing < %d (met1.2)" + area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)" + + surround mcon/m1 *met1 30 absence_illegal \ + "Metal1 overlap of local interconnect contact < %d (met1.4)" + surround mcon/m1 *met1 60 directional \ + "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)" + + angles allm1,m1fill 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)" + +variants (fast),(full) + widespacing allm1 3005 allm1,*obsm1,m1fill 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)" + widespacing *obsm1 3005 allm1 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)" + +variants (full) + cifmaxwidth m1_hole_empty 0 bend_illegal \ + "Min area of metal1 holes > 0.14um^2 (met1.7)" + + cifspacing m1_large_halo m1_large_halo 280 touching_ok \ + "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)" +variants * + +#-------------------------------------------------- +# VIA1 +#-------------------------------------------------- + + width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)" + spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)" + surround v1/m1 *m1,rm1 30 directional \ + "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)" + surround v1/m2 *m2,rm2 30 directional \ + "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)" + + exact_overlap v1/m1 + +#-------------------------------------------------- +# ReRAM +#-------------------------------------------------- + + width reram 260 "ReRAM width < %d (rr1.1)" + spacing reram reram 55 touching_illegal "ReRAM spacing < %d (rr1.2)" + surround reram *m1,rm1 30 directional \ + "Metal1 overlap of ReRAM < %d in one direction (via.5a - via.4a)" + surround reram *m2,rm2 30 directional \ + "Metal2 overlap of ReRAM < %d in one direction (met2.5 - met2.4)" + + no_overlap reram v1 + + +#-------------------------------------------------- +# METAL2 - +#-------------------------------------------------- + + width allm2,m2fill 140 "Metal2 width < %d (met2.1)" + spacing allm2 allm2,obsm2,m2fill 140 touching_ok "Metal2 spacing < %d (met2.2)" + area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)" + + angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)" + +variants (fast),(full) + widespacing allm2 3005 allm2,obsm2,m2fill 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)" + widespacing obsm2 3005 allm2 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)" + +variants (full) + cifmaxwidth m2_hole_empty 0 bend_illegal \ + "Min area of metal2 holes > 0.14um^2 (met2.7)" + + cifspacing m2_large_halo m2_large_halo 280 touching_ok \ + "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)" +variants * + +#-------------------------------------------------- +# VIA2 +#-------------------------------------------------- + + width v2/m2 280 "via2 width < %d (via2.1a + 2 * via2.4)" + + spacing v2 v2 120 touching_ok "via2 spacing < %d (via2.2 - 2 * via2.4)" + + surround v2/m2 *m2,rm2 45 directional \ + "Metal2 overlap of via2 < %d in one direction (via2.4a - via2.4)" + surround v2/m3 *m3,rm3 25 absence_illegal "Metal3 overlap of via2 < %d (met3.4)" + + exact_overlap v2/m2 + +#-------------------------------------------------- +# METAL3 - +#-------------------------------------------------- + + width allm3,m3fill 300 "Metal3 width < %d (met3.1)" + spacing allm3 allm3,obsm3,m3fill 300 touching_ok "Metal3 spacing < %d (met3.2)" + area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)" + + angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)" + +variants (fast),(full) + widespacing allm3,m3fill 3005 allm3,obsm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)" + widespacing obsm3 3005 allm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)" +variants (full) + cifspacing m3_large_halo m3_large_halo 400 touching_ok \ + "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)" +variants * + + +#-------------------------------------------------- +# VIA3 - Requires METAL5 Module +#-------------------------------------------------- + + width v3/m3 320 "via3 width < %d (via3.1 + 2 * via3.4)" + spacing v3 v3 80 touching_ok "via3 spacing < %d (via3.2 - 2 * via3.4)" + surround v3/m3 *m3,rm3 30 directional \ + "Metal3 overlap of via3 in one direction < %d (via3.5 - via3.4)" + surround v3/m4 *m4,rm4 5 absence_illegal \ + "Metal4 overlap of via3 < %d (met4.3 - via3.4)" + + exact_overlap v3/m3 + +#----------------------------- +# METAL4 - METAL4 Module +#----------------------------- + +variants * + + width allm4,m4fill 300 "Metal4 width < %d (met4.1)" + spacing allm4 allm4,obsm4,m4fill 300 touching_ok "Metal4 spacing < %d (met4.2)" + area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)" + + angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)" + +variants (fast),(full) + widespacing allm4,m4fill 3005 allm4,obsm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)" + widespacing obsm4 3005 allm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)" +variants (full) + cifspacing m4_large_halo m4_large_halo 400 touching_ok \ + "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)" +variants * + +#-------------------------------------------------- +# VIA4 - Requires METAL5 Module +#-------------------------------------------------- + + width v4/m4 1180 "via4 width < %d (via4.1 + 2 * via4.4)" + spacing v4 v4 420 touching_ok "via4 spacing < %d (via4.2 - 2 * via4.4)" + surround v4/m5 *m5,rm5 120 absence_illegal \ + "Metal5 overlap of via4 < %d (met5.3 - via4.4)" + + exact_overlap v4/m4 + +#----------------------------- +# METAL5 - METAL5 Module +#----------------------------- + + width allm5,m5fill 1600 "Metal5 width < %d (met5.1)" + spacing allm5 allm5,obsm5,m5fill 1600 touching_ok "Metal5 spacing < %d (met5.2)" + area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)" + + angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)" + + + +variants (full) + + width metrdl 10000 "RDL width < %d (rdl.1)" + spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)" + surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)" + spacing glass metrdl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)" + +variants (fast),(full) + + +#-------------------------------------------------- +# NMOS, PMOS +#-------------------------------------------------- + + edge4way *poly allfetsstd 420 allfets 0 0 \ + "Transistor width < %d (diff/tap.2)" + edge4way *poly allfetsspecial 360 allfets 0 0 \ + "Transistor in standard cell width < %d (diff/tap.2)" + edge4way *poly npass,npd,nsonos 210 allfets 0 0 \ + "N-Transistor in SRAM core width < %d (diff/tap.2)" + edge4way *poly ppu 140 allfets 0 0 \ + "P-Transistor in SRAM core width < %d (diff/tap.2)" + + # Except: Note that standard cells allow transistor width minimum 0.36um + width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)" + + spacing allpolynonfet,polyfill *nsd 55 corner_ok var,varhvt,corenvar \ + "poly spacing to diffusion tap < %d (poly.5)" + spacing allpolynonfet,polyfill *psd 55 corner_ok corepvar \ + "poly spacing to diffusion tap < %d (poly.5)" + spacing allpolynonfet,polyfill *mvnsd 55 corner_ok mvvar \ + "poly spacing to diffusion tap < %d (poly.5)" + spacing allpolynonfet,polyfill *mvpsd 55 touching_illegal \ + "poly spacing to diffusion tap < %d (poly.5)" + + edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \ + "Butting P-tap spacing to NMOS gate < %d (poly.6)" + edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \ + "Butting N-tap spacing to PMOS gate < %d (poly.6)" + edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnfetesd,mvnnfet,nnfet)/a *mvpsd 300 \ + "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)" + edge4way *mvnsd *mvpdiff 300 ~(mvpfet,mvpfetesd)/a *mvnsd 300 \ + "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)" + + # No LV FETs in HV diff + spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \ + "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)" + + spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \ + "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)" + + # No HV FETs in LV diff + spacing mvpfet,mvpfetesd,*mvpdiff *pdiff 360 touching_illegal \ + "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)" + + spacing mvnfet,mvnfetesd,mvvaractor,*mvndiff *ndiff 360 touching_illegal \ + "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)" + + # Minimum length of MV FETs. Note that this is larger than the minimum + # width (0.29um), so an edge rule is required + + edge4way mvndiff mvnfet,mvnfetesd 500 mvnfet,mvnfetesd 0 0 \ + "MV NMOS minimum length < %d (poly.13)" + + edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \ + "MV Varactor minimum length < %d (poly.13)" + + edge4way mvpdiff mvpfet,mvpfetesd 500 mvpfet,mvpfetesd 0 0 \ + "MV PMOS minimum length < %d (poly.13)" + +#-------------------------------------------------- +# mrp1 (N+ poly resistor) +#-------------------------------------------------- + + width mrp1 330 "mrp1 resistor width < %d (poly.3)" + +#-------------------------------------------------- +# xhrpoly (P+ poly resistor) +# uhrpoly (P+ poly resistor, 2kOhm/sq) +#-------------------------------------------------- + + # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27. + width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)" + width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)" + + spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \ + "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)" + + spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing mrp1 *poly 480 touching_ok \ + "Poly resistor spacing to poly < %d (poly.9)" + + spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \ + "Poly resistor spacing to diffusion < %d (poly.9)" + +#------------------------------------ +# nsonos +#------------------------------------ + +variants (full) + cifmaxwidth bbox_missing 0 bend_illegal \ + "SONOS transistor must be in cell with abutment box (tunm.8)" +variants (fast),(full) + +#------------------------------------ +# MOS Varactor device rules +#------------------------------------ + + overhang *nsd var,varhvt 250 \ + "N-Tap overhang of Varactor < %d (var.4)" + + overhang *mvnsd mvvar 250 \ + "N-Tap overhang of Varactor < %d (var.4)" + + width var,varhvt,mvvar 180 "Varactor length < %d (var.1)" + extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)" + +variants (full) + cifmaxwidth var_poly_no_nwell 0 bend_illegal \ + "N-well overlap of varactor poly < 0.15um (varac.5)" + + cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \ + "Varactor N-well must not contain P+ diffusion (varac.7)" +variants (fast),(full) + +#----------------------------------------------------------- +# MiM CAP (CAPM) - +#----------------------------------------------------------- + + width *mimcap 1000 "MiM cap width < %d (capm.1)" + spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)" + spacing *mimcap via3/m3 80 touching_illegal \ + "MiM cap spacing to via3 < %d (capm.5 - via3.4)" + surround *mimcc *mimcap 80 absence_illegal \ + "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)" + rect_only *mimcap "MiM cap must be rectangular (capm.7) + + surround *mimcap *metal3/m3 140 absence_illegal \ + "Metal3 must surround MiM cap by %d (capm.3)" + spacing via2 *mimcap 100 touching_illegal \ + "MiM cap spacing to via2 < %d (capm.8 - via2.4)" + spacing *mimcap *metal3/m3 500 surround_ok \ + "MiM cap spacing to unrelated metal3 < %d (capm.11)" + +variants (full) + cifspacing mim_bottom mim_bottom 1200 touching_ok \ + "MiM cap bottom plate spacing < %d (capm.2b)" +variants (fast),(full) + + # MiM cap contact rules (VIA3) + + width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)" + spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)" + surround mimcc/m4 *m4 5 directional \ + "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)" + exact_overlap mimcc/c1 + + width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)" + spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)" + spacing *mimcap2 via4/m4 10 touching_illegal \ + "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)" + surround *mim2cc *mimcap2 10 absence_illegal \ + "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)" + rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7) + + surround *mimcap2 *metal4/m4 140 absence_illegal \ + "Metal4 must surround MiM2 cap by %d (cap2m.3)" + spacing via3 *mimcap2 80 touching_illegal \ + "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)" + spacing *mimcap2 *metal4/m4 500 surround_ok \ + "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)" + +variants (full) + cifmaxwidth mim2_contact_overlap 0 bend_illegal \ + "MiM2 cap contact must not cross MiM cap contact (cap2m.8)" + + cifspacing mim2_bottom mim2_bottom 1200 touching_ok \ + "MiM2 cap bottom plate spacing < %d (cap2m.2b)" +variants (fast),(full) + + # MiM cap contact rules (VIA4) + + width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)" + spacing mim2cc mim2cc 420 touching_ok \ + "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)" + surround mim2cc/m5 *m5 120 absence_illegal \ + "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)" + exact_overlap mim2cc/c2 + + +#---------------------------- +# HVNTM +#---------------------------- +variants (full) + cifspacing hvntm_generate hvntm_generate 700 touching_ok \ + "HVNTM spacing < %d (hvntm.2)" +variants (fast),(full) + +#---------------------------- +# End DRC style +#---------------------------- + +end + +#---------------------------- +# LEF format definitions +#---------------------------- + +lef + + masterslice pwell pwell PWELL substrate + masterslice nwell nwell NWELL + + routing li li1 LI1 LI li + + routing m1 met1 MET1 m1 + routing m2 met2 MET2 m2 + routing m3 met3 MET3 m3 + routing m4 met4 MET4 m4 + routing m5 met5 MET5 m5 + routing mrdl met6 MET6 m6 MRDL METRDL + + cut mcon mcon MCON Mcon + cut m2c via via1 VIA VIA1 cont2 via12 + cut m3c via2 VIA2 cont3 via23 + cut via3 via3 VIA3 cont4 via34 + cut via4 via4 VIA4 cont5 via45 + + obs obsli li1 + obs obsm1 met1 + obs obsm2 met2 + obs obsm3 met3 + + obs obsm4 met4 + obs obsm5 met5 + obs obsmrdl met6 + + # NOTE: obsmcon only used with li1, not obsli. + obs obsmcon mcon + + # Vias on obstruction layers should be ignored, so cast to obstruction metal. + obs obsm1 via + obs obsm2 via2 + obs obsm3 via3 + obs obsm4 via4 + +end + +#----------------------------------------------------- +# Device and Parasitic extraction +#----------------------------------------------------- + +extract + style ngspice variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc),(nowell) + cscale 1 + # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all + # dimensions must be in units of microns in the extract file. + # Use extract style "ngspice(si)" to override this and produce + # a file with SI units for length/area. + + variants (),(orig),(hrhc),(lrhc),(hrlc),(lrlc),(nowell) + lambda 1E6 + variants (si) + lambda 1.0 + variants * + + units microns + step 7 + sidehalo 8 + fringeshieldhalo 8 + + # NOTE: MiM cap layers have been purposely put out of order, + # may want to reconsider. + + planeorder dwell 0 + planeorder well 1 + planeorder active 2 + planeorder locali 3 + planeorder metal1 4 + planeorder metal2 5 + planeorder metal3 6 + planeorder metal4 7 + planeorder metal5 8 + planeorder metali 9 + planeorder block 10 + planeorder comment 11 + planeorder cap1 12 + planeorder cap2 13 + + height dnwell -0.1 0.1 + height nwell,pwell 0.0 0.2062 + height alldiff 0.2062 0.12 + height fomfill 0.2062 0.12 + height allpoly 0.3262 0.18 + height polyfill 0.3262 0.18 + height alldiffcont 0.3262 0.61 + height pc 0.5062 0.43 + height allli 0.9361 0.10 + height mcon 1.0361 0.34 + height allm1 1.3761 0.36 + height m1fill 1.3761 0.36 + height v1 1.7361 0.565 + height allm2 2.3011 0.36 + height m2fill 2.3011 0.36 + height v2 2.6611 0.42 + height allm3 3.0811 0.845 + height m3fill 3.0811 0.845 + height mimcap 2.7611 0.2 + height mimcap2 4.0261 0.2 + height mimcc 2.9611 0.12 + height mim2cc 4.2261 0.09 + height v3 3.9261 0.39 + height allm4 4.3161 0.845 + height m4fill 4.3161 0.845 + height v4 5.1611 0.505 + height allm5 5.6661 1.26 + height m5fill 5.6661 1.26 + height mrdlc 6.9261 0.63 + height mrdl 7.5561 3.0 + + # Antenna check parameters + # Note that checks w/diode diffusion are not modeled + model partial + antenna poly sidewall 50 none + antenna allcont surface 3 none + antenna li sidewall 75 0 450 + antenna mcon surface 3 0 18 + antenna m1,m2,m3 sidewall 400 2200 400 + antenna v1 surface 3 0 18 + antenna v2 surface 6 0 36 + antenna m4,m5 sidewall 400 2200 400 + antenna v3,v4 surface 6 0 36 + + tiedown alldiffnonfet + +variants (),(orig),(si),(hrhc),(lrhc),(hrlc),(lrlc) + # for all variants except (nowell) + + substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub + +variants * + +# Resistances are in milliohms per square +# Optional 3rd argument is the corner adjustment fraction +# Device values come from trtc.cor (typical corner) + +variants (),(orig),(si),(nowell) + + resist (pwell,isosub)/well 4400000 + resist (dnwell)/dwell 2200000 + resist (nwell)/well 950000 + resist (rpw)/well 3050000 0.5 + resist (*ndiff,nsd)/active 120000 + resist (*pdiff,*psd)/active 197000 + resist (*mvndiff,mvnsd)/active 114000 + resist (*mvpdiff,*mvpsd)/active 191000 + + resist ndiffres/active 120000 0.5 + resist pdiffres/active 197000 0.5 + resist mvndiffres/active 114000 0.5 + resist mvpdiffres/active 191000 0.5 + resist mrp1/active 48200 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 48200 + resist rmp/active 48200 + + resist (allli)/locali 12800 + resist (allm1)/metal1 125 + resist (allm2)/metal2 125 + resist (allm3)/metal3 47 + resist (allm4)/metal4 47 + resist (allm5)/metal5 29 + resist mrdl/metali 5 + + contact ndc,nsc 185000 + contact ndic,ndilvtc,nndic 185000 + contact pdc,psc 585000 + contact pdic,pdilvtc,pdihvtc 585000 + contact mvndc,mvnsc,mvndic 185000 + contact mvpdc,mvpsc,mvpdic 585000 + contact pc,xpc 152000 + contact mcon 9300 + contact m2c 9000 + contact m3c 3410 + contact mimcc 4500 + contact mim2cc 3410 + contact via3 3410 + contact via4 380 + contact mrdlc 6 + +variants (hrhc),(hrlc) + + # High-end corner resistances + # No corner values available for: substrate, xhrpoly, uhrpoly, RDL + resist (pwell,isosub)/well 4400000 + resist (dnwell)/dwell 2575000 + resist (nwell)/well 1350000 + resist (rpw)/well 3535000 0.5 + resist (*ndiff,nsd)/active 132000 + resist (*pdiff,*psd)/active 228000 + resist (*mvndiff,mvnsd)/active 126000 + resist (*mvpdiff,*mvpsd)/active 228000 + + resist ndiffres/active 132000 0.5 + resist pdiffres/active 228000 0.5 + resist mvndiffres/active 126000 0.5 + resist mvpdiffres/active 228000 0.5 + resist mrp1/active 55800 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 55800 + resist rmp/active 55800 + + resist (allli)/locali 17000 + resist (allm1)/metal1 145 + resist (allm2)/metal2 145 + resist (allm3)/metal3 56 + resist (allm4)/metal4 56 + resist (allm5)/metal5 36 + resist mrdl/metali 5 + + contact ndc,nsc 280000 + contact ndic,ndilvtc,nndic 280000 + contact pdc,psc 840000 + contact pdic,pdilvtc,pdihvtc 840000 + contact mvndc,mvnsc,mvndic 280000 + contact mvpdc,mvpsc,mvpdic 840000 + contact pc,xpc 252000 + contact mcon 23000 + contact m2c 30000 + contact m3c 8000 + contact mimcc 15000 + contact mim2cc 8000 + contact via3 8000 + contact via4 891 + contact mrdlc 6 + +variants (lrhc),(lrlc) + + # Low-end corner resistances + # No corner values available for: substrate, xhrpoly, uhrpoly, RDL + resist (pwell,isosub)/well 4400000 + resist (dnwell)/dwell 1825000 + resist (nwell)/well 550000 + resist (rpw)/well 2565000 0.5 + resist (*ndiff,nsd)/active 108000 + resist (*pdiff,*psd)/active 166000 + resist (*mvndiff,mvnsd)/active 102000 + resist (*mvpdiff,*mvpsd)/active 160000 + + resist ndiffres/active 108000 0.5 + resist pdiffres/active 166000 0.5 + resist mvndiffres/active 102000 0.5 + resist mvpdiffres/active 160000 0.5 + resist mrp1/active 42200 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 42200 + resist rmp/active 42200 + + resist (allli)/locali 10500 + resist (allm1)/metal1 105 + resist (allm2)/metal2 105 + resist (allm3)/metal3 38 + resist (allm4)/metal4 38 + resist (allm5)/metal5 21 + resist mrdl/metali 5 + + contact ndc,nsc 95000 + contact ndic,ndilvtc,nndic 95000 + contact pdc,psc 345000 + contact pdic,pdilvtc,pdihvtc 345000 + contact mvndc,mvnsc,mvndic 95000 + contact mvpdc,mvpsc,mvpdic 345000 + contact pc,xpc 52000 + contact mcon 1600 + contact m2c 4000 + contact m3c 500 + contact mimcc 2000 + contact mim2cc 500 + contact via3 500 + contact via4 12 + contact mrdlc 6 + +variants * + + # These types should not be considered as electrical nodes + resist blocktypes None + resist obstypes None + resist comment None + +#------------------------------------------------------------------------- +# Parasitic capacitance values: Use document (...) +#------------------------------------------------------------------------- +# This uses the new "default" definitions that determine the intervening +# planes from the planeorder stack, take care of the reflexive sideoverlap +# definitions, and generally clean up the section and make it more readable. +# +# Also uses "units microns" statement. All values are taken from the +# document PEX/xRC/cap_models. Fringe capacitance values are approximated. +# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps. +#------------------------------------------------------------------------- +# Remember that device capacitances to substrate are taken care of by the +# models. Thus, active and poly definitions ignore all "fet" types. +# fet types are excluded when computing parasitic capacitance to +# active from layers above them because poly is a shield; fet types are +# included for parasitics from layers above to poly. Resistor types +# should be removed from all parasitic capacitance calculations, or else +# they just create floating caps. Technically, the capacitance probably +# should be split between the two terminals. Unsure of the correct model. +#------------------------------------------------------------------------- + +variants (),(orig),(si) +# Nominal capacitances + +#deep n-well +defaultareacap dnwell dwell 120 + +#p-well +defaultoverlap pwell well dnwell dwell 120 + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well dnwell dwell 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 17 +# defaultareacap allpolynonfet active 106 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 16.0 + defaultareacap *poly active 106.13 + defaultperimeter *poly active 55.27 + defaultoverlap *poly active nwell,pwell well 106.13 + defaultsideoverlap *poly active nwell,pwell well 55.27 + +#locali + defaultsidewall allli locali 25.5 0.14 + defaultareacap allli locali 36.99 + defaultperimeter allli locali 40.70 + defaultoverlap allli locali nwell,pwell well 36.99 + defaultsideoverlap allli locali nwell,pwell well 40.70 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 55.3 + defaultsideoverlap allli locali allactivenonfet active 44.27 + +#locali->poly + defaultoverlap allli locali allpolynonres active 94.16 + defaultsideoverlap allli locali allpolynonres active 51.85 + defaultsideoverlap *poly active allli locali 25.14 + +#metal1 + defaultsidewall allm1 metal1 44 0.25 + defaultareacap allm1 metal1 25.78 + defaultperimeter allm1 metal1 40.57 + defaultoverlap allm1 metal1 nwell,pwell well 25.78 + defaultsideoverlap allm1 metal1 nwell,pwell well 40.57 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 33.6 + defaultsideoverlap allm1 metal1 allactivenonfet active 43.10 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 44.81 + defaultsideoverlap allm1 metal1 allpolynonres active 46.72 + defaultsideoverlap *poly active allm1 metal1 16.69 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 114.20 + defaultsideoverlap allm1 metal1 allli locali 59.50 + defaultsideoverlap allli locali allm1 metal1 34.70 + +#metal2 + defaultsidewall allm2 metal2 50 0.3 + +# For ReRAM, all parasitics account for the additional 0.295um between +# metal1 and metal2 + + defaultareacap allm2 metal2 14.73 + defaultperimeter allm2 metal2 32.92 + defaultoverlap allm2 metal2 nwell,pwell well 14.73 + defaultsideoverlap allm2 metal2 nwell,pwell well 32.92 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 17.87 + defaultsideoverlap allm2 metal2 allactivenonfet active 33.96 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 20.47 + defaultsideoverlap allm2 metal2 allpolynonres active 34.44 + defaultsideoverlap *poly active allm2 metal2 9.33 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 28.80 + defaultsideoverlap allm2 metal2 allli locali 35.49 + defaultsideoverlap allli locali allm2 metal2 16.67 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 63.97 + defaultsideoverlap allm2 metal2 allm1 metal1 32.04 + defaultsideoverlap allm1 metal1 allm2 metal2 23.03 + + +#metal3 + defaultsidewall allm3 metal3 74.0 0.40 + + defaultareacap allm3 metal3 11.19 + defaultperimeter allm3 metal3 37.07 + defaultoverlap allm3 metal3 nwell,pwell well 11.19 + defaultsideoverlap allm3 metal3 nwell,pwell well 37.07 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 11.92 + defaultsideoverlap allm3 metal3 allactive active 37.94 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 14.22 + defaultsideoverlap allm3 metal3 allpolynonres active 38.54 + defaultsideoverlap *poly active allm3 metal3 8.13 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 17.79 + defaultsideoverlap allm3 metal3 allli locali 39.97 + defaultsideoverlap allli locali allm3 metal3 12.90 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 26.96 + defaultsideoverlap allm3 metal3 allm1 metal1 42.79 + defaultsideoverlap allm1 metal1 allm3 metal3 20.83 + + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 86.19 + defaultsideoverlap allm3 metal3 allm2 metal2 69.85 + defaultsideoverlap allm2 metal2 allm3 metal3 44.43 + +#metal4 + defaultsidewall allm4 metal4 94.0 0.57 + defaultareacap allm4 metal4 7.84 + defaultperimeter allm4 metal4 34.17 + defaultoverlap allm4 metal4 nwell,pwell well 7.84 + defaultsideoverlap allm4 metal4 nwell,pwell well 34.17 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 8.21 + defaultsideoverlap allm4 metal4 allactivenonfet active 34.87 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 9.24 + defaultsideoverlap allm4 metal4 allpolynonres active 35.16 + defaultsideoverlap *poly active allm4 metal4 5.86 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 10.62 + defaultsideoverlap allm4 metal4 allli locali 36.14 + defaultsideoverlap allli locali allm4 metal4 9.23 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 13.31 + defaultsideoverlap allm4 metal4 allm1 metal1 37.70 + defaultsideoverlap allm1 metal1 allm4 metal4 14.54 + + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 20.33 + defaultsideoverlap allm4 metal4 allm2 metal2 46.38 + defaultsideoverlap allm2 metal2 allm4 metal4 22.33 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 84.03 + defaultsideoverlap allm4 metal4 allm3 metal3 70.52 + defaultsideoverlap allm3 metal3 allm4 metal4 42.64 + +#metal5 + defaultsidewall allm5 metal5 155 0.5 + defaultareacap allm5 metal5 5.99 + defaultperimeter allm5 metal5 36.83 + defaultoverlap allm5 metal5 nwell,pwell well 5.99 + defaultsideoverlap allm5 metal5 nwell,pwell well 36.83 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 6.21 + defaultsideoverlap allm5 metal5 allactivenonfet active 37.39 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 6.80 + defaultsideoverlap allm5 metal5 allpolynonres active 37.63 + defaultsideoverlap *poly active allm5 metal5 6.12 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 7.52 + defaultsideoverlap allm5 metal5 allli locali 38.53 + defaultsideoverlap allli locali allm5 metal5 7.15 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 8.77 + defaultsideoverlap allm5 metal5 allm1 metal1 39.95 + defaultsideoverlap allm1 metal1 allm5 metal5 11.12 + + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 11.34 + defaultsideoverlap allm5 metal5 allm2 metal2 45.59 + defaultsideoverlap allm2 metal2 allm5 metal5 15.69 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 19.63 + defaultsideoverlap allm5 metal5 allm3 metal3 54.15 + defaultsideoverlap allm3 metal3 allm5 metal5 27.84 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 68.33 + defaultsideoverlap allm5 metal5 allm4 metal4 82.82 + defaultsideoverlap allm4 metal4 allm5 metal5 46.98 + +#------------------------------------------------------------------------- +# Parasitic capacitance values for minimum corner +#------------------------------------------------------------------------- + +variants (hrlc),(lrlc) +# Minimum corner capacitances + +#deep n-well +defaultareacap dnwell dwell 120 + +#p-well +defaultoverlap pwell well dnwell dwell 120 + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well dnwell dwell 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 80.4 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 17.0 0.21 + defaultareacap *poly active 80.4 + defaultperimeter *poly active 48.83 + defaultoverlap *poly active nwell,pwell well 80.4 + defaultsideoverlap *poly active nwell,pwell well 48.83 + +#locali + defaultsidewall allli locali 26.7 0.17 + defaultareacap allli locali 29.3 + defaultperimeter allli locali 35.69 + defaultoverlap allli locali nwell,pwell well 29.3 + defaultsideoverlap allli locali nwell,pwell well 35.69 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 45.3 + defaultsideoverlap allli locali allactivenonfet active 39.59 + +#locali->poly + defaultoverlap allli locali allpolynonres active 64.5 + defaultsideoverlap allli locali allpolynonres active 43.75 + defaultsideoverlap *poly active allli locali 21.21 + +#metal1 + defaultsidewall allm1 metal1 35.6 0.14 + defaultareacap allm1 metal1 20.2 + defaultperimeter allm1 metal1 34.41 + defaultoverlap allm1 metal1 nwell,pwell well 20.2 + defaultsideoverlap allm1 metal1 nwell,pwell well 34.41 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 26.7 + defaultsideoverlap allm1 metal1 allactivenonfet active 37.22 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 32.3 + defaultsideoverlap allm1 metal1 allpolynonres active 40.34 + defaultsideoverlap *poly active allm1 metal1 14.41 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 77.2 + defaultsideoverlap allm1 metal1 allli locali 49.46 + defaultsideoverlap allli locali allm1 metal1 28.84 + +#metal2 + defaultsidewall allm2 metal2 37.61 0.14 + +# For ReRAM, all parasitics account for the additional 0.295um between +# metal1 and metal2 + + defaultareacap allm2 metal2 12.52 + defaultperimeter allm2 metal2 27.90 + defaultoverlap allm2 metal2 nwell,pwell well 12.52 + defaultsideoverlap allm2 metal2 nwell,pwell well 27.90 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 13.60 + defaultsideoverlap allm2 metal2 allactivenonfet active 29.35 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 17.11 + defaultsideoverlap allm2 metal2 allpolynonres active 28.80 + defaultsideoverlap *poly active allm2 metal2 7.52 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 24.68 + defaultsideoverlap allm2 metal2 allli locali 30.42 + defaultsideoverlap allli locali allm2 metal2 14.29 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 51.37 + defaultsideoverlap allm2 metal2 allm1 metal1 25.73 + defaultsideoverlap allm1 metal1 allm2 metal2 18.50 + + +#metal3 + defaultsidewall allm3 metal3 52.0 0.30 + + defaultareacap allm3 metal3 9.84 + defaultperimeter allm3 metal3 32.60 + defaultoverlap allm3 metal3 nwell,pwell well 9.84 + defaultsideoverlap allm3 metal3 nwell,pwell well 32.60 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 10.60 + defaultsideoverlap allm3 metal3 allactive active 33.73 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 12.51 + defaultsideoverlap allm3 metal3 allpolynonres active 33.89 + defaultsideoverlap *poly active allm3 metal3 7.15 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 15.90 + defaultsideoverlap allm3 metal3 allli locali 35.72 + defaultsideoverlap allli locali allm3 metal3 11.53 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 24.01 + defaultsideoverlap allm3 metal3 allm1 metal1 38.11 + defaultsideoverlap allm1 metal1 allm3 metal3 18.55 + + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 59.5 + defaultsideoverlap allm3 metal3 allm2 metal2 61.18 + defaultsideoverlap allm2 metal2 allm3 metal3 38.92 + +#metal4 + defaultsidewall allm4 metal4 53.7 0.30 + defaultareacap allm4 metal4 6.92 + defaultperimeter allm4 metal4 30.18 + defaultoverlap allm4 metal4 nwell,pwell well 6.92 + defaultsideoverlap allm4 metal4 nwell,pwell well 30.18 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 7.33 + defaultsideoverlap allm4 metal4 allactivenonfet active 30.88 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 8.14 + defaultsideoverlap allm4 metal4 allpolynonres active 30.99 + defaultsideoverlap *poly active allm4 metal4 5.17 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 9.49 + defaultsideoverlap allm4 metal4 allli locali 32.30 + defaultsideoverlap allli locali allm4 metal4 8.25 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 11.81 + defaultsideoverlap allm4 metal4 allm1 metal1 33.92 + defaultsideoverlap allm1 metal1 allm4 metal4 13.08 + + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 17.8 + defaultsideoverlap allm4 metal4 allm2 metal2 42.08 + defaultsideoverlap allm2 metal2 allm4 metal4 20.26 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 57.6 + defaultsideoverlap allm4 metal4 allm3 metal3 59.42 + defaultsideoverlap allm3 metal3 allm4 metal4 35.93 + +#metal5 + defaultsidewall allm5 metal5 81.5 1.6 + defaultareacap allm5 metal5 5.34 + defaultperimeter allm5 metal5 32.85 + defaultoverlap allm5 metal5 nwell,pwell well 5.34 + defaultsideoverlap allm5 metal5 nwell,pwell well 32.85 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 5.54 + defaultsideoverlap allm5 metal5 allactivenonfet active 33.48 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 6.06 + defaultsideoverlap allm5 metal5 allpolynonres active 33.55 + defaultsideoverlap *poly active allm5 metal5 5.46 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 6.80 + defaultsideoverlap allm5 metal5 allli locali 34.87 + defaultsideoverlap allli locali allm5 metal5 6.47 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 7.98 + defaultsideoverlap allm5 metal5 allm1 metal1 36.36 + defaultsideoverlap allm1 metal1 allm5 metal5 10.12 + + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 10.1 + defaultsideoverlap allm5 metal5 allm2 metal2 41.75 + defaultsideoverlap allm2 metal2 allm5 metal5 14.37 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 16.7 + defaultsideoverlap allm5 metal5 allm3 metal3 48.75 + defaultsideoverlap allm3 metal3 allm5 metal5 25.06 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 48.7 + defaultsideoverlap allm5 metal5 allm4 metal4 70.26 + defaultsideoverlap allm4 metal4 allm5 metal5 39.86 + +#------------------------------------------------------------------------- +# Parasitic capacitance values for maximum corner +#------------------------------------------------------------------------- + +variants (hrhc),(lrhc) +# Maximum corner capacitances + +#deep n-well +defaultareacap dnwell dwell 120 + +#p-well +defaultoverlap pwell well dnwell dwell 120 + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well dnwell dwell 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 106 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 17.0 0.21 + defaultareacap *poly active 155.0 + defaultperimeter *poly active 64.82 + defaultoverlap *poly active nwell,pwell well 155.0 + defaultsideoverlap *poly active nwell,pwell well 64.82 + +#locali + defaultsidewall allli locali 28.7 0.17 + defaultareacap allli locali 49.7 + defaultperimeter allli locali 47.02 + defaultoverlap allli locali nwell,pwell well 49.7 + defaultsideoverlap allli locali nwell,pwell well 47.02 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 70.9 + defaultsideoverlap allli locali allactivenonfet active 49.94 + +#locali->poly + defaultoverlap allli locali allpolynonres active 174.0 + defaultsideoverlap allli locali allpolynonres active 66.60 + defaultsideoverlap *poly active allli locali 32.29 + +#metal1 + defaultsidewall allm1 metal1 37.6 0.14 + defaultareacap allm1 metal1 35.7 + defaultperimeter allm1 metal1 49.59 + defaultoverlap allm1 metal1 nwell,pwell well 35.7 + defaultsideoverlap allm1 metal1 nwell,pwell well 49.59 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 45.4 + defaultsideoverlap allm1 metal1 allactivenonfet active 51.17 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 73.2 + defaultsideoverlap allm1 metal1 allpolynonres active 59.78 + defaultsideoverlap *poly active allm1 metal1 21.36 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 215.0 + defaultsideoverlap allm1 metal1 allli locali 80.12 + defaultsideoverlap allli locali allm1 metal1 46.73 + +#metal2 + defaultsidewall allm2 metal2 40.2 0.14 + +# For ReRAM, all parasitics account for the additional 0.295um between +# metal1 and metal2 + + defaultareacap allm2 metal2 20.49 + defaultperimeter allm2 metal2 40.13 + defaultoverlap allm2 metal2 nwell,pwell well 20.49 + defaultsideoverlap allm2 metal2 nwell,pwell well 40.13 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 23.52 + defaultsideoverlap allm2 metal2 allactivenonfet active 40.77 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 29.66 + defaultsideoverlap allm2 metal2 allpolynonres active 42.87 + defaultsideoverlap *poly active allm2 metal2 11.20 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 40.10 + defaultsideoverlap allm2 metal2 allli locali 42.61 + defaultsideoverlap allli locali allm2 metal2 20.01 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 149.6 + defaultsideoverlap allm2 metal2 allm1 metal1 48.92 + defaultsideoverlap allm1 metal1 allm2 metal2 35.16 + + +#metal3 + defaultsidewall allm3 metal3 60.6 0.30 + + defaultareacap allm3 metal3 14.74 + defaultperimeter allm3 metal3 42.85 + defaultoverlap allm3 metal3 nwell,pwell well 14.74 + defaultsideoverlap allm3 metal3 nwell,pwell well 42.85 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 16.24 + defaultsideoverlap allm3 metal3 allactive active 43.24 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 18.86 + defaultsideoverlap allm3 metal3 allpolynonres active 44.66 + defaultsideoverlap *poly active allm3 metal3 9.42 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 22.51 + defaultsideoverlap allm3 metal3 allli locali 45.60 + defaultsideoverlap allli locali allm3 metal3 14.72 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 35.29 + defaultsideoverlap allm3 metal3 allm1 metal1 49.09 + defaultsideoverlap allm1 metal1 allm3 metal3 23.90 + + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 131.0 + defaultsideoverlap allm3 metal3 allm2 metal2 82.67 + defaultsideoverlap allm2 metal2 allm3 metal3 52.59 + +#metal4 + defaultsidewall allm4 metal4 65.4 0.30 + defaultareacap allm4 metal4 9.97 + defaultperimeter allm4 metal4 39.49 + defaultoverlap allm4 metal4 nwell,pwell well 9.97 + defaultsideoverlap allm4 metal4 nwell,pwell well 39.49 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 10.58 + defaultsideoverlap allm4 metal4 allactivenonfet active 39.91 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 11.63 + defaultsideoverlap allm4 metal4 allpolynonres active 40.58 + defaultsideoverlap *poly active allm4 metal4 6.76 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 13.01 + defaultsideoverlap allm4 metal4 allli locali 41.04 + defaultsideoverlap allli locali allm4 metal4 10.48 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 16.39 + defaultsideoverlap allm4 metal4 allm1 metal1 42.58 + defaultsideoverlap allm1 metal1 allm4 metal4 16.42 + + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 25.2 + defaultsideoverlap allm4 metal4 allm2 metal2 51.98 + defaultsideoverlap allm2 metal2 allm4 metal4 25.03 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 191.0 + defaultsideoverlap allm4 metal4 allm3 metal3 92.12 + defaultsideoverlap allm3 metal3 allm4 metal4 55.70 + +#metal5 + defaultsidewall allm5 metal5 118.7 1.6 + defaultareacap allm5 metal5 7.36 + defaultperimeter allm5 metal5 42.58 + defaultoverlap allm5 metal5 nwell,pwell well 7.36 + defaultsideoverlap allm5 metal5 nwell,pwell well 42.58 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 7.70 + defaultsideoverlap allm5 metal5 allactivenonfet active 43.01 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 8.25 + defaultsideoverlap allm5 metal5 allpolynonres active 43.67 + defaultsideoverlap *poly active allm5 metal5 7.10 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 8.88 + defaultsideoverlap allm5 metal5 allli locali 44.08 + defaultsideoverlap allli locali allm5 metal5 8.18 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 10.36 + defaultsideoverlap allm5 metal5 allm1 metal1 45.73 + defaultsideoverlap allm1 metal1 allm5 metal5 12.73 + + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 13.3 + defaultsideoverlap allm5 metal5 allm2 metal2 51.69 + defaultsideoverlap allm2 metal2 allm5 metal5 17.79 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 24.6 + defaultsideoverlap allm5 metal5 allm3 metal3 63.24 + defaultsideoverlap allm3 metal3 allm5 metal5 32.51 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 115.0 + defaultsideoverlap allm5 metal5 allm4 metal4 109.69 + defaultsideoverlap allm4 metal4 allm5 metal5 62.22 + +#--------------------------------------------------------- + +variants * + + +# Devices: Base models (not subcircuit wrappers) + +variants (),(si),(hrhc),(lrhc),(hrlc),(lrlc) + + device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_latch ppu \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error w>=0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_01v8_hvt scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres nwell error w<0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + + device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error \ + w>=0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_01v8 scnfet \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error \ + w<0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *srampvar pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_pass npass \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \ + *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device subcircuit sky130_fd_pr__cap_var_lvt varactor \ + *nndiff pwell,space/w error l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt \ + *nndiff pwell,space/w error l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor \ + *mvnndiff pwell,space/w error l=l w=w + + # Bipolars + device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a1=area + device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \ + error a1>0.99 a1<1.01 + device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \ + error a1>1.99 a1<2.01 + device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a1=area + device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \ + pwell,space/w a1>0.45 a1<0.47 + device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \ + pwell,space/w a1>11.55 a1<11.57 + device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a1=area + device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \ + dnwell space/w error a1>0.99 a1<1.01 + + # Ignore the extended-drain FET geometry that forms part of the high-voltage + # bipolar devices. + device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp + device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp + + # Extended drain devices (must appear before the regular devices) + device msubcircuit sky130_fd_pr__nfet_g5v0d16v0 mvnfet *mvndiff \ + extdrain,*mvnsd pwell,space/w error l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_g5v0d16v0 mvpfet *mvpdiff \ + extdrain,*mvpsd nwell error l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd + device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd + device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ + pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd + + device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \ + *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w \ + a1=as p1=ps a2=ad p2=pd + + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 + device ndiode sky130_fd_pr__model__parasitic__diode_ps2dn \ + photo pwell,space/w error a=area + + device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \ + xpc nwell,pwell,space/w error l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \ + xpc nwell,pwell,space/w error w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \ + xpc nwell,pwell,space/w error w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \ + xpc nwell,pwell,space/w error w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \ + xpc nwell,pwell,space/w error w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \ + xpc nwell,pwell,space/w error w>5.72 w<5.74 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \ + xpc nwell,pwell,space/w error l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \ + xpc nwell,pwell,space/w error w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \ + xpc nwell,pwell,space/w error w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \ + xpc nwell,pwell,space/w error w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \ + xpc nwell,pwell,space/w error w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \ + xpc nwell,pwell,space/w error w>5.72 w<5.74 l=l+0.16 + + device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \ + *ndiff pwell,space/w error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \ + *pdiff nwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_iso_pw rpw \ + pwell dnwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \ + *mvndiff pwell,space/w error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \ + *mvpdiff nwell error l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + + # NOTE: SkyWater diode models have bizarre units requiring bizarre scaling + device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area*1E12 p=pj*1E6 + + device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area*1E12 p=pj*1E6 + + device csubcircuit sky130_fd_pr_reram__reram_cell reram m1 a=area_ox + + device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l + device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l + +variants (nowell) + + device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_latch ppu \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \ + *pdiff,pdiffres *pdiff,pdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres w>=0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_pfet_01v8_hvt scpfethvt \ + *pdiff,pdiffres *pdiff,pdiffres w<0.42 l=l \ + w=w a1=as p1=ps a2=ad p2=pd + + device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \ + *ndiff,ndiffres *ndiff,ndiffres \ + w>=0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_01v8 scnfet \ + *ndiff,ndiffres *ndiff,ndiffres \ + w<0.42 l=l w=w a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_latch npd \ + *ndiff,ndiffres *srampvar l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__special_nfet_pass npass \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \ + *ndiff,ndiffres *ndiff,ndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device subcircuit sky130_fd_pr__cap_var_lvt varactor \ + *nndiff l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt \ + *nndiff l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor \ + *mvnndiff l=l w=w + + # Bipolars +# device msubcircuit sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a1=area +# device msubcircuit sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w \ +# error a1>0.99 a1<1.01 +# device msubcircuit sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w \ +# error a1>1.99 a1<2.01 +# device msubcircuit sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a1=area +# device msubcircuit sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff \ +# pwell,space/w a1>0.45 a1<0.47 +# device msubcircuit sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff \ +# pwell,space/w a1>11.55 a1<11.57 +# device msubcircuit sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a1=area +# device msubcircuit sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff \ +# dnwell space/w error a1>0.99 a1<1.01 + + # Ignore the extended-drain FET geometry that forms part of the high-voltage + # bipolar devices. +# device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp +# device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp + + # Extended drain devices (must appear before the regular devices) +# device msubcircuit sky130_fd_pr__nfet_g5v0d16v0 mvnfet *mvndiff \ +# extdrain,*mvnsd pwell,space/w error l=l w=w a1=as p1=ps a2=ad p2=pd +# device msubcircuit sky130_fd_pr__pfet_g5v0d16v0 mvpfet *mvpdiff \ +# extdrain,*mvpsd nwell error l=l w=w a1=as p1=ps a2=ad p2=pd +# device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ +# dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd +# device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ +# dnwell pwell,space/w error l=l w=w a1=as a2=ad p1=ps p2=pd +# device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ +# pwell,space/w nwell error l=l w=w a1=as a2=ad p1=ps p2=pd + + device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__nfet_03v3_nvt nnfet \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd \ + *mvndiff,mvndiffres *mvndiff,mvndiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + device msubcircuit sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd \ + *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres l=l w=w \ + a1=as p1=ps a2=ad p2=pd + + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 +# device ndiode sky130_fd_pr__model__parasitic__diode_ps2dn \ +# photo pwell,space/w error a=area + + device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \ + xpc l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \ + xpc w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \ + xpc w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \ + xpc w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \ + xpc w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \ + xpc w>5.72 w<5.74 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \ + xpc l=l+0.16 w=w + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \ + xpc w>0.34 w<0.36 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \ + xpc w>0.68 w<0.70 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \ + xpc w>1.40 w<1.42 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \ + xpc w>2.84 w<2.86 l=l+0.16 + device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \ + xpc w>5.72 w<5.74 l=l+0.16 + + device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \ + *ndiff l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \ + *pdiff l=l w=w +# device rsubcircuit sky130_fd_pr__res_iso_pw rpw \ +# pwell dnwell error l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_nd__hv mvndiffres \ + *mvndiff l=l w=w + device rsubcircuit sky130_fd_pr__res_generic_pd__hv mvpdiffres \ + *mvpdiff l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + + # NOTE: SkyWater diode models have bizarre units requiring bizarre scaling +# device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area*1E12 p=pj*1E6 +# device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area*1E12 p=pj*1E6 +# device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area*1E12 p=pj*1E6 +# device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area*1E12 p=pj*1E6 + +# device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area*1E12 p=pj*1E6 +# device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area*1E12 p=pj*1E6 +# device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area*1E12 p=pj*1E6 +# device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area*1E12 p=pj*1E6 + + device csubcircuit sky130_fd_pr_reram__reram_cell reram m1 a=area_ox + + device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l + device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l + + variants (orig) + + device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__special_pfet_latch ppu pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell + device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w + device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \ + pwell,space/w + + # Note that corenvar, corepvar are not considered devices, and extract as + # parasitic capacitance instead (but cap values need to be added). + + # Extended drain devices (must appear before the regular devices) + device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error + device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \ + dnwell pwell,space/w error + device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \ + pwell,space/w nwell error + + device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell + device mosfet sky130_fd_pr__esd_pfet_g5v0d10v5 mvpfetesd mvpdiff,mvpdiffres,mvpdc nwell + device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w + device mosfet sky130_fd_pr__esd_nfet_g5v0d10v5 mvnfetesd mvndiff,mvndiffres,mvndc pwell,space/w + device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w + device mosfet sky130_fd_pr__nfet_03v3_nvt nnfet *mvndiff,mvndiffres pwell,space/w + + # These devices always extract as subcircuits + device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w + device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w + + device resistor sky130_fd_pr__res_generic_po rmp *poly + device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli + device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1 + device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2 + device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3 + device resistor sky130_fd_pr__res_generic_m4 rm4 *m4 + device resistor sky130_fd_pr__res_generic_m5 rm5 *m5 + + device resistor sky130_fd_pr__res_high_po xhrpoly xpc + device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc + device resistor sky130_fd_pr__res_generic_po mrp1 *poly + device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff + device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff + device resistor mrdn_hv mvndiffres *mvndiff + device resistor mrdp_hv mvpdiffres *mvpdiff + device resistor sky130_fd_pr__res_iso_pw rpw pwell + + # NOTE: SkyWater diode models have bizarre units requiring bizarre scaling + device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area*1E12 p=pj*1E6 + device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area*1E12 p=pj*1E6 + + device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area*1E12 p=pj*1E6 + device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area*1E12 p=pj*1E6 + + device bjt sky130_fd_pr__npn_05v5 npn *ndiff dnwell space/w error a1=area + device bjt sky130_fd_pr__npn_05v5_W1p00L1p00 npn *ndiff dnwell space/w error \ + a1>0.99 a1<1.01 + device bjt sky130_fd_pr__npn_05v5_W1p00L2p00 npn *ndiff dnwell space/w error \ + a1>1.99 a1<2.01 + device bjt sky130_fd_pr__pnp_05v5 pnp *pdiff pwell,space/w a1=area + device bjt sky130_fd_pr__pnp_05v5_W0p68L0p68 pnp *pdiff pwell,space/w \ + a1>0.45 a1<0.48 + device bjt sky130_fd_pr__pnp_05v5_W3p40L3p40 pnp *pdiff pwell,space/w \ + a1>11.55 a1<11.57 + device bjt sky130_fd_pr__npn_11v0 npn *mvndiff dnwell space/w error a1=area + device bjt sky130_fd_pr__npn_11v0_W1p00L1p00 npn *mvndiff dnwell space/w error \ + a1>0.99 a1<1.01 + + device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1 + device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1 + +end + +#----------------------------------------------------- +# Wiring tool definitions +#----------------------------------------------------- + +wiring + # All wiring values are in nanometers + scalefactor 10 + + contact mcon 170 li 0 0 m1 30 60 + contact v1 260 m1 0 30 m2 0 30 + contact v2 280 m2 0 45 m3 25 0 + contact v3 320 m3 0 30 m4 5 5 + contact v4 1180 m4 0 m5 120 + + contact pc 170 poly 50 80 li 0 80 + contact pdc 170 pdiff 40 60 li 0 80 + contact ndc 170 ndiff 40 60 li 0 80 + contact psc 170 psd 40 60 li 0 80 + contact nsc 170 nsd 40 60 li 0 80 + +end + +#----------------------------------------------------- +# Plain old router. . . +#----------------------------------------------------- + +router +end + +#------------------------------------------------------------ +# Plowing (restored in magic 8.2, need to fill this section) +#------------------------------------------------------------ + +plowing +end + +#----------------------------------------------------------------- +# No special plot layers defined (use default PNM color choices) +#----------------------------------------------------------------- + +plot + style pnm + default + draw fillblock no_color_at_all + draw fillblock4 no_color_at_all + draw fomfill no_color_at_all + draw polyfill no_color_at_all + draw m1fill no_color_at_all + draw m2fill no_color_at_all + draw m3fill no_color_at_all + draw m4fill no_color_at_all + draw m5fill no_color_at_all + draw nwell cwell +end + diff --git a/scripts/be_checks/tech/sky130B/sky130B_setup.tcl b/scripts/be_checks/tech/sky130B/sky130B_setup.tcl new file mode 100644 index 00000000..90eecdba --- /dev/null +++ b/scripts/be_checks/tech/sky130B/sky130B_setup.tcl @@ -0,0 +1,555 @@ +#--------------------------------------------------------------- +# Setup file for netgen LVS +# SkyWater sky130B +#--------------------------------------------------------------- +permute default +property default +property parallel none + +# Allow override of default #columns in the output format. +catch {format $env(NETGEN_COLUMNS)} + +#--------------------------------------------------------------- +# For the following, get the cell lists from +# circuit1 and circuit2. +#--------------------------------------------------------------- + +set cells1 [cells list -all -circuit1] +set cells2 [cells list -all -circuit2] + +#------------------------------------------- +# Resistors (except metal) +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__res_iso_pw +lappend devices sky130_fd_pr__res_high_po_0p35 +lappend devices sky130_fd_pr__res_high_po_0p69 +lappend devices sky130_fd_pr__res_high_po_1p41 +lappend devices sky130_fd_pr__res_high_po_2p85 +lappend devices sky130_fd_pr__res_high_po_5p73 +lappend devices sky130_fd_pr__res_high_po +lappend devices sky130_fd_pr__res_xhigh_po_0p35 +lappend devices sky130_fd_pr__res_xhigh_po_0p69 +lappend devices sky130_fd_pr__res_xhigh_po_1p41 +lappend devices sky130_fd_pr__res_xhigh_po_2p85 +lappend devices sky130_fd_pr__res_xhigh_po_5p73 +lappend devices sky130_fd_pr__res_xhigh_po +lappend devices sky130_fd_pr__res_generic_nd +lappend devices sky130_fd_pr__res_generic_pd +lappend devices sky130_fd_pr__res_generic_nd__hv +lappend devices sky130_fd_pr__res_generic_pd__hv +lappend devices mrdn_hv mrdp_hv + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" 1 2 + property "-circuit1 $dev" series enable + property "-circuit1 $dev" series {w critical} + property "-circuit1 $dev" series {l add} + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" parallel {value par} + property "-circuit1 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" 1 2 + property "-circuit2 $dev" series enable + property "-circuit2 $dev" series {w critical} + property "-circuit2 $dev" series {l add} + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" parallel {value par} + property "-circuit2 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#------------------------------------------- +# poly resistor +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__res_generic_po + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" end_a end_b + property "-circuit1 $dev" series enable + property "-circuit1 $dev" series {w critical} + property "-circuit1 $dev" series {l add} + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" parallel {value par} + property "-circuit1 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" end_a end_b + property "-circuit2 $dev" series enable + property "-circuit2 $dev" series {w critical} + property "-circuit2 $dev" series {l add} + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" parallel {value par} + property "-circuit2 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#------------------------------------------- +# MRM (metal) resistors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__res_generic_l1 +lappend devices sky130_fd_pr__res_generic_m1 +lappend devices sky130_fd_pr__res_generic_m2 +lappend devices sky130_fd_pr__res_generic_m3 +lappend devices sky130_fd_pr__res_generic_m4 +lappend devices sky130_fd_pr__res_generic_m5 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" end_a end_b + property "-circuit1 $dev" series enable + property "-circuit1 $dev" series {w critical} + property "-circuit1 $dev" series {l add} + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" parallel {value par} + property "-circuit1 $dev" tolerance {l 10.0} {w 10.0} + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" end_a end_b + property "-circuit2 $dev" series enable + property "-circuit2 $dev" series {w critical} + property "-circuit2 $dev" series {l add} + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" parallel {value par} + property "-circuit2 $dev" tolerance {l 10.0} {w 10.0} + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#------------------------------------------- +# (MOS) transistors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__nfet_01v8 +lappend devices sky130_fd_pr__nfet_01v8_lvt +lappend devices sky130_fd_bs_flash__special_sonosfet_star +lappend devices sky130_fd_pr__nfet_g5v0d10v5 +lappend devices sky130_fd_pr__nfet_03v3_nvt +lappend devices sky130_fd_pr__nfet_05v0_nvt +lappend devices sky130_fd_pr__pfet_01v8 +lappend devices sky130_fd_pr__pfet_01v8_lvt +lappend devices sky130_fd_pr__pfet_01v8_mvt +lappend devices sky130_fd_pr__pfet_01v8_hvt +lappend devices sky130_fd_pr__pfet_g5v0d10v5 +lappend devices sky130_fd_pr__special_nfet_latch +lappend devices sky130_fd_pr__special_nfet_pass +lappend devices sky130_fd_pr__special_pfet_latch +lappend devices sky130_fd_pr__special_nfet_01v8 +lappend devices sky130_fd_pr__special_pfet_01v8_hvt +lappend devices sky130_fd_pr__cap_var_lvt +lappend devices sky130_fd_pr__cap_var_hvt +lappend devices sky130_fd_pr__cap_var + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" 1 3 + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" 1 3 + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } +} + +#--------------------------------------------------------------------- +# Extended drain MOSFET devices. These have asymmetric source and +# drain, and so the source and drain are not permutable. +#--------------------------------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__nfet_20v0_zvt +lappend devices sky130_fd_pr__nfet_20v0_nvt +lappend devices sky130_fd_pr__nfet_20v0_iso +lappend devices sky130_fd_pr__nfet_20v0 +lappend devices sky130_fd_pr__pfet_20v0 +lappend devices sky130_fd_pr__nfet_g5v0d16v0 +lappend devices sky130_fd_pr__pfet_g5v0d16v0 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" tolerance {w 0.01} {l 0.01} + # Ignore these properties + property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } +} + +#--------------------------------------------------------------------- +# (MOS) ESD transistors. Note that the ESD transistors have a flanged +# gate. Magic disagrees slightly on how to interpret the width of the +# devices, so the tolerance is increased to 7% to cover the difference +#--------------------------------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__esd_nfet_g5v0d10v5 +lappend devices sky130_fd_pr__esd_pfet_g5v0d10v5 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + permute "-circuit1 $dev" 1 3 + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {l critical} + property "-circuit1 $dev" parallel {w add} + property "-circuit1 $dev" tolerance {w 0.07} {l 0.01} + # Ignore these properties + property "-circuit1 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } + if {[lsearch $cells2 $dev] >= 0} { + permute "-circuit2 $dev" 1 3 + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {l critical} + property "-circuit2 $dev" parallel {w add} + property "-circuit2 $dev" tolerance {w 0.07} {l 0.01} + # Ignore these properties + property "-circuit2 $dev" delete as ad ps pd mult sa sb sd nf nrd nrs area perim topography + } +} + +#------------------------------------------- +# diodes +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__diode_pw2nd_05v5 +lappend devices sky130_fd_pr__diode_pw2nd_05v5_lvt +lappend devices sky130_fd_pr__diode_pw2nd_05v5_nvt +lappend devices sky130_fd_pr__diode_pd2nw_05v5 +lappend devices sky130_fd_pr__diode_pd2nw_05v5_lvt +lappend devices sky130_fd_pr__diode_pd2nw_05v5_hvt +lappend devices sky130_fd_pr__diode_pw2nd_11v0 +lappend devices sky130_fd_pr__diode_pd2nw_11v0 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {area add} + property "-circuit1 $dev" parallel {pj add} + property "-circuit1 $dev" parallel {value add} + property "-circuit1 $dev" tolerance {area 0.02} {pj 0.02} + # Ignore these properties + property "-circuit1 $dev" delete mult perim + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {area add} + property "-circuit2 $dev" parallel {pj add} + property "-circuit2 $dev" parallel {value add} + property "-circuit2 $dev" tolerance {area 0.02} {pj 0.02} + # Ignore these properties + property "-circuit2 $dev" delete mult perim + } +} + +#------------------------------------------- +# capacitors +# MiM capacitors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__cap_mim_m3_1 +lappend devices sky130_fd_pr__cap_mim_m3_2 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + property "-circuit1 $dev" parallel {area add} + property "-circuit1 $dev" parallel {value add} + property "-circuit1 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit1 $dev" delete mult perim mf + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + property "-circuit2 $dev" parallel {area add} + property "-circuit2 $dev" parallel {value add} + property "-circuit2 $dev" tolerance {l 0.01} {w 0.01} + # Ignore these properties + property "-circuit2 $dev" delete mult perim mf + } +} + +#------------------------------------------- +# Fixed-layout devices +# bipolar transistors, +# VPP capacitors +#------------------------------------------- + +set devices {} +lappend devices sky130_fd_pr__npn_05v5_W1p00L1p00 +lappend devices sky130_fd_pr__npn_05v5_W1p00L2p00 +lappend devices sky130_fd_pr__pnp_05v5_W0p68L0p68 +lappend devices sky130_fd_pr__pnp_05v5_W3p40L3p40 +lappend devices sky130_fd_pr__rf_npn_05v5_W1p00L1p00 +lappend devices sky130_fd_pr__rf_npn_05v5_W1p00L2p00 +lappend devices sky130_fd_pr__rf_pnp_05v5_W0p68L0p68 +lappend devices sky130_fd_pr__rf_pnp_05v5_W3p40L3p40 +lappend devices sky130_fd_pr__npn_05v5 +lappend devices sky130_fd_pr__pnp_05v5 +lappend devices sky130_fd_pr__npn_11v0 + +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m4_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_pom4_shield +lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_lim4_shield +lappend devices sky130_fd_pr__cap_vpp_6p8x6p1_polym4_shield +lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_lim5_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_li_shield +lappend devices sky130_fd_pr__cap_vpp_11p5x11p7_m3_shield +lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_li_shield +lappend devices sky130_fd_pr__cap_vpp_1p8x1p8_m3_shield +lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_li_shield +lappend devices sky130_fd_pr__cap_vpp_4p4x4p6_m3_shield +lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_li_shield +lappend devices sky130_fd_pr__cap_vpp_8p6x7p9_m3_shield +lappend devices sky130_fd_pr__ind_04_01 +lappend devices sky130_fd_pr__ind_04_02 + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" parallel enable + # Ignore these properties + property "-circuit1 $dev" delete mult + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" parallel enable + # Ignore these properties + property "-circuit2 $dev" delete mult + } +} + +#--------------------------------------------------------------- +# ReRAM +#--------------------------------------------------------------- + +set devices {sky130_fd_pr_reram__reram_cell} + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + property "-circuit1 $dev" delete Tfilament_0 + } + if {[lsearch $cells2 $dev] >= 0} { + property "-circuit2 $dev" delete Tfilament_0 + } +} + +#--------------------------------------------------------------- +# Schematic cells which are not extractable +#--------------------------------------------------------------- + +set devices {sky130_fd_io__condiode sky130_fd_io__tap_1} + +foreach dev $devices { + if {[lsearch $cells1 $dev] >= 0} { + ignore class "-circuit1 $dev" + } + if {[lsearch $cells2 $dev] >= 0} { + ignore class "-circuit2 $dev" + } +} + +#--------------------------------------------------------------- +# Digital cells (ignore decap, fill, and tap cells) +# Make a separate list for each supported library +#--------------------------------------------------------------- +# e.g., ignore class "-circuit2 sky130_fc_sc_hd__decap_3" +#--------------------------------------------------------------- + +#--------------------------------------------------------------- +# Allow the fill, decap, etc., cells to be parallelized +#--------------------------------------------------------------- + +foreach cell $cells1 { + if {[regexp {.*sky130_.._sc_[^_]+__decap_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__fill_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__diode_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } + if {[regexp {.*sky130_.._sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} { + property "-circuit1 $cell" parallel enable + } +} +foreach cell $cells2 { + if {[regexp {sky130_ef_sc_[^_]+__decap_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__fill_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__tapvpwrvgnd_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__diode_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_fd_sc_[^_]+__fill_diode_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } + if {[regexp {sky130_ef_sc_[^_]+__fakediode_[[:digit:]]+} $cell match]} { + property "-circuit2 $cell" parallel enable + } +} + +#--------------------------------------------------------------- +# Handle cells captured from Electric +# +# Find cells of the form "__" in the netlist +# from Electric where the extracted layout netlist has only +# "". Cross-check by ensuring that the full name +# "__" does not exist in both cells, and that +# the truncated name "" does not exist in both cells. +#--------------------------------------------------------------- +# e.g., hydra_spi_controller__hydra_spi_controller +#--------------------------------------------------------------- + +foreach cell $cells1 { + if {[regexp "(.+)__(.+)" $cell match library cellname]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0) && \ + ([lsearch $cells1 $cellname] < 0)} { + equate classes "-circuit1 $cell" "-circuit2 $cellname" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + #puts stdout "Matching pins of $cell in circuit 1 and $cellname in circuit 2" + #equate pins "-circuit1 $cell" "-circuit2 $cellname" + } + } +} + +foreach cell $cells2 { + if {[regexp "(.+)__(.+)" $cell match library cellname]} { + if {([lsearch $cells1 $cell] < 0) && \ + ([lsearch $cells1 $cellname] >= 0) && \ + ([lsearch $cells2 $cellname] < 0)} { + equate classes "-circuit1 $cellname" "-circuit2 $cell" + puts stdout "Equating $cellname in circuit 1 and $cell in circuit 2" + #puts stdout "Matching pins of $cellname in circuit 1 and $cell in circuit 2" + #equate pins "-circuit1 $cellname" "-circuit2 $cell" + } + } +} + +# Match pins on black-box cells if LVS is called with "-blackbox" +if {[model blackbox]} { + foreach cell $cells1 { + if {[model "-circuit1 $cell"] == "blackbox"} { + if {[lsearch $cells2 $cell] >= 0} { + puts stdout "Matching pins of $cell in circuits 1 and 2" + equate pins "-circuit1 $cell" "-circuit2 $cell" + } + } + } +} + +#--------------------------------------------------------------- +# Equate sram layout cells with corresponding source +foreach cell $cells1 { + if {[regexp {([A-Z][A-Z0-9]_)*sky130_sram_([^_]+)_([^_]+)_([^_]+)_([^_]+)_(.+)} $cell match prefix memory_size memory_type matrix io cellname]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0) && \ + ([lsearch $cells1 $cellname] < 0)} { + # netlist with the N names should always be the second netlist + equate classes "-circuit2 $cellname" "-circuit1 $cell" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + #equate pins "-circuit1 $cell" "-circuit2 $cellname" + } + } +} + +# Equate prefixed layout cells with corresponding source +foreach cell $cells1 { + set layout $cell + while {[regexp {([A-Z][A-Z0-9]_)(.*)} $layout match prefix cellname]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0)} { + # netlist with the N names should always be the second netlist + equate classes "-circuit2 $cellname" "-circuit1 $cell" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + #if { [lsearch $cells1 $cellname] > 0 } { + #equate classes "-circuit2 $cellname" "-circuit1 $cellname" + #puts stdout "Equating $cellname in circuit 1 and $cellname in circuit 2" + #} + #equate pins "-circuit1 $cell" "-circuit2 $cellname" + } + set layout $cellname + } +} + +# Equate suffixed layout cells with corresponding source +foreach cell $cells1 { + if {[regexp {(.*)(\$[0-9])} $cell match cellname suffix]} { + if {([lsearch $cells2 $cell] < 0) && \ + ([lsearch $cells2 $cellname] >= 0)} { + # netlist with the N names should always be the second netlist + equate classes "-circuit2 $cellname" "-circuit1 $cell" + puts stdout "Equating $cell in circuit 1 and $cellname in circuit 2" + } + } +} + +#Added programatically. diff --git a/scripts/be_checks/tech/sky130B/spi2cdl b/scripts/be_checks/tech/sky130B/spi2cdl new file mode 100755 index 00000000..10072646 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/spi2cdl @@ -0,0 +1,42 @@ +#! /bin/bash + +awk ' +/^X.*pr__diode.*=/ { + print "D" $0; + next; +} +/^X.*__special_[^ _]*fet.*=/ || /^X.*pr__.fet.*=/ || /^X.*pr__esd_.fet.*=/ || /^X.*[np]fet_[0-9]*v[0-9].*=/ { + print "M" $0; + next; +} +/^X.*pr__pnp_.*=/ || /^X.*pr__pnp_[^ ]* *$/ { + print "Q" $0; + next; +} +/^X.*pr__cap_mim_.*=/ || /^X.*mim_2p0fF.*=/ || /^X.*cap_mim_2f0_m4m5/ { + print "C" $0; + next; +} +/^X.*pr__cap_var.*=/ { + bulk = $4; + $4 = ""; + print "C" $0, "$SUB=" bulk; + next; +} +/^X.*pr__res_.*=/ || /^X.*ppolyf_u_1k_6p0/ { + bulk = $4; + $4 = ""; + print "R" $0, "$SUB=" bulk; + next; +} +/^X.*sky130_fd_pr.*_reram_cell.*=/ { + print "R" $0; + next; +} +/^R/ && NF == 4 && $4 == "0.000000" { + $4 = "short " $4; +} + { + print $0; +}' $1 + diff --git a/scripts/be_checks/tech/sky130B/user_analog_project_wrapper_dummy.v b/scripts/be_checks/tech/sky130B/user_analog_project_wrapper_dummy.v new file mode 100644 index 00000000..ef2ad663 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/user_analog_project_wrapper_dummy.v @@ -0,0 +1,123 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_analog_project_wrapper + * + * This wrapper enumerates all of the pins available to the + * user for the user analog project. + * + *------------------------------------------------------------- + */ + +/// sta-blackbox +module user_analog_project_wrapper ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + /* GPIOs. There are 27 GPIOs, on either side of the analog. + * These have the following mapping to the GPIO padframe pins + * and memory-mapped registers, since the numbering remains the + * same as caravel but skips over the analog I/O: + * + * io_in/out/oeb/in_3v3 [26:14] <---> mprj_io[37:25] + * io_in/out/oeb/in_3v3 [13:0] <---> mprj_io[13:0] + * + * When the GPIOs are configured by the Management SoC for + * user use, they have three basic bidirectional controls: + * in, out, and oeb (output enable, sense inverted). For + * analog projects, a 3.3V copy of the signal input is + * available. out and oeb must be 1.8V signals. + */ + + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in, + input [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb, + + /* Analog (direct connection to GPIO pad---not for high voltage or + * high frequency use). The management SoC must turn off both + * input and output buffers on these GPIOs to allow analog access. + * These signals may drive a voltage up to the value of VDDIO + * (3.3V typical, 5.5V maximum). + * + * Note that analog I/O is not available on the 7 lowest-numbered + * GPIO pads, and so the analog_io indexing is offset from the + * GPIO indexing by 7, as follows: + * + * gpio_analog/noesd [17:7] <---> mprj_io[35:25] + * gpio_analog/noesd [6:0] <---> mprj_io[13:7] + * + */ + + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog, + inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd, + + /* Analog signals, direct through to pad. These have no ESD at all, + * so ESD protection is the responsibility of the designer. + * + * user_analog[10:0] <---> mprj_io[24:14] + * + */ + inout [`ANALOG_PADS-1:0] io_analog, + + /* Additional power supply ESD clamps, one per analog pad. The + * high side should be connected to a 3.3-5.5V power supply. + * The low side should be connected to ground. + * + * clamp_high[2:0] <---> mprj_io[20:18] + * clamp_low[2:0] <---> mprj_io[20:18] + * + */ + inout [2:0] io_clamp_high, + inout [2:0] io_clamp_low, + + // Independent clock (on independent integer divider) + input user_clock2, + + // User maskable interrupt signals + output [2:0] user_irq +); + + +endmodule // user_analog_project_wrapper diff --git a/scripts/be_checks/tech/sky130B/user_project_wrapper_dummy.v b/scripts/be_checks/tech/sky130B/user_project_wrapper_dummy.v new file mode 100644 index 00000000..bf76cf09 --- /dev/null +++ b/scripts/be_checks/tech/sky130B/user_project_wrapper_dummy.v @@ -0,0 +1,87 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_project_wrapper + * + * This wrapper enumerates all of the pins available to the + * user for the user project. + * + * An example user project is provided in this wrapper. The + * example should be removed and replaced with the actual + * user project. + * + *------------------------------------------------------------- + */ + +module user_project_wrapper #( + parameter BITS = 32 +) ( +`ifdef USE_POWER_PINS + inout vdda1, // User area 1 3.3V supply + inout vdda2, // User area 2 3.3V supply + inout vssa1, // User area 1 analog ground + inout vssa2, // User area 2 analog ground + inout vccd1, // User area 1 1.8V supply + inout vccd2, // User area 2 1.8v supply + inout vssd1, // User area 1 digital ground + inout vssd2, // User area 2 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb, + + // Analog (direct connection to GPIO pad---use with caution) + // Note that analog I/O is not available on the 7 lowest-numbered + // GPIO pads, and so the analog_io indexing is offset from the + // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io). + inout [`MPRJ_IO_PADS-10:0] analog_io, + + // Independent clock (on independent integer divider) + input user_clock2, + + // User maskable interrupt signals + output [2:0] user_irq +); + +/*--------------------------------------*/ +/* User project is instantiated here */ +/*--------------------------------------*/ + +endmodule // user_project_wrapper + +`default_nettype wire diff --git a/scripts/be_checks/tech/soft.lvs.script b/scripts/be_checks/tech/soft.lvs.script new file mode 100644 index 00000000..470f90a9 --- /dev/null +++ b/scripts/be_checks/tech/soft.lvs.script @@ -0,0 +1 @@ +lvs "$::env(WORK_ROOT)/ext/$::env(TOP).gds.nowell.spice $::env(TOP)" "$::env(WORK_ROOT)/nowell.ext/$::env(TOP).gds.nowell.spice $::env(TOP)" $::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/$::env(PDK)_setup.tcl $::env(WORK_ROOT)/soft.report