Hardware implementation of the SHA-256 cryptographic hash function. The rtl is based on this repo
AHBL wrapper is provided, APB and wishbone wrappers will be provided soon.
Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the AHBL wrapper:
SW_SHA256_AHBL INST (
`TB_AHBL_SLAVE_CONN
);NOTE: `TB_AHBL_SLAVE_CONN is a convenient macro provided by BusWrap.
The following table is the result for implementing the SW_SHA256 IP with different wrappers using Sky130 PDK and OpenLane2 flow.
| Module | Number of cells | Max. freq |
|---|---|---|
| SW_SHA256 | TBD | TBD |
| SW_SHA256_APB | TBD | TBD |
| SW_SHA256_AHBL | TBD | TBD |
| SW_SHA256_WB | TBD | TBD |
| Name | Offset | Reset Value | Access Mode | Description |
|---|---|---|---|---|
| STATUS | 0000 | 0x00000000 | r | Status register bit 0: digest is valid , bit 1: ready |
| CTRL | 0004 | 0x00000000 | w | Control register bit 0: Initial bit (init) bit 1: Next bit , bit 2: Mode bit |
| BLOCK0 | 0008 | 0x00000000 | w | Contains the bits 31-0 of the input block value |
| BLOCK1 | 000c | 0x00000000 | w | Contains the bits 63-32 of the input block value |
| BLOCK2 | 0010 | 0x00000000 | w | Contains the bits 95-64 of the input block value |
| BLOCK3 | 0014 | 0x00000000 | w | Contains the bits 127-96 of the input block value |
| BLOCK4 | 0018 | 0x00000000 | w | Contains the bits 159-128 of the input block value |
| BLOCK5 | 001c | 0x00000000 | w | Contains the bits 191-160 of the input block value |
| BLOCK6 | 0020 | 0x00000000 | w | Contains the bits 223-192 of the input block value |
| BLOCK7 | 0024 | 0x00000000 | w | Contains the bits 255-224 of the input block value |
| BLOCK8 | 0028 | 0x00000000 | w | Contains the bits 287-256 of the input block value |
| BLOCK9 | 002c | 0x00000000 | w | Contains the bits 319-288 of the input block value |
| BLOCK10 | 0030 | 0x00000000 | w | Contains the bits 351-320 of the input block value |
| BLOCK11 | 0034 | 0x00000000 | w | Contains the bits 383-352 of the input block value |
| BLOCK12 | 0038 | 0x00000000 | w | Contains the bits 415-384 of the input block value |
| BLOCK13 | 003c | 0x00000000 | w | Contains the bits 447-416 of the input block value |
| BLOCK14 | 0040 | 0x00000000 | w | Contains the bits 479-448 of the input block value |
| BLOCK15 | 0044 | 0x00000000 | w | Contains the bits 512-480 of the input block value |
| DIGEST0 | 0048 | 0x00000000 | w | Contains the bits 31-0 of the input digest value |
| DIGEST1 | 004c | 0x00000000 | w | Contains the bits 63-32 of the input digest value |
| DIGEST2 | 0050 | 0x00000000 | w | Contains the bits 95-64 of the input digest value |
| DIGEST3 | 0054 | 0x00000000 | w | Contains the bits 127-96 of the input digest value |
| DIGEST4 | 0058 | 0x00000000 | w | Contains the bits 159-128 of the input digest value |
| DIGEST5 | 005c | 0x00000000 | w | Contains the bits 191-160 of the input digest value |
| DIGEST6 | 0060 | 0x00000000 | w | Contains the bits 223-192 of the input digest value |
| DIGEST7 | 0064 | 0x00000000 | w | Contains the bits 255-224 of the input digest value |
| IM | ff00 | 0x00000000 | w | Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details |
| RIS | ff08 | 0x00000000 | w | Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details |
| MIS | ff04 | 0x00000000 | w | Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details |
| IC | ff0c | 0x00000000 | w | Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details |
Status register bit 0: digest is valid , bit 1: ready
| bit | field name | width | description |
|---|---|---|---|
| 6 | ready_reg | 1 | Ready to start |
| 7 | digest_valid_reg | 1 | Digest is valid |
Control register bit 0: Initial bit (init) bit 1: Next bit , bit 2: Mode bit
| bit | field name | width | description |
|---|---|---|---|
| 0 | init_reg | 1 | Initial bit |
| 1 | next_reg | 1 | Next bit |
| 2 | mode_reg | 1 | Mode bit; “0” means SHA224 “1” means SHA256" |
Contains the bits 31-0 of the input block value
Contains the bits 63-32 of the input block value
Contains the bits 95-64 of the input block value
Contains the bits 127-96 of the input block value
Contains the bits 159-128 of the input block value
Contains the bits 191-160 of the input block value
Contains the bits 223-192 of the input block value
Contains the bits 255-224 of the input block value
Contains the bits 287-256 of the input block value
Contains the bits 319-288 of the input block value
Contains the bits 351-320 of the input block value
Contains the bits 383-352 of the input block value
Contains the bits 415-384 of the input block value
Contains the bits 447-416 of the input block value
Contains the bits 479-448 of the input block value
Contains the bits 512-480 of the input block value
Contains the bits 31-0 of the input digest value
Contains the bits 63-32 of the input digest value
Contains the bits 95-64 of the input digest value
Contains the bits 127-96 of the input digest value
Contains the bits 159-128 of the input digest value
Contains the bits 191-160 of the input digest value
Contains the bits 223-192 of the input digest value
Contains the bits 255-224 of the input digest value
The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the BusWrap bus_wrap.py utility.
Each register has a group of bits for the interrupt sources/flags.
-
IM: is used to enable/disable interrupt sources. -
RIS: has the current interrupt status (interrupt flags) whether they are enabled or disabled. -
MIS: is the result of masking (ANDing) RIS by IM. -
IC: is used to clear an interrupt flag.
The following are the bit definitions for the interrupt registers:
| Bit | Flag | Width | Description |
|---|---|---|---|
| 0 | VALID | 1 | Digest is valid |
| 1 | READY | 1 | Ready to start |
| Port | Direction | Width | Description |
|---|---|---|---|
| init | input | 1 | Initial bit |
| next | input | 1 | Next bit |
| mode | input | 1 | Mode bit; '0' means SHA224 '1' means SHA256 |
| block | input | 512 | block value |
| ready | output | 1 | ready to start |
| digest | output | 256 | digest value |
| digest_valid | output | 1 | digest is valid |
TBD
You can either clone repo or use IPM which is an open-source IPs Package Manager
- To clone repo:
git clone https://github.com/efabless/SW_SHA256 - To download via IPM , follow installation guides here then run
ipm install SW_SHA256
TBD