diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md
index 8cda2ec..76cddd6 100644
--- a/doc/project_mgt_hw.md
+++ b/doc/project_mgt_hw.md
@@ -135,7 +135,6 @@ Verification/Validation
     - [ ] https://github.com/chipsalliance/Surelog
     - [ ] https://stackoverflow.com/questions/65534532/how-to-estimation-a-chip-size-with-standard-cell-library
 - [ ] Core config
-    - [ ] Supporter des set de config du core en test bench.
     - [ ] Faire un test de synthèse selon les configs du core
     - [ ] Support cache disable in testbench
 - [ ] Error Logger Interface
@@ -173,6 +172,8 @@ Hardware Tests
 
 # DONE
 
+- [X] v1.6.0
+    - [X] Supporter des set de config du core en test bench.
 - [X] v1.5.1: maintenance
     - [X] Preload jal even if processing is busy
     - [X] Print des tests qui ne marchent pas, un par un, dans le bash
diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv
index 85caef1..df8f3a3 100644
--- a/rtl/friscv_control.sv
+++ b/rtl/friscv_control.sv
@@ -257,8 +257,10 @@ module friscv_control
         else if (cause=='h0)  get_mcause_desc = "Instruction address misaligned";
         else if (cause=='h4)  get_mcause_desc = "LOAD address misaligned";
         else if (cause=='h6)  get_mcause_desc = "STORE address misaligned";
-        else if (cause=='h2)  get_mcause_desc = "Instruction decoding error";
-        else if (cause=='hB)  get_mcause_desc = "Environment call";
+        else if (cause=='h10) get_mcause_desc = "Instruction decoding error";
+        else if (cause=='h8)  get_mcause_desc = "Environment call (U-mode)";
+        else if (cause=='hB)  get_mcause_desc = "Environment call (M-mode)";
+        else if (cause=='h2)  get_mcause_desc = "Illegal instruction";
         // Asynchronous Trap
         else if (cause=='h80000003)  get_mcause_desc = "Machine Software Interrupt";
         else if (cause=='h80000007)  get_mcause_desc = "Machine Timer Interrupt";
@@ -1094,7 +1096,7 @@ module friscv_control
                                      (sys[`IS_MRET])                     ? inst_ready : 
                                      (sys[`IS_CSR] && csr[9:8] != 2'b00) ? inst_ready : 
                                      // Check if WFI must be trapped or not
-                                     (sys[`IS_WFI] )                     ? inst_ready : 
+                                     // (sys[`IS_WFI] )                     ? inst_ready : 
                                                                            '0;
     end else begin : NO_UMODE
         assign illegal_instruction = '0;
@@ -1164,26 +1166,27 @@ module friscv_control
                          (csr_sb[`MTIP])        ? {1'b1, {XLEN-5{1'b0}}, 4'h7} :
                          (csr_sb[`MEIP])        ? {1'b1, {XLEN-5{1'b0}}, 4'hB} :
                          // then follow sync exceptions
-                         (illegal_instruction)  ? {{XLEN-4{1'b0}}, 4'h2} :
-                         (csr_ro_wr)            ? {{XLEN-4{1'b0}}, 4'h2} :
-                         (inst_dec_error)       ? {{XLEN-4{1'b0}}, 4'h2} :
-                         (inst_addr_misaligned) ? {XLEN{1'b0}} :
-                         (ecall_umode)          ? {{XLEN-4{1'b0}}, 4'h8} :
-                         (ecall_mmode)          ? {{XLEN-4{1'b0}}, 4'hB} :
-                         (sys[`IS_EBREAK])      ? {{XLEN-4{1'b0}}, 4'h3} :
-                         (store_misaligned)     ? {{XLEN-4{1'b0}}, 4'h6} :
-                         (load_misaligned)      ? {{XLEN-4{1'b0}}, 4'h4} :
-                                                  {XLEN{1'b0}};
+                         (illegal_instruction)  ? {{XLEN-4{1'b0}}, 4'h2}  :
+                         (csr_ro_wr)            ? {{XLEN-4{1'b0}}, 4'h2}  :
+                         (inst_addr_misaligned) ? '0                      :
+                         (ecall_umode)          ? {{XLEN-4{1'b0}}, 4'h8}  :
+                         (ecall_mmode)          ? {{XLEN-4{1'b0}}, 4'hB}  :
+                         (sys[`IS_EBREAK])      ? {{XLEN-4{1'b0}}, 4'h3}  :
+                         (store_misaligned)     ? {{XLEN-4{1'b0}}, 4'h6}  :
+                         (load_misaligned)      ? {{XLEN-4{1'b0}}, 4'h4}  :
+                         (inst_dec_error)       ? {{XLEN-5{1'b0}}, 5'h18} :
+                                                  '0;
 
     // MTVAL: exception-specific information
     assign mtval_info = (inst_dec_error)       ? instruction :
                         (wfi_not_allowed)      ? instruction :
                         (illegal_instruction)  ? instruction :
+                        (inst_dec_error)       ? instruction :
                         (csr_ro_wr)            ? instruction :
                         (inst_addr_misaligned) ? pc_reg      :
                         (sys[`IS_ECALL])       ? pc_reg      :
                         (sys[`IS_EBREAK])      ? pc_reg      :
-                                                 {XLEN{1'b0}};
+                                                 '0;
 
     // Trigger the trap handling execution in main FSM
 
@@ -1194,8 +1197,7 @@ module friscv_control
     assign sync_trap_occuring = csr_ro_wr            |
                                 inst_addr_misaligned |
                                 load_misaligned      |
-                                // wfi_not_allowed      |
-                                // illegal_instruction  |
+                                illegal_instruction  |
                                 store_misaligned     |
                                 inst_dec_error       ;
 
diff --git a/rtl/friscv_registers.sv b/rtl/friscv_registers.sv
index b24e053..0a538e4 100644
--- a/rtl/friscv_registers.sv
+++ b/rtl/friscv_registers.sv
@@ -76,12 +76,65 @@ module friscv_registers
         input  wire  [XLEN                -1:0] csr_rd_val
     );
 
+    `ifdef TRACE_REGISTERS
+    //------------------------------------------------
+    // Function to print register name and information
+    // @i: register number to get info
+    // @returns a string describing the register
+    //------------------------------------------------
+    function string get_name(integer i);
+        get_name = "!?";
+        if (i== 0) get_name = "  zero  (hardwired zero)";
+        if (i== 1) get_name = "  ra    (return address)";
+        if (i== 2) get_name = "  sp    (stack pointer)";
+        if (i== 3) get_name = "  gp    (global pointer)";
+        if (i== 4) get_name = "  tp    (thread pointer)";
+        if (i== 5) get_name = "  t0    (temporary register 0)";
+        if (i== 6) get_name = "  t1    (temporary register 0)";
+        if (i== 7) get_name = "  t2    (temporary register 0)";
+        if (i== 8) get_name = "  s0_fp (saved register 0 / frame pointer)";
+        if (i== 9) get_name = "  s1    (saved register 1)";
+        if (i==10) get_name = "  a0    (function argument 0 / return value 0)";
+        if (i==11) get_name = "  a1    (function argument 1 / return value 1)";
+        if (i==12) get_name = "  a2    (function argument 2)";
+        if (i==13) get_name = "  a3    (function argument 3)";
+        if (i==14) get_name = "  a4    (function argument 4)";
+        if (i==15) get_name = "  a5    (function argument 5)";
+        if (i==16) get_name = "  a6    (function argument 6)";
+        if (i==17) get_name = "  a7    (function argument 7)";
+        if (i==18) get_name = "  s2    (saved register 2)";
+        if (i==19) get_name = "  s3    (saved register 3)";
+        if (i==20) get_name = "  s4    (saved register 4)";
+        if (i==21) get_name = "  s5    (saved register 5)";
+        if (i==22) get_name = "  s6    (saved register 6)";
+        if (i==23) get_name = "  s7    (saved register 7)";
+        if (i==24) get_name = "  s8    (saved register 8)";
+        if (i==25) get_name = "  s9    (saved register 9)";
+        if (i==26) get_name = "  s10   (saved register 10)";
+        if (i==27) get_name = "  s11   (saved register 11)";
+        if (i==28) get_name = "  t3    (temporary register 3)";
+        if (i==29) get_name = "  t4    (temporary register 4)";
+        if (i==30) get_name = "  t5    (temporary register 5)";
+        if (i==31) get_name = "  t6    (temporary register 6)";
+    endfunction
+    `endif
+
+
     // E extension limiting the register number to 16
     localparam REGNUM = (RV32E) ? 16 : 32;
 
     // ISA registers 0-31
     logic [XLEN-1:0] regs [REGNUM-1:0];
 
+    // Tracer setup
+    `ifdef TRACE_REGISTERS
+    integer f;
+    string fname;
+    initial begin
+        $sformat(fname, "trace_%s.txt", "registers");
+        f = $fopen(fname, "w");
+    end
+    `endif
 
     generate
 
@@ -120,7 +173,7 @@ module friscv_registers
                 end else if (csr_rd_wr && csr_rd_addr==i) begin
                     regs[i] = csr_rd_val;
 
-                // Access from data memory controller
+                // Access from processing units
                 end else if (|proc_rd_wr) begin
                     for (u=0;u<NB_ALU_UNIT;u=u+1) begin
                         if (proc_rd_wr[u] && proc_rd_addr[u*5+:5]==i) begin
@@ -135,9 +188,37 @@ module friscv_registers
             end
         end
 
+        `ifdef TRACE_REGISTERS
+        always @ (posedge aclk) begin
+            if (aresetn) begin
+
+                if (ctrl_rd_wr && ctrl_rd_addr==i)
+                    $fwrite(f, "(@ %0t) Ctrl Write :  reg[%2d] = 0x%x (0xf) %s\n", $realtime, i, ctrl_rd_val, get_name(i));
+
+                if (csr_rd_wr && csr_rd_addr==i)
+                    $fwrite(f, "(@ %0t) CSR Write :   reg[%2d] = 0x%x (0xf) %s\n", $realtime, i, csr_rd_val, get_name(i));
+
+                for (u=0;u<NB_ALU_UNIT;u=u+1) begin
+                    if (proc_rd_wr[u] && proc_rd_addr[u*5+:5]==i) begin
+
+                        if (u==0)
+                            $fwrite(f, "(@ %0t) ALU Write :   reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
+                        else if (u==1)
+                            $fwrite(f, "(@ %0t) Memfy Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
+                        else if (u==2)
+                            $fwrite(f, "(@ %0t) M_Ext Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
+                        else
+                            $fwrite(f, "(@ %0t) Ext%d Write :  reg[%2d] = 0x%x (0x%x) %s\n", $realtime, u, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
+
+                    end
+                end
+            end
+        end
+        `endif
     end
     endgenerate
 
+
     generate
 
     if (SYNC_READ==0) begin: COMB_READ
@@ -184,37 +265,38 @@ module friscv_registers
     end
     endgenerate
 
-    assign x1_ra     = regs[1];
-    assign x2_sp     = regs[2];
-    assign x3_gp     = regs[3];
-    assign x4_tp     = regs[4];
-    assign x5_t0     = regs[5];
-    assign x6_t1     = regs[6];
-    assign x7_t2     = regs[7];
-    assign x8_s0_fp  = regs[8];
-    assign x9_s1     = regs[9];
-    assign x10_a0    = regs[10];
-    assign x11_a1    = regs[11];
-    assign x12_a2    = regs[12];
-    assign x13_a3    = regs[13];
-    assign x14_a4    = regs[14];
-    assign x15_a5    = regs[15];
-    assign x16_a6    = regs[16];
-    assign x17_a7    = regs[17];
-    assign x18_s2    = regs[18];
-    assign x19_s3    = regs[19];
-    assign x20_s4    = regs[20];
-    assign x21_s5    = regs[21];
-    assign x22_s6    = regs[22];
-    assign x23_s7    = regs[23];
-    assign x24_s8    = regs[24];
-    assign x25_s9    = regs[25];
-    assign x26_s10   = regs[26];
-    assign x27_s11   = regs[27];
-    assign x28_t3    = regs[28];
-    assign x29_t4    = regs[29];
-    assign x30_t5    = regs[30];
-    assign x31_t6    = regs[31];
+    // Debug purpose only
+    assign x1_ra    = regs[1];
+    assign x2_sp    = regs[2];
+    assign x3_gp    = regs[3];
+    assign x4_tp    = regs[4];
+    assign x5_t0    = regs[5];
+    assign x6_t1    = regs[6];
+    assign x7_t2    = regs[7];
+    assign x8_s0_fp = regs[8];
+    assign x9_s1    = regs[9];
+    assign x10_a0   = regs[10];
+    assign x11_a1   = regs[11];
+    assign x12_a2   = regs[12];
+    assign x13_a3   = regs[13];
+    assign x14_a4   = regs[14];
+    assign x15_a5   = regs[15];
+    assign x16_a6   = regs[16];
+    assign x17_a7   = regs[17];
+    assign x18_s2   = regs[18];
+    assign x19_s3   = regs[19];
+    assign x20_s4   = regs[20];
+    assign x21_s5   = regs[21];
+    assign x22_s6   = regs[22];
+    assign x23_s7   = regs[23];
+    assign x24_s8   = regs[24];
+    assign x25_s9   = regs[25];
+    assign x26_s10  = regs[26];
+    assign x27_s11  = regs[27];
+    assign x28_t3   = regs[28];
+    assign x29_t4   = regs[29];
+    assign x30_t5   = regs[30];
+    assign x31_t6   = regs[31];
 
 endmodule
 
diff --git a/test/c_testsuite/config.cfg b/test/c_testsuite/config.cfg
new file mode 100644
index 0000000..19f8bfa
--- /dev/null
+++ b/test/c_testsuite/config.cfg
@@ -0,0 +1,6 @@
+XLEN,32
+CACHE_EN,1
+CACHE_BLOCK_W,128
+GEN_EIRQ,0
+ERROR_STATUS_X31,1
+USER_MODE,0
diff --git a/test/c_testsuite/run.sh b/test/c_testsuite/run.sh
index 884b7f8..c9fc9e9 100755
--- a/test/c_testsuite/run.sh
+++ b/test/c_testsuite/run.sh
@@ -11,12 +11,12 @@
 # Variables and setup
 #------------------------------------------------------------------------------
 
+cfg_file="config.cfg"
+
 # Timeout upon which the simulation is ran
 TIMEOUT=200000
 # Minumum value the program counter should reach in bytes
 MIN_PC=65692
-# Check X31 used to detect testcase execution error
-ERROR_STATUS_X31=1
 
 source ../common/functions.sh
 
@@ -35,18 +35,17 @@ main() {
 
     # Clean up compiled applications and exit
     if [ $do_clean -eq 1 ]; then
-        clean
         for dir in tests/*/; do
             if [ "$dir" != "tests/common/" ]; then
                 echo "INFO: Clean $dir"
                 make clean -C "$dir";
             fi
         done
-        exit 0;
+        clean
     fi
 
     # Build all applications
-    if [ $NO_COMPILE -eq 0 ]; then
+    if [ "$NO_COMPILE" -eq 0 ]; then
         echo "INFO: C tests"
         set -e
         for dir in tests/*/; do
@@ -60,17 +59,12 @@ main() {
 
     # If user specified a testcase, or a testsuite, use it
     if [[ -n $TC ]]; then
-        run_testsuite "$TC"
+        run_testsuite "$TC" "$cfg_file"
     # Else run all the supported testsuite
     else
         # Execute the testsuites
-        run_testsuite "./tests/*.v"
+        run_testsuite "./tests/*.v" "$cfg_file"
     fi
-
-    # OK, sounds good, exit gently
-    echo -e "${GREEN}SUCCESS: C testsuite successfully terminated ^^${NC}"
-
-    exit 0
 }
 
 main "$@"
diff --git a/test/common/friscv_testbench.sv b/test/common/friscv_testbench.sv
index 4b51dc5..56a4b35 100644
--- a/test/common/friscv_testbench.sv
+++ b/test/common/friscv_testbench.sv
@@ -76,6 +76,10 @@ module friscv_testbench(
     `define TB_CHOICE 0
     `endif
 
+    `ifndef USER_MODE
+    `define USER_MODE 0
+    `endif
+
     parameter TB_CHOICE = (`TB_CHOICE==0) ? "CORE" : "PLATFORM";
 
     // Instruction length
@@ -102,7 +106,7 @@ module friscv_testbench(
     // Support supervisor mode
     parameter SUPERVISOR_MODE = 0;
     // Support user mode
-    parameter USER_MODE = 1;
+    parameter USER_MODE = `USER_MODE;
     // Insert a pipeline on instruction bus coming from the controller
     parameter PROCESSING_BUS_PIPELINE = 1;
 
diff --git a/test/common/functions.sh b/test/common/functions.sh
index d9e8d2c..9f990f4 100755
--- a/test/common/functions.sh
+++ b/test/common/functions.sh
@@ -18,25 +18,16 @@ BLUE='\033[0;34m'
 GREEN='\033[0;32m'
 NC='\033[0m' # No Color
 
-# Architecture choice
-XLEN=32
-# Instruction width
-ILEN=32
-# Enable both instruction & data caches
-CACHE_EN=1
-# Cache block width in bits
-CACHE_BLOCK_W=128
-# Number of instruction per cache block
-INST_PER_BLOCK=$(($CACHE_BLOCK_W/$ILEN))
-# Boot address, will be determined by python during elf extraction
-BOOT_ADDR=0
-
 
 #----------------------------------------------------------------
 # This section gathers parameters enabled or setup conditionally
 # in a flow (WBA, C, RISCV, ...)
 #----------------------------------------------------------------
 
+# Used to format the RAM file
+INST_PER_LINE=
+# Boot address, will be determined by python during elf extraction
+BOOT_ADDR=0
 # Force run without trying to compile again C or ASM programs
 # Can be overridden by -- no-compile argument
 NO_COMPILE=0
@@ -54,8 +45,6 @@ TC=
 [[ -z $NO_VCD ]] && NO_VCD=0
 # INTERACTIVE enable a UART to read/write from Verilator
 [[ -z $INTERACTIVE ]] && INTERACTIVE=0
-# Generate an external IRQ in the core
-[[ -z $GEN_EIRQ ]] && GEN_EIRQ=0
 # RAM is by default in compliance mode
 [[ -z $RAM_MODE ]] && RAM_MODE="compliance"
 
@@ -66,6 +55,7 @@ TC=
 [[ -z $TRACE_FETCHER ]] && TRACE_FETCHER=1
 [[ -z $TRACE_PUSHER ]] && TRACE_PUSHER=1
 [[ -z $TRACE_TB_RAM ]] && TRACE_TB_RAM=1
+[[ -z $TRACE_REGISTERS ]] && TRACE_REGISTERS=1
 
 # Variable used to check if RTL sources or testbench changed. Only compile if 1
 to_compile=0
@@ -75,6 +65,27 @@ ts_res=""
 ts_ret=0
 
 
+#------------------------------------------------------------------------------
+# Read a configuration file listing parameters and values, comma separated
+#------------------------------------------------------------------------------
+read_config() {
+
+    cen=0 # cache enable
+    cw=32 # cache width
+
+    DEFINES="FRISV_SIM=1;USE_SVL=1;"
+
+    while IFS=, read -r name value; do
+        DEFINES="${DEFINES}${name}=${value};"
+        [[ "$name" == "CACHE_BLOCK_W" ]] && cw="$value"
+        [[ "$name" == "CACHE_EN" ]] && cen="$value"
+    done < "$1"
+
+    # Compute the number of instruction per line to format in RAM init file for the instruction cache
+    [[ "$cen" -eq 1 ]] && INST_PER_LINE=$(($cw/32)) || INST_PER_LINE=1
+}
+#------------------------------------------------------------------------------
+
 #------------------------------------------------------------------------------
 # Clean compiled programs
 #------------------------------------------------------------------------------
@@ -98,14 +109,11 @@ clean() {
 
 get_defines() {
 
+    read_config "$1"
+
     # Print testcase description and its configuration
-    echo ""
-    echo -e "${BLUE}INFO: Execute ${test}${NC}"
-    echo ""
-    echo "  - XLEN:             $XLEN"
+    echo "  - Config file:      $cfg_file"
     echo "  - BOOT_ADDR:        $BOOT_ADDR"
-    echo "  - CACHE_EN:         $CACHE_EN"
-    echo "  - CACHE_BLOCK_W:    $CACHE_BLOCK_W"
     echo "  - TIMEOUT:          $TIMEOUT"
     echo "  - MIN_PC:           $MIN_PC"
     echo "  - TB_CHOICE:        $TB_CHOICE (0=CORE, 1=PLATFORM)"
@@ -113,36 +121,24 @@ get_defines() {
     echo "  - SIMULATOR:        $SIM"
     echo "  - NO_VCD:           $NO_VCD"
     echo "  - INTERACTIVE:      $INTERACTIVE"
-    echo "  - ERROR_STATUS_X31: $ERROR_STATUS_X31"
-    echo "  - GEN_EIRQ:         $GEN_EIRQ"
     echo "  - RAM_MODE:         $RAM_MODE"
-    echo "  - TRACE_CONTROL:    $TRACE_CONTROL"
-    echo "  - TRACE_CACHE:      $TRACE_CACHE"
-    echo "  - TRACE_BLOCKS:     $TRACE_BLOCKS"
-    echo "  - TRACE_FETCHER:    $TRACE_FETCHER"
-    echo "  - TRACE_PUSHER:     $TRACE_PUSHER"
-    echo "  - TRACE_TB_RAM:     $TRACE_TB_RAM"
-
-    DEFINES="${DEFINES}XLEN=$XLEN;"
+
     DEFINES="${DEFINES}BOOT_ADDR=$BOOT_ADDR;"
-    DEFINES="${DEFINES}CACHE_EN=$CACHE_EN;"
-    DEFINES="${DEFINES}CACHE_BLOCK_W=$CACHE_BLOCK_W;"
     DEFINES="${DEFINES}TIMEOUT=$TIMEOUT;"
     DEFINES="${DEFINES}MIN_PC=$MIN_PC;"
     DEFINES="${DEFINES}TB_CHOICE=$TB_CHOICE;"
     DEFINES="${DEFINES}TCNAME=$test_name;"
     DEFINES="${DEFINES}INTERACTIVE=$INTERACTIVE;"
-    DEFINES="${DEFINES}ERROR_STATUS_X31=$ERROR_STATUS_X31;"
-    DEFINES="${DEFINES}GEN_EIRQ=$GEN_EIRQ;"
 
     [[ $RAM_MODE == "performance" ]] && DEFINES="${DEFINES}RAM_MODE_PERF=1;"
 
-    [[ $TRACE_CONTROL -eq 1 ]] && DEFINES="${DEFINES}TRACE_CONTROL=$TRACE_CONTROL;"
-    [[ $TRACE_CACHE   -eq 1 ]] && DEFINES="${DEFINES}TRACE_CACHE=$TRACE_CACHE;"
-    [[ $TRACE_BLOCKS  -eq 1 ]] && DEFINES="${DEFINES}TRACE_BLOCKS=$TRACE_BLOCKS;"
-    [[ $TRACE_FETCHER -eq 1 ]] && DEFINES="${DEFINES}TRACE_FETCHER=$TRACE_FETCHER;"
-    [[ $TRACE_PUSHER  -eq 1 ]] && DEFINES="${DEFINES}TRACE_PUSHER=$TRACE_PUSHER;"
-    [[ $TRACE_TB_RAM  -eq 1 ]] && DEFINES="${DEFINES}TRACE_TB_RAM=$TRACE_TB_RAM;"
+    [[ $TRACE_CONTROL   -eq 1 ]] && DEFINES="${DEFINES}TRACE_CONTROL=$TRACE_CONTROL;"
+    [[ $TRACE_CACHE     -eq 1 ]] && DEFINES="${DEFINES}TRACE_CACHE=$TRACE_CACHE;"
+    [[ $TRACE_BLOCKS    -eq 1 ]] && DEFINES="${DEFINES}TRACE_BLOCKS=$TRACE_BLOCKS;"
+    [[ $TRACE_FETCHER   -eq 1 ]] && DEFINES="${DEFINES}TRACE_FETCHER=$TRACE_FETCHER;"
+    [[ $TRACE_PUSHER    -eq 1 ]] && DEFINES="${DEFINES}TRACE_PUSHER=$TRACE_PUSHER;"
+    [[ $TRACE_REGISTERS -eq 1 ]] && DEFINES="${DEFINES}TRACE_REGISTERS=$TRACE_REGISTERS;"
+    [[ $TRACE_TB_RAM    -eq 1 ]] && DEFINES="${DEFINES}TRACE_TB_RAM=$TRACE_TB_RAM;"
 
     [[ $NO_VCD -eq 1 ]] && DEFINES="${DEFINES}NO_VCD=1;"
 
@@ -217,6 +213,8 @@ run_tests() {
     # Execute one by one the available tests
     for test in $1; do
 
+        echo -e "${BLUE}INFO: Execute ${test}${NC}"
+
         # Go to run-only once we know the testbench has been compiled one time
         if [[ $did_compile -eq 1 ]]; then
             run_only="-run-only"
@@ -232,14 +230,8 @@ run_tests() {
         test_file=$(basename "$test")
         test_name=${test_file%%.*}
 
-        ## SVLogger and so extra logging/tracing can be deactivated. Usefull for Apps testsuite
-        if [[ -z $NO_SVL ]]; then
-            DEFINES="FRISV_SIM=1;USE_SVL=1;"
-        else
-            DEFINES="FRISV_SIM=1;"
-        fi
-
-        get_defines
+        # Grab all defines necessary for testbench & flow setup
+        get_defines "$2"
 
         # Execute the testcase with SVUT
         svutRun -t ./friscv_testbench.sv \
@@ -254,7 +246,7 @@ run_tests() {
         # Grab the return code used later to determine the compliance status
         ts_ret=$((ts_ret+_tc_ret))
         # Prepare results to print
-        gather_result "$(basename "$test" .v)" "$_tc_ret"
+        gather_result "$test_name" "$_tc_ret"
         # Pack all intermediate results into a single file
         cat tc.log >> simulation.log
         rm -f tc.log
@@ -264,7 +256,7 @@ run_tests() {
             cp ./friscv_testbench.vcd "./tests/$test_name.vcd"
         fi
 
-        # Create the trace of the C execution
+        # Create the trace of the C execution (function jumps)
         if [ -f "./trace_control.csv" ] && [ -f "tests/${test_name}.symbols" ]; then
             ../common/trace.py --itrace trace_control.csv \
                                --otrace "tests/${test_name}_trace.csv" \
@@ -323,6 +315,9 @@ check_status() {
         echo "  - error count: $ec"
         echo "  - testsuite status: $ts_ret"
         exit 1
+    else
+        # OK, sounds good, exit gently
+        echo -e "${GREEN}SUCCESS: Testsuite successfully terminated ^^${NC}"
     fi
 }
 #------------------------------------------------------------------------------
@@ -336,18 +331,6 @@ get_args() {
 
     while [ "$1" != "" ]; do
         case $1 in
-            --cache_en )
-                shift
-                CACHE_EN=$1
-            ;;
-            --cache_block )
-                shift
-                CACHE_BLOCK_W=$1
-            ;;
-            -x | --xlen )
-                shift
-                XLEN=$1
-            ;;
             -c | --clean )
                 do_clean=1
             ;;
@@ -374,6 +357,10 @@ get_args() {
                 shift
                 SIM=$1
             ;;
+            --cfg )
+                shift
+                cfg_file=$1
+            ;;
             --novcd )
                 shift
                 NO_VCD=1
@@ -407,15 +394,13 @@ usage: bash ./run.sh ...
 
 -c    | --clean             Clean-up and exit
 -h    | --help              Brings up this menu
--x    | --xlen              XLEN, 32 or 64 bits (32 bits by default)
 -t    | --timeout           Timeout in number of cycles before the simulation stops (10000 by default, 0 inactivate it)
-        --cache_en          Enable instruction and data caches (Enabled by default)
-        --cache_block       Cache line width in bits (128 bits by default)
         --tb                'core' or 'platform' ('core' by default)
         --tc                A specific testcase to launch, can use wildcard if enclosed with ' (Run all by default)
         --simulator         Choose between icarus or verilator (icarus is default)
         --novcd             Don't dump VCD during simulation (Dump by default)
         --nocompile         Don't try to compile C or assembler (CI tests only)
+        --cfg               Pass a specific configuration files
 EOF
 }
 #------------------------------------------------------------------------------
diff --git a/test/common/run.sh b/test/common/run.sh
deleted file mode 100755
index bec058d..0000000
--- a/test/common/run.sh
+++ /dev/null
@@ -1,62 +0,0 @@
-#!/usr/bin/env bash
-
-# distributed under the mit license
-# https://opensource.org/licenses/mit-license.php
-
-# -e: exit if one command fails
-# -o pipefail: causes a pipeline to fail if any command fails
-# set -e -o pipefail
-
-#------------------------------------------------------------------------------
-# Variables and setup
-#------------------------------------------------------------------------------
-
-# Don't assert a testbench error if X31 is asserted
-ERROR_STATUS_X31=1
-
-source ../common/functions.sh
-
-
-#------------------------------------------------------------------------------
-# Main
-#------------------------------------------------------------------------------
-
-main() {
-
-    echo "INFO: Start RISCV Compliance Testsuite"
-    PID=$$
-    echo "PID: $PID"
-
-    get_args "$@"
-
-    # Then clean temp files into testcase folders
-    if [ $do_clean -eq 1 ]; then clean; fi
-
-    # Compile appplication if necessary
-    if [ $NO_COMPILE -eq 0 ]; then
-        if [ -n "$(find tests/ -maxdepth 1 -name \*.v -print -quit)" ] ; then
-            echo "INFO: Found compiled programs, execute ./run -C to rebuild from scratch"
-        else
-            set -e
-            make -C ./tests XLEN=$XLEN
-            set +e
-        fi
-    fi
-
-    # If user specified a testcase, or a testsuite, use it
-    if [[ -n $TC ]]; then
-        run_testsuite "$TC"
-    # Else run all the supported testsuite
-    else
-        # Execute the testsuites
-        run_testsuite "./tests/rv32ui-p*.v"
-        if [[ -f "./tests/rv32um-p*.v" ]]; then run_testsuite "./tests/rv32um-p*.v"; fi
-    fi
-
-    # OK, sounds good, exit gently
-    echo -e "${GREEN}SUCCESS: Testsuite successfully terminated ^^${NC}"
-
-    exit 0
-}
-
-main "$@"
diff --git a/test/priv_sec_testsuite/config.cfg b/test/priv_sec_testsuite/config.cfg
new file mode 100644
index 0000000..17fb332
--- /dev/null
+++ b/test/priv_sec_testsuite/config.cfg
@@ -0,0 +1,6 @@
+XLEN,32
+CACHE_EN,1
+CACHE_BLOCK_W,128
+GEN_EIRQ,1
+ERROR_STATUS_X31,1
+USER_MODE,1
diff --git a/test/priv_sec_testsuite/run.sh b/test/priv_sec_testsuite/run.sh
index 86974fc..eb74012 100755
--- a/test/priv_sec_testsuite/run.sh
+++ b/test/priv_sec_testsuite/run.sh
@@ -7,18 +7,10 @@
 # -o pipefail: causes a pipeline to fail if any command fails
 # set -e -o pipefail
 
-#------------------------------------------------------------------------------
-# Variables and setup
-#------------------------------------------------------------------------------
-
-# Don't assert a testbench error if X31 is asserted
-ERROR_STATUS_X31=1
-# Generate an external IRQ on the EIRQ IO
-GEN_EIRQ=1
+cfg_file="config.cfg"
 
 source ../common/functions.sh
 
-
 #------------------------------------------------------------------------------
 # Main
 #------------------------------------------------------------------------------
@@ -35,30 +27,24 @@ main() {
     if [ $do_clean -eq 1 ]; then clean; fi
 
     # Compile appplication if necessary
-    if [ $NO_COMPILE -eq 0 ]; then
+    if [ "$NO_COMPILE" -eq 0 ]; then
         if [ -n "$(find tests/ -maxdepth 1 -name \*.v -print -quit)" ] ; then
             echo "INFO: Found compiled programs, execute ./run -C to rebuild from scratch"
         else
             set -e
-            make -C ./tests XLEN=$XLEN
+            make -C ./tests XLEN=32
             set +e
         fi
     fi
 
     # If user specified a testcase, or a testsuite, use it
     if [[ -n $TC ]]; then
-        run_testsuite "$TC"
+        run_testsuite "$TC" "$cfg_file"
     # Else run all the supported testsuite
     else
         # Execute the testsuites
-        run_testsuite "./tests/rv32ui-p*.v"
-        if [[ -f "./tests/rv32um-p*.v" ]]; then run_testsuite "./tests/rv32um-p*.v"; fi
+        run_testsuite "./tests/rv32ui-p*.v" "$cfg_file"
     fi
-
-    # OK, sounds good, exit gently
-    echo -e "${GREEN}SUCCESS: Testsuite successfully terminated ^^${NC}"
-
-    exit 0
 }
 
 main "$@"
diff --git a/test/riscv-tests/config.cfg b/test/riscv-tests/config.cfg
new file mode 100644
index 0000000..dd5f6b4
--- /dev/null
+++ b/test/riscv-tests/config.cfg
@@ -0,0 +1,6 @@
+XLEN,32
+CACHE_EN,1
+CACHE_BLOCK_W,128
+GEN_EIRQ,1
+ERROR_STATUS_X31,1
+USER_MODE,0
diff --git a/test/riscv-tests/run.sh b/test/riscv-tests/run.sh
deleted file mode 120000
index aee911b..0000000
--- a/test/riscv-tests/run.sh
+++ /dev/null
@@ -1 +0,0 @@
-../common/run.sh
\ No newline at end of file
diff --git a/test/riscv-tests/run.sh b/test/riscv-tests/run.sh
new file mode 100755
index 0000000..7bd0eb1
--- /dev/null
+++ b/test/riscv-tests/run.sh
@@ -0,0 +1,58 @@
+#!/usr/bin/env bash
+
+# distributed under the mit license
+# https://opensource.org/licenses/mit-license.php
+
+# -e: exit if one command fails
+# -o pipefail: causes a pipeline to fail if any command fails
+# set -e -o pipefail
+
+#------------------------------------------------------------------------------
+# Variables and setup
+#------------------------------------------------------------------------------
+
+cfg_file="config.cfg"
+source ../common/functions.sh
+
+
+#------------------------------------------------------------------------------
+# Main
+#------------------------------------------------------------------------------
+
+main() {
+
+    echo "INFO: Start RISCV Compliance Testsuite"
+    PID=$$
+    echo "PID: $PID"
+
+    get_args "$@"
+
+    # Then clean temp files into testcase folders
+    if [ $do_clean -eq 1 ]; then clean; fi
+
+    # Compile appplication if necessary
+    if [ "$NO_COMPILE" -eq 0 ]; then
+        if [ -n "$(find tests/ -maxdepth 1 -name \*.v -print -quit)" ] ; then
+            echo "INFO: Found compiled programs, execute ./run -C to rebuild from scratch"
+        else
+            set -e
+            make -C ./tests
+            set +e
+        fi
+    fi
+
+    # If user specified a testcase, or a testsuite, use it
+    if [[ -n $TC ]]; then
+        run_testsuite "$TC" "$cfg_file"
+    # Else run all the supported testsuite
+    else
+        # Execute the testsuites
+        run_testsuite "./tests/rv32ui-p*.v" "$cfg_file"
+        # Continue to execute if m extension tests exist
+        if [[ -f "./tests/rv32um-p*.v" ]]; then
+            run_testsuite "./tests/rv32um-p*.v" "$cfg_file"
+        fi
+    fi
+}
+
+main "$@"
diff --git a/test/wba_testsuite/config.cfg b/test/wba_testsuite/config.cfg
new file mode 100644
index 0000000..dd5f6b4
--- /dev/null
+++ b/test/wba_testsuite/config.cfg
@@ -0,0 +1,6 @@
+XLEN,32
+CACHE_EN,1
+CACHE_BLOCK_W,128
+GEN_EIRQ,1
+ERROR_STATUS_X31,1
+USER_MODE,0
diff --git a/test/wba_testsuite/run.sh b/test/wba_testsuite/run.sh
index 86974fc..eb74012 100755
--- a/test/wba_testsuite/run.sh
+++ b/test/wba_testsuite/run.sh
@@ -7,18 +7,10 @@
 # -o pipefail: causes a pipeline to fail if any command fails
 # set -e -o pipefail
 
-#------------------------------------------------------------------------------
-# Variables and setup
-#------------------------------------------------------------------------------
-
-# Don't assert a testbench error if X31 is asserted
-ERROR_STATUS_X31=1
-# Generate an external IRQ on the EIRQ IO
-GEN_EIRQ=1
+cfg_file="config.cfg"
 
 source ../common/functions.sh
 
-
 #------------------------------------------------------------------------------
 # Main
 #------------------------------------------------------------------------------
@@ -35,30 +27,24 @@ main() {
     if [ $do_clean -eq 1 ]; then clean; fi
 
     # Compile appplication if necessary
-    if [ $NO_COMPILE -eq 0 ]; then
+    if [ "$NO_COMPILE" -eq 0 ]; then
         if [ -n "$(find tests/ -maxdepth 1 -name \*.v -print -quit)" ] ; then
             echo "INFO: Found compiled programs, execute ./run -C to rebuild from scratch"
         else
             set -e
-            make -C ./tests XLEN=$XLEN
+            make -C ./tests XLEN=32
             set +e
         fi
     fi
 
     # If user specified a testcase, or a testsuite, use it
     if [[ -n $TC ]]; then
-        run_testsuite "$TC"
+        run_testsuite "$TC" "$cfg_file"
     # Else run all the supported testsuite
     else
         # Execute the testsuites
-        run_testsuite "./tests/rv32ui-p*.v"
-        if [[ -f "./tests/rv32um-p*.v" ]]; then run_testsuite "./tests/rv32um-p*.v"; fi
+        run_testsuite "./tests/rv32ui-p*.v" "$cfg_file"
     fi
-
-    # OK, sounds good, exit gently
-    echo -e "${GREEN}SUCCESS: Testsuite successfully terminated ^^${NC}"
-
-    exit 0
 }
 
 main "$@"
diff --git a/test/wba_testsuite/tests/rv64ui/test5.S b/test/wba_testsuite/tests/rv64ui/test5.S
index c50fd09..4f7d5e2 100644
--- a/test/wba_testsuite/tests/rv64ui/test5.S
+++ b/test/wba_testsuite/tests/rv64ui/test5.S
@@ -5,7 +5,7 @@
 #include "test_macros.h"
 
 # Test 5: CSRs: Throttle execution by accessing the ISA CSRs
-# 
+#
 # This testcase executes memory and arithmetic instructions break up by CSR
 # accesses. CSR instructions require several cycles to complete, thus could lead
 # to failure in control unit.