From 8db051843764d8135d6cff981fe8ef40615d0ed8 Mon Sep 17 00:00:00 2001 From: Damien Pretet Date: Sun, 3 Sep 2023 09:39:18 +0200 Subject: [PATCH] Fix: enclose function around ifdef to avoid yosys synthesis error --- rtl/friscv_registers.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/rtl/friscv_registers.sv b/rtl/friscv_registers.sv index 4e61a3c..0a538e4 100644 --- a/rtl/friscv_registers.sv +++ b/rtl/friscv_registers.sv @@ -76,6 +76,7 @@ module friscv_registers input wire [XLEN -1:0] csr_rd_val ); + `ifdef TRACE_REGISTERS //------------------------------------------------ // Function to print register name and information // @i: register number to get info @@ -116,6 +117,7 @@ module friscv_registers if (i==30) get_name = " t5 (temporary register 5)"; if (i==31) get_name = " t6 (temporary register 6)"; endfunction + `endif // E extension limiting the register number to 16