diff --git a/doc/friscv.drawio b/doc/friscv.drawio index 2b75fab..78cfd75 100644 --- a/doc/friscv.drawio +++ b/doc/friscv.drawio @@ -1,6 +1,6 @@ - + - + @@ -5003,4 +5003,194 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md index 997b36b..62c0ef1 100644 --- a/doc/project_mgt_hw.md +++ b/doc/project_mgt_hw.md @@ -5,7 +5,6 @@ - [-] Support U-mode - [-] Support PMP/PMA - [ ] Atomic operations for single core - - [ ] fence/fence.i instructions - [ ] AXI Exception management with a CLIC - [ ] Zc extension diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv index 770c15e..1b28064 100644 --- a/rtl/friscv_control.sv +++ b/rtl/friscv_control.sv @@ -1288,12 +1288,12 @@ module friscv_control (wfi_tw) ? 1'b1 : '0 ; - assign illegal_csr = (priv_mode==`MMODE || !sys[`IS_CSR]) ? '0 : - (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? 1'b1 : // Cycle - (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? 1'b1 : // Time - (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? 1'b1 : // Instret - (csr[11:4]=='hFC) ? 1'b1 : // Custom perf. registers - (csr[ 9:8]!=2'b00) ? 1'b1 : // M-Mode only registers + assign illegal_csr = (priv_mode==`MMODE || !sys[`IS_CSR]) ? 1'b0 : + (csr[11:0]=='hC00 && !sb_mcounteren[0]) ? inst_ready : // Cycle + (csr[11:0]=='hC01 && !sb_mcounteren[1]) ? inst_ready : // Time + (csr[11:0]=='hC02 && !sb_mcounteren[2]) ? inst_ready : // Instret + (csr[11:4]=='hFC) ? inst_ready : // Custom perf. registers + (csr[ 9:8]!=2'b00) ? inst_ready : // M-Mode only registers 1'b0 ; end else begin : NO_UMODE diff --git a/rtl/friscv_pmp_region.sv b/rtl/friscv_pmp_region.sv index a5eda9b..dd4cbe3 100644 --- a/rtl/friscv_pmp_region.sv +++ b/rtl/friscv_pmp_region.sv @@ -69,7 +69,7 @@ module friscv_pmp_region logic [RLEN-1:0] mask; logic [XLEN-1:0] size; begin - size = 3; + size = 2; mask = '1 << size; base = {csr_addr, 2'b0} & mask; get_na4 = {mask, base}; diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw index 1b42864..a191e72 100644 --- a/test/common/debug_platform_verilator.gtkw +++ b/test/common/debug_platform_verilator.gtkw @@ -1,29 +1,33 @@ [*] [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Thu Oct 26 19:01:31 2023 +[*] Wed Nov 1 17:02:29 2023 [*] [dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd" -[dumpfile_mtime] "Thu Oct 26 18:59:38 2023" -[dumpfile_size] 7831491 +[dumpfile_mtime] "Wed Nov 1 17:00:10 2023" +[dumpfile_size] 224490635 [savefile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/debug_platform_verilator.gtkw" -[timestart] 1868 -[size] 1440 900 +[timestart] 6064 +[size] 2560 1440 [pos] -1 -1 -*-3.355745 1895 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-5.355745 6248 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] friscv_testbench. [treeopen] friscv_testbench.friscv_testbench. [treeopen] friscv_testbench.friscv_testbench.genblk2. +[treeopen] friscv_testbench.friscv_testbench.genblk2.axi4l_ram. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu. +[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[0].REGION_ACTIVE. +[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing. +[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE. +[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks. -[sst_width] 255 -[signals_width] 230 +[sst_width] 365 +[signals_width] 334 [sst_expanded] 1 -[sst_vpaned_height] 397 +[sst_vpaned_height] 365 @c00200 -AXI4-lite RAM @22 @@ -93,7 +97,7 @@ friscv_testbench.friscv_testbench.genblk2.axi4l_ram.p1_bvalid - @1401200 -Interconnect -@c00200 +@800200 -CSRs @200 - @@ -136,9 +140,22 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ctrl_mepc[31:0] @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0] -@1401200 +@200 +- +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_rden +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr_wren +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.csr[11:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.newval[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.oldval[31:0] +@200 +- +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.pmpcfg0[31:0] +@1000200 -CSRs -@c00200 +@800200 -ISA Regsiters @200 - @@ -176,7 +193,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x30_t5[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x31_t6[31:0] @200 - -@1401200 +@1000200 -ISA Regsiters @c00200 -iCache @@ -245,7 +262,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rid[7:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.priv_mode[1:0] @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] -@201 +@200 - @28 [color] 3 @@ -287,6 +304,8 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ro_wr friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_addr_misaligned @200 - +@c00200 +-CSRs @c00022 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0] @28 @@ -410,10 +429,65 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtie friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtip @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sb_mtvec[31:0] +@1401200 +-CSRs @200 - @1000200 -control +@800200 +-Memfy +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_valid +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_ready +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.mpu_allow[3:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.addr[31:0] +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_ready_fsm +@200 +- +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awaddr[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awid[7:0] +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awready +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awvalid +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.wdata[31:0] +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.bvalid +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.bresp[1:0] +@200 +- +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.araddr[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arid[7:0] +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arready +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arvalid +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.rvalid +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.rdata[31:0] +@200 +- +@28 +[color] 3 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.waiting_rd_cpl +[color] 3 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.waiting_wr_cpl +@200 +- +@28 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.check_access +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.load_access_fault +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.load_misaligned +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_access_fault +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_misaligned +@200 +- +@1000200 +-Memfy @c00200 -Registers @22 @@ -450,7 +524,7 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x30_t5[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x31_t6[31:0] @1401200 -Registers -@c00200 +@800200 -MPU @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.imem_addr[31:0] @@ -482,27 +556,6 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_active[15:0] @1401200 -PMP Cfg @c00200 --PMP Mask -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask0[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask1[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask2[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask3[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask4[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask5[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask6[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask7[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask8[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask9[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask10[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask11[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask12[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask13[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask14[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask15[31:0] -@1401200 --PMP Mask -@800200 -PMP Base @22 friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_base0[31:0] @@ -521,149 +574,49 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_base12[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_base13[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_base14[31:0] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_base15[31:0] -@1000200 +@1401200 -PMP Base +@c00200 +-PMP Mask +@22 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask0[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask1[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask2[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask3[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask4[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask5[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask6[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask7[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask8[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask9[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask10[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask11[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask12[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask13[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask14[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.pmp_mask15[31:0] @1401200 --MPU +-PMP Mask @c00200 --Memfy -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_ready +-Region 0 @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.mpu_allow[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.addr[31:0] -@200 -- +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[0].REGION_ACTIVE.pmp_region.pmp_cfg[7:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[0].REGION_ACTIVE.pmp_region.pmp_addr[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[0].REGION_ACTIVE.pmp_region.pmp_base[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[0].REGION_ACTIVE.pmp_region.pmp_mask[31:0] +@1401200 +-Region 0 +@800200 +-Region 1 @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awvalid -@200 -- +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_cfg[7:0] +@23 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.mpu.MPU_ON.PMP_REGION_CHECKERS[1].REGION_ACTIVE.pmp_region.pmp_addr[31:0] @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arvalid -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.check_access -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.load_access_fault -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.load_misaligned -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_access_fault -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.store_misaligned -@200 -- -@c00022 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -@28 -(0)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(1)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(2)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(3)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(4)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(5)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(6)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(7)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(8)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(9)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(10)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(11)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(12)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(13)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(14)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(15)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(16)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(17)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(18)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(19)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(20)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(21)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(22)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(23)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(24)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] -(25)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_exceptions[99:0] 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https://opensource.org/licenses/mit-license.php + +.equ OFF, 0 +.equ TOR_RWX, 0x0F +.equ TOR_RW, 0x0B +.equ TOR_RX, 0x0D +.equ NA4_RWX, 0x17 +.equ NA4_RW, 0x13 +.equ NA4_RX, 0x15 +.equ NAPOT_RWX, 0x1F +.equ NAPOT_RW , 0x1B +.equ NAPOT_RX , 0x1D + +.equ TOR_LRWX, 0x8F +.equ TOR_LRW, 0x8B +.equ TOR_LRX, 0x8D +.equ NA4_LRWX, 0x97 +.equ NA4_LRW, 0x93 +.equ NA4_LRX, 0x95 +.equ NAPOT_LRWX, 0x9F +.equ NAPOT_LRW , 0x9B +.equ NAPOT_LRX , 0x9D + +.equ TOR, 0x08 +.equ NA4, 0x10 +.equ NAPOT, 0x18 diff --git a/test/priv_sec_testsuite/tests/env/pmp_service.S b/test/priv_sec_testsuite/tests/env/pmp_service.S new file mode 100644 index 0000000..5afedcf --- /dev/null +++ b/test/priv_sec_testsuite/tests/env/pmp_service.S @@ -0,0 +1,484 @@ +# distributed under the mit license +# https://opensource.org/licenses/mit-license.php + +#include "pmp.S" + +//////////////////////////////////////////// +// Erase all PMP configurations +//////////////////////////////////////////// +ERASE_PMP: + csrw pmpcfg0, zero + csrw pmpcfg1, zero + csrw pmpcfg2, zero + csrw pmpcfg3, zero + csrw pmpaddr0, zero + csrw pmpaddr1, zero + csrw pmpaddr2, zero + csrw pmpaddr3, zero + csrw pmpaddr4, zero + csrw pmpaddr5, zero + csrw pmpaddr6, zero + csrw pmpaddr7, zero + csrw pmpaddr8, zero + csrw pmpaddr9, zero + csrw pmpaddr10, zero + csrw pmpaddr11, zero + csrw pmpaddr12, zero + csrw pmpaddr13, zero + csrw pmpaddr14, zero + csrw pmpaddr15, zero + j RET_ECALL + +/////////////////////////////////////////////////////////////////////// +// Write all PMP registers to check it's accessible without limitations +/////////////////////////////////////////////////////////////////////// +CHECK_RW_PMP: + + li t0, 0 + // pmpaddr0 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr0, t4 + csrr t5, pmpaddr0 + bne t4, t5, fail + csrw pmpaddr0, x0 + + // pmpaddr1 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr1, t4 + csrr t5, pmpaddr1 + bne t4, t5, fail + csrw pmpaddr1, x0 + + // pmpaddr2 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr2, t4 + csrr t5, pmpaddr2 + bne t4, t5, fail + csrw pmpaddr2, x0 + + // pmpaddr3 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr3, t4 + csrr t5, pmpaddr3 + bne t4, t5, fail + csrw pmpaddr3, x0 + + // pmpaddr4 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr4, t4 + csrr t5, pmpaddr4 + bne t4, t5, fail + csrw pmpaddr4, x0 + + // pmpaddr5 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr5, t4 + csrr t5, pmpaddr5 + bne t4, t5, fail + csrw pmpaddr5, x0 + + // pmpaddr6 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr6, t4 + csrr t5, pmpaddr6 + bne t4, t5, fail + csrw pmpaddr6, x0 + + // pmpaddr7 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr7, t4 + csrr t5, pmpaddr7 + bne t4, t5, fail + csrw pmpaddr7, x0 + + // pmpaddr8 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr8, t4 + csrr t5, pmpaddr8 + bne t4, t5, fail + csrw pmpaddr8, x0 + + // pmpaddr9 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr9, t4 + csrr t5, pmpaddr9 + bne t4, t5, fail + csrw pmpaddr9, x0 + + // pmpaddr10 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr10, t4 + csrr t5, pmpaddr10 + bne t4, t5, fail + csrw pmpaddr10, x0 + + // pmpaddr1 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr11, t4 + csrr t5, pmpaddr11 + bne t4, t5, fail + csrw pmpaddr11, x0 + + // pmpaddr12 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr12, t4 + csrr t5, pmpaddr12 + bne t4, t5, fail + csrw pmpaddr12, x0 + + // pmpaddr13 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr13, t4 + csrr t5, pmpaddr13 + bne t4, t5, fail + csrw pmpaddr13, x0 + + // pmpaddr14 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr14, t4 + csrr t5, pmpaddr14 + bne t4, t5, fail + csrw pmpaddr14, x0 + + // pmpaddr15 + lui t4, %hi(PMPADDR) + addi t4, t4, %lo(PMPADDR) + csrw pmpaddr15, t4 + csrr t5, pmpaddr15 + bne t4, t5, fail + csrw pmpaddr15, x0 + + // pmpcfg0 + lui t4, %hi(PMPCFG) + addi t4, t4, %lo(PMPCFG) + csrw pmpcfg0, t4 + csrr t5, pmpcfg0 + bne t4, t5, fail + csrw pmpcfg0, x0 + + // pmpcfg1 + lui t4, %hi(PMPCFG) + addi t4, t4, %lo(PMPCFG) + csrw pmpcfg1, t4 + csrr t5, pmpcfg1 + bne t4, t5, fail + csrw pmpcfg1, x0 + + // pmpcfg2 + lui t4, %hi(PMPCFG) + addi t4, t4, %lo(PMPCFG) + csrw pmpcfg2, t4 + csrr t5, pmpcfg2 + bne t4, t5, fail + csrw pmpcfg2, x0 + + // pmpaddr3 + lui t4, %hi(PMPCFG) + addi t4, t4, %lo(PMPCFG) + csrw pmpcfg3, t4 + csrr t5, pmpcfg3 + bne t4, t5, fail + csrw pmpcfg3, x0 + j RET_ECALL + +//////////////////////////////////////////// +# Enable asynchronous traps +//////////////////////////////////////////// +INTP_SERVICE: + # Enable IRQ + lui t5, %hi(MIE_ON) + addi t5, t5, %lo(MIE_ON) + csrr t4, mstatus + or t4, t4, t5 + csrw mstatus, t4 + # Enable EIRQ + lui t5, %hi(MEIE_ON) + addi t5, t5, %lo(MEIE_ON) + csrr t4, mie + or t4, t4, t5 + csrw mie, t4 + j RET_ECALL + +EXP_SERVICE: + addi s0, s0, 1 + # j RET_ECALL + mret + +//////////////////////////////////////////// +# Configure a NAPOT / NA4 region +//////////////////////////////////////////// +SET_NA4: +SET_NAPOT: + # napot_size + addi a2, a2, -1 + srli a2, a2, 3 + # pmp_addr + srli a1, a1, 2 + or a1, a1, a2 + j SET_PMP + + +//////////////////////////////////////////// +# Configure a TOR region +//////////////////////////////////////////// +SET_TOR: + // prepare address, must be store by removing 2 LSBs + srli a1, a1, 2 +SET_PMP: + // select the right pmpcfg place + li t0, 4 + blt a0, t0, CFGREG0 + li t0, 8 + blt a0, t0, CFGREG1 + li t0, 12 + blt a0, t0, CFGREG2 + li t0, 16 + blt a0, t0, CFGREG3 + // region number not supported (>16) + li a0, 1 + j RET_ECALL + +CFGREG0: + // load configuration to update + csrr t1, pmpcfg0 + // select pmp region to configure + li t0, 0 + beq t0, a0, 0f + li t0, 1 + beq t0, a0, 1f + li t0, 2 + beq t0, a0, 2f + li t0, 3 + beq t0, a0, 3f +0: + csrw pmpaddr0, a1 + li t0, 0xFFFFFF00 + and t1, t1, t0 + j 4f +1: + csrw pmpaddr1, a1 + li t0, 0xFFFF00FF + and t1, t1, t0 + slli a3, a3, 8 + j 4f +2: + csrw pmpaddr2, a1 + li t0, 0xFF00FFFF + and t1, t1, t0 + slli a3, a3, 16 + j 4f +3: + csrw pmpaddr3, a1 + li t0, 0x00FFFFFF + and t1, t1, t0 + slli a3, a3, 24 + j 4f +4: + // Store config and start MPU + or t1, t1, a3 + csrw pmpcfg0, t1 + j RET_ECALL + +CFGREG1: + // load configuration to update + csrr t1, pmpcfg1 + // select pmp region to configure + li t0, 0 + beq t0, a0, 0f + li t0, 1 + beq t0, a0, 1f + li t0, 2 + beq t0, a0, 2f + li t0, 3 + beq t0, a0, 3f +0: + csrw pmpaddr4, a1 + li t0, 0xFFFFFF00 + and t1, t1, t0 + j 4f +1: + csrw pmpaddr5, a1 + li t0, 0xFFFF00FF + and t1, t1, t0 + slli a3, a3, 8 + j 4f +2: + csrw pmpaddr6, a1 + li t0, 0xFF00FFFF + and t1, t1, t0 + slli a3, a3, 16 + j 4f +3: + csrw pmpaddr7, a1 + li t0, 0x00FFFFFF + and t1, t1, t0 + slli a3, a3, 24 + j 4f +4: + or t1, t1, a3 + csrw pmpcfg1, t1 + j RET_ECALL + +CFGREG2: + // load configuration to update + csrr t1, pmpcfg2 + // select pmp region to configure + li t0, 0 + beq t0, a0, 0f + li t0, 1 + beq t0, a0, 1f + li t0, 2 + beq t0, a0, 2f + li t0, 3 + beq t0, a0, 3f +0: + csrw pmpaddr8, a1 + li t0, 0xFFFFFF00 + and t1, t1, t0 + j 4f +1: + csrw pmpaddr9, a1 + li t0, 0xFFFF00FF + and t1, t1, t0 + slli a3, a3, 8 + j 4f +2: + li t0, 0xFF00FFFF + and t1, t1, t0 + slli a3, a3, 16 + j 4f +3: + csrw pmpaddr10, a1 + li t0, 0x00FFFFFF + and t1, t1, t0 + slli a3, a3, 24 + j 4f +4: + csrw pmpaddr11, a1 + or t1, t1, a3 + csrw pmpcfg2, t1 + j RET_ECALL + + +CFGREG3: + // load configuration to update + csrr t1, pmpcfg3 + // select pmp region to configure + li t0, 0 + beq t0, a0, 0f + li t0, 1 + beq t0, a0, 1f + li t0, 2 + beq t0, a0, 2f + li t0, 3 + beq t0, a0, 3f +0: + csrw pmpaddr12, a1 + li t0, 0xFFFFFF00 + and t1, t1, t0 + j 4f +1: + csrw pmpaddr13, a1 + li t0, 0xFFFF00FF + and t1, t1, t0 + slli a3, a3, 8 + j 4f +2: + csrw pmpaddr14, a1 + li t0, 0xFF00FFFF + and t1, t1, t0 + slli a3, a3, 16 + j 4f +3: + csrw pmpaddr15, a1 + li t0, 0x00FFFFFF + and t1, t1, t0 + slli a3, a3, 24 + j 4f +4: + or t1, t1, a3 + csrw pmpcfg3, t1 + j RET_ECALL + +////////////////////////////////////////////////// +// Set a PMP region and its attributes +// +// @a0: region number +// @a1: region base address +// @a2: region size (NAPOT/ +// NA4 only) +// @a3: region permission +// @a4: region type (NAPOT/NA4/TOR/OFF) + R/W/X +// @returns 1 if wrong region type, otherwise 0 +////////////////////////////////////////////////// +PMP_SERVICE: + li t0, OFF + beq a4, t0, RET_ECALL + li t0, TOR + beq a4, t0, SET_TOR + li t0, NA4 + beq a4, t0, SET_NA4 + li t0, NAPOT + beq a4, t0, SET_NAPOT + // region type unsupported, returns an error + li a0, 1 + j RET_ECALL + + +///////////////////////////////////////////////////// +# Entry point for user-mode system call +# Redirect to the right service +# +# a7 is the syscall number +# - 0: erase PMP registers +# - 1: setup pmp addr with 0xFFFFFFFF +# - 8: PMP_SERVICE syscall +# - 9: Interrupt setup syscall +# a0-a6 are the arguments for PMP_SERVICE syscall +///////////////////////////////////////////////////// +ECALL_USER_MODE: + # Init PMP registers + li t4, 0 + beq a7, t4, ERASE_PMP + # Setup PMPADDRs/CFGs with 0xFFFFFFFF/0x77777777 + li t4, 1 + beq a7, t4, CHECK_RW_PMP + # PMP service + li t4, 8 + beq a7, t4, PMP_SERVICE + # Interrupt service + li t4, 9 + beq a7, t4, INTP_SERVICE + j RET_ECALL + +//////////////////////////////////////////// +# Return to user-mode after ecall +//////////////////////////////////////////// +RET_ECALL: + csrr t4, mepc + add t4, t4, 4 + csrw mepc, t4 + mret + +//////////////////////////////////////////// +# Simple trap to count async interrupts +# To check we passed thru the async trap +//////////////////////////////////////////// +INTP: + add x20, x20, 1 + mret diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v index 717b5dd..89594a6 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-p-test2.v +++ b/test/priv_sec_testsuite/tests/rv32ui-p-test2.v @@ -1,85 +1,132 @@ @00010000 -6F 00 80 08 73 2F 20 34 93 0E 80 00 63 02 DF 6D -93 0E 90 00 63 02 DF 1B 93 0E B0 00 63 02 DF 1B -93 0E 20 00 63 00 DF 1B B7 0E 00 80 93 8E BE 00 -63 0A DF 6D B7 0E 00 80 93 8E 3E 00 63 04 DF 6D -B7 0E 00 80 93 8E 7E 00 63 0E DF 6B 93 0E 50 00 -63 00 DF 3F 93 0E 70 00 63 0C DF 3D 93 0E 10 00 -63 08 DF 3D 13 0F 00 00 63 04 0F 00 67 00 0F 00 -73 2F 20 34 63 54 0F 00 6F 00 40 00 93 E1 91 53 -17 1F 00 00 23 20 3F F8 93 00 00 00 13 01 00 00 -93 01 00 00 13 02 00 00 93 02 00 00 13 03 00 00 -93 03 00 00 13 04 00 00 93 04 00 00 13 05 00 00 -93 05 00 00 13 06 00 00 93 06 00 00 13 07 00 00 -93 07 00 00 13 08 00 00 93 08 00 00 13 09 00 00 -93 09 00 00 13 0A 00 00 93 0A 00 00 13 0B 00 00 -93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0D 00 00 -93 0D 00 00 13 0E 00 00 93 0E 00 00 13 0F 00 00 -93 0F 00 00 73 25 40 F1 63 10 05 00 97 02 00 00 -93 82 02 01 73 90 52 30 73 50 00 18 97 02 00 00 -93 82 02 02 73 90 52 30 B7 02 00 80 93 82 F2 FF -73 90 02 3B 93 02 F0 01 73 90 02 3A 73 50 40 30 -97 02 00 00 93 82 42 01 73 90 52 30 73 50 20 30 -73 50 30 30 93 01 00 00 97 02 00 00 93 82 C2 EA -73 90 52 30 13 05 10 00 13 15 F5 01 63 4C 05 00 -0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00 -73 00 10 00 93 02 00 00 63 8A 02 00 73 90 52 10 -B7 B2 00 00 93 82 92 10 73 90 22 30 73 50 00 30 -97 02 00 00 93 82 42 01 73 90 12 34 73 25 40 F1 -73 00 20 30 6F 00 80 55 93 8F 1F 00 73 00 10 00 -6F 00 40 53 93 8F 1F 00 73 00 10 00 73 10 00 3A -73 10 10 3A 73 10 20 3A 73 10 30 3A 73 10 00 3B -73 10 10 3B 73 10 20 3B 73 10 30 3B 73 10 40 3B -73 10 50 3B 73 10 60 3B 73 10 70 3B 73 10 80 3B -73 10 90 3B 73 10 A0 3B 73 10 B0 3B 73 10 C0 3B -73 10 D0 3B 73 10 E0 3B 73 10 F0 3B 6F 00 80 4D -B7 0E 00 00 93 8E FE FF 73 90 0E 3B 73 2F 00 3B -63 98 EE 5F 73 10 00 3B B7 0E 00 00 93 8E FE FF -73 90 1E 3B 73 2F 10 3B 63 9C EE 5D 73 10 10 3B +6F 00 40 0A 73 2F 20 34 93 0E 80 00 63 14 DF 01 +6F 20 80 53 93 0E 90 00 63 0E DF 1B 93 0E B0 00 +63 0E DF 1B 93 0E 20 00 63 0C DF 1B B7 0E 00 80 +93 8E BE 00 63 14 DF 01 6F 20 40 54 B7 0E 00 80 +93 8E 3E 00 63 14 DF 01 6F 20 40 53 B7 0E 00 80 +93 8E 7E 00 63 14 DF 01 6F 20 40 52 93 0E 50 00 +63 14 DF 01 6F 20 40 25 93 0E 70 00 63 14 DF 01 +6F 20 80 24 93 0E 10 00 63 14 DF 01 6F 20 C0 23 +13 0F 00 00 63 04 0F 00 67 00 0F 00 73 2F 20 34 +63 54 0F 00 6F 00 40 00 93 E1 91 53 17 1F 00 00 +23 22 3F F6 93 00 00 00 13 01 00 00 93 01 00 00 +13 02 00 00 93 02 00 00 13 03 00 00 93 03 00 00 +13 04 00 00 93 04 00 00 13 05 00 00 93 05 00 00 +13 06 00 00 93 06 00 00 13 07 00 00 93 07 00 00 +13 08 00 00 93 08 00 00 13 09 00 00 93 09 00 00 +13 0A 00 00 93 0A 00 00 13 0B 00 00 93 0B 00 00 +13 0C 00 00 93 0C 00 00 13 0D 00 00 93 0D 00 00 +13 0E 00 00 93 0E 00 00 13 0F 00 00 93 0F 00 00 +73 25 40 F1 63 10 05 00 97 02 00 00 93 82 02 01 +73 90 52 30 73 50 00 18 97 02 00 00 93 82 02 02 +73 90 52 30 B7 02 00 80 93 82 F2 FF 73 90 02 3B +93 02 F0 01 73 90 02 3A 73 50 40 30 97 02 00 00 +93 82 42 01 73 90 52 30 73 50 20 30 73 50 30 30 +93 01 00 00 97 02 00 00 93 82 02 E9 73 90 52 30 +13 05 10 00 13 15 F5 01 63 4C 05 00 0F 00 F0 0F +93 01 10 00 93 08 D0 05 13 05 00 00 73 00 10 00 +93 02 00 00 63 8A 02 00 73 90 52 10 B7 B2 00 00 +93 82 92 10 73 90 22 30 73 50 00 30 97 02 00 00 +93 82 42 01 73 90 12 34 73 25 40 F1 73 00 20 30 +6F 00 80 01 93 8F 1F 00 73 00 10 00 6F 20 00 39 +93 8F 1F 00 73 00 10 00 93 08 00 00 73 00 00 00 +93 08 10 00 73 00 00 00 13 05 00 00 B7 05 10 00 +13 06 00 00 93 06 F0 00 13 07 80 00 93 08 80 00 +73 00 00 00 EF 00 C0 13 B7 02 10 00 23 20 50 00 +03 23 00 00 63 90 62 16 23 AE 52 FE 03 A3 C2 FF +63 9A 62 14 B7 02 10 00 23 A0 02 00 13 00 00 00 +13 00 00 00 13 00 00 00 93 02 10 00 63 1C 54 12 +93 08 00 00 73 00 00 00 13 04 00 00 13 05 00 00 +93 05 00 00 37 06 10 00 93 06 F0 01 13 07 80 01 +93 08 80 00 73 00 00 00 EF 00 80 0D B7 02 10 00 +23 20 50 00 03 23 00 00 63 9E 62 0E 23 AE 52 FE +03 A3 C2 FF 63 98 62 0E B7 02 10 00 23 A0 02 00 +13 00 00 00 13 00 00 00 13 00 00 00 93 02 10 00 +63 1A 54 0C 93 08 00 00 73 00 00 00 13 04 00 00 +13 05 00 00 93 05 00 00 37 06 04 00 93 06 F0 01 +13 07 80 01 93 08 80 00 73 00 00 00 13 05 10 00 +B7 05 08 00 13 06 40 00 93 06 70 01 13 07 00 01 +93 08 80 00 73 00 00 00 B7 02 08 00 23 A0 52 00 +03 A3 02 00 63 90 62 08 B7 02 08 00 23 AE 02 FE +13 00 00 00 13 00 00 00 13 00 00 00 93 02 10 00 +63 12 54 06 B7 02 08 00 23 A2 02 00 13 00 00 00 +13 00 00 00 13 00 00 00 93 02 20 00 63 14 54 04 +93 08 00 00 73 00 00 00 13 04 00 00 6F 00 C0 05 +93 02 00 00 13 03 A0 00 93 03 00 00 13 0E 00 00 +B3 83 53 00 23 20 7E 00 93 83 13 00 83 23 0E 00 +93 82 12 00 13 9E 22 00 E3 94 62 FE 67 80 00 00 +63 14 30 02 0F 00 F0 0F 63 80 01 00 93 91 11 00 +93 E1 11 00 93 08 D0 05 13 85 01 00 93 8F 1F 00 +73 00 10 00 73 00 10 00 0F 00 F0 0F 93 01 10 00 +93 08 D0 05 13 05 00 00 73 00 10 00 73 00 10 00 +73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00011000 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +@00012000 +73 10 00 3A 73 10 10 3A 73 10 20 3A 73 10 30 3A +73 10 00 3B 73 10 10 3B 73 10 20 3B 73 10 30 3B +73 10 40 3B 73 10 50 3B 73 10 60 3B 73 10 70 3B +73 10 80 3B 73 10 90 3B 73 10 A0 3B 73 10 B0 3B +73 10 C0 3B 73 10 D0 3B 73 10 E0 3B 73 10 F0 3B +6F 00 C0 51 93 02 00 00 B7 0E 00 00 93 8E FE FF +73 90 0E 3B 73 2F 00 3B 63 84 EE 01 6F E0 8F B1 +73 10 00 3B B7 0E 00 00 93 8E FE FF 73 90 1E 3B +73 2F 10 3B 63 84 EE 01 6F E0 CF AF 73 10 10 3B B7 0E 00 00 93 8E FE FF 73 90 2E 3B 73 2F 20 3B -63 90 EE 5D 73 10 20 3B B7 0E 00 00 93 8E FE FF -73 90 3E 3B 73 2F 30 3B 63 94 EE 5B 73 10 30 3B -B7 0E 00 00 93 8E FE FF 73 90 4E 3B 73 2F 40 3B -63 98 EE 59 73 10 40 3B B7 0E 00 00 93 8E FE FF -73 90 5E 3B 73 2F 50 3B 63 9C EE 57 73 10 50 3B +63 84 EE 01 6F E0 0F AE 73 10 20 3B B7 0E 00 00 +93 8E FE FF 73 90 3E 3B 73 2F 30 3B 63 84 EE 01 +6F E0 4F AC 73 10 30 3B B7 0E 00 00 93 8E FE FF +73 90 4E 3B 73 2F 40 3B 63 84 EE 01 6F E0 8F AA +73 10 40 3B B7 0E 00 00 93 8E FE FF 73 90 5E 3B +73 2F 50 3B 63 84 EE 01 6F E0 CF A8 73 10 50 3B B7 0E 00 00 93 8E FE FF 73 90 6E 3B 73 2F 60 3B -63 90 EE 57 73 10 60 3B B7 0E 00 00 93 8E FE FF -73 90 7E 3B 73 2F 70 3B 63 94 EE 55 73 10 70 3B -B7 0E 00 00 93 8E FE FF 73 90 8E 3B 73 2F 80 3B -63 98 EE 53 73 10 80 3B B7 0E 00 00 93 8E FE FF -73 90 9E 3B 73 2F 90 3B 63 9C EE 51 73 10 90 3B +63 84 EE 01 6F E0 0F A7 73 10 60 3B B7 0E 00 00 +93 8E FE FF 73 90 7E 3B 73 2F 70 3B 63 84 EE 01 +6F E0 4F A5 73 10 70 3B B7 0E 00 00 93 8E FE FF +73 90 8E 3B 73 2F 80 3B 63 84 EE 01 6F E0 8F A3 +73 10 80 3B B7 0E 00 00 93 8E FE FF 73 90 9E 3B +73 2F 90 3B 63 84 EE 01 6F E0 CF A1 73 10 90 3B B7 0E 00 00 93 8E FE FF 73 90 AE 3B 73 2F A0 3B -63 90 EE 51 73 10 A0 3B B7 0E 00 00 93 8E FE FF -73 90 BE 3B 73 2F B0 3B 63 94 EE 4F 73 10 B0 3B -B7 0E 00 00 93 8E FE FF 73 90 CE 3B 73 2F C0 3B -63 98 EE 4D 73 10 C0 3B B7 0E 00 00 93 8E FE FF -73 90 DE 3B 73 2F D0 3B 63 9C EE 4B 73 10 D0 3B +63 84 EE 01 6F E0 0F A0 73 10 A0 3B B7 0E 00 00 +93 8E FE FF 73 90 BE 3B 73 2F B0 3B 63 84 EE 01 +6F E0 4F 9E 73 10 B0 3B B7 0E 00 00 93 8E FE FF +73 90 CE 3B 73 2F C0 3B 63 84 EE 01 6F E0 8F 9C +73 10 C0 3B B7 0E 00 00 93 8E FE FF 73 90 DE 3B +73 2F D0 3B 63 84 EE 01 6F E0 CF 9A 73 10 D0 3B B7 0E 00 00 93 8E FE FF 73 90 EE 3B 73 2F E0 3B -63 90 EE 4B 73 10 E0 3B B7 0E 00 00 93 8E FE FF -73 90 FE 3B 73 2F F0 3B 63 94 EE 49 73 10 F0 3B -B7 7E 77 77 93 8E 7E 77 73 90 0E 3A 73 2F 00 3A -63 98 EE 47 73 10 00 3A B7 7E 77 77 93 8E 7E 77 -73 90 1E 3A 73 2F 10 3A 63 9C EE 45 73 10 10 3A +63 84 EE 01 6F E0 0F 99 73 10 E0 3B B7 0E 00 00 +93 8E FE FF 73 90 FE 3B 73 2F F0 3B 63 84 EE 01 +6F E0 4F 97 73 10 F0 3B B7 7E 77 77 93 8E 7E 77 +73 90 0E 3A 73 2F 00 3A 63 84 EE 01 6F E0 8F 95 +73 10 00 3A B7 7E 77 77 93 8E 7E 77 73 90 1E 3A +73 2F 10 3A 63 84 EE 01 6F E0 CF 93 73 10 10 3A B7 7E 77 77 93 8E 7E 77 73 90 2E 3A 73 2F 20 3A -63 90 EE 45 73 10 20 3A B7 7E 77 77 93 8E 7E 77 -73 90 3E 3A 73 2F 30 3A 63 94 EE 43 73 10 30 3A -6F 00 40 2F 37 0F 00 00 13 0F 8F 08 F3 2E 00 30 -B3 EE EE 01 73 90 0E 30 37 1F 00 00 13 0F 0F 80 -F3 2E 40 30 B3 EE EE 01 73 90 4E 30 6F 00 80 2C -13 04 14 00 73 00 20 30 6F 00 C0 2B 13 56 16 00 -13 06 F6 FF B3 85 C5 00 93 D5 25 00 6F 00 40 00 -93 02 40 00 63 42 55 02 93 02 80 00 63 44 55 0A -93 02 C0 00 63 46 55 12 93 02 00 01 63 48 55 1A -13 05 10 00 6F 00 00 28 93 D5 25 00 73 23 00 3A -93 02 00 00 63 8E A2 00 93 02 10 00 63 82 A2 02 -93 02 20 00 63 8A A2 02 93 02 30 00 63 82 A2 04 -73 90 05 3B 93 02 00 F0 33 73 53 00 6F 00 C0 04 -73 90 15 3B B7 02 FF FF 93 82 F2 0F 33 73 53 00 -93 96 86 00 6F 00 40 03 73 90 25 3B B7 02 01 FF -93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 -73 90 35 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 -93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 03 3A -6F 00 40 1F 93 D5 25 00 73 23 10 3A 93 02 00 00 +63 84 EE 01 6F E0 0F 92 73 10 20 3A B7 7E 77 77 +93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 84 EE 01 +6F E0 4F 90 73 10 30 3A 6F 00 40 2E 37 0F 00 00 +13 0F 8F 08 F3 2E 00 30 B3 EE EE 01 73 90 0E 30 +37 1F 00 00 13 0F 0F 80 F3 2E 40 30 B3 EE EE 01 +73 90 4E 30 6F 00 80 2B 13 04 14 00 73 00 20 30 +13 06 F6 FF 13 56 36 00 93 D5 25 00 B3 E5 C5 00 +6F 00 80 00 93 D5 25 00 93 02 40 00 63 42 55 02 +93 02 80 00 63 42 55 0A 93 02 C0 00 63 42 55 12 +93 02 00 01 63 42 55 1A 13 05 10 00 6F 00 00 27 +73 23 00 3A 93 02 00 00 63 8E A2 00 93 02 10 00 +63 82 A2 02 93 02 20 00 63 8A A2 02 93 02 30 00 +63 82 A2 04 73 90 05 3B 93 02 00 F0 33 73 53 00 +6F 00 C0 04 73 90 15 3B B7 02 FF FF 93 82 F2 0F +33 73 53 00 93 96 86 00 6F 00 40 03 73 90 25 3B +B7 02 01 FF 93 82 F2 FF 33 73 53 00 93 96 06 01 +6F 00 C0 01 73 90 35 3B B7 02 00 01 93 82 F2 FF +33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 +73 10 03 3A 6F 00 80 1E 73 23 10 3A 93 02 00 00 63 8E A2 00 93 02 10 00 63 82 A2 02 93 02 20 00 63 8A A2 02 93 02 30 00 63 82 A2 04 73 90 45 3B 93 02 00 F0 33 73 53 00 6F 00 C0 04 73 90 55 3B @@ -87,57 +134,28 @@ B7 02 FF FF 93 82 F2 0F 33 73 53 00 93 96 86 00 6F 00 40 03 73 90 65 3B B7 02 01 FF 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 75 3B B7 02 00 01 93 82 F2 FF 33 73 53 00 93 96 86 01 -6F 00 40 00 33 63 D3 00 73 10 03 3A 6F 00 80 16 -93 D5 25 00 73 23 10 3A 93 02 00 00 63 8E A2 00 -93 02 10 00 63 82 A2 02 93 02 20 00 63 8A A2 02 -93 02 30 00 63 80 A2 04 73 90 85 3B 93 02 00 F0 -33 73 53 00 6F 00 80 04 73 90 95 3B B7 02 FF FF -93 82 F2 0F 33 73 53 00 93 96 86 00 6F 00 00 03 -B7 02 01 FF 93 82 F2 FF 33 73 53 00 93 96 06 01 -6F 00 C0 01 73 90 A5 3B B7 02 00 01 93 82 F2 FF -33 73 53 00 93 96 86 01 6F 00 40 00 73 90 B5 3B -33 63 D3 00 73 10 03 3A 6F 00 C0 0D 93 D5 25 00 -73 23 30 3A 93 02 00 00 63 8E A2 00 93 02 10 00 +6F 00 40 00 33 63 D3 00 73 10 13 3A 6F 00 00 16 +73 23 20 3A 93 02 00 00 63 8E A2 00 93 02 10 00 63 82 A2 02 93 02 20 00 63 8A A2 02 93 02 30 00 -63 82 A2 04 73 90 C5 3B 93 02 00 F0 33 73 53 00 -6F 00 C0 04 73 90 D5 3B B7 02 FF FF 93 82 F2 0F -33 73 53 00 93 96 86 00 6F 00 40 03 73 90 E5 3B -B7 02 01 FF 93 82 F2 FF 33 73 53 00 93 96 06 01 -6F 00 C0 01 73 90 F5 3B B7 02 00 01 93 82 F2 FF -33 73 53 00 93 96 86 01 6F 00 40 00 33 63 D3 00 -73 10 33 3A 6F 00 00 05 93 02 00 00 63 04 57 04 -93 02 80 00 E3 0E 57 D8 93 02 00 01 E3 0E 57 D6 -93 02 80 01 E3 0C 57 D6 13 05 10 00 6F 00 80 02 -93 0E 00 00 E3 8C D8 AF 93 0E 10 00 E3 82 D8 B5 -93 0E 80 00 E3 82 D8 FD 93 0E 90 00 E3 8C D8 D1 -6F 00 40 00 F3 2E 10 34 93 8E 4E 00 73 90 1E 34 -73 00 20 30 13 0A 1A 00 73 00 20 30 93 08 00 00 -73 00 00 00 93 08 10 00 73 00 00 00 13 05 00 00 -B7 05 10 00 13 06 00 00 93 06 F0 08 13 07 80 00 -93 08 80 00 73 00 00 00 EF 00 40 0B B7 02 10 00 -23 20 50 00 03 23 00 00 63 9C 62 0C 23 AE 52 FE -03 A3 C2 FF 63 96 62 0C B7 02 10 00 23 A0 02 00 -13 00 00 00 13 00 00 00 13 00 00 00 93 02 10 00 -63 18 54 0A 93 08 00 00 73 00 00 00 13 04 00 00 -13 05 00 00 93 05 00 00 37 06 10 00 93 06 F0 09 -93 06 80 01 93 08 80 00 73 00 00 00 EF 00 00 05 -B7 02 10 00 23 20 50 00 03 23 00 00 63 9A 62 06 -23 AE 52 FE 03 A3 C2 FF 63 94 62 06 B7 02 10 00 -23 A0 02 00 13 00 00 00 13 00 00 00 13 00 00 00 -93 02 10 00 63 16 54 04 13 04 00 00 93 08 00 00 -73 00 00 00 13 04 00 00 6F 00 C0 05 93 02 00 00 -13 03 A0 00 93 03 00 00 13 0E 00 00 B3 83 53 00 -23 20 7E 00 93 83 13 00 83 23 0E 00 93 82 12 00 -13 9E 22 00 E3 94 62 FE 67 80 00 00 63 14 30 02 -0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 -93 08 D0 05 13 85 01 00 93 8F 1F 00 73 00 10 00 -73 00 10 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05 -13 05 00 00 73 00 10 00 73 00 10 00 73 10 00 C0 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 -@00011000 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 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1E 34 73 00 20 30 13 0A 1A 00 +73 00 20 30 diff --git a/test/priv_sec_testsuite/tests/rv32ui-v-test2.v b/test/priv_sec_testsuite/tests/rv32ui-v-test2.v index 9916880..b994cb8 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-v-test2.v +++ b/test/priv_sec_testsuite/tests/rv32ui-v-test2.v @@ -9,8 +9,8 @@ 13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 13 0F 00 00 93 0F 00 00 97 02 00 00 93 82 02 F8 73 90 52 30 17 81 00 00 13 01 C1 ED F3 22 40 F1 -93 92 C2 00 33 01 51 00 73 10 01 34 EF 20 10 13 -17 35 00 00 13 05 05 93 6F 20 00 74 83 22 45 08 +93 92 C2 00 33 01 51 00 73 10 01 34 EF 20 50 66 +17 35 00 00 13 05 45 E6 6F 20 00 74 83 22 45 08 73 90 12 14 83 20 45 00 03 21 85 00 83 21 C5 00 03 22 05 01 83 22 45 01 03 23 85 01 83 23 C5 01 03 24 05 02 83 24 45 02 83 25 C5 02 03 26 05 03 @@ -121,11 +121,11 @@ E3 9C 07 FD 73 90 08 10 93 97 26 00 B3 06 F6 00 63 94 E5 04 93 96 26 00 B3 06 D6 00 23 A0 F6 00 73 00 05 12 83 20 C1 00 13 01 01 01 67 80 00 00 93 E7 07 04 6F F0 1F FE 97 57 00 00 23 A4 07 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73 90 BE 3B 73 2F B0 3B 63 94 EE 55 -73 10 B0 3B B7 0E 00 00 93 8E FE FF 73 90 CE 3B -73 2F C0 3B 63 98 EE 53 73 10 C0 3B B7 0E 00 00 -93 8E FE FF 73 90 DE 3B 73 2F D0 3B 63 9C EE 51 -73 10 D0 3B B7 0E 00 00 93 8E FE FF 73 90 EE 3B -73 2F E0 3B 63 90 EE 51 73 10 E0 3B B7 0E 00 00 -93 8E FE FF 73 90 FE 3B 73 2F F0 3B 63 94 EE 4F -73 10 F0 3B B7 7E 77 77 93 8E 7E 77 73 90 0E 3A -73 2F 00 3A 63 98 EE 4D 73 10 00 3A B7 7E 77 77 -93 8E 7E 77 73 90 1E 3A 73 2F 10 3A 63 9C EE 4B -73 10 10 3A B7 7E 77 77 93 8E 7E 77 73 90 2E 3A -73 2F 20 3A 63 90 EE 4B 73 10 20 3A B7 7E 77 77 -93 8E 7E 77 73 90 3E 3A 73 2F 30 3A 63 94 EE 49 -73 10 30 3A 6F 00 40 35 37 0F 00 00 13 0F 8F 08 -F3 2E 00 30 B3 EE EE 01 73 90 0E 30 37 1F 00 00 -13 0F 0F 80 F3 2E 40 30 B3 EE EE 01 73 90 4E 30 -6F 00 80 32 13 04 14 00 73 00 20 30 6F 00 C0 31 -13 56 16 00 13 06 F6 FF B3 85 C5 00 93 D5 25 00 -6F 00 40 00 93 02 40 00 63 42 55 02 93 02 80 00 -63 40 55 0C 93 02 C0 00 63 4E 55 14 93 02 00 01 -63 4C 55 1E 13 05 10 00 6F 00 00 2E 93 D5 25 00 -73 23 00 3A 93 02 00 00 63 8E A2 00 93 02 10 00 -63 86 A2 02 93 02 20 00 63 82 A2 04 93 02 30 00 -63 8E A2 04 73 90 05 3B 9B 02 10 00 93 92 02 02 -93 82 02 F0 33 73 53 00 6F 00 C0 05 73 90 15 3B -B7 02 01 00 9B 82 F2 FF 93 92 02 01 93 82 F2 0F -33 73 53 00 93 96 86 00 6F 00 C0 03 73 90 25 3B -B7 02 01 00 9B 82 12 F0 93 92 02 01 93 82 F2 FF -33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 35 3B -B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 -6F 00 40 00 33 63 D3 00 73 10 03 3A 6F 00 C0 23 -93 D5 25 00 73 23 10 3A 93 02 00 00 63 8E A2 00 +17 15 00 00 13 05 05 96 EF F0 5F 90 13 05 30 00 +EF F0 5F 94 73 10 00 3A 73 10 10 3A 73 10 20 3A +73 10 30 3A 73 10 00 3B 73 10 10 3B 73 10 20 3B +73 10 30 3B 73 10 40 3B 73 10 50 3B 73 10 60 3B +73 10 70 3B 73 10 80 3B 73 10 90 3B 73 10 A0 3B +73 10 B0 3B 73 10 C0 3B 73 10 D0 3B 73 10 E0 3B +73 10 F0 3B 6F 00 C0 52 93 02 00 00 B7 0E 00 00 +93 8E FE FF 73 90 0E 3B 73 2F 00 3B 63 92 EE 6F +73 10 00 3B B7 0E 00 00 93 8E FE FF 73 90 1E 3B +73 2F 10 3B 63 96 EE 6D 73 10 10 3B B7 0E 00 00 +93 8E FE FF 73 90 2E 3B 73 2F 20 3B 63 9A EE 6B +73 10 20 3B B7 0E 00 00 93 8E FE FF 73 90 3E 3B +73 2F 30 3B 63 9E EE 69 73 10 30 3B B7 0E 00 00 +93 8E FE FF 73 90 4E 3B 73 2F 40 3B 63 92 EE 69 +73 10 40 3B B7 0E 00 00 93 8E FE FF 73 90 5E 3B +73 2F 50 3B 63 96 EE 67 73 10 50 3B B7 0E 00 00 +93 8E FE FF 73 90 6E 3B 73 2F 60 3B 63 9A EE 65 +73 10 60 3B B7 0E 00 00 93 8E FE FF 73 90 7E 3B +73 2F 70 3B 63 9E EE 63 73 10 70 3B B7 0E 00 00 +93 8E FE FF 73 90 8E 3B 73 2F 80 3B 63 92 EE 63 +73 10 80 3B B7 0E 00 00 93 8E FE FF 73 90 9E 3B +73 2F 90 3B 63 96 EE 61 73 10 90 3B B7 0E 00 00 +93 8E FE FF 73 90 AE 3B 73 2F A0 3B 63 9A EE 5F +73 10 A0 3B B7 0E 00 00 93 8E FE FF 73 90 BE 3B +73 2F B0 3B 63 9E EE 5D 73 10 B0 3B B7 0E 00 00 +93 8E FE FF 73 90 CE 3B 73 2F C0 3B 63 92 EE 5D +73 10 C0 3B B7 0E 00 00 93 8E FE FF 73 90 DE 3B +73 2F D0 3B 63 96 EE 5B 73 10 D0 3B B7 0E 00 00 +93 8E FE FF 73 90 EE 3B 73 2F E0 3B 63 9A EE 59 +73 10 E0 3B B7 0E 00 00 93 8E FE FF 73 90 FE 3B +73 2F F0 3B 63 9E EE 57 73 10 F0 3B B7 7E 77 77 +93 8E 7E 77 73 90 0E 3A 73 2F 00 3A 63 92 EE 57 +73 10 00 3A B7 7E 77 77 93 8E 7E 77 73 90 1E 3A +73 2F 10 3A 63 96 EE 55 73 10 10 3A B7 7E 77 77 +93 8E 7E 77 73 90 2E 3A 73 2F 20 3A 63 9A EE 53 +73 10 20 3A B7 7E 77 77 93 8E 7E 77 73 90 3E 3A +73 2F 30 3A 63 9E EE 51 73 10 30 3A 6F 00 40 34 +37 0F 00 00 13 0F 8F 08 F3 2E 00 30 B3 EE EE 01 +73 90 0E 30 37 1F 00 00 13 0F 0F 80 F3 2E 40 30 +B3 EE EE 01 73 90 4E 30 6F 00 80 31 13 04 14 00 +73 00 20 30 13 06 F6 FF 13 56 36 00 93 D5 25 00 +B3 E5 C5 00 6F 00 80 00 93 D5 25 00 93 02 40 00 +63 42 55 02 93 02 80 00 63 4E 55 0A 93 02 C0 00 +63 4A 55 14 93 02 00 01 63 46 55 1E 13 05 10 00 +6F 00 00 2D 73 23 00 3A 93 02 00 00 63 8E A2 00 +93 02 10 00 63 86 A2 02 93 02 20 00 63 82 A2 04 +93 02 30 00 63 8E A2 04 73 90 05 3B 9B 02 10 00 +93 92 02 02 93 82 02 F0 33 73 53 00 6F 00 C0 05 +73 90 15 3B B7 02 01 00 9B 82 F2 FF 93 92 02 01 +93 82 F2 0F 33 73 53 00 93 96 86 00 6F 00 C0 03 +73 90 25 3B B7 02 01 00 9B 82 12 F0 93 92 02 01 +93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 +73 90 35 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 +93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 03 3A +6F 00 00 23 73 23 10 3A 93 02 00 00 63 8E A2 00 93 02 10 00 63 86 A2 02 93 02 20 00 63 82 A2 04 93 02 30 00 63 8E A2 04 73 90 45 3B 9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00 6F 00 C0 05 @@ -251,55 +249,64 @@ B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 73 90 65 3B B7 02 01 00 9B 82 12 F0 93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 75 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 -93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 03 3A -6F 00 80 19 93 D5 25 00 73 23 10 3A 93 02 00 00 -63 8E A2 00 93 02 10 00 63 86 A2 02 93 02 20 00 -63 82 A2 04 93 02 30 00 63 8C A2 04 73 90 85 3B -9B 02 10 00 93 92 02 02 93 82 02 F0 33 73 53 00 -6F 00 80 05 73 90 95 3B B7 02 01 00 9B 82 F2 FF -93 92 02 01 93 82 F2 0F 33 73 53 00 93 96 86 00 -6F 00 80 03 B7 02 01 00 9B 82 12 F0 93 92 02 01 +93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 13 3A +6F 00 00 19 73 23 20 3A 93 02 00 00 63 8E A2 00 +93 02 10 00 63 86 A2 02 93 02 20 00 63 82 A2 04 +93 02 30 00 63 8C A2 04 73 90 85 3B 9B 02 10 00 +93 92 02 02 93 82 02 F0 33 73 53 00 6F 00 80 05 +73 90 95 3B B7 02 01 00 9B 82 F2 FF 93 92 02 01 +93 82 F2 0F 33 73 53 00 93 96 86 00 6F 00 80 03 +B7 02 01 00 9B 82 12 F0 93 92 02 01 93 82 F2 FF +33 73 53 00 93 96 06 01 6F 00 C0 01 73 90 A5 3B +B7 02 00 01 9B 82 F2 FF 33 73 53 00 93 96 86 01 +6F 00 40 00 73 90 B5 3B 33 63 D3 00 73 10 23 3A +6F 00 00 0F 73 23 30 3A 93 02 00 00 63 8E A2 00 +93 02 10 00 63 86 A2 02 93 02 20 00 63 82 A2 04 +93 02 30 00 63 8E A2 04 73 90 C5 3B 9B 02 10 00 +93 92 02 02 93 82 02 F0 33 73 53 00 6F 00 C0 05 +73 90 D5 3B B7 02 01 00 9B 82 F2 FF 93 92 02 01 +93 82 F2 0F 33 73 53 00 93 96 86 00 6F 00 C0 03 +73 90 E5 3B B7 02 01 00 9B 82 12 F0 93 92 02 01 93 82 F2 FF 33 73 53 00 93 96 06 01 6F 00 C0 01 -73 90 A5 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 -93 96 86 01 6F 00 40 00 73 90 B5 3B 33 63 D3 00 -73 10 03 3A 6F 00 40 0F 93 D5 25 00 73 23 30 3A -93 02 00 00 63 8E A2 00 93 02 10 00 63 86 A2 02 -93 02 20 00 63 82 A2 04 93 02 30 00 63 8E A2 04 -73 90 C5 3B 9B 02 10 00 93 92 02 02 93 82 02 F0 -33 73 53 00 6F 00 C0 05 73 90 D5 3B B7 02 01 00 -9B 82 F2 FF 93 92 02 01 93 82 F2 0F 33 73 53 00 -93 96 86 00 6F 00 C0 03 73 90 E5 3B B7 02 01 00 -9B 82 12 F0 93 92 02 01 93 82 F2 FF 33 73 53 00 -93 96 06 01 6F 00 C0 01 73 90 F5 3B B7 02 00 01 -9B 82 F2 FF 33 73 53 00 93 96 86 01 6F 00 40 00 -33 63 D3 00 73 10 33 3A 6F 00 00 05 93 02 00 00 -63 04 57 04 93 02 80 00 E3 0E 57 D2 93 02 00 01 -E3 0E 57 D0 93 02 80 01 E3 0C 57 D0 13 05 10 00 -6F 00 80 02 93 0E 00 00 E3 8C D8 A9 93 0E 10 00 -E3 82 D8 AF 93 0E 80 00 E3 82 D8 FD 93 0E 90 00 -E3 8C D8 CB 6F 00 40 00 F3 2E 10 34 93 8E 4E 00 -73 90 1E 34 73 00 20 30 13 0A 1A 00 73 00 20 30 -93 08 00 00 73 00 00 00 93 08 10 00 73 00 00 00 -13 05 00 00 B7 05 10 00 13 06 00 00 93 06 F0 08 -13 07 80 00 93 08 80 00 73 00 00 00 EF 00 40 0B -B7 02 10 00 23 20 50 00 03 23 00 00 63 9C 62 0C -23 AE 52 FE 03 A3 C2 FF 63 96 62 0C B7 02 10 00 -23 A0 02 00 13 00 00 00 13 00 00 00 13 00 00 00 -93 02 10 00 63 18 54 0A 93 08 00 00 73 00 00 00 -13 04 00 00 13 05 00 00 93 05 00 00 37 06 10 00 -93 06 F0 09 93 06 80 01 93 08 80 00 73 00 00 00 -EF 00 00 05 B7 02 10 00 23 20 50 00 03 23 00 00 -63 9A 62 06 23 AE 52 FE 03 A3 C2 FF 63 94 62 06 +73 90 F5 3B B7 02 00 01 9B 82 F2 FF 33 73 53 00 +93 96 86 01 6F 00 40 00 33 63 D3 00 73 10 33 3A +6F 00 00 05 93 02 00 00 63 04 57 04 93 02 80 00 +E3 04 57 D4 93 02 00 01 E3 06 57 D2 93 02 80 01 +E3 02 57 D2 13 05 10 00 6F 00 80 02 93 0E 00 00 +E3 82 D8 AB 93 0E 10 00 E3 88 D8 AF 93 0E 80 00 +E3 82 D8 FD 93 0E 90 00 E3 84 D8 CD 6F 00 40 00 +F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30 +13 0A 1A 00 73 00 20 30 67 80 00 00 6F 00 80 01 +93 8F 1F 00 73 00 10 00 6F F0 9F FD 93 8F 1F 00 +73 00 10 00 93 08 00 00 73 00 00 00 93 08 10 00 +73 00 00 00 13 05 00 00 B7 05 10 00 13 06 00 00 +93 06 F0 00 13 07 80 00 93 08 80 00 73 00 00 00 +EF 00 C0 13 B7 02 10 00 23 20 50 00 03 23 00 00 +63 90 62 16 23 AE 52 FE 03 A3 C2 FF 63 9A 62 14 B7 02 10 00 23 A0 02 00 13 00 00 00 13 00 00 00 -13 00 00 00 93 02 10 00 63 16 54 04 13 04 00 00 -93 08 00 00 73 00 00 00 13 04 00 00 6F 00 80 04 -93 02 00 00 13 03 A0 00 93 03 00 00 13 0E 00 00 -B3 83 53 00 23 20 7E 00 93 83 13 00 83 23 0E 00 -93 82 12 00 13 9E 22 00 E3 94 62 FE 67 80 00 00 -63 1A 30 00 13 95 11 00 63 00 05 00 13 65 15 00 -73 00 00 00 13 05 10 00 73 00 00 00 73 00 10 00 -73 10 00 C0 -@80003058 +13 00 00 00 93 02 10 00 63 1C 54 12 93 08 00 00 +73 00 00 00 13 04 00 00 13 05 00 00 93 05 00 00 +37 06 10 00 93 06 F0 01 13 07 80 01 93 08 80 00 +73 00 00 00 EF 00 80 0D B7 02 10 00 23 20 50 00 +03 23 00 00 63 9E 62 0E 23 AE 52 FE 03 A3 C2 FF +63 98 62 0E B7 02 10 00 23 A0 02 00 13 00 00 00 +13 00 00 00 13 00 00 00 93 02 10 00 63 1A 54 0C +93 08 00 00 73 00 00 00 13 04 00 00 13 05 00 00 +93 05 00 00 37 06 04 00 93 06 F0 01 13 07 80 01 +93 08 80 00 73 00 00 00 13 05 10 00 B7 05 08 00 +13 06 40 00 93 06 70 01 13 07 00 01 93 08 80 00 +73 00 00 00 B7 02 08 00 23 A0 52 00 03 A3 02 00 +63 90 62 08 B7 02 08 00 23 AE 02 FE 13 00 00 00 +13 00 00 00 13 00 00 00 93 02 10 00 63 12 54 06 +B7 02 08 00 23 A2 02 00 13 00 00 00 13 00 00 00 +13 00 00 00 93 02 20 00 63 14 54 04 93 08 00 00 +73 00 00 00 13 04 00 00 6F 00 80 04 93 02 00 00 +13 03 A0 00 93 03 00 00 13 0E 00 00 B3 83 53 00 +23 20 7E 00 93 83 13 00 83 23 0E 00 93 82 12 00 +13 9E 22 00 E3 94 62 FE 67 80 00 00 63 1A 30 00 +13 95 11 00 63 00 05 00 13 65 15 00 73 00 00 00 +13 05 10 00 73 00 00 00 73 00 10 00 73 10 00 C0 +@800030D0 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20 diff --git a/test/priv_sec_testsuite/tests/rv64ui/test2.S b/test/priv_sec_testsuite/tests/rv64ui/test2.S index bd90040..792907e 100644 --- a/test/priv_sec_testsuite/tests/rv64ui/test2.S +++ b/test/priv_sec_testsuite/tests/rv64ui/test2.S @@ -5,6 +5,8 @@ #include "riscv_test.h" #include "test_macros.h" +#include "pmp_service.S" +#include "pmp.S" ###################################################################### # Test 2: PMP configuration and checking @@ -34,26 +36,16 @@ .equ PMPADDR, 0xFFFFFFFF .equ PMPCFG, 0x77777777 +.equ S2MB, 0x200000 .equ S1MB, 0x100000 +.equ S512K, 0x80000 +.equ S256K, 0x40000 .equ S64KB, 0x10000 .equ S16KB, 0x10000 .equ S4KB, 0x4000 .equ S1KB, 0x1000 -.equ OFF, 0 -.equ TOR_RWX, 0x8F -.equ TOR_RW, 0x8B -.equ TOR_RX, 0x8D -.equ NA4_RWX, 0x97 -.equ NA4_RW, 0x93 -.equ NA4_RX, 0x95 -.equ NAPOT_RWX, 0x9F -.equ NAPOT_RW , 0x9B -.equ NAPOT_RX , 0x9D -.equ TOR, 0x08 -.equ NA4, 0x10 -.equ NAPOT, 0x18 RVTEST_RV64U @@ -88,481 +80,6 @@ ILLEGAL_INSTRUCTION: ebreak -//////////////////////////////////////////// -// Erase all PMP configurations -//////////////////////////////////////////// -ERASE_PMP: - csrw pmpcfg0, x0 - csrw pmpcfg1, x0 - csrw pmpcfg2, x0 - csrw pmpcfg3, x0 - csrw pmpaddr0, x0 - csrw pmpaddr1, x0 - csrw pmpaddr2, x0 - csrw pmpaddr3, x0 - csrw pmpaddr4, x0 - csrw pmpaddr5, x0 - csrw pmpaddr6, x0 - csrw pmpaddr7, x0 - csrw pmpaddr8, x0 - csrw pmpaddr9, x0 - csrw pmpaddr10, x0 - csrw pmpaddr11, x0 - csrw pmpaddr12, x0 - csrw pmpaddr13, x0 - csrw pmpaddr14, x0 - csrw pmpaddr15, x0 - j RET_ECALL - -/////////////////////////////////////////////////////////////////////// -// Write all PMP registers to check it's accessible without limitations -/////////////////////////////////////////////////////////////////////// -CHECK_RW_PMP: - - // pmpaddr0 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr0, t4 - csrr t5, pmpaddr0 - bne t4, t5, fail - csrw pmpaddr0, x0 - - // pmpaddr1 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr1, t4 - csrr t5, pmpaddr1 - bne t4, t5, fail - csrw pmpaddr1, x0 - - // pmpaddr2 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr2, t4 - csrr t5, pmpaddr2 - bne t4, t5, fail - csrw pmpaddr2, x0 - - // pmpaddr3 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr3, t4 - csrr t5, pmpaddr3 - bne t4, t5, fail - csrw pmpaddr3, x0 - - // pmpaddr4 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr4, t4 - csrr t5, pmpaddr4 - bne t4, t5, fail - csrw pmpaddr4, x0 - - // pmpaddr5 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr5, t4 - csrr t5, pmpaddr5 - bne t4, t5, fail - csrw pmpaddr5, x0 - - // pmpaddr6 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr6, t4 - csrr t5, pmpaddr6 - bne t4, t5, fail - csrw pmpaddr6, x0 - - // pmpaddr7 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr7, t4 - csrr t5, pmpaddr7 - bne t4, t5, fail - csrw pmpaddr7, x0 - - // pmpaddr8 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr8, t4 - csrr t5, pmpaddr8 - bne t4, t5, fail - csrw pmpaddr8, x0 - - // pmpaddr9 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr9, t4 - csrr t5, pmpaddr9 - bne t4, t5, fail - csrw pmpaddr9, x0 - - // pmpaddr10 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr10, t4 - csrr t5, pmpaddr10 - bne t4, t5, fail - csrw pmpaddr10, x0 - - // pmpaddr1 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr11, t4 - csrr t5, pmpaddr11 - bne t4, t5, fail - csrw pmpaddr11, x0 - - // pmpaddr12 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr12, t4 - csrr t5, pmpaddr12 - bne t4, t5, fail - csrw pmpaddr12, x0 - - // pmpaddr13 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr13, t4 - csrr t5, pmpaddr13 - bne t4, t5, fail - csrw pmpaddr13, x0 - - // pmpaddr14 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr14, t4 - csrr t5, pmpaddr14 - bne t4, t5, fail - csrw pmpaddr14, x0 - - // pmpaddr15 - lui t4, %hi(PMPADDR) - addi t4, t4, %lo(PMPADDR) - csrw pmpaddr15, t4 - csrr t5, pmpaddr15 - bne t4, t5, fail - csrw pmpaddr15, x0 - - // pmpcfg0 - lui t4, %hi(PMPCFG) - addi t4, t4, %lo(PMPCFG) - csrw pmpcfg0, t4 - csrr t5, pmpcfg0 - bne t4, t5, fail - csrw pmpcfg0, x0 - - // pmpcfg1 - lui t4, %hi(PMPCFG) - addi t4, t4, %lo(PMPCFG) - csrw pmpcfg1, t4 - csrr t5, pmpcfg1 - bne t4, t5, fail - csrw pmpcfg1, x0 - - // pmpcfg2 - lui t4, %hi(PMPCFG) - addi t4, t4, %lo(PMPCFG) - csrw pmpcfg2, t4 - csrr t5, pmpcfg2 - bne t4, t5, fail - csrw pmpcfg2, x0 - - // pmpaddr3 - lui t4, %hi(PMPCFG) - addi t4, t4, %lo(PMPCFG) - csrw pmpcfg3, t4 - csrr t5, pmpcfg3 - bne t4, t5, fail - csrw pmpcfg3, x0 - j RET_ECALL - -//////////////////////////////////////////// -# Enable asynchronous traps -//////////////////////////////////////////// -INTP_SERVICE: - # Enable IRQ - lui t5, %hi(MIE_ON) - addi t5, t5, %lo(MIE_ON) - csrr t4, mstatus - or t4, t4, t5 - csrw mstatus, t4 - # Enable EIRQ - lui t5, %hi(MEIE_ON) - addi t5, t5, %lo(MEIE_ON) - csrr t4, mie - or t4, t4, t5 - csrw mie, t4 - j RET_ECALL - -EXP_SERVICE: - addi s0, s0, 1 - # j RET_ECALL - mret - -//////////////////////////////////////////// -# Configure a NAPOT / NA4 region -//////////////////////////////////////////// -SET_NA4: - j RET_ECALL -SET_NAPOT: - # napot_size = ((size/2)-1) - srli a2, a2, 1 - addi a2, a2, -1 - # pmp_addr = (base + napot_size)>>2 - add a1, a1, a2 - srli a1, a1, 2 - j SET_PMP - - -//////////////////////////////////////////// -# Configure a TOR region -//////////////////////////////////////////// -SET_PMP: -SET_TOR: - li t0, 4 - blt a0, t0, CFGREG0 - li t0, 8 - blt a0, t0, CFGREG1 - li t0, 12 - blt a0, t0, CFGREG2 - li t0, 16 - blt a0, t0, CFGREG3 - // region number not supported (>16) - li a0, 1 - j RET_ECALL - -CFGREG0: - // prepare address, must be store by removing 2 LSBs - srli a1, a1, 2 - // load configuration to update - csrr t1, pmpcfg0 - // check pmp region to configure - li t0, 0 - beq t0, a0, 0f - li t0, 1 - beq t0, a0, 1f - li t0, 2 - beq t0, a0, 2f - li t0, 3 - beq t0, a0, 3f -0: - csrw pmpaddr0, a1 - li t0, 0xFFFFFF00 - and t1, t1, t0 - j 4f -1: - csrw pmpaddr1, a1 - li t0, 0xFFFF00FF - and t1, t1, t0 - slli a3, a3, 8 - j 4f -2: - csrw pmpaddr2, a1 - li t0, 0xFF00FFFF - and t1, t1, t0 - slli a3, a3, 16 - j 4f -3: - csrw pmpaddr3, a1 - li t0, 0x00FFFFFF - and t1, t1, t0 - slli a3, a3, 24 - j 4f -4: - // Store config and start MPU - or t1, t1, a3 - csrw pmpcfg0, t1 - j RET_ECALL - -CFGREG1: - srli a1, a1, 2 - csrr t1, pmpcfg1 - li t0, 0 - beq t0, a0, 0f - li t0, 1 - beq t0, a0, 1f - li t0, 2 - beq t0, a0, 2f - li t0, 3 - beq t0, a0, 3f -0: - csrw pmpaddr4, a1 - li t0, 0xFFFFFF00 - and t1, t1, t0 - j 4f -1: - csrw pmpaddr5, a1 - li t0, 0xFFFF00FF - and t1, t1, t0 - slli a3, a3, 8 - j 4f -2: - csrw pmpaddr6, a1 - li t0, 0xFF00FFFF - and t1, t1, t0 - slli a3, a3, 16 - j 4f -3: - csrw pmpaddr7, a1 - li t0, 0x00FFFFFF - and t1, t1, t0 - slli a3, a3, 24 - j 4f -4: - or t1, t1, a3 - csrw pmpcfg0, t1 - j RET_ECALL - -CFGREG2: - srli a1, a1, 2 - csrr t1, pmpcfg1 - li t0, 0 - beq t0, a0, 0f - li t0, 1 - beq t0, a0, 1f - li t0, 2 - beq t0, a0, 2f - li t0, 3 - beq t0, a0, 3f -0: - csrw pmpaddr8, a1 - li t0, 0xFFFFFF00 - and t1, t1, t0 - j 4f -1: - csrw pmpaddr9, a1 - li t0, 0xFFFF00FF - and t1, t1, t0 - slli a3, a3, 8 - j 4f -2: - li t0, 0xFF00FFFF - and t1, t1, t0 - slli a3, a3, 16 - j 4f -3: - csrw pmpaddr10, a1 - li t0, 0x00FFFFFF - and t1, t1, t0 - slli a3, a3, 24 - j 4f -4: - csrw pmpaddr11, a1 - or t1, t1, a3 - csrw pmpcfg0, t1 - j RET_ECALL - - -CFGREG3: - srli a1, a1, 2 - csrr t1, pmpcfg3 - li t0, 0 - beq t0, a0, 0f - li t0, 1 - beq t0, a0, 1f - li t0, 2 - beq t0, a0, 2f - li t0, 3 - beq t0, a0, 3f -0: - csrw pmpaddr12, a1 - li t0, 0xFFFFFF00 - and t1, t1, t0 - j 4f -1: - csrw pmpaddr13, a1 - li t0, 0xFFFF00FF - and t1, t1, t0 - slli a3, a3, 8 - j 4f -2: - csrw pmpaddr14, a1 - li t0, 0xFF00FFFF - and t1, t1, t0 - slli a3, a3, 16 - j 4f -3: - csrw pmpaddr15, a1 - li t0, 0x00FFFFFF - and t1, t1, t0 - slli a3, a3, 24 - j 4f -4: - or t1, t1, a3 - csrw pmpcfg3, t1 - j RET_ECALL - -////////////////////////////////////////////////// -// Set a PMP region and its attributes -// -// @a0: the region number -// @a1: the region base address -// @a2: the region size (NAPOT) only -// @a3: the region type (NAPOT/NA4/TOR/OFF) + R/W/X -// @returns 1 if wrong region type, otherwise 0 -////////////////////////////////////////////////// -PMP_SERVICE: - li t0, OFF - beq a4, t0, RET_ECALL - li t0, TOR - beq a4, t0, SET_TOR - li t0, NA4 - beq a4, t0, SET_NA4 - li t0, NAPOT - beq a4, t0, SET_NAPOT - // region type unsupported, returns an error - li a0, 1 - j RET_ECALL - - -///////////////////////////////////////////////////// -# Entry point for user-mode system call -# Redirect to the right service -# -# a7 is the syscall number -# - 0: erase PMP registers -# - 1: setup pmp addr with 0xFFFFFFFF -# - 8: PMP_SERVICE syscall -# - 9: Interrupt setup syscall -# a0-a6 are the arguments for PMP_SERVICE syscall -///////////////////////////////////////////////////// -ECALL_USER_MODE: - # Init PMP registers - li t4, 0 - beq a7, t4, ERASE_PMP - # Setup PMPADDRs/CFGs with 0xFFFFFFFF/0x77777777 - li t4, 1 - beq a7, t4, CHECK_RW_PMP - # PMP service - li t4, 8 - beq a7, t4, PMP_SERVICE - # Interrupt service - li t4, 9 - beq a7, t4, INTP_SERVICE - j RET_ECALL - -//////////////////////////////////////////// -# Return to user-mode after ecall -//////////////////////////////////////////// -RET_ECALL: - csrr t4, mepc - add t4, t4, 4 - csrw mepc, t4 - mret - -//////////////////////////////////////////// -# Simple trap to count async interrupts -# To check we passed thru the async trap -//////////////////////////////////////////// -INTP: - add x20, x20, 1 - mret - - ################################################## # # Testcases @@ -619,8 +136,10 @@ TEST3_OUT_OF_BOUND: bne s0, t0, fail TEST3_TEARDOWN: + # Erase PMP configuration li a7, 0 ecall + # Reset error count li s0, 0 // NAPOT region - 1MB RWX @@ -630,7 +149,7 @@ TEST4_1NAPOT: li a1, 0 // base address li a2, S1MB // size li a3, NAPOT_RWX // permissions - li a3, NAPOT // type + li a4, NAPOT // type li a7, 8 ecall // Run some duties into the region @@ -650,8 +169,6 @@ TEST4_BOUNDS: // Try to access outside the memory region TEST4_OUT_OF_BOUND: li t0, S1MB - # lui t0, %hi(S1MB) - # addi t0, t0, %lo(S1MB) sw x0, 0(t0) // raise an exception, which will increment s0 # bunch of nop to wait for exception handling nop @@ -660,14 +177,66 @@ TEST4_OUT_OF_BOUND: // Check the exception has been handled correctly li t0, 1 bne s0, t0, fail - li s0, 0 TEST4_TEARDOWN: + # Erase PMP configuration li a7, 0 ecall + # Reset error count li s0, 0 - j pass +// NA4 region - 2MB RWX +TEST5_NA4: + // Configure a NAPOT 512 KB for code + li a0, 0 // pmp number + li a1, 0 // base address + li a2, S256K // size + li a3, NAPOT_RWX // permissions + li a4, NAPOT // type + li a7, 8 + ecall + // Configure a NA4 + li a0, 1 // pmp number + li a1, S512K // base address + li a2, 4 // size + li a3, NA4_RWX // permissions + li a4, NA4 // type + li a7, 8 + ecall +// Try to access the extreme boundaries of the memory region +TEST5_REGION: + li t0, S512K + sw t0, 0(t0) + lw t1, 0(t0) + bne t0, t1, fail +// Try to access outside the memory region +TEST5_OUT_OF_BOUND: + li t0, S512K + sw x0, -4(t0) // raise an exception, which will increment s0 + # bunch of nop to wait for exception handling + nop + nop + nop + // Check the exception has been handled correctly + li t0, 1 + bne s0, t0, fail + li t0, S512K + sw x0, 4(t0) // raise an exception, which will increment s0 + # bunch of nop to wait for exception handling + nop + nop + nop + // Check the exception has been handled correctly + li t0, 2 + bne s0, t0, fail + +TEST5_TEARDOWN: + # Erase PMP configuration + li a7, 0 + ecall + # Reset error count + li s0, 0 + j pass ////////////////////////////////////////////////////// // Stupid loop to access the memory over a small range