diff --git a/doc/privilege.md b/doc/privilege.md index a3078f8..7060128 100644 --- a/doc/privilege.md +++ b/doc/privilege.md @@ -72,6 +72,7 @@ The privilege modes support have been designed based on RISC-V ISA specification - Study PMA (Physical Memory Attribute) (section 3.6) - Replace existing IO_MAP by PMP & PMA - Support cycle registers per mode +- Pass compliance with U-mode ## Supervisor diff --git a/rtl/friscv_control.sv b/rtl/friscv_control.sv index df8f3a3..e6facc0 100644 --- a/rtl/friscv_control.sv +++ b/rtl/friscv_control.sv @@ -666,6 +666,7 @@ module friscv_control `endif status[3] <= 1'b1; flush_pipe <= 1'b1; + if (USER_MODE) priv_mode <= `MMODE; pc_reg <= mtvec; // Needs to jump or branch thus stop the pipeline @@ -1090,21 +1091,21 @@ module friscv_control assign inst_dec_error = dec_error & (cfsm==FETCH) & inst_ready; - generate + generate if (USER_MODE) begin: UMODE_EXPEC assign illegal_instruction = (priv_mode==`MMODE) ? '0 : - (sys[`IS_MRET]) ? inst_ready : - (sys[`IS_CSR] && csr[9:8] != 2'b00) ? inst_ready : + (sys[`IS_MRET]) ? inst_ready : + (sys[`IS_CSR] && csr[9:8] != 2'b00) ? inst_ready : // Check if WFI must be trapped or not - // (sys[`IS_WFI] ) ? inst_ready : + // (sys[`IS_WFI] ) ? inst_ready : '0; end else begin : NO_UMODE assign illegal_instruction = '0; end endgenerate - assign ecall_umode = (sys[`ECALL] && priv_mode==`UMODE); - assign ecall_mmode = (sys[`ECALL] && priv_mode==`MMODE); + assign ecall_umode = (sys[`IS_ECALL] && priv_mode==`UMODE); + assign ecall_mmode = (sys[`IS_ECALL] && priv_mode==`MMODE); /////////////////////////////////////////////////////////////////////////// // diff --git a/test/common/debug_core_verilator.gtkw b/test/common/debug_core_verilator.gtkw index 2f03f52..1b0a8aa 100644 --- a/test/common/debug_core_verilator.gtkw +++ b/test/common/debug_core_verilator.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI -[*] Thu Apr 20 18:56:23 2023 +[*] Sat Sep 16 11:53:18 2023 [*] [dumpfile] "/Users/damien/workspace/hdl/friscv/test/riscv-tests/friscv_testbench.vcd" -[dumpfile_mtime] "Mon Apr 17 18:46:54 2023" -[dumpfile_size] 6519480 +[dumpfile_mtime] "Wed Sep 13 18:20:19 2023" +[dumpfile_size] 1779051 [savefile] "/Users/damien/workspace/hdl/friscv/test/common/debug_core_verilator.gtkw" -[timestart] 5908 -[size] 2560 1440 +[timestart] 1 +[size] 1440 900 [pos] -1 -1 -*-4.164201 5944 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-9.303937 1589 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] friscv_testbench. [treeopen] friscv_testbench.friscv_testbench. [treeopen] friscv_testbench.friscv_testbench.genblk2. @@ -17,15 +17,14 @@ [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.control. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.csrs. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.processing. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache. [sst_width] 335 [signals_width] 526 [sst_expanded] 1 -[sst_vpaned_height] 460 -@c00201 +[sst_vpaned_height] 642 +@c00200 -Testbench -@25 +@24 friscv_testbench.friscv_testbench.AXI_ADDR_W[31:0] friscv_testbench.friscv_testbench.AXI_DATA_W[31:0] friscv_testbench.friscv_testbench.AXI_DMEM_MASK[31:0] @@ -47,78 +46,81 @@ friscv_testbench.friscv_testbench.INST_OSTDREQ_NUM[31:0] friscv_testbench.friscv_testbench.MIN_PC[31:0] friscv_testbench.friscv_testbench.M_EXTENSION[31:0] friscv_testbench.friscv_testbench.PROCESSING_BUS_PIPELINE[31:0] -friscv_testbench.friscv_testbench.PROCESSING_QUEUE_DEPTH[31:0] friscv_testbench.friscv_testbench.RV32E[31:0] friscv_testbench.friscv_testbench.TB_CHOICE[63:0] friscv_testbench.friscv_testbench.TIMEOUT[31:0] friscv_testbench.friscv_testbench.XLEN[31:0] -@23 +@22 friscv_testbench.friscv_testbench.TIMEOUT[31:0] friscv_testbench.friscv_testbench.timer[31:0] -@1401201 +@1401200 -Testbench -@800201 +@800200 -Control -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.aclk -@201 +@200 - -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.control.araddr[31:0] [color] 3 friscv_testbench.friscv_testbench.genblk2.dut.control.arid[7:0] -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.control.arvalid friscv_testbench.friscv_testbench.genblk2.dut.control.arready [color] 2 friscv_testbench.friscv_testbench.genblk2.dut.control.fifo_empty -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.control.instruction[31:0] -@201 +@200 - -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.control.cfsm[3:0] -@201 +@28 +friscv_testbench.friscv_testbench.genblk2.dut.control.priv_mode[1:0] +@23 +friscv_testbench.friscv_testbench.genblk2.dut.csrs.mstatus[31:0] +@200 - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.control.proc_valid friscv_testbench.friscv_testbench.genblk2.dut.control.proc_ready -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.control.proc_instbus[85:0] -@201 +@200 - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.control.ctrl_rd_wr -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.control.ctrl_rd_addr[4:0] friscv_testbench.friscv_testbench.genblk2.dut.control.ctrl_rd_val[31:0] -@201 +@200 - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.processing.memfy.memfy_rd_wr -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.processing.memfy.memfy_rd_addr[4:0] friscv_testbench.friscv_testbench.genblk2.dut.processing.memfy.memfy_rd_val[31:0] -@201 +@200 - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.processing.alu.alu_rd_wr -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.processing.alu.alu_rd_addr[4:0] friscv_testbench.friscv_testbench.genblk2.dut.processing.alu.alu_rd_val[31:0] -@201 +@200 - -@800029 +@800028 friscv_testbench.friscv_testbench.genblk2.dut.processing.proc_rd_wr[2:0] -@29 +@28 (0)friscv_testbench.friscv_testbench.genblk2.dut.processing.proc_rd_wr[2:0] (1)friscv_testbench.friscv_testbench.genblk2.dut.processing.proc_rd_wr[2:0] (2)friscv_testbench.friscv_testbench.genblk2.dut.processing.proc_rd_wr[2:0] -@1001201 +@1001200 -group_end -@201 +@200 - -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.x1_ra[31:0] friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.x2_sp[31:0] friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.x3_gp[31:0] @@ -150,92 +152,91 @@ friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.x28_t3[31:0] friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.x29_t4[31:0] friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.x30_t5[31:0] friscv_testbench.friscv_testbench.genblk2.dut.isa_registers.x31_t6[31:0] -@201 +@200 - - - - - - -@1000201 +@1000200 -Control -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.ctrl_araddr[31:0] friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.ctrl_arid[7:0] -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.ctrl_arready friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.ctrl_arvalid -@201 +@200 - -@29 -friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.fetcher.fifo_empty_if +@28 friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.fetcher.cache_ren -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.fetcher.cache_raddr[31:0] -@201 +@200 - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.fetcher.cache_hit friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.fetcher.cache_miss -@201 +@200 - -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.ctrl_rid[7:0] -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.ctrl_rready friscv_testbench.friscv_testbench.genblk2.dut.USE_ICACHE.icache.ctrl_rvalid -@201 +@200 - -@c00201 +@c00200 -Bus Perf -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.NB_BUS[31:0] friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.REG_W[31:0] -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.aclk friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.aresetn friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.srst -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.perfs[287:0] -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.valid[2:0] friscv_testbench.friscv_testbench.genblk2.dut.bus_perf.ready[2:0] -@201 +@200 - - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.inst_arvalid_s friscv_testbench.friscv_testbench.genblk2.dut.inst_arready_s -@201 +@200 - -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.csrs.instreq_perf_active[31:0] friscv_testbench.friscv_testbench.genblk2.dut.csrs.instreq_perf_sleep[31:0] friscv_testbench.friscv_testbench.genblk2.dut.csrs.instreq_perf_stall[31:0] -@201 +@200 - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.inst_rvalid_s friscv_testbench.friscv_testbench.genblk2.dut.inst_rready_s -@201 +@200 - -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.csrs.instcpl_perf_active[31:0] friscv_testbench.friscv_testbench.genblk2.dut.csrs.instcpl_perf_sleep[31:0] friscv_testbench.friscv_testbench.genblk2.dut.csrs.instcpl_perf_stall[31:0] -@201 +@200 - -@29 +@28 friscv_testbench.friscv_testbench.genblk2.dut.proc_valid friscv_testbench.friscv_testbench.genblk2.dut.proc_ready friscv_testbench.friscv_testbench.genblk2.dut.proc_busy -@201 +@200 - -@23 +@22 friscv_testbench.friscv_testbench.genblk2.dut.csrs.proc_perf_active[31:0] friscv_testbench.friscv_testbench.genblk2.dut.csrs.proc_perf_sleep[31:0] friscv_testbench.friscv_testbench.genblk2.dut.csrs.proc_perf_stall[31:0] -@1401201 +@1401200 -Bus Perf [pattern_trace] 1 [pattern_trace] 0 diff --git a/test/common/debug_platform_verilator.gtkw b/test/common/debug_platform_verilator.gtkw index c396cfe..70babc9 100644 --- a/test/common/debug_platform_verilator.gtkw +++ b/test/common/debug_platform_verilator.gtkw @@ -1,39 +1,24 @@ [*] [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI -[*] Fri Sep 8 12:02:24 2023 +[*] Sun Sep 17 13:56:01 2023 [*] -[dumpfile] "/Users/damien/workspace/hdl/friscv/test/wba_testsuite/friscv_testbench.vcd" -[dumpfile_mtime] "Fri Sep 8 12:00:46 2023" -[dumpfile_size] 1855324 +[dumpfile] "/Users/damien/workspace/hdl/friscv/test/priv_sec_testsuite/friscv_testbench.vcd" +[dumpfile_mtime] "Sun Sep 17 13:55:53 2023" +[dumpfile_size] 1896801 [savefile] "/Users/damien/workspace/hdl/friscv/test/common/debug_platform_verilator.gtkw" -[timestart] 1741 +[timestart] 1853 [size] 1440 900 [pos] -1 -1 -*-4.607932 1809 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-2.607932 1861 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] friscv_testbench. [treeopen] friscv_testbench.friscv_testbench. [treeopen] friscv_testbench.friscv_testbench.genblk2. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.axi4lite_crossbar_inst.switchs. [treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.IO_FECTHER_INSTANCE. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.genblk1. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.GEN_WSTRB. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.IN_ORDER_CPL. -[treeopen] friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem. [sst_width] 287 [signals_width] 300 [sst_expanded] 1 -[sst_vpaned_height] 332 +[sst_vpaned_height] 357 @c00200 -AXI4-lite RAM @22 @@ -96,277 +81,17 @@ friscv_testbench.friscv_testbench.genblk2.axi4l_ram.p1_bvalid -AXI4-lite RAM @c00200 -Interconnect -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.AXI_ADDR_W[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.AXI_AUSER_W[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.AXI_BUSER_W[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.AXI_DATA_W[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.AXI_ID_W[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.AXI_RUSER_W[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.AXI_WUSER_W[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST0_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST0_ID_MASK[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST0_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST0_PRIORITY[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST0_ROUTES[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST0_RW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST1_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST1_ID_MASK[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST1_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST1_PRIORITY[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST1_ROUTES[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST1_RW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST2_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST2_ID_MASK[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST2_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST2_PRIORITY[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST2_ROUTES[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST2_RW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST3_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST3_ID_MASK[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST3_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST3_PRIORITY[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST3_ROUTES[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST3_RW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST_NB[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.MST_PIPELINE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV0_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV0_START_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV0_END_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV0_KEEP_BASE_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV0_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV1_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV1_START_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV1_END_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV1_KEEP_BASE_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV1_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV2_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV2_END_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV2_KEEP_BASE_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV2_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV2_START_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV3_CDC[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV3_END_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV3_KEEP_BASE_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV3_OSTDREQ_NUM[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV3_START_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV_NB[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.SLV_PIPELINE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.STRB_MODE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.TIMEOUT_ENABLE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.TIMEOUT_VALUE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.USER_SUPPORT[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.aclk -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.aresetn @200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_aclk -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_aresetn -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_arready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_aruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_arvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_awprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_awready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_awuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_awvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_bready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_bresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_buser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_bvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_rdata[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_rready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_ruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_rvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_wdata[127:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_wready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_wstrb[15:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_wuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv0_wvalid -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_aclk -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_aresetn -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_arready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_aruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_arvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_awprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_awready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_awuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_awvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_bready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_bresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_buser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_bvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_rdata[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_rready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_ruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_rvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_wdata[127:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_wready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_wstrb[15:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_wuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.slv1_wvalid -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_aclk -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_aresetn -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_arready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_aruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_arvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_awprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_awready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_awuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_awvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_bready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_bresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_buser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_bvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_rdata[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_rready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_ruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_rvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_wdata[127:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_wready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_wstrb[15:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_wuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst0_wvalid -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_aclk -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_aresetn -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_arready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_aruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_arvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_awprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_awready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_awuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_awvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_bready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_bresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_buser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_bvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_rdata[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_rready -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_ruser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_rvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_wdata[127:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_wready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_wstrb[15:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_wuser[0] -friscv_testbench.friscv_testbench.genblk2.dut.axi4lite_crossbar.mst1_wvalid @1401200 -Interconnect @c00200 -CSRs -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mcause[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mcounteren[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.medeleg[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mhartid[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mideleg[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mie[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mip[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.misa[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mscratch[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtval[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtvec[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.rdcycle[63:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.rdinstret[63:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.rdtime[63:0] @200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ext_irq -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.sw_irq -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.timer_irq -@200 - @1401200 -CSRs @@ -374,1399 +99,120 @@ friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.timer_irq -ISA Regsiters @200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rd_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rd_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rd_val[31:0] -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_strb[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_val[31:0] -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_strb[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_val[31:0] -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.proc_rd_wr[2:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.proc_rd_addr[14:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.proc_rd_strb[11:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.proc_rd_val[95:0] -@200 - -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x1_ra[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x2_sp[31:0] -@24 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x3_gp[31:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x4_tp[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x5_t0[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x6_t1[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x7_t2[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x8_s0_fp[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x9_s1[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x10_a0[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x11_a1[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x12_a2[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x13_a3[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x14_a4[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x15_a5[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x16_a6[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x17_a7[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x18_s2[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x19_s3[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x20_s4[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x21_s5[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x22_s6[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x23_s7[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x24_s8[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x25_s9[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x26_s10[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x27_s11[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x28_t3[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x29_t4[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x30_t5[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x31_t6[31:0] @1401200 -ISA Regsiters @c00200 -iCache -top -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_arready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_arvalid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_rvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_rready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.ctrl_rresp[1:0] @200 - -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_arcache[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_arready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_arvalid -@200 - -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_raddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_rcache -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_rdata_blk[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_rready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mst_rvalid -@200 - -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_araddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arburst[1:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arcache[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arid[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arlen[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arlock[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arprot[2:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arqos[3:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arregion[3:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arsize[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_arvalid -@200 - -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_rdata[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_rlast -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_rready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.mem_ctrl.mem_rvalid @1401200 -top @c00200 -iCache Fetcher -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.aresetn @200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.flush_blocks -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.flush_reqs -@200 - -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_arprot[2:0] -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_arvalid -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_arready -@200 - -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_rid[7:0] -@28 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_rvalid -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.mst_rready -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.arvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.arready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.araddr_ffd[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.fetching -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.loader[1:0] -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.pull_rac -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.push_rac -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.rac_empty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.rdc_afull -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.rac_full -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.push_rdc -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.pull_rdc -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.rdc_empty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.rdc_full -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.cache_ren -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.cache_raddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.cache_hit -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.cache_miss -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.block_fill -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.cache_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.fetcher.cache_rid[7:0] -@200 - @1401200 -iCache Fetcher @c00200 -iCache Prefetch -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.aresetn -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.araddr_ffd[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.addr_to_fetch[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.arid_ffd[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.arprot_ffd[2:0] @200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.loader[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.fetch_next -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.next_addr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.block_fill -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.cache_ren -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.cache_raddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.cache_rprot[2:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.cache_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.cache_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.cache_hit -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.cache_miss -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.mem_cpl_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.mem_cpl_wr -@200 - -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.memctrl_arvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.memctrl_arready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.memctrl_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.memctrl_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.prefetcher.memctrl_arprot[2:0] @1401200 -iCache Prefetch @c00200 -iCache Blocks -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.p1_ren -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.p1_raddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.p1_hit -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.p1_miss -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.p1_wen -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.p1_waddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_ICACHE.icache.cache_blocks.p1_wdata[127:0] @1401200 -iCache Blocks -iCache -@800200 --dCache -@c00200 --dCache Fetcher -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.aclk -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arvalid -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rvalid -@200 -- -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_arvalid -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.block_fetcher.mst_rvalid -@1401200 --dCache Fetcher -@c00200 --dCache Prefetch -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.aresetn -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.araddr_ffd[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.arid_ffd[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.arprot_ffd[2:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.loader[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.block_fill -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.fetch_next -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.next_addr[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.cache_ren -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.cache_raddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.cache_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.cache_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.cache_rprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.cache_miss -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.cache_hit -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.mem_cpl_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.mem_cpl_wr @200 - @28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.memctrl_arvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.memctrl_arready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.memctrl_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.memctrl_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.prefetcher.memctrl_arprot[2:0] -@1401200 --dCache Prefetch -@c00200 --dCache Rd OoO -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arcache[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arid[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arid_next[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arid_w[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arready_blk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arready_io -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arvalid_blk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.memfy_arvalid_io +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk @200 - @28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.RD_OOO_INSTANCE.rd_ooo_mgt.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.RD_OOO_INSTANCE.rd_ooo_mgt.aresetn -@200 -- +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.priv_mode[1:0] @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.RD_OOO_INSTANCE.rd_ooo_mgt.next_tag[7:0] -@1401200 --dCache Rd OoO -@c00200 --Pusher -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.aresetn +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] @200 - @28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_ren +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.flush_pipe +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.pull_inst +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_ready @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_raddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_hit -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_miss +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.pc_reg[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.instruction[31:0] @200 - -- +@29 +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring @28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_wen +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.illegal_instruction +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ecall_mmode +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ecall_umode @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_waddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_wdata[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cache_wstrb[15:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sys[5:0] @200 - @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_awprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_awvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_awready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_wdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_wstrb[3:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_wvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_wready +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mcause[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mepc[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mie[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mip[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mstatus[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtval[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.mtvec[31:0] @200 - @22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_bresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_bvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.mst_bready -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.addr_fifo_empty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.addr_fifo_full -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.data_fifo_empty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.data_fifo_full -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.resp_fifo_empty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.resp_fifo_full -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.id_ram[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.push_resp -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.cpl_id_m[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.to_cpl -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.pull_resp -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.req_id_m[7:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_awprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_awvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_awready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_wdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_wstrb[3:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_wvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_wready -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_bresp[1:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_bvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.pusher.memctrl_bready -@1401200 --Pusher -@c00200 --Wr OoO Mgt -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.aresetn -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl1_data[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl1_id[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl1_id_m[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl1_resp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl1_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl1_ready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl2_data[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl2_id[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl2_id_m[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl2_resp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl2_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.cpl2_ready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.next_tag[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.req_tag_pt[4:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.tag_avlb -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.tags[63:0] -@200 -- -@c00022 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_acache[3:0] -@28 -(0)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_acache[3:0] -(1)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_acache[3:0] -(2)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_acache[3:0] -(3)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_acache[3:0] -@1401200 --group_end -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_addr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_aid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_avalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_aready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_data[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_id[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_resp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.wr_ooo_mgt.slv_ready -@200 -- -@1401200 --Wr OoO Mgt -@c00200 --MemCtrl -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_araddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_arready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_arvalid -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_awprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_awready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_awvalid -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_wdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_wstrb[3:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_wvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_wready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_bready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_bresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mst_bvalid -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_awaddr[31:0] -@28 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_awvalid -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_awready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.woffset[1:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_wdata[127:0] -@28 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_wvalid -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_wready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.mem_wstrb[15:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.wr_strb_pos[1:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.push_woffset -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.push_woffset_r -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.wch_full -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.wch_empty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.wch_aempty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.pull_woffset -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.woffset_r[1:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.ADDR_WIDTH[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.DATA_WIDTH[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.PASS_THRU[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.aempty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.afull -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.aresetn -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.data_fifo[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.data_in[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.data_out[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.empty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.empty_flag -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.flush -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.full -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.pass_thru -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.aempty -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.afull -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.push -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.pull -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.USE_DCACHE.dcache.mem_ctrl.WRITE_CHANNELS.wroffset_fifo.wr_en -@1401200 --MemCtrl -@1000200 --dCache -@800200 --Control -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aresetn -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.async_trap_occuring -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sync_trap_occuring -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.mcause[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring -@c00022 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] -@28 -(0)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] -(1)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] -(2)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] -(3)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] -@1401200 --group_end -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.flush_pipe -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.flush_reqs -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.flush_blocks -@200 -- -@c00200 --flushs -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.flush_ack -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.flush_blocks -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.flush_reqs -@1401200 --flushs -@800200 --axi4-lite -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.araddr[31:0] -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.arprot[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.arvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.arready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rid[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rdata[31:0] -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rvalid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.rready -@1000200 --axi4-lite -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.aclk -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cfsm[3:0] -@28 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.pull_inst -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_ready -@22 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.pc_reg[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.instruction[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.jal -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.jalr -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.branching -@200 -- -@29 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_busy -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_ready -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cant_jump -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cant_lui_auipc -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cant_process -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.cant_sys -@200 -- -@c00200 --CSR IFs -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rd_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rd_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rd_val[31:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rs1_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rs1_val[31:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rs2_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.ctrl_rs2_val[31:0] -@1401200 --CSR IFs -@200 -- -@800200 --Processing -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_valid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_instbus[85:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_busy -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.proc_ready -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_en -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ready -@1000200 --Processing -@200 -- -@c00200 --Traps -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.sync_trap_occuring -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.async_trap_occuring -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.trap_occuring -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.store_misaligned -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.load_misaligned -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.dec_error -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.csr_ro_wr -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_addr_misaligned -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.inst_dec_error -@1401200 --Traps -@1000200 --Control -@c00200 --processing -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.aclk -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_instbus[85:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_ready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_busy -@22 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.pc_reg[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.control.instruction[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_valid_p -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_ready_p -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.i_inst -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.ls_inst -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.m_inst -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu_ready -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.m_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.m_ready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.m_regs_sts[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_ready -@c00022 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -@28 -(0)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(1)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(2)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(3)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(4)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(5)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(6)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(7)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(8)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(9)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(10)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(11)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(12)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(13)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(14)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(15)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(16)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(17)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(18)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(19)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(20)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(21)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(22)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(23)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(24)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(25)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(26)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(27)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(28)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(29)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(30)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -(31)friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy_regs_sts[31:0] -@1401200 --group_end -@200 -- -@c00200 --pipe -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_instbus_p[85:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_valid_p -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.proc_ready_p -@1401200 --pipe -@c00200 --ALU -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.aresetn -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_instbus[85:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_ready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.rs1[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.rs2[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.rd[4:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.funct3[2:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.funct7[6:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.imm12[11:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.opcode[6:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.shamt[4:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_strb[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rd_val[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rs1_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rs1_val[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rs2_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.alu.alu_rs2_val[31:0] -@1401200 --ALU -@c00200 --Memfy -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.IO_MAP[63:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.IO_MAP_NB[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.aresetn -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_ready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_instbus[85:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_ready_fsm -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.imm12[11:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.state[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.waiting_rd_cpl -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.waiting_wr_cpl -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.addr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.io_map_hit[0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.is_io_req -@200 -- -@22 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.araddr[31:0] -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arcache[3:0] -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arid[7:0] -@28 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arvalid -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.arready -@200 -- -@22 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.rdata[31:0] -@820 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.rdata[31:0] -@28 -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.rresp[1:0] -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.rvalid -[color] 2 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.rready -@200 -- -@22 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awaddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awcache[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awid[7:0] -@28 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awvalid -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.awready -@200 -- -@22 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.wdata[31:0] -@820 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.wdata[31:0] -@22 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.wstrb[3:0] -@28 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.wvalid -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.wready -@200 -- -@28 -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.bresp[1:0] -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.bvalid -[color] 3 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.bready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs1_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs1_val[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs2_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs2_val[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_strb[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rd_val[31:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs1_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs1_val[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs2_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.memfy.memfy_rs2_val[31:0] -@1401200 --Memfy -@c00200 --divisor -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_instbus[85:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_ready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.funct3[2:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.funct7[6:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.opcode[6:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.rd[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.rs1[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.rs2[4:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.funct3_r[2:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.rd_wr_div -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.rd_r[4:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rd_wr -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rd_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rd_strb[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rd_val[31:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rs1_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rs1_val[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rs2_addr[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.m_rs2_val[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.aclk -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.aresetn -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.computing -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.i_ready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.i_valid -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.signed_div -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.divd[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.divs[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.o_ready -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.o_valid -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.quot[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.rem[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.zero_div -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.quot_next[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.quot_sign -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.rem_sign -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.rem_sub[32:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.srst -@22 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.step_cnt[4:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.acc[32:0] -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.processing.M_EXTENSION_SUPPORT.m_ext.div32.acc_next[32:0] -@1401200 --divisor --processing -@c00200 --peripheral --IO Subsystem -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.ADDRW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.DATAW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.DSCALE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.DWIX[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.IDW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.SLV0_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.SLV0_SIZE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.SLV1_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.SLV1_SIZE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.SLV2_ADDR[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.SLV2_SIZE[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.UART_FIFO_DEPTH[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.cfsm[1:0] -@200 -- -@c00200 --axi4-lite -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_awid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_awprot[2:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_awaddr[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_awvalid -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_awready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_wdata[127:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_wstrb[15:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_wvalid -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_wready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_bid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_bready -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_bresp[1:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_bvalid -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_araddr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_arid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_arready -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_arvalid -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_rdata[127:0] -@820 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_rdata[127:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_rvalid -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_rready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_rid[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv_rresp[1:0] -@1401200 --axi4-lite -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.mst_wr -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.mst_en -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.mst_ready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.mst_addr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.mst_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.mst_wdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.mst_strb[3:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv0_addr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv0_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv0_wdata[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv0_en -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv0_wr -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv0_ready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv1_addr[31:0] -@820 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv1_rdata[31:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv1_rdata[31:0] -@24 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv1_wdata[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv1_en -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv1_wr -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv1_ready -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv2_addr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv2_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv2_wdata[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv2_en -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv2_wr -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.slv2_ready -@1401200 --IO Subsystem -@c00200 --UART -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.ADDRW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.CLK_DIVIDER[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.RXTX_FIFO_DEPTH[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.XLEN[31:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.aclk -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.aresetn -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_en -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_wr -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_ready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_addr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_rdata[31:0] -@820 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_rdata[31:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_strb[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_wdata[31:0] -@820 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.slv_wdata[31:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.clock_divider[15:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.enable -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.busy -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.loopback_mode -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.parity_en -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.parity_mode -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.stop_mode -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register0[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register2[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register3[7:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register0[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register2[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register3[7:0] -@200 -- -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rxfsm[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rx_baud_cnt[15:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rx_bit_cnt[3:0] -@820 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rx_data[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rx_empty -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rx_full -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rx_pull -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.rx_push -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_push -@820 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register2[7:0] -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.register2[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.txfsm[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_baud_cnt[15:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_bit_cnt[3:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_data[7:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_data_srr[7:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_empty -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_full -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.tx_pull -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.uart_cts -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.uart_cts_sync -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.uart_rts -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.uart_rx -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.uart_rx_sync -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.uart.uart_tx -@1401200 --UART -@c00200 --Clint -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.ADDRW[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.XLEN[31:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.aclk -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.rtc -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.aresetn -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.slv_en -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.slv_wr -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.slv_ready -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.slv_addr[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.slv_rdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.slv_wdata[31:0] -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.slv_strb[3:0] -@200 -- -@28 -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ext_irq -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.ext_irq_sync -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.sw_irq -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.sw_irq_sync -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.timer_irq -friscv_testbench.friscv_testbench.genblk2.dut.cpu0.csrs.timer_irq_sync -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.mtime[63:0] -@28 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.mtime_en -@22 -friscv_testbench.friscv_testbench.genblk2.dut.io_subsystem.clint.mtimecmp[63:0] -@1401200 --Clint --peripheral +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x1_ra[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x2_sp[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x3_gp[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x4_tp[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x5_t0[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x6_t1[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x7_t2[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x8_s0_fp[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x9_s1[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x10_a0[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x11_a1[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x12_a2[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x13_a3[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x14_a4[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x15_a5[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x16_a6[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x17_a7[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x18_s2[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x19_s3[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x20_s4[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x21_s5[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x22_s6[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x23_s7[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x24_s8[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x25_s9[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x26_s10[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x27_s11[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x28_t3[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x29_t4[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x30_t5[31:0] +friscv_testbench.friscv_testbench.genblk2.dut.cpu0.isa_registers.x31_t6[31:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/test/priv_sec_testsuite/tests/env/p/riscv_test.h b/test/priv_sec_testsuite/tests/env/p/riscv_test.h index 19a9b73..38823cb 100644 --- a/test/priv_sec_testsuite/tests/env/p/riscv_test.h +++ b/test/priv_sec_testsuite/tests/env/p/riscv_test.h @@ -169,12 +169,14 @@ _start: \ trap_vector: \ /* test whether the test came from pass/fail */ \ csrr t5, mcause; \ - li t6, CAUSE_USER_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_SUPERVISOR_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_MACHINE_ECALL; \ - beq t5, t6, write_tohost; \ + li t4, CAUSE_USER_ECALL; \ + beq t5, t4, ECALL_USER_MODE; \ + li t4, CAUSE_SUPERVISOR_ECALL; \ + beq t5, t4, ECALL_SUPERVISOR_MODE; \ + li t4, CAUSE_MACHINE_ECALL; \ + beq t5, t4, ECALL_MACHINE_MODE; \ + li t4, 2; \ + beq t5, t4, ILLEGAL_INSTRUCTION; \ /* if an mtvec_handler is defined, jump to it */ \ la t5, mtvec_handler; \ beqz t5, 1f; \ @@ -188,9 +190,7 @@ handle_exception: \ other_exception: \ /* some unhandlable exception occurred */ \ 1: ori TESTNUM, TESTNUM, 1337; \ - write_tohost: \ sw TESTNUM, tohost, t5; \ - j write_tohost; \ reset_vector: \ INIT_XREG; \ RISCV_MULTICORE_DISABLE; \ diff --git a/test/priv_sec_testsuite/tests/rv32ui-p-test0.v b/test/priv_sec_testsuite/tests/rv32ui-p-test0.v index 7a1eb14..584553a 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-p-test0.v +++ b/test/priv_sec_testsuite/tests/rv32ui-p-test0.v @@ -1,32 +1,40 @@ @00010000 -6F 00 80 04 73 2F 20 34 93 0F 80 00 63 08 FF 03 -93 0F 90 00 63 04 FF 03 93 0F B0 00 63 00 FF 03 -13 0F 00 00 63 04 0F 00 67 00 0F 00 73 2F 20 34 -63 54 0F 00 6F 00 40 00 93 E1 91 53 17 1F 00 00 -23 22 3F FC 6F F0 9F FF 93 00 00 00 13 01 00 00 -93 01 00 00 13 02 00 00 93 02 00 00 13 03 00 00 -93 03 00 00 13 04 00 00 93 04 00 00 13 05 00 00 -93 05 00 00 13 06 00 00 93 06 00 00 13 07 00 00 -93 07 00 00 13 08 00 00 93 08 00 00 13 09 00 00 -93 09 00 00 13 0A 00 00 93 0A 00 00 13 0B 00 00 -93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0D 00 00 -93 0D 00 00 13 0E 00 00 93 0E 00 00 13 0F 00 00 -93 0F 00 00 73 25 40 F1 63 10 05 00 97 02 00 00 -93 82 02 01 73 90 52 30 73 50 00 18 97 02 00 00 -93 82 02 02 73 90 52 30 B7 02 00 80 93 82 F2 FF -73 90 02 3B 93 02 F0 01 73 90 02 3A 73 50 40 30 -97 02 00 00 93 82 42 01 73 90 52 30 73 50 20 30 -73 50 30 30 93 01 00 00 97 02 00 00 93 82 C2 EE -73 90 52 30 13 05 10 00 13 15 F5 01 63 4C 05 00 -0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00 -73 00 10 00 93 02 00 00 63 8A 02 00 73 90 52 10 -B7 B2 00 00 93 82 92 10 73 90 22 30 73 50 00 30 -97 02 00 00 93 82 42 01 73 90 12 34 73 25 40 F1 -73 00 20 30 6F 00 40 00 6F 00 80 02 63 12 30 02 -0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 -93 08 D0 05 13 85 01 00 93 8F 1F 00 73 00 10 00 -0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00 -73 00 10 00 73 00 10 00 73 10 00 C0 +6F 00 C0 04 73 2F 20 34 93 0E 80 00 63 0C DF 17 +93 0E 90 00 63 04 DF 17 93 0E B0 00 63 0E DF 17 +93 0E 20 00 63 0C DF 17 13 0F 00 00 63 04 0F 00 +67 00 0F 00 73 2F 20 34 63 54 0F 00 6F 00 40 00 +93 E1 91 53 17 1F 00 00 23 2E 3F FA 93 00 00 00 +13 01 00 00 93 01 00 00 13 02 00 00 93 02 00 00 +13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 +13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 +13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 +13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 +13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 +13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 +13 0F 00 00 93 0F 00 00 73 25 40 F1 63 10 05 00 +97 02 00 00 93 82 02 01 73 90 52 30 73 50 00 18 +97 02 00 00 93 82 02 02 73 90 52 30 B7 02 00 80 +93 82 F2 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A +73 50 40 30 97 02 00 00 93 82 42 01 73 90 52 30 +73 50 20 30 73 50 30 30 93 01 00 00 97 02 00 00 +93 82 82 EE 73 90 52 30 13 05 10 00 13 15 F5 01 +63 4C 05 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05 +13 05 00 00 73 00 10 00 93 02 00 00 63 8A 02 00 +73 90 52 10 B7 B2 00 00 93 82 92 10 73 90 22 30 +73 50 00 30 97 02 00 00 93 82 42 01 73 90 12 34 +73 25 40 F1 73 00 20 30 6F 00 80 03 93 8F 1F 00 +73 00 10 00 13 0A 1A 00 F3 2E 10 34 93 8E 4E 00 +73 90 1E 34 73 00 20 30 73 00 10 00 13 0A 1A 00 +F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30 +73 00 00 00 93 00 10 00 63 12 1A 02 73 00 20 30 +93 80 10 00 63 1C 1A 00 F3 2E 00 30 93 80 10 00 +63 16 1A 00 6F 00 80 02 63 12 30 02 0F 00 F0 0F +63 80 01 00 93 91 11 00 93 E1 11 00 93 08 D0 05 +13 85 01 00 93 8F 1F 00 73 00 10 00 0F 00 F0 0F +93 01 10 00 93 08 D0 05 13 05 00 00 73 00 10 00 +73 00 10 00 73 10 00 C0 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 @00011000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/test/priv_sec_testsuite/tests/rv32ui-v-test0.v b/test/priv_sec_testsuite/tests/rv32ui-v-test0.v index 625fde1..f454bb8 100755 --- a/test/priv_sec_testsuite/tests/rv32ui-v-test0.v +++ b/test/priv_sec_testsuite/tests/rv32ui-v-test0.v @@ -121,11 +121,11 @@ E3 9C 07 FD 73 90 08 10 93 97 26 00 B3 06 F6 00 63 94 E5 04 93 96 26 00 B3 06 D6 00 23 A0 F6 00 73 00 05 12 83 20 C1 00 13 01 01 01 67 80 00 00 93 E7 07 04 6F F0 1F FE 97 47 00 00 23 A4 07 AC -6F F0 1F F0 17 05 00 00 13 05 85 4C EF F0 5F D0 -13 05 30 00 EF F0 5F D6 17 05 00 00 13 05 85 4F +6F F0 1F F0 17 05 00 00 13 05 05 52 EF F0 5F D0 +13 05 30 00 EF F0 5F D6 17 05 00 00 13 05 05 55 EF F0 1F CF 13 05 30 00 EF F0 1F D5 17 05 00 00 -13 05 C5 52 EF F0 DF CD 13 05 30 00 EF F0 DF D3 -17 05 00 00 13 05 05 53 EF F0 9F CC 13 05 30 00 +13 05 45 58 EF F0 DF CD 13 05 30 00 EF F0 DF D3 +17 05 00 00 13 05 85 58 EF F0 9F CC 13 05 30 00 EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04 23 26 11 04 23 22 91 04 23 20 21 05 23 2E 31 03 23 2C 41 03 23 2A 51 03 23 28 61 03 23 26 71 03 @@ -139,14 +139,14 @@ EF F0 9F D2 83 25 C5 08 13 01 01 FB 23 24 81 04 03 2D 01 02 83 2D C1 01 13 01 01 05 6F D0 1F A8 03 27 45 08 93 77 37 00 63 98 07 08 EF 07 80 00 73 10 30 00 03 27 07 00 83 A7 07 00 63 0A F7 06 -13 05 10 04 97 05 00 00 93 85 85 48 97 F6 FF FF +13 05 10 04 97 05 00 00 93 85 05 4E 97 F6 FF FF 93 86 46 99 17 F6 FF FF 13 06 C6 9C 03 A7 06 00 83 A7 46 00 13 08 05 00 93 85 15 00 33 67 F7 00 B7 08 01 01 63 02 07 02 13 07 00 00 23 20 E6 00 93 07 00 00 23 22 F6 00 03 A7 06 00 83 A7 46 00 33 67 F7 00 E3 12 07 FE 03 C5 05 00 23 A0 06 01 23 A2 16 01 E3 1C 05 FA 13 05 30 00 EF F0 DF BE -13 05 10 00 EF F0 5F BE 17 05 00 00 13 05 85 4A +13 05 10 00 EF F0 5F BE 17 05 00 00 13 05 05 50 EF F0 1F B7 13 05 30 00 EF F0 1F BD 03 29 85 02 37 1C 00 00 97 14 00 00 93 84 C4 90 97 2B 00 00 93 8B 4B 90 37 0B 04 00 B7 0A C0 FF 97 4D 00 00 @@ -160,10 +160,10 @@ EF F0 1F B7 13 05 30 00 EF F0 1F BD 03 29 85 02 93 FC 0C 08 83 25 C1 00 63 80 0C 04 37 16 00 00 13 05 0C 00 EF F0 DF 86 B3 87 84 00 73 10 0D 10 03 A7 0D 00 23 A0 07 00 E3 1E 07 F6 23 A0 FD 00 -23 20 FA 00 6F F0 9F F7 17 05 00 00 13 05 C5 3E -EF F0 1F A9 6F F0 5F F0 17 05 00 00 13 05 45 38 +23 20 FA 00 6F F0 9F F7 17 05 00 00 13 05 45 44 +EF F0 1F A9 6F F0 5F F0 17 05 00 00 13 05 C5 3D EF F0 1F A8 13 05 30 00 EF F0 1F AE 17 05 00 00 -13 05 C5 33 EF F0 DF A6 13 05 30 00 EF F0 DF AC +13 05 45 39 EF F0 DF A6 13 05 30 00 EF F0 DF AC 13 05 09 00 EF F0 5F AC F3 27 40 F1 63 96 07 16 17 36 00 00 13 06 06 80 93 57 C6 00 13 01 01 F6 93 97 A7 00 23 2E 11 08 23 2C 81 08 97 15 00 00 @@ -193,12 +193,18 @@ EF F0 CF F1 B7 07 00 80 33 04 F4 00 13 05 01 00 93 D6 17 00 B3 E6 D5 00 B3 C7 D7 00 93 97 E7 01 B3 75 F5 00 13 57 17 00 93 87 06 00 33 E7 E5 00 B3 F6 C7 00 93 F5 17 00 B3 86 06 01 E3 96 05 FC -03 A0 06 00 6F F0 9F FC 17 05 00 00 13 05 85 20 +03 A0 06 00 6F F0 9F FC 17 05 00 00 13 05 05 26 EF F0 1F 88 13 05 30 00 EF F0 1F 8E 67 80 00 00 -6F 00 40 00 6F 00 80 01 63 1A 30 00 13 95 11 00 -63 00 05 00 13 65 15 00 73 00 00 00 13 05 10 00 -73 00 00 00 73 00 10 00 73 10 00 C0 -@80002A0C +6F 00 80 03 93 8F 1F 00 73 00 10 00 13 0A 1A 00 +F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30 +73 00 10 00 13 0A 1A 00 F3 2E 10 34 93 8E 4E 00 +73 90 1E 34 73 00 20 30 73 00 00 00 93 00 10 00 +63 12 1A 02 73 00 20 30 93 80 10 00 63 1C 1A 00 +F3 2E 00 30 93 80 10 00 63 16 1A 00 6F 00 80 01 +63 1A 30 00 13 95 11 00 63 00 05 00 13 65 15 00 +73 00 00 00 13 05 10 00 73 00 00 00 73 00 10 00 +73 10 00 C0 +@80002A64 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20 diff --git a/test/priv_sec_testsuite/tests/rv64ui-p-test0.v b/test/priv_sec_testsuite/tests/rv64ui-p-test0.v index f6641a3..41de969 100755 --- a/test/priv_sec_testsuite/tests/rv64ui-p-test0.v +++ b/test/priv_sec_testsuite/tests/rv64ui-p-test0.v @@ -1,34 +1,38 @@ @00010000 -6F 00 80 04 73 2F 20 34 93 0F 80 00 63 08 FF 03 -93 0F 90 00 63 04 FF 03 93 0F B0 00 63 00 FF 03 -13 0F 00 00 63 04 0F 00 67 00 0F 00 73 2F 20 34 -63 54 0F 00 6F 00 40 00 93 E1 91 53 17 1F 00 00 -23 22 3F FC 6F F0 9F FF 93 00 00 00 13 01 00 00 -93 01 00 00 13 02 00 00 93 02 00 00 13 03 00 00 -93 03 00 00 13 04 00 00 93 04 00 00 13 05 00 00 -93 05 00 00 13 06 00 00 93 06 00 00 13 07 00 00 -93 07 00 00 13 08 00 00 93 08 00 00 13 09 00 00 -93 09 00 00 13 0A 00 00 93 0A 00 00 13 0B 00 00 -93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0D 00 00 -93 0D 00 00 13 0E 00 00 93 0E 00 00 13 0F 00 00 -93 0F 00 00 73 25 40 F1 63 10 05 00 97 02 00 00 -93 82 02 01 73 90 52 30 73 50 00 18 97 02 00 00 -93 82 42 02 73 90 52 30 9B 02 10 00 93 92 52 03 -93 82 F2 FF 73 90 02 3B 93 02 F0 01 73 90 02 3A -73 50 40 30 97 02 00 00 93 82 42 01 73 90 52 30 -73 50 20 30 73 50 30 30 93 01 00 00 97 02 00 00 -93 82 82 EE 73 90 52 30 13 05 10 00 13 15 F5 01 -63 5C 05 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05 -13 05 00 00 73 00 10 00 93 02 00 00 63 8A 02 00 -73 90 52 10 B7 B2 00 00 9B 82 92 10 73 90 22 30 -73 50 00 30 97 02 00 00 93 82 42 01 73 90 12 34 -73 25 40 F1 73 00 20 30 6F 00 40 00 6F 00 80 02 -63 12 30 02 0F 00 F0 0F 63 80 01 00 93 91 11 00 -93 E1 11 00 93 08 D0 05 13 85 01 00 93 8F 1F 00 -73 00 10 00 0F 00 F0 0F 93 01 10 00 93 08 D0 05 -13 05 00 00 73 00 10 00 73 00 10 00 73 10 00 C0 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +6F 00 C0 04 73 2F 20 34 93 0E 80 00 63 0E DF 17 +93 0E 90 00 63 06 DF 17 93 0E B0 00 63 00 DF 19 +93 0E 20 00 63 0E DF 17 13 0F 00 00 63 04 0F 00 +67 00 0F 00 73 2F 20 34 63 54 0F 00 6F 00 40 00 +93 E1 91 53 17 1F 00 00 23 2E 3F FA 93 00 00 00 +13 01 00 00 93 01 00 00 13 02 00 00 93 02 00 00 +13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 +13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 +13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 +13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 +13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 +13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 +13 0F 00 00 93 0F 00 00 73 25 40 F1 63 10 05 00 +97 02 00 00 93 82 02 01 73 90 52 30 73 50 00 18 +97 02 00 00 93 82 42 02 73 90 52 30 9B 02 10 00 +93 92 52 03 93 82 F2 FF 73 90 02 3B 93 02 F0 01 +73 90 02 3A 73 50 40 30 97 02 00 00 93 82 42 01 +73 90 52 30 73 50 20 30 73 50 30 30 93 01 00 00 +97 02 00 00 93 82 42 EE 73 90 52 30 13 05 10 00 +13 15 F5 01 63 5C 05 00 0F 00 F0 0F 93 01 10 00 +93 08 D0 05 13 05 00 00 73 00 10 00 93 02 00 00 +63 8A 02 00 73 90 52 10 B7 B2 00 00 9B 82 92 10 +73 90 22 30 73 50 00 30 97 02 00 00 93 82 42 01 +73 90 12 34 73 25 40 F1 73 00 20 30 6F 00 80 03 +93 8F 1F 00 73 00 10 00 13 0A 1A 00 F3 2E 10 34 +93 8E 4E 00 73 90 1E 34 73 00 20 30 73 00 10 00 +13 0A 1A 00 F3 2E 10 34 93 8E 4E 00 73 90 1E 34 +73 00 20 30 73 00 00 00 93 00 10 00 63 12 1A 02 +73 00 20 30 93 80 10 00 63 1C 1A 00 F3 2E 00 30 +93 80 10 00 63 16 1A 00 6F 00 80 02 63 12 30 02 +0F 00 F0 0F 63 80 01 00 93 91 11 00 93 E1 11 00 +93 08 D0 05 13 85 01 00 93 8F 1F 00 73 00 10 00 +0F 00 F0 0F 93 01 10 00 93 08 D0 05 13 05 00 00 +73 00 10 00 73 00 10 00 73 10 00 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @00011000 diff --git a/test/priv_sec_testsuite/tests/rv64ui-v-test0.v b/test/priv_sec_testsuite/tests/rv64ui-v-test0.v index 91e12e0..e01f30b 100755 --- a/test/priv_sec_testsuite/tests/rv64ui-v-test0.v +++ b/test/priv_sec_testsuite/tests/rv64ui-v-test0.v @@ -114,11 +114,11 @@ E3 9C 07 FD 73 90 08 10 93 97 36 00 B3 06 F6 00 63 94 E5 04 93 96 36 00 B3 06 D6 00 23 B0 F6 00 73 00 05 12 83 30 81 00 13 01 01 01 67 80 00 00 93 E7 07 04 6F F0 1F FE 97 67 00 00 23 BC 07 B2 -6F F0 1F F0 17 05 00 00 13 05 45 4C EF F0 1F D8 -13 05 30 00 EF F0 1F DC 17 05 00 00 13 05 85 4F +6F F0 1F F0 17 05 00 00 13 05 C5 51 EF F0 1F D8 +13 05 30 00 EF F0 1F DC 17 05 00 00 13 05 05 55 EF F0 DF D6 13 05 30 00 EF F0 DF DA 17 05 00 00 -13 05 C5 52 EF F0 9F D5 13 05 30 00 EF F0 9F D9 -17 05 00 00 13 05 05 53 EF F0 5F D4 13 05 30 00 +13 05 45 58 EF F0 9F D5 13 05 30 00 EF F0 9F D9 +17 05 00 00 13 05 85 58 EF F0 5F D4 13 05 30 00 EF F0 5F D8 83 35 85 11 13 01 01 F8 23 38 81 06 23 3C 11 06 23 34 91 06 23 30 21 07 23 3C 31 05 23 38 41 05 23 34 51 05 23 30 61 05 23 3C 71 03 @@ -132,12 +132,12 @@ EF F0 5F D8 83 35 85 11 13 01 01 F8 23 38 81 06 03 3D 01 02 83 3D 81 01 13 01 01 08 6F D0 1F AF 03 37 85 10 93 77 37 00 63 98 07 06 EF 07 80 00 73 10 30 00 03 27 07 00 83 A7 07 00 63 0A F7 04 -13 05 10 10 93 07 10 04 97 06 00 00 93 86 86 48 +13 05 10 10 93 07 10 04 97 06 00 00 93 86 06 4E 17 F7 FF FF 13 07 07 A0 13 15 05 03 83 35 07 00 93 86 16 00 33 E6 A7 00 63 8A 05 00 97 F7 FF FF 23 B2 07 A2 83 37 07 00 E3 9A 07 FE 83 C7 06 00 23 30 C7 00 E3 9C 07 FC 13 05 30 00 EF F0 9F C6 -13 05 10 00 EF F0 1F C6 17 05 00 00 13 05 85 4D +13 05 10 00 EF F0 1F C6 17 05 00 00 13 05 05 53 EF F0 DF C0 13 05 30 00 EF F0 DF C4 03 29 05 05 37 1C 00 00 97 14 00 00 93 84 C4 99 97 2B 00 00 93 8B 4B 99 37 0B 04 00 B7 0A E0 FF 97 6D 00 00 @@ -151,10 +151,10 @@ EF F0 DF C0 13 05 30 00 EF F0 DF C4 03 29 05 05 93 FC 0C 08 83 35 81 00 63 80 0C 04 37 16 00 00 13 05 0C 00 EF F0 DF 8F B3 87 84 00 73 10 0D 10 03 B7 0D 00 23 B0 07 00 E3 1E 07 F6 23 B0 FD 00 -23 30 FA 00 6F F0 9F F7 17 05 00 00 13 05 05 42 -EF F0 DF B2 6F F0 5F F0 17 05 00 00 13 05 05 3B +23 30 FA 00 6F F0 9F F7 17 05 00 00 13 05 85 47 +EF F0 DF B2 6F F0 5F F0 17 05 00 00 13 05 85 40 EF F0 DF B1 13 05 30 00 EF F0 DF B5 17 05 00 00 -13 05 45 36 EF F0 9F B0 13 05 30 00 EF F0 9F B4 +13 05 C5 3B EF F0 9F B0 13 05 30 00 EF F0 9F B4 13 05 09 00 EF F0 1F B4 F3 27 40 F1 63 9A 07 18 97 47 00 00 93 87 07 89 13 01 01 ED 93 D7 C7 00 23 30 81 12 17 58 00 00 13 08 C8 87 13 04 05 00 @@ -186,12 +186,17 @@ E3 1A E3 FC 13 06 00 12 93 05 00 00 13 05 01 00 2F 20 07 00 13 D7 17 00 B3 C7 E7 00 93 97 E7 03 B3 F7 D7 00 B3 E7 E7 00 33 F7 C7 00 93 F5 17 00 33 07 A7 00 E3 9E 05 FC 03 20 07 00 6F F0 9F FD -17 05 00 00 13 05 85 22 EF F0 5F 90 13 05 30 00 -EF F0 5F 94 67 80 00 00 6F 00 40 00 6F 00 80 01 -63 1A 30 00 13 95 11 00 63 00 05 00 13 65 15 00 -73 00 00 00 13 05 10 00 73 00 00 00 73 00 10 00 -73 10 00 C0 -@80002998 +17 05 00 00 13 05 05 28 EF F0 5F 90 13 05 30 00 +EF F0 5F 94 67 80 00 00 6F 00 80 03 93 8F 1F 00 +73 00 10 00 13 0A 1A 00 F3 2E 10 34 93 8E 4E 00 +73 90 1E 34 73 00 20 30 73 00 10 00 13 0A 1A 00 +F3 2E 10 34 93 8E 4E 00 73 90 1E 34 73 00 20 30 +73 00 00 00 93 00 10 00 63 12 1A 02 73 00 20 30 +93 80 10 00 63 1C 1A 00 F3 2E 00 30 93 80 10 00 +63 16 1A 00 6F 00 80 01 63 1A 30 00 13 95 11 00 +63 00 05 00 13 65 15 00 73 00 00 00 13 05 10 00 +73 00 00 00 73 00 10 00 73 10 00 C0 +@800029F0 41 73 73 65 72 74 69 6F 6E 20 66 61 69 6C 65 64 3A 20 61 64 64 72 20 3E 3D 20 28 31 55 4C 20 3C 3C 20 31 32 29 20 26 26 20 61 64 64 72 20 3C 20 diff --git a/test/priv_sec_testsuite/tests/rv64ui/test0.S b/test/priv_sec_testsuite/tests/rv64ui/test0.S index 0f15655..6276817 100644 --- a/test/priv_sec_testsuite/tests/rv64ui/test0.S +++ b/test/priv_sec_testsuite/tests/rv64ui/test0.S @@ -7,24 +7,70 @@ #include "riscv_test.h" #include "test_macros.h" -# Test 1: Sequence of LUI / AUIPC / Arithmetic instructions +# Test 0: M-mode <-> U-mode transition. # -# Injects a set of alternating LUI / AUIPC / Aritmetic instructions to ensure the -# control unit correctly handles this kind of situation. +# Basic test to ensure we can move back and forth the modes +# and manage correctly ebreak/mret and execute a basic program # -# All these instructions are handled in one cycle and shouldn't introduce any -# wait cycles between each others. - # x3/gp is the tes number in the unit test flow, must be greater than 0 # 0 means the processor din't move out the initialization correctly and is stucked +# +# x20/s4 stores a count of ecall/trap executed, used to ensure +# we enter the right number of time into them along the test +# +# x31 is the error status register to trigger the testbench status +# when encounter a problem during the testcase RVTEST_RV64U RVTEST_CODE_BEGIN j TEST +# Not supported for the moment +ECALL_SUPERVISOR_MODE: + add x31, x31, 1 + ebreak + +ECALL_USER_MODE: + add x20, x20, 1 + # Increment PC value to return next instruction + csrr t4, mepc + add t4, t4, 4 + csrw mepc, t4 + mret + +ECALL_MACHINE_MODE: + ebreak + +ILLEGAL_INSTRUCTION: + add x20, x20, 1 + # Increment PC value to return next instruction + csrr t4, mepc + add t4, t4, 4 + csrw mepc, t4 + mret + TEST: +# Try a basic ecall instruction +TEST1: + ecall + li x1, 1 + bne x20, x1, fail + +# Try to mret with user mode +TEST2: + mret + add x1, x1, 1 + bne x20, x1, fail + +# Try to access machine-mode CSR +TEST3: + csrr t4, mstatus + add x1, x1, 1 + bne x20, x1, fail + + j pass TEST_PASSFAIL