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x80.cxx
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// 8080 and Z80 emulator.
// Written by David Lee
// useful: https://pastraiser.com/cpu/i8080/i8080_opcodes.html
// https://altairclone.com/downloads/manuals/8080%20Programmers%20Manual.pdf
// http://popolony2k.com.br/xtras/programming/asm/nemesis-lonestar/8080-z80-instruction-set.html
// https://www.zilog.com/docs/z80/um0080.pdf
// http://www.z80.info/z80time.txt
// http://www.z80.info/zip/z80-documented.pdf
// http://www.z80.info/z80undoc.htm
// http://www.z80.info/z80sflag.htm
// http://www.righto.com/2012/12/the-6502-overflow-flag-explained.html
// https://mdfs.net/Software/Z80/Exerciser/
// https://onlinedisassembler.com/odaweb/
// symbols that start with z80_ are (unsurprisingly) Z80-specific. 80% of this code is Z80-specific.
// 8080 emulation would be >20% faster if not for the z80 checks
// Validated 100% pass for 8080 with 8080ex1.com, 8080pre.com, Microcosm v1.0, and cputest.com Diagnostics II V1.2 in 8080 mode.
// Validated 100% pass for Z80 with zexall.com, zexdoc.com, and cputest.com in Z80 mode.
#include <stdio.h>
#include <memory.h>
#include <assert.h>
#include <vector>
#include <cstring>
#include <bitset>
#include <djl_os.hxx>
#include <djltrace.hxx>
using namespace std;
#include "x80.hxx"
uint8_t memory[ 65536 ];
registers reg;
static const char * reg_strings[ 8 ] = { "b", "c", "d", "e", "h", "l", "m", "a" };
static const char * rp_strings[ 4 ] = { "bc", "de", "hl", "sp" };
static const char * z80_math_strings[ 8 ] = { "add", "adc", "sub", "sbb", "and", "xor", "or", "cp" };
static const char * z80_rotate_strings[ 8 ] = { "rlc", "rrc", "rl", "rr", "sla", "sra", "sll", "srl" };
static uint8_t g_State = 0;
const uint8_t stateTraceInstructions = 1;
const uint8_t stateEndEmulation = 2;
void x80_trace_instructions( bool t ) { if ( t ) g_State |= stateTraceInstructions; else g_State &= ~stateTraceInstructions; }
void x80_end_emulation() { g_State |= stateEndEmulation; }
enum z80_value_source { vs_register, vs_memory, vs_indexed }; // this impacts how Z80 undocumented Y and X flags are updated
const uint8_t cyclesnt = 6; // cycles not taken when a conditional call, jump, or return isn't taken
// instructions starting with '*' are undocumented for 8080, and not implemented here. They also signal likely Z80 instructions
static const char i8080_instructions[ 256 ][ 16 ] =
{
/*00*/ "nop", "lxi b, d16", "stax b", "inx b", "inr b", "dcr b", "mvi b, d8", "rlc",
/*08*/ "*nop", "dad b", "ldax b", "dcx b", "inr c", "dcr c", "mvi c, d8", "rrc",
/*10*/ "*nop", "lxi d, d16", "stax d", "inx d", "inr d", "dcr d", "mvi d, d8", "ral",
/*18*/ "*nop", "dad d", "ldax d", "dcx d", "inr e", "dcr e", "mvi e, d8", "rar",
/*20*/ "*nop", "lxi h, d16", "shld a16", "inx h", "inr h", "dcr h", "mvi h, d8", "daa",
/*28*/ "*nop", "dad h", "lhld a16", "dcx h", "inr l", "dcr l", "mvi l, d8", "cma",
/*30*/ "*nop", "lxi sp, d16", "sta a16", "inx sp", "inr m", "dcr m", "mvi m, d8", "stc",
/*38*/ "*nop", "dad sp", "lda a16", "dcx sp", "inr a", "dcr a", "mvi a, d8", "cmc",
/*40*/ "mov b, b", "mov b, c", "mov b, d", "mov b, e", "mov b, h", "mov b, l", "mov b, m", "mov b, a",
/*48*/ "mov c, b", "mov c, c", "mov c, d", "mov c, e", "mov c, h", "mov c, l", "mov c, m", "mov c, a",
/*50*/ "mov d, b", "mov d, c", "mov d, d", "mov d, e", "mov d, h", "mov d, l", "mov d, m", "mov d, a",
/*58*/ "mov e, b", "mov e, c", "mov e, d", "mov e, e", "mov e, h", "mov e, l", "mov e, m", "mov e, a",
/*60*/ "mov h, b", "mov h, c", "mov h, d", "mov h, e", "(hook)", "mov h, l", "mov h, m", "mov h, a",
/*68*/ "mov l, b", "mov l, c", "mov l, d", "mov l, e", "mov l, h", "mov l, l", "mov l, m", "mov l, a",
/*70*/ "mov m, b", "mov m, c", "mov m, d", "mov m, e", "mov m, h", "mov m, l", "hlt", "mov m, a",
/*78*/ "mov a, b", "mov a, c", "mov a, d", "mov a, e", "mov a, h", "mov a, l", "mov a, m", "mov a, a",
/*80*/ "add b", "add c", "add d", "add e", "add h", "add l", "add m", "add a",
/*88*/ "adc b", "adc c", "adc d", "adc e", "adc h", "adc l", "adc m", "adc a",
/*90*/ "sub b", "sub c", "sub d", "sub e", "sub h", "sub l", "sub m", "sub a",
/*98*/ "sbb b", "sbb c", "sbb d", "sbb e", "sbb h", "sbb l", "sbb m", "sbb a",
/*a0*/ "ana b", "ana c", "ana d", "ana e", "ana h", "ana l", "ana m", "ana a",
/*a8*/ "xra b", "xra c", "xra d", "xra e", "xra h", "xra l", "xra m", "xra a",
/*b0*/ "ora b", "ora c", "ora d", "ora e", "ora h", "ora l", "ora m", "ora a",
/*b8*/ "cmp b", "cmp c", "cmp d", "cmp e", "cmp h", "cmp l", "cmp m", "cmp a",
/*c0*/ "rnz", "pop b", "jnz a16", "jmp a16", "cnz a16", "push b", "adi d8", "rst 0",
/*c8*/ "rz", "ret", "jz a16", "*jmp", "cz a16", "call a16", "aci d8", "rst 1",
/*d0*/ "rnc", "pop d", "jnc a16", "out d8", "cnc a16", "push d", "sui d8", "rst 2",
/*d8*/ "rc", "*ret", "jc a16", "in d8", "cc a16", "*call a16", "sbi d8", "rst 3",
/*e0*/ "rpo", "pop h", "jpo a16", "xthl", "cpo a16", "push h", "ani d8", "rst 4",
/*e8*/ "rpe", "pchl", "jpe a16", "xchg", "cpe a16", "*call a16", "xri d8", "rst 5",
/*f0*/ "rp", "pop psw", "jp a16", "di", "cp a16", "push psw", "ori d8", "rst 6",
/*f8*/ "rm", "sphl", "jm a16", "ei", "cm a16", "*call a16", "cpi d8", "rst 7",
};
// instructions starting with '*' are Z80-specific, generally multi-byte, and handled separately.
// instructions listed here are the overlap with 8080 but with the Z80 naming.
static const char z80_instructions[ 256 ][ 16 ] =
{
/*00*/ "nop", "ld bc, d16", "ld (bc), a", "inc bc", "inc b", "dec b", "ld b, d8", "rlca",
/*08*/ "*'", "add hl, bc", "ld a, (bc)", "dec bc", "inc c", "dec c", "ld c, d8", "rrca",
/*10*/ "*", "ld de, d16", "ld (de), a", "inc de", "inc d", "dec d", "ld d, d8", "rla",
/*18*/ "*", "add hl, de", "ld a, (de)", "dec de", "inc e", "dec e", "ld e, d8", "rra",
/*20*/ "*", "ld hl, d16", "ld (a16), hl", "inc hl", "inc h", "dec h", "ld h, d8", "daa",
/*28*/ "*", "add hl, hl", "ld hl, (a16)", "dec hl", "inc l", "dec l", "ld l, d8", "cpl",
/*30*/ "*", "ld sp, d16", "ld (a16), a", "inc sp", "inc (hl)", "dec (hl)", "ld (hl), d8", "scf",
/*38*/ "*", "add hl, sp", "ld a, (a16)", "dec sp", "inc a", "dec a", "ld a, d8", "ccf",
/*40*/ "ld b, b", "ld b, c", "ld b, d", "ld b, e", "ld b, h", "ld b, l", "ld b, (hl)", "ld b, a",
/*48*/ "ld c, b", "ld c, c", "ld c, d", "ld c, e", "ld c, h", "ld c, l", "ld c, (hl)", "ld c, a",
/*50*/ "ld d, b", "ld d, c", "ld d, d", "ld d, e", "ld d, h", "ld d, l", "ld d, (hl)", "ld d, a",
/*58*/ "ld e, b", "ld e, c", "ld e, d", "ld e, e", "ld e, h", "ld e, l", "ld e, (hl)", "ld e, a",
/*60*/ "ld h, b", "ld h, c", "ld h, d", "ld h, e", "(hook)", "ld h, l", "ld h, (hl)", "ld h, a",
/*68*/ "ld l, b", "ld l, c", "ld l, d", "ld l, e", "ld l, h", "ld l, l", "ld l, (hl)", "ld l, a",
/*70*/ "ld (hl), b", "ld (hl), c", "ld (hl), d", "ld (hl), e", "ld (hl), h", "ld (hl), l", "halt", "ld (hl), a",
/*78*/ "ld a, b", "ld a, c", "ld a, d", "ld a, e", "ld a, h", "ld a, l", "ld a, (hl)", "ld a, a",
/*80*/ "add a, b", "add a, c", "add a, d", "add a, e", "add a, h", "add a, l", "add a, (hl)", "add a, a",
/*88*/ "adc a, b", "adc a, c", "adc a, d", "adc a, e", "adc a, h", "adc a, l", "adc a, (hl)", "adc a, a",
/*90*/ "sub b", "sub c", "sub d", "sub e", "sub h", "sub l", "sub (hl)", "sub a",
/*98*/ "sbc a, b", "sbc a, c", "sbc a, d", "sbc a, e", "sbc a, h", "sbc a, l", "sbc a, (hl)", "sbc a, a",
/*a0*/ "and b", "and c", "and d", "and e", "and h", "and l", "and (hl)", "and a",
/*a8*/ "xor b", "xor c", "xor d", "xor e", "xor h", "xor l", "xor (hl)", "xor a",
/*b0*/ "or b", "or c", "or d", "or e", "or h", "or l", "or (hl)", "or a",
/*b8*/ "cp b", "cp c", "cp d", "cp e", "cp h", "cp l", "cp (hl)", "cp a",
/*c0*/ "ret nz", "pop bc", "jp nz, a16", "jp a16", "call nz, a16", "push bc", "add a, d8", "rst 0",
/*c8*/ "ret z", "ret", "jp z, a16", "*", "call z, a16", "call a16", "adc a, d8", "rst 1",
/*d0*/ "ret nc", "pop de", "jp nc, a16", "out (d8), a", "call nc, a16", "push de", "sub d8", "rst 2",
/*d8*/ "ret c", "*", "jp c, a16", "in a, (d8)", "call c, a16", "*", "sbc d8", "rst 3",
/*e0*/ "ret po", "pop hl", "jp po, a16", "ex (sp), hl", "call po, a16", "push hl", "and d8", "rst 4",
/*e8*/ "ret pe", "jp (hl)", "jp pe, a16", "ex de, hl", "call pe, a16", "*", "xor d8", "rst 5",
/*f0*/ "ret p", "pop af", "jp p, a16", "di", "call p, a16", "push af", "or d8", "rst 6",
/*f8*/ "ret m", "ld sp, hl", "jp m, a16", "ei", "call m, a16", "*", "cp d8", "rst 7",
};
// base cycles. 8080 conditional calls take 11 (not 17) if not taken. conditional returns take 5 (not 11) if not taken.
typedef uint8_t acycles_t[ 256 ];
static const acycles_t i8080_cycles =
{
/*00*/ 4, 10, 7, 5, 5, 5, 7, 4, 4, 10, 7, 5, 5, 5, 7, 4,
/*10*/ 4, 10, 7, 5, 5, 5, 7, 4, 4, 10, 7, 5, 5, 5, 7, 4,
/*20*/ 4, 10, 16, 5, 5, 5, 7, 4, 4, 10, 16, 5, 5, 5, 7, 4,
/*30*/ 4, 10, 13, 5, 10, 10, 10, 4, 4, 10, 13, 5, 5, 5, 7, 4,
/*40*/ 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5,
/*50*/ 5, 5, 5, 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5,
/*60*/ 5, 5, 5, 5, 0, 5, 7, 5, 5, 5, 5, 5, 5, 5, 7, 5,
/*70*/ 7, 7, 7, 7, 7, 7, 7, 7, 5, 5, 5, 5, 5, 5, 7, 5,
/*80*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*90*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*a0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*b0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*c0*/ 11, 10, 10, 10, 17, 11, 7, 11, 11, 10, 10, 10, 17, 17, 7, 11,
/*d0*/ 11, 10, 10, 10, 17, 11, 7, 11, 11, 10, 10, 10, 17, 17, 7, 11,
/*e0*/ 11, 10, 10, 18, 17, 11, 7, 11, 11, 5, 10, 5, 17, 17, 7, 11,
/*f0*/ 11, 10, 10, 4, 17, 11, 7, 11, 11, 5, 10, 4, 17, 17, 7, 11,
};
static const acycles_t z80_cycles =
{
/*00*/ 4, 10, 7, 6, 4, 4, 7, 4, 4, 11, 7, 6, 4, 4, 7, 4,
/*10*/ 0, 10, 7, 6, 4, 4, 7, 4, 0, 11, 7, 6, 4, 4, 7, 4,
/*20*/ 0, 10, 16, 6, 4, 4, 7, 4, 0, 11, 20, 6, 4, 4, 7, 4,
/*30*/ 0, 10, 13, 6, 11, 11, 10, 4, 0, 11, 13, 6, 4, 4, 7, 4,
/*40*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*50*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*60*/ 4, 4, 4, 4, 0, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*70*/ 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
/*80*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*90*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*a0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*b0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
/*c0*/ 11, 10, 10, 10, 17, 11, 7, 11, 11, 10, 10, 0, 17, 17, 7, 11,
/*d0*/ 11, 10, 10, 11, 17, 11, 7, 11, 11, 0, 10, 11, 17, 0, 7, 11,
/*e0*/ 11, 10, 10, 19, 17, 11, 7, 11, 11, 4, 10, 4, 17, 0, 7, 11,
/*f0*/ 11, 10, 10, 4, 17, 11, 7, 11, 11, 5, 10, 4, 17, 0, 7, 11,
};
static uint16_t mword( uint16_t offset ) { return * ( (uint16_t *) & memory[ offset ] ); }
static void setmword( uint16_t offset, uint16_t value ) { * (uint16_t *) & memory[ offset ] = value; }
static uint8_t pcbyte() { return memory[ reg.pc++ ]; }
static uint16_t pcword() { uint16_t r = mword( reg.pc ); reg.pc += 2; return r; }
static void pushword( uint16_t val ) { reg.sp -= 2; setmword( reg.sp, val ); }
static uint16_t popword() { uint16_t val = mword( reg.sp ); reg.sp += 2; return val; }
bool is_parity_even( uint8_t x )
{
#if defined(_M_AMD64) && !defined(__GNUC__)
return ( ! ( __popcnt16( x ) & 1 ) ); // less portable, but faster
#else
return ( ! ( std::bitset<8>( x ).count() & 1 ) );
#endif
} //is_parity_even
void set_parity( uint8_t x ) { reg.fParityEven_Overflow = is_parity_even( x ); }
void set_sign_zero( uint8_t x )
{
reg.fSign = ( 0 != ( 0x80 & x ) );
reg.fZero = ( 0 == x );
} //set_sign_zero
void set_sign_zero_parity( uint8_t x )
{
set_sign_zero( x );
set_parity( x );
} //set_sign_zero_parity
void z80_set_sign_zero_16( uint16_t x )
{
reg.fSign = ( 0 != ( 0x8000 & x ) );
reg.fZero = ( 0 == x );
} //z80_set_sign_zero_16
uint8_t op_inc( uint8_t x )
{
x++;
reg.fAuxCarry = ( 0 == ( x & 0xf ) );
set_sign_zero( x );
if ( reg.fZ80Mode )
{
reg.fParityEven_Overflow = ( x == 0x80 );
reg.fWasSubtract = false;
reg.z80_assignYX( x );
}
else
set_parity( x );
return x;
} //op_inc
uint8_t op_dec( uint8_t x )
{
uint8_t result = x - 1;
set_sign_zero( result );
if ( reg.fZ80Mode )
{
reg.fParityEven_Overflow = ( x == 0x80 );
reg.fWasSubtract = true;
// Aux / Half carry returns the opposite value on Z80 as on 8080
reg.fAuxCarry = ( 0xf == ( result & 0xf ) );
reg.z80_assignYX( result );
}
else
{
set_parity( result );
reg.fAuxCarry = ( 0xf != ( result & 0xf ) );
}
return result;
} //op_dec
force_inlined void op_add( uint8_t x, bool carry = false )
{
uint16_t carry_int = carry ? 1 : 0;
uint16_t r16 = (uint16_t) reg.a + (uint16_t) x + carry_int;
uint8_t r8 = r16 & 0xff;
reg.fCarry = ( 0 != ( r16 & 0x0100 ) );
// low nibble add + carry overflows to high nibble
reg.fAuxCarry = ( 0 != ( ( ( 0xf & reg.a ) + ( 0xf & x ) + carry_int ) & 0x10 ) );
set_sign_zero( r8 );
// if not ( ( one of lhs and rhs are negative ) and ( one of lhs and result are negative ) )
if ( reg.fZ80Mode )
{
reg.fParityEven_Overflow = ( ! ( ( reg.a ^ x ) & 0x80 ) ) && ( ( reg.a ^ r8 ) & 0x80 );
reg.fWasSubtract = false;
reg.z80_assignYX( r8 );
}
else
set_parity( r8 );
reg.a = r8;
} //op_add
void op_adc( uint8_t x )
{
op_add( x, reg.fCarry );
} //op_adc
force_inlined uint8_t op_sub( uint8_t x, bool borrow = false )
{
// com == ones-complement
uint8_t com_x = ~x;
uint8_t borrow_int = borrow ? 0 : 1;
uint16_t res16 = (uint16_t) reg.a + (uint16_t) com_x + (uint16_t) borrow_int;
uint8_t res8 = res16 & 0xff;
reg.fCarry = ( 0 == ( res16 & 0x100 ) );
set_sign_zero( res8 );
reg.fAuxCarry = ( 0 != ( ( ( reg.a & 0xf ) + ( com_x & 0xf ) + borrow_int ) & 0x10 ) );
if ( reg.fZ80Mode )
{
// if not ( ( one of lhs and com_x are negative ) and ( one of lhs and result are negative ) )
reg.fParityEven_Overflow = ! ( ( reg.a ^ com_x ) & 0x80 ) && ( ( reg.a ^ res8 ) & 0x80 );
reg.fWasSubtract = true;
reg.fAuxCarry = !reg.fAuxCarry; // opposite meaning on z80 for subtract
reg.z80_assignYX( res8 );
}
else
set_parity( res8 );
// op_sub is the only op_X that doesn't update reg.a because it's also used for op_cmp
return res8;
} //op_sub
force_inlined void op_sbb( uint8_t x )
{
reg.a = op_sub( x, reg.fCarry );
} //op_sbb
force_inlined void op_cmp( uint8_t x )
{
op_sub( x, false );
if ( reg.fZ80Mode )
reg.z80_assignYX( x ); // done on operand, not the result or reg.a
} //op_cmp
void op_ana( uint8_t x )
{
reg.fAuxCarry = ( 0 != ( 0x8 & ( reg.a | x ) ) ); // documented for 8080, not true for 8085
reg.fCarry = false;
reg.a &= x;
set_sign_zero_parity( reg.a );
if ( reg.fZ80Mode )
{
reg.fWasSubtract = false;
reg.fAuxCarry = true;
reg.z80_assignYX( reg.a );
}
} //op_ana
void op_ora( uint8_t x )
{
reg.a |= x;
reg.fAuxCarry = false;
reg.fCarry = false;
set_sign_zero_parity( reg.a );
if ( reg.fZ80Mode )
{
reg.fWasSubtract = false;
reg.z80_assignYX( reg.a );
}
} //op_ora
void op_xra( uint8_t x )
{
reg.a ^= x;
reg.fAuxCarry = false;
reg.fCarry = false;
set_sign_zero_parity( reg.a );
if ( reg.fZ80Mode )
{
reg.fWasSubtract = false;
reg.z80_assignYX( reg.a );
}
} //op_xra
void op_math( uint8_t opcode, uint8_t src )
{
uint8_t math = ( opcode >> 3 ) & 7;
assert( math <= 7 );
if ( 7 == math ) op_cmp( src ); // in order of usage for performance
else if ( 6 == math ) op_ora( src );
else if ( 4 == math ) op_ana( src );
else if ( 5 == math ) op_xra( src );
else if ( 0 == math ) op_add( src );
else if ( 2 == math ) reg.a = op_sub( src ); // sub doesn't update reg.a
else if ( 1 == math ) op_adc( src );
else op_sbb( src ); // 3
} //op_math
void op_dad( uint16_t x )
{
// add x to H and set Carry if warranted
uint32_t result = (uint32_t) reg.H() + (uint32_t) x;
reg.fCarry = ( 0 != ( 0x10000 & result ) );
if ( reg.fZ80Mode )
{
uint32_t auxResult = ( reg.H() & 0xfff ) + ( x & 0xfff );
reg.fAuxCarry = ( 0 != ( auxResult & 0xf000 ) );
reg.fWasSubtract = false;
reg.z80_assignYX( (uint8_t) ( result >> 8 ) );
}
reg.SetH( (uint16_t) ( result & 0xffff ) );
} //op_dad
void op_cma()
{
reg.a = ~reg.a;
if ( reg.fZ80Mode )
{
reg.fAuxCarry = true;
reg.fWasSubtract = true;
reg.z80_assignYX( reg.a );
}
} //op_cma
void op_cmc()
{
reg.fCarry = !reg.fCarry;
if ( reg.fZ80Mode )
{
reg.fWasSubtract = false;
reg.fAuxCarry = !reg.fCarry; // some docs say !reg.fAuxCarry
reg.z80_assignYX( reg.a );
}
} //op_cmc
not_inlined void op_daa()
{
if ( reg.fZ80Mode ) // this BCD add logic pulled from Sean Young's doc
{
uint8_t diff = 0x66;
uint8_t hn = ( ( reg.a >> 4 ) & 0xf );
uint8_t ln = ( reg.a & 0xf );
if ( reg.fCarry )
{
if ( !reg.fAuxCarry && ln <= 9 )
diff = 0x60;
}
else
{
if ( hn <= 9 && !reg.fAuxCarry && ln <= 9 )
diff = 0;
else if ( ( hn <= 9 && reg.fAuxCarry && ln <= 9 ) || ( hn <= 8 && ln > 9 ) )
diff = 6;
else if ( hn > 9 && !reg.fAuxCarry && ln <= 9 )
diff = 0x60;
}
bool newCarry = reg.fCarry;
if ( !reg.fCarry )
{
if ( ( hn <= 9 && ln <= 9 ) || ( hn <= 8 && ln > 9 ) )
newCarry = false;
else if ( ( hn >= 9 && ln > 9 ) || ( hn > 9 && ln <= 9 ) )
newCarry = true;
}
bool newAuxCarry = reg.fAuxCarry;
if ( reg.fWasSubtract )
{
if ( !reg.fAuxCarry )
newAuxCarry = false;
else
newAuxCarry = ( ln < 6 );
}
else
newAuxCarry = ( ln > 9 );
if ( reg.fWasSubtract )
reg.a -= diff;
else
reg.a += diff;
set_sign_zero_parity( reg.a );
reg.z80_assignYX( reg.a );
reg.fCarry = newCarry;
reg.fAuxCarry = newAuxCarry;
}
else
{
uint8_t loNibble = reg.a & 0xf;
uint8_t toadd = 0;
if ( reg.fAuxCarry || ( loNibble > 9 ) )
toadd = 6;
bool carry = reg.fCarry;
uint8_t hiNibble = reg.a & 0xf0;
if ( ( hiNibble > 0x90 ) || ( hiNibble >= 0x90 && loNibble > 0x9 ) || carry )
{
toadd |= 0x60;
carry = true;
}
op_add( toadd );
reg.fCarry = carry; // this doesn't change regardless of the result
}
} //op_daa
uint8_t * dst_address_rm( uint8_t rm )
{
assert( rm <= 7 );
if ( 6 != rm )
return reg.regOffset( rm );
return & memory[ reg.H() ];
} //dst_address_rm
uint8_t * dst_address( uint8_t op )
{
uint8_t rm = 7 & ( op >> 3 );
return dst_address_rm( rm );
} //dst_address
uint8_t src_value_rm( uint8_t rm )
{
if ( 6 != rm )
return * ( reg.regOffset( rm ) );
return memory[ reg.H() ];
} //src_value_rm
uint8_t src_value( uint8_t op )
{
uint8_t rm = 0x7 & op;
return src_value_rm( rm );
} //src_value
void z80_ni( uint8_t op, uint8_t op2 )
{
x80_hard_exit( "bugbug: not-implemented z80 instruction: %#x, next byte is %#x\n", op, op2 );
} //z80_ni
void z80_op_bit( uint8_t val, uint8_t bit, z80_value_source vs )
{
assert( bit <= 7 );
reg.fAuxCarry = true; // per doc
reg.fWasSubtract = false;
reg.fSign = ( ( 7 == bit ) && ( 0 != ( 0x80 & val ) ) ); // Zilog doc says fSign is "unknown", but hardware does this
uint8_t cmp = ( 1 << bit );
reg.fZero = ( 0 == ( val & cmp ) );
reg.fParityEven_Overflow = reg.fZero; // non-documented
// Y and X are set from the source value, not as 4.1 from "The Undocumented Z80 Documented"
// has from the value resulting from the bit operation. But only if the source is a register.
if ( vs_register == vs )
reg.z80_assignYX( val );
} //z80_op_bit
void z80_op_rlc( uint8_t * pval )
{
// rotate left carry. 7 bit to both C and 0 bit. flags: S, Z, H reset, Parity, N reset, and C
uint8_t x = *pval;
bool bit7 = ( 0 != ( x & 0x80 ) );
x <<= 1;
reg.fCarry = bit7;
if ( bit7 )
x |= 1;
set_sign_zero_parity( x );
reg.fAuxCarry = false;
reg.fWasSubtract = false;
reg.z80_assignYX( x );
*pval = x;
} //z80_op_rlc
void z80_op_rl( uint8_t * pval )
{
// rotate left. 7 bit to C. Old carry bit to 0. flags: S, Z, H reset, Parity, N reset, and C
uint8_t x = *pval;
bool bit7 = ( 0 != ( x & 0x80 ) );
x <<= 1;
if ( reg.fCarry )
x |= 1;
reg.fCarry = bit7;
set_sign_zero_parity( x );
reg.fAuxCarry = false;
reg.fWasSubtract = false;
reg.z80_assignYX( x );
*pval = x;
} //z80_op_rl
void z80_op_rrc( uint8_t * pval )
{
// rotate right carry. 0 bit to both C and 7 bit. flags: S, Z, H reset, Parity, N reset, and C
uint8_t x = *pval;
bool bit0 = ( 0 != ( x & 1 ) );
x >>= 1;
reg.fCarry = bit0;
if ( bit0 )
x |= 0x80;
set_sign_zero_parity( x );
reg.fAuxCarry = false;
reg.fWasSubtract = false;
reg.z80_assignYX( x );
*pval = x;
} //z80_op_rrc
void z80_op_rr( uint8_t * pval )
{
// rotate right. 0 bit to C. Old C to 7 bit. flags: S, Z, H reset, Parity, N reset, and C
uint8_t x = *pval;
bool bit0 = ( 0 != ( x & 1 ) );
x >>= 1;
if ( reg.fCarry )
x |= 0x80;
reg.fCarry = bit0;
set_sign_zero_parity( x );
reg.fAuxCarry = false;
reg.fWasSubtract = false;
reg.z80_assignYX( x );
*pval = x;
} //z80_op_rr
uint16_t z80_op_sub_16( uint16_t lhs, uint16_t rhs, bool borrow = false )
{
// com == ones-complement
uint16_t com_rhs = ~rhs;
uint16_t borrow_int = borrow ? 0 : 1;
uint32_t res32 = (uint32_t) lhs + (uint32_t) com_rhs + (uint32_t) borrow_int;
uint16_t res16 = res32 & 0xffff;
reg.fCarry = ( 0 == ( res32 & 0x10000 ) );
z80_set_sign_zero_16( res16 );
// if not ( ( one of lhs and com_rhs are negative ) and ( one of lhs and result are negative ) )
reg.fParityEven_Overflow = ! ( ( lhs ^ com_rhs ) & 0x8000 ) && ( ( lhs ^ res16 ) & 0x8000 );
reg.fWasSubtract = true;
if ( borrow )
rhs++;
reg.fAuxCarry = ( ( rhs & 0xfff ) > ( lhs & 0xfff ) );
reg.z80_assignYX( res16 >> 8 );
return res16;
} //z80_op_sub_16
uint16_t z80_op_add_16( uint16_t a, uint16_t b )
{
uint32_t resultAux = ( (uint32_t) ( a & 0xfff ) + (uint32_t) ( b & 0xfff ) );
reg.fAuxCarry = ( 0 != ( resultAux & 0xfffff000 ) );
reg.fWasSubtract = false;
uint32_t result = ( (uint32_t) a + (uint32_t) b );
reg.fCarry = ( 0 != ( result & 0x10000 ) );
reg.z80_assignYX( (uint8_t) ( result >> 8 ) );
return (uint16_t) result;
} //z80_op_add_16
uint16_t z80_op_adc_16( uint16_t l, uint16_t r )
{
uint16_t carryOut, result, resultAux;
if ( reg.fCarry )
{
carryOut = ( l >= ( 0xffff - r ) );
result = r + l + 1;
resultAux = ( 0xfff & r ) + ( 0xfff & l ) + 1;
}
else
{
carryOut = ( l > ( 0xffff - r ) );
result = r + l;
resultAux = ( 0xfff & r ) + ( 0xfff & l );
}
reg.z80_assignYX( result >> 8 );
reg.fAuxCarry = ( 0 != ( 0xf000 & resultAux ) );
uint16_t carryIns = result ^ l ^ r;
z80_set_sign_zero_16( result );
reg.fParityEven_Overflow = ( carryIns >> 15 ) ^ carryOut;
reg.fCarry = ( 0 != carryOut );
reg.fWasSubtract = false;
return result;
} //z80_op_adc_16
void z80_op_sla( uint8_t * pval )
{
uint8_t val = *pval;
reg.fCarry = ( 0 != ( val & 0x80 ) );
val <<= 1;
set_sign_zero_parity( val );
reg.clearHN();
reg.z80_assignYX( val );
*pval = val;
} //z80_op_sla
void z80_op_sll( uint8_t * pval ) // not a documented opcode
{
uint8_t val = *pval;
reg.fCarry = ( 0 != ( val & 0x80 ) );
val <<= 1;
val |= 1;
set_sign_zero_parity( val );
reg.clearHN();
reg.z80_assignYX( val );
*pval = val;
} //z80_op_sll
void z80_op_sra( uint8_t * pval )
{
uint8_t val = *pval;
reg.fCarry = ( 0 != ( val & 1 ) );
val >>= 1;
val |= ( ( *pval ) & 0x80 ); // leave high bit unchanged
set_sign_zero_parity( val );
reg.clearHN();
reg.z80_assignYX( val );
*pval = val;
} //z80_op_sra
void z80_op_srl( uint8_t * pval )
{
uint8_t val = *pval;
reg.fCarry = ( val & 1 );
val >>= 1;
set_sign_zero_parity( val );
reg.clearHN();
reg.z80_assignYX( val );
*pval = val;
} //z80_op_srl
uint16_t z80_emulate( uint8_t op ) // this is just for instructions that aren't shared with 8080
{
uint16_t opaddress = reg.pc - 1;
uint8_t op2 = memory[ reg.pc ];
uint8_t op3 = memory[ reg.pc + 1 ];
uint8_t op4 = memory[ reg.pc + 2 ];
int op3int = (int) (int8_t) op3;
uint16_t cycles = 4; // general-purpose default
switch ( op )
{
case 0x08: // ex af and af'
{
swap( reg.a, reg.ap );
reg.materializeFlags();
swap( reg.f, reg.fp );
reg.unmaterializeFlags();
break;
}
case 0x10: // djnz
{
uint8_t offset = pcbyte();
reg.b = reg.b - 1;
if ( 0 != reg.b )
{
reg.pc = opaddress + 2 + (int16_t) (int8_t) offset;
cycles = 13;
}
else
cycles = 8;
break;
}
case 0x18: // jr n
{
uint8_t offset = pcbyte();
reg.pc = opaddress + 2 + (int16_t) (int8_t) offset;
cycles = 12;
break;
}
case 0x20: // jr nz, n
{
uint8_t offset = pcbyte();
if ( !reg.fZero )
{
reg.pc = opaddress + 2 + (int16_t) (int8_t) offset;
cycles = 12;
}
else
cycles = 7;
break;
}
case 0x28: // jr z, n
{
uint8_t offset = pcbyte();
if ( reg.fZero )
{
reg.pc = opaddress + 2 + (int16_t) (int8_t) offset;
cycles = 12;
}
else
cycles = 7;
break;
}
case 0x30: // jr nc, n
{
uint8_t offset = pcbyte();
if ( !reg.fCarry )
{
reg.pc = opaddress + 2 + (int16_t) (int8_t) offset;
cycles = 12;
}
else
cycles = 7;
break;
}
case 0x38: // jr c, n
{
uint8_t offset = pcbyte();
if ( reg.fCarry )
{
reg.pc = opaddress + 2 + (int16_t) (int8_t) offset;
cycles = 12;
}
else
cycles = 7;
break;
}
case 0xcb: // rotate / bits
{
pcbyte(); // get past op2
if ( 0x20 == ( op2 & 0xf8 ) ) // sla
{
cycles = 8;
uint8_t rm = op2 & 0x7;
if ( 6 == rm )
cycles += 2;
uint8_t * pdst = dst_address_rm( rm );
z80_op_sla( pdst );
}
else if ( 0x28 == ( op2 & 0xf8 ) ) // sra
{
cycles = 8;
uint8_t rm = op2 & 0x7;
if ( 6 == rm )
cycles += 2;
uint8_t * pdst = dst_address_rm( rm );
z80_op_sra( pdst );
}
else if ( op2 >= 0x30 && op2 <= 0x3f )
{
uint8_t rm = op2 & 0x7;
uint8_t * pdst = dst_address_rm( rm );
if ( op2 <= 0x37 )
z80_op_sll( pdst );
else
z80_op_srl( pdst );
}
else if ( 0x38 == ( op2 & 0xf8 ) ) // srl r = shift right logical
{
cycles = 8;
uint8_t rm = op2 >> 4;
if ( 6 == rm )
cycles += 2;
uint8_t * pdst = dst_address_rm( rm );
z80_op_srl( pdst );
}
else if ( op2 >= 0x40 && op2 <= 0x7f ) // bit #, rm
{
cycles = 8;
uint8_t rm = op2 & 0x7;
if ( 6 == rm )
cycles += 4;
uint8_t bit = ( op2 >> 3 ) & 0x7;
uint8_t val = src_value_rm( rm );
z80_op_bit( val, bit, ( 6 == rm ) ? vs_memory : vs_register );
}
else if ( op2 >= 0x80 && op2 <= 0xbf ) // res bit #, rm AKA reset
{
cycles = 8;
uint8_t rm = op2 & 0x7;
if ( 6 == rm )
cycles += 7;
uint8_t bit = ( op2 >> 3 ) & 0x7;
uint8_t val = src_value_rm( rm );
uint8_t mask = ~ ( 1 << bit );
val &= mask;
* dst_address_rm( rm ) = val;
}
else if ( op2 >= 0xc0 && op2 <= 0xff ) // set bit #, rm
{
cycles = 8;
uint8_t rm = op2 & 0x7;
if ( 6 == rm )
cycles += 7;
uint8_t bit = ( op2 >> 3 ) & 0x7;
uint8_t val = src_value_rm( rm );
uint8_t mask = 1 << bit;
val |= mask;
* dst_address_rm( rm ) = val;
}
else if ( op2 <= 0x1f ) // rlc, rrc, rl, rr on rm
{
cycles = 8;
uint8_t mod = op2;
uint8_t rot = ( mod >> 3 ) & 0x3;
uint8_t rm = mod & 0x7;
if ( 6 == rm )
cycles += 2;
uint8_t * pval = dst_address_rm( rm );
if ( 0 == rot )
z80_op_rlc( pval );
else if ( 1 == rot )
z80_op_rrc( pval );
else if ( 2 == rot )
z80_op_rl( pval );
else // if ( 3 == rot )
z80_op_rr( pval );
}
else
z80_ni( op, op2 );
break;
}
case 0xd9: // exx B, D, H with B', D', H'
{
swap( reg.b, reg.bp );
swap( reg.c, reg.cp );
swap( reg.d, reg.dp );
swap( reg.e, reg.ep );
swap( reg.h, reg.hp );
swap( reg.l, reg.lp );
break;
}
case 0xdd: case 0xfd: // ix & iy operations
{
reg.r++;
pcbyte(); // consume op2: the dd or fd
if ( 0x21 == op2 ) // ld ix/iy word
* reg.z80_indexAddress( op ) = pcword();
else if ( 0x22 == op2 ) // ld (address), ix/iy
{
cycles = 20;
uint16_t address = pcword();
setmword( address, reg.z80_getIndex( op ) );
}
else if ( 0x23 == op2 ) // inc ix/iy
{
cycles = 10;
* reg.z80_indexAddress( op ) = reg.z80_getIndex( op ) + 1; // no flags are affected
}
else if ( 0x26 == op2 ) // ld ix/iy h. not documented
* reg.z80_getIndexByteAddress( op, 0 ) = pcbyte();
else if ( 0x2a == op2 ) // ld ix, (address)
{
cycles = 20;
uint16_t address = pcword();
reg.z80_setIndex( op, mword( address ) );
}
else if ( 0x2b == op2 ) // dec ix/iy
{
cycles = 10;
* reg.z80_indexAddress( op ) = reg.z80_getIndex( op ) - 1; // no flags are affected
}
else if ( 0x2e == op2 ) // ld ix/iy l. not documented
{
cycles = 20; // guess
* reg.z80_getIndexByteAddress( op, 1 ) = pcbyte();
}
else if ( 0x34 == op2 ) // inc (i + index)
{
cycles = 23;
uint16_t i = reg.z80_getIndex( op ) + (int16_t) (int8_t) pcbyte();
uint8_t x = memory[ i ];
memory[i] = op_inc( x );
}
else if ( 0x35 == op2 ) // dec (i + index)
{
cycles = 23;
uint16_t i = reg.z80_getIndex( op ) + (int16_t) (int8_t) pcbyte();
uint8_t x = memory[ i ];
memory[ i ] = op_dec( x );
}
else if ( 0x36 == op2 ) // ld (ix/iy + index), immediate byte
{
cycles = 19;
uint16_t i = reg.z80_getIndex( op ) + (int16_t) (int8_t) pcbyte();
uint8_t val = pcbyte();
memory[ i ] = val;
}
else if ( ( ( op2 >= 0x40 && op2 <= 0x6f ) || ( op2 >= 0x78 && op2 <= 0x7f ) ) && // ld [bcdeIhIla][bcdeIhIla]
( ( ( op2 & 0xf ) != 6 ) && ( ( op2 & 0xf ) != 0xe ) ) )
{
uint8_t fromval = op2 & 0xf;
if ( fromval >= 8 )
fromval -= 8;
uint8_t tmp = ( 0 == fromval ) ? reg.b :
( 1 == fromval ) ? reg.c :
( 2 == fromval ) ? reg.d :
( 3 == fromval ) ? reg.e :
( 4 == fromval ) ? reg.z80_getIndexByte( op, 0 ) :
( 5 == fromval ) ? reg.z80_getIndexByte( op, 1 ) :
reg.a;
if ( op2 <= 0x47 )
reg.b = tmp;
else if ( op2 <= 0x4f )
reg.c = tmp;
else if ( op2 <= 0x57 )
reg.d = tmp;
else if ( op2 <= 0x5f )
reg.e = tmp;
else if ( op2 <= 0x67 )
*reg.z80_getIndexByteAddress( op, 0 ) = tmp;
else if ( op2 <= 0x6f )
*reg.z80_getIndexByteAddress( op, 1 ) = tmp;
else
reg.a = tmp;
}
else if ( 0x46 == ( op2 & 0x47 ) ) // ld r, (i + #)
{
cycles = 19;
pcbyte(); // consume op3
uint16_t address = reg.z80_getIndex( op ) + (uint16_t) op3int;
* dst_address( op2 ) = memory[ address ];
}
else if ( 0x70 == ( op2 & 0xf8 ) ) // ld (i+#), r/#
{
cycles = 19;
pcbyte(); // consume op3