-
Notifications
You must be signed in to change notification settings - Fork 10
/
hw_pcie_constants.h
executable file
·157 lines (135 loc) · 6.52 KB
/
hw_pcie_constants.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
/*
* Copyright (c) 2014, Altera Corporation.
* All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* BSD 3-Clause license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* - Neither Altera nor the names of its contributors may be
* used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
////////////////////////////////////////////////////////////
// //
// hw_pcie_constants.h //
// Constants to keep in sync with the HW board design //
// //
// Note: This file *MUST* be kept in sync with any //
// changes to the HW board design! //
// //
////////////////////////////////////////////////////////////
#ifndef HW_PCIE_CONSTANTS_H
#define HW_PCIE_CONSTANTS_H
#define ACL_PCIE_READ_BIT( w, b ) (((w) >> (b)) & 1)
#define ACL_PCIE_READ_BIT_RANGE( w, h, l ) (((w) >> (l)) & ((1 << ((h) - (l) + 1)) - 1))
#define ACL_PCIE_SET_BIT( w, b ) ((w) |= (1 << (b)))
#define ACL_PCIE_CLEAR_BIT( w, b ) ((w) &= (~(1 << (b))))
#define ACL_PCIE_GET_BIT( b ) (unsigned) (1 << (b))
#define QSYS_IFACE 1
// Number of Base Address Registers in the PCIe core
#define ACL_PCI_NUM_BARS 4
// PCI Vendor and Device IDs
#define ACL_PCI_ALTERA_VENDOR_ID 0x1172
#define ACL_PCI_BSP_DEVICE_ID 0xAB00
#define ACL_PCI_SUBSYSTEM_VENDOR_ID 0x1172
#define ACL_PCI_SUBSYSTEM_DEVICE_ID 0x0004
#define ACL_BOARD_PKG_NAME "de5net"
#define ACL_VENDOR_NAME "Terasic Corporation"
#define ACL_BOARD_NAME "Terasic's Preferred Board"
// Global memory
#define ACL_PCI_GLOBAL_MEM_BAR 0
// PCIe control register addresses
#define ACL_PCI_CRA_BAR 0
#define ACL_PCI_CRA_OFFSET 0
#define ACL_PCI_CRA_SIZE 0x4000
// Kernel control/status register addresses
#define ACL_KERNEL_CSR_BAR 0
#define ACL_KERNEL_CSR_OFFSET 0x4000
// DMA control/status register address
#define ACL_PCIE_DMA_BAR 0
#define ACL_PCIE_DMA_OFFSET 0x0c800
// DMA descriptor slave address
#define ACL_PCIE_DMA_DESCRIPTOR_BAR 0
#define ACL_PCIE_DMA_DESCRIPTOR_OFFSET 0x0c820
// Avalon Tx port address as seen by the DMA read/write masters
#define ACL_PCIE_TX_PORT 0x200000000ll
// Global memory window slave address. The host has different "view" of global
// memory: it sees only 512megs segments of memory at a time for non-DMA xfers
#define ACL_PCIE_MEMWINDOW_BAR 0
#define ACL_PCIE_MEMWINDOW_CRA 0x0c870
#define ACL_PCIE_MEMWINDOW_BASE 0x10000
#define ACL_PCIE_MEMWINDOW_SIZE 0x10000
// PCI express control-register offsets
#define PCIE_CRA_IRQ_STATUS 0x0040
#define PCIE_CRA_IRQ_ENABLE 0x0050
#define PCIE_CRA_ADDR_TRANS 0x1000
// IRQ vector mappings (as seen by the PCIe RxIRQ port)
#define ACL_PCIE_KERNEL_IRQ_VEC 0
#define ACL_PCIE_DMA_IRQ_VEC 1
// PLL related
#define USE_KERNELPLL_RECONFIG 1
#define ACL_PCIE_KERNELPLL_RECONFIG_BAR 0
#define ACL_PCIE_KERNELPLL_RECONFIG_OFFSET 0x0c000
#ifndef QSYS_IFACE
// PCI express IRQ register bits
#define PCIE_CRA_IRQ_RXMIRQ 7
#define PCIE_CRA_AVL_IRQ_VEC_LO 8
#define PCIE_CRA_AVL_IRQ_VEC_HI 13
#endif
// DMA descriptor control bits
#define DMA_ALIGNMENT_BYTES 64
#define DMA_ALIGNMENT_BYTE_MASK (DMA_ALIGNMENT_BYTES-1)
#define DMA_DC_TRANSFER_COMPLETE_IRQ_MASK 14
#define DMA_DC_EARLY_DONE_ENABLE 24
#define DMA_DC_GO 31
// DMA controller control/status registers
#define DMA_CSR_STATUS 0x00
#define DMA_CSR_CONTROL 0x04
// DMA CSR status bits
#define DMA_STATUS_BUSY 0
#define DMA_STATUS_DESCRIPTOR_EMPTY 1
#define DMA_STATUS_RESETTING 6
#define DMA_STATUS_IRQ 9
#define DMA_STATUS_COUNT_LO 16
#define DMA_STATUS_COUNT_HI 31
// DMA CSR control bits
#define DMA_CTRL_STOP 0
#define DMA_CTRL_RESET 1
#define DMA_CTRL_IRQ_ENABLE 4
#define PIO_DATA 0*4
#define PIO_SET 4*4
#define PIO_CLR 5*4
// Temperature sensor presence and base address macros
#define ACL_PCIE_HAS_TEMP_SENSOR 1
#define ACL_PCIE_TEMP_SENSOR_ADDRESS 0xcff0
#define ACL_VERSIONID_BAR 0
#define ACL_VERSIONID_OFFSET 0xcfc0
#define ACL_VERSIONID 0xA0C7C1E0
#define ACL_UNIPHYSTATUS_BAR 0
#define ACL_UNIPHYSTATUS_OFFSET 0xcfe0
#endif // HW_PCIE_CONSTANTS_H