Skip to content

Latest commit

 

History

History
144 lines (117 loc) · 7.57 KB

CHANGELOG.md

File metadata and controls

144 lines (117 loc) · 7.57 KB
Raw

Changelog

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

Note that the Python ecosystem itself doesn't really adhere to Semantic Versioning. Dependency updates are automatically managed with Renovate Bot on Sentinel's two branches to detect dependency breakage that warrants a new release/yank.

The Sentinel repository has two active branches: main and next. Releases and patches live on main, and development takes place on next. next is developed against the upstream/git versions of Amaranth and associated packages. These include, but are not limited to:

If necessary, patches from main can be forward-ported to next, and commits from next and be backported to main for a point-release. When possible, releases are made against Amaranth packages on PyPI, even though development is done against the Amaranth git repos.

Unreleased

0.1.0-alpha.1 - 2024-03-12

First release after the next/main split.

Added

  • Test gateware generation in CI.
  • Updates available for dependencies are tracked with Renovate Bot.
    • Applies to both main and next.
  • The yosys version for Verilog/RTLIL/gateware generation is also tracked in CI using a new workflow.
  • Demo SoC example can optionally use peripherals whose registers are implemented using the amaranth-soc CSR bus.
    • Only fits on HX8K Evaluation board at present.
    • Peripherals are at different addresses when using the CSR bus; the Rust firmware can detect which version of the gateware is loaded by querying the MIP register after reset.
  • Demo prints addresses of peripherals in table format.
  • Rust Demo SoC can be simulated as part of Pytest tests.
    • Disabled by default, pass --runsoc to pytest to enabled.
  • Implement remote Demo SoC builds using paramiko.
  • Add usage as a Python dependency in README.md.

Changed

  • Replace ELF generator with pyelftools.
    • This simplifies the inline objcopy implementation.
  • GPIO peripheral in SoC demo has input, output, and output-enable ports now.
  • Use a dynamic Python version (no releases ever saw the manual behavior).
  • dodo.py dependency graph has been cleaned up a bit.
  • Start improving Signatures used throughout Sentinel core.
    • Mostly limited to Decoder, ExceptionRouter, and ALU for now.
    • Many signals remain to be wired up to formal harness via Signatures, rather that the formal harness reaching into Sentinel.
  • Python, Rust, and CI dependencies have been updated to most recent versions.
  • Rust firmware development DoIt tasks are no longer targeted to IceStick only.
    • HX8K development board support is up to parity with IceStick.

Fixed

  • All Amaranth deprecations for the upcoming version 0.5 have been addressed, up to commit 715a8d4.
  • Correct gen usage outside pdm in README.md.
  • dodo.py no longer errors when removing directory trees that don't exist.
    • Removing dirs is required as part of RISCOF test cleanup.
  • Load-bearing optimization implemented in 39005c1 that saves ~30 LUTs in SoC demo.
    • Check to see if this can be removed/is no longer necessary.

v0.1.0-alpha - 2023-11-29

Initial release. This is a retroactive release, created just before the next/main split.

PDM should be used for interacting with this repo; type pdm run --list for a list of commands. pdm will defer to DoIt for complex tasks such as orchestrating RISC-V Formal.

Pytest is used for basic testing, and Flake8 is used for linting. Due to code cleanups required, as well as some tooling still being in flux, no documentation beyond the CHANGELOG.md and README.md is provided yet.

Due to git dependencies, this release is only usable within the pdm environment. Specifically, the SoC example, tests, and Verilog generation works, but using Sentinel as a dependency of another Python/Amaranth/pdm project does not work.

Added

  • Working SoC example for Lattice IceStick and iCE40-HX8K Breakout Board.

    • Includes custom Amaranth peripherals and a contrived Rust firmware.

      Run using pdm demo (Assembly firmware) or pdm demo-rust (Rust firmware).

    • Demo is using special options to yosys to make Sentinel fit onto IceStick.

    • Microcode written using the m5meta microcode assembler, version 1.x.

      • An upcoming version 2.x of m5meta is expected in the moderate-near future. I plan to rewrite the microcode then, and the rewrite will not be compatible with version 1.x.
  • Working RISC-V soft-core implementing the RV32I_Zcsr specification.
    • Core passes the RISC-V Formal verification tests, as well as the tests used by RISC-V International as part of the RISCOF framework.
  • Bespoke test suite with my own custom tests and pytest fixtures for simulating Sentinel with Amaranth's Python simulator.
    • Many of the pytest test come from an older test suite no-longer used by RISC-V International. I feel they are fine as a first layer of tests to detect immediate breakage of Sentinel.
  • CI using Github Actions tests using pytest, RISC-V Formal, RISCOF, and demo synthesis every push and PR.
    • The demo test is allowed to fail due to lack of space on Icestick due to different compilers optimizing yosys slightly differently. See #2.
  • A nice logo by Tokino Kei :).