From 3b1f6c14d6096b3e41ff68781eafac9a30bc6abc Mon Sep 17 00:00:00 2001 From: gabrielbrunheira Date: Wed, 18 Jan 2023 14:56:33 -0300 Subject: [PATCH 1/3] Included SWLS resonant converter spec, fixed IIB interlocks and alarms from FAC_DCDC_EMA --- CHANGES.md | 10 +++++++ src/pydrs/__init__.py | 4 +-- src/pydrs/base.py | 25 ++++++++++++++++-- src/pydrs/consts/__init__.py | 51 +----------------------------------- src/pydrs/consts/common.py | 2 +- src/pydrs/consts/fac.py | 4 +-- src/pydrs/consts/resonant.py | 17 ++++++++++++ 7 files changed, 56 insertions(+), 57 deletions(-) create mode 100644 src/pydrs/consts/resonant.py diff --git a/CHANGES.md b/CHANGES.md index 30dcee6..5875196 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -1,5 +1,15 @@ # Changelog +## [2.1.0] - 2022-01-18 +### Added: +- SWLS resonant converter PS module specification + +### Changed: +- Fixed variable type for IIB interlock and alarm registers from FAC-DCDC-EMA PS module + +### Removed: +- Obsolete ListVar list from consts + ## [1.2.5] - 2022-08-15 ### Added: - `read_csv_dsp_modules_bank` diff --git a/src/pydrs/__init__.py b/src/pydrs/__init__.py index fcd8990..8daa052 100644 --- a/src/pydrs/__init__.py +++ b/src/pydrs/__init__.py @@ -1,4 +1,4 @@ from .pydrs import EthDRS, GenericDRS, SerialDRS # noqa: F401 -__version__ = "2.0.1" -__date__ = "21/11/2022" +__version__ = "2.1.0" +__date__ = "18/01/2023" diff --git a/src/pydrs/base.py b/src/pydrs/base.py index 7cf9fe6..175adec 100644 --- a/src/pydrs/base.py +++ b/src/pydrs/base.py @@ -26,6 +26,7 @@ fac, fap, fbp, + resonant, num_blocks_curves_fax, num_blocks_curves_fbp, num_coeffs_dsp_modules, @@ -1688,8 +1689,12 @@ def read_vars_common(self, vals: bytes = None) -> dict: vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "V" vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "V" else: - vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "%" - vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "%" + if (vars_dict["status"]["model"] == "RESONANT_SWLS"): + vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "Hz" + vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "Hz" + else: + vars_dict["ps_setpoint"] = vars_dict["ps_setpoint"][:-1] + "%" + vars_dict["ps_reference"] = vars_dict["ps_reference"][:-1] + "%" vars_dict["siggen_type"] = common.sig_gen_types[int(vars_dict["siggen_type"])] vars_dict["wfmref_sync_mode"] = common.wfmref_sync_modes[ @@ -2193,6 +2198,22 @@ def read_vars_fac_2p_dcdc_imas(self, com_add=1) -> dict: fac.list_2p_dcdc_imas_hard_interlocks, ) + def read_vars_swls_resonant_converter(self) -> dict: + """ + Reads SWLS resonant converter power supply variables + + + Returns + ------- + dict + Dictionary with power supply variables + """ + return self._read_vars_generic( + resonant.bsmp, + resonant.list_soft_interlocks, + resonant.list_hard_interlocks, + ) + def check_param_bank(self, param_file: str): ps_param_list = [] diff --git a/src/pydrs/consts/__init__.py b/src/pydrs/consts/__init__.py index 0f48291..15017fe 100644 --- a/src/pydrs/consts/__init__.py +++ b/src/pydrs/consts/__init__.py @@ -22,7 +22,7 @@ COM_REQUEST_CURVE = "\x40" COM_SEND_WFM_REF = "\x41" -UDC_FIRMWARE_VERSION = "0.44 2022-06-30" +UDC_FIRMWARE_VERSION = "0.44.01 08/22" ufm_offset = { "serial": 0, @@ -53,55 +53,6 @@ num_blocks_curves_fax = [16, 16, 16] size_curve_block = [1024, 1024, 1024] -ListVar = [ - "iLoad1", - "iLoad2", - "iMod1", - "iMod2", - "iMod3", - "iMod4", - "vLoad", - "vDCMod1", - "vDCMod2", - "vDCMod3", - "vDCMod4", - "vOutMod1", - "vOutMod2", - "vOutMod3", - "vOutMod4", - "temp1", - "temp2", - "temp3", - "temp4", - "ps_OnOff", - "ps_OpMode", - "ps_Remote", - "ps_OpenLoop", - "ps_SoftInterlocks", - "ps_HardInterlocks", - "iRef", - "wfmRef_Gain", - "wfmRef_Offset", - "sigGen_Enable", - "sigGen_Type", - "sigGen_Ncycles", - "sigGenPhaseStart", - "sigGen_PhaseEnd", - "sigGen_Freq", - "sigGen_Amplitude", - "sigGen_Offset", - "sigGen_Aux", - "dp_ID", - "dp_Class", - "dp_Coeffs", - "ps_Model", - "wfmRef_PtrBufferStart", - "wfmRef_PtrBufferEnd", - "wfmRef_PtrBufferK", - "wfmRef_SyncMode", -] - - hradc_variant = [ "HRADC-FBP", "HRADC-FAX-A", diff --git a/src/pydrs/consts/common.py b/src/pydrs/consts/common.py index c7ce406..8aa6785 100644 --- a/src/pydrs/consts/common.py +++ b/src/pydrs/consts/common.py @@ -15,7 +15,7 @@ "FAP_IMAS", "FAC_2P_ACDC_IMAS", "FAC_2P_DCDC_IMAS", - "Invalid", + "RESONANT_SWLS", "Invalid", "Invalid", "Invalid", diff --git a/src/pydrs/consts/fac.py b/src/pydrs/consts/fac.py index e0816bc..3da178b 100644 --- a/src/pydrs/consts/fac.py +++ b/src/pydrs/consts/fac.py @@ -376,8 +376,8 @@ "i_leakage_iib": {"addr": 46, "format": "f", "size": 4, "egu": "A"}, "temp_board_iib": {"addr": 47, "format": "f", "size": 4, "egu": "°C"}, "rh_iib": {"addr": 48, "format": "f", "size": 4, "egu": "%"}, - "iib_interlocks": {"addr": 49, "format": "f", "size": 4, "egu": ""}, - "iib_alarms": {"addr": 50, "format": "f", "size": 4, "egu": ""}, + "iib_interlocks": {"addr": 49, "format": "I", "size": 4, "egu": ""}, + "iib_alarms": {"addr": 50, "format": "I", "size": 4, "egu": ""}, "ps_alarms": {"addr": 51, "format": "I", "size": 4, "egu": ""}, } diff --git a/src/pydrs/consts/resonant.py b/src/pydrs/consts/resonant.py new file mode 100644 index 0000000..9727bd4 --- /dev/null +++ b/src/pydrs/consts/resonant.py @@ -0,0 +1,17 @@ +# SWLS Resonant Converter +list_soft_interlocks = [] + +list_hard_interlocks = [ + "Load Overcurrent", + "DCLink Overvoltage", + "DCLink Undervoltage", +] + +bsmp = { + "ps_alarms": {"addr": 33, "format": "I", "size": 4, "egu": ""}, + "i_load": {"addr": 34, "format": "f", "size": 4, "egu": "A"}, + "v_dclink": {"addr": 35, "format": "f", "size": 4, "egu": "V"}, + "i_load_error": {"addr": 36, "format": "f", "size": 4, "egu": "A"}, + "freq_modulated": {"addr": 37, "format": "f", "size": 4, "egu": "Hz"}, + "freq_modulated_ff": {"addr": 38, "format": "f", "size": 4, "egu": "Hz"}, +} \ No newline at end of file From e9c48e7383883f623430e9e8fdab2d2b93f6e810 Mon Sep 17 00:00:00 2001 From: Gabriel Oehlmeyer Brunheira Date: Wed, 25 Jan 2023 10:31:35 -0300 Subject: [PATCH 2/3] Include leakage overcurrent interlock for FAC-DCDC and FAC-DCDC-EMA --- src/pydrs/consts/fac.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/pydrs/consts/fac.py b/src/pydrs/consts/fac.py index 3da178b..f4a2794 100644 --- a/src/pydrs/consts/fac.py +++ b/src/pydrs/consts/fac.py @@ -85,6 +85,7 @@ "IIB Interlock", "External Interlock", "Rack Interlock", + "Leakage_Overcurrent", ] list_dcdc_iib_interlocks = [ @@ -239,6 +240,7 @@ "Load Waterflow", "Load Overtemperature", "IIB Itlk", + "Leakage_Overcurrent", ] list_dcdc_ema_iib_interlocks = [ From ca03ac394324d0dc279cd230a4742df7d7e9b9b2 Mon Sep 17 00:00:00 2001 From: Gabriel Oehlmeyer Brunheira Date: Wed, 25 Jan 2023 10:34:59 -0300 Subject: [PATCH 3/3] Update changelog --- CHANGES.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGES.md b/CHANGES.md index 5875196..9961481 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -3,6 +3,8 @@ ## [2.1.0] - 2022-01-18 ### Added: - SWLS resonant converter PS module specification +- Leakage overcurrent interlock for FAC-DCDC and FAC-DCDC-EMA + ### Changed: - Fixed variable type for IIB interlock and alarm registers from FAC-DCDC-EMA PS module