From 5e47c45d21e9732955546d504da41045a93999e0 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 21 Jul 2022 18:03:03 +0200 Subject: [PATCH] Removed superfluous cell models Signed-off-by: Maciej Kurc --- ql-qlf-plugin/qlf_k6n10f/cells_sim.v | 81 ---------------------------- ql-qlf-plugin/qlf_k6n10f/dsp_sim.v | 21 -------- 2 files changed, 102 deletions(-) diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v index d3b78caea..3eb9b5ad3 100644 --- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v +++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v @@ -43,87 +43,6 @@ module adder_carry( endmodule -(* abc9_box, lib_whitebox *) -module adder_lut5( - output wire lut5_out, - (* abc9_carry *) - output wire cout, - input wire [0:4] in, - (* abc9_carry *) - input wire cin -); - parameter [0:15] LUT=0; - parameter IN2_IS_CIN = 0; - - wire [0:4] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3], in[4]} : {in[0], in[1], in[2], in[3],in[4]}; - - // Output function - wire [0:15] s1 = li[0] ? - {LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14], LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30]}: - {LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15], LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31]}; - - wire [0:7] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6], s1[8], s1[10], s1[12], s1[14]} : - {s1[1], s1[3], s1[5], s1[7], s1[9], s1[11], s1[13], s1[15]}; - - wire [0:3] s3 = li[2] ? {s2[0], s2[2], s2[4], s2[6]} : {s2[1], s2[3], s2[5], s2[7]}; - wire [0:1] s4 = li[3] ? {s3[0], s3[2]} : {s3[1], s3[3]}; - - assign lut5_out = li[4] ? s4[0] : s4[1]; - - // Carry out function - assign cout = (s3[2]) ? cin : s3[3]; - -endmodule - -(* abc9_lut=1, lib_whitebox *) -module frac_lut6( - input wire [0:5] in, - output wire [0:3] lut4_out, - output wire [0:1] lut5_out, - output wire lut6_out -); - parameter [0:63] LUT = 0; - // Effective LUT input - wire [0:5] li = in; - - // Output function - wire [0:31] s1 = li[0] ? - {LUT[0] , LUT[2] , LUT[4] , LUT[6] , LUT[8] , LUT[10], LUT[12], LUT[14], - LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30], - LUT[32], LUT[34], LUT[36], LUT[38], LUT[40], LUT[42], LUT[44], LUT[46], - LUT[48], LUT[50], LUT[52], LUT[54], LUT[56], LUT[58], LUT[60], LUT[62]}: - {LUT[1] , LUT[3] , LUT[5] , LUT[7] , LUT[9] , LUT[11], LUT[13], LUT[15], - LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31], - LUT[33], LUT[35], LUT[37], LUT[39], LUT[41], LUT[43], LUT[45], LUT[47], - LUT[49], LUT[51], LUT[53], LUT[55], LUT[57], LUT[59], LUT[61], LUT[63]}; - - wire [0:15] s2 = li[1] ? - {s1[0] , s1[2] , s1[4] , s1[6] , s1[8] , s1[10], s1[12], s1[14], - s1[16], s1[18], s1[20], s1[22], s1[24], s1[26], s1[28], s1[30]}: - {s1[1] , s1[3] , s1[5] , s1[7] , s1[9] , s1[11], s1[13], s1[15], - s1[17], s1[19], s1[21], s1[23], s1[25], s1[27], s1[29], s1[31]}; - - wire [0:7] s3 = li[2] ? - {s2[0], s2[2], s2[4], s2[6], s2[8], s2[10], s2[12], s2[14]}: - {s2[1], s2[3], s2[5], s2[7], s2[9], s2[11], s2[13], s2[15]}; - - wire [0:3] s4 = li[3] ? {s3[0], s3[2], s3[4], s3[6]}: - {s3[1], s3[3], s3[5], s3[7]}; - - wire [0:1] s5 = li[4] ? {s4[0], s4[2]} : {s4[1], s4[3]}; - - assign lut4_out[0] = s4[0]; - assign lut4_out[1] = s4[1]; - assign lut4_out[2] = s4[2]; - assign lut4_out[3] = s4[3]; - - assign lut5_out[0] = s5[0]; - assign lut5_out[1] = s5[1]; - - assign lut6_out = li[5] ? s5[0] : s5[1]; - -endmodule - (* abc9_flop, lib_whitebox *) module dff( output reg Q, diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v b/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v index 14ec751dd..44e528cff 100644 --- a/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v +++ b/ql-qlf-plugin/qlf_k6n10f/dsp_sim.v @@ -16,27 +16,6 @@ `default_nettype none -(* blackbox *) -module QL_DSP1 ( - input wire [19:0] a, - input wire [17:0] b, - (* clkbuf_sink *) - input wire clk0, - (* clkbuf_sink *) - input wire clk1, - input wire [ 1:0] feedback0, - input wire [ 1:0] feedback1, - input wire load_acc0, - input wire load_acc1, - input wire reset0, - input wire reset1, - output reg [37:0] z -); - parameter MODE_BITS = 27'b00000000000000000000000000; -endmodule /* QL_DSP1 */ - - - // ---------------------------------------- // // ----- DSP cells simulation modules ----- // // --------- Control bits in ports -------- //