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docs: Show all READMEs from the tests in the docs #71

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Changes:

Close #70

Signed-off-by: Daniel Lim Wee Soong [email protected]

Signed-off-by: Daniel Lim Wee Soong <[email protected]>
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Some problems I faced:

Undefined module OMUX

This line from pair.sim.v references an OMUX module

https://github.com/SymbiFlow/python-symbiflow-v2x/blob/21da32a7818df89a7815011d5ac38af476585a0a/tests/vtr/lutff-pair/pair.sim.v#L13

that is only generated and removed when running the tests as shown here

https://github.com/SymbiFlow/python-symbiflow-v2x/blob/21da32a7818df89a7815011d5ac38af476585a0a/tests/test_v2x.py#L57

This causes yosys to give an error when trying to generate a verilog-diagram for the PAIR module. Currently I avoided the error by not adding verilog-diagram to that section.

netlistsvg diagram too wide

image

Will need to modify the sphinxcontrib-verilog-diagram extension upstream code.

Code blocks have too many lines

Some of the model.xml files included have a few hundred lines, making the page very long. I don't think it would be good to truncate them as it will affect the completeness of this documentation. Might be good to extend the no-license extension to allow expanding/collapsing the code blocks, which can be done along with SymbiFlow/sphinxcontrib-hdl-diagrams#36. Alternatively, we can only show a maximum number of lines and give a link to the actual file on Github.

Any ideas?

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This should still be work in progress because of the problems above and the examples could have more explanation, but I'm not exactly sure what to add because of my limited knowledge of the project. Any suggestions would be helpful.

Signed-off-by: Daniel Lim Wee Soong <[email protected]>
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mithro commented Sep 11, 2020

@mkurc, could you take over this can and get it merged?

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mkurc commented Sep 11, 2020

Wrong mkurc.

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mithro commented Sep 14, 2020

Opps, sorry! -- @mkurc-ant, could you take over this can and get it merged?

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@mithro Ok, I'll take over this one.

@mkurc-ant mkurc-ant mentioned this pull request Sep 16, 2020
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Since I cannot push to daniellimws' repo I'm continuing this work in #78

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mithro commented Sep 16, 2020

Replaced by #78

@mithro mithro closed this Sep 16, 2020
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DSP and Verilog to Routing pages are broken
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