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Alongside the missing calibration routines from #56, the clock configuration steps were also removed. So, if a design uses an external clock, calling init fails to set up the ADCs, resulting in an unclocked FPGA.
The text was updated successfully, but these errors were encountered:
Alongside the missing calibration routines from #56, the clock configuration steps were also removed. So, if a design uses an external clock, calling
init
fails to set up the ADCs, resulting in an unclocked FPGA.The text was updated successfully, but these errors were encountered: