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FinalProject.qsf
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FinalProject.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# Date created = 11:28:28 July 23, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# FinalProject_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY FinalProject
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:28:28 JULY 23, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name VERILOG_FILE secondsClock.v
set_global_assignment -name VERILOG_FILE FinalProject.v
set_global_assignment -name VERILOG_FILE sevenSeg.v
set_global_assignment -name VERILOG_FILE ovenClock.v
set_global_assignment -name VERILOG_FILE temp_input.v
set_location_assignment PIN_C17 -to Hex0[6]
set_location_assignment PIN_C14 -to Hex0[0]
set_location_assignment PIN_E15 -to Hex0[1]
set_location_assignment PIN_C15 -to Hex0[2]
set_location_assignment PIN_C16 -to Hex0[3]
set_location_assignment PIN_E16 -to Hex0[4]
set_location_assignment PIN_D17 -to Hex0[5]
set_location_assignment PIN_D15 -to Hex0[7]
set_location_assignment PIN_B20 -to Hex2[0]
set_location_assignment PIN_A20 -to Hex2[1]
set_location_assignment PIN_B19 -to Hex2[2]
set_location_assignment PIN_A21 -to Hex2[3]
set_location_assignment PIN_B21 -to Hex2[4]
set_location_assignment PIN_C22 -to Hex2[5]
set_location_assignment PIN_B22 -to Hex2[6]
set_location_assignment PIN_A19 -to Hex2[7]
set_location_assignment PIN_F21 -to Hex3[0]
set_location_assignment PIN_E22 -to Hex3[1]
set_location_assignment PIN_E21 -to Hex3[2]
set_location_assignment PIN_C19 -to Hex3[3]
set_location_assignment PIN_C20 -to Hex3[4]
set_location_assignment PIN_D19 -to Hex3[5]
set_location_assignment PIN_E17 -to Hex3[6]
set_location_assignment PIN_D22 -to Hex3[7]
set_location_assignment PIN_F18 -to Hex4[0]
set_location_assignment PIN_E20 -to Hex4[1]
set_location_assignment PIN_E19 -to Hex4[2]
set_location_assignment PIN_H19 -to Hex4[4]
set_location_assignment PIN_J18 -to Hex4[3]
set_location_assignment PIN_F19 -to Hex4[5]
set_location_assignment PIN_F20 -to Hex4[6]
set_location_assignment PIN_F17 -to Hex4[7]
set_location_assignment PIN_J20 -to Hex5[0]
set_location_assignment PIN_K20 -to Hex5[1]
set_location_assignment PIN_L18 -to Hex5[2]
set_location_assignment PIN_N18 -to Hex5[3]
set_location_assignment PIN_M20 -to Hex5[4]
set_location_assignment PIN_N19 -to Hex5[5]
set_location_assignment PIN_N20 -to Hex5[6]
set_location_assignment PIN_L19 -to Hex5[7]
set_location_assignment PIN_P11 -to clk
set_location_assignment PIN_F15 -to in[3]
set_location_assignment PIN_B14 -to in[2]
set_location_assignment PIN_A14 -to in[1]
set_location_assignment PIN_A13 -to in[0]
set_location_assignment PIN_C18 -to Hex1[0]
set_location_assignment PIN_D18 -to Hex1[1]
set_location_assignment PIN_E18 -to Hex1[2]
set_location_assignment PIN_B16 -to Hex1[3]
set_location_assignment PIN_A17 -to Hex1[4]
set_location_assignment PIN_A18 -to Hex1[5]
set_location_assignment PIN_B17 -to Hex1[6]
set_location_assignment PIN_C10 -to onOff
set_location_assignment PIN_B8 -to pushButton[0]
set_location_assignment PIN_A7 -to pushButton[1]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE bakingState.v
set_location_assignment PIN_B11 -to readyLed
set_global_assignment -name VERILOG_FILE fastClock.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top