-
-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathpwm.py
50 lines (38 loc) · 1.07 KB
/
pwm.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
from amaranth import *
from amaranth.sim import *
class PWM(Elaboratable):
def __init__(self, bits=8, duty=1):
self.bits = bits
self.duty = Signal(bits, reset=duty)
self.out = Signal()
self.ports = (
self.duty,
self.out
)
def elaborate(self, platform):
counter = Signal(self.bits, reset=0)
m = Module()
m.d.sync += counter.eq(counter + 1)
with m.If(counter < self.duty):
m.d.sync += self.out.eq(1)
with m.Else():
m.d.sync += self.out.eq(0)
return m
if __name__ == '__main__':
dut = PWM(bits=8, duty=10)
sim = Simulator(dut)
def do():
for i in range(512):
yield
def proc():
yield from do()
yield dut.duty.eq(20)
yield from do()
yield dut.duty.eq(128)
yield from do()
yield dut.duty.eq(1)
yield from do()
sim.add_clock(1e-6)
sim.add_sync_process(proc)
with sim.write_vcd('pwm.vcd', 'pwm_orig.gtkw', traces=dut.ports):
sim.run()