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up.patch
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diff -urN msm-3.4.2/Makefile msm-3.4.4/Makefile
--- msm-3.4.2/Makefile 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/Makefile 2012-06-23 03:37:50.000000000 +0900
@@ -1,6 +1,6 @@
VERSION = 3
PATCHLEVEL = 4
-SUBLEVEL = 2
+SUBLEVEL = 4
EXTRAVERSION =
NAME = Saber-toothed Squirrel
diff -urN msm-3.4.2/arch/arm/mach-imx/crm-regs-imx5.h msm-3.4.4/arch/arm/mach-imx/crm-regs-imx5.h
--- msm-3.4.2/arch/arm/mach-imx/crm-regs-imx5.h 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/arm/mach-imx/crm-regs-imx5.h 2012-06-23 03:37:50.000000000 +0900
@@ -23,7 +23,7 @@
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
-#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
/* PLL Register Offsets */
#define MXC_PLL_DP_CTL 0x00
diff -urN msm-3.4.2/arch/arm/mach-imx/hotplug.c msm-3.4.4/arch/arm/mach-imx/hotplug.c
--- msm-3.4.2/arch/arm/mach-imx/hotplug.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/arm/mach-imx/hotplug.c 2012-06-23 03:37:50.000000000 +0900
@@ -12,6 +12,7 @@
#include <linux/errno.h>
#include <asm/cacheflush.h>
+#include <asm/cp15.h>
#include <mach/common.h>
int platform_cpu_kill(unsigned int cpu)
@@ -19,6 +20,44 @@
return 1;
}
+static inline void cpu_enter_lowpower(void)
+{
+ unsigned int v;
+
+ flush_cache_all();
+ asm volatile(
+ "mcr p15, 0, %1, c7, c5, 0\n"
+ " mcr p15, 0, %1, c7, c10, 4\n"
+ /*
+ * Turn off coherency
+ */
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " bic %0, %0, %3\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ " mrc p15, 0, %0, c1, c0, 0\n"
+ " bic %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ : "=&r" (v)
+ : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+ : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+ unsigned int v;
+
+ asm volatile(
+ "mrc p15, 0, %0, c1, c0, 0\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c1, c0, 0\n"
+ " mrc p15, 0, %0, c1, c0, 1\n"
+ " orr %0, %0, %2\n"
+ " mcr p15, 0, %0, c1, c0, 1\n"
+ : "=&r" (v)
+ : "Ir" (CR_C), "Ir" (0x40)
+ : "cc");
+}
+
/*
* platform-specific code to shutdown a CPU
*
@@ -26,9 +65,10 @@
*/
void platform_cpu_die(unsigned int cpu)
{
- flush_cache_all();
+ cpu_enter_lowpower();
imx_enable_cpu(cpu, false);
cpu_do_idle();
+ cpu_leave_lowpower();
/* We should never return from idle */
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
diff -urN msm-3.4.2/arch/arm/mach-imx/mach-mx21ads.c msm-3.4.4/arch/arm/mach-imx/mach-mx21ads.c
--- msm-3.4.2/arch/arm/mach-imx/mach-mx21ads.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/arm/mach-imx/mach-mx21ads.c 2012-06-23 03:37:50.000000000 +0900
@@ -32,7 +32,7 @@
* Memory-mapped I/O on MX21ADS base board
*/
#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
-#define MX21ADS_MMIO_SIZE SZ_16M
+#define MX21ADS_MMIO_SIZE 0xc00000
#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
(MX21ADS_MMIO_BASE_ADDR + (offset))
diff -urN msm-3.4.2/arch/powerpc/include/asm/hw_irq.h msm-3.4.4/arch/powerpc/include/asm/hw_irq.h
--- msm-3.4.2/arch/powerpc/include/asm/hw_irq.h 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/powerpc/include/asm/hw_irq.h 2012-06-23 03:37:50.000000000 +0900
@@ -99,6 +99,9 @@
get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
}
+/* include/linux/interrupt.h needs hard_irq_disable to be a macro */
+#define hard_irq_disable hard_irq_disable
+
/*
* This is called by asynchronous interrupts to conditionally
* re-enable hard interrupts when soft-disabled after having
diff -urN msm-3.4.2/arch/powerpc/kernel/module_32.c msm-3.4.4/arch/powerpc/kernel/module_32.c
--- msm-3.4.2/arch/powerpc/kernel/module_32.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/powerpc/kernel/module_32.c 2012-06-23 03:37:50.000000000 +0900
@@ -176,8 +176,8 @@
static inline int entry_matches(struct ppc_plt_entry *entry, Elf32_Addr val)
{
- if (entry->jump[0] == 0x3d600000 + ((val + 0x8000) >> 16)
- && entry->jump[1] == 0x396b0000 + (val & 0xffff))
+ if (entry->jump[0] == 0x3d800000 + ((val + 0x8000) >> 16)
+ && entry->jump[1] == 0x398c0000 + (val & 0xffff))
return 1;
return 0;
}
@@ -204,10 +204,9 @@
entry++;
}
- /* Stolen from Paul Mackerras as well... */
- entry->jump[0] = 0x3d600000+((val+0x8000)>>16); /* lis r11,sym@ha */
- entry->jump[1] = 0x396b0000 + (val&0xffff); /* addi r11,r11,sym@l*/
- entry->jump[2] = 0x7d6903a6; /* mtctr r11 */
+ entry->jump[0] = 0x3d800000+((val+0x8000)>>16); /* lis r12,sym@ha */
+ entry->jump[1] = 0x398c0000 + (val&0xffff); /* addi r12,r12,sym@l*/
+ entry->jump[2] = 0x7d8903a6; /* mtctr r12 */
entry->jump[3] = 0x4e800420; /* bctr */
DEBUGP("Initialized plt for 0x%x at %p\n", val, entry);
diff -urN msm-3.4.2/arch/powerpc/kernel/time.c msm-3.4.4/arch/powerpc/kernel/time.c
--- msm-3.4.2/arch/powerpc/kernel/time.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/powerpc/kernel/time.c 2012-06-23 03:37:50.000000000 +0900
@@ -474,6 +474,7 @@
struct pt_regs *old_regs;
u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
struct clock_event_device *evt = &__get_cpu_var(decrementers);
+ u64 now;
/* Ensure a positive value is written to the decrementer, or else
* some CPUs will continue to take decrementer exceptions.
@@ -508,9 +509,16 @@
irq_work_run();
}
- *next_tb = ~(u64)0;
- if (evt->event_handler)
- evt->event_handler(evt);
+ now = get_tb_or_rtc();
+ if (now >= *next_tb) {
+ *next_tb = ~(u64)0;
+ if (evt->event_handler)
+ evt->event_handler(evt);
+ } else {
+ now = *next_tb - now;
+ if (now <= DECREMENTER_MAX)
+ set_dec((int)now);
+ }
#ifdef CONFIG_PPC64
/* collect purr register values often, for accurate calculations */
diff -urN msm-3.4.2/arch/x86/crypto/aesni-intel_asm.S msm-3.4.4/arch/x86/crypto/aesni-intel_asm.S
--- msm-3.4.2/arch/x86/crypto/aesni-intel_asm.S 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/x86/crypto/aesni-intel_asm.S 2012-06-23 03:37:50.000000000 +0900
@@ -2460,10 +2460,12 @@
pxor IN3, STATE4
movaps IN4, IV
#else
- pxor (INP), STATE2
- pxor 0x10(INP), STATE3
pxor IN1, STATE4
movaps IN2, IV
+ movups (INP), IN1
+ pxor IN1, STATE2
+ movups 0x10(INP), IN2
+ pxor IN2, STATE3
#endif
movups STATE1, (OUTP)
movups STATE2, 0x10(OUTP)
diff -urN msm-3.4.2/arch/x86/include/asm/uv/uv_bau.h msm-3.4.4/arch/x86/include/asm/uv/uv_bau.h
--- msm-3.4.2/arch/x86/include/asm/uv/uv_bau.h 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/x86/include/asm/uv/uv_bau.h 2012-06-23 03:37:50.000000000 +0900
@@ -149,7 +149,6 @@
/* 4 bits of software ack period */
#define UV2_ACK_MASK 0x7UL
#define UV2_ACK_UNITS_SHFT 3
-#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
/*
diff -urN msm-3.4.2/arch/x86/kernel/cpu/mcheck/mce_amd.c msm-3.4.4/arch/x86/kernel/cpu/mcheck/mce_amd.c
--- msm-3.4.2/arch/x86/kernel/cpu/mcheck/mce_amd.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/x86/kernel/cpu/mcheck/mce_amd.c 2012-06-23 03:37:50.000000000 +0900
@@ -51,6 +51,7 @@
unsigned int cpu;
u32 address;
u16 interrupt_enable;
+ bool interrupt_capable;
u16 threshold_limit;
struct kobject kobj;
struct list_head miscj;
@@ -83,6 +84,21 @@
u16 old_limit;
};
+static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
+{
+ /*
+ * bank 4 supports APIC LVT interrupts implicitly since forever.
+ */
+ if (bank == 4)
+ return true;
+
+ /*
+ * IntP: interrupt present; if this bit is set, the thresholding
+ * bank can generate APIC LVT interrupts
+ */
+ return msr_high_bits & BIT(28);
+}
+
static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
{
int msr = (hi & MASK_LVTOFF_HI) >> 20;
@@ -104,8 +120,10 @@
return 1;
};
-/* must be called with correct cpu affinity */
-/* Called via smp_call_function_single() */
+/*
+ * Called via smp_call_function_single(), must be called with correct
+ * cpu affinity.
+ */
static void threshold_restart_bank(void *_tr)
{
struct thresh_restart *tr = _tr;
@@ -128,6 +146,12 @@
(new_count & THRESHOLD_MAX);
}
+ /* clear IntType */
+ hi &= ~MASK_INT_TYPE_HI;
+
+ if (!tr->b->interrupt_capable)
+ goto done;
+
if (tr->set_lvt_off) {
if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
/* set new lvt offset */
@@ -136,9 +160,10 @@
}
}
- tr->b->interrupt_enable ?
- (hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
- (hi &= ~MASK_INT_TYPE_HI);
+ if (tr->b->interrupt_enable)
+ hi |= INT_TYPE_APIC;
+
+ done:
hi |= MASK_COUNT_EN_HI;
wrmsr(tr->b->address, lo, hi);
@@ -202,14 +227,17 @@
if (shared_bank[bank] && c->cpu_core_id)
break;
- offset = setup_APIC_mce(offset,
- (high & MASK_LVTOFF_HI) >> 20);
-
memset(&b, 0, sizeof(b));
- b.cpu = cpu;
- b.bank = bank;
- b.block = block;
- b.address = address;
+ b.cpu = cpu;
+ b.bank = bank;
+ b.block = block;
+ b.address = address;
+ b.interrupt_capable = lvt_interrupt_supported(bank, high);
+
+ if (b.interrupt_capable) {
+ int new = (high & MASK_LVTOFF_HI) >> 20;
+ offset = setup_APIC_mce(offset, new);
+ }
mce_threshold_block_init(&b, offset);
mce_threshold_vector = amd_threshold_interrupt;
@@ -309,6 +337,9 @@
struct thresh_restart tr;
unsigned long new;
+ if (!b->interrupt_capable)
+ return -EINVAL;
+
if (strict_strtoul(buf, 0, &new) < 0)
return -EINVAL;
@@ -467,6 +498,7 @@
b->cpu = cpu;
b->address = address;
b->interrupt_enable = 0;
+ b->interrupt_capable = lvt_interrupt_supported(bank, high);
b->threshold_limit = THRESHOLD_MAX;
INIT_LIST_HEAD(&b->miscj);
diff -urN msm-3.4.2/arch/x86/platform/uv/tlb_uv.c msm-3.4.4/arch/x86/platform/uv/tlb_uv.c
--- msm-3.4.2/arch/x86/platform/uv/tlb_uv.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/x86/platform/uv/tlb_uv.c 2012-06-23 03:37:50.000000000 +0900
@@ -1295,7 +1295,6 @@
*/
mmr_image |= (1L << SOFTACK_MSHIFT);
if (is_uv2_hub()) {
- mmr_image &= ~(1L << UV2_LEG_SHFT);
mmr_image |= (1L << UV2_EXT_SHFT);
}
write_mmr_misc_control(pnode, mmr_image);
diff -urN msm-3.4.2/arch/x86/xen/enlighten.c msm-3.4.4/arch/x86/xen/enlighten.c
--- msm-3.4.2/arch/x86/xen/enlighten.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/arch/x86/xen/enlighten.c 2012-06-23 03:37:50.000000000 +0900
@@ -207,6 +207,9 @@
xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : "");
}
+#define CPUID_THERM_POWER_LEAF 6
+#define APERFMPERF_PRESENT 0
+
static __read_mostly unsigned int cpuid_leaf1_edx_mask = ~0;
static __read_mostly unsigned int cpuid_leaf1_ecx_mask = ~0;
@@ -240,6 +243,11 @@
*dx = cpuid_leaf5_edx_val;
return;
+ case CPUID_THERM_POWER_LEAF:
+ /* Disabling APERFMPERF for kernel usage */
+ maskecx = ~(1 << APERFMPERF_PRESENT);
+ break;
+
case 0xb:
/* Suppress extended topology stuff */
maskebx = 0;
diff -urN msm-3.4.2/drivers/acpi/video.c msm-3.4.4/drivers/acpi/video.c
--- msm-3.4.2/drivers/acpi/video.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/acpi/video.c 2012-06-23 03:37:50.000000000 +0900
@@ -1745,6 +1745,7 @@
static int __init intel_opregion_present(void)
{
+ int i915 = 0;
#if defined(CONFIG_DRM_I915) || defined(CONFIG_DRM_I915_MODULE)
struct pci_dev *dev = NULL;
u32 address;
@@ -1757,10 +1758,10 @@
pci_read_config_dword(dev, 0xfc, &address);
if (!address)
continue;
- return 1;
+ i915 = 1;
}
#endif
- return 0;
+ return i915;
}
int acpi_video_register(void)
diff -urN msm-3.4.2/drivers/ata/ata_piix.c msm-3.4.4/drivers/ata/ata_piix.c
--- msm-3.4.2/drivers/ata/ata_piix.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/ata/ata_piix.c 2012-06-23 03:37:50.000000000 +0900
@@ -1554,6 +1554,39 @@
return false;
}
+static int prefer_ms_hyperv = 1;
+module_param(prefer_ms_hyperv, int, 0);
+
+static void piix_ignore_devices_quirk(struct ata_host *host)
+{
+#if IS_ENABLED(CONFIG_HYPERV_STORAGE)
+ static const struct dmi_system_id ignore_hyperv[] = {
+ {
+ /* On Hyper-V hypervisors the disks are exposed on
+ * both the emulated SATA controller and on the
+ * paravirtualised drivers. The CD/DVD devices
+ * are only exposed on the emulated controller.
+ * Request we ignore ATA devices on this host.
+ */
+ .ident = "Hyper-V Virtual Machine",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR,
+ "Microsoft Corporation"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
+ },
+ },
+ { } /* terminate list */
+ };
+ const struct dmi_system_id *dmi = dmi_first_match(ignore_hyperv);
+
+ if (dmi && prefer_ms_hyperv) {
+ host->flags |= ATA_HOST_IGNORE_ATA;
+ dev_info(host->dev, "%s detected, ATA device ignore set\n",
+ dmi->ident);
+ }
+#endif
+}
+
/**
* piix_init_one - Register PIIX ATA PCI device with kernel services
* @pdev: PCI device to register
@@ -1669,6 +1702,9 @@
}
host->flags |= ATA_HOST_PARALLEL_SCAN;
+ /* Allow hosts to specify device types to ignore when scanning. */
+ piix_ignore_devices_quirk(host);
+
pci_set_master(pdev);
return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
}
diff -urN msm-3.4.2/drivers/ata/libata-core.c msm-3.4.4/drivers/ata/libata-core.c
--- msm-3.4.2/drivers/ata/libata-core.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/ata/libata-core.c 2012-06-23 03:37:50.000000000 +0900
@@ -1973,6 +1973,12 @@
if (class == ATA_DEV_ATA) {
if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
goto err_out;
+ if (ap->host->flags & ATA_HOST_IGNORE_ATA &&
+ ata_id_is_ata(id)) {
+ ata_dev_dbg(dev,
+ "host indicates ignore ATA devices, ignored\n");
+ return -ENOENT;
+ }
} else {
if (ata_id_is_ata(id))
goto err_out;
diff -urN msm-3.4.2/drivers/bcma/driver_chipcommon_pmu.c msm-3.4.4/drivers/bcma/driver_chipcommon_pmu.c
--- msm-3.4.2/drivers/bcma/driver_chipcommon_pmu.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/bcma/driver_chipcommon_pmu.c 2012-06-23 03:37:50.000000000 +0900
@@ -139,7 +139,9 @@
bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
break;
case 0x4331:
- /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
+ case 43431:
+ /* Ext PA lines must be enabled for tx on BCM4331 */
+ bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
break;
case 43224:
if (bus->chipinfo.rev == 0) {
diff -urN msm-3.4.2/drivers/bcma/sprom.c msm-3.4.4/drivers/bcma/sprom.c
--- msm-3.4.2/drivers/bcma/sprom.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/bcma/sprom.c 2012-06-23 03:37:50.000000000 +0900
@@ -432,13 +432,13 @@
if (!sprom)
return -ENOMEM;
- if (bus->chipinfo.id == 0x4331)
+ if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431)
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
pr_debug("SPROM offset 0x%x\n", offset);
bcma_sprom_read(bus, offset, sprom);
- if (bus->chipinfo.id == 0x4331)
+ if (bus->chipinfo.id == 0x4331 || bus->chipinfo.id == 43431)
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
err = bcma_sprom_valid(sprom);
diff -urN msm-3.4.2/drivers/char/agp/intel-agp.c msm-3.4.4/drivers/char/agp/intel-agp.c
--- msm-3.4.2/drivers/char/agp/intel-agp.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/char/agp/intel-agp.c 2012-06-23 03:37:50.000000000 +0900
@@ -898,6 +898,7 @@
ID(PCI_DEVICE_ID_INTEL_B43_HB),
ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
+ ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
diff -urN msm-3.4.2/drivers/char/agp/intel-agp.h msm-3.4.4/drivers/char/agp/intel-agp.h
--- msm-3.4.2/drivers/char/agp/intel-agp.h 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/char/agp/intel-agp.h 2012-06-23 03:37:50.000000000 +0900
@@ -211,6 +211,7 @@
#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
+#define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
diff -urN msm-3.4.2/drivers/char/hw_random/atmel-rng.c msm-3.4.4/drivers/char/hw_random/atmel-rng.c
--- msm-3.4.2/drivers/char/hw_random/atmel-rng.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/char/hw_random/atmel-rng.c 2012-06-23 03:37:50.000000000 +0900
@@ -34,8 +34,15 @@
u32 *data = buf;
/* data ready? */
- if (readl(trng->base + TRNG_ODATA) & 1) {
+ if (readl(trng->base + TRNG_ISR) & 1) {
*data = readl(trng->base + TRNG_ODATA);
+ /*
+ ensure data ready is only set again AFTER the next data
+ word is ready in case it got set between checking ISR
+ and reading ODATA, so we don't risk re-reading the
+ same word
+ */
+ readl(trng->base + TRNG_ISR);
return 4;
} else
return 0;
diff -urN msm-3.4.2/drivers/edac/i7core_edac.c msm-3.4.4/drivers/edac/i7core_edac.c
--- msm-3.4.2/drivers/edac/i7core_edac.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/edac/i7core_edac.c 2012-06-23 03:37:50.000000000 +0900
@@ -1932,12 +1932,6 @@
if (mce->bank != 8)
return NOTIFY_DONE;
-#ifdef CONFIG_SMP
- /* Only handle if it is the right mc controller */
- if (mce->socketid != pvt->i7core_dev->socket)
- return NOTIFY_DONE;
-#endif
-
smp_rmb();
if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
smp_wmb();
@@ -2234,8 +2228,6 @@
if (pvt->enable_scrub)
disable_sdram_scrub_setting(mci);
- mce_unregister_decode_chain(&i7_mce_dec);
-
/* Disable EDAC polling */
i7core_pci_ctl_release(pvt);
@@ -2336,8 +2328,6 @@
/* DCLK for scrub rate setting */
pvt->dclk_freq = get_dclk_freq();
- mce_register_decode_chain(&i7_mce_dec);
-
return 0;
fail0:
@@ -2481,8 +2471,10 @@
pci_rc = pci_register_driver(&i7core_driver);
- if (pci_rc >= 0)
+ if (pci_rc >= 0) {
+ mce_register_decode_chain(&i7_mce_dec);
return 0;
+ }
i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
pci_rc);
@@ -2498,6 +2490,7 @@
{
debugf2("MC: " __FILE__ ": %s()\n", __func__);
pci_unregister_driver(&i7core_driver);
+ mce_unregister_decode_chain(&i7_mce_dec);
}
module_init(i7core_init);
diff -urN msm-3.4.2/drivers/edac/sb_edac.c msm-3.4.4/drivers/edac/sb_edac.c
--- msm-3.4.2/drivers/edac/sb_edac.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/edac/sb_edac.c 2012-06-23 03:37:50.000000000 +0900
@@ -599,7 +599,7 @@
pvt->is_close_pg = false;
}
- pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, ®);
+ pci_read_config_dword(pvt->pci_ddrio, RANK_CFG_A, ®);
if (IS_RDIMM_ENABLED(reg)) {
/* FIXME: Can also be LRDIMM */
debugf0("Memory is registered\n");
@@ -1669,8 +1669,6 @@
debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
__func__, mci, &sbridge_dev->pdev[0]->dev);
- mce_unregister_decode_chain(&sbridge_mce_dec);
-
/* Remove MC sysfs nodes */
edac_mc_del_mc(mci->dev);
@@ -1738,7 +1736,6 @@
goto fail0;
}
- mce_register_decode_chain(&sbridge_mce_dec);
return 0;
fail0:
@@ -1867,8 +1864,10 @@
pci_rc = pci_register_driver(&sbridge_driver);
- if (pci_rc >= 0)
+ if (pci_rc >= 0) {
+ mce_register_decode_chain(&sbridge_mce_dec);
return 0;
+ }
sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
pci_rc);
@@ -1884,6 +1883,7 @@
{
debugf2("MC: " __FILE__ ": %s()\n", __func__);
pci_unregister_driver(&sbridge_driver);
+ mce_unregister_decode_chain(&sbridge_mce_dec);
}
module_init(sbridge_init);
diff -urN msm-3.4.2/drivers/gpu/drm/gma500/psb_drv.c msm-3.4.4/drivers/gpu/drm/gma500/psb_drv.c
--- msm-3.4.2/drivers/gpu/drm/gma500/psb_drv.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/gma500/psb_drv.c 2012-06-23 03:37:50.000000000 +0900
@@ -349,7 +349,7 @@
PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
/* igd_opregion_init(&dev_priv->opregion_dev); */
- acpi_video_register();
+/* acpi_video_register(); */
if (dev_priv->lid_state)
psb_lid_timer_init(dev_priv);
diff -urN msm-3.4.2/drivers/gpu/drm/i915/intel_dp.c msm-3.4.4/drivers/gpu/drm/i915/intel_dp.c
--- msm-3.4.2/drivers/gpu/drm/i915/intel_dp.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/i915/intel_dp.c 2012-06-23 03:37:50.000000000 +0900
@@ -368,7 +368,7 @@
int recv_bytes;
uint32_t status;
uint32_t aux_clock_divider;
- int try, precharge = 5;
+ int try, precharge;
intel_dp_check_edp(intel_dp);
/* The clock divider is based off the hrawclk,
@@ -388,6 +388,11 @@
else
aux_clock_divider = intel_hrawclk(dev) / 2;
+ if (IS_GEN6(dev))
+ precharge = 3;
+ else
+ precharge = 5;
+
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
status = I915_READ(ch_ctl);
diff -urN msm-3.4.2/drivers/gpu/drm/i915/intel_ringbuffer.c msm-3.4.4/drivers/gpu/drm/i915/intel_ringbuffer.c
--- msm-3.4.2/drivers/gpu/drm/i915/intel_ringbuffer.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/i915/intel_ringbuffer.c 2012-06-23 03:37:50.000000000 +0900
@@ -309,6 +309,7 @@
ring->head = I915_READ_HEAD(ring);
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ring->space = ring_space(ring);
+ ring->last_retired_head = -1;
}
return 0;
@@ -1026,6 +1027,10 @@
if (ret)
goto err_unref;
+ ret = i915_gem_object_set_to_gtt_domain(obj, true);
+ if (ret)
+ goto err_unpin;
+
ring->map.size = ring->size;
ring->map.offset = dev->agp->base + obj->gtt_offset;
ring->map.type = 0;
diff -urN msm-3.4.2/drivers/gpu/drm/nouveau/nouveau_connector.c msm-3.4.4/drivers/gpu/drm/nouveau/nouveau_connector.c
--- msm-3.4.2/drivers/gpu/drm/nouveau/nouveau_connector.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/nouveau/nouveau_connector.c 2012-06-23 03:37:50.000000000 +0900
@@ -654,7 +654,13 @@
if (nv_connector->edid && connector->display_info.bpc)
return;
- /* if not, we're out of options unless we're LVDS, default to 8bpc */
+ /* EDID 1.4 is *supposed* to be supported on eDP, but, Apple... */
+ if (nv_connector->type == DCB_CONNECTOR_eDP) {
+ connector->display_info.bpc = 6;
+ return;
+ }
+
+ /* we're out of options unless we're LVDS, default to 8bpc */
if (nv_encoder->dcb->type != OUTPUT_LVDS) {
connector->display_info.bpc = 8;
return;
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/evergreen.c msm-3.4.4/drivers/gpu/drm/radeon/evergreen.c
--- msm-3.4.2/drivers/gpu/drm/radeon/evergreen.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/evergreen.c 2012-06-23 03:37:50.000000000 +0900
@@ -2210,6 +2210,9 @@
smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
WREG32(SMX_DC_CTL0, smx_dc_ctl0);
+ if (rdev->family <= CHIP_SUMO2)
+ WREG32(SMX_SAR_CTL0, 0x00010000);
+
WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/evergreen_cs.c msm-3.4.4/drivers/gpu/drm/radeon/evergreen_cs.c
--- msm-3.4.2/drivers/gpu/drm/radeon/evergreen_cs.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/evergreen_cs.c 2012-06-23 03:37:50.000000000 +0900
@@ -52,6 +52,7 @@
u32 cb_color_view[12];
u32 cb_color_pitch[12];
u32 cb_color_slice[12];
+ u32 cb_color_slice_idx[12];
u32 cb_color_attrib[12];
u32 cb_color_cmask_slice[8];/* unused */
u32 cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@
track->cb_color_info[i] = 0;
track->cb_color_view[i] = 0xFFFFFFFF;
track->cb_color_pitch[i] = 0;
- track->cb_color_slice[i] = 0;
+ track->cb_color_slice[i] = 0xfffffff;
+ track->cb_color_slice_idx[i] = 0;
}
track->cb_target_mask = 0xFFFFFFFF;
track->cb_shader_mask = 0xFFFFFFFF;
track->cb_dirty = true;
+ track->db_depth_slice = 0xffffffff;
track->db_depth_view = 0xFFFFC000;
track->db_depth_size = 0xFFFFFFFF;
track->db_depth_control = 0xFFFFFFFF;
@@ -250,10 +253,9 @@
{
struct evergreen_cs_track *track = p->track;
unsigned palign, halign, tileb, slice_pt;
+ unsigned mtile_pr, mtile_ps, mtileb;
tileb = 64 * surf->bpe * surf->nsamples;
- palign = track->group_size / (8 * surf->bpe * surf->nsamples);
- palign = MAX(8, palign);
slice_pt = 1;
if (tileb > surf->tsplit) {
slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@
/* macro tile width & height */
palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
- surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
+ mtileb = (palign / 8) * (halign / 8) * tileb;;
+ mtile_pr = surf->nbx / palign;
+ mtile_ps = (mtile_pr * surf->nby) / halign;
+ surf->layer_size = mtile_ps * mtileb * slice_pt;
surf->base_align = (palign / 8) * (halign / 8) * tileb;
surf->palign = palign;
surf->halign = halign;
@@ -434,6 +439,39 @@
offset += surf.layer_size * mslice;
if (offset > radeon_bo_size(track->cb_color_bo[id])) {
+ /* old ddx are broken they allocate bo with w*h*bpp but
+ * program slice with ALIGN(h, 8), catch this and patch
+ * command stream.
+ */
+ if (!surf.mode) {
+ volatile u32 *ib = p->ib->ptr;
+ unsigned long tmp, nby, bsize, size, min = 0;
+
+ /* find the height the ddx wants */
+ if (surf.nby > 8) {
+ min = surf.nby - 8;
+ }
+ bsize = radeon_bo_size(track->cb_color_bo[id]);
+ tmp = track->cb_color_bo_offset[id] << 8;
+ for (nby = surf.nby; nby > min; nby--) {
+ size = nby * surf.nbx * surf.bpe * surf.nsamples;
+ if ((tmp + size * mslice) <= bsize) {
+ break;
+ }
+ }
+ if (nby > min) {
+ surf.nby = nby;
+ slice = ((nby * surf.nbx) / 64) - 1;
+ if (!evergreen_surface_check(p, &surf, "cb")) {
+ /* check if this one works */
+ tmp += surf.layer_size * mslice;
+ if (tmp <= bsize) {
+ ib[track->cb_color_slice_idx[id]] = slice;
+ goto old_ddx_ok;
+ }
+ }
+ }
+ }
dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
"offset %d, max layer %d, bo size %ld, slice %d)\n",
__func__, __LINE__, id, surf.layer_size,
@@ -446,6 +484,7 @@
surf.tsplit, surf.mtilea);
return -EINVAL;
}
+old_ddx_ok:
return 0;
}
@@ -1532,6 +1571,7 @@
case CB_COLOR7_SLICE:
tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+ track->cb_color_slice_idx[tmp] = idx;
track->cb_dirty = true;
break;
case CB_COLOR8_SLICE:
@@ -1540,6 +1580,7 @@
case CB_COLOR11_SLICE:
tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+ track->cb_color_slice_idx[tmp] = idx;
track->cb_dirty = true;
break;
case CB_COLOR0_ATTRIB:
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/evergreend.h msm-3.4.4/drivers/gpu/drm/radeon/evergreend.h
--- msm-3.4.2/drivers/gpu/drm/radeon/evergreend.h 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/evergreend.h 2012-06-23 03:37:50.000000000 +0900
@@ -273,6 +273,7 @@
#define SCRATCH_UMSK 0x8540
#define SCRATCH_ADDR 0x8544
+#define SMX_SAR_CTL0 0xA008
#define SMX_DC_CTL0 0xA020
#define USE_HASH_FUNCTION (1 << 0)
#define NUMBER_OF_SETS(x) ((x) << 1)
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/r600.c msm-3.4.4/drivers/gpu/drm/radeon/r600.c
--- msm-3.4.2/drivers/gpu/drm/radeon/r600.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/r600.c 2012-06-23 03:37:50.000000000 +0900
@@ -1906,6 +1906,7 @@
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
NUM_CLIP_SEQ(3)));
WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
+ WREG32(VC_ENHANCE, 0);
}
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/r600d.h msm-3.4.4/drivers/gpu/drm/radeon/r600d.h
--- msm-3.4.2/drivers/gpu/drm/radeon/r600d.h 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/r600d.h 2012-06-23 03:37:50.000000000 +0900
@@ -483,6 +483,7 @@
#define TC_L2_SIZE(x) ((x)<<5)
#define L2_DISABLE_LATE_HIT (1<<9)
+#define VC_ENHANCE 0x9714
#define VGT_CACHE_INVALIDATION 0x88C4
#define CACHE_INVALIDATION(x) ((x)<<0)
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/radeon_drv.c msm-3.4.4/drivers/gpu/drm/radeon/radeon_drv.c
--- msm-3.4.2/drivers/gpu/drm/radeon/radeon_drv.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/radeon_drv.c 2012-06-23 03:37:50.000000000 +0900
@@ -57,9 +57,10 @@
* 2.13.0 - virtual memory support, streamout
* 2.14.0 - add evergreen tiling informations
* 2.15.0 - add max_pipes query
+ * 2.16.0 - fix evergreen 2D tiled surface calculation
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 15
+#define KMS_DRIVER_MINOR 16
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/rv770.c msm-3.4.4/drivers/gpu/drm/radeon/rv770.c
--- msm-3.4.2/drivers/gpu/drm/radeon/rv770.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/rv770.c 2012-06-23 03:37:50.000000000 +0900
@@ -782,6 +782,9 @@
ACK_FLUSH_CTL(3) |
SYNC_FLUSH_CTL));
+ if (rdev->family != CHIP_RV770)
+ WREG32(SMX_SAR_CTL0, 0x00003f3f);
+
db_debug3 = RREG32(DB_DEBUG3);
db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
switch (rdev->family) {
@@ -960,7 +963,7 @@
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
NUM_CLIP_SEQ(3)));
-
+ WREG32(VC_ENHANCE, 0);
}
void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
diff -urN msm-3.4.2/drivers/gpu/drm/radeon/rv770d.h msm-3.4.4/drivers/gpu/drm/radeon/rv770d.h
--- msm-3.4.2/drivers/gpu/drm/radeon/rv770d.h 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/radeon/rv770d.h 2012-06-23 03:37:50.000000000 +0900
@@ -208,6 +208,7 @@
#define SCRATCH_UMSK 0x8540
#define SCRATCH_ADDR 0x8544
+#define SMX_SAR_CTL0 0xA008
#define SMX_DC_CTL0 0xA020
#define USE_HASH_FUNCTION (1 << 0)
#define CACHE_DEPTH(x) ((x) << 1)
@@ -307,6 +308,8 @@
#define TCP_CNTL 0x9610
#define TCP_CHAN_STEER 0x9614
+#define VC_ENHANCE 0x9714
+
#define VGT_CACHE_INVALIDATION 0x88C4
#define CACHE_INVALIDATION(x) ((x)<<0)
#define VC_ONLY 0
diff -urN msm-3.4.2/drivers/gpu/drm/sis/sis_drv.c msm-3.4.4/drivers/gpu/drm/sis/sis_drv.c
--- msm-3.4.2/drivers/gpu/drm/sis/sis_drv.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/sis/sis_drv.c 2012-06-23 03:37:50.000000000 +0900
@@ -47,9 +47,9 @@
if (dev_priv == NULL)
return -ENOMEM;
+ idr_init(&dev_priv->object_idr);
dev->dev_private = (void *)dev_priv;
dev_priv->chipset = chipset;
- idr_init(&dev->object_name_idr);
return 0;
}
diff -urN msm-3.4.2/drivers/gpu/drm/ttm/ttm_bo.c msm-3.4.4/drivers/gpu/drm/ttm/ttm_bo.c
--- msm-3.4.2/drivers/gpu/drm/ttm/ttm_bo.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/ttm/ttm_bo.c 2012-06-23 03:37:50.000000000 +0900
@@ -1193,6 +1193,7 @@
(*destroy)(bo);
else
kfree(bo);
+ ttm_mem_global_free(mem_glob, acc_size);
return -EINVAL;
}
bo->destroy = destroy;
@@ -1294,22 +1295,14 @@
struct ttm_buffer_object **p_bo)
{
struct ttm_buffer_object *bo;
- struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
size_t acc_size;
int ret;
- acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
- ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
- if (unlikely(ret != 0))
- return ret;
-
bo = kzalloc(sizeof(*bo), GFP_KERNEL);
-
- if (unlikely(bo == NULL)) {
- ttm_mem_global_free(mem_glob, acc_size);
+ if (unlikely(bo == NULL))
return -ENOMEM;
- }
+ acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
buffer_start, interruptible,
persistent_swap_storage, acc_size, NULL);
diff -urN msm-3.4.2/drivers/gpu/drm/udl/udl_drv.c msm-3.4.4/drivers/gpu/drm/udl/udl_drv.c
--- msm-3.4.2/drivers/gpu/drm/udl/udl_drv.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/udl/udl_drv.c 2012-06-23 03:37:50.000000000 +0900
@@ -13,8 +13,21 @@
static struct drm_driver driver;
+/*
+ * There are many DisplayLink-based graphics products, all with unique PIDs.
+ * So we match on DisplayLink's VID + Vendor-Defined Interface Class (0xff)
+ * We also require a match on SubClass (0x00) and Protocol (0x00),
+ * which is compatible with all known USB 2.0 era graphics chips and firmware,
+ * but allows DisplayLink to increment those for any future incompatible chips
+ */
static struct usb_device_id id_table[] = {
- {.idVendor = 0x17e9, .match_flags = USB_DEVICE_ID_MATCH_VENDOR,},
+ {.idVendor = 0x17e9, .bInterfaceClass = 0xff,
+ .bInterfaceSubClass = 0x00,
+ .bInterfaceProtocol = 0x00,
+ .match_flags = USB_DEVICE_ID_MATCH_VENDOR |
+ USB_DEVICE_ID_MATCH_INT_CLASS |
+ USB_DEVICE_ID_MATCH_INT_SUBCLASS |
+ USB_DEVICE_ID_MATCH_INT_PROTOCOL,},
{},
};
MODULE_DEVICE_TABLE(usb, id_table);
diff -urN msm-3.4.2/drivers/gpu/drm/via/via_map.c msm-3.4.4/drivers/gpu/drm/via/via_map.c
--- msm-3.4.2/drivers/gpu/drm/via/via_map.c 2012-06-10 00:36:33.000000000 +0900
+++ msm-3.4.4/drivers/gpu/drm/via/via_map.c 2012-06-23 03:37:50.000000000 +0900