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Considering combinational logic circuit (biparted graph) as adjacent list and enumerate all the paths from input to output.
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Visualise gate-level verilog code as a directed graph.
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Networkx library was used to draw the graphs
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Input: Verilog file with Gate Level Modelling
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Output: All paths from input to output of the circuit enumerated by the Verilog file and the exported graph
- Networkx // for graph algorithms
- Python
- Verilog
python3 main.py --verbose VERBOSE <path-to-verilog-file>
Enumerated paths and graphical representation of Full Adder
Enumerated paths and graphical representation of 4x1 Multiplexer
