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data-center-rdimm-ddr5-tester.kicad_pro
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data-center-rdimm-ddr5-tester.kicad_pro
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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
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"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 0.8,
"width": 0.4
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 0.7,
"silk_text_size_v": 0.7,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.19999999999999998
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "ignore",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "warning",
"shorting_items": "error",
"silk_edge_clearance": "ignore",
"silk_over_copper": "ignore",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"solder_mask_bridge": "ignore",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "ignore",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "ignore",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
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"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.09999999999999999,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.19,
"min_hole_clearance": 0.19,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.6,
"min_text_thickness": 0.09,
"min_through_hole_diameter": 0.09999999999999999,
"min_track_width": 0.09999999999999999,
"min_via_annular_width": 0.125,
"min_via_diameter": 0.44999999999999996,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
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"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
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"td_target_name": "td_round_shape",
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},
{
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"td_target_name": "td_rect_shape",
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},
{
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"td_target_name": "td_track_end",
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}
],
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],
"via_dimensions": [
{
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"drill": 0.0
},
{
"diameter": 0.45,
"drill": 0.1
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
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"net_not_bus_member|1638300|1866900|7e581d28-eb4c-444e-adad-1c8f69f81e68|99179502-6fa8-4b96-b057-fd98beb4715e|/1faa6543-e26a-4449-8bac-ee14b9f19e5f/e98c799f-d02e-47b6-ad5c-871bd722b830||",
"net_not_bus_member|1638300|1905000|f0d87f45-2340-45ab-90e3-ecdbbf59ae33|99179502-6fa8-4b96-b057-fd98beb4715e|/1faa6543-e26a-4449-8bac-ee14b9f19e5f/e98c799f-d02e-47b6-ad5c-871bd722b830||",
"net_not_bus_member|1638300|1930400|c6ef9503-ae48-4f6f-a252-fffb98b9dcc0|816464f2-36a0-43b2-a8df-d10cf89a6833|/1faa6543-e26a-4449-8bac-ee14b9f19e5f/e98c799f-d02e-47b6-ad5c-871bd722b830||",
"net_not_bus_member|1638300|1968500|e57379ec-2bbd-4caa-aeef-a8191a83a5fa|c62c8fa6-3b13-43c3-b4f6-2bd0fad03262|/1faa6543-e26a-4449-8bac-ee14b9f19e5f/e98c799f-d02e-47b6-ad5c-871bd722b830||",
"net_not_bus_member|1638300|1993900|382f3b9a-d8fe-4b87-87a9-9ee93168e5c5|c62c8fa6-3b13-43c3-b4f6-2bd0fad03262|/1faa6543-e26a-4449-8bac-ee14b9f19e5f/e98c799f-d02e-47b6-ad5c-871bd722b830||",
"pin_not_driven|762000|1003300|e83f95ad-3979-42dc-94ca-5d149f8262fa|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1028700|a4f62b2b-b24f-4629-baa6-4e5294737c40|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1054100|4714d44e-5dd7-440b-9faf-26a3c8517dee|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1079500|ad5ca1a2-547f-4c39-9e18-5971c9c9a8a6|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1104900|364907e7-04f9-4228-8ee6-c5da581e7e98|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1130300|d5376db2-de73-46d0-9456-348ae51bdce1|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1155700|aebe3eee-1d51-4a1b-bb24-34d08d022a67|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1181100|4c74151f-1886-449f-bda8-0f981015dfd5|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1778000|2e8fd697-4a18-458d-b963-358f76d96e60|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1803400|dc756b92-e954-4c1c-9a62-317a73dea10f|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1828800|6d9bfa0a-697d-4620-9b21-81abd18ceba0|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1854200|964f20a1-4872-48ec-96bc-0e09e6780b05|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1879600|82c4a4b0-a9ec-4b26-abe1-2c6e437b5edc|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1905000|dd08429e-3418-4114-8deb-bb447b2f9739|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1930400|b70d6ac3-c0f3-4c3b-b7a1-adf547e7cf64|00000000-0000-0000-0000-000000000000|||",
"pin_not_driven|762000|1955800|0185e2d8-bda1-4f7b-b911-a64e72e3558e|00000000-0000-0000-0000-000000000000|||"
],
"meta": {
"version": 0
},
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[
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]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "ignore",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "ignore",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "ignore",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "data-center-rdimm-ddr5-tester.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.1,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "100Ohm-diff",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.1,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "12V",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.1,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "40Ohm-se_DQ",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.1,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "50Ohm-se",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.1,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "80Ohm-diff_DQS",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.1,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "85Ohm-diff_PCIe",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
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"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
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"microvia_diameter": 0.3,
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"name": "90Ohm-diff",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.1,
"via_diameter": 0.45,
"via_drill": 0.1,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.1,
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"diff_pair_width": 0.2,
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"name": "Supply",
"pcb_color": "rgba(0, 0, 0, 0.000)",
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"via_diameter": 0.45,
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"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
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"name": "tunning",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
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}
],
"meta": {
"version": 3
},
"net_colors": {
"GND": "rgb(0, 0, 255)"
},
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH1_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH1_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH2_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH2_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH3_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH3_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH4_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/Ethernet/ETH4_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 12/HyperRAM.CK_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 12/HyperRAM.CK_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.CLK_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.CLK_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.D0_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.D0_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.D1_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.D1_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.D2_N"
},
{
"netclass": "100Ohm-diff",
"pattern": "/FPGA bank 16/HDMI.D2_P"
},
{
"netclass": "100Ohm-diff",
"pattern": "/HDMI + SD Card/HDMI_OUT_CONN*"
},
{
"netclass": "12V",
"pattern": "/Supply/12V_PCIE_fused"
},
{
"netclass": "12V",
"pattern": "/Supply/12V_aux"
},
{
"netclass": "12V",
"pattern": "/Supply/12V_aux_fused"
},
{
"netclass": "12V",
"pattern": "VDC"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.MDC"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.MDIO"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.REF_CLK"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.RXC"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.RXD0"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.RXD1"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.RXD2"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.RXD3"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.RX_CTL"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.TXC"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.TXD0"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.TXD1"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.TXD2"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.TXD3"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.TX_CTL"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.~{INT}"
},
{
"netclass": "50Ohm-se",
"pattern": "/Ethernet/ETH.~{RESET}"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA Config/FLASH.IO0"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA Config/FLASH.IO1"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA Config/FLASH.IO2"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA Config/FLASH.IO3"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA Config/FLASH.SCK"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA Config/FLASH.~{CS}"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ0"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ1"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ2"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ3"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ4"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ5"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ6"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.DQ7"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.RWDS"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.~{CS}"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 12/HyperRAM.~{RESET}"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/GCLK100"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/SD.CD"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/SD.CLK"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/SD.CMD"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/SD.DAT0"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/SD.DAT1"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/SD.DAT2"
},
{
"netclass": "50Ohm-se",
"pattern": "/FPGA bank 16/SD.DAT3"
},
{
"netclass": "50Ohm-se",
"pattern": "/HyperRAM + QSPI Flash/IO0"
},
{
"netclass": "50Ohm-se",
"pattern": "/HyperRAM + QSPI Flash/IO1"
},
{
"netclass": "50Ohm-se",
"pattern": "/HyperRAM + QSPI Flash/IO2"
},
{
"netclass": "50Ohm-se",
"pattern": "/HyperRAM + QSPI Flash/IO3"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTR_REFCLK0_N"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTR_REFCLK0_P"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX0_N"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX0_P"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX1_N"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX1_P"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX2_N"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX2_P"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX3_N"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/GTX_TX3_P"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/PCIE.CLK_N"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/PCIE.CLK_P"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/PCIE.RXD0_N"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/PCIE.RXD0_P"
},
{
"netclass": "85Ohm-diff_PCIe",
"pattern": "/FPGA MGT Interface/PCIE.RXD1_N"
},
{
"netclass": "85Ohm-diff_PCIe",