From fd6bf7635ed968d601b4bd48e5cb55c86d64b6bd Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Tue, 16 Jul 2024 17:06:44 +0000
Subject: [PATCH 1/3] Update version to 9.2.111 [ci skip]

---
 pyvex/__init__.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pyvex/__init__.py b/pyvex/__init__.py
index 8b958a01..1fbfd371 100644
--- a/pyvex/__init__.py
+++ b/pyvex/__init__.py
@@ -3,7 +3,7 @@
 For an introduction to VEX, take a look here: https://docs.angr.io/advanced-topics/ir
 """
 
-__version__ = "9.2.111.dev0"
+__version__ = "9.2.111"
 
 from . import const, expr, stmt
 from .arches import (

From 73be02b37d4e07e936d867a4d2bef2c27b833ca8 Mon Sep 17 00:00:00 2001
From: shay margolis <shay@inbar.co.il>
Date: Tue, 16 Jul 2024 21:46:08 +0300
Subject: [PATCH 2/3] pyvex: Add TILEGX to arches

---
 pyvex/__init__.py       | 2 ++
 pyvex/arches.py         | 3 +++
 pyvex/lifting/libvex.py | 1 +
 3 files changed, 6 insertions(+)

diff --git a/pyvex/__init__.py b/pyvex/__init__.py
index 1fbfd371..18997cff 100644
--- a/pyvex/__init__.py
+++ b/pyvex/__init__.py
@@ -23,6 +23,7 @@
     ARCH_RISCV64_LE,
     ARCH_S390X,
     ARCH_X86,
+    ARCH_TILEGX,
 )
 from .block import IRSB, IRTypeEnv
 from .const import get_type_size, get_type_spec_size, tag_to_const_class
@@ -89,4 +90,5 @@
     "ARCH_MIPS64_BE",
     "ARCH_MIPS64_LE",
     "ARCH_RISCV64_LE",
+    "ARCH_TILEGX",
 ]
diff --git a/pyvex/arches.py b/pyvex/arches.py
index 79bf50e5..b67a7c1f 100644
--- a/pyvex/arches.py
+++ b/pyvex/arches.py
@@ -28,6 +28,7 @@ def __init__(self, name: str, bits: int, memory_endness: str, instruction_endnes
             "MIPS32": "VexArchMIPS32",
             "MIPS64": "VexArchMIPS64",
             "RISCV64": "VexArchRISCV64",
+            "TILEGX": "VexArchTILEGX",
         }[name]
         self.ip_offset = guest_offsets[
             (
@@ -43,6 +44,7 @@ def __init__(self, name: str, bits: int, memory_endness: str, instruction_endnes
                     "MIPS32": "pc",
                     "MIPS64": "pc",
                     "RISCV64": "pc",
+                    "TILEGX": "pc",
                 }[name],
             )
         ]
@@ -92,3 +94,4 @@ def get_register_offset(self, name: str) -> int:
 ARCH_MIPS64_BE = PyvexArch("MIPS64", 64, "Iend_BE")
 ARCH_MIPS64_LE = PyvexArch("MIPS64", 64, "Iend_LE")
 ARCH_RISCV64_LE = PyvexArch("RISCV64", 64, "Iend_LE", instruction_endness="Iend_LE")
+ARCH_TILEGX = PyvexArch("TILEGX", 64, "Iend_LE")
diff --git a/pyvex/lifting/libvex.py b/pyvex/lifting/libvex.py
index 52329483..104026ab 100644
--- a/pyvex/lifting/libvex.py
+++ b/pyvex/lifting/libvex.py
@@ -26,6 +26,7 @@
     "PPC64",
     "S390X",
     "RISCV64",
+    "TILEGX"
 }
 
 VEX_MAX_INSTRUCTIONS = 99

From d06588c2bc5f8de7237ecfa527ef3d35ab552dd0 Mon Sep 17 00:00:00 2001
From: shay margolis <shay@inbar.co.il>
Date: Tue, 16 Jul 2024 21:46:40 +0300
Subject: [PATCH 3/3] pyvex_c: Allow VexArchTILEGX lifting

---
 pyvex_c/pyvex.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/pyvex_c/pyvex.c b/pyvex_c/pyvex.c
index caf6d554..4a6f0649 100644
--- a/pyvex_c/pyvex.c
+++ b/pyvex_c/pyvex.c
@@ -279,6 +279,9 @@ static void vex_prepare_vai(VexArch arch, VexArchInfo *vai) {
 		case VexArchRISCV64:
 			vai->hwcaps = 0;
 			break;
+		case VexArchTILEGX:
+			vai->hwcaps = 0;
+			break;
 		default:
 			pyvex_error("Invalid arch in vex_prepare_vai.\n");
 			break;