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PlutoSDR not working after external clock #92

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Argonghost opened this issue Nov 26, 2023 · 19 comments
Open

PlutoSDR not working after external clock #92

Argonghost opened this issue Nov 26, 2023 · 19 comments

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@Argonghost
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Argonghost commented Nov 26, 2023 •
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Hi @mhennerich @tfcollins
I have a similar problem to the one in this thread. When i tried to use an external GPS clock with 40MHz output, and injected it to the pluto's CLK_IN and changed the xo_correction setting in the config.txt as per the instructions in link above, i now get this persisting error in PyADI:

Traceback (most recent call last):
  File "/home/argonghost/Desktop/new.py", line 8, in <module>
    sdr = adi.ad9361(uri)
  File "/home/argonghost/.local/lib/python3.10/site-packages/adi/rx_tx.py", line 718, in __init__
    rx_def.__init__(self, *args, **kwargs)
  File "/home/argonghost/.local/lib/python3.10/site-packages/adi/rx_tx.py", line 637, in __init__
    shared_def.__init__(self, *args, **kwargs)
  File "/home/argonghost/.local/lib/python3.10/site-packages/adi/rx_tx.py", line 605, in __init__
    raise Exception(
Exception: No device found with name ad9361-phy

the pluto was working perfectly fine before. How can i reset back to factory settings ? also, what is the correct way to properly introduce external clock

Originally posted by @Argonghost in #50 (comment)
@mhennerich
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How can i reset back to factory settings ? also, what is the correct way to properly introduce external clock

Copy the plutosdr-fw-v0.38.zip as is onto the mass storage drive. Don't unzip it, etc.
This will reset to the default environment.

Regarding external clock please see here: https://wiki.analog.com/university/tools/pluto/devs/booting#examples

@Argonghost
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hi @mhennerich

So when i set refclk_source back to "internal" everything works fine and no issues in PyADI. However, when i try to follow the instructions in https://wiki.analog.com/university/tools/pluto/devs/booting#examples I still get the error:

Traceback (most recent call last):
  File "/home/argonghost/Desktop/new.py", line 8, in <module>
    sdr = adi.ad9361(uri)
  File "/home/argonghost/.local/lib/python3.10/site-packages/adi/rx_tx.py", line 718, in __init__
    rx_def.__init__(self, *args, **kwargs)
  File "/home/argonghost/.local/lib/python3.10/site-packages/adi/rx_tx.py", line 637, in __init__
    shared_def.__init__(self, *args, **kwargs)
  File "/home/argonghost/.local/lib/python3.10/site-packages/adi/rx_tx.py", line 605, in __init__
    raise Exception(
Exception: No device found with name ad9361-phy

I've seen in the AD wiki pages that issues regarding external GPS clocks have been addresses and solved before, but the threads were more in depth (regardin GPIO's and and device tree etc).

can you please help me

thanks

@tfcollins
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Please SSH to Pluto and run the command dmesg. Paste the output here

@Argonghost
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Hi @tfcollins @mhennerich

This is the output i get:

# dmesg
Booting Linux on physical CPU 0x0
Linux version 5.15.0-175882-ge14e351533f9 (michael@mhenneri-D06) (arm-linux-gnueabihf-gcc (Linaro GCC 7.3-2018.05) 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701], GNU ld (Linaro_Binutils-2018.05) 2.28.2.20170706) #1 SMP PREEMPT Fri Nov 17 10:23:58 CET 2023
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Analog Devices PlutoSDR Rev.C (Z7010/AD9363)
Memory policy: Data cache writealloc
cma: Reserved 256 MiB at 0x0e400000
Zone ranges:
  Normal   [mem 0x0000000000000000-0x000000001fffffff]
  HighMem  empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x000000001fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
percpu: Embedded 11 pages/cpu s13772 r8192 d23092 u45056
pcpu-alloc: s13772 r8192 d23092 u45056 alloc=11*4096
pcpu-alloc: [0] 0 [0] 1 
Built 1 zonelists, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyPS0,115200 maxcpus=1 rootfstype=ramfs root=/dev/ram0 rw quiet loglevel=4 clk_ignore_unused uboot=U-Boot PlutoSDR v0.20-PlutoSDR-00055-g469a0fd (Jul 06 2020 - 16:01:30 +0200)
Unknown command line parameters: PlutoSDR (Jul 06 2020 - 16:01:30 +0200) uboot=U-Boot
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 238896K/524288K available (6144K kernel code, 659K rwdata, 2012K rodata, 1024K init, 141K bss, 23248K reserved, 262144K cma-reserved, 0K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu: 	RCU event tracing is enabled.
rcu: 	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
	Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x384/0x618 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 166MHz, resolution 6ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x26703d7dd8, max_idle_ns: 440795208065 ns
Switching to timer-based delay loop, resolution 6ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=25
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 333.33 BogoMIPS (lpj=1666666)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated (333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered PF_NETLINK/PF_ROUTE protocol family
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor ladder
amba f8801000.etb: Fixing up cyclic dependency with replicator
amba f8803000.tpiu: Fixing up cyclic dependency with replicator
amba f8804000.funnel: Fixing up cyclic dependency with replicator
amba f889c000.ptm: Fixing up cyclic dependency with f8804000.funnel
amba f889d000.ptm: Fixing up cyclic dependency with f8804000.funnel
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
xuartps e0001000.serial: No serial alias passed. Using the first free id
xuartps e0001000.serial: Checking id 0
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 32, base_baud = 6249999) is a xuartps
printk: console [ttyPS0] enabled
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]>
PTP clock support registered
FPGA manager framework
clocksource: Switched to clocksource arm_global_timer
NET: Registered PF_INET protocol family
IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes, linear)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
NET: Registered PF_UNIX/PF_LOCAL protocol family
armv7-pmu f8891000.pmu: hw perfevents: no interrupt-affinity property, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
Initialise system trusted keyrings
workingset: timestamp_bits=30 max_order=17 bucket_order=0
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
Key type asymmetric registered
Asymmetric key parser 'x509' registered
io scheduler mq-deadline registered
io scheduler kyber registered
Trying to unpack rootfs image as initramfs...
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
gpio-954 (clock_internal_en): hogged as output/low
brd: module loaded
loop: module loaded
spi-nor spi2.0: SPI-NOR-UniqueID 10447376de0b0007e8ff2000395599724c
spi-nor spi2.0: n25q256ax1 (32768 Kbytes)
4 fixed-partitions partitions found on MTD device spi2.0
Creating 4 MTD partitions on "spi2.0":
0x000000000000-0x000000100000 : "qspi-fsbl-uboot"
0x000000100000-0x000000120000 : "qspi-uboot-env"
0x000000120000-0x000000200000 : "qspi-nvmfs"
0x000000200000-0x000002000000 : "qspi-linux"
libphy: Fixed MDIO Bus: probed
usbcore: registered new interface driver rt2500usb
usbcore: registered new interface driver rt73usb
usbcore: registered new interface driver rt2800usb
usbcore: registered new interface driver rtl8187
usbcore: registered new interface driver rtl8192cu
usbcore: registered new interface driver rtl8xxxu
usbcore: registered new interface driver r8152
usbcore: registered new interface driver lan78xx
usbcore: registered new interface driver asix
usbcore: registered new interface driver ax88179_178a
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver dm9601
usbcore: registered new interface driver smsc75xx
usbcore: registered new interface driver smsc95xx
usbcore: registered new interface driver rndis_host
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
Freeing initrd memory: 6492K
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
i2c_dev: i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Xilinx Zynq CpuIdle Driver started
ledtrig-cpu: registered to indicate activity on CPUs
hid: raw HID events driver (C) Jiri Kosina
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
usbcore: registered new interface driver r8712u
usbcore: registered new interface driver r8188eu
ad9361 spi0.0: ad9361_probe : enter (ad9361)
random: fast init done
ad9361 spi0.0: ad9361_probe : AD936x Rev 0 successfully initialized
cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x79024000 mapped to 0x(ptrval), probed DDS AD9361
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered PF_PACKET protocol family
lib80211: common routines for IEEE802.11 drivers
lib80211_crypt: registered algorithm 'NULL'
lib80211_crypt: registered algorithm 'WEP'
lib80211_crypt: registered algorithm 'CCMP'
Registering SWP/SWPB emulation handler
Loading compiled-in X.509 certificates
cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (10.03.) at 0x79020000 mapped to 0x(ptrval) probed ADC AD9361 as MASTER
adi_iio_fakedev amba:iio_axi_tdd_0@0: Faking 35 attributes from 7c440000.axi-tdd-0
input: gpio_keys as /devices/soc0/gpio_keys/input/input0
cfg80211: Loading compiled-in X.509 certificates for regulatory database
cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
cfg80211: failed to load regulatory.db
clk: Not disabling unused clocks
Freeing unused kernel image (initmem) memory: 1024K
Run /init as init process
  with arguments:
    /init
    PlutoSDR
    (Jul
    06
    2020
    -
    16:01:30
    +0200)
  with environment:
    HOME=/
    TERM=linux
    uboot=U-Boot
file system registered
using random self ethernet address
using random host ethernet address
Mass Storage Function, version: 2009/09/11
LUN: removable file: (no medium)
read descriptors
read strings
usb0: HOST MAC 00:e0:22:b0:c5:46
usb0: MAC 00:05:f7:3e:c1:93
random: dbus-uuidgen: uninitialized urandom read (12 bytes read)
random: dbus-uuidgen: uninitialized urandom read (8 bytes read)
random: dbus-daemon: uninitialized urandom read (12 bytes read)
random: crng init done
random: 1 urandom warning(s) missed due to ratelimiting
loop7: detected capacity change from 0 to 61440
#

when running my code in PyADI after setting external refclk i still get the error i mentioned earlier :(

@tfcollins
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Transceiver looks fine. Can you do 2 things.

  1. Verify the URI is correct. Which one are you using?
  2. Provide the output of this command:
iio_attr -u <uri of device> -d

@Argonghost
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@tfcollins

iio_attr -u 192.168.2.1 -d
Unable to create IIO context 192.168.2.1: Function not implemented (38)

@Argonghost
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@tfcollins

since everything works perfectly fine when redefine refclk_source to be internal , could it be possible that this is due to the pluto not receiving external clock input to be with?

Because im using the Leo Bodnar GPS external clock, and from i what naively know it only starts to output square waves when there's a PLL lock with a satellite. and as per the current status of the clock now , this is what i get :

9E1F0B95ED /dev/hidraw1: SAT unlocked PLL locked Loss: 1

implying that there is not satellite lock and whence no square wave output of 40 MHz. is it possible that cold boot of the this type of clock itself takes time?

@mhennerich
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Was the dmesg with internal or external clock?

@Argonghost
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@mhennerich this is the output with external clock:

Booting Linux on physical CPU 0x0
Linux version 5.15.0-175882-ge14e351533f9 (michael@mhenneri-D06) (arm-linux-gnueabihf-gcc (Linaro GCC 7.3-2018.05) 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701], GNU ld (Linaro_Binutils-2018.05) 2.28.2.20170706) #1 SMP PREEMPT Fri Nov 17 10:23:58 CET 2023
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Analog Devices PlutoSDR Rev.C (Z7010/AD9363)
Memory policy: Data cache writealloc
cma: Reserved 256 MiB at 0x0e400000
Zone ranges:
  Normal   [mem 0x0000000000000000-0x000000001fffffff]
  HighMem  empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000000000-0x000000001fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]
percpu: Embedded 11 pages/cpu s13772 r8192 d23092 u45056
pcpu-alloc: s13772 r8192 d23092 u45056 alloc=11*4096
pcpu-alloc: [0] 0 [0] 1 
Built 1 zonelists, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyPS0,115200 maxcpus=1 rootfstype=ramfs root=/dev/ram0 rw quiet loglevel=4 clk_ignore_unused uboot=U-Boot PlutoSDR v0.20-PlutoSDR-00055-g469a0fd (Jul 06 2020 - 16:01:30 +0200)
Unknown command line parameters: PlutoSDR (Jul 06 2020 - 16:01:30 +0200) uboot=U-Boot
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 238896K/524288K available (6144K kernel code, 659K rwdata, 2012K rodata, 1024K init, 141K bss, 23248K reserved, 262144K cma-reserved, 0K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu: 	RCU event tracing is enabled.
rcu: 	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
	Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x384/0x618 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 166MHz, resolution 6ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x26703d7dd8, max_idle_ns: 440795208065 ns
Switching to timer-based delay loop, resolution 6ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=25
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 333.33 BogoMIPS (lpj=1666666)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
smp: Brought up 1 node, 1 CPU
SMP: Total of 1 processors activated (333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered PF_NETLINK/PF_ROUTE protocol family
DMA: preallocated 256 KiB pool for atomic coherent allocations
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor ladder
amba f8801000.etb: Fixing up cyclic dependency with replicator
amba f8803000.tpiu: Fixing up cyclic dependency with replicator
amba f8804000.funnel: Fixing up cyclic dependency with replicator
amba f889c000.ptm: Fixing up cyclic dependency with f8804000.funnel
amba f889d000.ptm: Fixing up cyclic dependency with f8804000.funnel
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
xuartps e0001000.serial: No serial alias passed. Using the first free id
xuartps e0001000.serial: Checking id 0
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 32, base_baud = 6249999) is a xuartps
printk: console [ttyPS0] enabled
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]>
PTP clock support registered
FPGA manager framework
clocksource: Switched to clocksource arm_global_timer
NET: Registered PF_INET protocol family
IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes, linear)
TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes, linear)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
NET: Registered PF_UNIX/PF_LOCAL protocol family
armv7-pmu f8891000.pmu: hw perfevents: no interrupt-affinity property, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
Initialise system trusted keyrings
workingset: timestamp_bits=30 max_order=17 bucket_order=0
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
Key type asymmetric registered
Asymmetric key parser 'x509' registered
io scheduler mq-deadline registered
io scheduler kyber registered
Trying to unpack rootfs image as initramfs...
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
gpio-954 (clock_extern_en): hogged as output/high
brd: module loaded
loop: module loaded
spi-nor spi2.0: SPI-NOR-UniqueID 10447376de0b0007e8ff2000395599724c
spi-nor spi2.0: n25q256ax1 (32768 Kbytes)
4 fixed-partitions partitions found on MTD device spi2.0
Creating 4 MTD partitions on "spi2.0":
0x000000000000-0x000000100000 : "qspi-fsbl-uboot"
0x000000100000-0x000000120000 : "qspi-uboot-env"
0x000000120000-0x000000200000 : "qspi-nvmfs"
0x000000200000-0x000002000000 : "qspi-linux"
libphy: Fixed MDIO Bus: probed
usbcore: registered new interface driver rt2500usb
usbcore: registered new interface driver rt73usb
usbcore: registered new interface driver rt2800usb
usbcore: registered new interface driver rtl8187
usbcore: registered new interface driver rtl8192cu
usbcore: registered new interface driver rtl8xxxu
usbcore: registered new interface driver r8152
usbcore: registered new interface driver lan78xx
usbcore: registered new interface driver asix
usbcore: registered new interface driver ax88179_178a
usbcore: registered new interface driver cdc_ether
usbcore: registered new interface driver dm9601
usbcore: registered new interface driver smsc75xx
usbcore: registered new interface driver smsc95xx
usbcore: registered new interface driver rndis_host
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
usbcore: registered new interface driver usb-storage
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver ftdi_sio
usbserial: USB Serial support registered for FTDI USB Serial Device
Freeing initrd memory: 6492K
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
i2c_dev: i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s
Xilinx Zynq CpuIdle Driver started
ledtrig-cpu: registered to indicate activity on CPUs
hid: raw HID events driver (C) Jiri Kosina
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
usbcore: registered new interface driver r8712u
usbcore: registered new interface driver r8188eu
ad9361 spi0.0: ad9361_probe : enter (ad9361)
random: fast init done
ad9361 spi0.0: Calibration TIMEOUT (0x5E, 0x80)
random: crng init done
ad9361 spi0.0: Calibration TIMEOUT (0x244, 0x80)
ad9361: probe of spi0.0 failed with error -110
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered PF_PACKET protocol family
lib80211: common routines for IEEE802.11 drivers
lib80211_crypt: registered algorithm 'NULL'
lib80211_crypt: registered algorithm 'WEP'
lib80211_crypt: registered algorithm 'CCMP'
Registering SWP/SWPB emulation handler
Loading compiled-in X.509 certificates
input: gpio_keys as /devices/soc0/gpio_keys/input/input0
cfg80211: Loading compiled-in X.509 certificates for regulatory database
cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
cfg80211: failed to load regulatory.db
clk: Not disabling unused clocks
Freeing unused kernel image (initmem) memory: 1024K
Run /init as init process
  with arguments:
    /init
    PlutoSDR
    (Jul
    06
    2020
    -
    16:01:30
    +0200)
  with environment:
    HOME=/
    TERM=linux
    uboot=U-Boot
file system registered
using random self ethernet address
using random host ethernet address
Mass Storage Function, version: 2009/09/11
LUN: removable file: (no medium)
read descriptors
read strings
usb0: HOST MAC 00:e0:22:b0:c5:46
usb0: MAC 00:05:f7:3e:c1:93
loop7: detected capacity change from 0 to 61440
#

@mhennerich
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ad9361 spi0.0: ad9361_probe : enter (ad9361)
random: fast init done
ad9361 spi0.0: Calibration TIMEOUT (0x5E, 0x80)
random: crng init done
ad9361 spi0.0: Calibration TIMEOUT (0x244, 0x80)
ad9361: probe of spi0.0 failed with error -110

This means that the AD9361 device failed with error.
It's likely that the expected clock wasn't present or it was outside of technical specification.
This of course leads to the fact that you can't access this device from python afterwards...

@Argonghost
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@mhennerich

I also tried setting xo_correction to 40000000 in the config.txt file. According to https://ez.analog.com/adieducation/university-program/f/q-a/560517/pluto-rev-d-off-frequency-with-bodnar-external-reference-a-config-issue/465787 i shouldnt need to do that right?

@mhennerich
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When you switch from internal to external you also need to specify the external clock.
Did you do that?
Can you post #cat /sys/kernel/debug/clk/clk_summary of your external case?

@Argonghost
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@mhennerich

# cat /sys/kernel/debug/clk/clk_summary
                                 enable  prepare  protect                                duty         hardware
   clock                          count    count    count        rate   accuracy phase  cycle  nshot    enable
--------------------------------------------------------------------------------------------------------------
 spi0.0-tx_lo_dummy                   0        0        0  1225000000          0     0  50000        0
         Y
 spi0.0-rx_lo_dummy                   0        0        0  1200000000          0     0  50000        0
         Y
 ad9364_ext_refclk                    4        4        0    40000000     200000     0  50000        0
         Y
    spi0.0-bb_refclk                  1        1        0    40000000     200000     0  50000        0
         Y
       spi0.0-bbpll_clk               1        1        0  1280000000     200000     0  50000        0
         Y
          spi0.0-adc_clk              1        1        0   640000000     200000     0  50000        0
         Y
             spi0.0-dac_clk           1        1        0   320000000     200000     0  50000        0
         Y
                spi0.0-t2_clk         1        1        0   160000000     200000     0  50000        0
         Y
                   spi0.0-t1_clk       1        1        0    80000000     200000     0  50000        0
         Y
                      spi0.0-clktf_clk       1        1        0    80000000     200000     0  50000        0
         Y
                         spi0.0-tx_sampl_clk       2        2        0    20000000     200000     0  50000        0
         Y
                            spi0.0-pl_intf_clk       1        1        0    40000000     200000     0  50000        0
         Y
             spi0.0-r2_clk            0        0        0   320000000     200000     0  50000        0
         Y
                spi0.0-r1_clk         0        0        0   160000000     200000     0  50000        0
         Y
                   spi0.0-clkrf_clk       0        0        0    80000000     200000     0  50000        0
         Y
                      spi0.0-rx_sampl_clk       0        0        0    20000000     200000     0  50000        0
         Y
    spi0.0-rx_refclk                  1        1        0    80000000     200000     0  50000        0
         Y
       spi0.0-rx_rfpll_int            1        1        0   787709999     200000     0  50000        0
         Y
          spi0.0-rx_rfpll             1        1        0   787709999     200000     0  50000        0
         Y
    spi0.0-tx_refclk                  1        1        0    80000000     200000     0  50000        0
         Y
       spi0.0-tx_rfpll_int            1        1        0  1225000000     200000     0  50000        0
         Y
          spi0.0-tx_rfpll             1        1        0  1225000000     200000     0  50000        0
         Y
 ps_clk                               3        3        0    33333333          0     0  50000        0
         Y
    iopll_int                         1        1        0   999999990          0     0  50000        0
         Y
       iopll                          9        9        0   999999990          0     0  50000        0
         Y
          dbg_mux                     1        1        0   999999990          0     0  50000        0
         Y
             dbg_div                  1        1        0    66666666          0     0  50000        0
         Y
                dbg_emio_mux          1        1        0    66666666          0     0  50000        0
         Y
                   dbg_trc            1        1        0    66666666          0     0  50000        0
         Y
          can_mux                     0        0        0   999999990          0     0  50000        0
         Y
             can_div0                 0        0        0    40000000          0     0  50000        0
         Y
                can_div1              0        0        0     8000000          0     0  50000        0
         Y
                   can1_gate          0        0        0     8000000          0     0  50000        0
         Y
                      can1            0        0        0     8000000          0     0  50000        0
         Y
                   can0_gate          0        0        0     8000000          0     0  50000        0
         Y
                      can0            0        0        0     8000000          0     0  50000        0
         Y
          gem1_mux                    0        0        0   999999990          0     0  50000        0
         Y
             gem1_div0                0        0        0    16666667          0     0  50000        0
         Y
                gem1_div1             0        0        0    16666667          0     0  50000        0
         Y
                   gem1_emio_mux       0        0        0    16666667          0     0  50000        0
         Y
                      gem1            0        0        0    16666667          0     0  50000        0
         Y
          gem0_mux                    0        0        0   999999990          0     0  50000        0
         Y
             gem0_div0                0        0        0    16666667          0     0  50000        0
         Y
                gem0_div1             0        0        0    16666667          0     0  50000        0
         Y
                   gem0_emio_mux       0        0        0    16666667          0     0  50000        0
         Y
                      gem0            0        0        0    16666667          0     0  50000        0
         Y
          spi0_mux                    1        1        0   999999990          0     0  50000        0
         Y
             spi0_div                 1        1        0   166666665          0     0  50000        0
         Y
                spi1                  0        0        0   166666665          0     0  50000        0
         N
                spi0                  1        1        0   166666665          0     0  50000        0
         Y
          uart0_mux                   1        1        0   999999990          0     0  50000        0
         Y
             uart0_div                1        1        0    99999999          0     0  50000        0
         Y
                uart1                 1        1        0    99999999          0     0  50000        0
         Y
                uart0                 0        0        0    99999999          0     0  50000        0
         N
          sdio0_mux                   0        0        0   999999990          0     0  50000        0
         Y
             sdio0_div                0        0        0    33333333          0     0  50000        0
         Y
                sdio1                 0        0        0    33333333          0     0  50000        0
         Y
                sdio0                 0        0        0    33333333          0     0  50000        0
         Y
          pcap_mux                    1        1        0   999999990          0     0  50000        0
         Y
             pcap_div                 1        1        0   199999998          0     0  50000        0
         Y
                pcap                  1        2        0   199999998          0     0  50000        0
         Y
          lqspi_mux                   1        1        0   999999990          0     0  50000        0
         Y
             lqspi_div                1        1        0   199999998          0     0  50000        0
         Y
                lqspi                 1        1        0   199999998          0     0  50000        0
         Y
          fclk3_mux                   1        1        0   999999990          0     0  50000        0
         Y
             fclk3_div0               1        1        0    41666667          0     0  50000        0
         Y
                fclk3_div1            1        1        0    41666667          0     0  50000        0
         Y
                   fclk3              1        1        0    41666667          0     0  50000        0
         Y
          fclk2_mux                   1        1        0   999999990          0     0  50000        0
         Y
             fclk2_div0               1        1        0    41666667          0     0  50000        0
         Y
                fclk2_div1            1        1        0    41666667          0     0  50000        0
         Y
                   fclk2              1        1        0    41666667          0     0  50000        0
         Y
          fclk1_mux                   1        1        0   999999990          0     0  50000        0
         Y
             fclk1_div0               1        1        0   199999998          0     0  50000        0
         Y
                fclk1_div1            1        1        0   199999998          0     0  50000        0
         Y
                   fclk1              3        3        0   199999998          0     0  50000        0
         Y
          fclk0_mux                   1        1        0   999999990          0     0  50000        0
         Y
             fclk0_div0               1        1        0   199999998          0     0  50000        0
         Y
                fclk0_div1            1        1        0    99999999          0     0  50000        0
         Y
                   fclk0              2        3        0    99999999          0     0  50000        0
         Y
    ddrpll_int                        1        1        0  1066666656          0     0  50000        0
         Y
       ddrpll                         3        3        0  1066666656          0     0  50000        0
         Y
          dci_div0                    1        1        0    71111111          0     0  50000        0
         Y
             dci_div1                 1        1        0    10158731          0     0  50000        0
         Y
                dci                   1        1        0    10158731          0     0  50000        0
         Y
          ddr3x_div                   1        1        0   533333328          0     0  50000        0
         Y
             ddr3x                    1        1        0   533333328          0     0  50000        0
         Y
          ddr2x_div                   1        1        0   355555552          0     0  50000        0
         Y
             ddr2x                    1        1        0   355555552          0     0  50000        0
         Y
    armpll_int                        1        1        0  1333333320          0     0  50000        0
         Y
       armpll                         1        1        0  1333333320          0     0  50000        0
         Y
          smc_mux                     0        0        0  1333333320          0     0  50000        0
         Y
             smc_div                  0        0        0    22222222          0     0  50000        0
         Y
                smc                   0        0        0    22222222          0     0  50000        0
         Y
          cpu_mux                     1        1        0  1333333320          0     0  50000        0
         Y
             cpu_div                  3        3        0   666666660          0     0  50000        0
         Y
                cpu_1x_div            1        1        0   111111110          0     0  50000        0
         Y
                   cpu_1x             9        9        0   111111110          0     0  50000        0
         Y
                      smc_aper        0        0        0   111111110          0     0  50000        0
         Y
                      lqspi_aper       1        1        0   111111110          0     0  50000        0
         Y
                      gpio_aper       1        1        0   111111110          0     0  50000        0
         Y
                      uart1_aper       1        1        0   111111110          0     0  50000        0
         Y
                      uart0_aper       0        0        0   111111110          0     0  50000        0
         N
                      i2c1_aper       0        0        0   111111110          0     0  50000        0
         Y
                      i2c0_aper       0        0        0   111111110          0     0  50000        0
         Y
                      can1_aper       0        0        0   111111110          0     0  50000        0
         N
                      can0_aper       0        0        0   111111110          0     0  50000        0
         N
                      spi1_aper       0        0        0   111111110          0     0  50000        0
         N
                      spi0_aper       1        1        0   111111110          0     0  50000        0
         Y
                      sdio1_aper       0        0        0   111111110          0     0  50000        0
         N
                      sdio0_aper       0        0        0   111111110          0     0  50000        0
         N
                      gem1_aper       0        0        0   111111110          0     0  50000        0
         N
                      gem0_aper       0        0        0   111111110          0     0  50000        0
         N
                      usb1_aper       0        0        0   111111110          0     0  50000        0
         Y
                      usb0_aper       1        1        0   111111110          0     0  50000        0
         Y
                      dbg_apb         1        1        0   111111110          0     0  50000        0
         Y
                      swdt            1        1        0   111111110          0     0  50000        0
         Y
                cpu_2x_div            1        1        0   222222220          0     0  50000        0
         Y
                   cpu_2x             1        1        0   222222220          0     0  50000        0
         Y
                      dma             0        0        0   222222220          0     0  50000        0
         N
                cpu_3or2x_div         1        1        0   333333330          0     0  50000        0
         Y
                   cpu_3or2x          2        2        0   333333330          0     0  50000        0
         Y
                cpu_6or4x             0        0        0   666666660          0     0  50000        0
         Y
 can1_mio_mux                         0        0        0           0          0     0  50000        0
         Y
 can0_mio_mux                         0        0        0           0          0     0  50000        0
         Y
#

@mhennerich
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ad9364_ext_refclk 4 4 0 40000000 200000 0 50000 0

Ok that means that the device expects 40MHz did you measure the clock and made sure it's available when you start the unit?

@Argonghost
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@mhennerich

it just worked now. strangely,

i did fw_setenv attr_val ad9364 and now my PyADI script works perfectly fine even though the GPS clock doesn't seem to be locked into a satellite as per:

9E1F0B95ED  /dev/hidraw1: SAT unlocked  PLL locked    Loss: 1

is it because of AD9364 ???

@Argonghost
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When you switch from internal to external you also need to specify the external clock. Did you do that? Can you post #cat /sys/kernel/debug/clk/clk_summary of your external case?

What do you mean??? Do you mean the ext clock frequency in the config.txt file ???

@BloodSqueezer
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@tfcollins

iio_attr -u 192.168.2.1 -d
Unable to create IIO context 192.168.2.1: Function not implemented (38)

should be: iio_attr -u ip:192.168.2.1 -d

@tfcollins
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Its not required to set the device in AD9364 mode to use an external reference. However, you need to connect and power the reference before booting Pluto.

@BloodSqueezer
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BloodSqueezer commented Dec 2, 2023 •
edited
Loading

Its not required to set the device in AD9364 mode to use an external reference. However, you need to connect and power the reference before booting Pluto.

Phil Greenland advises against applying voltage to the external clock before turning on Pluto:
https://www.quantulum.co.uk/wp-content/uploads/2023/06/pluto_hardware_connection-768x639.webp

Here's what he wrote about it:
I thought for a moment that I’d killed the LTC6957HMS-3 clock buffer chip that the external clock input feeds. The PCB has a note that the external reference shouldn’t exceed 3.3v…which I dont believe I did. However reading on Analog’s forums it seems that the chip possibly shouldn’t have an input signal present when its supplies are off. I’ve done this quite a few times now 🙈.
I got concerned after seeing timeout errors in the kernel log as the device was booting. Upon further investigation there was no output on the clk_out UFL connection on the board, which is the second buffered output of the chip.
While flapping around online trying to find a replacement (gotta love the parts shortage), the chip seemingly recovered, presenting the clock output on the scope again. Lesson learnt, go real careful with the external clock input – it may be rather sensitive.

https://www.quantulum.co.uk/blog/private-lte-with-analog-adalm-pluto/

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@tfcollins @mhennerich @BloodSqueezer @Argonghost