From 69f61080d8859dc2868ef5216eb0baac6c9cc59f Mon Sep 17 00:00:00 2001 From: David Winter Date: Fri, 15 Oct 2021 14:23:06 +0200 Subject: [PATCH 1/2] Revert "data_offload: Fix oversized inputs in TX mode" This reverts commit 0e8f55b2d7947cfb8007f9b27251b898ddfc9886. --- library/data_offload/data_offload_fsm.v | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/library/data_offload/data_offload_fsm.v b/library/data_offload/data_offload_fsm.v index 6d9a3c8dbc..860f83c0b1 100644 --- a/library/data_offload/data_offload_fsm.v +++ b/library/data_offload/data_offload_fsm.v @@ -55,7 +55,7 @@ module data_offload_fsm #( output reg wr_resetn_out, input wr_valid_in, output wr_valid_out, - output reg wr_ready, + output wr_ready, output reg [WR_ADDRESS_WIDTH-1:0] wr_addr, input wr_last, input [WR_DATA_WIDTH/8-1:0] wr_tkeep, @@ -260,11 +260,12 @@ module data_offload_fsm #( always @(posedge wr_clk) begin wr_ready_d <= wr_ready; - // flush out the DMA if the transfer is bigger than the storage size - wr_ready <= ((wr_fsm_state == WR_WRITE_TO_MEM) || - ((wr_fsm_state == WR_WAIT_TO_END) && wr_ready_d && !(wr_valid_in && wr_last))) ? 1'b1 : 1'b0; end + // flush out the DMA if the transfer is bigger than the storage size + assign wr_ready = ((wr_fsm_state == WR_WRITE_TO_MEM) || + ((wr_fsm_state == WR_WAIT_TO_END) && wr_valid_in && wr_ready_d && wr_full)) ? 1'b1 : 1'b0; + // write control assign wr_valid_out = (wr_fsm_state == WR_WRITE_TO_MEM) & wr_valid_in; From 9053bb5f059f1937874a60e82d1f58f05dd883e7 Mon Sep 17 00:00:00 2001 From: David Winter Date: Fri, 15 Oct 2021 18:29:30 +0200 Subject: [PATCH 2/2] data_offload: Fix oversized TX input transactions Signed-off-by: David Winter --- library/data_offload/data_offload_fsm.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/data_offload/data_offload_fsm.v b/library/data_offload/data_offload_fsm.v index 860f83c0b1..87a258ab13 100644 --- a/library/data_offload/data_offload_fsm.v +++ b/library/data_offload/data_offload_fsm.v @@ -259,12 +259,12 @@ module data_offload_fsm #( end always @(posedge wr_clk) begin - wr_ready_d <= wr_ready; + wr_ready_d <= wr_ready && !(wr_valid_in && wr_last); end // flush out the DMA if the transfer is bigger than the storage size assign wr_ready = ((wr_fsm_state == WR_WRITE_TO_MEM) || - ((wr_fsm_state == WR_WAIT_TO_END) && wr_valid_in && wr_ready_d && wr_full)) ? 1'b1 : 1'b0; + (TX_OR_RXN_PATH && ((wr_fsm_state == WR_WAIT_TO_END) && wr_ready_d))) ? 1'b1 : 1'b0; // write control assign wr_valid_out = (wr_fsm_state == WR_WRITE_TO_MEM) & wr_valid_in;