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FunctionBuilder.cpp
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/* Copyright (c) 2014 Steven Flintham
*
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the 'Software'),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, provided that the above copyright notice(s) and this
* permission notice appear in all copies of the Software and that both the
* above copyright notice(s) and this permission notice appear in supporting
* documentation.
*
* THE SOFTWARE IS PROVIDED 'AS IS'. USE ENTIRELY AT YOUR OWN RISK.
*/
#include "FunctionBuilder.h"
// Throughout this file we must be careful to avoid incorrect wrap-around
// handling; for example, it's wrong to do memory[pc + 2] because if pc is
// 0xffff this will access off the end of memory. We must always use uint16_t
// intermediate values to get the right wrapping behaviour. Similar
// considerations apply when using zero-page addressing; we must ensure we wrap
// around at 0xff.
#include "config.h"
#include <algorithm>
#include <assert.h>
#include <iomanip>
#include "llvm/Analysis/Passes.h"
#include "llvm/ExecutionEngine/ExecutionEngine.h"
#include "llvm/ExecutionEngine/JIT.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/TypeBuilder.h"
#if defined HAVE_LLVM_ANALYSIS_VERIFIER_H
#include "llvm/Analysis/Verifier.h"
#elif defined HAVE_LLVM_IR_VERIFIER_H
#include "llvm/IR/Verifier.h"
#else
#error Need LLVM Verifier.h
#endif
#include "llvm/PassManager.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Scalar.h"
#include <sstream>
#include "AddressRange.h"
#include "const.h"
#include "Function.h"
#include "LLVMStuff.h"
#include "M6502Internal.h"
#include "Registers.h"
#include "util.h"
namespace llvm
{
template<bool xcompile>
class TypeBuilder<M6502, xcompile>
{
public:
static StructType *get(LLVMContext &context)
{
static StructType *t = StructType::create(context, "M6502");
return t;
}
};
template<bool xcompile>
class TypeBuilder<Registers, xcompile>
{
public:
static StructType *get(LLVMContext &context)
{
static StructType *t = StructType::create("Registers",
TypeBuilder<types::i<8>, xcompile>::get(context), // a
TypeBuilder<types::i<8>, xcompile>::get(context), // x
TypeBuilder<types::i<8>, xcompile>::get(context), // y
TypeBuilder<types::i<8>, xcompile>::get(context), // s
TypeBuilder<JitBool , xcompile>::get(context), // flag_n
TypeBuilder<JitBool , xcompile>::get(context), // flag_v
TypeBuilder<JitBool , xcompile>::get(context), // flag_d
TypeBuilder<JitBool , xcompile>::get(context), // flag_i
TypeBuilder<JitBool , xcompile>::get(context), // flag_z
TypeBuilder<JitBool , xcompile>::get(context), // flag_c
TypeBuilder<types::i<16>, xcompile>::get(context), // pc
TypeBuilder<types::i<16>, xcompile>::get(context), // addr
TypeBuilder<types::i<8>, xcompile>::get(context), // data
NULL);
return t;
}
};
}
namespace
{
const std::string hex_prefix = "&";
bool callback_in_bounds(const M6502_Callback *callbacks,
const AddressRange &bounds)
{
for (AddressRange::const_iterator it = bounds.begin();
it != bounds.end(); ++it)
{
if (callbacks[*it] != 0)
{
return true;
}
}
return false;
}
}
// BoundedAddress contains an llvm::Value of type i16 which refers to
// an address in the emulated memory. It additionally contains a range of
// possible addresses which the llvm::Value can evaluate to (derived from the
// addressing mode which created it). This is used to optimise the generated
// code.
class FunctionBuilder::BoundedAddress
{
public:
// Construct a BoundedAddress with the widest possible bounds; this
// is always safe, but if possible should be avoided as it reduces
// optimisation potential.
BoundedAddress(FunctionBuilder &fb, llvm::Value *addr);
// Construct a BoundedAddress with the given bounds.
BoundedAddress(FunctionBuilder &fb, llvm::Value *addr,
const AddressRange &bounds);
llvm::Value *addr() const
{
return addr_;
}
const AddressRange &bounds() const
{
return bounds_;
}
friend
std::ostream &operator<<(std::ostream &s, const BoundedAddress &ba)
{
std::stringstream t;
t << "[0x" << std::hex << std::setfill('0') << std::setw(4) <<
ba.bounds().range_begin() << ", 0x" << std::setw(4) <<
ba.bounds().range_end() << ")";
s << t.str();
return s;
}
private:
llvm::Value *addr_;
AddressRange bounds_;
};
FunctionBuilder::BoundedAddress::BoundedAddress(
FunctionBuilder &fb, llvm::Value *addr)
: addr_(addr), bounds_(0, memory_size)
{
assert(addr->getType() == fb.i16_type_);
}
FunctionBuilder::BoundedAddress::BoundedAddress(
FunctionBuilder &fb, llvm::Value *addr, const AddressRange &bounds)
: addr_(addr), bounds_(bounds)
{
assert(addr->getType() == fb.i16_type_);
#ifndef NDEBUG
llvm::ConstantInt *addr_ci = llvm::dyn_cast<llvm::ConstantInt>(addr);
if (addr_ci != 0)
{
// We can verify the claimed bounds at compile time.
uint16_t addr16 = addr_ci->getLimitedValue();
assert(addr16 == bounds.range_begin());
assert(addr16 == (bounds.range_end() - 1));
}
else
{
// We can't verify the claimed bounds at compile time, so generate code
// to check at runtime.
llvm::BasicBlock *bounds_maybe_ok_block =
llvm::BasicBlock::Create(fb.context_, "bounds_maybe_ok_block",
fb.llvm_function_);
llvm::BasicBlock *bounds_not_ok_block =
llvm::BasicBlock::Create(fb.context_, "bounds_not_ok");
llvm::BasicBlock *bounds_ok_block =
llvm::BasicBlock::Create(fb.context_, "bounds_ok");
if (bounds.range_end() <= memory_size)
{
TRACE("Generating bounds check code for non-wrapped case");
llvm::Value *lower_bound_ok =
fb.builder_.CreateICmpUGE(
addr, fb.constant_u16(bounds.range_begin()));
fb.builder_.CreateCondBr(lower_bound_ok, bounds_maybe_ok_block,
bounds_not_ok_block);
fb.builder_.SetInsertPoint(bounds_maybe_ok_block);
llvm::Value *upper_bound_ok =
fb.builder_.CreateICmpULE(
addr, fb.constant_u16(bounds.range_end() - 1));
fb.builder_.CreateCondBr(upper_bound_ok, bounds_ok_block,
bounds_not_ok_block);
}
else
{
TRACE("Generating bounds check code for wrapped case");
llvm::Value *in_upper_range =
fb.builder_.CreateICmpUGE(
addr, fb.constant_u16(bounds.range_begin()));
fb.builder_.CreateCondBr(in_upper_range, bounds_ok_block,
bounds_maybe_ok_block);
fb.builder_.SetInsertPoint(bounds_maybe_ok_block);
// We want to truncate bounds.range_end() - 1 to 16 bits here.
llvm::Value *in_lower_range =
fb.builder_.CreateICmpULE(
addr, fb.constant_u16(bounds.range_end() - 1));
fb.builder_.CreateCondBr(in_lower_range, bounds_ok_block,
bounds_not_ok_block);
}
fb.llvm_function_->getBasicBlockList().push_back(bounds_not_ok_block);
fb.builder_.SetInsertPoint(bounds_not_ok_block);
fb.return_invalid_bounds();
fb.llvm_function_->getBasicBlockList().push_back(bounds_ok_block);
fb.builder_.SetInsertPoint(bounds_ok_block);
}
#endif
}
FunctionBuilder::FunctionBuilder(
M6502 *mpu, const uint8_t *ct_memory, JitBool *code_at_address,
uint16_t address)
: built_(false),
mpu_(mpu),
code_at_address_(code_at_address),
address_(address),
ct_memory_(ct_memory),
callbacks_(*(mpu->callbacks)),
instructions_(0),
max_instructions_(std::max(1, mpu->internal->max_instructions_)),
context_(llvm::getGlobalContext()),
native_int_type_(llvm::TypeBuilder<int, false>::get(context_)),
callback_type_(llvm::TypeBuilder<M6502_Callback, false>::get(context_)),
i1_type_(llvm::TypeBuilder<llvm::types::i<1>, false>::get(context_)),
i8_type_(llvm::TypeBuilder<llvm::types::i<8>, false>::get(context_)),
i16_type_(llvm::TypeBuilder<llvm::types::i<16>, false>::get(context_)),
i32_type_(llvm::TypeBuilder<llvm::types::i<32>, false>::get(context_)),
i64_type_(llvm::TypeBuilder<llvm::types::i<64>, false>::get(context_)),
jit_bool_type_(llvm::TypeBuilder<JitBool, false>::get(context_)),
builder_(mpu_->internal->llvm_stuff_.builder_),
address_block_(),
code_generated_for_address_()
{
llvm::FunctionType *ft = llvm::TypeBuilder<int(), false>::get(context_);
std::stringstream name;
name << "x" << std::hex << std::setw(4) << std::setfill('0') << address_;
llvm_function_ = llvm::Function::Create(
ft, llvm::Function::PrivateLinkage, name.str(),
mpu_->internal->llvm_stuff_.module_.get());
llvm::BasicBlock *BB =
llvm::BasicBlock::Create(context_, "prologue", llvm_function_);
builder_.SetInsertPoint(BB);
mpu_llvm_ = constant_ptr(mpu, "mpu");
code_at_address_llvm_ = constant_ptr(code_at_address, "code_at_address");
registers_ = constant_ptr(&(mpu->internal->registers_), "registers");
read_callbacks_ = constant_ptr(callbacks_.read, "read_callbacks");
write_callbacks_ = constant_ptr(callbacks_.write, "write_callbacks");
call_callbacks_ = constant_ptr(callbacks_.call, "call_callbacks");
memory_base_ = constant_ptr(mpu->memory, "memory");
function_result_ =
builder_.CreateAlloca(native_int_type_, 0, "function_result");
// Function prologue: Copy the registers from Registers into local
// variables for use. The epilogue will reverse this process before the
// function returns for registers which actually get modified. (The
// LLVM optimiser is then able to remove loads which would just load
// unused values.)
initialise_i8_reg(a_ , 0, "a");
initialise_i8_reg(x_ , 1, "x");
initialise_i8_reg(y_ , 2, "y");
initialise_i8_reg(s_ , 3, "s");
initialise_jb_reg(flag_n_, 4, "flag_n");
initialise_jb_reg(flag_v_, 5, "flag_v");
initialise_jb_reg(flag_d_, 6, "flag_d");
initialise_jb_reg(flag_i_, 7, "flag_i");
initialise_jb_reg(flag_z_, 8, "flag_z");
initialise_jb_reg(flag_c_, 9, "flag_c");
pc_ = builder_.CreateAlloca(i16_type_, 0, "pc");
builder_.CreateStore(
builder_.CreateLoad(
builder_.CreateStructGEP(registers_, 10), false, "pc"),
pc_);
// Temporary variable used when invoking read callbacks; no need to
// initialise.
read_callback_result_ =
builder_.CreateAlloca(i8_type_, 0, "read_callback_result");
// Temporary variables for ADC/SBC implementation; no need to initialise.
p_tmp_ = builder_.CreateAlloca(i8_type_, 0, "p_tmp");
l_tmp_ = builder_.CreateAlloca(i8_type_, 0, "l_tmp");
s_tmp_ = builder_.CreateAlloca(i16_type_, 0, "s_tmp");
t_tmp_ = builder_.CreateAlloca(i16_type_, 0, "t_tmp");
epilogue_ = llvm::BasicBlock::Create(context_, "epilogue");
}
// The Register objects are initialised using these functions instead of
// constructors mainly because we need a builder_ with an associated BasicBlock
// to initialise a Register, and we don't have that when the FunctionBuilder
// object is first constructed.
void FunctionBuilder::initialise_i8_reg(
Register &r, int structure_index, const std::string &name)
{
llvm::Value *v = builder_.CreateAlloca(i8_type_, 0, name);
builder_.CreateStore(
builder_.CreateLoad(
builder_.CreateStructGEP(registers_, structure_index), false, name),
v);
r.v_ = v;
r.modified_ = false;
}
void FunctionBuilder::initialise_jb_reg(
Register &r, int structure_index, const std::string &name)
{
llvm::Value *v = builder_.CreateAlloca(jit_bool_type_, 0, name);
builder_.CreateStore(
builder_.CreateLoad(
builder_.CreateStructGEP(registers_, structure_index), false, name),
v);
r.v_ = v;
r.modified_ = false;
}
void FunctionBuilder::ensure_address_block_created(uint16_t addr)
{
if (address_block_[addr] == 0)
{
std::stringstream s;
s << "l" << std::hex << std::setw(4) << std::setfill('0') << addr;
address_block_[addr] =
llvm::BasicBlock::Create(context_, s.str(), llvm_function_);
}
}
boost::shared_ptr<Function> FunctionBuilder::build()
{
// This can't be invoked twice on the same FunctionBuilder object;
// at present, for example, attempts to insert into 'epilogue_' crash
// (presumably because it's been used to generate code already). There
// is no reason to do this and I'm not going to convolute things to make
// this pointless case work. Even asserting that this doesn't happen
// seems like overkill, but let's do it anyway.
assert(!built_);
// While it doesn't strictly matter, the fact that pending_ is a std::set
// means it will internally sort the addresses. This makes it more likely
// that multiple backward jumps will only result in one stretch of code
// being produced, since the furthest jump backwards will be JITted first.
pending_.insert(address_);
while (!pending_.empty())
{
// We take addresses to JIT at from pending_ to start with, and when
// there's no "better" address...
uint16_t ct_pc = *(pending_.begin());
// ... but if we can continue JITting where we left off, we prefer
// to do that. Since each block of code emitted by build_at() is
// independent, this doesn't alter the behaviour of the generated
// code, but it avoids gratuitous discontinuities in the generated
// code compared with the source machine code.
do
{
pending_.erase(ct_pc);
uint16_t new_ct_pc = build_at(ct_pc);
if (new_ct_pc == ct_pc)
{
// build_at() did no work.
}
else if (new_ct_pc > ct_pc)
{
code_range_.insert(AddressRange(ct_pc, new_ct_pc));
}
else
{
// PC wrapped around during the translation.
uint32_t range_end = new_ct_pc;
range_end += memory_size;
code_range_.insert(AddressRange(ct_pc, range_end));
}
ct_pc = new_ct_pc;
}
while (pending_.find(ct_pc) != pending_.end());
}
LLVMStuff &llvm_stuff = mpu_->internal->llvm_stuff_;
llvm::FunctionPassManager fpm(llvm_stuff.module_.get());
#ifdef HAVE_LLVM_DATA_LAYOUT_PASS
fpm.add(new llvm::DataLayoutPass(llvm_stuff.module_.get()));
#else
fpm.add(
new llvm::DataLayout(*llvm_stuff.execution_engine_->getDataLayout()));
#endif
fpm.add(llvm::createBasicAliasAnalysisPass());
fpm.add(llvm::createPromoteMemoryToRegisterPass());
fpm.add(llvm::createInstructionCombiningPass());
fpm.add(llvm::createReassociatePass());
fpm.add(llvm::createGVNPass());
fpm.add(llvm::createCFGSimplificationPass());
fpm.doInitialization();
// We could have passed llvm_function_ to BasicBlock::Create() earlier
// and then we wouldn't need to do this push_back() here, but doing
// this means the epilogue appears at the end of the IR. It makes no
// functional difference but it seems slightly more logical to read.
llvm_function_->getBasicBlockList().push_back(epilogue_);
builder_.SetInsertPoint(epilogue_);
if (a_.modified_)
{
builder_.CreateStore(
builder_.CreateLoad(a_.v_),
builder_.CreateStructGEP(registers_, 0));
}
if (x_.modified_)
{
builder_.CreateStore(
builder_.CreateLoad(x_.v_),
builder_.CreateStructGEP(registers_, 1));
}
if (y_.modified_)
{
builder_.CreateStore(
builder_.CreateLoad(y_.v_),
builder_.CreateStructGEP(registers_, 2));
}
if (s_.modified_)
{
builder_.CreateStore(
builder_.CreateLoad(s_.v_),
builder_.CreateStructGEP(registers_, 3));
}
if (flag_n_.modified_)
{
builder_.CreateStore(
register_load(flag_n_),
builder_.CreateStructGEP(registers_, 4));
}
if (flag_v_.modified_)
{
builder_.CreateStore(
register_load(flag_v_),
builder_.CreateStructGEP(registers_, 5));
}
if (flag_d_.modified_)
{
builder_.CreateStore(
register_load(flag_d_),
builder_.CreateStructGEP(registers_, 6));
}
if (flag_i_.modified_)
{
builder_.CreateStore(
register_load(flag_i_),
builder_.CreateStructGEP(registers_, 7));
}
if (flag_z_.modified_)
{
builder_.CreateStore(
register_load(flag_z_),
builder_.CreateStructGEP(registers_, 8));
}
if (flag_c_.modified_)
{
builder_.CreateStore(
register_load(flag_c_),
builder_.CreateStructGEP(registers_, 9));
}
builder_.CreateStore(
builder_.CreateLoad(pc_),
builder_.CreateStructGEP(registers_, 10));
builder_.CreateRet(builder_.CreateLoad(function_result_));
#ifdef LOG
std::string unoptimised_ir;
{
llvm::raw_string_ostream s(unoptimised_ir);
llvm_function_->print(s);
s.str();
}
#endif
llvm::verifyFunction(*llvm_function_);
fpm.run(*llvm_function_);
#ifdef LOG
std::string optimised_ir;
{
llvm::raw_string_ostream s(optimised_ir);
llvm_function_->print(s);
s.str();
}
#endif
boost::shared_ptr<Function> f(
new Function(mpu_, address_, code_range_, optimistic_writes_,
llvm_function_));
#ifdef LOG
f->set_disassembly(disassembly_.str());
f->set_unoptimised_ir(unoptimised_ir);
f->set_optimised_ir(optimised_ir);
#endif
built_ = true;
return f;
}
// This translates a linear stream of 6502 instructions into LLVM IR. The
// generation stops either when we've translated enough 6502 instructions
// or when we hit an instruction which unconditionally transfers control
// elsewhere. Branch targets found during the translation are added to pending_
// for further consideration; at a minimum, address_block[] entries with
// associated code to transfer control to those addresses must be generated
// for each of these before terminating the build process for the function.
//
// The address of the first byte not translated is returned.
uint16_t FunctionBuilder::build_at(uint16_t ct_pc)
{
TRACE("Translating linear stream of instructions at 0x" << std::hex <<
std::setfill('0') << std::setw(4) << ct_pc);
const uint16_t original_ct_pc = ct_pc;
// If we already translated this stretch of code, we don't need to do
// anything at all.
if (code_generated_for_address_[ct_pc])
{
TRACE("Already translated this linear stream");
return ct_pc;
}
while (true)
{
TRACE("Translating at 0x" << std::hex << std::setfill('0') <<
std::setw(4) << ct_pc << ", opcode 0x" << std::setw(2) <<
static_cast<int>(ct_memory_[ct_pc]));
const uint16_t this_opcode_at = ct_pc;
if (code_generated_for_address_[ct_pc])
{
// We already translated this instruction, so we can stop
// translating and just jump there. Since this is just linear
// flow of control from the perspective of the 6502 code, this
// cannot trigger a call callback.
TRACE("Already translated this instruction");
if (builder_.GetInsertBlock()->getTerminator() == 0)
{
control_transfer_to(constant_u16(ct_pc), opcode_implicit);
}
break;
}
// Each instruction forms its own basic block (since we build up the
// IR as we go, we can't know where we might want to branch into,
// so we cannot merge multiple instructions into a single basic
// block). Basic blocks must end with a terminator, so if there isn't
// already a terminator at the end of the previous instruction's basic
// block, we insert an unconditional branch to this instruction's
// basic block. If there is already a terminator, we stop translating
// this stream of instructions unless this is the first instruction
// in this linear sequence; this way we avoid generating unreachable
// code if the previous instruction (for example) returned some kind
// of status code to our caller. (If the following instruction is
// reachable in some other way, it will be translated separately -
// as the first instruction in a linear sequence - because it will
// be present in pending.)
bool insert_block_has_terminator =
(builder_.GetInsertBlock()->getTerminator() != 0);
if (insert_block_has_terminator && (ct_pc != original_ct_pc))
{
TRACE("Not translating as not first instruction in linear stream "
"and previous instruction's basic block has a terminator");
break;
}
ensure_address_block_created(ct_pc);
if (!insert_block_has_terminator)
{
builder_.CreateBr(address_block_[ct_pc]);
}
builder_.SetInsertPoint(address_block_[ct_pc]);
// Note that we only set this flag for the opcode byte, not the
// whole length of the instruction. Apart from being easiest,
// this is actually correct. Someone might do LDA #<opcode for
// LDA #>:STA <opcode for RTS> or something weird like that and
// interleave instructions.
code_generated_for_address_[ct_pc] = true;
if (instructions_ >= max_instructions_)
{
TRACE("Translated maximum number of instructions");
// We must *not* use control_transfer_to() here; it would see
// that we have set code_generated_for_address_ and generate a
// branch to here, i.e. an infinite loop. It is correct that we
// have set code_generated_for_address_ since we must set that
// if we generate a corresponding address_block entry and we must
// do that so that any branches to this address can be resolved.
return_control_transfer_direct(constant_u16(ct_pc));
break;
}
++instructions_;
uint8_t opcode = ct_memory_[ct_pc];
if (opcode == opcode_brk)
{
disassemble1(ct_pc, "BRK");
llvm::Value *new_pc_low = memory_read(abs(0xfffe));
llvm::Value *new_pc_high = memory_read(abs(0xffff));
llvm::Value *new_pc = create_u16(new_pc_low, new_pc_high);
// Because BRK pushes three bytes onto the stack, we devolve
// responsibility for checking for code living on the stack
// being modified to our caller (by returning result_brk), so
// we use push*raw() here. (We don't support optimistic writes;
// BRK isn't performance critical so there's no payoff for the
// extra complexity.)
uint16_t pc_to_stack = this_opcode_at + 2;
push_u16_raw(pc_to_stack);
llvm::Value *p = flag_byte();
p = builder_.CreateOr(p, constant_u8(flagB | flagX));
push_u8_raw(p);
register_store(constant_jb(jit_bool_true), flag_i_);
register_store(constant_jb(jit_bool_false), flag_d_);
return_brk(new_pc);
}
else if (opcode == 0x01)
{
uint8_t operand;
disassemble2(ct_pc, "ORA (", operand, ",X)");
ora(memory_read(
zp_pre_index(constant_u8(operand), register_load(x_))));
}
else if (opcode == 0x02)
{
illegal_instruction(ct_pc, 2);
}
else if (opcode == 0x03)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x04)
{
uint8_t operand;
disassemble2(ct_pc, "TSB ", operand);
memory_op(&FunctionBuilder::tsb, zp(operand), ct_pc);
}
else if (opcode == 0x05)
{
uint8_t operand;
disassemble2(ct_pc, "ORA ", operand);
ora(memory_read(zp(operand)));
}
else if (opcode == 0x06)
{
uint8_t operand;
disassemble2(ct_pc, "ASL ", operand);
memory_op(&FunctionBuilder::asl, zp(operand), ct_pc);
}
else if (opcode == 0x07)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x08)
{
disassemble1(ct_pc, "PHP");
llvm::Value *p = flag_byte();
p = builder_.CreateOr(p, constant_u8(flagB | flagX));
push_u8(p, ct_pc);
}
else if (opcode == 0x09)
{
uint8_t operand;
disassemble2(ct_pc, "ORA #", operand);
ora(constant_u8(operand));
}
else if (opcode == 0x0a)
{
disassemble1(ct_pc, "ASL A");
register_op(&FunctionBuilder::asl, a_);
}
else if (opcode == 0x0b)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x0c)
{
uint16_t operand;
disassemble3(ct_pc, "TSB ", operand);
memory_op(&FunctionBuilder::tsb, abs(operand), ct_pc);
}
else if (opcode == 0x0d)
{
uint16_t operand;
disassemble3(ct_pc, "ORA ", operand);
ora(memory_read(abs(operand)));
}
else if (opcode == 0x0e)
{
uint16_t operand;
disassemble3(ct_pc, "ASL ", operand);
memory_op(&FunctionBuilder::asl, abs(operand), ct_pc);
}
else if (opcode == 0x0f)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == opcode_bpl)
{
uint16_t target;
disassemble_branch(ct_pc, "BPL ", target);
pending_.insert(target);
branch(flag_n_, false, target);
}
else if (opcode == 0x11)
{
uint8_t operand;
disassemble2(ct_pc, "ORA (", operand, "),Y");
ora(memory_read(
zp_post_index(constant_u8(operand), register_load(y_))));
}
else if (opcode == 0x12)
{
uint8_t operand;
disassemble2(ct_pc, "ORA (", operand, ")");
ora(memory_read(
zp_post_index(constant_u8(operand), constant_u8(0))));
}
else if (opcode == 0x13)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x14)
{
uint8_t operand;
disassemble2(ct_pc, "TRB ", operand);
memory_op(&FunctionBuilder::trb, zp(operand), ct_pc);
}
else if (opcode == 0x15)
{
uint8_t operand;
disassemble2(ct_pc, "ORA ", operand, ",X");
ora(memory_read(zp_index(constant_u8(operand), register_load(x_))));
}
else if (opcode == 0x16)
{
uint8_t operand;
disassemble2(ct_pc, "ASL ", operand, ",X");
memory_op(&FunctionBuilder::asl,
zp_index(constant_u8(operand), register_load(x_)), ct_pc);
}
else if (opcode == 0x17)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x18)
{
disassemble1(ct_pc, "CLC");
register_store(constant_jb(jit_bool_false), flag_c_);
}
else if (opcode == 0x19)
{
uint16_t operand;
disassemble3(ct_pc, "ORA ", operand, ",Y");
ora(memory_read(
abs_index(constant_u16(operand), register_load(y_))));
}
else if (opcode == 0x1a)
{
disassemble1(ct_pc, "INC A");
register_op(&FunctionBuilder::inc, a_);
}
else if (opcode == 0x1b)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x1c)
{
uint16_t operand;
disassemble3(ct_pc, "TRB ", operand);
memory_op(&FunctionBuilder::trb, abs(operand), ct_pc);
}
else if (opcode == 0x1d)
{
uint16_t operand;
disassemble3(ct_pc, "ORA ", operand, ",X");
ora(memory_read(
abs_index(constant_u16(operand), register_load(x_))));
}
else if (opcode == 0x1e)
{
uint16_t operand;
disassemble3(ct_pc, "ASL ", operand, ",X");
memory_op(
&FunctionBuilder::asl,
abs_index(constant_u16(operand), register_load(x_)),
ct_pc);
}
else if (opcode == 0x1f)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == opcode_jsr)
{
uint16_t operand;
disassemble3(ct_pc, "JSR ", operand);
uint16_t mangled_return_addr = ct_pc - 1;
// We are pushing two bytes onto the stack here and possibly
// requiring our caller to handle the control transfer, so the
// standard mechanisms for handling writes to code and control
// transfer aren't enough. control_transfer_to() contains special
// logic for JSR and we just use push_u16_raw() here.
push_u16_raw(mangled_return_addr);
// We generally want to translate the subroutine code into
// this function, so control_transfer_to() can perform the
// control transfer with a simple branch. However, if there is
// a call callback, control_transfer_to() will have to arrange
// a control transfer via the generated function's caller. It
// would be strictly harmless for us to translate the subroutine
// code anyway, as it will just never be executed, but it is
// both pointless and makes the generated IR less readable (it
// has a superficially buggy appearance, since it will show a
// translation of possibly junk code at the callback address
// which may never actually execute).
bool is_call_callback = (callbacks_.call[operand] != 0);
if (!is_call_callback)
{
pending_.insert(operand);
// We can predict that the RTS in the subroutine we are
// about to call will return to the immediately following
// instruction. (This is not guaranteed; the subroutine
// might fiddle with the stack. If that happens the "code"
// at ct_pc might be junk, but that's an acceptable risk;
// we will translate it but it will never be executed, and
// any stream of bytes can be translated even if the code
// is nonsense.)
pending_.insert(ct_pc);
predicted_rts_targets_[operand].insert(ct_pc);
}
control_transfer_to(constant_u16(operand), opcode);
}
else if (opcode == 0x21)
{
uint8_t operand;
disassemble2(ct_pc, "AND (", operand, ",X)");
And(memory_read(
zp_pre_index(constant_u8(operand), register_load(x_))));
}
else if (opcode == 0x22)
{
illegal_instruction(ct_pc, 2);
}
else if (opcode == 0x23)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x24)
{
uint8_t operand;
disassemble2(ct_pc, "BIT ", operand);
bit(memory_read(zp(operand)));
}
else if (opcode == 0x25)
{
uint8_t operand;
disassemble2(ct_pc, "AND ", operand);
And(memory_read(zp(operand)));
}
else if (opcode == 0x26)
{
uint8_t operand;
disassemble2(ct_pc, "ROL ", operand);
memory_op(&FunctionBuilder::rol, zp(operand), ct_pc);
}
else if (opcode == 0x27)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x28)
{
disassemble1(ct_pc, "PLP");
pop_flags();
}
else if (opcode == 0x29)
{
uint8_t operand;
disassemble2(ct_pc, "AND #", operand);
And(constant_u8(operand));
}
else if (opcode == 0x2a)
{
disassemble1(ct_pc, "ROL A");
register_op(&FunctionBuilder::rol, a_);
}
else if (opcode == 0x2b)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x2c)
{
uint16_t operand;
disassemble3(ct_pc, "BIT ", operand);
bit(memory_read(abs(operand)));
}
else if (opcode == 0x2d)
{
uint16_t operand;
disassemble3(ct_pc, "AND ", operand);
And(memory_read(abs(operand)));
}
else if (opcode == 0x2e)
{
uint16_t operand;
disassemble3(ct_pc, "ROL ", operand);
memory_op(&FunctionBuilder::rol, abs(operand), ct_pc);
}
else if (opcode == 0x2f)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == opcode_bmi)
{
uint16_t target;
disassemble_branch(ct_pc, "BMI ", target);
pending_.insert(target);
branch(flag_n_, true, target);
}
else if (opcode == 0x31)
{
uint8_t operand;
disassemble2(ct_pc, "AND (", operand, "),Y");
And(memory_read(
zp_post_index(constant_u8(operand), register_load(y_))));
}
else if (opcode == 0x32)
{
uint8_t operand;
disassemble2(ct_pc, "AND (", operand, ")");
And(memory_read(
zp_post_index(constant_u8(operand), constant_u8(0))));
}
else if (opcode == 0x33)
{
illegal_instruction(ct_pc, 1);
}
else if (opcode == 0x34)
{
uint8_t operand;
disassemble2(ct_pc, "BIT ", operand, ",X");
bit(memory_read(zp_index(constant_u8(operand), register_load(x_))));
}
else if (opcode == 0x35)
{
uint8_t operand;
disassemble2(ct_pc, "AND ", operand, ",X");
And(memory_read(zp_index(constant_u8(operand), register_load(x_))));
}
else if (opcode == 0x36)
{
uint8_t operand;