Mapping a Xilinx netlist to SkyWater

[mayureshw]

I am completely new to Yosys.

I have a netlist produced by synthesis using Xilinx Vivado. It makes use of LUTs, FDCE, IBUF.

I would like to map this to SkyWater (or any other cell library for ASICs).

Is this something possible using (say) techmap in Yosys?

Please suggest a recipe for this.

[QuantamHD]

I'm not super familiar with the FPGA part of Yosys, but assuming it just works. If you run the abc pass with a liberty file it might just unmap your LUTs and move them to standard cells

[KrystalDelusion]

I'm not sure how up to date the synth_xilinx pass is, but you'll probably need something along the lines of the begin section for Yosys to know what the cells do, i.e.

read_verilog -lib -specify +/xilinx/cells_sim.v
read_verilog -lib +/xilinx/cells_xtra.v
read_verilog <netlist>.v
...

I don't know how to get from there to another cell library though.