Ensuring module output ports are always a single net, not a concatenation of nets

[gussmith23]

Hello!

I have a module that has an output port which is currently defined as:

    .P({ \P_0[47:32] , _2_ }),

I would love to rewrite it so that it is simply

    .P(newnet),

and then somewhere else,

  logic [...] newnet = { \P_0[47:32] , _2_ });

Is there a pass that will do this?

I'm currently running splice and splitnets -driver, but neither of them do this.

Note: I've also tried scatter, which doesn't work for what I'm trying to do.

[udif]

Lets start with the fact that logic doesn't behave the way you expect it.
(I also removed the extra ) at the end of the line.

 logic [...] newnet = { \P_0[47:32] , _2_ };

As you wrote, does NOT behave like:

 wire [...] newnet = { \P_0[47:32] , _2_ };

Which is probably what you expect, but rather like:

 reg [...] newnet;
 initial
  newnet = { \P_0[47:32] , _2_ };