Correct yosys usage

[janetatomas1]

Hello.
I have a verilog design. I have a cell library that I want the design mapped to.
What is the correct way to run synthesis ?

read_verilog file.v

hierarchy -check -top Mod
proc; opt
memory; opt
fsm; opt
techmap; opt

dfflibmap -liberty cells.lib
abc -liberty cells.lib

When I run this script, then in the output edif file are many lins like this:
libraryRef LIB,
and engineers that I give the edif to argue that they can't work with this.
I thought this is the reference for the cells.lib.

Thanks.