Yosys pass to make sign extension of e.g. AND inputs explicit

[gussmith23]

This is similar to this question: #4330

Verilog allows you to write things like

input a; input b;
logic [1:0] v = a & b;

where it will automatically cast up the result of a & b to two bits. Are there any passes that makes that conversion explicit, e.g.

input a; input b;
logic [1:0] v = { 1'b0, a & b };

Another way to put this: I would like my RTLIL logic cells to have equal A, B, and Y widths for ops like and, or, etc.

Any help appreciated! Thanks!

[KrystalDelusion]

wreduce springs to mind, but (afaik) that sets everything to the minimum width necessary, rather than the maximum. But that does let you "have equal A, B, and Y widths."