Yosys pass to explicate zero-extending?

[ninehusky]

Verilog implicitly extends constants to fit the bitwidth of their types, e.g. in the case of:
logic [1:0] a = 1'b0;

Is there a Yosys pass to explicate these extensions? It would be great if the above code snippet would be converted to:
logic [1:0] a = {1'b0, 1'b0}

Happy to provide more context as needed!

cc @gussmith23

[whitequark]

Have you tried read_verilog followed by write_verilog?

[ninehusky]

Thanks for your response! Is there a way to do this without needing to read the Verilog back in? Alternatively, is there a way to easily read the Verilog back in after writing it (i.e. without needing to write the Verilog to a file, and then read it back in)?

[whitequark]

It is reading the Verilog that performs the sign extension; if you want to operate on the representation of the code that has the constant extended, then a simple read_verilog is enough.