Support for FIRRTL SeqMem primitives #3201
Unanswered
hadirkhan10
asked this question in
Q&A
Replies: 0 comments
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
-
@azidar I am seeing some work being done in the yosys backend for FIRRTL.. does it support emitting SeqMem FIRRTL primitives for memories in verilog? I am not seeing any memory test here:
https://github.com/YosysHQ/yosys/blob/master/backends/firrtl/test.v
Beta Was this translation helpful? Give feedback.
All reactions