liberty file description of flip flops with synchronouse set/reset

[cpldcpu]

According to the liberty file format description this is a valiud description for a DFF with synchrnous clear (see page 5-9)

`
cell(rt_DFF6NOR_NPCLR) {

area: 15;
ff(IQ, IQN) { clocked_on: "C'";
              next_state: "D * CLR'"; }
pin(C) { direction: input;
             clock: true; }
pin(CLR) { direction: input; }    
pin(D) { direction: input;
         nextstate_type: data;  }
pin(Q) { direction: output;
          function: "IQ"; }
pin(QN) { direction: output;
          function: "IQN"; }

}
`

Yosys does not seem to like have boolean statement in "next state":
Warning: Found unsupported expression 'D*CLR' in pin attribute of cell 'rt_DFF6NOR_NPCLR' - skipping.

Any idea how to address this? Should I move to verilog entity descriptions?