Releases · Xilinx/RapidWright

14 Sep 02:36

clavin-xlnx

v2023.1.3-beta

7cec512

RapidWright 2023.1.3-beta Release

Release Notes:
Notes:

Fix DesignTools.getConnectionPIPs() (#809)
[PhysNetlistWriter] RouteBranchNode.getDrivers() to return input BelPin (#800)
Adds site pins to example code generation for nets. (#807)
Update to fixed microblazeAndILA_3pblocks.dcp (#808)
[LogNetlistWriter] Refactor writeStrings method to be public static (#804)
[VivadoTools] ReportRouteStatusResult to parse more stats (#805)
EDIF improvements (#806)
RWRoute improvements (#803)
Adds a createBitstream() method to VivadoTools (#801)
Small DesignTools improvements (#797)
added static function that helps produce test nets (including PIPs) (#784)
Add reference copy methods (#794)
[RWRoute] Add alternate source pins and set source routed flags (#787)
Adds support for RouteThru LUT equations and makes LUTEquationEvaluator public (#795)
Fix TestDCPLoad to prevent issues with parallel testing (#793)
[PhysNetlistWriter] Fix route tree construction for bidir PIPs (#791)
VivadoTools.reportRouteStatus() to handle encrypted cells (#777)
[PhysNetlistWriter] Insert site port BELPin before site pin (#790)
fixed null pointer exception in getPhysicalNetFromPin() (#775)
LUT cell companion helper methods (#764)
Check for error situation RAPIDWRIGHT_PATH set but not CLASSPATH (#772)
Set reversed flag on bi-directional PIPs used from end->start (#774)
Fix RouterHelper.projectOutputPinToINTNode() for depop pins (#779)
Make PartialRouter.getUnroutedPins() public (#778)
FileTools.runCommand() - Adds ability to choose run directory (#769)
[GlobalSignalRouting] Static router to not create site pin if exists (#768)
RouteThru support for FFs in UltraScale architecture
Fixes minor SitePinInst creation when reading a DCP
Improvements to Net.rename() when tracking changes
Design.detachNetlist() to detach routethru cells
Adds reference copy APIs and ability to keep copies of modified
SiteInsts and Nets
Improvements to DCP reading compatibility for different flows
within Vivado
API Additions:
- com.xilinx.rapidwright.bitstream.BitLocation "public int hashCode()"
- com.xilinx.rapidwright.bitstream.BitLocation "public boolean equals(Object obj)"
- com.xilinx.rapidwright.bitstream.Bitstream "public static Bitstream readBitstream(Path fileName)"
- com.xilinx.rapidwright.bitstream.Block "public int getBit(BitLocation bit, Tile tile)"
- com.xilinx.rapidwright.bitstream.Block "public boolean updateBit(BitLocation bit, Tile tile, int value, Block golden)"
- com.xilinx.rapidwright.bitstream.ConfigRow "public ConfigRow(int configRowIdx)"
- com.xilinx.rapidwright.bitstream.FAR "public Block getConfigBlock(int slrCfgOrder)"
- com.xilinx.rapidwright.bitstream.Packet "public int hashCode()"
- com.xilinx.rapidwright.bitstream.Packet "public boolean equals(Object obj)"
- com.xilinx.rapidwright.design.Cell "public static final String FF_ROUTETHRU_TYPE"
- com.xilinx.rapidwright.design.Cell "public Cell getReferenceCopy()"
- com.xilinx.rapidwright.design.Cell "public boolean isFFRoutethruCell()"
- com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalNetsRouting()"
- com.xilinx.rapidwright.design.Design "public void setCopyingOriginalNetsRouting(boolean copyOrigNets)"
- com.xilinx.rapidwright.design.Design "public Map<String, List> getOriginalNetRouting()"
- com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalSiteInsts()"
- com.xilinx.rapidwright.design.Design "public void setCopyingOriginalSiteInsts(boolean copyOrigSiteInsts)"
- com.xilinx.rapidwright.design.Design "public Map<String, SiteInst> getOriginalSiteInsts()"
- com.xilinx.rapidwright.design.Net "public List getCopyOfPIPs()"
- com.xilinx.rapidwright.design.SiteInst "public void addPin(SitePinInst sitePinInst)"
- com.xilinx.rapidwright.design.SiteInst "public SiteInst getReferenceCopy()"

Assets 9

24 Jul 22:49

clavin-xlnx

v2023.1.2-beta

92eb05d

RapidWright 2023.1.2-beta Release

Release Notes:

Shell creation improvements to enable lock_design and timing closure preservation (#760)
Adds a MakeBlackBox command line tool (#747)
Removes the VCC A6 pin on 5LUT usages when removing cells (#741)
Add DesignTools.getAllRoutedSitePinsFromPhysicalPin() (#755)
Correctly update dual-output route flags when unrouting (#737)
[PhysNetlistReader] Set cell type of LOCKED cells (#767)
Updates RAM32X1S property to correct default (#751)
[Interchange] PhysNetlistReader to create STATIC_SOURCE SiteInsts (#766)
RWRoute Fixes (#765)
GlobalSignalRouting.routeStaticNet() to create output SPIs (#761)
DesignTools.createCeSrRstPinsToVCC() to skip non-SLICE FFs (#744)
[PartialRouter] Improve incremental global routing (#759)
GlobalSignalRouting fixes for routing to non clock-pins (#757)
DesignTools.makePhysNetNamesConsistent() to merge static nets too (#753)
[UltraScaleClockRouting] Reset RouteNode.parent (#752)
Created parameterizable counter with an adder as a submodule (#713)
[RWRoute] Fix PartialRouter for when clk node already unpreserved (#746)
[Interchange] Fix PhysicalNetlist's MultiCellPinMapping (#743)
Unroute site routing when removing a cell (#729)
PartialRouter's global router to not unpreserve sink nodes (#736)
DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
Add DcpToInterchange class (#704)
Add compile step (#733)
Add EdifToLogicalNetlist to MainEntrypoint (#731)
Fix Javadoc warnings (#723)
Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
[PhysNetlistReader] Set Cell type for routethru cells (#727)
Multilevel macro expansion (#726)
TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
Fix to create alternate source pins on dual output nets.
Fixes incorrect Versal SLR corner tile entries
Cell.getProperty() returns null if no EDIFCellInst found
Cell.getAllSitePinsFromLogicalPin() to not return any null pins
Cell.getAllCorrespondingSitePinNames() to not NPE if no physical pin mapping
Cell.getCorrespondingSitePinName() to consider F?MUX routethrus
API Additions:
- com.xilinx.rapidwright.device.PIP "public boolean isLogicalDriver()"
- com.xilinx.rapidwright.design.Cell "public String getCorrespondingSitePinName(String logicalPinName, String physPinName, List siteWires)"

Assets 9

21 Jun 22:06

clavin-xlnx

v2023.1.1-beta

802345b

RapidWright 2023.1.1-beta Release

Release Notes:

UltraScale Incremental Clock Router Improvements (#540)
Adds VivadoTools, a Vivado wrapper/helper in RapidWright (#684)
Fixes published Maven Central jar (#698)
Enhancements to RWRoute (#691, #696)
Interchange reader/writer improvements (#677)
Fix for issue #709
Improves handling of site routing and site pins when updating
physical netlist

Assets 9

01 Jun 17:12

clavin-xlnx

v2023.1.0-beta

cefe09a

RapidWright 2023.1.0-beta Release

Release Notes:

Support for Vivado 2023.1 devices and reading 2023.1 DCPs
Full adoption of Zstandard compression for all device and data
files - 11% faster device loads and 108% faster device cache loads with file size reductions of 32% and 52% respectively.
Has a new 'rapidwright' run wrapper that avoids the need to set CLASSPATH, provides convenience to run any class file with a main() method, run the Jython interpreter and enables one-liner Jython commands. Run rapidwright at the prompt for more details.
Fix duplicate net source pins (won't set the alternate source if it is the same as the source)
Change Net.connect() behavior to connect to existing SitePinInst if net is null
DesignTools.createCeSrRstPinsToVCC() to detect gnd to invert (#664)
EDIFNetlist.cellInstIOStandardFallback to collect set of IOSTANDARDs instead of throwing an error if there is a conflict (#671)
[EDIF] More expanded macros to be deep copied from prim library (#672)
Ignore TestCheckOpenFilesInstalled.test if outside of gradle (#674)
[EDIF] EDIFNetlist.collapseMacroUnisims() to not clobber cell (#675)
[EDIF] Explicit DEFAULT IOStandard on Cell to be overriden by Net (#686)
API Additions:
- (None)
API Deprecation Removals (--> Replacements) [Closed Source]:
- com.xilinx.rapidwright.device.Tile "public String getNameRoot() --> "public string getRootName()"
- com.xilinx.rapidwright.device.Device "public Tile[][] getTilesByNameRoot(String nameRoot)" --> "getTilesByRootName(String rootName)"

Assets 9

03 May 21:32

clavin-xlnx

v2022.2.3-beta

368002d

RapidWright 2022.2.3-beta Release

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

Adds preliminary support for Zstandard compression. Uses it in device cache file generation. Next release will use it for all data files.
Fixes an issue with missing Versal Premium families unisim data (#631)
Adds an option to the Interchange device model writer to exclude routing info. to enable placement of the largest devices (#658)
Fixes an issue in the PBlockGenerator parser (#633)
Resolves an issue where collapsed macro ports' parent reference was not set properly (#654)
EDIFNetlist.getIOStandard() to inherit IOStandard from EDIFNet (#646)
API Additions:
- com.xilinx.rapidwright.design.Design "public static boolean readEdifAndXdefInParallel()"
- com.xilinx.rapidwright.design.Design "public static void setReadEdifAndXdefInParallel(boolean readEdifAndXdefInParallel)"

Assets 10

11 Mar 03:11

clavin-xlnx

v2022.2.2-beta

891d3e6

RapidWright 2022.2.2-beta Release

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

Includes new API to ensure all downloaded/generated dependant files are present in RapidWright install (#613)
Change in Cell.hashCode() and Cell.equals() behavior such that it now distinguishes routethru cells (#624), see Issue #611
Fixes an issue with isFF() (#622)
Resolves issue with Cells and Nets that contain backslashes not being properly loaded (#612)
Fix for parsing gzipped EDIF files in parallel (#619)
Fix for EDIF export bussed names that collide with bitty names (#616)
API Additions:
- com.xilinx.rapidwright.device.Device "public void ensureDeviceCacheFileIsGenerated()"

Assets 10

20 Jan 06:05

clavin-xlnx

v2022.2.1-beta

94caa5c

RapidWright 2022.2.1-beta Release

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

Preserves hwdef information in DCP (#597)
Adds APIs to access BELAttr information in design (#598)
Many improvements to RWRoute to cleanup code and improves both quality and runtime performance
Fixes a bug with 2022.2 DCPs where hierarchical names were getting mangled in RapidWright (#603)
Adds support for reading gzipped EDIF files
Fixes an issue with Design.updateDesignWithCheckpointPlaceAndRoute() on more recent version DCPs (#601)
API Additions:
- com.xilinx.rapidwright.design.Design "public Map<Site, SiteConfig> getBELAttrs()"
- com.xilinx.rapidwright.design.Design "public BELAttr addBELAttr(Net net, Site site, SiteTypeEnum type, BEL bel, String name, String value)"
- com.xilinx.rapidwright.device.Device "public BEL getBEL(SiteTypeEnum type, String belName)"
- com.xilinx.rapidwright.device.Device "public BEL[] getBELs(SiteTypeEnum type)"

Assets 10

17 Nov 04:54

clavin-xlnx

v2022.2.0-beta

6730ee7

RapidWright 2022.2.0-beta Release

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

Support for Vivado 2022.2 devices and DCPs
~5% memory usage improvement over 2022.1.4 when loading (large) DCPs
Removes several deprecated APIs (See list below)
Fixes the method "public synchronized boolean isIOStandardSupported(String ioStandard)" on Package.
Corrects null node scenario as seen in #581
Moving device root tile name cache into open source (#578)
API Additions:
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFHierCellInst inst)"
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFHierCellInst inst, SiteInst i)"
- com.xilinx.rapidwright.design.Cell "public Map<String, EDIFPropertyValue> getProperties()"
- com.xilinx.rapidwright.device.Device "public Tile[][] getTilesByRootName(String rootName)"
- com.xilinx.rapidwright.device.Tile.java "public String getRootName()"
API Deprecation Removals (--> Replacements) [Open Source]:
- com.xilinx.rapidwright.design.ModuleInst "public ArrayList getInsts()"
  --> "public List getSiteInsts()"
- com.xilinx.rapidwright.design.ModuleInst "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile, Device dev)"
  --> "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile)"
- com.xilinx.rapidwright.edif.EDIFCellInst "public Map<String, EDIFPortInst> getPortInstMap()"
  --> "public Collection getPortInsts()"
- com.xilinx.rapidwright.edif.EDIFCellInst "public void updateCellType(EDIFCell cellType)"
  --> "public void setCellType(EDIFCell cellType)"
- com.xilinx.rapidwright.edif.EDIFNet "public Map<String, EDIFPortInst> getPortInstMap()"
  --> "public Collection getPortInsts()"
- com.xilinx.rapidwright.edif.EDIFNet "public EDIFPortInst getPortInst(String fullName)"
  --> "public EDIFPortInst getPortInst(EDIFCellInst inst, String portInstName)"
- com.xilinx.rapidwright.edif.EDIFNet "public EDIFPortInst removePortInst(String portInstName)"
  --> "public EDIFPortInst removePortInst(EDIFCellInst inst, String portInstName)"
  --> "public EDIFPortInst removePortInst(EDIFPortInst portInst)"
- com.xilinx.rapidwright.edif.EDIFNetlist "public static String getHierParentName(String hierReferenceName)"
  --> com.xilinx.rapidwright.edif.EDIFHierCellInst.getParent().toString()
  --> com.xilinx.rapidwright.edif.EDIFHierNet.getParent().toString()
  --> com.xilinx.rapidwright.edif.EDIFHierPortInst.getParent().toString()
- com.xilinx.rapidwright.edif.EDIFNetlist "public static String getNextHierChildName(String ancestor, String descendent)"
  --> com.xilinx.rapidwright.edif.EDIFHierCellInst.getParent().toString()
- com.xilinx.rapidwright.edif.EDIFNetlist "public HashMap<String,EDIFPort> generateEDIFPortMap()"
  --> com.xilinx.rapidwright.edif.EDIFCell.getPortMap()
- com.xilinx.rapidwright.edif.EDIFTools "public static EDIFNet connectLogicalNetAcrossHierarchy(String sinkParentInstName, String srcParentInstName, Map<String, EDIFNet> parentInstNameToLogNet, EDIFNetlist netlist)"
  --> "public static void connectPortInstsThruHier(EDIFHierPortInst src, EDIFHierPortInst snk, String newName)"
- com.xilinx.rapidwright.edif.EDIFPort "public String getStemName()"
  --> "public static String getRootBusName(String name, boolean includeOpenBracket)"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public EDIFPropertyValue addProperty(EDIFName key, EDIFPropertyValue value)"
  --> "public EDIFPropertyValue addProperty(String key, EDIFPropertyValue value)"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public void addProperties(Map<EDIFName,EDIFPropertyValue> properties)"
  --> "public EDIFPropertyValue addProperty(String key, EDIFPropertyValue value)"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public Map<EDIFName, EDIFPropertyValue> getProperties()"
  --> "public Map<String, EDIFPropertyValue> getPropertiesMap()"
- com.xilinx.rapidwright.edif.EDIFPropertyObject "public void setProperties(Map<EDIFName, EDIFPropertyValue> properties)"
  --> "public void setPropertiesMap(Map<String, EDIFPropertyValue> properties)"
- com.xilinx.rapidwright.edif.EDIFTools "public static EDIFCellInst getEDIFCellInst(EDIFNetlist netlist, String hierarchicalName)"
  --> com.xilinx.rapidwright.edif.EDIFNetlist.getCellInstFromHierName()
- com.xilinx.rapidwright.edif.EDIFTools "public static String getHierarchicalRootFromPinName(String s)"
  --> com.xilinx.rapidwright.edif.EDIFHierCellInst.getParent().toString()
- com.xilinx.rapidwright.edif.EDIFTools "public static void flattenNetlist(Design design)"
  --> "public static Boolean uniqueifyNetlist(Design design)"
- com.xilinx.rapidwright.util.FileTools "public static boolean checkIfRapidWrightResourceExists(String name)"
  --> N/A
- com.xilinx.rapidwright.util.FileTools "public static boolean folderCheck(String name)"
  --> java.io.File().exists()
- com.xilinx.rapidwright.util.MessageGenerator "public static void briefErrorAndExit(String msg)"
  --> System.err.println(), return or throw new RuntimeException() (avoid System.exit())
- com.xilinx.rapidwright.util.MessageGenerator "public static void briefMessageAndExit(String msg)"
  --> System.out.println(), return or throw new RuntimeException() (avoid System.exit())
API Deprecation Removals (--> Replacements) [Closed Source]:
- com.xilinx.rapidwright.design.Cell "public Map<EDIFName, EDIFPropertyValue> getProperties()"
  --> "public Map<String, EDIFPropertyValue> getProperties()"
- com.xilinx.rapidwright.design.Cell "public Cell(String name, EDIFCellInst edifCellInst)"
  --> "public Cell(String name)"
- com.xilinx.rapidwright.design.Cell "public Cell(String name, BEL bel, EDIFCellInst edifCellInst)"
  --> "public Cell(String name, BEL bel)"
- com.xilinx.rapidwright.design.Cell "public Cell(String name, SiteInst siteInst, BEL bel, EDIFCellInst edifCellInst)"
  --> "public Cell(String name, SiteInst siteInst, BEL bel)"
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFCellInst edifCellInst)"
  --> "public Cell(String name)"
- com.xilinx.rapidwright.design.Cell "public Cell copyCell(String name, EDIFCellInst edifCellInst, SiteInst i)"
  --> "public Cell(String name)"
- com.xilinx.rapidwright.design.Cell "public void setEDIFCellInst(EDIFCellInst edifCellInst)"
  --> "public void setEDIFHierCellInst(EDIFHierCellInst inst)"
- com.xilinx.rapidwright.design.Cell "public void setProperties(Map<EDIFName, EDIFPropertyValue> properties)"
  --> "public void setPropertiesMap(Map<String, EDIFPropertyValue> properties)"
- com.xilinx.rapidwright.design.Design "public Net createNet(EDIFNet net)"
  --> "public Net createNet(EDIFHierNet net)"
- com.xilinx.rapidwright.design.Design "public Net createNet(String name, EDIFNet net)"
  --> "public Net createNet(EDIFHierNet net)"
- com.xilinx.rapidwright.design.Design "public HashMap<String,EDIFCellInst> getNetlistInstMap()"
  --> com.xilinx.rapidwright.netlist.EDIFNetlist.generateCellInstMap();
- com.xilinx.rapidwright.design.Design "public HashMap<String, EDIFNet> getNetlistNetMap()"
  --> com.xilinx.rapidwright.netlist.EDIFNetlist.generateEDIFNetMap();
- com.xilinx.rapidwright.design.Module "public boolean isValidPlacement(Site proposedAnchorSite, Device dev, Design design)"
  --> "public boolean isValidPlacement(Site proposedAnchorSite, Design design)"
- com.xilinx.rapidwright.design.Module "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile, Device dev)"
  --> "public Tile getCorrespondingTile(Tile templateTile, Tile newAnchorTile)"
- com.xilinx.rapidwright.design.Net "public Net(String name, EDIFNet logicalNet)"
  --> "public Net(String name)"
- com.xilinx.rapidwright.design.Net "public Net(EDIFNet logicalNet)"
  --> "public Net(EDIFHierNet net)"
- com.xilinx.rapidwright.design.Net "public SitePinInst createPin(boolean isOutput, String pinName, SiteInst si)"
  --> "public SitePinInst createPin(String pinName, SiteInst si)"
- com.xilinx.rapidwright.design.Net "public void setLogicalNet(EDIFNet logicalNet)"
  --> "public void setLogicalHierNet(EDIFHierNet logicalHierNet)"
- com.xilinx.rapidwright.design.SiteInst "public Set getNetList()"
  --> "public Set getConnectedNets()"
- com.xilinx.rapidwright.design.SiteInst "public Map<String,Net> getNetSiteWireMap()"
  --> "public Map<String, Net> getSiteWireToNetMap()"
- com.xilinx.rapidwright.device.Device "public String getDeviceName()"
  --> "public String getName()"
- com.xilinx.rapidwright.device.Node "public Node(Tile tile, int wire)"
  --> "public static Node getNode(Tile tile, int wire)"
- com.xilinx.rapidwright.device.Node "public Node(Wire w)"
  --> "public static Node getNode(Wire wire)"
- com.xilinx.rapidwright.device.Node "public Node(Tile tile, String wireName)"
  --> "public static Node getNode(Tile tile, int wire)"
- com.xilinx.rapidwright.device.Node "public Node(String nodeName, Device dev)"
  --> "public static Node getNode(String nodeName, Device dev)"
- com.xilinx.rapidwright.device.Node "public Node(RouteNode routeNode)"
  --> "public static Node getNode(RouteNode routeNode)"
- com.xilinx.rapidwright.device.Package "public String getSiteType(String packagePinName)"
  --> "public Site getSiteFromPackagePin(String packagePinName)"
- com.xilinx.rapidwright.device.PackagePin "public String getSiteType()"
  --> "public Site getSite()"

Assets 10

04 Nov 01:36

clavin-xlnx

v2022.1.4-beta

e9ba1c5

RapidWright 2022.1.4-beta Release

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

Can now load EDIF netlist in parallel with placement and routing when reading a DCP
Allows the Design object to detach the corresponding EDIFNetlist to save working memory
Restores the original EDIFPort.getBusName() behavior
Changes EDIFPortInstList duplicate behavior from prohibit to overwrite
Net.removePin() to unset alternate source
Fix Net.removePin() for static nets under preserveOtherRoutes
Option to track process peak memory usage
Fix for #548, #572, #564
Fixes intrasite routing to CARRY pins from LUT outputs on UltraScale/+

API Additions:
- com.xilinx.rapidwright.design.Cell "public void setEDIFHierCellInst(EDIFHierCellInst inst)"
- com.xilinx.rapidwright.design.Design "public void detachNetlist()"
- com.xilinx.rapidwright.device.Node "public Collection getAllDownhillNodes(Collection nodes)"
- com.xilinx.rapidwright.device.Node "public Collection getAllUphillNodes(Collection nodes)"

Assets 10

20 Sep 05:00

clavin-xlnx

v2022.1.3-beta

61cb018

RapidWright 2022.1.3-beta Release

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

Adds support for partition pins, several new APIs added as seen below
Fixes site routing for F8MUX inputs and routethrus on CARRY pins
Fix for DCPs created with -binary_only option
Fix for DCPs that don't end with '.dcp' extension
Optimizes EDIF memory usage (see #463)
Improved handling of dual-output nets
Fixes BEL.canInvert()
Preserves BEL attributes DB in Versal DCPs

API Additions:
- com.xilinx.rapidwright.design.Cell "public void setPropertiesMap(Map<String, EDIFPropertyValue> properties)"
- com.xilinx.rapidwright.design.Cell "public List getAllCorrespondingSitePinNames(String logicalPinName, boolean considerLutRoutethru)"
- com.xilinx.rapidwright.design.Design "public boolean addPartitionPin(PartitionPin pin)"
- com.xilinx.rapidwright.design.Design "public boolean removePartitionPin(PartitionPin pin)"
- com.xilinx.rapidwright.design.Design "public List getPartitionPins()"
- com.xilinx.rapidwright.design.Design "public PartitionPin createPartitionPin(EDIFHierPortInst pin, Node node)"
- com.xilinx.rapidwright.design.Design "public PartitionPin createPartitionPin(EDIFPort port, int index, Node node)"
- com.xilinx.rapidwright.design.Design "public PartitionPin createPartitionPin(EDIFPort port, Node node)"
- com.xilinx.rapidwright.design.Design "public void unrouteSites()"
- com.xilinx.rapidwright.design.Net "public static final String Z_NET = "GLOBAL_DUMMY_ROUTE""
- com.xilinx.rapidwright.design.PartitionPin "public Tile getTile()"
- com.xilinx.rapidwright.design.PartitionPin "public String getTileName()"
- com.xilinx.rapidwright.design.PartitionPin "public void setNode(Node node)"
- com.xilinx.rapidwright.design.PartitionPin "public Node getNode()"
- com.xilinx.rapidwright.design.PartitionPin "public int getWireIndex()"
- com.xilinx.rapidwright.design.PartitionPin "public String getWireName()"
- com.xilinx.rapidwright.design.PartitionPin "public void setIsFixed(boolean isFixed)"
- com.xilinx.rapidwright.design.PartitionPin "public void setIsWireFixed(boolean isWireFixed)"
- com.xilinx.rapidwright.design.PartitionPin "public boolean isFixed()"
- com.xilinx.rapidwright.design.PartitionPin "public boolean isWireFixed()"
- com.xilinx.rapidwright.design.PartitionPin "public String getInstanceName()"
- com.xilinx.rapidwright.design.PartitionPin "public boolean isPort()"
- com.xilinx.rapidwright.design.PartitionPin "public String getTerminalName()"
- com.xilinx.rapidwright.design.PartitionPin "public String getLibCellName()"
- com.xilinx.rapidwright.design.PartitionPin "public String toString()"
- com.xilinx.rapidwright.design.SiteInst "public boolean removePin(SitePinInst sitePinInst)"

Assets 10

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