From 2a96896f258d33fca95890601a07947c99a691f4 Mon Sep 17 00:00:00 2001 From: eddieh-xlnx Date: Thu, 2 Jan 2025 10:46:09 -0800 Subject: [PATCH] Apply suggestions from code review Signed-off-by: eddieh-xlnx Signed-off-by: Eddie Hung --- .../rapidwright/design/TestDesignTools.java | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java index 75c694a39..71babfe5f 100644 --- a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java +++ b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java @@ -1476,12 +1476,8 @@ public void testGetConnectedCellsVersal() { Assertions.assertEquals("[processor/zero_flag_flop(BEL: DFF2)]", DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString()); } - // This design has no site routing for CLK - // { - // SitePinInst spi = si.getSitePinInst("CLK"); - // Assertions.assertEquals("[]", - // DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString()); - // } + // This design has no intra-site routing for CLK so this test + // does not check for connected cells as done in other tests } @Test @@ -1508,12 +1504,8 @@ public void testGetConnectedBELPinsVersal() { Assertions.assertEquals("[DFF2.CE]", DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString()); } - // This design has no site routing for CLK - // { - // SitePinInst spi = si.getSitePinInst("CLK"); - // Assertions.assertEquals("[]", - // DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString()); - // } + // This design has no intra-site routing for CLK so this test + // does not check for connected cells as done in other tests } @ParameterizedTest