diff --git a/registers/x86.xml b/registers/x86.xml
index cd785e90..011477c4 100644
--- a/registers/x86.xml
+++ b/registers/x86.xml
@@ -658,4 +658,28 @@
             <Flag bit="47" label="Base" description="Starting address of IDT"></Flag>
         </Flags>
     </Register>
+    <Register name="xmm0" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm1" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm2" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm3" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm4" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm5" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm6" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm7" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
 </InstructionSet>
diff --git a/registers/x86_64.xml b/registers/x86_64.xml
index 93af45b0..e1539d61 100644
--- a/registers/x86_64.xml
+++ b/registers/x86_64.xml
@@ -834,4 +834,292 @@ In newer CPUs, this can also be written with the WRGSBASE instruction at any pri
             <Flag bit="79" label="Base" description="Starting address of IDT (Bits 16-47 if 32 bit operand, bits 16-79 if 64 bit operand)"></Flag>
         </Flags>
     </Register>
+    <Register name="xmm0" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm1" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm2" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm3" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm4" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm5" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm6" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm7" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm8" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm9" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm10" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm11" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm12" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm13" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm14" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm15" description="A SIMD register. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm16" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm17" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm18" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm19" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm20" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm21" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm22" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm23" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm24" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm25" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm26" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm27" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm28" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm29" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm30" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="xmm31" description="A SIMD register available when AVX-512 is supported. Under SSE, this register can be used to store four 32-bit single-precision floating point numbers. SSE2 would later expand its usage to also allow two 64-bit double-precision floating point numbers, two 64-bit integers, four 32-bit integers, eight 16-bit short integers, or sixteen 8-bit bytes or characters." 
+    type="SIMD Register" width="128 bits">
+    </Register>
+    <Register name="ymm0" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm1" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm2" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm3" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm4" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm5" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm6" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm7" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm8" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm9" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm10" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm11" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm12" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm13" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm14" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm15" description="A SIMD register. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm16" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm17" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm18" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm19" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm20" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm21" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm22" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm23" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm24" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm25" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm26" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm27" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm28" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm29" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm30" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="ymm31" description="A SIMD register available when AVX-512 is supported. This register can be used to store four 64-bit double-precision floating point numbers, or eight 32-bit single precision floating point numbers. The lower half maps onto the corresponding XMM register." 
+    type="SIMD Register" width="256 bits">
+    </Register>
+    <Register name="zmm0" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm1" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm2" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm3" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm4" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm5" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm6" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm7" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm8" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm9" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm10" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm11" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm12" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm13" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm14" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm15" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm16" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm17" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm18" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm19" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm20" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm21" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm22" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm23" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm24" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm25" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm26" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm27" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm28" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm29" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm30" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
+    <Register name="zmm31" description="A SIMD register. The lower half maps onto the corresponding YMM register." 
+    type="SIMD Register" width="512 bits">
+    </Register>
 </InstructionSet>
diff --git a/samples/gas.s b/samples/gas.s
index 328af5ee..51fd6f7f 100644
--- a/samples/gas.s
+++ b/samples/gas.s
@@ -21,6 +21,7 @@ main:
 	.cfi_def_cfa_offset 16
 	.cfi_offset 6, -16
 	movq	%rsp, %rbp
+    %zmm0
 	.cfi_def_cfa_register 6
 	subq	$32, %rsp
 	MOVLPS
diff --git a/src/types.rs b/src/types.rs
index 50421b54..9b0ae02b 100644
--- a/src/types.rs
+++ b/src/types.rs
@@ -336,8 +336,12 @@ pub enum RegisterType {
 
 #[derive(Debug, Hash, PartialEq, Eq, Clone, Copy, EnumString, AsRefStr, Display)]
 pub enum RegisterWidth {
-    #[strum(serialize = "80 bits")]
-    Bits80,
+    #[strum(serialize = "512 bits")]
+    Bits512,
+    #[strum(serialize = "256 bits")]
+    Bits256,
+    #[strum(serialize = "128 bits")]
+    Bits128,
     #[strum(serialize = "32(64) bits")]
     Bits32Or64,
     #[strum(serialize = "64 bits")]