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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/projects/tt_um_ajstein_stopwatch/commit_id.json b/projects/tt_um_ajstein_stopwatch/commit_id.json new file mode 100644 index 0000000..f2f1d3d --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/commit_id.json @@ -0,0 +1,9 @@ +{ + "app": "Tiny Tapeout tt07 68e6da5b", + "repo": "https://github.com/aj-stein-nist/tt_stopwatch_project", + "commit": "f65b4932e00ecbc9090ad2f631bb6f8d29d80ed1", + "workflow_url": "https://github.com/aj-stein-nist/tt_stopwatch_project/actions/runs/9037224514", + "sort_id": 1715371848811, + "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b", + "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943" +} \ No newline at end of file diff --git a/projects/tt_um_ajstein_stopwatch/docs/info.md b/projects/tt_um_ajstein_stopwatch/docs/info.md new file mode 100644 index 0000000..45d29ab --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/docs/info.md @@ -0,0 +1,22 @@ + + +## How it works + +This is a Tiny Tapeout project (designed to start for Tiny Tapeout 7 in May 2024) to use the 20 MHz of the ASIC chip to make a stopwatch that can count seconds in decimal format for ten second increments (from 0 to 9 and loops back to 0). + +## How to test + +This is a simple project and has limited testing infrastructure. To test in simulation and analyze changes to the logic with a waveform analyzer, you can use [the published MakerChip project](https://mest.makerchip.com/sandbox/0DkfBhkK5/0k5hO4j#) associated with this GitHub repo and check the `clock_speed` to have smaller clock speeds and increment the decimal stopwatch much quicker than the necessary hardware clock speed. + +To test this with a Tiny Tapeout 3 Demo Board (v 2.2.5) and the ASIC Simulator (v1.2) using [this test harness repo](https://github.com/aj-stein-nist/tt_stopwatch_project_fpga.git) and use `dfu-util` to flash it on this device. + +## External hardware + +This project is a simple first experiment that does not require additional external inputs or outputs. diff --git a/projects/tt_um_ajstein_stopwatch/info.yaml b/projects/tt_um_ajstein_stopwatch/info.yaml new file mode 100644 index 0000000..730d172 --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/info.yaml @@ -0,0 +1,52 @@ +# Tiny Tapeout project information +project: + title: "Stopwatch Project" + author: "A.J. Stein" + description: "A TinyTapeout project to display a stopwatch counter one digit at a time" + language: "Verilog" + clock_hz: 20000000 + + # How many tiles your design occupies? A single tile is about 167x108 uM. + tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 + + # Your top module name must start with "tt_um_". Make it unique by including your github username: + top_module: "tt_um_ajstein_stopwatch" + + # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: + source_files: + - "project.v" + +# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. +pinout: + # Inputs + ui[0]: "N/A" + ui[1]: "N/A" + ui[2]: "N/A" + ui[3]: "N/A" + ui[4]: "N/A" + ui[5]: "N/A" + ui[6]: "N/A" + ui[7]: "N/A" + + # Outputs + uo[0]: "N/A" + uo[1]: "N/A" + uo[2]: "N/A" + uo[3]: "N/A" + uo[4]: "N/A" + uo[5]: "N/A" + uo[6]: "N/A" + uo[7]: "N/A" + + # Bidirectional pins + uio[0]: "N/A" + uio[1]: "N/A" + uio[2]: "N/A" + uio[3]: "N/A" + uio[4]: "N/A" + uio[5]: "N/A" + uio[6]: "N/A" + uio[7]: "N/A" + +# Do not change! +yaml_version: 6 diff --git a/projects/tt_um_ajstein_stopwatch/stats/metrics.csv b/projects/tt_um_ajstein_stopwatch/stats/metrics.csv new file mode 100644 index 0000000..0f8694a --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/stats/metrics.csv @@ -0,0 +1,2 @@ +design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY +/work/src,tt_um_ajstein_stopwatch,wokwi,flow completed,0h1m2s0ms,0h0m45s0ms,31635.135496404288,0.01795472,15817.567748202144,14.67,16.287399999999998,523.79,261,0,0,0,0,0,0,0,0,0,0,-1,-1,3697,1628,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,2582128.0,0.0,8.32,5.62,0.49,0.08,-1,311,500,59,248,0,0,0,339,3,36,20,7,130,31,2,5,37,51,13,1108,225,0,288,284,1905,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0 diff --git a/projects/tt_um_ajstein_stopwatch/stats/synthesis-stats.txt b/projects/tt_um_ajstein_stopwatch/stats/synthesis-stats.txt new file mode 100644 index 0000000..78b8d26 --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/stats/synthesis-stats.txt @@ -0,0 +1,52 @@ + +63. Printing statistics. + +=== tt_um_ajstein_stopwatch === + + Number of wires: 245 + Number of wire bits: 280 + Number of public wires: 128 + Number of public wire bits: 163 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 261 + sky130_fd_sc_hd__a211oi_2 1 + sky130_fd_sc_hd__a21o_2 9 + sky130_fd_sc_hd__a21oi_2 9 + sky130_fd_sc_hd__a221o_2 1 + sky130_fd_sc_hd__a221oi_2 1 + sky130_fd_sc_hd__a22o_2 1 + sky130_fd_sc_hd__a22oi_2 1 + sky130_fd_sc_hd__a31o_2 5 + sky130_fd_sc_hd__a41o_2 1 + sky130_fd_sc_hd__and2_2 12 + sky130_fd_sc_hd__and3_2 13 + sky130_fd_sc_hd__and3b_2 7 + sky130_fd_sc_hd__and4_2 8 + sky130_fd_sc_hd__and4b_2 2 + sky130_fd_sc_hd__buf_1 22 + sky130_fd_sc_hd__buf_2 30 + sky130_fd_sc_hd__conb_1 27 + sky130_fd_sc_hd__dfxtp_2 36 + sky130_fd_sc_hd__inv_2 6 + sky130_fd_sc_hd__nand2_2 6 + sky130_fd_sc_hd__nand3_2 5 + sky130_fd_sc_hd__nor2_2 14 + sky130_fd_sc_hd__nor2b_2 1 + sky130_fd_sc_hd__nor3_2 1 + sky130_fd_sc_hd__nor4_2 1 + sky130_fd_sc_hd__o2111a_2 1 + sky130_fd_sc_hd__o211a_2 3 + sky130_fd_sc_hd__o21a_2 4 + sky130_fd_sc_hd__o21ai_2 14 + sky130_fd_sc_hd__or2_2 5 + sky130_fd_sc_hd__or2b_2 1 + sky130_fd_sc_hd__or3b_2 2 + sky130_fd_sc_hd__or4_2 4 + sky130_fd_sc_hd__or4b_2 5 + sky130_fd_sc_hd__or4bb_2 1 + sky130_fd_sc_hd__xnor2_2 1 + + Chip area for module '\tt_um_ajstein_stopwatch': 2334.739200 + diff --git a/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.gds b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.gds new file mode 100644 index 0000000..e614bfb Binary files /dev/null and b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.gds differ diff --git a/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.lef b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.lef new file mode 100644 index 0000000..fe5c5ef --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.lef @@ -0,0 +1,495 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO tt_um_ajstein_stopwatch + CLASS BLOCK ; + FOREIGN tt_um_ajstein_stopwatch ; + ORIGIN 0.000 0.000 ; + SIZE 161.000 BY 111.520 ; + PIN VGND + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 40.830 2.480 42.430 109.040 ; + END + PORT + LAYER met4 ; + RECT 79.700 2.480 81.300 109.040 ; + END + PORT + LAYER met4 ; + RECT 118.570 2.480 120.170 109.040 ; + END + PORT + LAYER met4 ; + RECT 157.440 2.480 159.040 109.040 ; + END + END VGND + PIN VPWR + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 21.395 2.480 22.995 109.040 ; + END + PORT + LAYER met4 ; + RECT 60.265 2.480 61.865 109.040 ; + END + PORT + LAYER met4 ; + RECT 99.135 2.480 100.735 109.040 ; + END + PORT + LAYER met4 ; + RECT 138.005 2.480 139.605 109.040 ; + END + END VPWR + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.852000 ; + PORT + LAYER met4 ; + RECT 154.870 110.520 155.170 111.520 ; + END + END clk + PIN ena + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 158.550 110.520 158.850 111.520 ; + END + END ena + PIN rst_n + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; + PORT + LAYER met4 ; + RECT 151.190 110.520 151.490 111.520 ; + END + END rst_n + PIN ui_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 147.510 110.520 147.810 111.520 ; + END + END ui_in[0] + PIN ui_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 143.830 110.520 144.130 111.520 ; + END + END ui_in[1] + PIN ui_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 140.150 110.520 140.450 111.520 ; + END + END ui_in[2] + PIN ui_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 136.470 110.520 136.770 111.520 ; + END + END ui_in[3] + PIN ui_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 132.790 110.520 133.090 111.520 ; + END + END ui_in[4] + PIN ui_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 129.110 110.520 129.410 111.520 ; + END + END ui_in[5] + PIN ui_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 125.430 110.520 125.730 111.520 ; + END + END ui_in[6] + PIN ui_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.318000 ; + PORT + LAYER met4 ; + RECT 121.750 110.520 122.050 111.520 ; + END + END ui_in[7] + PIN uio_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 118.070 110.520 118.370 111.520 ; + END + END uio_in[0] + PIN uio_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 114.390 110.520 114.690 111.520 ; + END + END uio_in[1] + PIN uio_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 110.710 110.520 111.010 111.520 ; + END + END uio_in[2] + PIN uio_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 107.030 110.520 107.330 111.520 ; + END + END uio_in[3] + PIN uio_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 103.350 110.520 103.650 111.520 ; + END + END uio_in[4] + PIN uio_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 99.670 110.520 99.970 111.520 ; + END + END uio_in[5] + PIN uio_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 95.990 110.520 96.290 111.520 ; + END + END uio_in[6] + PIN uio_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 92.310 110.520 92.610 111.520 ; + END + END uio_in[7] + PIN uio_oe[0] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 29.750 110.520 30.050 111.520 ; + END + END uio_oe[0] + PIN uio_oe[1] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 26.070 110.520 26.370 111.520 ; + END + END uio_oe[1] + PIN uio_oe[2] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 22.390 110.520 22.690 111.520 ; + END + END uio_oe[2] + PIN uio_oe[3] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 18.710 110.520 19.010 111.520 ; + END + END uio_oe[3] + PIN uio_oe[4] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 15.030 110.520 15.330 111.520 ; + END + END uio_oe[4] + PIN uio_oe[5] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 11.350 110.520 11.650 111.520 ; + END + END uio_oe[5] + PIN uio_oe[6] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 7.670 110.520 7.970 111.520 ; + END + END uio_oe[6] + PIN uio_oe[7] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 3.990 110.520 4.290 111.520 ; + END + END uio_oe[7] + PIN uio_out[0] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 59.190 110.520 59.490 111.520 ; + END + END uio_out[0] + PIN uio_out[1] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 55.510 110.520 55.810 111.520 ; + END + END uio_out[1] + PIN uio_out[2] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 51.830 110.520 52.130 111.520 ; + END + END uio_out[2] + PIN uio_out[3] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 48.150 110.520 48.450 111.520 ; + END + END uio_out[3] + PIN uio_out[4] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 44.470 110.520 44.770 111.520 ; + END + END uio_out[4] + PIN uio_out[5] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 40.790 110.520 41.090 111.520 ; + END + END uio_out[5] + PIN uio_out[6] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 37.110 110.520 37.410 111.520 ; + END + END uio_out[6] + PIN uio_out[7] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 33.430 110.520 33.730 111.520 ; + END + END uio_out[7] + PIN uo_out[0] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 88.630 110.520 88.930 111.520 ; + END + END uo_out[0] + PIN uo_out[1] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + ANTENNADIFFAREA 0.795200 ; + PORT + LAYER met4 ; + RECT 84.950 110.520 85.250 111.520 ; + END + END uo_out[1] + PIN uo_out[2] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 81.270 110.520 81.570 111.520 ; + END + END uo_out[2] + PIN uo_out[3] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 77.590 110.520 77.890 111.520 ; + END + END uo_out[3] + PIN uo_out[4] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 73.910 110.520 74.210 111.520 ; + END + END uo_out[4] + PIN uo_out[5] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 70.230 110.520 70.530 111.520 ; + END + END uo_out[5] + PIN uo_out[6] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; + PORT + LAYER met4 ; + RECT 66.550 110.520 66.850 111.520 ; + END + END uo_out[6] + PIN uo_out[7] + DIRECTION OUTPUT TRISTATE ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 62.870 110.520 63.170 111.520 ; + END + END uo_out[7] + OBS + LAYER nwell ; + RECT 2.570 107.385 158.430 108.990 ; + RECT 2.570 101.945 158.430 104.775 ; + RECT 2.570 96.505 158.430 99.335 ; + RECT 2.570 91.065 158.430 93.895 ; + RECT 2.570 85.625 158.430 88.455 ; + RECT 2.570 80.185 158.430 83.015 ; + RECT 2.570 74.745 158.430 77.575 ; + RECT 2.570 69.305 158.430 72.135 ; + RECT 2.570 63.865 158.430 66.695 ; + RECT 2.570 58.425 158.430 61.255 ; + RECT 2.570 52.985 158.430 55.815 ; + RECT 2.570 47.545 158.430 50.375 ; + RECT 2.570 42.105 158.430 44.935 ; + RECT 2.570 36.665 158.430 39.495 ; + RECT 2.570 31.225 158.430 34.055 ; + RECT 2.570 25.785 158.430 28.615 ; + RECT 2.570 20.345 158.430 23.175 ; + RECT 2.570 14.905 158.430 17.735 ; + RECT 2.570 9.465 158.430 12.295 ; + RECT 2.570 4.025 158.430 6.855 ; + LAYER li1 ; + RECT 2.760 2.635 158.240 108.885 ; + LAYER met1 ; + RECT 2.760 2.480 159.040 109.040 ; + LAYER met2 ; + RECT 4.230 2.535 159.010 110.005 ; + LAYER met3 ; + RECT 3.950 2.555 159.030 109.985 ; + LAYER met4 ; + RECT 4.690 110.120 7.270 110.520 ; + RECT 8.370 110.120 10.950 110.520 ; + RECT 12.050 110.120 14.630 110.520 ; + RECT 15.730 110.120 18.310 110.520 ; + RECT 19.410 110.120 21.990 110.520 ; + RECT 23.090 110.120 25.670 110.520 ; + RECT 26.770 110.120 29.350 110.520 ; + RECT 30.450 110.120 33.030 110.520 ; + RECT 34.130 110.120 36.710 110.520 ; + RECT 37.810 110.120 40.390 110.520 ; + RECT 41.490 110.120 44.070 110.520 ; + RECT 45.170 110.120 47.750 110.520 ; + RECT 48.850 110.120 51.430 110.520 ; + RECT 52.530 110.120 55.110 110.520 ; + RECT 56.210 110.120 58.790 110.520 ; + RECT 59.890 110.120 62.470 110.520 ; + RECT 63.570 110.120 66.150 110.520 ; + RECT 67.250 110.120 69.830 110.520 ; + RECT 70.930 110.120 73.510 110.520 ; + RECT 74.610 110.120 77.190 110.520 ; + RECT 78.290 110.120 80.870 110.520 ; + RECT 81.970 110.120 84.550 110.520 ; + RECT 85.650 110.120 88.230 110.520 ; + RECT 89.330 110.120 91.910 110.520 ; + RECT 93.010 110.120 95.590 110.520 ; + RECT 96.690 110.120 99.270 110.520 ; + RECT 100.370 110.120 102.950 110.520 ; + RECT 104.050 110.120 106.630 110.520 ; + RECT 107.730 110.120 110.310 110.520 ; + RECT 111.410 110.120 113.990 110.520 ; + RECT 115.090 110.120 117.670 110.520 ; + RECT 118.770 110.120 121.350 110.520 ; + RECT 122.450 110.120 125.030 110.520 ; + RECT 126.130 110.120 128.710 110.520 ; + RECT 129.810 110.120 132.390 110.520 ; + RECT 133.490 110.120 136.070 110.520 ; + RECT 137.170 110.120 139.750 110.520 ; + RECT 140.850 110.120 143.430 110.520 ; + RECT 144.530 110.120 147.110 110.520 ; + RECT 148.210 110.120 150.790 110.520 ; + RECT 151.890 110.120 154.470 110.520 ; + RECT 3.975 109.440 155.185 110.120 ; + RECT 3.975 89.255 20.995 109.440 ; + RECT 23.395 89.255 40.430 109.440 ; + RECT 42.830 89.255 59.865 109.440 ; + RECT 62.265 89.255 79.300 109.440 ; + RECT 81.700 89.255 98.735 109.440 ; + RECT 101.135 89.255 118.170 109.440 ; + RECT 120.570 89.255 137.605 109.440 ; + RECT 140.005 89.255 155.185 109.440 ; + END +END tt_um_ajstein_stopwatch +END LIBRARY + diff --git a/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.spef b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.spef new file mode 100644 index 0000000..d713bf2 --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.spef @@ -0,0 +1,9802 @@ +*SPEF "ieee 1481-1999" +*DESIGN "tt_um_ajstein_stopwatch" +*DATE "20:06:41 Friday May 10, 2024" +*VENDOR "The OpenROAD Project" +*PROGRAM "OpenROAD" +*VERSION "da0053d7b0014ab9c87ea148875ff6c2a0f9b658" +*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE" +*DIVIDER / +*DELIMITER : +*BUS_DELIMITER [] +*T_UNIT 1 NS +*C_UNIT 1 PF +*R_UNIT 1 OHM +*L_UNIT 1 HENRY + +*NAME_MAP +*3 clk +*4 ena +*5 rst_n +*6 ui_in[0] +*7 ui_in[1] +*8 ui_in[2] +*9 ui_in[3] +*10 ui_in[4] +*11 ui_in[5] +*12 ui_in[6] +*13 ui_in[7] +*14 uio_in[0] +*15 uio_in[1] +*16 uio_in[2] +*17 uio_in[3] +*18 uio_in[4] +*19 uio_in[5] +*20 uio_in[6] +*21 uio_in[7] +*22 net2 +*23 net3 +*24 net4 +*25 net5 +*26 net6 +*27 net7 +*28 net8 +*29 net9 +*30 net10 +*31 net11 +*32 net12 +*33 net13 +*34 net14 +*35 net15 +*36 net16 +*37 net17 +*38 uo_out[0] +*39 uo_out[1] +*40 uo_out[2] +*41 uo_out[3] +*42 uo_out[4] +*43 uo_out[5] +*44 uo_out[6] +*45 net18 +*46 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[0\] +*47 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[1\] +*48 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[2\] +*49 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[3\] +*50 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[4\] +*51 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[5\] +*52 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[6\] +*53 DEBUG_SIGS_GTKWAVE\.\@0\$slideswitch\[7\] +*54 DEBUG_SIGS_GTKWAVE\.\@0\$sseg_segment_n\[0\] +*55 DEBUG_SIGS_GTKWAVE\.\@0\$sseg_segment_n\[1\] +*56 DEBUG_SIGS_GTKWAVE\.\@0\$sseg_segment_n\[2\] +*57 DEBUG_SIGS_GTKWAVE\.\@0\$sseg_segment_n\[3\] +*58 DEBUG_SIGS_GTKWAVE\.\@0\$sseg_segment_n\[4\] +*59 DEBUG_SIGS_GTKWAVE\.\@0\$sseg_segment_n\[5\] +*60 DEBUG_SIGS_GTKWAVE\.\@0\$sseg_segment_n\[6\] +*61 DEBUG_SIGS_GTKWAVE\.\/digit\[0\]\.\/leds\[0\]\.\/\/\@0\$viz_lit +*62 DEBUG_SIGS_GTKWAVE\.\/digit\[0\]\.\/leds\[1\]\.\/\/\@0\$viz_lit +*63 DEBUG_SIGS_GTKWAVE\.\/digit\[0\]\.\/leds\[2\]\.\/\/\@0\$viz_lit +*64 DEBUG_SIGS_GTKWAVE\.\/digit\[0\]\.\/leds\[3\]\.\/\/\@0\$viz_lit +*65 DEBUG_SIGS_GTKWAVE\.\/digit\[0\]\.\/leds\[4\]\.\/\/\@0\$viz_lit +*66 DEBUG_SIGS_GTKWAVE\.\/digit\[0\]\.\/leds\[5\]\.\/\/\@0\$viz_lit +*67 DEBUG_SIGS_GTKWAVE\.\/digit\[0\]\.\/leds\[6\]\.\/\/\@0\$viz_lit +*68 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[0\] +*69 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[10\] +*70 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[11\] +*71 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[12\] +*72 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[13\] +*73 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[14\] +*74 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[15\] +*75 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[16\] +*76 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[17\] +*77 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[18\] +*78 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[19\] +*79 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[1\] +*80 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[20\] +*81 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[21\] +*82 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[22\] +*83 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[23\] +*84 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[24\] +*85 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[25\] +*86 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[26\] +*87 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[27\] +*88 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[28\] +*89 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[29\] +*90 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[2\] +*91 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[30\] +*92 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[31\] +*93 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[3\] +*94 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[4\] +*95 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[5\] +*96 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[6\] +*97 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[7\] +*98 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[8\] +*99 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$cycle_counter\[9\] +*100 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$display_counter\[0\] +*101 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$display_counter\[1\] +*102 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$display_counter\[2\] +*103 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$display_counter\[3\] +*104 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$reset +*105 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$segments\[0\] +*106 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$segments\[1\] +*107 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$segments\[2\] +*108 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$segments\[3\] +*109 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$segments\[4\] +*110 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$segments\[5\] +*111 DEBUG_SIGS_GTKWAVE\.\/fpga_pins\.\/fpga\.\/\/\@0\$segments\[6\] +*112 DEBUG_SIGS_GTKWAVE\.\/switch\[0\]\.\/\@0\$viz_switch +*113 DEBUG_SIGS_GTKWAVE\.\/switch\[1\]\.\/\@0\$viz_switch +*114 DEBUG_SIGS_GTKWAVE\.\/switch\[2\]\.\/\@0\$viz_switch +*115 DEBUG_SIGS_GTKWAVE\.\/switch\[3\]\.\/\@0\$viz_switch +*116 DEBUG_SIGS_GTKWAVE\.\/switch\[4\]\.\/\@0\$viz_switch +*117 DEBUG_SIGS_GTKWAVE\.\/switch\[5\]\.\/\@0\$viz_switch +*118 DEBUG_SIGS_GTKWAVE\.\/switch\[6\]\.\/\@0\$viz_switch +*119 DEBUG_SIGS_GTKWAVE\.\/switch\[7\]\.\/\@0\$viz_switch +*120 FpgaPins_Fpga_cycle_counter_a1\[0\] +*121 FpgaPins_Fpga_cycle_counter_a1\[10\] +*122 FpgaPins_Fpga_cycle_counter_a1\[11\] +*123 FpgaPins_Fpga_cycle_counter_a1\[12\] +*124 FpgaPins_Fpga_cycle_counter_a1\[13\] +*125 FpgaPins_Fpga_cycle_counter_a1\[14\] +*126 FpgaPins_Fpga_cycle_counter_a1\[15\] +*127 FpgaPins_Fpga_cycle_counter_a1\[16\] +*128 FpgaPins_Fpga_cycle_counter_a1\[17\] +*129 FpgaPins_Fpga_cycle_counter_a1\[18\] +*130 FpgaPins_Fpga_cycle_counter_a1\[19\] +*131 FpgaPins_Fpga_cycle_counter_a1\[1\] +*132 FpgaPins_Fpga_cycle_counter_a1\[20\] +*133 FpgaPins_Fpga_cycle_counter_a1\[21\] +*134 FpgaPins_Fpga_cycle_counter_a1\[22\] +*135 FpgaPins_Fpga_cycle_counter_a1\[23\] +*136 FpgaPins_Fpga_cycle_counter_a1\[24\] +*137 FpgaPins_Fpga_cycle_counter_a1\[25\] +*138 FpgaPins_Fpga_cycle_counter_a1\[26\] +*139 FpgaPins_Fpga_cycle_counter_a1\[27\] +*140 FpgaPins_Fpga_cycle_counter_a1\[28\] +*141 FpgaPins_Fpga_cycle_counter_a1\[29\] +*142 FpgaPins_Fpga_cycle_counter_a1\[2\] +*143 FpgaPins_Fpga_cycle_counter_a1\[30\] +*144 FpgaPins_Fpga_cycle_counter_a1\[31\] +*145 FpgaPins_Fpga_cycle_counter_a1\[3\] +*146 FpgaPins_Fpga_cycle_counter_a1\[4\] +*147 FpgaPins_Fpga_cycle_counter_a1\[5\] +*148 FpgaPins_Fpga_cycle_counter_a1\[6\] +*149 FpgaPins_Fpga_cycle_counter_a1\[7\] +*150 FpgaPins_Fpga_cycle_counter_a1\[8\] +*151 FpgaPins_Fpga_cycle_counter_a1\[9\] +*152 FpgaPins_Fpga_display_counter_a1\[0\] +*153 FpgaPins_Fpga_display_counter_a1\[1\] +*154 FpgaPins_Fpga_display_counter_a1\[2\] +*155 FpgaPins_Fpga_display_counter_a1\[3\] +*156 _000_ +*157 _001_ +*158 _002_ +*159 _003_ +*160 _004_ +*161 _005_ +*162 _006_ +*163 _007_ +*164 _008_ +*165 _009_ +*166 _010_ +*167 _011_ +*168 _012_ +*169 _013_ +*170 _014_ +*171 _015_ +*172 _016_ +*173 _017_ +*174 _018_ +*175 _019_ +*176 _020_ +*177 _021_ +*178 _022_ +*179 _023_ +*180 _024_ +*181 _025_ +*182 _026_ +*183 _027_ +*184 _028_ +*185 _029_ +*186 _030_ +*187 _031_ +*188 _032_ +*189 _033_ +*190 _034_ +*191 _035_ +*192 _036_ +*193 _037_ +*194 _038_ +*195 _039_ +*196 _040_ +*197 _041_ +*198 _042_ +*199 _043_ +*200 _044_ +*201 _045_ +*202 _046_ +*203 _047_ +*204 _048_ +*205 _049_ +*206 _050_ +*207 _051_ +*208 _052_ +*209 _053_ +*210 _054_ +*211 _055_ +*212 _056_ +*213 _057_ +*214 _058_ +*215 _059_ +*216 _060_ +*217 _061_ +*218 _062_ +*219 _063_ +*220 _064_ +*221 _065_ +*222 _066_ +*223 _067_ +*224 _068_ +*225 _069_ +*226 _070_ +*227 _071_ +*228 _072_ +*229 _073_ +*230 _074_ +*231 _075_ +*232 _076_ +*233 _077_ +*234 _078_ +*235 _079_ +*236 _080_ +*237 _081_ +*238 _082_ +*239 _083_ +*240 _084_ +*241 _085_ +*242 _086_ +*243 _087_ +*244 _088_ +*245 _089_ +*246 _090_ +*247 _091_ +*248 _092_ +*249 _093_ +*250 _094_ +*251 _095_ +*252 _096_ +*253 _097_ +*254 _098_ +*255 _099_ +*256 _100_ +*257 _101_ +*258 _102_ +*259 _103_ +*260 _104_ +*261 _105_ +*262 _106_ +*263 _107_ +*264 _108_ +*265 _109_ +*266 _110_ +*267 _111_ +*268 _112_ +*269 _113_ +*270 _114_ +*271 _115_ +*272 _116_ +*273 clknet_0_clk +*274 clknet_2_0__leaf_clk +*275 clknet_2_1__leaf_clk +*276 clknet_2_2__leaf_clk +*277 clknet_2_3__leaf_clk +*278 net1 +*279 net19 +*280 net20 +*281 net21 +*282 net22 +*283 net23 +*284 net24 +*285 net25 +*286 net26 +*287 net27 +*288 net28 +*289 net29 +*290 net30 +*291 net31 +*292 net32 +*293 net33 +*294 net34 +*295 net35 +*296 net36 +*297 net37 +*298 net38 +*299 net39 +*300 net40 +*301 net41 +*302 net42 +*303 net43 +*304 net44 +*305 net45 +*306 FILLER_0_0_109 +*307 FILLER_0_0_113 +*308 FILLER_0_0_125 +*309 FILLER_0_0_137 +*310 FILLER_0_0_141 +*311 FILLER_0_0_15 +*312 FILLER_0_0_153 +*313 FILLER_0_0_165 +*314 FILLER_0_0_169 +*315 FILLER_0_0_181 +*316 FILLER_0_0_193 +*317 FILLER_0_0_197 +*318 FILLER_0_0_209 +*319 FILLER_0_0_221 +*320 FILLER_0_0_225 +*321 FILLER_0_0_237 +*322 FILLER_0_0_249 +*323 FILLER_0_0_253 +*324 FILLER_0_0_265 +*325 FILLER_0_0_27 +*326 FILLER_0_0_277 +*327 FILLER_0_0_281 +*328 FILLER_0_0_29 +*329 FILLER_0_0_293 +*330 FILLER_0_0_3 +*331 FILLER_0_0_305 +*332 FILLER_0_0_309 +*333 FILLER_0_0_321 +*334 FILLER_0_0_333 +*335 FILLER_0_0_41 +*336 FILLER_0_0_53 +*337 FILLER_0_0_57 +*338 FILLER_0_0_69 +*339 FILLER_0_0_81 +*340 FILLER_0_0_85 +*341 FILLER_0_0_97 +*342 FILLER_0_10_109 +*343 FILLER_0_10_121 +*344 FILLER_0_10_133 +*345 FILLER_0_10_139 +*346 FILLER_0_10_141 +*347 FILLER_0_10_15 +*348 FILLER_0_10_153 +*349 FILLER_0_10_165 +*350 FILLER_0_10_177 +*351 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TAP_TAPCELL_ROW_28_241 +*1822 TAP_TAPCELL_ROW_28_242 +*1823 TAP_TAPCELL_ROW_29_243 +*1824 TAP_TAPCELL_ROW_29_244 +*1825 TAP_TAPCELL_ROW_29_245 +*1826 TAP_TAPCELL_ROW_29_246 +*1827 TAP_TAPCELL_ROW_29_247 +*1828 TAP_TAPCELL_ROW_2_94 +*1829 TAP_TAPCELL_ROW_2_95 +*1830 TAP_TAPCELL_ROW_2_96 +*1831 TAP_TAPCELL_ROW_2_97 +*1832 TAP_TAPCELL_ROW_2_98 +*1833 TAP_TAPCELL_ROW_2_99 +*1834 TAP_TAPCELL_ROW_30_248 +*1835 TAP_TAPCELL_ROW_30_249 +*1836 TAP_TAPCELL_ROW_30_250 +*1837 TAP_TAPCELL_ROW_30_251 +*1838 TAP_TAPCELL_ROW_30_252 +*1839 TAP_TAPCELL_ROW_30_253 +*1840 TAP_TAPCELL_ROW_31_254 +*1841 TAP_TAPCELL_ROW_31_255 +*1842 TAP_TAPCELL_ROW_31_256 +*1843 TAP_TAPCELL_ROW_31_257 +*1844 TAP_TAPCELL_ROW_31_258 +*1845 TAP_TAPCELL_ROW_32_259 +*1846 TAP_TAPCELL_ROW_32_260 +*1847 TAP_TAPCELL_ROW_32_261 +*1848 TAP_TAPCELL_ROW_32_262 +*1849 TAP_TAPCELL_ROW_32_263 +*1850 TAP_TAPCELL_ROW_32_264 +*1851 TAP_TAPCELL_ROW_33_265 +*1852 TAP_TAPCELL_ROW_33_266 +*1853 TAP_TAPCELL_ROW_33_267 +*1854 TAP_TAPCELL_ROW_33_268 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TAP_TAPCELL_ROW_38_302 +*1889 TAP_TAPCELL_ROW_3_100 +*1890 TAP_TAPCELL_ROW_3_101 +*1891 TAP_TAPCELL_ROW_3_102 +*1892 TAP_TAPCELL_ROW_3_103 +*1893 TAP_TAPCELL_ROW_3_104 +*1894 TAP_TAPCELL_ROW_4_105 +*1895 TAP_TAPCELL_ROW_4_106 +*1896 TAP_TAPCELL_ROW_4_107 +*1897 TAP_TAPCELL_ROW_4_108 +*1898 TAP_TAPCELL_ROW_4_109 +*1899 TAP_TAPCELL_ROW_4_110 +*1900 TAP_TAPCELL_ROW_5_111 +*1901 TAP_TAPCELL_ROW_5_112 +*1902 TAP_TAPCELL_ROW_5_113 +*1903 TAP_TAPCELL_ROW_5_114 +*1904 TAP_TAPCELL_ROW_5_115 +*1905 TAP_TAPCELL_ROW_6_116 +*1906 TAP_TAPCELL_ROW_6_117 +*1907 TAP_TAPCELL_ROW_6_118 +*1908 TAP_TAPCELL_ROW_6_119 +*1909 TAP_TAPCELL_ROW_6_120 +*1910 TAP_TAPCELL_ROW_6_121 +*1911 TAP_TAPCELL_ROW_7_122 +*1912 TAP_TAPCELL_ROW_7_123 +*1913 TAP_TAPCELL_ROW_7_124 +*1914 TAP_TAPCELL_ROW_7_125 +*1915 TAP_TAPCELL_ROW_7_126 +*1916 TAP_TAPCELL_ROW_8_127 +*1917 TAP_TAPCELL_ROW_8_128 +*1918 TAP_TAPCELL_ROW_8_129 +*1919 TAP_TAPCELL_ROW_8_130 +*1920 TAP_TAPCELL_ROW_8_131 +*1921 TAP_TAPCELL_ROW_8_132 +*1922 TAP_TAPCELL_ROW_9_133 +*1923 TAP_TAPCELL_ROW_9_134 +*1924 TAP_TAPCELL_ROW_9_135 +*1925 TAP_TAPCELL_ROW_9_136 +*1926 TAP_TAPCELL_ROW_9_137 +*1927 _117_ +*1928 _118_ +*1929 _119_ +*1930 _120_ +*1931 _121_ +*1932 _122_ +*1933 _123_ +*1934 _124_ +*1935 _125_ +*1936 _126_ +*1937 _127_ +*1938 _128_ +*1939 _129_ +*1940 _130_ +*1941 _131_ +*1942 _132_ +*1943 _133_ +*1944 _134_ +*1945 _135_ +*1946 _136_ +*1947 _137_ +*1948 _138_ +*1949 _139_ +*1950 _140_ +*1951 _141_ +*1952 _142_ +*1953 _143_ +*1954 _144_ +*1955 _145_ +*1956 _146_ +*1957 _147_ +*1958 _148_ +*1959 _149_ +*1960 _150_ +*1961 _151_ +*1962 _152_ +*1963 _153_ +*1964 _154_ +*1965 _155_ +*1966 _156_ +*1967 _157_ +*1968 _158_ +*1969 _159_ +*1970 _160_ +*1971 _161_ +*1972 _162_ +*1973 _163_ +*1974 _164_ +*1975 _165_ +*1976 _166_ +*1977 _167_ +*1978 _168_ +*1979 _169_ +*1980 _170_ +*1981 _171_ +*1982 _172_ +*1983 _173_ +*1984 _174_ +*1985 _175_ +*1986 _176_ +*1987 _177_ +*1988 _178_ +*1989 _179_ +*1990 _180_ +*1991 _181_ +*1992 _182_ +*1993 _183_ +*1994 _184_ +*1995 _185_ +*1996 _186_ +*1997 _187_ +*1998 _188_ +*1999 _189_ +*2000 _190_ +*2001 _191_ +*2002 _192_ +*2003 _193_ +*2004 _194_ +*2005 _195_ +*2006 _196_ +*2007 _197_ +*2008 _198_ +*2009 _199_ +*2010 _200_ +*2011 _201_ +*2012 _202_ +*2013 _203_ +*2014 _204_ +*2015 _205_ +*2016 _206_ +*2017 _207_ +*2018 _208_ +*2019 _209_ +*2020 _210_ +*2021 _211_ +*2022 _212_ +*2023 _213_ +*2024 _214_ +*2025 _215_ +*2026 _216_ +*2027 _217_ +*2028 _218_ +*2029 _219_ +*2030 _220_ +*2031 _221_ +*2032 _222_ +*2033 _223_ +*2034 _224_ +*2035 _225_ +*2036 _226_ +*2037 _227_ +*2038 _228_ +*2039 _229_ +*2040 _230_ +*2041 _231_ +*2042 _232_ +*2043 _233_ +*2044 _234_ +*2045 _235_ +*2046 _236_ +*2047 _237_ +*2048 _238_ +*2049 _239_ +*2050 _240_ +*2051 _241_ +*2052 _242_ +*2053 _243_ +*2054 _244_ +*2055 _245_ +*2056 _246_ +*2057 _247_ +*2058 _248_ +*2059 _249_ +*2060 _250_ +*2061 _251_ +*2062 _252_ +*2063 _253_ +*2064 _254_ +*2065 _255_ +*2066 _256_ +*2067 _257_ +*2068 _258_ +*2069 _259_ +*2070 _260_ +*2071 _261_ +*2072 _262_ +*2073 _263_ +*2074 _264_ +*2075 _265_ +*2076 _266_ +*2077 _267_ +*2078 _268_ +*2079 _269_ +*2080 _270_ +*2081 _271_ +*2082 _272_ +*2083 _273_ +*2084 _274_ +*2085 _275_ +*2086 _276_ +*2087 _277_ +*2088 _278_ +*2089 _279_ +*2090 _280_ +*2091 _281_ +*2092 _282_ +*2093 _283_ +*2094 _284_ +*2095 _285_ +*2096 _286_ +*2097 _287_ +*2098 _288_ +*2099 _289_ +*2100 _290_ +*2101 _291_ +*2102 _292_ +*2103 _293_ +*2104 _294_ +*2105 _295_ +*2106 _296_ +*2107 _297_ +*2108 _298_ +*2109 _299_ +*2110 _300_ +*2111 _301_ +*2112 _302_ +*2113 _303_ +*2114 _304_ +*2115 _305_ +*2116 _306_ +*2117 _307_ +*2118 _308_ +*2119 _309_ +*2120 _310_ +*2121 _311_ +*2122 _312_ +*2123 _313_ +*2124 _314_ +*2125 _315_ +*2126 _316_ +*2127 _317_ +*2128 _318_ +*2129 _319_ +*2130 _320_ +*2131 _348_ +*2132 _349_ +*2133 _350_ +*2134 _351_ +*2135 _352_ +*2136 _353_ +*2137 _354_ +*2138 _355_ +*2139 _356_ +*2140 _357_ +*2141 _358_ +*2142 _359_ +*2143 _360_ +*2144 _361_ +*2145 _362_ +*2146 _363_ +*2147 _364_ +*2148 _365_ +*2149 _366_ +*2150 _367_ +*2151 _368_ +*2152 _369_ +*2153 _370_ +*2154 _371_ +*2155 _372_ +*2156 _373_ +*2157 _374_ +*2158 _375_ +*2159 _376_ +*2160 _377_ +*2161 clkbuf_0_clk +*2162 clkbuf_2_0__f_clk +*2163 clkbuf_2_1__f_clk +*2164 clkbuf_2_2__f_clk +*2165 clkbuf_2_3__f_clk +*2166 hold1 +*2167 hold10 +*2168 hold11 +*2169 hold12 +*2170 hold13 +*2171 hold14 +*2172 hold15 +*2173 hold16 +*2174 hold17 +*2175 hold18 +*2176 hold19 +*2177 hold2 +*2178 hold20 +*2179 hold21 +*2180 hold22 +*2181 hold23 +*2182 hold24 +*2183 hold25 +*2184 hold26 +*2185 hold27 +*2186 hold3 +*2187 hold4 +*2188 hold5 +*2189 hold6 +*2190 hold7 +*2191 hold8 +*2192 hold9 +*2193 input1 +*2194 tt_um_ajstein_stopwatch_10 +*2195 tt_um_ajstein_stopwatch_11 +*2196 tt_um_ajstein_stopwatch_12 +*2197 tt_um_ajstein_stopwatch_13 +*2198 tt_um_ajstein_stopwatch_14 +*2199 tt_um_ajstein_stopwatch_15 +*2200 tt_um_ajstein_stopwatch_16 +*2201 tt_um_ajstein_stopwatch_17 +*2202 tt_um_ajstein_stopwatch_18 +*2203 tt_um_ajstein_stopwatch_2 +*2204 tt_um_ajstein_stopwatch_3 +*2205 tt_um_ajstein_stopwatch_4 +*2206 tt_um_ajstein_stopwatch_5 +*2207 tt_um_ajstein_stopwatch_6 +*2208 tt_um_ajstein_stopwatch_7 +*2209 tt_um_ajstein_stopwatch_8 +*2210 tt_um_ajstein_stopwatch_9 + +*PORTS +clk I +ena I +rst_n I +ui_in[0] I +ui_in[1] I +ui_in[2] I +ui_in[3] I +ui_in[4] I +ui_in[5] I +ui_in[6] I +ui_in[7] I +uio_in[0] I +uio_in[1] I +uio_in[2] I +uio_in[3] I +uio_in[4] I +uio_in[5] I +uio_in[6] I +uio_in[7] I +uio_oe[0] O +uio_oe[1] O +uio_oe[2] O +uio_oe[3] O +uio_oe[4] O +uio_oe[5] O +uio_oe[6] O +uio_oe[7] O +uio_out[0] O +uio_out[1] O +uio_out[2] O +uio_out[3] O +uio_out[4] O +uio_out[5] O +uio_out[6] O +uio_out[7] O +uo_out[0] O +uo_out[1] O +uo_out[2] O +uo_out[3] O +uo_out[4] O +uo_out[5] O +uo_out[6] O +uo_out[7] O + +*D_NET *3 0.00706781 +*CONN +*P clk I +*I *2161:A I *D sky130_fd_sc_hd__clkbuf_16 +*CAP +1 clk 0.00321645 +2 *2161:A 0.00321645 +3 *2161:A *2045:A1 0.000108229 +4 *2161:A *2048:C 6.69276e-05 +5 *2161:A *2193:A 1.86598e-05 +6 *2161:A *6:15 0 +7 *2161:A *163:12 0.000154762 +8 *2161:A *277:63 0.000286334 +*RES +1 clk *2161:A 31.9065 +*END + +*D_NET *5 0.000809218 +*CONN +*P rst_n I +*I *2193:A I *D sky130_fd_sc_hd__clkbuf_2 +*CAP +1 rst_n 0.000339778 +2 *2193:A 0.000339778 +3 *2193:A *6:15 3.32266e-05 +4 *2193:A *278:18 7.77751e-05 +5 *2161:A *2193:A 1.86598e-05 +*RES +1 rst_n *2193:A 24.6556 +*END + +*D_NET *6 0.000831855 +*CONN +*P ui_in[0] I +*I *2141:A I *D sky130_fd_sc_hd__buf_2 +*I *2139:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[0] 0.000348921 +2 *2141:A 3.47527e-05 +3 *2139:A 0 +4 *6:15 0.000383674 +5 *6:15 *7:17 3.12806e-05 +6 *2161:A *6:15 0 +7 *2193:A *6:15 3.32266e-05 +*RES +1 ui_in[0] *6:15 12.9469 +2 *6:15 *2139:A 9.3 +3 *6:15 *2141:A 9.83571 +*END + +*D_NET *7 0.000815039 +*CONN +*P ui_in[1] I +*I *2142:A I *D sky130_fd_sc_hd__buf_2 +*I *2138:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[1] 0.0003483 +2 *2142:A 2.79386e-05 +3 *2138:A 0 +4 *7:17 0.000376239 +5 *7:17 *2140:A 0 +6 *7:17 *8:13 3.12806e-05 +7 *6:15 *7:17 3.12806e-05 +*RES +1 ui_in[1] *7:17 14.0158 +2 *7:17 *2138:A 9.3 +3 *7:17 *2142:A 9.83571 +*END + +*D_NET *8 0.00110195 +*CONN +*P ui_in[2] I +*I *2143:A I *D sky130_fd_sc_hd__buf_2 +*I *2140:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[2] 0.000300468 +2 *2143:A 0 +3 *2140:A 0.000163991 +4 *8:13 0.000464459 +5 *2140:A *1995:B 7.43578e-06 +6 *2140:A *1995:C 8.69386e-05 +7 *2140:A *147:6 2.77258e-05 +8 *8:13 *9:17 1.96473e-05 +9 *7:17 *2140:A 0 +10 *7:17 *8:13 3.12806e-05 +*RES +1 ui_in[2] *8:13 8.15862 +2 *8:13 *2140:A 16.9964 +3 *8:13 *2143:A 13.8 +*END + +*D_NET *9 0.000861352 +*CONN +*P ui_in[3] I +*I *2144:A I *D sky130_fd_sc_hd__buf_2 +*I *2150:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[3] 0.000377207 +2 *2144:A 2.80047e-05 +3 *2150:A 0 +4 *9:17 0.000405212 +5 *9:17 *10:15 3.12806e-05 +6 *8:13 *9:17 1.96473e-05 +*RES +1 ui_in[3] *9:17 13.6771 +2 *9:17 *2150:A 9.3 +3 *9:17 *2144:A 9.83571 +*END + +*D_NET *10 0.000788592 +*CONN +*P ui_in[4] I +*I *2145:A I *D sky130_fd_sc_hd__buf_2 +*I *2153:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[4] 0.000328263 +2 *2145:A 3.47527e-05 +3 *2153:A 0 +4 *10:15 0.000363015 +5 *10:15 *11:15 3.12806e-05 +6 *9:17 *10:15 3.12806e-05 +*RES +1 ui_in[4] *10:15 12.8748 +2 *10:15 *2153:A 9.3 +3 *10:15 *2145:A 9.83571 +*END + +*D_NET *11 0.000794547 +*CONN +*P ui_in[5] I +*I *2152:A I *D sky130_fd_sc_hd__buf_2 +*I *2146:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[5] 0.0003068 +2 *2152:A 5.91929e-05 +3 *2146:A 0 +4 *11:15 0.000365993 +5 *11:15 *12:15 3.12806e-05 +6 *10:15 *11:15 3.12806e-05 +*RES +1 ui_in[5] *11:15 12.8028 +2 *11:15 *2146:A 9.3 +3 *11:15 *2152:A 10.2464 +*END + +*D_NET *12 0.000745666 +*CONN +*P ui_in[6] I +*I *2151:A I *D sky130_fd_sc_hd__buf_2 +*I *2147:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[6] 0.0003068 +2 *2151:A 3.47527e-05 +3 *2147:A 0 +4 *12:15 0.000341553 +5 *12:15 *13:15 3.12806e-05 +6 *11:15 *12:15 3.12806e-05 +*RES +1 ui_in[6] *12:15 12.8028 +2 *12:15 *2147:A 9.3 +3 *12:15 *2151:A 9.83571 +*END + +*D_NET *13 0.000750475 +*CONN +*P ui_in[7] I +*I *2148:A I *D sky130_fd_sc_hd__buf_2 +*I *2149:A I *D sky130_fd_sc_hd__buf_2 +*CAP +1 ui_in[7] 0.000324845 +2 *2148:A 3.47527e-05 +3 *2149:A 0 +4 *13:15 0.000359597 +5 *12:15 *13:15 3.12806e-05 +*RES +1 ui_in[7] *13:15 12.8028 +2 *13:15 *2149:A 9.3 +3 *13:15 *2148:A 9.83571 +*END + +*D_NET *22 0.000397559 +*CONN +*P uio_oe[0] O +*I *2203:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[0] 0.000173808 +2 *2203:LO 0.000173808 +3 uio_oe[0] uio_oe[1] 2.49709e-05 +4 uio_oe[0] uio_out[7] 2.49709e-05 +*RES +1 *2203:LO uio_oe[0] 21.4044 +*END + +*D_NET *23 0.000415653 +*CONN +*P uio_oe[1] O +*I *2204:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[1] 0.000189409 +2 *2204:LO 0.000189409 +3 uio_oe[1] uio_oe[2] 1.18636e-05 +4 uio_oe[1] uio_oe[3] 0 +5 uio_oe[0] uio_oe[1] 2.49709e-05 +*RES +1 *2204:LO uio_oe[1] 21.4044 +*END + +*D_NET *24 0.000586403 +*CONN +*P uio_oe[2] O +*I *2205:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[2] 0.000280523 +2 *2205:LO 0.000280523 +3 uio_oe[2] uio_oe[3] 1.34925e-05 +4 uio_oe[1] uio_oe[2] 1.18636e-05 +*RES +1 *2205:LO uio_oe[2] 23.0134 +*END + +*D_NET *25 0.000399299 +*CONN +*P uio_oe[3] O +*I *2206:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[3] 0.000180418 +2 *2206:LO 0.000180418 +3 uio_oe[3] uio_oe[4] 2.49709e-05 +4 uio_oe[1] uio_oe[3] 0 +5 uio_oe[2] uio_oe[3] 1.34925e-05 +*RES +1 *2206:LO uio_oe[3] 21.4044 +*END + +*D_NET *26 0.000489475 +*CONN +*P uio_oe[4] O +*I *2207:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[4] 0.000219767 +2 *2207:LO 0.000219767 +3 uio_oe[4] uio_oe[5] 2.49709e-05 +4 uio_oe[3] uio_oe[4] 2.49709e-05 +*RES +1 *2207:LO uio_oe[4] 21.5485 +*END + +*D_NET *27 0.000397559 +*CONN +*P uio_oe[5] O +*I *2208:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[5] 0.000173808 +2 *2208:LO 0.000173808 +3 uio_oe[5] uio_oe[6] 2.49709e-05 +4 uio_oe[4] uio_oe[5] 2.49709e-05 +*RES +1 *2208:LO uio_oe[5] 21.4044 +*END + +*D_NET *28 0.000397559 +*CONN +*P uio_oe[6] O +*I *2209:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[6] 0.000173808 +2 *2209:LO 0.000173808 +3 uio_oe[6] uio_oe[7] 2.49709e-05 +4 uio_oe[5] uio_oe[6] 2.49709e-05 +*RES +1 *2209:LO uio_oe[6] 21.4044 +*END + +*D_NET *29 0.000395728 +*CONN +*P uio_oe[7] O +*I *2210:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_oe[7] 0.000185379 +2 *2210:LO 0.000185379 +3 uio_oe[6] uio_oe[7] 2.49709e-05 +*RES +1 *2210:LO uio_oe[7] 21.4044 +*END + +*D_NET *30 0.000419324 +*CONN +*P uio_out[0] O +*I *2194:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[0] 0.000187353 +2 *2194:LO 0.000187353 +3 uio_out[0] uio_out[1] 2.49709e-05 +4 uio_out[0] uo_out[7] 1.96473e-05 +*RES +1 *2194:LO uio_out[0] 21.4044 +*END + +*D_NET *31 0.000397559 +*CONN +*P uio_out[1] O +*I *2195:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[1] 0.000173808 +2 *2195:LO 0.000173808 +3 uio_out[1] uio_out[2] 2.49709e-05 +4 uio_out[0] uio_out[1] 2.49709e-05 +*RES +1 *2195:LO uio_out[1] 21.4044 +*END + +*D_NET *32 0.000397559 +*CONN +*P uio_out[2] O +*I *2196:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[2] 0.000173808 +2 *2196:LO 0.000173808 +3 uio_out[2] uio_out[3] 2.49709e-05 +4 uio_out[1] uio_out[2] 2.49709e-05 +*RES +1 *2196:LO uio_out[2] 21.4044 +*END + +*D_NET *33 0.000397559 +*CONN +*P uio_out[3] O +*I *2197:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[3] 0.000173808 +2 *2197:LO 0.000173808 +3 uio_out[3] uio_out[4] 2.49709e-05 +4 uio_out[2] uio_out[3] 2.49709e-05 +*RES +1 *2197:LO uio_out[3] 21.4044 +*END + +*D_NET *34 0.000405317 +*CONN +*P uio_out[4] O +*I *2198:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[4] 0.000184241 +2 *2198:LO 0.000184241 +3 uio_out[4] uio_out[5] 1.18636e-05 +4 uio_out[4] uio_out[6] 0 +5 uio_out[3] uio_out[4] 2.49709e-05 +*RES +1 *2198:LO uio_out[4] 21.4044 +*END + +*D_NET *35 0.000597216 +*CONN +*P uio_out[5] O +*I *2199:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[5] 0.00028593 +2 *2199:LO 0.00028593 +3 uio_out[5] uio_out[6] 1.34925e-05 +4 uio_out[4] uio_out[5] 1.18636e-05 +*RES +1 *2199:LO uio_out[5] 23.0134 +*END + +*D_NET *36 0.000397025 +*CONN +*P uio_out[6] O +*I *2200:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[6] 0.000179281 +2 *2200:LO 0.000179281 +3 uio_out[6] uio_out[7] 2.49709e-05 +4 uio_out[4] uio_out[6] 0 +5 uio_out[5] uio_out[6] 1.34925e-05 +*RES +1 *2200:LO uio_out[6] 21.4044 +*END + +*D_NET *37 0.000397559 +*CONN +*P uio_out[7] O +*I *2201:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uio_out[7] 0.000173808 +2 *2201:LO 0.000173808 +3 uio_oe[0] uio_out[7] 2.49709e-05 +4 uio_out[6] uio_out[7] 2.49709e-05 +*RES +1 *2201:LO uio_out[7] 21.4044 +*END + +*D_NET *38 0.000611102 +*CONN +*P uo_out[0] O +*I *2154:X O *D sky130_fd_sc_hd__buf_2 +*CAP +1 uo_out[0] 0.000226153 +2 *2154:X 0.000226153 +3 uo_out[0] uo_out[1] 0.000158797 +*RES +1 *2154:X uo_out[0] 21.5485 +*END + +*D_NET *39 0.0018195 +*CONN +*P uo_out[1] O +*I *2155:X O *D sky130_fd_sc_hd__clkbuf_4 +*CAP +1 uo_out[1] 0.000804143 +2 *2155:X 0.000804143 +3 uo_out[1] uo_out[2] 1.18636e-05 +4 uo_out[1] uo_out[3] 0 +5 uo_out[1] *2155:A 4.0552e-05 +6 uo_out[0] uo_out[1] 0.000158797 +*RES +1 *2155:X uo_out[1] 26.8578 +*END + +*D_NET *40 0.000648095 +*CONN +*P uo_out[2] O +*I *2156:X O *D sky130_fd_sc_hd__buf_2 +*CAP +1 uo_out[2] 0.000310036 +2 *2156:X 0.000310036 +3 uo_out[2] uo_out[3] 1.61603e-05 +4 uo_out[1] uo_out[2] 1.18636e-05 +*RES +1 *2156:X uo_out[2] 23.1575 +*END + +*D_NET *41 0.000870111 +*CONN +*P uo_out[3] O +*I *2157:X O *D sky130_fd_sc_hd__buf_2 +*CAP +1 uo_out[3] 0.00041449 +2 *2157:X 0.00041449 +3 uo_out[3] uo_out[4] 2.49709e-05 +4 uo_out[1] uo_out[3] 0 +5 uo_out[2] uo_out[3] 1.61603e-05 +*RES +1 *2157:X uo_out[3] 21.9089 +*END + +*D_NET *42 0.000397515 +*CONN +*P uo_out[4] O +*I *2158:X O *D sky130_fd_sc_hd__buf_2 +*CAP +1 uo_out[4] 0.000173787 +2 *2158:X 0.000173787 +3 uo_out[4] uo_out[5] 2.49709e-05 +4 uo_out[3] uo_out[4] 2.49709e-05 +*RES +1 *2158:X uo_out[4] 21.4044 +*END + +*D_NET *43 0.000489483 +*CONN +*P uo_out[5] O +*I *2159:X O *D sky130_fd_sc_hd__buf_2 +*CAP +1 uo_out[5] 0.00021977 +2 *2159:X 0.00021977 +3 uo_out[5] uo_out[6] 2.49709e-05 +4 uo_out[4] uo_out[5] 2.49709e-05 +*RES +1 *2159:X uo_out[5] 21.5485 +*END + +*D_NET *44 0.000446557 +*CONN +*P uo_out[6] O +*I *2160:X O *D sky130_fd_sc_hd__buf_2 +*CAP +1 uo_out[6] 0.000198308 +2 *2160:X 0.000198308 +3 uo_out[6] uo_out[7] 2.49709e-05 +4 uo_out[5] uo_out[6] 2.49709e-05 +*RES +1 *2160:X uo_out[6] 21.4765 +*END + +*D_NET *45 0.00041727 +*CONN +*P uo_out[7] O +*I *2202:LO O *D sky130_fd_sc_hd__conb_1 +*CAP +1 uo_out[7] 0.000186326 +2 *2202:LO 0.000186326 +3 uio_out[0] uo_out[7] 1.96473e-05 +4 uo_out[6] uo_out[7] 2.49709e-05 +*RES +1 *2202:LO uo_out[7] 21.4044 +*END + +*D_NET *61 0.000464802 +*CONN +*I *2154:A I *D sky130_fd_sc_hd__buf_2 +*I *2088:Y O *D sky130_fd_sc_hd__a22oi_1 +*CAP +1 *2154:A 0.000193095 +2 *2088:Y 0.000193095 +3 *2154:A *2088:A1 0 +4 *2154:A *2157:A 0 +5 *2154:A *254:32 0 +6 *2154:A *255:12 0 +7 *2154:A *255:16 2.14658e-05 +8 *2154:A *255:24 5.71472e-05 +*RES +1 *2088:Y *2154:A 31.1 +*END + +*D_NET *62 0.000355724 +*CONN +*I *2155:A I *D sky130_fd_sc_hd__clkbuf_4 +*I *2089:Y O *D sky130_fd_sc_hd__nand3_1 +*CAP +1 *2155:A 0.000157586 +2 *2089:Y 0.000157586 +3 *2155:A *2132:A 0 +4 uo_out[1] *2155:A 4.0552e-05 +*RES +1 *2089:Y *2155:A 30.2964 +*END + +*D_NET *63 0.000707279 +*CONN +*I *2156:A I *D sky130_fd_sc_hd__buf_2 +*I *2091:X O *D sky130_fd_sc_hd__clkbuf_1 +*CAP +1 *2156:A 0.000353639 +2 *2091:X 0.000353639 +3 *2156:A *2157:A 0 +*RES +1 *2091:X *2156:A 32.7786 +*END + +*D_NET *64 0.000364451 +*CONN +*I *2157:A I *D sky130_fd_sc_hd__buf_2 +*I *2092:Y O *D sky130_fd_sc_hd__a221oi_1 +*CAP +1 *2157:A 0.000153652 +2 *2092:Y 0.000153652 +3 *2157:A *2092:B1 5.71472e-05 +4 *2154:A *2157:A 0 +5 *2156:A *2157:A 0 +*RES +1 *2092:Y *2157:A 29.7786 +*END + +*D_NET *65 0.000186505 +*CONN +*I *2158:A I *D sky130_fd_sc_hd__buf_2 +*I *2093:Y O *D sky130_fd_sc_hd__o21ai_1 +*CAP +1 *2158:A 9.32525e-05 +2 *2093:Y 9.32525e-05 +3 *2158:A *2159:A 0 +*RES +1 *2093:Y *2158:A 29.2429 +*END + +*D_NET *66 0.000384359 +*CONN +*I *2159:A I *D sky130_fd_sc_hd__buf_2 +*I *2094:Y O *D sky130_fd_sc_hd__a21oi_1 +*CAP +1 *2159:A 0.000154835 +2 *2094:Y 0.000154835 +3 *2159:A *2160:A 0 +4 *2159:A *251:36 5.58941e-05 +5 *2159:A *258:41 1.87955e-05 +6 *2158:A *2159:A 0 +*RES +1 *2094:Y *2159:A 30.4571 +*END + +*D_NET *67 0.000683158 +*CONN +*I *2160:A I *D sky130_fd_sc_hd__buf_2 +*I *2073:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2160:A 0.000325475 +2 *2073:Y 0.000325475 +3 *2160:A *2073:B 2.47724e-05 +4 *2160:A *251:12 7.43578e-06 +5 *2160:A *251:36 0 +6 *2160:A *258:41 0 +7 *2159:A *2160:A 0 +*RES +1 *2073:Y *2160:A 32.6179 +*END + +*D_NET *68 0.000658001 +*CONN +*I *2099:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1978:Y O *D sky130_fd_sc_hd__nand2_1 +*CAP +1 *2099:D 0.000261025 +2 *1978:Y 0.000261025 +3 *2099:D *1931:A_N 4.72917e-05 +4 *2099:D *1931:B 5.52238e-05 +5 *2099:D *2101:CLK 3.34366e-05 +6 *2099:D *163:42 0 +*RES +1 *1978:Y *2099:D 31.7607 +*END + +*D_NET *69 0.000902305 +*CONN +*I *2109:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1948:Y O *D sky130_fd_sc_hd__a21oi_1 +*CAP +1 *2109:D 0.000307809 +2 *1948:Y 0.000307809 +3 *2109:D *2005:A1 0 +4 *2109:D *2109:CLK 0.000145973 +5 *2109:D *163:42 0.000140714 +6 *2109:D *169:10 0 +*RES +1 *1948:Y *2109:D 32.6045 +*END + +*D_NET *70 0.00184608 +*CONN +*I *2110:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1953:X O *D sky130_fd_sc_hd__clkbuf_1 +*CAP +1 *2110:D 0.000703644 +2 *1953:X 0.000703644 +3 *2110:D *2110:CLK 0.000169349 +4 *2110:D *122:10 8.42801e-05 +5 *2110:D *275:10 2.07878e-05 +6 *2110:D *275:56 0.00016438 +*RES +1 *1953:X *2110:D 28.9973 +*END + +*D_NET *71 0.000140934 +*CONN +*I *2171:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *2003:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2171:A 4.45863e-05 +2 *2003:Y 4.45863e-05 +3 *2171:A *163:63 5.17614e-05 +*RES +1 *2003:Y *2171:A 19.5464 +*END + +*D_NET *72 0.000344627 +*CONN +*I *2112:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1958:X O *D sky130_fd_sc_hd__clkbuf_1 +*CAP +1 *2112:D 9.60976e-05 +2 *1958:X 9.60976e-05 +3 *2112:D *1958:A 2.25554e-05 +4 *2112:D *2112:CLK 0.000129877 +*RES +1 *1958:X *2112:D 20.658 +*END + +*D_NET *73 0.00182264 +*CONN +*I *2113:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2006:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2113:D 0.000518193 +2 *2006:Y 0.000518193 +3 *2113:D *2006:A 0.000134844 +4 *2113:D *2007:A2 2.89114e-05 +5 *2113:D *125:19 0.000482594 +6 *2113:D *125:43 0.000139907 +*RES +1 *2006:Y *2113:D 29.4438 +*END + +*D_NET *74 0.00226105 +*CONN +*I *2114:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2008:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2114:D 0.000693187 +2 *2008:Y 0.000693187 +3 *2114:D *1959:A 5.7661e-06 +4 *2114:D *1959:C 0.000300951 +5 *2114:D *2007:B1 2.54632e-05 +6 *2114:D *2008:A 9.22103e-06 +7 *2114:D *2008:B 3.18676e-05 +8 *2114:D *2114:CLK 5.49544e-05 +9 *2114:D *126:10 7.20005e-05 +10 *2114:D *126:19 0.0003248 +11 *2114:D *126:38 4.96499e-05 +*RES +1 *2008:Y *2114:D 30.2295 +*END + +*D_NET *75 0.000505596 +*CONN +*I *2115:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1962:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2115:D 0.000169074 +2 *1962:Y 0.000169074 +3 *2115:D *1962:A 0 +4 *2115:D *2115:CLK 1.5546e-05 +5 *2115:D *274:60 0.000151903 +*RES +1 *1962:Y *2115:D 22.0643 +*END + +*D_NET *76 0.000451019 +*CONN +*I *2116:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2011:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2116:D 0.000184452 +2 *2011:Y 0.000184452 +3 *2116:D *2011:B 7.92879e-05 +4 *2116:D *274:73 2.8266e-06 +*RES +1 *2011:Y *2116:D 30.658 +*END + +*D_NET *77 0.000453457 +*CONN +*I *2117:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2014:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2117:D 0.000137288 +2 *2014:Y 0.000137288 +3 *2117:D *2013:B1 5.80706e-06 +4 *2117:D *2014:A 0.000151333 +5 *2117:D *2014:B 5.30637e-06 +6 *2117:D *274:44 1.64343e-05 +*RES +1 *2014:Y *2117:D 30.2473 +*END + +*D_NET *78 0.000333825 +*CONN +*I *2118:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2016:X O *D sky130_fd_sc_hd__o211a_1 +*CAP +1 *2118:D 9.62401e-05 +2 *2016:X 9.62401e-05 +3 *2118:D *1963:C 1.69142e-05 +4 *2118:D *2016:A2 0 +5 *2118:D *2118:CLK 0.00012443 +*RES +1 *2016:X *2118:D 20.8321 +*END + +*D_NET *79 0.00114262 +*CONN +*I *2180:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *1980:Y O *D sky130_fd_sc_hd__a21oi_1 +*CAP +1 *2180:A 0.000393107 +2 *1980:Y 0.000393107 +3 *2180:A *1980:A1 0.000124735 +4 *2180:A *1980:B1 0.000148903 +5 *2180:A *2179:A 5.52302e-05 +6 *2180:A *120:16 1.02504e-05 +7 *2180:A *187:24 1.72894e-05 +8 *2180:A *280:10 0 +*RES +1 *1980:Y *2180:A 34.725 +*END + +*D_NET *80 0.00082218 +*CONN +*I *2119:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1967:Y O *D sky130_fd_sc_hd__a21oi_1 +*CAP +1 *2119:D 0.000304655 +2 *1967:Y 0.000304655 +3 *2119:D *163:42 3.51442e-05 +4 *2119:D *274:14 7.27028e-05 +5 *2119:D *274:20 0.000105024 +*RES +1 *1967:Y *2119:D 33.0152 +*END + +*D_NET *81 0.000864815 +*CONN +*I *2120:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1972:X O *D sky130_fd_sc_hd__clkbuf_1 +*CAP +1 *2120:D 0.000387898 +2 *1972:X 0.000387898 +3 *2120:D *133:10 8.90199e-05 +4 *2120:D *134:12 0 +*RES +1 *1972:X *2120:D 34.6402 +*END + +*D_NET *82 0.000248487 +*CONN +*I *2121:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2019:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2121:D 0.000124243 +2 *2019:Y 0.000124243 +*RES +1 *2019:Y *2121:D 29.7116 +*END + +*D_NET *83 0.000406339 +*CONN +*I *2122:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2021:X O *D sky130_fd_sc_hd__o211a_1 +*CAP +1 *2122:D 0.000132613 +2 *2021:X 0.000132613 +3 *2122:D *276:39 8.16036e-05 +4 *2122:D *276:41 5.95099e-05 +*RES +1 *2021:X *2122:D 30.4259 +*END + +*D_NET *84 0.000578876 +*CONN +*I *2123:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *1976:Y O *D sky130_fd_sc_hd__a21oi_1 +*CAP +1 *2123:D 0.000240582 +2 *1976:Y 0.000240582 +3 *2123:D *135:10 0 +4 *2123:D *185:25 9.77118e-05 +*RES +1 *1976:Y *2123:D 31.35 +*END + +*D_NET *85 0.000202933 +*CONN +*I *2124:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2026:X O *D sky130_fd_sc_hd__clkbuf_1 +*CAP +1 *2124:D 9.32494e-05 +2 *2026:X 9.32494e-05 +3 *2124:D *2025:B 0 +4 *2124:D *2025:C 0 +5 *2124:D *137:8 1.64343e-05 +*RES +1 *2026:X *2124:D 29.1045 +*END + +*D_NET *86 0.000494377 +*CONN +*I *2125:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2028:X O *D sky130_fd_sc_hd__o21a_1 +*CAP +1 *2125:D 0.000121991 +2 *2028:X 0.000121991 +3 *2125:D *1977:A 0.00010326 +4 *2125:D *276:31 0.000147136 +5 *2125:D *276:39 0 +*RES +1 *2028:X *2125:D 30.3366 +*END + +*D_NET *87 0.000206905 +*CONN +*I *2126:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2032:X O *D sky130_fd_sc_hd__clkbuf_1 +*CAP +1 *2126:D 7.92576e-05 +2 *2032:X 7.92576e-05 +3 *2126:D *2032:A 3.92757e-05 +4 *2126:D *2124:CLK 9.11365e-06 +*RES +1 *2032:X *2126:D 29.1045 +*END + +*D_NET *88 0.000727496 +*CONN +*I *2127:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2035:Y O *D sky130_fd_sc_hd__nor2_1 +*CAP +1 *2127:D 0.000163709 +2 *2035:Y 0.000163709 +3 *2127:D *2034:A1 1.08359e-05 +4 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*2024:A2 0 +23 *136:19 *2025:A_N 6.74815e-05 +24 *136:19 *2025:B 0 +25 *136:21 *2024:A2 9.92409e-05 +26 *2027:B1 *2022:B 4.35768e-05 +*RES +1 *2123:Q *136:8 15.4429 +2 *136:8 *2188:A 13.8 +3 *136:8 *136:19 6.44643 +4 *136:19 *136:21 1.76786 +5 *136:21 *2022:B 13.4429 +6 *136:21 *1929:D_N 22.3 +7 *136:19 *2024:A1 10.6571 +*END + +*D_NET *137 0.002783 +*CONN +*I *1929:A I *D sky130_fd_sc_hd__or4b_1 +*I *2022:A I *D sky130_fd_sc_hd__and2_1 +*I *2024:B1 I *D sky130_fd_sc_hd__a21o_1 +*I *2124:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *1929:A 0.000145418 +2 *2022:A 5.73075e-05 +3 *2024:B1 0 +4 *2124:Q 0.000463742 +5 *137:17 0.000539488 +6 *137:8 0.000800504 +7 *1929:A *1929:C 1.33343e-05 +8 *1929:A *2027:A1 0.000100831 +9 *1929:A *216:17 8.61508e-05 +10 *2022:A *2027:A1 5.86454e-05 +11 *2022:A *2028:B1 5.49489e-05 +12 *137:8 *2124:CLK 7.50473e-05 +13 *137:17 *2024:A2 0.000167988 +14 *137:17 *2027:A1 4.18895e-05 +15 *137:17 *2124:CLK 1.3701e-05 +16 *2022:B *2022:A 1.20417e-05 +17 *2022:B *137:17 2.07382e-05 +18 *2024:A1 *137:17 1.15281e-05 +19 *2027:B1 *1929:A 0.000103267 +20 *2124:D *137:8 1.64343e-05 +*RES +1 *2124:Q *137:8 17.55 +2 *137:8 *2024:B1 9.3 +3 *137:8 *137:17 6.19643 +4 *137:17 *2022:A 10.675 +5 *137:17 *1929:A 21.7464 +*END + +*D_NET *138 0.00191986 +*CONN +*I *2173:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *2030:A1 I *D sky130_fd_sc_hd__a21o_1 +*I *2029:B I *D sky130_fd_sc_hd__and3_1 +*I *1929:C I *D sky130_fd_sc_hd__or4b_1 +*I *2125:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *2173:A 3.5968e-05 +2 *2030:A1 0 +3 *2029:B 0.000137642 +4 *1929:C 9.20937e-05 +5 *2125:Q 0.000223143 +6 *138:14 0.00025114 +7 *138:12 0.000125871 +8 *138:8 0.000363578 +9 *1929:C *1929:B 7.3237e-05 +10 *1929:C *216:17 3.14048e-05 +11 *1929:C *216:30 2.95726e-05 +12 *1929:C *216:43 1.56e-05 +13 *2029:B *1929:B 4.58976e-05 +14 *2029:B *139:16 0.00022459 +15 *2029:B *216:43 3.30237e-05 +16 *2029:B *220:10 5.33005e-05 +17 *2173:A *220:10 0 +18 *138:8 *276:31 9.58508e-05 +19 *138:8 *294:16 3.13687e-05 +20 *138:12 *1929:B 5.80706e-06 +21 *138:12 *2025:A_N 0 +22 *138:12 *2027:A2 1.78353e-05 +23 *138:12 *220:10 0 +24 *138:14 *2030:A2 9.35228e-06 +25 *1929:A *1929:C 1.33343e-05 +26 *1929:D_N *138:12 1.02504e-05 +27 *2027:B1 *2173:A 0 +*RES +1 *2125:Q *138:8 16.8 +2 *138:8 *138:12 6.14286 +3 *138:12 *138:14 0.428571 +4 *138:14 *1929:C 11.4786 +5 *138:14 *2029:B 13.0321 +6 *138:12 *2030:A1 9.3 +7 *138:8 *2173:A 14.5321 +*END + +*D_NET *139 0.0026281 +*CONN +*I *2029:A I *D sky130_fd_sc_hd__and3_1 +*I *2030:B1 I *D sky130_fd_sc_hd__a21o_1 +*I *1929:B I *D sky130_fd_sc_hd__or4b_1 +*I *2126:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *2029:A 0 +2 *2030:B1 0 +3 *1929:B 0.000203563 +4 *2126:Q 0.000635078 +5 *139:16 0.000310387 +6 *139:12 0.000741902 +7 *1929:B *2025:A_N 2.66026e-05 +8 *139:12 *2031:C 9.90431e-05 +9 *139:16 *2029:C 6.84179e-05 +10 *139:16 *2031:C 4.8344e-05 +11 *139:16 *216:43 0.000120512 +12 *1929:C *1929:B 7.3237e-05 +13 *1929:D_N *1929:B 2.47186e-05 +14 *2029:B *1929:B 4.58976e-05 +15 *2029:B *139:16 0.00022459 +16 *138:12 *1929:B 5.80706e-06 +*RES +1 *2126:Q *139:12 28.3893 +2 *139:12 *139:16 3.42857 +3 *139:16 *1929:B 21.5143 +4 *139:16 *2030:B1 9.3 +5 *139:12 *2029:A 9.3 +*END + +*D_NET *140 0.00448326 +*CONN +*I *2175:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *2036:B I *D sky130_fd_sc_hd__and2_1 +*I *1928:B I *D sky130_fd_sc_hd__or4_1 +*I *2033:A I *D sky130_fd_sc_hd__and2_1 +*I *2127:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *2175:A 0.000368746 +2 *2036:B 0.000225015 +3 *1928:B 0 +4 *2033:A 7.37925e-05 +5 *2127:Q 0.000396289 +6 *140:25 0.000301334 +7 *140:14 0.000457071 +8 *140:6 0.00107199 +9 *2033:A *2034:A2 5.52302e-05 +10 *2033:A *223:8 3.97677e-05 +11 *2036:B *1928:A 5.83233e-05 +12 *2036:B *1928:C 0.000221163 +13 *2036:B *2036:A 0.000206481 +14 *2036:B *2037:B 0.00012073 +15 *2036:B *2038:A2 1.08359e-05 +16 *2036:B *2130:CLK 0.000112418 +17 *2036:B *141:21 0.00012401 +18 *2036:B *162:12 2.91794e-05 +19 *2036:B *220:49 2.31791e-05 +20 *2036:B *220:62 0 +21 *2036:B *225:21 4.28984e-05 +22 *2175:A *2034:A1 7.77751e-05 +23 *2175:A *2127:CLK 5.94737e-05 +24 *2175:A *162:12 0 +25 *140:14 *2034:A2 6.42778e-05 +26 *140:14 *2034:B1 5.33005e-05 +27 *140:14 *2127:CLK 2.14083e-05 +28 *140:14 *223:8 5.52302e-05 +29 *140:25 *162:12 3.31397e-05 +30 *140:25 *162:16 9.87983e-06 +31 *140:25 *220:49 0.000125731 +32 *2127:D *140:14 4.45831e-05 +*RES +1 *2127:Q *140:6 13.9429 +2 *140:6 *140:14 5.21429 +3 *140:14 *2033:A 10.6571 +4 *140:14 *140:25 6.14286 +5 *140:25 *1928:B 13.8 +6 *140:25 *2036:B 21.425 +7 *140:6 *2175:A 25.2821 +*END + +*D_NET *141 0.00248409 +*CONN +*I *2167:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *2036:A I *D sky130_fd_sc_hd__and2_1 +*I *1928:A I *D sky130_fd_sc_hd__or4_1 +*I *2128:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *2167:A 9.62347e-05 +2 *2036:A 0.000178263 +3 *1928:A 1.82899e-05 +4 *2128:Q 0.000344456 +5 *141:21 0.000341324 +6 *141:8 0.000429573 +7 *1928:A *2038:A1 2.94103e-05 +8 *2036:A *2037:B 2.44318e-05 +9 *2036:A *2130:CLK 2.28499e-05 +10 *2167:A *2130:CLK 0.000175892 +11 *141:8 *2038:A1 2.14658e-05 +12 *141:8 *2038:A2 1.39726e-05 +13 *141:8 *220:49 8.25843e-06 +14 *141:21 *2038:A1 3.48235e-05 +15 *141:21 *220:49 0 +16 *141:21 *220:62 0 +17 *2036:B *1928:A 5.83233e-05 +18 *2036:B *2036:A 0.000206481 +19 *2036:B *141:21 0.00012401 +20 *2128:D *141:8 0.000356028 +*RES +1 *2128:Q *141:8 18.4429 +2 *141:8 *1928:A 14.5321 +3 *141:8 *141:21 6.14286 +4 *141:21 *2036:A 13.1571 +5 *141:21 *2167:A 11.0679 +*END + +*D_NET *142 0.00406003 +*CONN +*I *1984:A1 I *D sky130_fd_sc_hd__a31o_1 +*I *1933:B I *D sky130_fd_sc_hd__or4b_1 +*I *1982:A1 I *D sky130_fd_sc_hd__a31o_1 +*I *1938:B I *D sky130_fd_sc_hd__and4_1 +*I *2176:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *2101:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *1984:A1 3.46478e-05 +2 *1933:B 0 +3 *1982:A1 0 +4 *1938:B 0.000127686 +5 *2176:A 4.31674e-05 +6 *2101:Q 0.000310632 +7 *142:31 0.000336636 +8 *142:25 0.00046252 +9 *142:21 0.000375081 +10 *142:10 0.000440663 +11 *1938:B *1938:A 0 +12 *1938:B *1979:B1 0 +13 *1984:A1 *1984:B1 1.02504e-05 +14 *1984:A1 *150:14 1.18064e-05 +15 *2176:A *271:22 0.000227532 +16 *2176:A *273:8 0.000224583 +17 *142:25 *1985:B 0.000180496 +18 *142:31 *1981:B1 9.91086e-05 +19 *142:31 *271:24 0.000148189 +20 *1935:A *142:21 7.46039e-05 +21 *1935:A *142:25 5.49544e-05 +22 *1982:B1 *142:31 0.000331057 +23 *1984:A3 *1984:A1 2.6304e-05 +24 *1984:A3 *142:21 4.42631e-05 +25 *120:33 *142:10 5.28427e-05 +26 *120:61 *142:10 6.19181e-05 +27 *120:61 *142:21 2.16719e-05 +28 *131:21 *1938:B 9.25014e-06 +29 *131:43 *1938:B 0.000144038 +30 *131:58 *1938:B 5.83304e-05 +31 *131:79 *1938:B 1.02504e-05 +32 *131:79 *142:25 0.000100723 +33 *131:79 *142:31 3.68242e-05 +*RES +1 *2101:Q *142:10 18.0321 +2 *142:10 *2176:A 15.9786 +3 *142:10 *142:21 1.94643 +4 *142:21 *142:25 7.91071 +5 *142:25 *142:31 9.41071 +6 *142:31 *1938:B 16.3536 +7 *142:31 *1982:A1 13.8 +8 *142:25 *1933:B 9.3 +9 *142:21 *1984:A1 14.5321 +*END + +*D_NET *143 0.00426011 +*CONN +*I *2039:B1 I *D sky130_fd_sc_hd__a21o_1 +*I *1928:D I *D sky130_fd_sc_hd__or4_1 +*I *2044:A2 I *D sky130_fd_sc_hd__a41o_1 +*I *2040:A I *D sky130_fd_sc_hd__nand3_1 +*I *2129:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *2039:B1 0 +2 *1928:D 0.000190484 +3 *2044:A2 0.000195377 +4 *2040:A 0 +5 *2129:Q 0.000807017 +6 *143:16 0.000248998 +7 *143:12 0.0003296 +8 *143:10 0.000892511 +9 *1928:D *1928:C 0.000222878 +10 *1928:D *2044:A1 7.6644e-05 +11 *1928:D *2130:CLK 0 +12 *1928:D *162:12 0.000364253 +13 *2044:A2 *2040:B 5.52302e-05 +14 *2044:A2 *2040:C 1.67483e-05 +15 *2044:A2 *2044:A1 6.05161e-06 +16 *2044:A2 *2044:A4 1.64649e-05 +17 *2044:A2 *2045:B1 7.48301e-06 +18 *2044:A2 *220:75 9.80173e-05 +19 *2044:A2 *225:25 3.39921e-05 +20 *2044:A2 *228:6 1.33343e-05 +21 *143:10 *2129:CLK 0.000142053 +22 *143:10 *2130:CLK 1.17968e-05 +23 *143:10 *162:10 5.57727e-05 +24 *143:10 *277:21 6.75007e-05 +25 *143:10 *278:30 5.52302e-05 +26 *143:12 *2130:CLK 8.44027e-05 +27 *143:12 *162:10 1.00375e-05 +28 *143:12 *162:12 4.52833e-05 +29 *143:16 *2045:B1 6.71755e-05 +30 *143:16 *225:25 5.52238e-05 +31 *143:16 *228:6 8.56752e-05 +32 *2129:D *143:10 4.87669e-06 +*RES +1 *2129:Q *143:10 24.9071 +2 *143:10 *143:12 2.25 +3 *143:12 *143:16 6.26786 +4 *143:16 *2040:A 9.3 +5 *143:16 *2044:A2 13.1571 +6 *143:12 *1928:D 19.425 +7 *143:10 *2039:B1 13.8 +*END + +*D_NET *144 0.00458275 +*CONN +*I *2186:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *2044:A1 I *D sky130_fd_sc_hd__a41o_1 +*I *1928:C I *D sky130_fd_sc_hd__or4_1 +*I *2130:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *2186:A 0.000238833 +2 *2044:A1 0.000532234 +3 *1928:C 0.000114722 +4 *2130:Q 4.41446e-05 +5 *144:10 0.00130178 +6 *144:6 0.0009378 +7 *1928:C *2130:CLK 9.11365e-06 +8 *1928:C *162:12 1.18064e-05 +9 *2044:A1 *2039:A1 6.2589e-06 +10 *2044:A1 *2045:B1 0.000407783 +11 *2044:A1 *2130:CLK 2.1527e-05 +12 *2044:A1 *220:62 6.75806e-05 +13 *2044:A1 *220:75 2.12645e-05 +14 *2044:A1 *225:21 0 +15 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5.19835e-05 +14 *1984:B1 *150:14 5.22205e-05 +15 *1984:B1 *161:20 0.000271898 +16 *1984:B1 *271:24 0 +17 *145:23 *1933:C 3.34366e-05 +18 *145:23 *157:21 0.000105123 +19 *1935:A *1984:B1 0 +20 *1938:B *1938:A 0 +21 *1938:C *1938:A 9.60939e-05 +22 *1938:D *1938:A 1.74352e-05 +23 *1979:A1 *1938:A 2.2351e-05 +24 *1981:A2 *145:8 5.52302e-05 +25 *1982:B1 *1938:A 2.34204e-05 +26 *1982:B1 *145:23 0.00011741 +27 *1984:A1 *1984:B1 1.02504e-05 +*RES +1 *2102:Q *145:8 14.7464 +2 *145:8 *1938:A 19.6571 +3 *145:8 *145:23 8.875 +4 *145:23 *1933:A 9.3 +5 *145:23 *1984:B1 25.175 +*END + +*D_NET *146 0.00250366 +*CONN +*I *2174:A I *D sky130_fd_sc_hd__dlygate4sd3_1 +*I *1934:D I *D sky130_fd_sc_hd__or4_1 +*I *1940:D I *D sky130_fd_sc_hd__and4_1 +*I *1987:A I *D sky130_fd_sc_hd__and2_1 +*I *2103:Q O *D sky130_fd_sc_hd__dfxtp_1 +*CAP +1 *2174:A 5.34335e-05 +2 *1934:D 0 +3 *1940:D 0.000136697 +4 *1987:A 0.000122032 +5 *2103:Q 0.000167514 +6 *146:23 0.000225806 +7 *146:21 0.000164929 +8 *146:6 0.000311931 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sky130_fd_sc_hd__o21ai_1 +*I *2025:B I *D sky130_fd_sc_hd__and3b_1 +*I *1945:X O *D sky130_fd_sc_hd__clkbuf_2 +*CAP +1 *1992:A 8.79366e-05 +2 *2041:A 0 +3 *2034:B1 2.62157e-05 +4 *2031:B 3.68863e-05 +5 *1977:A 0.000265026 +6 *1946:B1 0.000312003 +7 *1985:C 0 +8 *1979:B1 0.000517458 +9 *2018:B1 0.000539206 +10 *2025:B 0.000585871 +11 *1945:X 0 +12 *162:51 0.00114935 +13 *162:47 0.000410065 +14 *162:43 0.00108312 +15 *162:33 0.00146497 +16 *162:31 0.000783097 +17 *162:16 0.000812885 +18 *162:12 0.000648647 +19 *162:10 0.00092671 +20 *162:4 0.00061923 +21 *1946:B1 *1943:A2 1.19402e-05 +22 *1946:B1 *2048:C 0.000219008 +23 *1946:B1 *267:10 0.000127256 +24 *1977:A *1974:C 0 +25 *1977:A *2023:D 0 +26 *1977:A *2028:B1 0.000149911 +27 *1977:A *187:10 9.69119e-06 +28 *1977:A *187:16 5.52238e-05 +29 *1977:A *187:140 0.000100481 +30 *1979:B1 *163:12 0 +31 *1992:A *1996:A2 2.78584e-05 +32 *1992:A *278:18 4.18895e-05 +33 *2018:B1 *2019:B 0.000111385 +34 *2018:B1 *2047:D_N 0 +35 *2018:B1 *2100:D 0.000154762 +36 *2018:B1 *163:12 0 +37 *2018:B1 *178:62 3.4879e-05 +38 *2018:B1 *180:42 2.56694e-05 +39 *2018:B1 *187:24 0 +40 *2025:B *2025:A_N 0 +41 *2025:B *2025:C 7.83659e-05 +42 *2025:B *2031:C 3.92854e-05 +43 *2025:B *2124:CLK 0 +44 *2025:B *220:10 7.09632e-05 +45 *2025:B *220:25 1.37861e-05 +46 *2025:B *276:10 0 +47 *2031:B *276:31 2.44318e-05 +48 *2034:B1 *2034:A2 5.52302e-05 +49 *162:10 *1994:A 1.00375e-05 +50 *162:10 *277:21 0 +51 *162:10 *278:18 5.71472e-05 +52 *162:10 *278:30 0.000429731 +53 *162:12 *2041:C 3.52194e-05 +54 *162:16 *2034:A1 7.79781e-06 +55 *162:16 *2035:B 2.59093e-05 +56 *162:16 *220:25 7.45393e-05 +57 *162:16 *220:49 6.8646e-06 +58 *162:16 *276:10 0 +59 *162:33 *276:31 0.000561123 +60 *162:43 *1932:A 1.69115e-05 +61 *162:43 *2047:B 5.10822e-05 +62 *162:43 *2048:C 2.56601e-05 +63 *162:43 *2100:CLK 5.71472e-05 +64 *162:43 *163:12 0 +65 *162:43 *264:12 1.76039e-05 +66 *162:43 *267:10 0.000237076 +67 *162:43 *276:31 0.00012389 +68 *162:43 *276:33 8.91587e-05 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*278:51 0.000115935 +35 *2052:B *278:55 8.84654e-05 +36 *2054:C *278:55 2.0954e-05 +37 *2055:A *278:55 7.48301e-06 +38 *2057:B *2057:C 0 +39 *2064:B *278:63 0 +40 *2104:D *278:18 7.6021e-05 +41 *2106:D *278:51 9.47931e-05 +42 *2129:CLK *278:30 0.000140933 +43 *2193:A *278:18 7.77751e-05 +44 *104:6 *278:34 0.000186437 +45 *104:10 *278:34 5.52302e-05 +46 *143:10 *278:30 5.52302e-05 +47 *147:47 *278:18 0 +48 *150:55 *1943:D1 1.32276e-05 +49 *153:8 *2057:C 0 +50 *153:12 *2057:C 2.89114e-05 +51 *153:12 *278:63 2.44318e-05 +52 *153:25 *278:63 3.18676e-05 +53 *153:52 *2057:C 0 +54 *153:52 *278:63 0 +55 *154:23 *278:55 5.03772e-05 +56 *154:31 *2057:C 0 +57 *154:31 *278:63 6.09572e-05 +58 *157:54 *278:51 0 +59 *157:88 *278:30 8.74399e-05 +60 *157:88 *278:34 0.000269428 +61 *158:45 *278:34 6.42095e-05 +62 *162:10 *278:18 5.71472e-05 +63 *162:10 *278:30 0.000429731 +64 *196:10 *278:18 5.01213e-05 +65 *236:19 *2057:C 0 +66 *245:6 *2057:C 5.52302e-05 +67 *245:6 *278:63 9.90367e-05 +68 *275:84 *2057:C 0 +69 *277:21 *278:30 9.69119e-06 +70 *277:32 *278:30 7.04538e-05 +71 *277:43 *278:30 7.86072e-05 +72 *277:51 *278:51 8.66961e-05 +73 *277:55 *278:51 0 +74 *277:63 *1943:D1 0 +75 *277:63 *278:51 0 +*RES +1 *2193:X *278:18 28.2821 +2 *278:18 *278:30 27.7857 +3 *278:30 *278:34 10.7857 +4 *278:34 *1943:D1 17.4161 +5 *278:34 *278:51 20.9821 +6 *278:51 *278:55 8.76786 +7 *278:55 *278:63 11.5893 +8 *278:63 *2057:C 22.3 +9 *278:63 *2062:A 9.3 +10 *278:55 *2066:A 9.3 +11 *278:51 *2054:A 9.72857 +12 *278:30 *1927:A 9.3 +13 *278:18 *1945:A 9.3 +*END + +*D_NET *279 0.000523204 +*CONN +*I *1998:A1 I *D sky130_fd_sc_hd__o21a_1 +*I *2166:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1998:A1 0.00010159 +2 *2166:X 0.00010159 +3 *1998:A2 *1998:A1 0.000320024 +*RES +1 *2166:X *1998:A1 21.6 +*END + +*D_NET *280 0.00321889 +*CONN +*I *1979:A2 I *D sky130_fd_sc_hd__o21ai_1 +*I *1980:A2 I *D sky130_fd_sc_hd__a21oi_1 +*I *1978:A I *D sky130_fd_sc_hd__nand2_1 +*I *2177:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1979:A2 0.00032176 +2 *1980:A2 7.59135e-05 +3 *1978:A 0.000190544 +4 *2177:X 0 +5 *280:10 0.00046207 +6 *280:6 0.000517372 +7 *1979:A2 *1983:A 0 +8 *280:10 *1980:A1 0 +9 *1931:A_N *1978:A 0.000359997 +10 *1983:B *1979:A2 0.000314139 +11 *2180:A *280:10 0 +12 *120:16 *1979:A2 0 +13 *120:16 *280:10 0 +14 *120:29 *1979:A2 0 +15 *187:24 *1978:A 0.000758031 +16 *187:24 *1980:A2 0.000219064 +*RES +1 *2177:X *280:6 13.8 +2 *280:6 *280:10 7.96429 +3 *280:10 *1978:A 16.9607 +4 *280:10 *1980:A2 11.4786 +5 *280:6 *1979:A2 19.4607 +*END + +*D_NET *281 0.00039513 +*CONN +*I *2043:A I *D sky130_fd_sc_hd__inv_2 +*I *2186:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2043:A 0.000197565 +2 *2186:X 0.000197565 +3 *2186:A *2043:A 0 +*RES +1 *2186:X *2043:A 30.1893 +*END + +*D_NET *282 0.000574717 +*CONN +*I *2130:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2187:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2130:D 0.000233278 +2 *2187:X 0.000233278 +3 *2186:A *2130:D 0 +4 *144:10 *2130:D 0.000108161 +*RES +1 *2187:X *2130:D 32.1759 +*END + +*D_NET *283 0.000629824 +*CONN +*I *1975:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *1976:A1 I *D sky130_fd_sc_hd__a21oi_1 +*I *2188:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1975:A1 0 +2 *1976:A1 8.36689e-05 +3 *2188:X 3.46559e-05 +4 *283:6 0.000118325 +5 *1975:B1 *1976:A1 0.000127246 +6 *1976:B1 *1976:A1 5.65955e-05 +7 *2024:A2 *1976:A1 5.71472e-05 +8 *2024:A2 *283:6 8.76257e-05 +9 *185:25 *1976:A1 6.45599e-05 +*RES +1 *2188:X *283:6 10.2464 +2 *283:6 *1976:A1 11.8893 +3 *283:6 *1975:A1 9.3 +*END + +*D_NET *284 0.000568818 +*CONN +*I *1994:A I *D sky130_fd_sc_hd__inv_2 +*I *2189:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1994:A 0.000193908 +2 *2189:X 0.000193908 +3 *162:10 *1994:A 1.00375e-05 +4 *193:35 *1994:A 7.15962e-05 +5 *277:43 *1994:A 6.42242e-05 +6 *278:18 *1994:A 0 +7 *278:30 *1994:A 3.51442e-05 +*RES +1 *2189:X *1994:A 31.0107 +*END + +*D_NET *285 0.000329797 +*CONN +*I *2105:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2190:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2105:D 8.65823e-05 +2 *2190:X 8.65823e-05 +3 *1995:C *2105:D 1.19402e-05 +4 *193:27 *2105:D 2.56601e-05 +5 *193:35 *2105:D 5.95163e-05 +6 *277:43 *2105:D 0 +7 *277:51 *2105:D 5.95163e-05 +*RES +1 *2190:X *2105:D 29.5152 +*END + +*D_NET *286 0.000982104 +*CONN +*I *1966:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *1967:A1 I *D sky130_fd_sc_hd__a21oi_1 +*I *2191:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1966:A1 0 +2 *1967:A1 0.000198456 +3 *2191:X 7.75247e-05 +4 *286:6 0.00027598 +5 *1967:B1 *1967:A1 7.49997e-05 +6 *163:34 *1967:A1 0.000113089 +7 *163:34 *286:6 0.000232399 +8 *178:28 *1967:A1 9.6561e-06 +*RES +1 *2191:X *286:6 11.4786 +2 *286:6 *1967:A1 12.7464 +3 *286:6 *1966:A1 9.3 +*END + +*D_NET *287 0.000803624 +*CONN +*I *2021:A1 I *D sky130_fd_sc_hd__o211a_1 +*I *2192:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2021:A1 8.12797e-05 +2 *2192:X 8.12797e-05 +3 *1975:B1 *2021:A1 0.000344617 +4 *2020:A *2021:A1 5.52238e-05 +5 *2021:A2 *2021:A1 3.57366e-05 +6 *2021:B1 *2021:A1 0.000126629 +7 *135:20 *2021:A1 1.02936e-05 +8 *163:24 *2021:A1 1.33343e-05 +9 *185:19 *2021:A1 5.52302e-05 +*RES +1 *2192:X *2021:A1 22.4393 +*END + +*D_NET *288 0.000637873 +*CONN +*I *2038:A1 I *D sky130_fd_sc_hd__o211a_1 +*I *2167:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2038:A1 0.000109407 +2 *2167:X 0.000109407 +3 *1928:A *2038:A1 2.94103e-05 +4 *2038:A2 *2038:A1 0.000188586 +5 *2038:B1 *2038:A1 0 +6 *2128:D *2038:A1 0.000144773 +7 *141:8 *2038:A1 2.14658e-05 +8 *141:21 *2038:A1 3.48235e-05 +*RES +1 *2167:X *2038:A1 31.0107 +*END + +*D_NET *289 0.000641171 +*CONN +*I *1948:A1 I *D sky130_fd_sc_hd__a21oi_1 +*I *1947:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2168:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1948:A1 0 +2 *1947:A1 5.56071e-05 +3 *2168:X 7.94067e-05 +4 *289:6 0.000135014 +5 *1947:A2 *1947:A1 0.000153588 +6 *1947:A2 *289:6 1.64621e-05 +7 *1948:B1 *1947:A1 5.65955e-05 +8 *161:28 *289:6 0.000144498 +*RES +1 *2168:X *289:6 11.0679 +2 *289:6 *1947:A1 11.0857 +3 *289:6 *1948:A1 9.3 +*END + +*D_NET *290 0.00119457 +*CONN +*I *2016:A1 I *D sky130_fd_sc_hd__o211a_1 +*I *2169:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2016:A1 0.000321096 +2 *2169:X 0.000321096 +3 *1963:C *2016:A1 5.33334e-05 +4 *1964:D *2016:A1 0 +5 *2016:B1 *2016:A1 0 +6 *178:12 *2016:A1 0.000226867 +7 *187:36 *2016:A1 0.00027218 +8 *187:38 *2016:A1 0 +*RES +1 *2169:X *2016:A1 34.1536 +*END + +*D_NET *291 0.000245765 +*CONN +*I *2002:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2170:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2002:A1 1.71756e-05 +2 *2170:X 1.71756e-05 +3 *2170:A *2002:A1 5.52302e-05 +4 *123:8 *2002:A1 5.52238e-05 +5 *275:10 *2002:A1 0.00010096 +*RES +1 *2170:X *2002:A1 19.5464 +*END + +*D_NET *292 0.000281413 +*CONN +*I *2111:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2171:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2111:D 0.000110951 +2 *2171:X 0.000110951 +3 *2112:CLK *2111:D 0 +4 *275:10 *2111:D 5.95099e-05 +*RES +1 *2171:X *2111:D 29.5152 +*END + +*D_NET *293 0.000372485 +*CONN +*I *2018:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2172:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2018:A1 0.000122653 +2 *2172:X 0.000122653 +3 *134:16 *2018:A1 0 +4 *134:25 *2018:A1 0 +5 *163:24 *2018:A1 5.71472e-05 +6 *180:10 *2018:A1 6.42242e-05 +7 *180:23 *2018:A1 5.80706e-06 +*RES +1 *2172:X *2018:A1 29.7786 +*END + +*D_NET *294 0.00194389 +*CONN +*I *2027:A1 I *D sky130_fd_sc_hd__a21oi_1 +*I *2028:A1 I *D sky130_fd_sc_hd__o21a_1 +*I *2173:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2027:A1 0.000381911 +2 *2028:A1 0 +3 *2173:X 0.000197861 +4 *294:16 0.000579772 +5 *1929:A *2027:A1 0.000100831 +6 *2022:A *2027:A1 5.86454e-05 +7 *2022:B *2027:A1 1.74352e-05 +8 *2027:B1 *2027:A1 8.97228e-05 +9 *2027:B1 *294:16 0 +10 *137:17 *2027:A1 4.18895e-05 +11 *138:8 *294:16 3.13687e-05 +12 *187:140 *2027:A1 1.18927e-05 +13 *187:140 *294:16 0.000154762 +14 *264:12 *2027:A1 9.86146e-05 +15 *276:31 *294:16 0.000179181 +*RES +1 *2173:X *294:16 22.9786 +2 *294:16 *2028:A1 9.3 +3 *294:16 *2027:A1 24.6571 +*END + +*D_NET *295 0.000694479 +*CONN +*I *1988:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2174:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1988:A1 0.000151869 +2 *2174:X 0.000151869 +3 *1987:B *1988:A1 5.33005e-05 +4 *1989:A *1988:A1 2.41481e-05 +5 *1989:B *1988:A1 5.33005e-05 +6 *1996:C1 *1988:A1 7.70035e-05 +7 *104:57 *1988:A1 5.33614e-05 +8 *146:23 *1988:A1 9.71197e-05 +9 *193:27 *1988:A1 3.25078e-05 +*RES +1 *2174:X *1988:A1 30.725 +*END + +*D_NET *296 0.000924441 +*CONN +*I *2034:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2175:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2034:A1 0.000324362 +2 *2175:X 0.000324362 +3 *2035:B *2034:A1 7.83587e-05 +4 *2127:CLK *2034:A1 6.42338e-05 +5 *2127:D *2034:A1 1.08359e-05 +6 *2175:A *2034:A1 7.77751e-05 +7 *162:16 *2034:A1 7.79781e-06 +8 *276:8 *2034:A1 3.67142e-05 +*RES +1 *2175:X *2034:A1 32.6536 +*END + +*D_NET *297 0.00128623 +*CONN +*I *1981:B1 I *D sky130_fd_sc_hd__a21oi_1 +*I *2176:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1981:B1 0.000271294 +2 *2176:X 0.000271294 +3 *1981:A2 *1981:B1 0.000136958 +4 *2178:A *1981:B1 0.000138881 +5 *131:79 *1981:B1 0.000100823 +6 *142:31 *1981:B1 9.91086e-05 +7 *271:22 *1981:B1 0.000267877 +*RES +1 *2176:X *1981:B1 32.8857 +*END + +*D_NET *298 0.000348128 +*CONN +*I *1983:A I *D sky130_fd_sc_hd__nor2_1 +*I *2178:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1983:A 0.000107775 +2 *2178:X 0.000107775 +3 *1979:A2 *1983:A 0 +4 *1983:B *1983:A 5.52238e-05 +5 *2101:D *1983:A 2.79092e-05 +6 *120:29 *1983:A 4.94455e-05 +*RES +1 *2178:X *1983:A 30.0821 +*END + +*D_NET *299 0.000637827 +*CONN +*I *1980:A1 I *D sky130_fd_sc_hd__a21oi_1 +*I *2179:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1980:A1 0.000229173 +2 *2179:X 0.000229173 +3 *1980:B1 *1980:A1 4.23086e-05 +4 *2180:A *1980:A1 0.000124735 +5 *120:8 *1980:A1 1.24368e-05 +6 *280:10 *1980:A1 0 +*RES +1 *2179:X *1980:A1 31.3143 +*END + +*D_NET *300 0.0004411 +*CONN +*I *2100:D I *D sky130_fd_sc_hd__dfxtp_1 +*I *2180:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2100:D 0.000134359 +2 *2180:X 0.000134359 +3 *2018:B1 *2100:D 0.000154762 +4 *2047:D_N *2100:D 0 +5 *187:24 *2100:D 1.76204e-05 +*RES +1 *2180:X *2100:D 30.2473 +*END + +*D_NET *301 0.000224162 +*CONN +*I *2010:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2181:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2010:A1 1.1121e-05 +2 *2181:X 1.1121e-05 +3 *2010:B1 *2010:A1 0.00010096 +4 *274:60 *2010:A1 0.00010096 +*RES +1 *2181:X *2010:A1 19.5464 +*END + +*D_NET *302 0.000769362 +*CONN +*I *2007:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2182:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2007:A1 0.000157692 +2 *2182:X 0.000157692 +3 *1959:A *2007:A1 0 +4 *1959:B *2007:A1 5.33005e-05 +5 *1959:C *2007:A1 7.17235e-05 +6 *2007:B1 *2007:A1 0 +7 *2008:A *2007:A1 9.90431e-05 +8 *2008:B *2007:A1 3.99614e-06 +9 *126:19 *2007:A1 3.18676e-05 +10 *126:38 *2007:A1 0.000140746 +11 *173:6 *2007:A1 5.33005e-05 +*RES +1 *2182:X *2007:A1 22.9929 +*END + +*D_NET *303 0.000976071 +*CONN +*I *2013:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2183:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2013:A1 0.00029646 +2 *2183:X 0.00029646 +3 *1963:D *2013:A1 1.39726e-05 +4 *2010:B1 *2013:A1 5.33433e-05 +5 *2013:B1 *2013:A1 6.8646e-06 +6 *128:8 *2013:A1 0 +7 *129:21 *2013:A1 7.47221e-05 +8 *209:8 *2013:A1 5.52302e-05 +9 *274:60 *2013:A1 0.000179018 +*RES +1 *2183:X *2013:A1 32.9571 +*END + +*D_NET *304 0.00050733 +*CONN +*I *2005:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2184:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *2005:A1 0.000110742 +2 *2184:X 0.000110742 +3 *2005:A2 *2005:A1 5.52238e-05 +4 *2109:D *2005:A1 0 +5 *163:57 *2005:A1 2.19684e-05 +6 *169:8 *2005:A1 3.17148e-05 +7 *169:10 *2005:A1 0.000128154 +8 *271:22 *2005:A1 4.87854e-05 +*RES +1 *2184:X *2005:A1 30.4929 +*END + +*D_NET *305 0.000445006 +*CONN +*I *1961:A1 I *D sky130_fd_sc_hd__o21ai_1 +*I *2185:X O *D sky130_fd_sc_hd__dlygate4sd3_1 +*CAP +1 *1961:A1 0.000195682 +2 *2185:X 0.000195682 +3 *1962:B *1961:A1 0 +4 *127:12 *1961:A1 5.36426e-05 +*RES +1 *2185:X *1961:A1 30.6 +*END diff --git a/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.v b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.v new file mode 100644 index 0000000..201974b --- /dev/null +++ b/projects/tt_um_ajstein_stopwatch/tt_um_ajstein_stopwatch.v @@ -0,0 +1,8354 @@ +module tt_um_ajstein_stopwatch (VGND, + VPWR, + clk, + ena, + rst_n, + ui_in, + uio_in, + uio_oe, + uio_out, + uo_out); + input VGND; + input VPWR; + input clk; + input ena; + input rst_n; + input [7:0] ui_in; + input [7:0] uio_in; + output [7:0] uio_oe; + output [7:0] uio_out; + output [7:0] uo_out; + + wire net2; + wire net3; + wire net4; + wire net5; + wire net6; + wire net7; + wire net8; + wire net9; + wire net10; + wire net11; + wire net12; + wire net13; + wire net14; + wire net15; + wire net16; + wire net17; + wire net18; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[0] ; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[1] ; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[2] ; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[3] ; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[4] ; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[5] ; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[6] ; + wire \DEBUG_SIGS_GTKWAVE.@0$slideswitch[7] ; + wire \DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[0] ; + wire \DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[1] ; + wire \DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[2] ; + wire \DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[3] ; + wire \DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[4] ; + wire \DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[5] ; + wire \DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[6] ; + wire \DEBUG_SIGS_GTKWAVE./digit[0]./leds[0].//@0$viz_lit ; + wire \DEBUG_SIGS_GTKWAVE./digit[0]./leds[1].//@0$viz_lit ; + wire \DEBUG_SIGS_GTKWAVE./digit[0]./leds[2].//@0$viz_lit ; + wire \DEBUG_SIGS_GTKWAVE./digit[0]./leds[3].//@0$viz_lit ; + wire \DEBUG_SIGS_GTKWAVE./digit[0]./leds[4].//@0$viz_lit ; + wire \DEBUG_SIGS_GTKWAVE./digit[0]./leds[5].//@0$viz_lit ; + wire \DEBUG_SIGS_GTKWAVE./digit[0]./leds[6].//@0$viz_lit ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[0] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[10] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[11] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[12] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[13] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[14] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[15] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[16] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[17] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[18] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[19] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[1] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[20] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[21] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[22] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[23] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[24] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[25] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[26] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[27] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[28] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[29] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[2] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[30] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[31] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[3] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[4] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[5] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[6] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[7] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[8] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[9] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[1] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[0] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[1] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[2] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[3] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[4] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[5] ; + wire \DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[6] ; + wire \DEBUG_SIGS_GTKWAVE./switch[0]./@0$viz_switch ; + wire \DEBUG_SIGS_GTKWAVE./switch[1]./@0$viz_switch ; + wire \DEBUG_SIGS_GTKWAVE./switch[2]./@0$viz_switch ; + wire \DEBUG_SIGS_GTKWAVE./switch[3]./@0$viz_switch ; + wire \DEBUG_SIGS_GTKWAVE./switch[4]./@0$viz_switch ; + wire \DEBUG_SIGS_GTKWAVE./switch[5]./@0$viz_switch ; + wire \DEBUG_SIGS_GTKWAVE./switch[6]./@0$viz_switch ; + wire \DEBUG_SIGS_GTKWAVE./switch[7]./@0$viz_switch ; + wire \FpgaPins_Fpga_cycle_counter_a1[0] ; + wire \FpgaPins_Fpga_cycle_counter_a1[10] ; + wire \FpgaPins_Fpga_cycle_counter_a1[11] ; + wire \FpgaPins_Fpga_cycle_counter_a1[12] ; + wire \FpgaPins_Fpga_cycle_counter_a1[13] ; + wire \FpgaPins_Fpga_cycle_counter_a1[14] ; + wire \FpgaPins_Fpga_cycle_counter_a1[15] ; + wire \FpgaPins_Fpga_cycle_counter_a1[16] ; + wire \FpgaPins_Fpga_cycle_counter_a1[17] ; + wire \FpgaPins_Fpga_cycle_counter_a1[18] ; + wire \FpgaPins_Fpga_cycle_counter_a1[19] ; + wire \FpgaPins_Fpga_cycle_counter_a1[1] ; + wire \FpgaPins_Fpga_cycle_counter_a1[20] ; + wire \FpgaPins_Fpga_cycle_counter_a1[21] ; + wire \FpgaPins_Fpga_cycle_counter_a1[22] ; + wire \FpgaPins_Fpga_cycle_counter_a1[23] ; + wire \FpgaPins_Fpga_cycle_counter_a1[24] ; + wire \FpgaPins_Fpga_cycle_counter_a1[25] ; + wire \FpgaPins_Fpga_cycle_counter_a1[26] ; + wire \FpgaPins_Fpga_cycle_counter_a1[27] ; + wire \FpgaPins_Fpga_cycle_counter_a1[28] ; + wire \FpgaPins_Fpga_cycle_counter_a1[29] ; + wire \FpgaPins_Fpga_cycle_counter_a1[2] ; + wire \FpgaPins_Fpga_cycle_counter_a1[30] ; + wire \FpgaPins_Fpga_cycle_counter_a1[31] ; + wire \FpgaPins_Fpga_cycle_counter_a1[3] ; + wire \FpgaPins_Fpga_cycle_counter_a1[4] ; + wire \FpgaPins_Fpga_cycle_counter_a1[5] ; + wire \FpgaPins_Fpga_cycle_counter_a1[6] ; + wire \FpgaPins_Fpga_cycle_counter_a1[7] ; + wire \FpgaPins_Fpga_cycle_counter_a1[8] ; + wire \FpgaPins_Fpga_cycle_counter_a1[9] ; + wire \FpgaPins_Fpga_display_counter_a1[0] ; + wire \FpgaPins_Fpga_display_counter_a1[1] ; + wire \FpgaPins_Fpga_display_counter_a1[2] ; + wire \FpgaPins_Fpga_display_counter_a1[3] ; + wire _000_; + wire _001_; + wire _002_; + wire _003_; + wire _004_; + wire _005_; + wire _006_; + wire _007_; + wire _008_; + wire _009_; + wire _010_; + wire _011_; + wire _012_; + wire _013_; + wire _014_; + wire _015_; + wire _016_; + wire _017_; + wire _018_; + wire _019_; + wire _020_; + wire _021_; + wire _022_; + wire _023_; + wire _024_; + wire _025_; + wire _026_; + wire _027_; + wire _028_; + wire _029_; + wire _030_; + wire _031_; + wire _032_; + wire _033_; + wire _034_; + wire _035_; + wire _036_; + wire _037_; + wire _038_; + wire _039_; + wire _040_; + wire _041_; + wire _042_; + wire _043_; + wire _044_; + wire _045_; + wire _046_; + wire _047_; + wire _048_; + wire _049_; + wire _050_; + wire _051_; + wire _052_; + wire _053_; + wire _054_; + wire _055_; + wire _056_; + wire _057_; + wire _058_; + wire _059_; + wire _060_; + wire _061_; + wire _062_; + wire _063_; + wire _064_; + wire _065_; + wire _066_; + wire _067_; + wire _068_; + wire _069_; + wire _070_; + wire _071_; + wire _072_; + wire _073_; + wire _074_; + wire _075_; + wire _076_; + wire _077_; + wire _078_; + wire _079_; + wire _080_; + wire _081_; + wire _082_; + wire _083_; + wire _084_; + wire _085_; + wire _086_; + wire _087_; + wire _088_; + wire _089_; + wire _090_; + wire _091_; + wire _092_; + wire _093_; + wire _094_; + wire _095_; + wire _096_; + wire _097_; + wire _098_; + wire _099_; + wire _100_; + wire _101_; + wire _102_; + wire _103_; + wire _104_; + wire _105_; + wire _106_; + wire _107_; + wire _108_; + wire _109_; + wire _110_; + wire _111_; + wire _112_; + wire _113_; + wire _114_; + wire _115_; + wire _116_; + wire clknet_0_clk; + wire clknet_2_0__leaf_clk; + wire clknet_2_1__leaf_clk; + wire clknet_2_2__leaf_clk; + wire clknet_2_3__leaf_clk; + wire net1; + wire net19; + wire net20; + wire net21; + wire net22; + wire net23; + wire net24; + wire net25; + wire net26; + wire net27; + wire net28; + wire net29; + wire net30; + wire net31; + wire net32; + wire net33; + wire net34; + wire net35; + wire net36; + wire net37; + wire net38; + wire net39; + wire net40; + wire net41; + wire net42; + wire net43; + wire net44; + wire net45; + + sky130_fd_sc_hd__decap_3 FILLER_0_0_109 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_113 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_125 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_137 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_141 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_15 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_153 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_165 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_169 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_181 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_193 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_197 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_209 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_221 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_225 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_237 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_249 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_253 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_265 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_1 FILLER_0_0_27 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_277 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_281 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_29 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_293 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_305 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_309 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_321 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 FILLER_0_0_333 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_41 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_53 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_57 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_69 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_0_81 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_85 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_97 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_109 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_121 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_10_133 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_10_139 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_141 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_15 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_153 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_165 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_177 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_10_189 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_10_195 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_197 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_209 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_221 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_233 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_10_245 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_10_251 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_253 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_265 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_1 FILLER_0_10_27 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_277 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_289 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_29 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_10_301 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_10_307 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_309 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_321 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 FILLER_0_10_333 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_41 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_53 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_65 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_10_77 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_10_83 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_85 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_10_97 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_11_105 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_11_111 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_113 (.VPWR(VPWR), + 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FILLER_0_11_281 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_293 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_305 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_317 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_11_329 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_39 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_4 FILLER_0_11_51 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_11_55 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_57 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_69 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_81 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_11_93 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_12_109 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_12_121 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_12_133 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_12_139 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_12_141 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_12_15 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_12_153 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + 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FILLER_0_13_181 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_13_193 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_13_205 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_13_217 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_13_223 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_13_225 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_13_237 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_13_249 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_13_261 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_13_27 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + 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FILLER_0_28_277 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_28_289 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_28_29 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_28_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_28_301 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_28_307 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_28_334 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_28_41 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_28_53 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_28_65 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + 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FILLER_0_2_265 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_1 FILLER_0_2_27 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_2_277 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_2_289 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_2_29 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_2_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_2_301 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_2_307 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_2_309 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_2_321 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 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FILLER_0_30_133 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_30_139 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_30_141 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_30_15 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_30_153 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_30_159 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_30_204 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_30_212 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_30_219 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_30_227 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + 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.VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_31_218 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_31_225 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_31_231 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_31_255 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_31_27 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 FILLER_0_31_271 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_31_281 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_4 FILLER_0_31_291 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_31_295 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_31_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_1 FILLER_0_31_304 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_31_309 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_31_332 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_31_39 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_4 FILLER_0_31_51 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_31_55 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_31_57 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_31_69 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_31_81 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_31_93 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_32_109 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_32_121 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_32_133 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_32_139 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_32_141 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_32_15 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_32_153 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_8 FILLER_0_32_165 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_32_173 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_32_205 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_32_245 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_32_251 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_32_258 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_32_269 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_32_27 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_32_287 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_32_29 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_32_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_4 FILLER_0_32_323 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + 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FILLER_0_35_317 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_35_332 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_35_39 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_4 FILLER_0_35_51 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_35_55 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_35_57 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_35_69 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_35_81 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_35_93 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_36_109 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + 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.VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_4_85 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_4_97 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_5_105 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_5_111 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_5_113 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_5_125 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_5_137 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_5_149 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_5_15 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_5_161 (.VGND(VGND), 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sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_2_Right_2 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_30_Left_69 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_30_Right_30 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_31_Left_70 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_31_Right_31 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_32_Left_71 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_32_Right_32 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_33_Left_72 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_33_Right_33 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_34_Left_73 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_34_Right_34 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_35_Left_74 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_35_Right_35 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_36_Left_75 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_36_Right_36 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_37_Left_76 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_37_Right_37 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_38_Left_77 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_38_Right_38 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_3_Left_42 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_3_Right_3 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_4_Left_43 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_4_Right_4 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_5_Left_44 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_5_Right_5 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_6_Left_45 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_6_Right_6 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_7_Left_46 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_7_Right_7 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_8_Left_47 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_8_Right_8 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_9_Left_48 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_9_Right_9 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_78 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_79 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_80 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_81 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_82 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_83 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_84 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_85 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_86 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_87 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_0_88 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_10_138 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_10_139 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_10_140 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_10_141 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_10_142 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_10_143 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_11_144 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_11_145 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_11_146 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_11_147 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_11_148 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_12_149 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_12_150 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_12_151 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_12_152 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_12_153 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_12_154 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_13_155 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_13_156 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_13_157 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_13_158 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_13_159 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_14_160 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_14_161 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_14_162 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_14_163 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_14_164 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_14_165 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_15_166 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_15_167 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_15_168 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_15_169 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_15_170 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_16_171 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_16_172 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_16_173 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_16_174 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_16_175 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_16_176 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_17_177 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_17_178 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_17_179 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_17_180 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_17_181 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_18_182 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_18_183 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_18_184 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_18_185 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_18_186 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_18_187 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_19_188 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_19_189 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_19_190 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_19_191 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_19_192 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_1_89 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_1_90 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_1_91 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_1_92 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_1_93 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_20_193 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_20_194 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_20_195 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_20_196 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_20_197 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_20_198 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_21_199 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_21_200 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_21_201 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_21_202 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_21_203 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_22_204 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_22_205 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_22_206 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_22_207 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_22_208 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_22_209 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_23_210 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_23_211 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_23_212 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_23_213 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_23_214 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_24_215 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_24_216 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_24_217 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_24_218 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_24_219 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_24_220 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_25_221 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_25_222 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_25_223 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_25_224 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_25_225 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_26_226 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_26_227 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_26_228 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_26_229 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_26_230 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_26_231 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_27_232 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_27_233 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_27_234 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_27_235 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_27_236 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_28_237 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_28_238 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_28_239 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_28_240 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_28_241 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_28_242 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_29_243 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_29_244 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_29_245 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_29_246 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_29_247 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_2_94 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_2_95 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_2_96 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_2_97 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_2_98 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_2_99 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_30_248 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_30_249 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_30_250 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_30_251 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_30_252 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_30_253 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_31_254 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_31_255 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_31_256 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_31_257 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_31_258 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_32_259 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_32_260 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_32_261 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_32_262 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_32_263 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_32_264 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_33_265 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_33_266 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_33_267 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_33_268 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_33_269 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_34_270 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_34_271 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_34_272 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_34_273 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_34_274 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_34_275 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_35_276 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_35_277 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_35_278 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_35_279 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_35_280 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_36_281 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_36_282 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_36_283 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_36_284 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_36_285 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_36_286 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_37_287 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_37_288 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_37_289 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_37_290 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_37_291 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_292 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_293 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_294 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_295 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_296 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_297 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_298 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_299 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_300 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_301 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_302 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_3_100 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_3_101 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_3_102 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_3_103 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_3_104 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_4_105 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_4_106 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_4_107 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_4_108 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_4_109 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_4_110 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_5_111 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_5_112 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_5_113 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_5_114 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_5_115 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_6_116 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_6_117 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_6_118 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_6_119 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_6_120 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_6_121 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_7_122 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_7_123 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_7_124 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_7_125 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_7_126 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_8_127 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_8_128 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_8_129 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_8_130 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_8_131 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_8_132 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_9_133 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_9_134 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_9_135 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_9_136 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_9_137 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__inv_2 _117_ (.A(net1), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset )); + sky130_fd_sc_hd__or4_1 _118_ (.A(\FpgaPins_Fpga_cycle_counter_a1[29] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[28] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[31] ), + .D(\FpgaPins_Fpga_cycle_counter_a1[30] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_107_)); + sky130_fd_sc_hd__or4b_1 _119_ (.A(\FpgaPins_Fpga_cycle_counter_a1[25] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[27] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[26] ), + .D_N(\FpgaPins_Fpga_cycle_counter_a1[24] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_108_)); + sky130_fd_sc_hd__or4_1 _120_ (.A(\FpgaPins_Fpga_cycle_counter_a1[19] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[18] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[23] ), + .D(\FpgaPins_Fpga_cycle_counter_a1[22] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_109_)); + sky130_fd_sc_hd__and4b_1 _121_ (.A_N(\FpgaPins_Fpga_cycle_counter_a1[17] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[16] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[21] ), + .D(\FpgaPins_Fpga_cycle_counter_a1[20] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_110_)); + sky130_fd_sc_hd__or4b_1 _122_ (.A(_107_), + .B(_108_), + .C(_109_), + .D_N(_110_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_111_)); + sky130_fd_sc_hd__or4b_1 _123_ (.A(\FpgaPins_Fpga_cycle_counter_a1[3] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[2] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[9] ), + .D_N(\FpgaPins_Fpga_cycle_counter_a1[8] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_112_)); + sky130_fd_sc_hd__or4_1 _124_ (.A(\FpgaPins_Fpga_cycle_counter_a1[7] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[6] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[5] ), + .D(\FpgaPins_Fpga_cycle_counter_a1[4] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_113_)); + sky130_fd_sc_hd__or4bb_1 _125_ (.A(\FpgaPins_Fpga_cycle_counter_a1[1] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[0] ), + .C_N(\FpgaPins_Fpga_cycle_counter_a1[11] ), + .D_N(\FpgaPins_Fpga_cycle_counter_a1[10] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_114_)); + sky130_fd_sc_hd__or4b_1 _126_ (.A(\FpgaPins_Fpga_cycle_counter_a1[12] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[15] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[14] ), + .D_N(\FpgaPins_Fpga_cycle_counter_a1[13] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_115_)); + sky130_fd_sc_hd__or4_1 _127_ (.A(_112_), + .B(_113_), + .C(_114_), + .D(_115_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_116_)); + sky130_fd_sc_hd__and4_1 _128_ (.A(\FpgaPins_Fpga_cycle_counter_a1[3] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[2] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[1] ), + .D(\FpgaPins_Fpga_cycle_counter_a1[0] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_000_)); + sky130_fd_sc_hd__clkbuf_2 _129_ (.A(_000_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_001_)); + sky130_fd_sc_hd__and4_1 _130_ (.A(\FpgaPins_Fpga_cycle_counter_a1[7] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[6] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[5] ), + .D(\FpgaPins_Fpga_cycle_counter_a1[4] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_002_)); + sky130_fd_sc_hd__a21o_1 _131_ (.A1(_001_), + .A2(_002_), + .B1(\FpgaPins_Fpga_cycle_counter_a1[8] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_003_)); + sky130_fd_sc_hd__nand3_1 _132_ (.A(\FpgaPins_Fpga_cycle_counter_a1[8] ), + .B(_001_), + .C(_002_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_004_)); + sky130_fd_sc_hd__o2111a_1 _133_ (.A1(_111_), + .A2(_116_), + .B1(_003_), + .C1(_004_), + .D1(net1), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[8] )); + sky130_fd_sc_hd__and4_2 _134_ (.A(\FpgaPins_Fpga_cycle_counter_a1[8] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[9] ), + .C(_001_), + .D(_002_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_005_)); + sky130_fd_sc_hd__clkbuf_2 _135_ (.A(net1), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_006_)); + sky130_fd_sc_hd__o21a_2 _136_ (.A1(_111_), + .A2(_116_), + .B1(_006_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_007_)); + sky130_fd_sc_hd__o21ai_1 _137_ (.A1(net29), + .A2(_005_), + .B1(_007_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_008_)); + sky130_fd_sc_hd__a21oi_1 _138_ (.A1(net29), + .A2(_005_), + .B1(_008_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[10] )); + sky130_fd_sc_hd__and2_1 _139_ (.A(\FpgaPins_Fpga_cycle_counter_a1[11] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[10] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_009_)); + sky130_fd_sc_hd__and2_1 _140_ (.A(_009_), + .B(_005_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_010_)); + sky130_fd_sc_hd__a21o_1 _141_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[10] ), + .A2(_005_), + .B1(\FpgaPins_Fpga_cycle_counter_a1[11] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_011_)); + sky130_fd_sc_hd__and3b_1 _142_ (.A_N(_010_), + .B(_007_), + .C(_011_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_012_)); + sky130_fd_sc_hd__clkbuf_1 _143_ (.A(_012_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[11] )); + sky130_fd_sc_hd__and4_1 _144_ (.A(\FpgaPins_Fpga_cycle_counter_a1[12] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[13] ), + .C(_009_), + .D(_005_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_013_)); + sky130_fd_sc_hd__and3_1 _145_ (.A(\FpgaPins_Fpga_cycle_counter_a1[12] ), + .B(_009_), + .C(_005_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_014_)); + sky130_fd_sc_hd__or2_1 _146_ (.A(\FpgaPins_Fpga_cycle_counter_a1[13] ), + .B(_014_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_015_)); + sky130_fd_sc_hd__and3b_1 _147_ (.A_N(_013_), + .B(_007_), + .C(_015_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_016_)); + sky130_fd_sc_hd__clkbuf_1 _148_ (.A(_016_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[13] )); + sky130_fd_sc_hd__and3_1 _149_ (.A(\FpgaPins_Fpga_cycle_counter_a1[15] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[14] ), + .C(_013_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_017_)); + sky130_fd_sc_hd__and2_1 _150_ (.A(\FpgaPins_Fpga_cycle_counter_a1[16] ), + .B(_017_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_018_)); + sky130_fd_sc_hd__o21ai_1 _151_ (.A1(net45), + .A2(_017_), + .B1(_007_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_019_)); + sky130_fd_sc_hd__nor2_1 _152_ (.A(_018_), + .B(_019_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[16] )); + sky130_fd_sc_hd__and4_1 _153_ (.A(\FpgaPins_Fpga_cycle_counter_a1[17] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[16] ), + .C(\FpgaPins_Fpga_cycle_counter_a1[19] ), + .D(\FpgaPins_Fpga_cycle_counter_a1[18] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_020_)); + sky130_fd_sc_hd__and4_1 _154_ (.A(\FpgaPins_Fpga_cycle_counter_a1[15] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[14] ), + .C(_013_), + .D(_020_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_021_)); + sky130_fd_sc_hd__clkbuf_2 _155_ (.A(_021_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_022_)); + sky130_fd_sc_hd__o21ai_1 _156_ (.A1(net26), + .A2(_022_), + .B1(_007_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_023_)); + sky130_fd_sc_hd__a21oi_1 _157_ (.A1(net26), + .A2(_022_), + .B1(_023_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[20] )); + sky130_fd_sc_hd__and2_1 _158_ (.A(\FpgaPins_Fpga_cycle_counter_a1[21] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[20] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_024_)); + sky130_fd_sc_hd__and2_1 _159_ (.A(_024_), + .B(_022_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_025_)); + sky130_fd_sc_hd__a21o_1 _160_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[20] ), + .A2(_022_), + .B1(\FpgaPins_Fpga_cycle_counter_a1[21] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_026_)); + sky130_fd_sc_hd__and3b_1 _161_ (.A_N(_025_), + .B(_007_), + .C(_026_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_027_)); + sky130_fd_sc_hd__clkbuf_1 _162_ (.A(_027_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[21] )); + sky130_fd_sc_hd__and2_1 _163_ (.A(\FpgaPins_Fpga_cycle_counter_a1[23] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[22] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_028_)); + sky130_fd_sc_hd__and3_1 _164_ (.A(_024_), + .B(_022_), + .C(_028_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_029_)); + sky130_fd_sc_hd__o21ai_1 _165_ (.A1(net23), + .A2(_029_), + .B1(_007_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_030_)); + sky130_fd_sc_hd__a21oi_1 _166_ (.A1(net23), + .A2(_029_), + .B1(_030_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[24] )); + sky130_fd_sc_hd__buf_2 _167_ (.A(_006_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_031_)); + sky130_fd_sc_hd__nand2_1 _168_ (.A(net20), + .B(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[0] )); + sky130_fd_sc_hd__o21ai_1 _169_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[1] ), + .A2(net20), + .B1(_006_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_032_)); + sky130_fd_sc_hd__a21oi_1 _170_ (.A1(net39), + .A2(net20), + .B1(_032_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[1] )); + sky130_fd_sc_hd__a21oi_1 _171_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[1] ), + .A2(\FpgaPins_Fpga_cycle_counter_a1[0] ), + .B1(net37), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_033_)); + sky130_fd_sc_hd__a31o_1 _172_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[2] ), + .A2(\FpgaPins_Fpga_cycle_counter_a1[1] ), + .A3(\FpgaPins_Fpga_cycle_counter_a1[0] ), + .B1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_034_)); + sky130_fd_sc_hd__nor2_1 _173_ (.A(net38), + .B(_034_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[2] )); + sky130_fd_sc_hd__a31o_1 _174_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[2] ), + .A2(\FpgaPins_Fpga_cycle_counter_a1[1] ), + .A3(\FpgaPins_Fpga_cycle_counter_a1[0] ), + .B1(\FpgaPins_Fpga_cycle_counter_a1[3] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_035_)); + sky130_fd_sc_hd__and3b_1 _175_ (.A_N(_001_), + .B(_035_), + .C(_006_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_036_)); + sky130_fd_sc_hd__clkbuf_1 _176_ (.A(_036_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[3] )); + sky130_fd_sc_hd__and2_1 _177_ (.A(\FpgaPins_Fpga_cycle_counter_a1[4] ), + .B(_001_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_037_)); + sky130_fd_sc_hd__o21ai_1 _178_ (.A1(net35), + .A2(_001_), + .B1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_038_)); + sky130_fd_sc_hd__nor2_1 _179_ (.A(_037_), + .B(_038_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[4] )); + sky130_fd_sc_hd__or2_1 _180_ (.A(\FpgaPins_Fpga_cycle_counter_a1[5] ), + .B(_037_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_039_)); + sky130_fd_sc_hd__nand2_1 _181_ (.A(\FpgaPins_Fpga_cycle_counter_a1[5] ), + .B(_037_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_040_)); + sky130_fd_sc_hd__and3_1 _182_ (.A(_006_), + .B(_039_), + .C(_040_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_041_)); + sky130_fd_sc_hd__clkbuf_1 _183_ (.A(_041_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[5] )); + sky130_fd_sc_hd__inv_2 _184_ (.A(net24), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_042_)); + sky130_fd_sc_hd__and3_1 _185_ (.A(\FpgaPins_Fpga_cycle_counter_a1[6] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[5] ), + .C(_037_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_043_)); + sky130_fd_sc_hd__a211oi_1 _186_ (.A1(_042_), + .A2(_040_), + .B1(_043_), + .C1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[6] )); + sky130_fd_sc_hd__a21oi_1 _187_ (.A1(_001_), + .A2(_002_), + .B1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_044_)); + sky130_fd_sc_hd__o21a_1 _188_ (.A1(net19), + .A2(_043_), + .B1(_044_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[7] )); + sky130_fd_sc_hd__a31o_1 _189_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[8] ), + .A2(_001_), + .A3(_002_), + .B1(\FpgaPins_Fpga_cycle_counter_a1[9] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_045_)); + sky130_fd_sc_hd__or3b_1 _190_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset ), + .B(_005_), + .C_N(_045_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_046_)); + sky130_fd_sc_hd__inv_2 _191_ (.A(_046_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[9] )); + sky130_fd_sc_hd__o21ai_1 _192_ (.A1(net31), + .A2(_010_), + .B1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_047_)); + sky130_fd_sc_hd__nor2_1 _193_ (.A(_014_), + .B(_047_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[12] )); + sky130_fd_sc_hd__and2_1 _194_ (.A(\FpgaPins_Fpga_cycle_counter_a1[14] ), + .B(_013_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_048_)); + sky130_fd_sc_hd__o21ai_1 _195_ (.A1(net44), + .A2(_013_), + .B1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_049_)); + sky130_fd_sc_hd__nor2_1 _196_ (.A(_048_), + .B(_049_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[14] )); + sky130_fd_sc_hd__o21ai_1 _197_ (.A1(net42), + .A2(_048_), + .B1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_050_)); + sky130_fd_sc_hd__nor2_1 _198_ (.A(_017_), + .B(_050_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[15] )); + sky130_fd_sc_hd__and3_1 _199_ (.A(\FpgaPins_Fpga_cycle_counter_a1[17] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[16] ), + .C(_017_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_051_)); + sky130_fd_sc_hd__o21ai_1 _200_ (.A1(net41), + .A2(_018_), + .B1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_052_)); + sky130_fd_sc_hd__nor2_1 _201_ (.A(_051_), + .B(_052_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[17] )); + sky130_fd_sc_hd__and2_1 _202_ (.A(\FpgaPins_Fpga_cycle_counter_a1[18] ), + .B(_051_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_053_)); + sky130_fd_sc_hd__o21ai_1 _203_ (.A1(net43), + .A2(_051_), + .B1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_054_)); + sky130_fd_sc_hd__nor2_1 _204_ (.A(_053_), + .B(_054_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[18] )); + sky130_fd_sc_hd__inv_2 _205_ (.A(_022_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_055_)); + sky130_fd_sc_hd__o211a_1 _206_ (.A1(net30), + .A2(_053_), + .B1(_055_), + .C1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[19] )); + sky130_fd_sc_hd__and3_1 _207_ (.A(\FpgaPins_Fpga_cycle_counter_a1[22] ), + .B(_024_), + .C(_022_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_056_)); + sky130_fd_sc_hd__o21ai_1 _208_ (.A1(net33), + .A2(_025_), + .B1(_006_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_057_)); + sky130_fd_sc_hd__nor2_1 _209_ (.A(_056_), + .B(_057_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[22] )); + sky130_fd_sc_hd__inv_2 _210_ (.A(_029_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_058_)); + sky130_fd_sc_hd__o211a_1 _211_ (.A1(net27), + .A2(_056_), + .B1(_058_), + .C1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[23] )); + sky130_fd_sc_hd__and2_1 _212_ (.A(\FpgaPins_Fpga_cycle_counter_a1[25] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[24] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_059_)); + sky130_fd_sc_hd__and4_1 _213_ (.A(_024_), + .B(_022_), + .C(_028_), + .D(_059_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_060_)); + sky130_fd_sc_hd__a21o_1 _214_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[24] ), + .A2(_029_), + .B1(\FpgaPins_Fpga_cycle_counter_a1[25] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_061_)); + sky130_fd_sc_hd__and3b_1 _215_ (.A_N(_060_), + .B(_006_), + .C(_061_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_062_)); + sky130_fd_sc_hd__clkbuf_1 _216_ (.A(_062_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[25] )); + sky130_fd_sc_hd__a21oi_1 _217_ (.A1(net34), + .A2(_060_), + .B1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_063_)); + sky130_fd_sc_hd__o21a_1 _218_ (.A1(net34), + .A2(_060_), + .B1(_063_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[26] )); + sky130_fd_sc_hd__and3_1 _219_ (.A(\FpgaPins_Fpga_cycle_counter_a1[27] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[26] ), + .C(_060_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_064_)); + sky130_fd_sc_hd__a21o_1 _220_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[26] ), + .A2(_060_), + .B1(\FpgaPins_Fpga_cycle_counter_a1[27] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_065_)); + sky130_fd_sc_hd__and3b_1 _221_ (.A_N(_064_), + .B(_006_), + .C(_065_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_066_)); + sky130_fd_sc_hd__clkbuf_1 _222_ (.A(_066_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[27] )); + sky130_fd_sc_hd__and2_1 _223_ (.A(\FpgaPins_Fpga_cycle_counter_a1[28] ), + .B(_064_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_067_)); + sky130_fd_sc_hd__o21ai_1 _224_ (.A1(net36), + .A2(_064_), + .B1(_006_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_068_)); + sky130_fd_sc_hd__nor2_1 _225_ (.A(_067_), + .B(_068_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[28] )); + sky130_fd_sc_hd__and2_1 _226_ (.A(\FpgaPins_Fpga_cycle_counter_a1[29] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[28] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_069_)); + sky130_fd_sc_hd__nand2_1 _227_ (.A(_064_), + .B(_069_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_070_)); + sky130_fd_sc_hd__o211a_1 _228_ (.A1(net28), + .A2(_067_), + .B1(_070_), + .C1(_031_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[29] )); + sky130_fd_sc_hd__a21o_1 _229_ (.A1(_064_), + .A2(_069_), + .B1(\FpgaPins_Fpga_cycle_counter_a1[30] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_071_)); + sky130_fd_sc_hd__nand3_1 _230_ (.A(\FpgaPins_Fpga_cycle_counter_a1[30] ), + .B(_064_), + .C(_069_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_072_)); + sky130_fd_sc_hd__and3_1 _231_ (.A(_006_), + .B(_071_), + .C(_072_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_073_)); + sky130_fd_sc_hd__clkbuf_1 _232_ (.A(_073_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[30] )); + sky130_fd_sc_hd__inv_2 _233_ (.A(net21), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_074_)); + sky130_fd_sc_hd__a41o_1 _234_ (.A1(\FpgaPins_Fpga_cycle_counter_a1[31] ), + .A2(\FpgaPins_Fpga_cycle_counter_a1[30] ), + .A3(_064_), + .A4(_069_), + .B1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$reset ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_075_)); + sky130_fd_sc_hd__a21oi_1 _235_ (.A1(_074_), + .A2(_072_), + .B1(_075_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[31] )); + sky130_fd_sc_hd__nand2_1 _236_ (.A(\FpgaPins_Fpga_cycle_counter_a1[11] ), + .B(\FpgaPins_Fpga_cycle_counter_a1[10] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_076_)); + sky130_fd_sc_hd__or4b_1 _237_ (.A(_107_), + .B(_108_), + .C(_109_), + .D_N(_110_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_077_)); + sky130_fd_sc_hd__nor4_1 _238_ (.A(\FpgaPins_Fpga_cycle_counter_a1[8] ), + .B(_076_), + .C(_077_), + .D(_115_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_078_)); + sky130_fd_sc_hd__and4_1 _239_ (.A(\FpgaPins_Fpga_display_counter_a1[0] ), + .B(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[8] ), + .C(_046_), + .D(_078_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_079_)); + sky130_fd_sc_hd__clkbuf_2 _240_ (.A(_079_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_080_)); + sky130_fd_sc_hd__a31o_1 _241_ (.A1(\FpgaPins_Fpga_display_counter_a1[2] ), + .A2(\FpgaPins_Fpga_display_counter_a1[1] ), + .A3(_080_), + .B1(\FpgaPins_Fpga_display_counter_a1[3] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_081_)); + sky130_fd_sc_hd__xnor2_1 _242_ (.A(\FpgaPins_Fpga_display_counter_a1[2] ), + .B(\FpgaPins_Fpga_display_counter_a1[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_082_)); + sky130_fd_sc_hd__nand3_1 _243_ (.A(\FpgaPins_Fpga_display_counter_a1[3] ), + .B(_080_), + .C(_082_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_083_)); + sky130_fd_sc_hd__and3_1 _244_ (.A(net1), + .B(_081_), + .C(_083_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_084_)); + sky130_fd_sc_hd__clkbuf_2 _245_ (.A(_084_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] )); + sky130_fd_sc_hd__a31o_1 _246_ (.A1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[8] ), + .A2(_046_), + .A3(_078_), + .B1(\FpgaPins_Fpga_display_counter_a1[0] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_085_)); + sky130_fd_sc_hd__and3b_1 _247_ (.A_N(_080_), + .B(_085_), + .C(net1), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_086_)); + sky130_fd_sc_hd__clkbuf_2 _248_ (.A(_086_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] )); + sky130_fd_sc_hd__nand2_1 _249_ (.A(\FpgaPins_Fpga_display_counter_a1[1] ), + .B(_080_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_087_)); + sky130_fd_sc_hd__or2b_1 _250_ (.A(\FpgaPins_Fpga_display_counter_a1[2] ), + .B_N(\FpgaPins_Fpga_display_counter_a1[3] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_088_)); + sky130_fd_sc_hd__a21o_1 _251_ (.A1(_080_), + .A2(_088_), + .B1(\FpgaPins_Fpga_display_counter_a1[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_089_)); + sky130_fd_sc_hd__and3_1 _252_ (.A(net1), + .B(_087_), + .C(_089_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_090_)); + sky130_fd_sc_hd__buf_1 _253_ (.A(_090_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[1] )); + sky130_fd_sc_hd__nand3_1 _254_ (.A(\FpgaPins_Fpga_display_counter_a1[2] ), + .B(\FpgaPins_Fpga_display_counter_a1[1] ), + .C(_080_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_091_)); + sky130_fd_sc_hd__a21o_1 _255_ (.A1(\FpgaPins_Fpga_display_counter_a1[1] ), + .A2(_080_), + .B1(\FpgaPins_Fpga_display_counter_a1[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_092_)); + sky130_fd_sc_hd__and3_1 _256_ (.A(net1), + .B(_091_), + .C(_092_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_093_)); + sky130_fd_sc_hd__clkbuf_2 _257_ (.A(_093_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] )); + sky130_fd_sc_hd__and4b_1 _258_ (.A_N(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] ), + .B(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .C(_089_), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_094_)); + sky130_fd_sc_hd__dlymetal6s2s_1 _259_ (.A(_094_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_095_)); + sky130_fd_sc_hd__nor3_2 _260_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] ), + .B(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[1] ), + .C(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_096_)); + sky130_fd_sc_hd__or2_1 _261_ (.A(_095_), + .B(_096_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_097_)); + sky130_fd_sc_hd__clkbuf_1 _262_ (.A(_097_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[6] )); + sky130_fd_sc_hd__nor2_1 _263_ (.A(_095_), + .B(_096_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[6].//@0$viz_lit )); + sky130_fd_sc_hd__nor2_1 _264_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .B(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_098_)); + sky130_fd_sc_hd__nor2b_2 _265_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] ), + .B_N(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_099_)); + sky130_fd_sc_hd__a22o_1 _266_ (.A1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .A2(_096_), + .B1(_098_), + .B2(_099_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[0] )); + sky130_fd_sc_hd__nand2_1 _267_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .B(_089_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_100_)); + sky130_fd_sc_hd__or2_1 _268_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .B(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_101_)); + sky130_fd_sc_hd__clkbuf_2 _269_ (.A(_101_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_102_)); + sky130_fd_sc_hd__and3_1 _270_ (.A(_099_), + .B(_100_), + .C(_102_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_103_)); + sky130_fd_sc_hd__clkbuf_1 _271_ (.A(_103_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[1] )); + sky130_fd_sc_hd__or3b_1 _272_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] ), + .B(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .C_N(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_104_)); + sky130_fd_sc_hd__nor2_1 _273_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .B(_104_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[2] )); + sky130_fd_sc_hd__a221o_1 _274_ (.A1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .A2(_096_), + .B1(_098_), + .B2(_099_), + .C1(_095_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[3] )); + sky130_fd_sc_hd__o21a_1 _275_ (.A1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .A2(_102_), + .B1(_104_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[4] )); + sky130_fd_sc_hd__nor2_1 _276_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] ), + .B(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(_105_)); + sky130_fd_sc_hd__a21o_1 _277_ (.A1(_105_), + .A2(_102_), + .B1(_095_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[5] )); + sky130_fd_sc_hd__a22oi_1 _278_ (.A1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .A2(_096_), + .B1(_098_), + .B2(_099_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[0].//@0$viz_lit )); + sky130_fd_sc_hd__nand3_1 _279_ (.A(_099_), + .B(_100_), + .C(_102_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[1].//@0$viz_lit )); + sky130_fd_sc_hd__or2_1 _280_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .B(_104_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(_106_)); + sky130_fd_sc_hd__clkbuf_1 _281_ (.A(_106_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[2].//@0$viz_lit )); + sky130_fd_sc_hd__a221oi_1 _282_ (.A1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .A2(_096_), + .B1(_098_), + .B2(_099_), + .C1(_095_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[3].//@0$viz_lit )); + sky130_fd_sc_hd__o21ai_1 _283_ (.A1(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .A2(_102_), + .B1(_104_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[4].//@0$viz_lit )); + sky130_fd_sc_hd__a21oi_1 _284_ (.A1(_105_), + .A2(_102_), + .B1(_095_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[5].//@0$viz_lit )); + sky130_fd_sc_hd__dfxtp_1 _285_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[0] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_display_counter_a1[0] )); + sky130_fd_sc_hd__dfxtp_1 _286_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_display_counter_a1[1] )); + sky130_fd_sc_hd__dfxtp_1 _287_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_display_counter_a1[2] )); + sky130_fd_sc_hd__dfxtp_1 _288_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$display_counter[3] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_display_counter_a1[3] )); + sky130_fd_sc_hd__dfxtp_1 _289_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[0] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[0] )); + sky130_fd_sc_hd__dfxtp_1 _290_ (.CLK(clknet_2_2__leaf_clk), + .D(net40), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[1] )); + sky130_fd_sc_hd__dfxtp_1 _291_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[2] )); + sky130_fd_sc_hd__dfxtp_1 _292_ (.CLK(clknet_2_3__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[3] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[3] )); + sky130_fd_sc_hd__dfxtp_1 _293_ (.CLK(clknet_2_3__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[4] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[4] )); + sky130_fd_sc_hd__dfxtp_1 _294_ (.CLK(clknet_2_3__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[5] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[5] )); + sky130_fd_sc_hd__dfxtp_1 _295_ (.CLK(clknet_2_3__leaf_clk), + .D(net25), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[6] )); + sky130_fd_sc_hd__dfxtp_1 _296_ (.CLK(clknet_2_3__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[7] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[7] )); + sky130_fd_sc_hd__dfxtp_1 _297_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[8] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[8] )); + sky130_fd_sc_hd__dfxtp_1 _298_ (.CLK(clknet_2_3__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[9] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[9] )); + sky130_fd_sc_hd__dfxtp_1 _299_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[10] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[10] )); + sky130_fd_sc_hd__dfxtp_1 _300_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[11] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[11] )); + sky130_fd_sc_hd__dfxtp_1 _301_ (.CLK(clknet_2_1__leaf_clk), + .D(net32), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[12] )); + sky130_fd_sc_hd__dfxtp_1 _302_ (.CLK(clknet_2_1__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[13] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[13] )); + sky130_fd_sc_hd__dfxtp_1 _303_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[14] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[14] )); + sky130_fd_sc_hd__dfxtp_1 _304_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[15] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[15] )); + sky130_fd_sc_hd__dfxtp_1 _305_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[16] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[16] )); + sky130_fd_sc_hd__dfxtp_1 _306_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[17] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[17] )); + sky130_fd_sc_hd__dfxtp_1 _307_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[18] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[18] )); + sky130_fd_sc_hd__dfxtp_1 _308_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[19] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[19] )); + sky130_fd_sc_hd__dfxtp_1 _309_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[20] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[20] )); + sky130_fd_sc_hd__dfxtp_1 _310_ (.CLK(clknet_2_0__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[21] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[21] )); + sky130_fd_sc_hd__dfxtp_1 _311_ (.CLK(clknet_2_2__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[22] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[22] )); + sky130_fd_sc_hd__dfxtp_1 _312_ (.CLK(clknet_2_2__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[23] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[23] )); + sky130_fd_sc_hd__dfxtp_1 _313_ (.CLK(clknet_2_2__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[24] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[24] )); + sky130_fd_sc_hd__dfxtp_1 _314_ (.CLK(clknet_2_2__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[25] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[25] )); + sky130_fd_sc_hd__dfxtp_1 _315_ (.CLK(clknet_2_2__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[26] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[26] )); + sky130_fd_sc_hd__dfxtp_1 _316_ (.CLK(clknet_2_2__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[27] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[27] )); + sky130_fd_sc_hd__dfxtp_1 _317_ (.CLK(clknet_2_2__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[28] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[28] )); + sky130_fd_sc_hd__dfxtp_1 _318_ (.CLK(clknet_2_3__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[29] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[29] )); + sky130_fd_sc_hd__dfxtp_1 _319_ (.CLK(clknet_2_3__leaf_clk), + .D(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[30] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[30] )); + sky130_fd_sc_hd__dfxtp_1 _320_ (.CLK(clknet_2_3__leaf_clk), + .D(net22), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\FpgaPins_Fpga_cycle_counter_a1[31] )); + sky130_fd_sc_hd__buf_2 _348_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[0] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[0] )); + sky130_fd_sc_hd__buf_2 _349_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[1] )); + sky130_fd_sc_hd__buf_2 _350_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[2] )); + sky130_fd_sc_hd__buf_2 _351_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[3] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[3] )); + sky130_fd_sc_hd__buf_2 _352_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[4] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[4] )); + sky130_fd_sc_hd__buf_2 _353_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[5] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[5] )); + sky130_fd_sc_hd__buf_2 _354_ (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$segments[6] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$sseg_segment_n[6] )); + sky130_fd_sc_hd__buf_2 _355_ (.A(ui_in[1]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[1] )); + sky130_fd_sc_hd__buf_2 _356_ (.A(ui_in[0]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[0] )); + sky130_fd_sc_hd__buf_2 _357_ (.A(ui_in[2]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[2] )); + sky130_fd_sc_hd__buf_2 _358_ (.A(ui_in[0]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[0]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _359_ (.A(ui_in[1]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[1]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _360_ (.A(ui_in[2]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[2]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _361_ (.A(ui_in[3]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[3]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _362_ (.A(ui_in[4]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[4]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _363_ (.A(ui_in[5]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[5]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _364_ (.A(ui_in[6]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[6]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _365_ (.A(ui_in[7]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE./switch[7]./@0$viz_switch )); + sky130_fd_sc_hd__buf_2 _366_ (.A(ui_in[7]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[7] )); + sky130_fd_sc_hd__buf_2 _367_ (.A(ui_in[3]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[3] )); + sky130_fd_sc_hd__buf_2 _368_ (.A(ui_in[6]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[6] )); + sky130_fd_sc_hd__buf_2 _369_ (.A(ui_in[5]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[5] )); + sky130_fd_sc_hd__buf_2 _370_ (.A(ui_in[4]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(\DEBUG_SIGS_GTKWAVE.@0$slideswitch[4] )); + sky130_fd_sc_hd__buf_2 _371_ (.A(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[0].//@0$viz_lit ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[0])); + sky130_fd_sc_hd__clkbuf_4 _372_ (.A(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[1].//@0$viz_lit ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[1])); + sky130_fd_sc_hd__buf_2 _373_ (.A(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[2].//@0$viz_lit ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[2])); + sky130_fd_sc_hd__buf_2 _374_ (.A(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[3].//@0$viz_lit ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[3])); + sky130_fd_sc_hd__buf_2 _375_ (.A(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[4].//@0$viz_lit ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[4])); + sky130_fd_sc_hd__buf_2 _376_ (.A(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[5].//@0$viz_lit ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[5])); + sky130_fd_sc_hd__buf_2 _377_ (.A(\DEBUG_SIGS_GTKWAVE./digit[0]./leds[6].//@0$viz_lit ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[6])); + sky130_fd_sc_hd__clkbuf_16 clkbuf_0_clk (.A(clk), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(clknet_0_clk)); + sky130_fd_sc_hd__clkbuf_16 clkbuf_2_0__f_clk (.A(clknet_0_clk), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(clknet_2_0__leaf_clk)); + sky130_fd_sc_hd__clkbuf_16 clkbuf_2_1__f_clk (.A(clknet_0_clk), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(clknet_2_1__leaf_clk)); + sky130_fd_sc_hd__clkbuf_16 clkbuf_2_2__f_clk (.A(clknet_0_clk), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(clknet_2_2__leaf_clk)); + sky130_fd_sc_hd__clkbuf_16 clkbuf_2_3__f_clk (.A(clknet_0_clk), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(clknet_2_3__leaf_clk)); + sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(\FpgaPins_Fpga_cycle_counter_a1[7] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net19)); + sky130_fd_sc_hd__dlygate4sd3_1 hold10 (.A(\FpgaPins_Fpga_cycle_counter_a1[29] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net28)); + sky130_fd_sc_hd__dlygate4sd3_1 hold11 (.A(\FpgaPins_Fpga_cycle_counter_a1[10] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net29)); + sky130_fd_sc_hd__dlygate4sd3_1 hold12 (.A(\FpgaPins_Fpga_cycle_counter_a1[19] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net30)); + sky130_fd_sc_hd__dlygate4sd3_1 hold13 (.A(\FpgaPins_Fpga_cycle_counter_a1[12] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net31)); + sky130_fd_sc_hd__dlygate4sd3_1 hold14 (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[12] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net32)); + sky130_fd_sc_hd__dlygate4sd3_1 hold15 (.A(\FpgaPins_Fpga_cycle_counter_a1[22] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net33)); + sky130_fd_sc_hd__dlygate4sd3_1 hold16 (.A(\FpgaPins_Fpga_cycle_counter_a1[26] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net34)); + sky130_fd_sc_hd__dlygate4sd3_1 hold17 (.A(\FpgaPins_Fpga_cycle_counter_a1[4] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net35)); + sky130_fd_sc_hd__dlygate4sd3_1 hold18 (.A(\FpgaPins_Fpga_cycle_counter_a1[28] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net36)); + sky130_fd_sc_hd__dlygate4sd3_1 hold19 (.A(\FpgaPins_Fpga_cycle_counter_a1[2] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net37)); + sky130_fd_sc_hd__dlygate4sd3_1 hold2 (.A(\FpgaPins_Fpga_cycle_counter_a1[0] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net20)); + sky130_fd_sc_hd__dlygate4sd3_1 hold20 (.A(_033_), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net38)); + sky130_fd_sc_hd__dlygate4sd3_1 hold21 (.A(\FpgaPins_Fpga_cycle_counter_a1[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net39)); + sky130_fd_sc_hd__dlygate4sd3_1 hold22 (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net40)); + sky130_fd_sc_hd__dlygate4sd3_1 hold23 (.A(\FpgaPins_Fpga_cycle_counter_a1[17] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net41)); + sky130_fd_sc_hd__dlygate4sd3_1 hold24 (.A(\FpgaPins_Fpga_cycle_counter_a1[15] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net42)); + sky130_fd_sc_hd__dlygate4sd3_1 hold25 (.A(\FpgaPins_Fpga_cycle_counter_a1[18] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net43)); + sky130_fd_sc_hd__dlygate4sd3_1 hold26 (.A(\FpgaPins_Fpga_cycle_counter_a1[14] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net44)); + sky130_fd_sc_hd__dlygate4sd3_1 hold27 (.A(\FpgaPins_Fpga_cycle_counter_a1[16] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net45)); + sky130_fd_sc_hd__dlygate4sd3_1 hold3 (.A(\FpgaPins_Fpga_cycle_counter_a1[31] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net21)); + sky130_fd_sc_hd__dlygate4sd3_1 hold4 (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[31] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net22)); + sky130_fd_sc_hd__dlygate4sd3_1 hold5 (.A(\FpgaPins_Fpga_cycle_counter_a1[24] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net23)); + sky130_fd_sc_hd__dlygate4sd3_1 hold6 (.A(\FpgaPins_Fpga_cycle_counter_a1[6] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net24)); + sky130_fd_sc_hd__dlygate4sd3_1 hold7 (.A(\DEBUG_SIGS_GTKWAVE./fpga_pins./fpga.//@0$cycle_counter[6] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net25)); + sky130_fd_sc_hd__dlygate4sd3_1 hold8 (.A(\FpgaPins_Fpga_cycle_counter_a1[20] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net26)); + sky130_fd_sc_hd__dlygate4sd3_1 hold9 (.A(\FpgaPins_Fpga_cycle_counter_a1[23] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net27)); + sky130_fd_sc_hd__clkbuf_2 input1 (.A(rst_n), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net1)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_10 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net10)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_11 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net11)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_12 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net12)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_13 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net13)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_14 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net14)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_15 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net15)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_16 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net16)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_17 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net17)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_18 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net18)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_2 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net2)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_3 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net3)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_4 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net4)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_5 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net5)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_6 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net6)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_7 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net7)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_8 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net8)); + sky130_fd_sc_hd__conb_1 tt_um_ajstein_stopwatch_9 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net9)); + assign uio_oe[0] = net2; + assign uio_oe[1] = net3; + assign uio_oe[2] = net4; + assign uio_oe[3] = net5; + assign uio_oe[4] = net6; + assign uio_oe[5] = net7; + assign uio_oe[6] = net8; + assign uio_oe[7] = net9; + assign uio_out[0] = net10; + assign uio_out[1] = net11; + assign uio_out[2] = net12; + assign uio_out[3] = net13; + assign uio_out[4] = net14; + assign uio_out[5] = net15; + assign uio_out[6] = net16; + assign uio_out[7] = net17; + assign uo_out[7] = net18; +endmodule