From ca29fc08070fa938fd5c72814989d662b523855f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=98yvind=20Harboe?= <oyvind.harboe@zylin.com>
Date: Wed, 16 Oct 2024 14:28:20 +0200
Subject: [PATCH] synth: .sdc file is generated as part of synth just like the
 other stages
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Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
---
 openroad.bzl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/openroad.bzl b/openroad.bzl
index bb561b77..7c43326d 100644
--- a/openroad.bzl
+++ b/openroad.bzl
@@ -633,7 +633,6 @@ def _yosys_impl(ctx):
             "do-yosys-keep-hierarchy",
             "do-yosys",
             "do-synth",
-            "/".join([_work_home(ctx), _artifact_name(ctx, "results", "1_synth.sdc")]),
         ],
         command = " && ".join(commands),
         env = _verilog_arguments([]) |