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Missing components for SRAMs #7

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mguthaus opened this issue Apr 21, 2023 · 0 comments

mguthaus commented Apr 21, 2023

The SRAMs seem to be missing a number of items:

spice or CDL netlists. Even the banks do not have netlists, but the README suggests that it does.
gds for anything but the 3 banks. The individual SRAMs obviously need some bank decoding, but that is not available anywhere.
verilog shows they are edge triggered, but the README suggests level sensitive. "The SRAMs are synchronous and read/write on the clock high, when either (READ or WRITE) and banksel are asserted high." Which is correct?

maliberty transferred this issue from another repository

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