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Working with the ASAP7 standard cell library, I noticed the absence of a handful of cells that commonly pop up in arithmetic architecture:
MUX2 and MUX2I
XOR2 is implemented as a cell that is very similar (not quite identical) to AOI22 / OAI22, just with two inverters on the side as well. The inverters technically don't have to sit inside the cell, one can replicate the functionality of XOR2 with AOI22 / OAI22 and inverters. But having the inverters inside the cell makes it smaller / faster due to intra-cell routing vs inter-cell.
Similarly, MUX2I in CMOS is very similar to AOI22 / OAI22, just with one inverter on the side. Same story as with XOR.
As far as I can see, the ASAP7 library has XOR/XNOR cells, but no MUX2/MUX2I cells. Adding these cells would be simple iteration, and would help with architecture design.
NAND2B and NOR2B
Arithmetic frequently uses alternating inverting logic to significantly improve performance. For example, an AND tree can be reduced to a NAND + NOR tree.
Technically NOR is not necessary. One can replicate it using NAND and inverters. But it's good to have, it improves performance.
Similarly, NAND2B and NOR2B are technically not necessary. But given how often the need for them arises in optimized arithmetic, they're also good to have.
The text was updated successfully, but these errors were encountered:
Working with the ASAP7 standard cell library, I noticed the absence of a handful of cells that commonly pop up in arithmetic architecture:
MUX2 and MUX2I
XOR2 is implemented as a cell that is very similar (not quite identical) to AOI22 / OAI22, just with two inverters on the side as well. The inverters technically don't have to sit inside the cell, one can replicate the functionality of XOR2 with AOI22 / OAI22 and inverters. But having the inverters inside the cell makes it smaller / faster due to intra-cell routing vs inter-cell.
Similarly, MUX2I in CMOS is very similar to AOI22 / OAI22, just with one inverter on the side. Same story as with XOR.
As far as I can see, the ASAP7 library has XOR/XNOR cells, but no MUX2/MUX2I cells. Adding these cells would be simple iteration, and would help with architecture design.
NAND2B and NOR2B
Arithmetic frequently uses alternating inverting logic to significantly improve performance. For example, an AND tree can be reduced to a NAND + NOR tree.
Technically NOR is not necessary. One can replicate it using NAND and inverters. But it's good to have, it improves performance.
Similarly, NAND2B and NOR2B are technically not necessary. But given how often the need for them arises in optimized arithmetic, they're also good to have.
The text was updated successfully, but these errors were encountered: