RELEASE_NOTES.TXT

============= RapidWright 2020.1.4-beta released on 2020-11-02 ================
Notes:
 * Adds 2020.1 update 1 Vivado devices (XCVU19P, XCZU46DR, XCZU47DR,
   XCZU48DR, XCZU49DR; Alveo devices: U55N, U55C)
 * Adds a netlist flattening helper method ()
 * Adds preliminary support for reproducing intermediate clock routing
   state through the use of partial PIPs - not necessarily modifiable
   though.  This is intermediate routing information added to clock nets
   after during place_design that informs clock routing during
   route_design.  Previously this was causing some ERRORs when writing
   out placed DCPs.
   * Some PIPs in these intermediate clock nets can have PIPs with no
     end wire.  This can be checked with PIP.isEndWireNull().  Or
     compare the end wire index with PIP.NULL_END_WIRE_IDX (0x0000FFFF).
 * Various netlist helper methods (see commit log for details).
 - API Additions:
   - com.xilinx.rapidwright.design.Net "public boolean hasGapRouting()"
   - com.xilinx.rapidwright.design.Net "public void setHasGapRouting(boolean hasGapRouting)"
   - com.xilinx.rapidwright.design.SitePinInst public Integer getSiteWireIndex()
   - com.xilinx.rapidwright.design.SitePinInst public Integer getSiteWireName()
   - com.xilinx.rapidwright.design.SitePinInst public Integer getSiteWireBELPins()
   - com.xilinx.rapidwright.device.PIP "public boolean isEndWireNull()"

============= RapidWright 2020.1.3-beta released on 2020-10-12 ================
Notes:
 * Re-adds missing macro primitive definitions that were absent in previous releases
 * Adds missing macro/translated primitive definitions IOBUFDS and OBUFTDS_DUAL_BUF
 * Adds some basic helper methods to handle route-thrus
 * Adds APIs to provide default property values for primitive cells (often unisims)
 * Minor update with API additions
 - API Additions:
   - com.xilinx.rapidwright.design.SiteInst "public void unrouteSite()"
   - com.xilinx.rapidwright.design.Design "public static EDIFLibrary getPrimitivesLibrary()"
   - com.xilinx.rapidwright.design.Design "public static VivadoProp getDefaultProperty(Series series, String cellTypeName, String propName)"
   - com.xilinx.rapidwright.design.Design "public static Map<String, VivadoProp> getDefaultCellProperties(Series series, String cellTypeName)"

============= RapidWright 2020.1.2-beta released on 2020-08-13 ================
Notes:
 * Minor update with API additions
 - API Additions:
   - com.xilinx.rapidwright.design.Cell "public AltPinMapping getAltPinMapping(String physicalPin)"
   - com.xilinx.rapidwright.design.Cell "public void addAltPinMapping(String physicalPin, AltPinMapping logicalPin)"
   - com.xilinx.rapidwright.design.Cell "public boolean hasAltPinMappings()"
   - com.xilinx.rapidwright.design.Cell "public Map<String,AltPinMapping> getAltPinMappings()"
   - com.xilinx.rapidwright.design.Cell "public boolean isLocked()"
   - com.xilinx.rapidwright.design.Cell "public void setNullBEL(boolean b)"
   - com.xilinx.rapidwright.design.Cell "public boolean isNullBEL()"
   - com.xilinx.rapidwright.design.Cell "public void setLocked(boolean isLocked)"
   - com.xilinx.rapidwright.design.Cell "public void setRoutethru(boolean isRoutethru)"
   - com.xilinx.rapidwright.design.Cell "public void setType(String type)"
   - com.xilinx.rapidwright.design.Cell "public void setAltBlockedSiteType(SiteTypeEnum typeEnum)"
   - com.xilinx.rapidwright.design.Cell "public SiteTypeEnum getAltBlockedSiteType()"
   - com.xilinx.rapidwright.design.SiteInst "public boolean isSiteLocked()"
   - com.xilinx.rapidwright.design.SiteInst "public void setSiteLocked(boolean isSiteLocked)"


============= RapidWright 2020.1.1-beta released on 2020-08-07 ================
Notes:
 * Minor update with API additions
 * Adds an alternative source pin to Nets (for dual output scenarios)
 - API Additions:
   - com.xilinx.rapidwright.design.Design "public static readCheckpoint(String dcpFileName, String edfFileName, CodePerfTracker t)"
   - com.xilinx.rapidwright.design.Net "public SitePinInst getAlternateSource()"
   - com.xilinx.rapidwright.design.Net "public void setAlternateSource(SitePinInst altSource)"
   - com.xilinx.rapidwright.design.SiteInst "public BELPin[] getSiteWirePins(String siteWireName)"
   - com.xilinx.rapidwright.design.SiteInst "public BELPin[] getSiteWirePins(int siteWireIdx)"
   - com.xilinx.rapidwright.design.SiteInst "public String[] getSiteWires()"
   - com.xilinx.rapidwright.design.SiteInst "public String[] getSitePinNames()"
   - com.xilinx.rapidwright.design.SiteInst "public int getHighestSitePinInputIndex()"
   - com.xilinx.rapidwright.design.SiteInst "public boolean isSitePinInput(String pinName)"
   - com.xilinx.rapidwright.design.SiteInst "public boolean isSitePinOutput(String pinName)"
   - com.xilinx.rapidwright.device.Node "public IntentCode getIntentCode()"

============= RapidWright 2020.1.0-beta released on 2020-07-31 ================
Notes:
 * Coresponds to the Vivado 2020.1 release, all device models consistent
 * Fixed an issue where timing designs would not open in Vivado
 * Adds utility method (DesignTools.createMissingSitePinInsts()) to
   create missing SitePinInsts to nets to faciltiate routing.
 * Changes hashCode() and equals() on PIP class to ignore flags, only
   includes tile and wire names
 - API Additions:
   - com.xilinx.rapidwright.design.Design "public ModuleInst createModuleInst(String name, Module module, boolean includePortRouting)"
   - com.xilinx.rapidwright.design.Design "public void copyPartitionPins(Design source, ModuleInst dest, Map<EDIFPort,EDIFPort> portMap)"
   - com.xilinx.rapidwright.design.Design "public void trimPartitionPins(Pair<Tile,Tile> range)"
   - com.xilinx.rapidwright.design.Net "public void trimPartitionPins(Pair<Tile,Tile> range)"
   - com.xilinx.rapidwright.device.BELPin "public SitePin getSitePin(Site site)" 
   - com.xilinx.rapidwright.device.BELPin "public Node getExternalNode(Site site)" 
   - com.xilinx.rapidwright.device.Node "public List<Node> getAllUphillNodes()"
   - com.xilinx.rapidwright.device.Node "public List<PIP> getAllUphillPIPs()"
   - com.xilinx.rapidwright.device.PIP "public boolean isReversed()"
   - com.xilinx.rapidwright.device.PIP "public void setIsReversed(boolean isReversed)"
 - API Refactored:
   - com.xilinx.rapidwright.device.Site "public Node getConnectedNode(int pinIndex)"
     - getconnectedNode(int pinIndex) --> getConnectedNode(int pinIndex)
 - Bug Fixes / Pull Requests:
   - Issue #70 - Fixes NPE when EDIFCellInst is null on Cell.
   - Issue #35 - Missing SitePinInsts for placed-only designs.
   - Pull Request #68 - Fixed getLUTSize(), proper processing of LUT size/parsing.
   - Other bug fixes (see commit log for details).   

============= RapidWright 2019.2.2-beta released on 2020-06-03 ================
Notes:
 * Minor feature: 
   - Support to manage/load EDIF files with blackboxes where encrypted
     IP is not populated. 
   - Adds a very basic Makefile to compile without Gradle on
     Linux-based platforms.
 - API Additions:
   - com.xilinx.rapidwright.device.Device "public int getSiteTypeCount()"
   - com.xilinx.rapidwright.device.Device "public int getTileTypeCount()"
   - com.xilinx.rapidwright.device.Site "public int getSiteWireCount()"
   - com.xilinx.rapidwright.device.Site "public String getSiteWireName(int wireIndex)"
   - com.xilinx.rapidwright.device.Site "public int getSitePinCount()"
   - com.xilinx.rapidwright.device.Site "public int getHighestInputPinIndex()"
   - com.xilinx.rapidwright.device.Site "public boolean isInputPin(int pinIndex)"
   - com.xilinx.rapidwright.device.Site "public boolean isOutputPin(int pinIndex)"
   - com.xilinx.rapidwright.device.Site "public SitePIP[] getSitePIPs()"
   - com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(int index)"
   - com.xilinx.rapidwright.device.Site "public int getSitePIPCount()"
   - com.xilinx.rapidwright.device.Site "public String[] getSiteWireNames()"
   - com.xilinx.rapidwright.device.Tile "public int getTilePatternIndex()"

 - Bug Fixes / Pull Requests:
   - Issue #4 - Java 9 Compliance
      - Updates several libraries and provides a workaround for Kryo
      to avoid Illegal access messages from JVM
   - Pull Request #58 - Fixed file naming issues when having multiple instances of an IP
   - Pull Request #60 - Horizontal density (pblock creation)
   - Pull Request #62 - Ensure that highlighted tile numbers are drawn above tile highlighting
   - Other bug fixes (see commit log for details).   


============= RapidWright 2019.2.1-beta released on 2020-03-10 ================
Notes:
 * Minor feature: 
     Module and ModuleInst information for physical hierarchy in
     designs is now stored with DCP files.
 - API Additions:
   - com.xilinx.rapidwright.design.Design "public Cell createAndPlaceCell(String name, Unisim cellType, String location, String...params)"
   - com.xilinx.rapidwright.design.Design "public Cell createAndPlaceCell(EDIFCell parent, String name, Unisim cellType, String location, String...params)"
   - com.xilinx.rapidwright.design.Design "public boolean renameSiteInst(SiteInst inst, String newName)"
   - com.xilinx.rapidwright.device.BELPin "public BELPin getSourcePin()"
   - com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(BELPin inputPin)"
   - com.xilinx.rapidwright.design.Cell "public Map<String,String> getPinMappingsL2P()"
   - com.xilinx.rapidwright.device.ClockRegion "public boolean hasTileColumn(int colIndex)"
   - com.xilinx.rapidwright.design.Design "public void addModuleImpls(ModuleImpls modImpls)"
 - Bug Fixes / Pull Requests:
   - Issue #56 - EDIF Parser fails on submodules with certain characters in their names
   - Pull Request #57 - TimingGroup: Make 'add' functions public
   - Pull Request #59 - Delay model changes (DelayModel interface is public, uses SiteTypeEnum instead of String)
   - Other bug fixes (see commit log for details).   


============= RapidWright 2019.2.0-beta released on 2019-12-11 ================
Notes:
 * Major feature: 
     Timing model and graph (published work at FPT 2019). Provides a
     data path delay model for UltraScale+ interconnect and logic.
     Provides approximate timing delays with ~2% error or less
     on average.  See com.xilinx.rapidwright.timing package and
     documentation for details.

 - API Additions:
   - com.xilinx.rapidwright.design.Cell "public Tile getTile()"
   - com.xilinx.rapidwright.design.ClockRegion "public static void calculateFrameECC(int[] frame, int[] mask)"
   - com.xilinx.rapidwright.design.ClockRegion "public SLR getSLR()"
   - com.xilinx.rapidwright.design.ClockRegion "public boolean containsTile(Tile tile)"
   - com.xilinx.rapidwright.device.Device "public SLR getMasterSLR()"
   - com.xilinx.rapidwright.device.Device "public SLR getSLRByConfigOrderIndex(int cfgOrderIdx)"
   - com.xilinx.rapidwright.device.SLR "public Device getDevice()"
   - com.xilinx.rapidwright.device.SLR "public Series getSeries()"
   - com.xilinx.rapidwright.device.SLR "public Collection<ClockRegion> getClockRegions()"
   - com.xilinx.rapidwright.device.SLR "public ClockRegion getClockRegion(String name)"
   - com.xilinx.rapidwright.device.SLR "public boolean hasClockRegion(String name)"
   - com.xilinx.rapidwright.device.SLR "public boolean containsTile(Tile tile)"
   - com.xilinx.rapidwright.device.SLR "public int getNumOfClockRegionRows()"
   - com.xilinx.rapidwright.device.SLR "public int getNumOfClockRegionColumns()"
   - com.xilinx.rapidwright.device.Tile "public SLR getSLR()"
 - Deprecated APIs:
   - com.xilinx.rapidwright.device.Device "public String getDeviceName()"
 - Bug Fixes:
   - Issue #51 - Missing macro proimitive definitions (DSP48E2)
   - Issue #52 - Re-enabled compact module format
   - Issue #54 - Fixed SLR name/index mismatch   
   - Several other bug fixes (see commit log for details).   

============= RapidWright 2019.1.2-beta released on 2019-09-30 ================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.Cell "public Map<SiteTypeEnum,Set<String>> getCompatiblePlacements()"
   - com.xilinx.rapidwright.device.PIP "public PIP(PIP prototype, Tile newTile)"
   - com.xilinx.rapidwright.design.Design "public static EDIFLibrary getMacroPrimitives(Series s)"
   - com.xilinx.rapidwright.design.Design "public Cell createCell(String instName, Unisim unisim)"
   - com.xilinx.rapidwright.device.Device "public String getName()"
   - com.xilinx.rapidwright.device.Device "public SLR[] getSLRs()"
   - com.xilinx.rapidwright.device.SLR "public String toString()"
   - com.xilinx.rapidwright.device.SLR "public String getName()"
 - Deprecated APIs:
   - com.xilinx.rapidwright.device.Device "public String getDeviceName()" 
 - Adds macro primitive expansion/translation and turns it on by
   default when loading EDIF/DCPs -- eliminates problems in netlist
   traversal and matches Vivado behavior on EDIF load
 - Fixes an issue when creating designs from scratch for certain
   devices not being loaded correctly in Vivado 
 - Updates device data to include SLR CONFIG_ORDER_INDEX property
 - Adjusts whitespace output in EDIF writer to more closely match Vivado generated 
   EDIF files
 - Several bug fixes (see commit log for details).   

============= RapidWright 2019.1.1-beta released on 2019-08-07 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.Design "public boolean removeSiteInst(SiteInst instance, boolean keepSitePinRouting)"
   - com.xilinx.rapidwright.design.Net "public Set<SiteInst> getSiteInsts()"
 - Removed APIs:
   - com.xilinx.rapidwright.design.SitePinInst "public ArrayList<Cell> getConnectedCells()"
   - com.xilinx.rapidwright.design.Design "public HashMap<String,EDIFPort> getNetlistPortMap()"
 - Improved GraalVM compatibility for C++ shared library creation.
   Some data files were being loaded using certain Kryo APIs that are
   incompatible with the native compilation flow in GraalVM.  This
   release replaced those APIs and improved startup time for use of
   those files by >10X (1.2 secs -> 0.1 secs).
 - Fixes a subtle internal site routing issue when creating module instances.  Most
   commonly seen on BRAMs with REGCLK* pins.  This ensures internal site routing
   matches to original template SiteInst.
 - Several bug fixes (see commit log for details).   

============= RapidWright 2019.1.0-beta released on 2019-07-01 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.device.Node "public boolean isTiedToGnd()"
   - com.xilinx.rapidwright.device.Node "public boolean isTiedToVcc()"
   - com.xilinx.rapidwright.device.Node "public boolean isTied()"
   - com.xilinx.rapidwright.design.Cell "public List<String> getAllPhysicalPinMappings(String logicalPin)"
   - com.xilinx.rapidwright.design.Net "public boolean rename(String newName)"
 - Deprecated APIs:
   - com.xilinx.rapidwright.design.SitePinInst "public ArrayList<Cell> getConnectedCells()"
   - com.xilinx.rapidwright.design.Design "public HashMap<String,EDIFPort> getNetlistPortMap()"
 - Bug Fixes:
   - Issue #32 - Adding the tied value of a node, see API additions above.
   - Issue #29 - Site.getIntTile() issues
   - Issue #12,#28 - Inserting 'src' folder as parent to 'com' folder.
   - Issue #33 - Fixes for createIBUFDS()
   - Issue #34 - Design.getNetlistPortMap() deprecated
   - Issue #36 - Updating Javadoc to reflect Routethru behavior
   - Issue #37 - Added getAllPhysicalPinMappings()
   - Issue #38,#39 - Created DesignTools.getConnectedCells(SitePinInst)
 - Support for Vivado 2019.1 devices.
 - Changes to enable GraalVM shared library compilation for
   interoperability with C++ (see documentation for tutorial details).
 - Several bug fixes (see commit log for details).   
 

============= RapidWright 2018.3.3-beta released on 2019-04-26 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.Cell "public boolean copyCell(String name, EDIFCellInst edifCellInst)"
   - com.xilinx.rapidwright.design.Cell "public boolean copyCell(String name, EDIFCellInst edifCellInst, SiteInst i)"
   - com.xilinx.rapidwright.device.Node "public Node(RouteNode routeNode)"
   - com.xilinx.rapidwright.device.Node "public Node getStartNode()"
   - com.xilinx.rapidwright.device.Node "public Node getEndNode()"
   - com.xilinx.rapidwright.device.Node "public Node getStartRouteNode()"
   - com.xilinx.rapidwright.device.Node "public Node getEndRouteNode()"
   - com.xilinx.rapidwright.design.Module "public void setValidPlacements(ArrayList<Site> placements)"
 - Adds stamp-based placement.  For designs with multiple instances of the same cell, this
   ability allows users to take an already placed and routed copy of the cell and apply that
   placement and routing to the various instances.  See DesignTools.stampPlacement() or 
   com.xilinx.rapidwright.examples.StampPlacement.java.
 - Several bug fixes (see commit log for details).   
 
 
============= RapidWright 2018.3.2-beta released on 2019-03-28 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.Cell "public boolean updateName(String newCellName)"
   - com.xilinx.rapidwright.design.Cell "public boolean isPlaced()"
   - com.xilinx.rapidwright.design.Design "public Cell addCell(Cell c)"
   - com.xilinx.rapidwright.design.Design "public void addSiteInst(SiteInst inst)";
   - com.xilinx.rapidwright.design.Design "public Net addNet(Net net)";
   - com.xilinx.rapidwright.design.Net "public boolean updateName(String newName)"
 - Fixes an issue related to creating a module instance if the cell instance isn't already present in the netlist
 - Adds return value for
 - com.xilinx.rapidwright.design.Design.removeNet(*), returns the net that was removed or null if unsuccessful
 - Changed behavior of com.xilinx.rapidwright.design.Design.removeSiteInst(SiteInst) -- now only unroutes portions of nets connected to SiteInst rather than the entire net.
 - Fixed potential NPE case in com.xilinx.rapidwright.design.Design.removeCell(Cell).
 - Changed com.xilinx.rapidwright.design.Net.addPins(ArrayList<SitePinInst>) to accept List<SitePinInst>.
 - Fixed an issue when unrouting partial nets in com.xilinx.rapidwright.design.Net.unroute().

============= RapidWright 2018.3.1-beta released on 2019-02-27 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.Design "public SiteInst createSiteInst(Site site)"
   - com.xilinx.rapidwright.design.Design "public SiteInst createSiteInst(String siteName)"
   - com.xilinx.rapidwright.design.Design "public SiteInst createSiteInst(String name, SiteTypeEnum type, Site placement)"
   - com.xilinx.rapidwright.design.SiteInst "public Cell getCell(BEL bel)"
   - com.xilinx.rapidwright.design.Cell "public Map<EDIFName, EDIFPropertyValue> getProperties()"
   - com.xilinx.rapidwright.design.Cell "public void setProperties(Map<EDIFName, EDIFPropertyValue> properties)"
 - API Removals (deprecated):
   - com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin, String outputPin)"
   - com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin, String outputPin)"
   - com.xilinx.rapidwright.device.Site "public BELPin[] getConnectedBELPins(int siteWireIndex)"
   - com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input, BELPin output)"
 - Changed the toString() method on SiteInst class to help address issue #23
 - Improved the error message when trying to create and place a transformed prim (issue #22)
 - Removed the Hessian library, no longer used
 - Fixes issue with SLRCrossingGenerator DCPs not always working with Vivado's clock router
 - Adds preliminary support for SAT routing
 - Pblock support for PerformanceExplorer

============= RapidWright 2018.3.0-beta released on 2019-01-10 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin)"
   - com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin)"
   - com.xilinx.rapidwright.design.SiteInst "public Set<String> getSiteWiresFromNet(Net net)"
   - com.xilinx.rapidwright.device.Device "public Node getNode(String name)"
   - com.xilinx.rapidwright.device.Device "public Wire getWire(String name)"
   - com.xilinx.rapidwright.device.Device "public PIP getPIP(String name)"
   - com.xilinx.rapidwright.device.Device "public SitePin getSitePin(String name)"
   - com.xilinx.rapidwright.device.Site "public Integer getSiteWireIndex(String siteWireName)"
   - com.xilinx.rapidwright.device.Site "public BELPin[] getBELPins(int siteWireIndex)"
   - com.xilinx.rapidwright.device.Site "public BELPin[] getBELPins(String siteWireName)"
   - com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input)"
   - com.xilinx.rapidwright.device.Wire "public Node getNode()"
 - Deprecated APIs:
   - com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin, String outputPin)"
   - com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin, String outputPin)"
   - com.xilinx.rapidwright.device.Site "public BELPin[] getConnectedBELPins(int siteWireIndex)"
   - com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input, BELPin output)"
 - Compatibility with Vivado 2018.3.0 and its devices
 - Adds support for RapidWright Jupyter Notebook kernels
 - Reduces device file size to improve download times and load times
 - Removes Hessian implementation dependency for PartNameTools resource file and
   ModuleCache files.  This was done to resolve Java >=9 issues with 
   obsolete reflection usage.
 - Removed com.xilinx.rapidwright.edif.InstPair class and replaced functionality
   with com.xilinx.rapidwright.edif.EDIFHierCellInst.
   
============= RapidWright 2018.2.5-beta released on 2018-11-28 =================
Notes:
 - Fixes an issue in
 com.xilinx.rapidwright.device.Tile.getWireConnections() that was
 causing an issue when routing clocking routes.  This was manifesting
 in the SLRCrosserGenerator demo.
Known Issues:
 - Netlists that have two ports by same name where one is a single bit
 bus and another is multi-bit are not currently supported (for
 example, a module has an input 'my_signal' and 'my_signal[2:0]' is
 currently not allowed in the EDIF parser.
 - Clock router in Router class is disabled (under development).  
 - PolynomialGenerator is a toy demonstration and does not produce a
 functionally valid circuit.  

============= RapidWright 2018.2.4-beta released on 2018-11-15 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.SiteInst "public boolean unrouteIntraSiteNet(BELPin src, BELPin snk)"
   - com.xilinx.rapidwright.design.SitePinInst "public void setSiteInst(SiteInst instance, boolean keepRouting"
   - com.xilinx.rapidwright.device.Wire "public ArrayList<PIP> getBackwardPIPs()"
   - com.xilinx.rapidwright.device.Wire "public ArrayList<PIP> getForwardPIPs()"
 - API Removals:
   - com.xilinx.rapidwright.device.Wire "public ? getBackwardPIPs()"
   - com.xilinx.rapidwright.device.Wire "public ? getForwardPIPs()"
 - Resolves issues: #14, 15
Known Issues:
 - Netlists that have two ports by same name where one is a single bit
 bus and another is multi-bit are not currently supported (for
 example, a module has an input 'my_signal' and 'my_signal[2:0]' is
 currently not allowed in the EDIF parser.
 - Clock router in Router class is disabled (under development).  
 - PolynomialGenerator is a toy demonstration and does not produce a
 functionally valid circuit.  

============= RapidWright 2018.2.3-beta released on 2018-10-29 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.design.Design "public Cell createAndPlaceIOB(String name, PinType dir, String pkgPin, String ioStandard, Net portNet, EDIFNet logNet)"
   - com.xilinx.rapidwright.design.Design "public Cell placeIOB(EDIFCellInst bufInst, String pkgPin, String ioStandard)"
 - API Removals:
   - com.xilinx.rapidwright.design.Design "public EDIFCellInst createIBUF(String portName, Site site, Net portNet, EDIFNet logNet, String ioStandard)"
   - com.xilinx.rapidwright.design.Design "public Cell createOBUF(String portName, Site site, Net portNet, EDIFNet logNet, String ioStandard)"
      
 - Enables fix to run HandPlacer in both modes of BlockStitcher (rapid_compile_ipi)
 - Fixes routing issue when loading two different devices
 - Fixes some issues related to creating top-level ports
 - Removes artificial anchor for Modules that do not have internal logic (anchor is allowed to be null)
 - Resolves issue: #8
Known Issues:
 - Netlists that have two ports by same name where one is a single bit
 bus and another is multi-bit are not currently supported (for
 example, a module has an input 'my_signal' and 'my_signal[2:0]' is
 currently not allowed in the EDIF parser.
 - Clock router in Router class is disabled (under development).  
 - PolynomialGenerator is a toy demonstration and does not produce a
 functionally valid circuit.  

============= RapidWright 2018.2.2-beta released on 2018-10-20 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.device.PIP "public boolean isRouteThru()"
   - com.xilinx.rapidwright.device.Site "public BEL[] getBELs()"
   - com.xilinx.rapidwright.design.SiteInst "public BEL[] getBELs()"
   - com.xilinx.rapidwright.design.SiteInst "public String getPrimarySitePinName(String alternateSitePinName)"
   - com.xilinx.rapidwright.design.SiteInst "public String getAlternateSitePinName(String primarySitePinName)"
   - com.xilinx.rapidwright.design.Module "public PBlock getPBlock()"
   - com.xilinx.rapidwright.design.Module "public void setPBlock(PBlock pblock)"
   - com.xilinx.rapidwright.design.Module "public Map<String, String> getMetaDataMap()"
   - com.xilinx.rapidwright.design.Module "public void setMetaDataMap(HashMap<String, String> metaDataMap)"
   
 - API Removals:
   - com.xilinx.rapidwright.design.Module "public String[] getExternalInputNames()"
   - com.xilinx.rapidwright.design.Module "public void setExternalInputNames(String[] externalInputNames)"
   - com.xilinx.rapidwright.design.Module "public String[] getExternalOutputNames()"
   - com.xilinx.rapidwright.design.Module "public void setExternalOutputNames(String[] externalOutputNames)"
   - com.xilinx.rapidwright.design.Module "public HashMap<String, ArrayList<String>> getMetaDataMap()"
   - com.xilinx.rapidwright.design.Module "public void setMetaDataMap(HashMap<String, ArrayList<String>> metaDataMap)"
   
 - API Renames:
   - com.xilinx.rapidwright.design.Module "public String getPBlock()" --> "public String getPBlockString()" 
 - Changes Implementation Guide File extension from '.impl.guide' to '.igf'
 - Fixed an issue in the HandPlacer where it would fail to start because of some missing saveDesign() methods.
 - Modules now store PBlocks when using the rapid_compile_ipi flow
 - If no impl guide file is supplied, rapid_compile_ipi will create an example file
 - enables non-LUT routethrus in Router
 - Resolves issue: #7
Known Issues:
 - Netlists that have two ports by same name where one is a single bit
 bus and another is multi-bit are not currently supported (for
 example, a module has an input 'my_signal' and 'my_signal[2:0]' is
 currently not allowed in the EDIF parser.
 - Clock router in Router class is disabled (under development).  
 - PolynomialGenerator is a toy demonstration and does not produce a
 functionally valid circuit.  

============= RapidWright 2018.2.1-beta released on 2018-10-15 =================
Notes:
 - API Additions:
   - com.xilinx.rapidwright.device.Site "public SiteTypeEnum[] getAlternateSiteTypeEnums()"
   - com.xilinx.rapidwright.design.SiteInst "public SiteTypeEnum getPrimarySiteTypeEnum()"
   - com.xilinx.rapidwright.design.SiteInst "public SiteTypeEnum[] getAlternateSiteTypeEnums()"
 - API Removals:
   - com.xilinx.rapidwright.device.Site "public SiteType getPrimarySiteType()"
 - Resolves issues: #5, #6
 - Preliminary tutorial for running IP Integrator flow (rapid_compile_ipi)
Known Issues:
 - Netlists that have two ports by same name where one is a single bit
 bus and another is multi-bit are not currently supported (for
 example, a module has an input 'my_signal' and 'my_signal[2:0]' is
 currently not allowed in the EDIF parser.
 - Clock router in Router class is disabled (under development).  
 - PolynomialGenerator is a toy demonstration and does not produce a
 functionally valid circuit.  
 - Issue #4 - JDK9 Compliance for some 3rd party libraries prints out warnings

============= RapidWright 2018.2.0-beta released on 2018-10-01 =================
Notes:
 - Initial release with new RapidWright API Library 
Known Issues:
 - Netlists that have two ports by same name where one is a single bit
 bus and another is multi-bit are not currently supported (for
 example, a module has an input 'my_signal' and 'my_signal[2:0]' is
 currently not allowed in the EDIF parser.
 - Clock router in Router class is disabled (under development).  
 - PolynomialGenerator is a toy demonstration and does not produce a
 functionally valid circuit.  
 - Issue #4 - JDK9 Compliance for some 3rd party libraries prints out warnings