Jade was out first-generation CGRA chip, which taped out in 2018.
- Jade - AHA first-generation CGRA, taped out May 2018
- Diablo - Processing Element (PE) used in Jade
- Pyroclast - Test board for Diablo
- Genesis2 - A perl-based chip generator language, used by Diablo
Jade is our first-generation CGRA chip, which taped out successfully in May of 2018. This travis script shows current status of the Jade tool flow. So long as this daily test passes, the Jade tool flow is still viable.
- CGRA Flow end-to-end test of hw and sw (StanfordAHA)
- CGRA Flow examples and documentation (StanfordAHA)
- CGRA Generator (Genesis2->Verilog (v) ) (StanfordAHA)
- Halide front end (Halide->CoreIR) (jeffsetter)
- CoreIR mapper (CoreIR->CoreIR) (StanfordAHA)
- PNR (CoreIR->bitstream (b) ) (Kuree)
- Testbench generator (b+v->output img) (StanfordAHA)
- CoreIR helpers (rdaly)
- CoreIR helpers (pycoreir) (leonart)
- Genesis2 generator framework (StanfordVLSI)
- Python-compatible PE spec for validation (phanrahan)
- CoreIR primitives (StanfordAHA)