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Got a first version of RPT prefetcher to work. WIP Scala CI #325: Commit 65b52ce pushed by Dolu1990
July 2, 2024 09:05 3m 32s prefetch
prefetch
July 2, 2024 09:05 3m 32s
fmax: litex soc now forced to keep tilelink timing buffers Scala CI #324: Commit 636acee pushed by Dolu1990
July 1, 2024 12:12 3m 52s prefetch
prefetch
July 1, 2024 12:12 3m 52s
Got very very basic hardware next-line prefetcher to work Scala CI #323: Commit aa38c72 pushed by Dolu1990
June 29, 2024 06:59 3m 23s prefetch
prefetch
June 29, 2024 06:59 3m 23s
cleanup bug fix Scala CI #322: Commit aa49197 pushed by Dolu1990
June 28, 2024 12:36 3m 48s prefetch
prefetch
June 28, 2024 12:36 3m 48s
sync before l1 d$ rework/cleaning Scala CI #321: Commit 8f8b3be pushed by Dolu1990
June 27, 2024 17:11 3m 49s prefetch
prefetch
June 27, 2024 17:11 3m 49s
software prefetcher WIP Scala CI #320: Commit 3746ec1 pushed by Dolu1990
June 27, 2024 10:36 3m 19s prefetch
prefetch
June 27, 2024 10:36 3m 19s
Add prefetch parameters and IntAluPlugin now make from for it. Scala CI #319: Commit 2ceced6 pushed by Dolu1990
June 27, 2024 08:00 3m 37s prefetch
prefetch
June 27, 2024 08:00 3m 37s
Enable MicroOp to have multiple MaskedLiterals Scala CI #318: Commit f83fa46 pushed by Dolu1990
June 27, 2024 07:13 3m 57s prefetch
prefetch
June 27, 2024 07:13 3m 57s
sync Scala CI #317: Commit 7b50ac8 pushed by Dolu1990
June 27, 2024 06:54 3m 30s dev
dev
June 27, 2024 06:54 3m 30s
fix #16 add --pyhsical-width xyz Scala CI #316: Commit 05ed94c pushed by Dolu1990
June 21, 2024 08:10 3m 29s dev
dev
June 21, 2024 08:10 3m 29s
sync Scala CI #315: Commit e991b31 pushed by Dolu1990
June 13, 2024 21:20 3m 32s dev
dev
June 13, 2024 21:20 3m 32s
Add litex axi3 support Scala CI #314: Commit 66974d1 pushed by Dolu1990
June 12, 2024 09:24 3m 52s dev
dev
June 12, 2024 09:24 3m 52s
doc++ Scala CI #313: Commit 4afe535 pushed by Dolu1990
June 11, 2024 10:57 3m 45s dev
dev
June 11, 2024 10:57 3m 45s
Update doc Scala CI #312: Commit ad03440 pushed by Dolu1990
June 11, 2024 10:12 3m 28s dev
dev
June 11, 2024 10:12 3m 28s
doc ++ Scala CI #311: Commit 1928911 pushed by Dolu1990
June 11, 2024 09:12 3m 21s dev
dev
June 11, 2024 09:12 3m 21s
update buildroot tuto Scala CI #310: Commit 2a5d3f0 pushed by Dolu1990
June 10, 2024 15:00 3m 46s dev
dev
June 10, 2024 15:00 3m 46s
Add litex buildroot tuto (wip) Scala CI #309: Commit 4cda296 pushed by Dolu1990
June 10, 2024 09:07 3m 37s dev
dev
June 10, 2024 09:07 3m 37s
Fix a lot of xprop and add boot mem init Scala CI #308: Commit 32ec8bd pushed by Dolu1990
June 7, 2024 16:31 3m 26s dev
dev
June 7, 2024 16:31 3m 26s
sync Scala CI #307: Commit d991713 pushed by Dolu1990
June 6, 2024 11:49 3m 34s dev
dev
June 6, 2024 11:49 3m 34s
Fix a few misspec and add a few pmu probes Scala CI #306: Commit e9324f0 pushed by Dolu1990
June 5, 2024 14:20 3m 52s dev
dev
June 5, 2024 14:20 3m 52s
Fix DispatchPlugin to allow late-alu to work when the pipeline is lon… Scala CI #305: Commit 102cc5a pushed by Dolu1990
May 30, 2024 14:17 3m 27s dev
dev
May 30, 2024 14:17 3m 27s
Fix https://github.com/SpinalHDL/NaxRiscv/issues/103 Scala CI #304: Commit b426896 pushed by Dolu1990
May 29, 2024 14:56 3m 32s dev
dev
May 29, 2024 14:56 3m 32s
sync Scala CI #303: Commit 61ed758 pushed by Dolu1990
May 28, 2024 10:58 3m 31s dev
dev
May 28, 2024 10:58 3m 31s
Add litex soc l2 self flush Scala CI #302: Commit 0ec757d pushed by Dolu1990
May 27, 2024 15:36 3m 32s dev
dev
May 27, 2024 15:36 3m 32s
Rework litex soc Scala CI #301: Commit 6912d4c pushed by Dolu1990
May 23, 2024 12:24 3m 24s dev
dev
May 23, 2024 12:24 3m 24s