From 17b0d1379a3cd4a2e2dbefa7d0f9bc281269f97e Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Fri, 10 Jan 2025 14:53:49 +0100 Subject: [PATCH] airoha: an7581: refresh DTS with changes for cpufreq, MTD and MMC Refresh DTS with required changes for cpufreq, MTD and MMC. While at it also fix wrong speed for MAC. Signed-off-by: Christian Marangi --- target/linux/airoha/dts/an7581-evb.dts | 31 ++++--- target/linux/airoha/dts/an7581.dtsi | 118 +++++++++++++++++++++++-- 2 files changed, 127 insertions(+), 22 deletions(-) diff --git a/target/linux/airoha/dts/an7581-evb.dts b/target/linux/airoha/dts/an7581-evb.dts index 3cf531a29c4401..9e88bc8a77b3ea 100644 --- a/target/linux/airoha/dts/an7581-evb.dts +++ b/target/linux/airoha/dts/an7581-evb.dts @@ -150,35 +150,40 @@ &spi_nand { partitions { - compatible = "airoha,fixed-partitions"; + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; bootloader@0 { label = "bootloader"; reg = <0x00000000 0x00080000>; + read-only; }; - tclinux@80000 { + art@200000 { + label = "art"; + reg = <0x00200000 0x00400000>; + }; + + tclinux@600000 { label = "tclinux"; - compatible = "denx,fit"; - reg = <0x00080000 0x02800000>; + reg = <0x00600000 0x03200000>; }; - tclinux_slave@2880000 { - label = "tclinux_slave"; - reg = <0x02880000 0x02800000>; + tclinux_slave@3800000 { + label = "tclinux_alt"; + reg = <0x03800000 0x03200000>; }; - rootfs_data@5080000 { + rootfs_data@6a00000 { label = "rootfs_data"; - reg = <0x5080000 0x00800000>; + reg = <0x06a00000 0x01400000>; }; - art@ffffffff { - compatible = "airoha,dynamic-art"; - label = "art"; - reg = <0xffffffff 0x00300000>; + reserved_bmt@7e00000 { + label = "reserved_bmt"; + reg = <0x07e00000 0x00200000>; + read-only; }; }; }; diff --git a/target/linux/airoha/dts/an7581.dtsi b/target/linux/airoha/dts/an7581.dtsi index 8abd736875c585..820ab0bfa8fb41 100644 --- a/target/linux/airoha/dts/an7581.dtsi +++ b/target/linux/airoha/dts/an7581.dtsi @@ -78,7 +78,10 @@ reg = <0x0>; operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -89,7 +92,10 @@ reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -100,7 +106,10 @@ reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -111,7 +120,10 @@ reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; - clock-frequency = <80000000>; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -125,68 +137,156 @@ }; }; + cpufreq: cpufreq { + compatible = "airoha,en7581-cpufreq"; + + operating-points-v2 = <&cpu_smcc_opp_table>; + + #power-domain-cells = <0>; + #clock-cells = <0>; + }; + cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; opp-500000000 { opp-hz = /bits/ 64 <500000000>; + required-opps = <&smcc_opp0>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; + required-opps = <&smcc_opp1>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; + required-opps = <&smcc_opp2>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; + required-opps = <&smcc_opp3>; }; opp-7000000000 { opp-hz = /bits/ 64 <700000000>; + required-opps = <&smcc_opp4>; }; opp-7500000000 { opp-hz = /bits/ 64 <750000000>; + required-opps = <&smcc_opp5>; }; opp-8000000000 { opp-hz = /bits/ 64 <800000000>; + required-opps = <&smcc_opp6>; }; opp-8500000000 { opp-hz = /bits/ 64 <850000000>; + required-opps = <&smcc_opp7>; }; opp-9000000000 { opp-hz = /bits/ 64 <900000000>; + required-opps = <&smcc_opp8>; }; opp-9500000000 { opp-hz = /bits/ 64 <950000000>; + required-opps = <&smcc_opp9>; }; opp-10000000000 { opp-hz = /bits/ 64 <1000000000>; + required-opps = <&smcc_opp10>; }; opp-10500000000 { opp-hz = /bits/ 64 <1050000000>; + required-opps = <&smcc_opp11>; }; opp-11000000000 { opp-hz = /bits/ 64 <1100000000>; + required-opps = <&smcc_opp12>; }; opp-11500000000 { opp-hz = /bits/ 64 <1150000000>; + required-opps = <&smcc_opp13>; }; opp-12000000000 { opp-hz = /bits/ 64 <1200000000>; + required-opps = <&smcc_opp14>; + }; + }; + + cpu_smcc_opp_table: opp-table-cpu-smcc { + compatible = "operating-points-v2"; + + smcc_opp0: opp0 { + opp-level = <0>; + }; + + smcc_opp1: opp1 { + opp-level = <1>; + }; + + smcc_opp2: opp2 { + opp-level = <2>; + }; + + smcc_opp3: opp3 { + opp-level = <3>; + }; + + smcc_opp4: opp4 { + opp-level = <4>; + }; + + smcc_opp5: opp5 { + opp-level = <5>; + }; + + smcc_opp6: opp6 { + opp-level = <6>; + }; + + smcc_opp7: opp7 { + opp-level = <7>; + }; + + smcc_opp8: opp8 { + opp-level = <8>; + }; + + smcc_opp9: opp9 { + opp-level = <9>; + }; + + smcc_opp10: opp10 { + opp-level = <10>; + }; + + smcc_opp11: opp11 { + opp-level = <11>; + }; + + smcc_opp12: opp12 { + opp-level = <12>; + }; + + smcc_opp13: opp13 { + opp-level = <13>; + }; + + smcc_opp14: opp14 { + opp-level = <14>; }; }; @@ -431,16 +531,16 @@ spi-max-frequency = <50000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <2>; - airoha,bmt; }; }; mmc0: mmc@1fa0e000 { - compatible = "mediatek,mt7622-mmc"; + compatible = "airoha,an7581-mmc"; reg = <0x0 0x1fa0e000 0x0 0x1000>, <0x0 0x1fa0c000 0x0 0x60>; interrupts = ; - bus-width = <4>; + clocks = <&scuclk EN7581_CLK_EMMC>; + clock-names = "source"; bus-width = <4>; max-frequency = <52000000>; disable-wp; cap-mmc-highspeed; @@ -587,7 +687,7 @@ status = "disabled"; fixed-link { - speed = <1000>; + speed = <10000>; full-duplex; pause; }; @@ -648,7 +748,7 @@ phy-mode = "internal"; fixed-link { - speed = <1000>; + speed = <10000>; full-duplex; pause; };