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NetFPGA-1G.html
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---
layout: page
---
<h1>NetFPGA 1G</h1>
<br>
<div id="accordion-1G1" class="accordion">
<div class="" data-toggle="collapse" href="#collapse-1G1">
<button class="card-title"><h2>Details  </h2></button>
</div>
<div id="collapse-1G1" class="collapse show" data-parent="#accordion-1G1">
<p>The NetFPGA is the low-cost reconfigurable hardware platform optimized for high-speed networking. The NetFPGA includes the all fo the logic resources, memory, and Gigabit Ethernet interfaces necessary to build a complete switch, router, and/or security device. Because the entire datapath is implemented in hardware, the system can support back-to-back packets at full Gigabit line rates and has a processing latency measured in only a few clock cycles.</p>
<ul>
<li>Field Programmable Gate Array (FPGA) Logic <ul>
<li><a href="http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex_ii_pro_fpgas/resources/index.htm" >Xilinx Virtex-II Pro 50</a></li>
<li>53,136 logic cells</li>
<li>4,176 Kbit block RAM</li>
<li>up to 738 Kbit distributed RAM</li>
<li>2 x PowerPC cores</li>
<li>Fully programmable by the user</li>
</ul></li>
<li>Gigabit Ethernet networking ports <ul>
<li>Connector block on left of PCB interfaces to 4 external RJ45 plugs</li>
<li>Interfaces with standard Cat5E or Cat6 copper network cables using <a href="http://www.broadcom.com/" >Broadcom</a> PHY</li>
<li>Wire-speed processing on all ports at all time using FPGA logic <ul>
<li>1 Gbits * 2 (bi-directional) * 4 (ports) = 8 Gbps throughput</li>
</ul></li>
</ul></li>
<li>Static Random Access Memory (SRAM) <ul>
<li>Suitable for storing forwarding table data</li>
<li>Zero-bus turnaround (ZBT), synchronous with the logic</li>
<li>Two parallel banks of 18 MBit (2.25 MByte) ZBT memories</li>
<li>Total capacity: 4.5 MBytes</li>
<li>Cypress: CY7C1370D-167AXC</li>
</ul></li>
<li>Double-Date Rate Random Access Memory (DDR2 DRAM) <ul>
<li>400 MHz Asynchronous clock</li>
<li>Suitable for packet buffering</li>
<li>25.6 Gbps peak memory throughput</li>
<li>Total capacity: 64 MBytes</li>
<li><a href="http://www.micron.com/" >Micron: MT47H16M16BG-5E</a></li>
</ul></li>
<li>Multi-gigabit I/O <ul>
<li>Two SATA-style connectors to Multi-Gigabit I/O (MGIO) on right-side of PCB</li>
<li>Allows multiple NetFPGAs within a PC to be chained together</li>
</ul></li>
<li>Standard PCI Form Factor <ul>
<li>Standard PCI card</li>
<li>Can be used in a PCI-X slot</li>
<li>Enables fast reconfiguration of the FPGA over PCI bus without using JTAG cable</li>
<li>Provides CPU access to memory-mapped registers and memory on the NetFPGA hardware</li>
</ul></li>
<li>Hardware Debugging ports <ul>
<li>JTAG cable connector can be used to run Xilinx ChipScope Pro</li>
</ul></li>
<li>Flexible, Open-source code <ul>
<li>BSD-style open-source reference router available from the NetFPGA.org website. Download it, use it, keep it, give back to the community if you choose.</li>
</ul></li>
</ul>
</div>
</div>
<br>
<hr>
<div id="accordion-1G2" class="accordion">
<div class="collapsed" data-toggle="collapse" href="#collapse-1G2">
<button class="card-title"><h2>Downloads  </h2></button>
</div>
<div id="collapse-1G2" class="collapse" data-parent="#accordion-1G2">
<h3>Projects</h3>
<table class="downloads">
<tr>
<th>Title</th>
<th>Organisation</th>
<th>Documentation</th>
</tr>
<tr>
<td>IPv4 Reference Router</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/ReferenceRouterWalkthrough" >Wiki</a></td>
</tr>
<tr>
<td>Quad-Port Gigabit NIC</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/ReferenceNICWalkthrough" >Wiki</a></td>
</tr>
<tr>
<td>Ethernet Switch</td>
<td>Stanford University</td>
<td>Wiki</td>
</tr>
<tr>
<td>Buffer Monitoring System</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/BufferMonitoringSystem" >Wiki</a></td>
</tr>
<tr>
<td>Hardware-Accelerated Linux Router</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/RouterKitWalkthrough" >Wiki</a></td>
</tr>
<tr>
<td>DRAM-Router</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/DRAMRouter" >Wiki</a></td>
</tr>
<tr>
<td>DRAM-Queue Test</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/DRAMQueueTest" >Wiki</a></td>
</tr>
<tr>
<td>Packet Generator</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/PacketGenerator" >Wiki</a></td>
</tr>
<tr>
<td>OpenFlow Switch</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/OpenFlowNetFPGA100" >Wiki</a></td>
</tr>
<tr>
<td>NetFlow Probe</td>
<td>Brno University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/NetFlowProbe" >Wiki</a></td>
</tr>
<tr>
<td>AirFPGA</td>
<td>Stanford University</td>
<td>Wiki</td>
</tr>
<tr>
<td>Fast Reroute & Multipath Router</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/FastRerouteAndMultipathRouter" >Wiki</a></td>
</tr>
<tr>
<td>NetThreads</td>
<td>University of Toronto</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/NetThreads" >Wiki</a></td>
</tr>
<tr>
<td>NetThreads-RE</td>
<td>University of Toronto</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/NetThreadsRE" >Wiki</a></td>
</tr>
<tr>
<td>NetTM</td>
<td>University of Toronto</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/NetTM" >Wiki</a></td>
</tr>
<tr>
<td>Precise Traffic Generator</td>
<td>University of Toronto</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/PreciseTrafGen" >Wiki</a></td>
</tr>
<tr>
<td>URL Extraction</td>
<td>Univ. of New South Wales</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/URL" >Wiki</a></td>
</tr>
<tr>
<td>zFilter Sprouter (Pub/Sub)</td>
<td>Ericsson</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/ZFilter" >Wiki</a></td>
</tr>
<tr>
<td>Windows Driver</td>
<td>Microsoft Research</td>
<td><a href="http://research.microsoft.com/en-us/downloads/78fad92b-87aa-4f3a-963a-9df15770e919/" >Wiki</a></td>
</tr>
<tr>
<td>RED</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/RED" >Wiki</a></td>
</tr>
<tr>
<td>Open Network Lab</td>
<td>Washington University</td>
<td>Wiki</td>
</tr>
<tr>
<td>DFA</td>
<td>UMass Lowell</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/DFA" >Wiki</a></td>
</tr>
<tr>
<td>G/PaX</td>
<td>Xilinx</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/G" >Wiki</a></td>
</tr>
<tr>
<td>RCP Router</td>
<td>Stanford University</td>
<td>Wiki</td>
</tr>
<tr>
<td>Deficit Round Robin (DRR)</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/DRRNetFPGA" >Wiki</a></td>
</tr>
<tr>
<td>OpenFlow-MPLS Switch</td>
<td>Ericsson</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/OpenFlowMPLSSwitch" >Wiki</a></td>
</tr>
<tr>
<td>PTP-enabled Router</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/PTPRouter" >Wiki</a></td>
</tr>
<tr>
<td>Vlan Tag Handler</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/VlanTagHandler" >Wiki</a></td>
</tr>
<tr>
<td>Port Aggregator</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/PortAggregator" >Wiki</a></td>
</tr>
<tr>
<td>IP Lookup w/Blooming Tree</td>
<td>University of Pisa</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/Blooming" >Wiki</a></td>
</tr>
<tr>
<td>KOREN Testbed</td>
<td>Chungnam-Korea</td>
<td>Wiki</td>
</tr>
<tr>
<td>Virtual Data Plane</td>
<td>Georgia Tech</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/VirtualDataPlane" >Wiki</a></td>
</tr>
<tr>
<td>Deficit Round Robin (DRR) Input Arbiter</td>
<td>Universidade Federal do Rio Grande do Sul (Brazil)</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/DRRInputArbiter" >Wiki</a></td>
</tr>
<tr>
<td>Counter Braids</td>
<td>Stanford (Lu, Jianying)</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/CounterBraids" >Wiki</a></td>
</tr>
<tr>
<td>Ethernet Switch with Real-time support</td>
<td>University of Waterloo and Universidad de Concepcion</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/RealTimeSwitch" >Wiki</a></td>
</tr>
<tr>
<td>End-to-End Ethernet Authorization</td>
<td>Euskal Herriko Unibertsitateko</td>
<td>Wiki</td>
</tr>
<tr>
<td>Ultra-high Speed Congestion-control</td>
<td>University of North Carolina</td>
<td>Wiki</td>
</tr>
<tr>
<td>Promiscuous Reference Router</td>
<td>University of Catania</td>
<td>Wiki</td>
</tr>
<tr>
<td>BORPH (Operating System)</td>
<td>University of Hong Kong / University of Cape Town</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/BORPH" >Wiki</a></td>
</tr>
<tr>
<td>Traffic Monitor</td>
<td>University of Catania</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/TrafficMonitor" >Wiki</a></td>
</tr>
<tr>
<td>Latency Measurement Module</td>
<td>Algo-Logic Systems</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/MeasurmentModule" >Wiki</a></td>
</tr>
<tr>
<td>NetFPGA Logic Analyzer</td>
<td>USC/ISI</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/LogicalAnalyzer" >Wiki</a></td>
</tr>
<tr>
<td>Bounded Jitter Policy</td>
<td>University of Toronto</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/BJP" >Wiki</a></td>
</tr>
<tr>
<td>Traffic Classifier</td>
<td>University of Toronto</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/TrafficClassification" >Wiki</a></td>
</tr>
<tr>
<td>Network IO Fairness</td>
<td>Georgia Tech</td>
<td>Wiki</td>
</tr>
<tr>
<td>Tunneling OpenFlow Switch with ICMP</td>
<td>Stanford University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/TunnelingOpenFlowNetFPGA100ICMP" >Wiki</a></td>
</tr>
<tr>
<td>zFormation PSrouter (Pub/Sub)</td>
<td>Ericsson</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/ZFormationPSrouter" >Wiki</a></td>
</tr>
<tr>
<td>High Performance Packet Classifier</td>
<td>University of Pisa</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/HighPerformancePacketClassifier" >Wiki</a></td>
</tr>
<tr>
<td>Flexible Router</td>
<td>University of Catania</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/Flexrouter" >Wiki</a></td>
</tr>
<tr>
<td>Monitoring System</td>
<td>University of Pisa / University of Cambridge</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/MonitoringSystem" >Wiki</a></td>
</tr>
<tr>
<td>Deficit Round Robin Router Backplane</td>
<td>Cairo University</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/DeficitRoundRobinRouterBackplane" >Wiki</a></td>
</tr>
<tr>
<td>NetCoding Project Transmit Node</td>
<td>?</td>
<td><a href="https://docs.google.com/file/d/0B4EuVzA5UdPRVG5EcGpkaGp4dTQ/edit?usp=sharing" >Download</a></td>
</tr>
<tr>
<td>Router Buffer Adaptation</td>
<td>University of New South Wales</td>
<td><a href="https://github.com/NetFPGA/netfpga/wiki/RouterBufferAdaptation" >Wiki</a></td>
</tr>
</table>
</div>
</div>
<br>
<hr>
<div id="accordion-1G4" class="accordion">
<div class="collapsed" data-toggle="collapse" href="#collapse-1G4">
<button class="card-title"><h2>Resources  </h2></button>
</div>
<div id="collapse-1G4" class="collapse" data-parent="#accordion-1G4">
<br>
<p class="FAQ">Where can I buy a NetFPGA 1G platform</p>
<ul>
<li>Check <a href="http://www.digilentinc.com/Products/Detail.cfm?NavTop=2&NavSub=521&Prod=NETFPGA&CFID=6415051&CFTOKEN=b9cd02fdf0c5c90e-97AD3ABC-5056-0201-020BD3EF8B8AD74C" >here</a>.</li>
</ul>
<p class="FAQ">It seems that my board is broken, what should I do?</p>
<ul>
<li>Contact your <a href="http://www.digilentinc.com/contact.cfm" >suppliers</a>.</li>
</ul>
<p class="FAQ">What if I have Hardware problems with my boards?</p>
<ul>
<li>Contact your <a href="http://www.digilentinc.com/contact.cfm" >suppliers</a>.</li>
</ul>
<p class="FAQ">What if I have Software problems with my board?</p>
<ul>
<li>Register to the NetFPGA Forums.</li>
</ul>
<p>You can exchange your ideas and questions with the NetFPGA community <a href="https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga" >here</a>.</p>
<p class="FAQ">How can I get involved with the NetFPGA project?</p>
<ul>
<li>Register with the <a href="https://lists.cam.ac.uk/mailman/listinfo/cl-netfpga-announce" >netfpga-announce mailing list</a> to receive NetFPGA project announcements</li>
<li>Become a <a href="http://www.facebook.com/home.php#/pages/NetFPGA/29922917839" >fan on Facebook</a>.</li>
<li>Become a <a href="https://twitter.com/netfpga" >fan on Twitter</a>.</li>
</ul>
<p class="FAQ">How can I obtain the gateware and software package?</p>
<ul>
<li><a href="https://github.com/NetFPGA/netfpga/wiki/Guide" >Guide</a></li>
<li><a href="https://github.com/NetFPGA/netfpga/wiki/Releases" >Releases</a></li>
<li><a href="{% link _pages/1G-License.html %}" >NetFPGA 1G license</a></li>
</ul>
<br>
<p>Once you have used the NetFPGA, we hope that you will contribute to the project.</p>
<br>
<p>You can find our Wiki <a href="https://github.com/NetFPGA/netfpga/wiki" >here</a>.</p>
</div>
</div>
<br>
<hr>