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vivado_9988.backup.log
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vivado_9988.backup.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Thu Dec 9 08:00:39 2021
# Process ID: 9988
# Current directory: G:/Projet_instrum_MHAH
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8696 G:\Projet_instrum_MHAH\Projet_instrum_MHAH.xpr
# Log file: G:/Projet_instrum_MHAH/vivado.log
# Journal file: G:/Projet_instrum_MHAH\vivado.jou
#-----------------------------------------------------------
start_gui
open_project G:/Projet_instrum_MHAH/Projet_instrum_MHAH.xpr
IINFO: [Project 1-313] Project file moved from 'D:/Projet_instrum_MHAH' since last save.SScanning sources...FFinished scanning sourcesIINFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specifiedIINFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.open_project: Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1112.062 ; gain = 0.000
update_compile_order -fileset sources_1
set_property top filter [current_fileset]
update_compile_order -fileset sources_1
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a100tcsg324-3
Top: filter
INFO: [Device 21-403] Loading part xc7a100tcsg324-3
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1496.285 ; gain = 244.344
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
ERROR: [Synth 8-690] width mismatch in assignment; target has 43 bits, source has 44 bits [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:54]
WARNING: [Synth 8-614] signal 'xk' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
WARNING: [Synth 8-614] signal 'input_filt' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
WARNING: [Synth 8-614] signal 'yk' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
WARNING: [Synth 8-614] signal 'cst' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
WARNING: [Synth 8-614] signal 'xk_1' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
WARNING: [Synth 8-614] signal 'yk_1' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
ERROR: [Synth 8-285] failed synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1545.875 ; gain = 293.934
---------------------------------------------------------------------------------
RTL Elaboration failed
2 Infos, 6 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a100tcsg324-3
Top: filter
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1545.875 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
WARNING: [Synth 8-614] signal 'cst' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'filter' (1#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1554.934 ; gain = 9.059
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1578.516 ; gain = 32.641
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1578.516 ; gain = 32.641
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1578.516 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'output[0]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'output[1]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'output[2]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'output[3]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'output[4]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'output[5]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'output[6]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'output[7]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'vauxn3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'vauxp3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1625.348 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
RTL Elaboration Complete: : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1715.914 ; gain = 170.039
4 Infos, 11 Warnings, 10 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1715.914 ; gain = 170.039
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_filter.vhd w ]
add_files -fileset sim_1 G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/tb_filter.vhd
update_compile_order -fileset sim_1
set_property top filter [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
set_property top_arch Behavioral [get_filesets sim_1]
set_property top_file G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd [get_filesets sim_1]
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
close [ open G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd w ]
add_files G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd
update_compile_order -fileset sources_1
close [ open G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd w ]
add_files G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd
update_compile_order -fileset sources_1
set_property top ADC_12b [current_fileset]
update_compile_order -fileset sources_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1807.461 ; gain = 56.273
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'ADC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:77]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (1#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
ERROR: [Synth 8-549] port width mismatch for port 'value_in': port width = 8, actual width = 12 [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:77]
ERROR: [Synth 8-549] port width mismatch for port 'value_out': port width = 8, actual width = 12 [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:63]
ERROR: [Synth 8-285] failed synthesizing module 'ADC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1841.043 ; gain = 89.855
---------------------------------------------------------------------------------
RTL Elaboration failed
refresh_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1841.078 ; gain = 89.891
ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
update_compile_order -fileset sources_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1867.062 ; gain = 11.121
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'ADC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:76]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'ADC' declared at 'g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (1#1) [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (2#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-256] done synthesizing module 'ADC_12b' (3#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1867.445 ; gain = 11.504
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1869.426 ; gain = 13.484
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1869.426 ; gain = 13.484
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1870.965 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1870.965 ; gain = 15.023
close [ open G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd w ]
add_files G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd
update_compile_order -fileset sources_1
set_property top DAC_12b [current_fileset]
update_compile_order -fileset sources_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1870.965 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'DAC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:21]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:40]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (1#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:46]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (2#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'DAC_12b' (3#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:21]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1870.965 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1870.965 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1870.965 ; gain = 0.000
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1870.965 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'vauxn3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'vauxp3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 1870.965 ; gain = 0.000
set_property top test_filter [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
refresh_design
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'vauxn3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'vauxp3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'vauxn3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'vauxp3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'global_output[0]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[1]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[2]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[3]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[4]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[5]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[6]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[7]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'i_vauxn3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'i_vauxp3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
update_compile_order -fileset sim_1
refresh_design
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'global_output[0]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[1]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[2]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[3]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[4]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[5]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[6]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[7]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'i_vauxn3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'i_vauxp3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
reset_run synth_1
ERROR: [Vivado 12-106] *** Exception: ui.utils.e: ui.frmwork.cmd.CommandFailedException: boost::filesystem::status: Accès refusé: "G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/.route_design.begin.rst" ui.frmwork.cmd.CommandFailedException: boost::filesystem::status: Accès refusé: "G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/.route_design.begin.rst"
at ui.project.projecti.ProjStateHelper_getBlingString(Native Method)
at ui.project.p.hLa(SourceFile:65)
at ui.data.experiment.D.czB(SourceFile:210)
at ui.data.experiment.F.aOt(SourceFile:378)
at ui.frmwork.y.run(SourceFile:203)
at java.base/java.lang.Thread.run(Thread.java:834)
(See G:/Projet_instrum_MHAH/vivado_pid7668.debug)
ERROR: [Common 17-39] 'reset_runs' failed due to earlier errors.
refresh_design
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
WARNING: [Vivado 12-584] No ports matched 'global_output[0]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:85]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[1]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:86]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[2]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:87]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[3]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:88]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[4]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:89]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[5]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:90]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[6]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:91]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'global_output[7]'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:92]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'vauxn3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:125]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'vauxp3'. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc:126]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
set_property top DAC_test [current_fileset]
update_compile_order -fileset sources_1
set_property top test_filter [current_fileset]
update_compile_order -fileset sources_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1938.559 ; gain = 16.383
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
INFO: [Synth 8-3491] module 'filter' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:33' bound to instance 'U_filter' of component 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:72]
INFO: [Synth 8-638] synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
WARNING: [Synth 8-614] signal 'cst' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
ERROR: [Synth 8-690] width mismatch in assignment; target has 12 bits, source has 2 bits [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:58]
ERROR: [Synth 8-285] failed synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
ERROR: [Synth 8-285] failed synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1938.574 ; gain = 16.398
---------------------------------------------------------------------------------
RTL Elaboration failed
refresh_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1938.574 ; gain = 16.398
ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
launch_runs synth_1 -jobs 4
[Thu Dec 9 09:31:11 2021] Launched synth_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
reset_run synth_1
launch_runs synth_1 -jobs 4
[Thu Dec 9 09:31:44 2021] Launched synth_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1959.953 ; gain = 18.805
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
INFO: [Synth 8-3491] module 'filter' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:33' bound to instance 'U_filter' of component 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:72]
INFO: [Synth 8-638] synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
WARNING: [Synth 8-614] signal 'cst' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
ERROR: [Synth 8-690] width mismatch in assignment; target has 12 bits, source has 2 bits [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:58]
ERROR: [Synth 8-285] failed synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
ERROR: [Synth 8-285] failed synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1959.961 ; gain = 18.812
---------------------------------------------------------------------------------
RTL Elaboration failed
refresh_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1959.961 ; gain = 18.812
ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1960.121 ; gain = 0.160
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
INFO: [Synth 8-3491] module 'filter' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:33' bound to instance 'U_filter' of component 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:72]
INFO: [Synth 8-638] synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
WARNING: [Synth 8-614] signal 'cst' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'filter' (1#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
ERROR: [Synth 8-549] port width mismatch for port 'output_filt': port width = 12, actual width = 8 [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:51]
ERROR: [Synth 8-285] failed synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1960.664 ; gain = 0.703
---------------------------------------------------------------------------------
RTL Elaboration failed
refresh_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1960.664 ; gain = 0.703
ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1976.457 ; gain = 15.539
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
INFO: [Synth 8-3491] module 'filter' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:33' bound to instance 'U_filter' of component 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:72]
INFO: [Synth 8-638] synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
WARNING: [Synth 8-614] signal 'cst' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'filter' (1#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
ERROR: [Synth 8-549] port width mismatch for port 'output_filt': port width = 12, actual width = 8 [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:75]
ERROR: [Synth 8-285] failed synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1976.457 ; gain = 15.539
---------------------------------------------------------------------------------
RTL Elaboration failed
refresh_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1976.457 ; gain = 15.539
ERROR: [Common 17-39] 'refresh_design' failed due to earlier errors.
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1977.258 ; gain = 0.801
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
INFO: [Synth 8-3491] module 'filter' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:33' bound to instance 'U_filter' of component 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:72]
INFO: [Synth 8-638] synthesizing module 'filter' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
WARNING: [Synth 8-614] signal 'cst' is read in the process but is not in the sensitivity list [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'filter' (1#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd:40]
INFO: [Synth 8-3491] module 'ADC_12b' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:34' bound to instance 'U_ADC_12b' of component 'ADC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:78]
INFO: [Synth 8-638] synthesizing module 'ADC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:76]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'ADC' declared at 'g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (2#1) [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (3#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-256] done synthesizing module 'ADC_12b' (4#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_12b.vhd:42]
INFO: [Synth 8-3491] module 'DAC_12b' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:14' bound to instance 'U_DAC_12b' of component 'DAC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:85]
INFO: [Synth 8-638] synthesizing module 'DAC_12b' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:21]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:40]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (5#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:46]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (6#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'DAC_12b' (7#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/DAC_12b.vhd:21]
INFO: [Synth 8-256] done synthesizing module 'test_filter' (8#1) [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_filter.vhd:43]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1977.258 ; gain = 0.801
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1977.258 ; gain = 0.801
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1977.258 ; gain = 0.801
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1991.941 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_12b/U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [g:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_12b/U_ADC_global/U_ADC/U0'
Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Finished Parsing XDC File [G:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 1991.941 ; gain = 15.484
open_hw_manager
connect_hw_server -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2020.2
**** Build date : Nov 18 2020 at 10:01:48
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3417] Launching cs_server...
INFO: [Labtools 27-2221] Launch Output:
******** Xilinx cs_server v2020.2
****** Build date : Nov 03 2020-22:02:56
**** Build number : 2020.2.1604437376
** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved.
connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:19 . Memory (MB): peak = 1993.121 ; gain = 1.180
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292AA7656A
open_hw_target: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3408.309 ; gain = 1415.188
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Thu Dec 9 09:40:49 2021] Launched synth_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Thu Dec 9 09:40:49 2021] Launched impl_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Thu Dec 9 09:41:12 2021] Launched synth_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Thu Dec 9 09:41:12 2021] Launched impl_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
reset_run impl_1
launch_runs impl_1 -jobs 4
[Thu Dec 9 09:41:27 2021] Launched synth_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Thu Dec 9 09:41:27 2021] Launched impl_1...
Run output will be captured here: G:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
reset_run synth_1
close_project
exit
INFO: [Common 17-206] Exiting Vivado at Thu Dec 9 09:46:12 2021...