-
Notifications
You must be signed in to change notification settings - Fork 0
/
vivado_7772.backup.log
492 lines (476 loc) · 36.2 KB
/
vivado_7772.backup.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Mon Nov 29 14:11:13 2021
# Process ID: 7772
# Current directory: D:/Projet_instrum_MHAH
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent540 D:\Projet_instrum_MHAH\Projet_instrum_MHAH.xpr
# Log file: D:/Projet_instrum_MHAH/vivado.log
# Journal file: D:/Projet_instrum_MHAH\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/Projet_instrum_MHAH/Projet_instrum_MHAH.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:08 . Memory (MB): peak = 1111.922 ; gain = 0.000
update_compile_order -fileset sources_1
open_hw_manager
connect_hw_server -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2020.2
**** Build date : Nov 18 2020 at 10:01:48
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3417] Launching cs_server...
INFO: [Labtools 27-2221] Launch Output:
******** Xilinx cs_server v2020.2
****** Build date : Nov 03 2020-22:02:56
**** Build number : 2020.2.1604437376
** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved.
connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 1111.922 ; gain = 0.000
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292B0F12DA
open_hw_target: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2531.953 ; gain = 1420.031
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 14:24:16 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 14:24:16 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 14:29:58 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 14:29:58 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a100tcsg324-3
Top: test_ADC
INFO: [Device 21-403] Loading part xc7a100tcsg324-3
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3154.316 ; gain = 261.492
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:41]
ERROR: [Synth 8-690] width mismatch in assignment; target has 12 bits, source has 8 bits [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:73]
ERROR: [Synth 8-285] failed synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:41]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3198.895 ; gain = 306.070
---------------------------------------------------------------------------------
RTL Elaboration failed
2 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a100tcsg324-3
Top: test_ADC
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3217.656 ; gain = 12.273
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:41]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:75]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
WARNING: [Synth 8-614] signal 'buffer1' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:25]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
ERROR: [Synth 8-549] port width mismatch for port 'value_in': port width = 8, actual width = 12 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:75]
ERROR: [Synth 8-549] port width mismatch for port 'value_out': port width = 8, actual width = 12 [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:61]
ERROR: [Synth 8-285] failed synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:41]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3217.656 ; gain = 12.273
---------------------------------------------------------------------------------
RTL Elaboration failed
4 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7a100tcsg324-3
Top: test_ADC
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3220.965 ; gain = 3.309
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:41]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:75]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
WARNING: [Synth 8-614] signal 'buffer1' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:25]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:81]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (2#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:86]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:23]
INFO: [Synth 8-3491] module 'ADC' declared at 'd:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (3#1) [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (4#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:23]
INFO: [Synth 8-256] done synthesizing module 'test_ADC' (5#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:41]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3220.965 ; gain = 3.309
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3234.965 ; gain = 17.309
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 3234.965 ; gain = 17.309
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3246.957 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Finished Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3285.406 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
RTL Elaboration Complete: : Time (s): cpu = 00:00:23 ; elapsed = 00:00:16 . Memory (MB): peak = 3344.371 ; gain = 126.715
19 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:17 . Memory (MB): peak = 3344.371 ; gain = 126.715
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 14:38:17 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 14:38:17 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3416.328 ; gain = 55.996
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:42]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:76]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
WARNING: [Synth 8-614] signal 'buffer1' is read in the process but is not in the sensitivity list [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:25]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:82]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (2#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:87]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:23]
INFO: [Synth 8-3491] module 'ADC' declared at 'd:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (3#1) [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (4#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:23]
INFO: [Synth 8-256] done synthesizing module 'test_ADC' (5#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:42]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3450.480 ; gain = 90.148
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3474.387 ; gain = 114.055
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3474.387 ; gain = 114.055
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3477.379 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Finished Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 3477.379 ; gain = 117.047
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 14:47:25 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 14:47:25 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 14:50:34 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 14:50:34 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/test_ADC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
reset_run impl_1 -prev_step
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 15:01:44 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
open_run impl_1
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3486.461 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.2
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 4017.137 ; gain = 0.000
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 4017.137 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4017.137 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
open_run: Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 4109.207 ; gain = 628.227
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/test_ADC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 15:10:14 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 15:10:14 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
current_design rtl_1
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/test_ADC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 15:17:34 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 15:17:34 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/test_ADC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 15:21:10 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 15:21:10 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/test_ADC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
file mkdir D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/simu_ADC.vhd w ]
add_files -fileset sim_1 D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sim_1/new/simu_ADC.vhd
update_compile_order -fileset sim_1
refresh_design
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 4214.984 ; gain = 38.551
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'test_ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:42]
INFO: [Synth 8-3491] module 'registre_DAC' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:14' bound to instance 'U_registre_DAC' of component 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:77]
INFO: [Synth 8-638] synthesizing module 'registre_DAC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-256] done synthesizing module 'registre_DAC' (1#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/registre_DAC.vhd:21]
INFO: [Synth 8-3491] module 'counter_1us' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:33' bound to instance 'U_counter_1us' of component 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:83]
INFO: [Synth 8-638] synthesizing module 'counter_1us' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'counter_1us' (2#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/counter_1us.vhd:39]
INFO: [Synth 8-3491] module 'ADC_global' declared at 'D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:14' bound to instance 'U_ADC_global' of component 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:88]
INFO: [Synth 8-638] synthesizing module 'ADC_global' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-3491] module 'ADC' declared at 'd:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:56' bound to instance 'U_ADC' of component 'ADC' [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:63]
INFO: [Synth 8-638] synthesizing module 'ADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
Parameter INIT_40 bound to: 16'b0000001000010011
Parameter INIT_41 bound to: 16'b0011000110101111
Parameter INIT_42 bound to: 16'b0000010000000000
Parameter INIT_43 bound to: 16'b0000000000000000
Parameter INIT_44 bound to: 16'b0000000000000000
Parameter INIT_45 bound to: 16'b0000000000000000
Parameter INIT_46 bound to: 16'b0000000000000000
Parameter INIT_47 bound to: 16'b0000000000000000
Parameter INIT_48 bound to: 16'b0000000100000000
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000000000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_59 bound to: 16'b0000000000000000
Parameter INIT_5A bound to: 16'b0000000000000000
Parameter INIT_5B bound to: 16'b0000000000000000
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter INIT_5D bound to: 16'b0000000000000000
Parameter INIT_5E bound to: 16'b0000000000000000
Parameter INIT_5F bound to: 16'b0000000000000000
Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0
Parameter IS_DCLK_INVERTED bound to: 1'b0
Parameter SIM_DEVICE bound to: 7SERIES - type: string
Parameter SIM_MONITOR_FILE bound to: design.txt - type: string
INFO: [Synth 8-113] binding component instance 'U0' to cell 'XADC' [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:147]
INFO: [Synth 8-256] done synthesizing module 'ADC' (3#1) [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.vhd:80]
INFO: [Synth 8-256] done synthesizing module 'ADC_global' (4#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/ADC_global.vhd:24]
INFO: [Synth 8-256] done synthesizing module 'test_ADC' (5#1) [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/test_ADC.vhd:42]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4250.949 ; gain = 74.516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4274.816 ; gain = 98.383
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 4274.816 ; gain = 98.383
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 4286.363 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Finished Parsing XDC File [d:/Projet_instrum_MHAH/Projet_instrum_MHAH.gen/sources_1/ip/ADC/ADC.xdc] for cell 'U_ADC_global/U_ADC/U0'
Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Finished Parsing XDC File [D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints
refresh_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 4286.363 ; gain = 109.930
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 15:29:07 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 15:29:07 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/test_ADC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream -jobs 4
[Mon Nov 29 15:36:17 2021] Launched synth_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/synth_1/runme.log
[Mon Nov 29 15:36:17 2021] Launched impl_1...
Run output will be captured here: D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/runme.log
set_property PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a100t_0]
set_property PROGRAM.FILE {D:/Projet_instrum_MHAH/Projet_instrum_MHAH.runs/impl_1/test_ADC.bit} [get_hw_devices xc7a100t_0]
program_hw_devices [get_hw_devices xc7a100t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
close [ open D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd w ]
add_files D:/Projet_instrum_MHAH/Projet_instrum_MHAH.srcs/sources_1/new/filter.vhd
update_compile_order -fileset sources_1
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210292B0F12DA