sdGetClockDivider() implementation conflicts with function description.

[ptrk8]

The function signature below states that 3 - 0x3FF are only possible answers for the divisor; however, in the following function located here, if divisor < 3, divisor is set to 4.

Should divisor be set to 3 or 4 if divisor < 3?

Thanks in advance!

/*-[INTERNAL: sdGetClockDivider]--------------------------------------------}
. Get clock divider for the given requested frequency. This is calculated
. relative to the SD base clock of 41.66667Mhz
. RETURN: 3 - 0x3FF are only possible answers for the divisor
. 10Aug17 LdB
.--------------------------------------------------------------------------*/
static uint32_t sdGetClockDivider(uint32_t freq) {
    uint32_t divisor =
            (41666667 + freq - 1) / freq;                // Pi SD frequency is always 41.66667Mhz on baremetal
    if (divisor > 0x3FF) divisor = 0x3FF;                            // Constrain divisor to max 0x3FF
    if (EMMC_SLOTISR_VER->SDVERSION <
        2) {                            // Any version less than HOST SPECIFICATION 3 (Aka numeric 2)
        uint_fast8_t shiftcount = fls_uint32_t(divisor);            // Only 8 bits and set pwr2 div on Hosts specs 1 & 2
        if (shiftcount > 0) shiftcount--;                            // Note the offset of shift by 1 (look at the spec)
        if (shiftcount > 7) shiftcount = 7;                            // It's only 8 bits maximum on HOST_SPEC_V2
        divisor = ((uint32_t) 1 << shiftcount);                        // Version 1,2 take power 2
    } else if (divisor < 3) divisor = 4;                            // Set minimum divisor limit
    LOG_DEBUG("Divisor = %i, Freq Set = %i\n", (int) divisor, (int) (41666667 / divisor));
    return divisor;                                                    // Return divisor that would be required
}