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Computer Architecture

VERILOG:

( NOTE :Tested in iverilog !!!)

Pipelined 32 bit adder (Recursive,Kogge stone carry look ahead)

Pipelined 32 bit wallace multiplier

Pipelined 64 bit adder (Recursive) (inside 32 bit wallace multiplier directory)

Pipelined 32-bit single precision floating point adder.

Pipelined 32 bit Single precision floating point Multiplier

Logical unit design

Rest in VLSI verilog part below

VLSI

Experiment 1: Magic Tool - Inverter Layout Design Practice -Draw the inverterlayout, extract the circuit persitics and verify its operation.

Experiment 2: Magic Tool - 2-input NOR gate Layout Design Practice - Draw the 2- input NOR gate layout, extract the circuit persitics and verify its operation.

VERILOG :

(IMPORTANT NOTE :Tested in iverilog !!!)

Experiment 3: Design 32 bit Ripple carry Adder using Verilog HDL using bottom-up approach

Experiment 4: Design 8-bit shift Register using Bottom- up approach using Verilog HDL

Experiment 5/6: Design 32-bit Adder -recursive doubling based carry lookahead adder using verilog HDL

Experiment 6/5: Design 32-bit Wallace Multiplier using carry save Adder tree, model the design is verilog HDL

Xilinx

Experiment 7: XILINX Design Flow practice- Modeling 8-bitparity generator circuit on target fpga. Model parity generator circuit in verilog HDL

Experiment 8: XILINX Design Flow practice - 16-bit ArrayMultiplier design usingVerilog HDL.Implementation on target FPGA board. Design parameter estimation.

Experiment 9: XILINX Design Flow -store Imag1 in one block ram and image2 in another block ram ,design image addition design and control logic to read each pixel from each image and perform addition resultant result store in another block ram.

Experiment 10: write a perl or python or any scripting language - combinational logic circuit (biparted graph) as adjacent list and enumerate the all the paths from input to output.

(Used Python)

Design Activity:

1.Write a perl or python or any scripting language based CMOS Compound Gate Design. Input to your code is compound gate based expresssion and output is compound gate stucture. (Not available)

2.16-bit Slansky Adder design using verilog HDL

32,64 bit kogge stone carry look ahead in exp 5,6