From 1e2d3522cf7df7020aa9d12ad3d11f7b03187355 Mon Sep 17 00:00:00 2001 From: Marcin Hajder Date: Tue, 11 Jul 2023 17:48:41 +0200 Subject: [PATCH] Added cl_khr_fp16 extension support for test_op_vector_insert from spirv_new (#1766) * Added cl_khr_fp16 extension support for test_op_vector_insert from spirv_new, work in progress. * Added cl_khr_fp16 extension support for test_op_vector_insert from spirv_new (issue #142) --- .../spirv_asm/vector_half8_insert.spvasm32 | 43 +++++++++++++++ .../spirv_asm/vector_half8_insert.spvasm64 | 48 +++++++++++++++++ .../spirv_new/test_op_vector_insert.cpp | 52 ++++++++++++------- test_conformance/spirv_new/types.hpp | 1 + 4 files changed, 125 insertions(+), 19 deletions(-) create mode 100644 test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm32 create mode 100644 test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm64 diff --git a/test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm32 b/test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm32 new file mode 100644 index 0000000000..278129388c --- /dev/null +++ b/test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm32 @@ -0,0 +1,43 @@ +; SPIR-V +; Version: 1.0 +; Generator: Khronos SPIR-V Tools Assembler; 0 +; Bound: 23 +; Schema: 0 + OpCapability Addresses + OpCapability Linkage + OpCapability Kernel + OpCapability Vector16 + OpCapability Float16 + OpMemoryModel Physical32 OpenCL + OpEntryPoint Kernel %1 "vector_half8_insert" %gl_GlobalInvocationID + OpName %in "in" + OpDecorate %gl_GlobalInvocationID BuiltIn GlobalInvocationId + OpDecorate %gl_GlobalInvocationID Constant + OpDecorate %in FuncParamAttr NoCapture + OpDecorate %4 FuncParamAttr NoCapture + OpDecorate %gl_GlobalInvocationID LinkageAttributes "__spirv_GlobalInvocationId" Import + %uint = OpTypeInt 32 0 + %v3uint = OpTypeVector %uint 3 +%_ptr_Input_v3uint = OpTypePointer Input %v3uint + %void = OpTypeVoid + %half = OpTypeFloat 16 + %v8half = OpTypeVector %half 8 +%_ptr_CrossWorkgroup_half = OpTypePointer CrossWorkgroup %half +%_ptr_CrossWorkgroup_v8half = OpTypePointer CrossWorkgroup %v8half + %13 = OpTypeFunction %void %_ptr_CrossWorkgroup_half %_ptr_CrossWorkgroup_v8half %uint +%gl_GlobalInvocationID = OpVariable %_ptr_Input_v3uint Input + %1 = OpFunction %void None %13 + %in = OpFunctionParameter %_ptr_CrossWorkgroup_half + %4 = OpFunctionParameter %_ptr_CrossWorkgroup_v8half + %14 = OpFunctionParameter %uint + %15 = OpLabel + %16 = OpLoad %v3uint %gl_GlobalInvocationID Aligned 0 + %17 = OpCompositeExtract %uint %16 0 + %18 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_half %in %17 + %19 = OpLoad %half %18 + %20 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_v8half %4 %17 + %21 = OpLoad %v8half %20 + %22 = OpVectorInsertDynamic %v8half %21 %19 %14 + OpStore %20 %22 + OpReturn + OpFunctionEnd diff --git a/test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm64 b/test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm64 new file mode 100644 index 0000000000..f140fc2533 --- /dev/null +++ b/test_conformance/spirv_new/spirv_asm/vector_half8_insert.spvasm64 @@ -0,0 +1,48 @@ +; SPIR-V +; Version: 1.0 +; Generator: Khronos SPIR-V Tools Assembler; 0 +; Bound: 27 +; Schema: 0 + OpCapability Addresses + OpCapability Linkage + OpCapability Kernel + OpCapability Int64 + OpCapability Vector16 + OpCapability Float16 + OpMemoryModel Physical64 OpenCL + OpEntryPoint Kernel %1 "vector_half8_insert" %gl_GlobalInvocationID + OpName %in "in" + OpDecorate %gl_GlobalInvocationID BuiltIn GlobalInvocationId + OpDecorate %gl_GlobalInvocationID Constant + OpDecorate %in FuncParamAttr NoCapture + OpDecorate %4 FuncParamAttr NoCapture + OpDecorate %gl_GlobalInvocationID LinkageAttributes "__spirv_GlobalInvocationId" Import + %ulong = OpTypeInt 64 0 + %v3ulong = OpTypeVector %ulong 3 +%_ptr_Input_v3ulong = OpTypePointer Input %v3ulong + %ulong_32 = OpConstant %ulong 32 + %uint = OpTypeInt 32 0 + %void = OpTypeVoid + %half = OpTypeFloat 16 + %v8half = OpTypeVector %half 8 +%_ptr_CrossWorkgroup_half = OpTypePointer CrossWorkgroup %half +%_ptr_CrossWorkgroup_v8half = OpTypePointer CrossWorkgroup %v8half + %15 = OpTypeFunction %void %_ptr_CrossWorkgroup_half %_ptr_CrossWorkgroup_v8half %uint +%gl_GlobalInvocationID = OpVariable %_ptr_Input_v3ulong Input + %1 = OpFunction %void None %15 + %in = OpFunctionParameter %_ptr_CrossWorkgroup_half + %4 = OpFunctionParameter %_ptr_CrossWorkgroup_v8half + %16 = OpFunctionParameter %uint + %17 = OpLabel + %18 = OpLoad %v3ulong %gl_GlobalInvocationID Aligned 0 + %19 = OpCompositeExtract %ulong %18 0 + %20 = OpShiftLeftLogical %ulong %19 %ulong_32 + %21 = OpShiftRightArithmetic %ulong %20 %ulong_32 + %22 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_half %in %21 + %23 = OpLoad %half %22 + %24 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_v8half %4 %21 + %25 = OpLoad %v8half %24 + %26 = OpVectorInsertDynamic %v8half %25 %23 %16 + OpStore %24 %26 + OpReturn + OpFunctionEnd diff --git a/test_conformance/spirv_new/test_op_vector_insert.cpp b/test_conformance/spirv_new/test_op_vector_insert.cpp index 0749c14abb..62fc78cb51 100644 --- a/test_conformance/spirv_new/test_op_vector_insert.cpp +++ b/test_conformance/spirv_new/test_op_vector_insert.cpp @@ -25,6 +25,17 @@ int test_insert(cl_device_id deviceID, cl_context context, return 0; } } + + if (std::string(name).find("half") != std::string::npos) + { + if (!is_extension_available(deviceID, "cl_khr_fp16")) + { + log_info( + "Extension cl_khr_fp16 not supported; skipping half tests.\n"); + return 0; + } + } + cl_int err = CL_SUCCESS; clProgramWrapper prog; err = get_program_with_il(prog, deviceID, context, name); @@ -94,27 +105,30 @@ int test_insert(cl_device_id deviceID, cl_context context, return 0; } -#define TEST_VECTOR_INSERT(TYPE, N) \ - TEST_SPIRV_FUNC(op_vector_##TYPE##N##_insert) \ - { \ - typedef cl_##TYPE##N Tv; \ - typedef cl_##TYPE Ts; \ - const int num = 1 << 20; \ - std::vector in(num); \ - const char *name = "vector_" #TYPE #N "_insert"; \ - \ - RandomSeed seed(gRandomSeed); \ - \ - for (int i = 0; i < num; i++) { \ - in[i] = genrand(seed); \ - } \ - \ - return test_insert(deviceID, \ - context, queue, \ - name, \ - in, N); \ +#define TEST_VECTOR_INSERT(TYPE, N) \ + TEST_SPIRV_FUNC(op_vector_##TYPE##N##_insert) \ + { \ + if (sizeof(cl_##TYPE) == 2) \ + { \ + PASSIVE_REQUIRE_FP16_SUPPORT(deviceID); \ + } \ + typedef cl_##TYPE##N Tv; \ + typedef cl_##TYPE Ts; \ + const int num = 1 << 20; \ + std::vector in(num); \ + const char *name = "vector_" #TYPE #N "_insert"; \ + \ + RandomSeed seed(gRandomSeed); \ + \ + for (int i = 0; i < num; i++) \ + { \ + in[i] = genrand(seed); \ + } \ + \ + return test_insert(deviceID, context, queue, name, in, N); \ } +TEST_VECTOR_INSERT(half, 8) TEST_VECTOR_INSERT(int, 4) TEST_VECTOR_INSERT(float, 4) TEST_VECTOR_INSERT(long, 2) diff --git a/test_conformance/spirv_new/types.hpp b/test_conformance/spirv_new/types.hpp index 939e6fa8c0..728b244558 100644 --- a/test_conformance/spirv_new/types.hpp +++ b/test_conformance/spirv_new/types.hpp @@ -113,6 +113,7 @@ GENRAND_REAL_FUNC(cl_double, 2) GENRAND_REAL_FUNC(cl_double, 4) GENRAND_REAL_FUNC(cl_half, 2) GENRAND_REAL_FUNC(cl_half, 4) +GENRAND_REAL_FUNC(cl_half, 8) template<> inline cl_half genrandReal(RandomSeed &seed) {