Bulk data from PC to FPGA with slow user logic

[quangdaovu]

Hi,

Firstly, please pardon me for my bad English. Secondly, also pardon me for my ironic questions (since I don't have enough time to carefully read and understand everything about riffa).

I'm now integrating my logic into RIFFA by modifing chnl_tester.v. The requirement is send 1 bulk data through PCI (1K of packet, each packet is 48 bytes) and then wait for its bulk responses. Normally my logic will process one packet in around 0.5ms (which is pretty slow in compared with RIFFA's performance). Since I don't really understand about how RIFFA works, is it ok to read one packet, wait for my logic to finish processing it, and then read another packet? Is there any chance of losing data? Do I have to read all the bulk data at once?

Thanks a lot for your help.
Your sincerely,
Quang Dao

[Johnhave]

Hi,
I have done similar question. That is, send and receive piece by piece. Each piece has 128 bits. When PC call the 'fpga_recv', system would wait and not receive until the signal 'CHNL_TX_DATA_REN' as well as 'CHNL_TX_DATA_VALID' is high. Therefore, you just need to manage the two signals with your ip cores.
Best wishes